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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-24 13:30:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-24 13:30:41 -0400
commit94e0fb086fc5663c38bbc0fe86d698be8314f82f (patch)
tree1c3be6c71ec3511aa2a4eb6dfa25f35677464ebb /drivers/gpu/drm/i915/i915_gem.c
parentb7f21bb2e23b4fec16b448a34889f467465be659 (diff)
parentc715089f49844260f1eeae8e3b55af9468ba1325 (diff)
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (57 commits) drm/i915: Handle ERESTARTSYS during page fault drm/i915: Warn before mmaping a purgeable buffer. drm/i915: Track purged state. drm/i915: Remove eviction debug spam drm/i915: Immediately discard any backing storage for uneeded objects drm/i915: Do not mis-classify clean objects as purgeable drm/i915: Whitespace correction for madv drm/i915: BUG_ON page refleak during unbind drm/i915: Search harder for a reusable object drm/i915: Clean up evict from list. drm/i915: Add tracepoints drm/i915: framebuffer compression for GM45+ drm/i915: split display functions by chip type drm/i915: Skip the sanity checks if the current relocation is valid drm/i915: Check that the relocation points to within the target drm/i915: correct FBC update when pipe base update occurs drm/i915: blacklist Acer AspireOne lid status ACPI: make ACPI button funcs no-ops if not built in drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks drm/i915: intel_display.c handle latency variable efficiently ... Fix up trivial conflicts in drivers/gpu/drm/i915/{i915_dma.c|i915_drv.h}
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c876
1 files changed, 652 insertions, 224 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c67317112f4..40727d4c291 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -29,6 +29,7 @@
29#include "drm.h" 29#include "drm.h"
30#include "i915_drm.h" 30#include "i915_drm.h"
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "i915_trace.h"
32#include "intel_drv.h" 33#include "intel_drv.h"
33#include <linux/swap.h> 34#include <linux/swap.h>
34#include <linux/pci.h> 35#include <linux/pci.h>
@@ -48,11 +49,15 @@ static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, 49static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment); 50 unsigned alignment);
50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); 51static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51static int i915_gem_evict_something(struct drm_device *dev); 52static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
52static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args, 55 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv); 56 struct drm_file *file_priv);
55 57
58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
56int i915_gem_do_init(struct drm_device *dev, unsigned long start, 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
57 unsigned long end) 62 unsigned long end)
58{ 63{
@@ -316,6 +321,45 @@ fail_unlock:
316 return ret; 321 return ret;
317} 322}
318 323
324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
319/** 363/**
320 * This is the fallback shmem pread path, which allocates temporary storage 364 * This is the fallback shmem pread path, which allocates temporary storage
321 * in kernel space to copy_to_user into outside of the struct_mutex, so we 365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
@@ -367,8 +411,8 @@ i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
367 411
368 mutex_lock(&dev->struct_mutex); 412 mutex_lock(&dev->struct_mutex);
369 413
370 ret = i915_gem_object_get_pages(obj); 414 ret = i915_gem_object_get_pages_or_evict(obj);
371 if (ret != 0) 415 if (ret)
372 goto fail_unlock; 416 goto fail_unlock;
373 417
374 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, 418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
@@ -842,8 +886,8 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
842 886
843 mutex_lock(&dev->struct_mutex); 887 mutex_lock(&dev->struct_mutex);
844 888
845 ret = i915_gem_object_get_pages(obj); 889 ret = i915_gem_object_get_pages_or_evict(obj);
846 if (ret != 0) 890 if (ret)
847 goto fail_unlock; 891 goto fail_unlock;
848 892
849 ret = i915_gem_object_set_to_cpu_domain(obj, 1); 893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
@@ -1155,28 +1199,22 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1155 /* Now bind it into the GTT if needed */ 1199 /* Now bind it into the GTT if needed */
1156 mutex_lock(&dev->struct_mutex); 1200 mutex_lock(&dev->struct_mutex);
1157 if (!obj_priv->gtt_space) { 1201 if (!obj_priv->gtt_space) {
1158 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); 1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1159 if (ret) { 1203 if (ret)
1160 mutex_unlock(&dev->struct_mutex); 1204 goto unlock;
1161 return VM_FAULT_SIGBUS;
1162 }
1163
1164 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1165 if (ret) {
1166 mutex_unlock(&dev->struct_mutex);
1167 return VM_FAULT_SIGBUS;
1168 }
1169 1205
1170 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); 1206 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1207
1208 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1209 if (ret)
1210 goto unlock;
1171 } 1211 }
1172 1212
1173 /* Need a new fence register? */ 1213 /* Need a new fence register? */
1174 if (obj_priv->tiling_mode != I915_TILING_NONE) { 1214 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1175 ret = i915_gem_object_get_fence_reg(obj); 1215 ret = i915_gem_object_get_fence_reg(obj);
1176 if (ret) { 1216 if (ret)
1177 mutex_unlock(&dev->struct_mutex); 1217 goto unlock;
1178 return VM_FAULT_SIGBUS;
1179 }
1180 } 1218 }
1181 1219
1182 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + 1220 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
@@ -1184,18 +1222,18 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1184 1222
1185 /* Finally, remap it using the new GTT offset */ 1223 /* Finally, remap it using the new GTT offset */
1186 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); 1224 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1187 1225unlock:
1188 mutex_unlock(&dev->struct_mutex); 1226 mutex_unlock(&dev->struct_mutex);
1189 1227
1190 switch (ret) { 1228 switch (ret) {
1229 case 0:
1230 case -ERESTARTSYS:
1231 return VM_FAULT_NOPAGE;
1191 case -ENOMEM: 1232 case -ENOMEM:
1192 case -EAGAIN: 1233 case -EAGAIN:
1193 return VM_FAULT_OOM; 1234 return VM_FAULT_OOM;
1194 case -EFAULT:
1195 case -EINVAL:
1196 return VM_FAULT_SIGBUS;
1197 default: 1235 default:
1198 return VM_FAULT_NOPAGE; 1236 return VM_FAULT_SIGBUS;
1199 } 1237 }
1200} 1238}
1201 1239
@@ -1388,6 +1426,14 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1388 1426
1389 obj_priv = obj->driver_private; 1427 obj_priv = obj->driver_private;
1390 1428
1429 if (obj_priv->madv != I915_MADV_WILLNEED) {
1430 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1431 drm_gem_object_unreference(obj);
1432 mutex_unlock(&dev->struct_mutex);
1433 return -EINVAL;
1434 }
1435
1436
1391 if (!obj_priv->mmap_offset) { 1437 if (!obj_priv->mmap_offset) {
1392 ret = i915_gem_create_mmap_offset(obj); 1438 ret = i915_gem_create_mmap_offset(obj);
1393 if (ret) { 1439 if (ret) {
@@ -1399,22 +1445,12 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1399 1445
1400 args->offset = obj_priv->mmap_offset; 1446 args->offset = obj_priv->mmap_offset;
1401 1447
1402 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1403
1404 /* Make sure the alignment is correct for fence regs etc */
1405 if (obj_priv->agp_mem &&
1406 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1407 drm_gem_object_unreference(obj);
1408 mutex_unlock(&dev->struct_mutex);
1409 return -EINVAL;
1410 }
1411
1412 /* 1448 /*
1413 * Pull it into the GTT so that we have a page list (makes the 1449 * Pull it into the GTT so that we have a page list (makes the
1414 * initial fault faster and any subsequent flushing possible). 1450 * initial fault faster and any subsequent flushing possible).
1415 */ 1451 */
1416 if (!obj_priv->agp_mem) { 1452 if (!obj_priv->agp_mem) {
1417 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); 1453 ret = i915_gem_object_bind_to_gtt(obj, 0);
1418 if (ret) { 1454 if (ret) {
1419 drm_gem_object_unreference(obj); 1455 drm_gem_object_unreference(obj);
1420 mutex_unlock(&dev->struct_mutex); 1456 mutex_unlock(&dev->struct_mutex);
@@ -1437,6 +1473,7 @@ i915_gem_object_put_pages(struct drm_gem_object *obj)
1437 int i; 1473 int i;
1438 1474
1439 BUG_ON(obj_priv->pages_refcount == 0); 1475 BUG_ON(obj_priv->pages_refcount == 0);
1476 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1440 1477
1441 if (--obj_priv->pages_refcount != 0) 1478 if (--obj_priv->pages_refcount != 0)
1442 return; 1479 return;
@@ -1444,13 +1481,21 @@ i915_gem_object_put_pages(struct drm_gem_object *obj)
1444 if (obj_priv->tiling_mode != I915_TILING_NONE) 1481 if (obj_priv->tiling_mode != I915_TILING_NONE)
1445 i915_gem_object_save_bit_17_swizzle(obj); 1482 i915_gem_object_save_bit_17_swizzle(obj);
1446 1483
1447 for (i = 0; i < page_count; i++) 1484 if (obj_priv->madv == I915_MADV_DONTNEED)
1448 if (obj_priv->pages[i] != NULL) { 1485 obj_priv->dirty = 0;
1449 if (obj_priv->dirty) 1486
1450 set_page_dirty(obj_priv->pages[i]); 1487 for (i = 0; i < page_count; i++) {
1488 if (obj_priv->pages[i] == NULL)
1489 break;
1490
1491 if (obj_priv->dirty)
1492 set_page_dirty(obj_priv->pages[i]);
1493
1494 if (obj_priv->madv == I915_MADV_WILLNEED)
1451 mark_page_accessed(obj_priv->pages[i]); 1495 mark_page_accessed(obj_priv->pages[i]);
1452 page_cache_release(obj_priv->pages[i]); 1496
1453 } 1497 page_cache_release(obj_priv->pages[i]);
1498 }
1454 obj_priv->dirty = 0; 1499 obj_priv->dirty = 0;
1455 1500
1456 drm_free_large(obj_priv->pages); 1501 drm_free_large(obj_priv->pages);
@@ -1489,6 +1534,26 @@ i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1489 obj_priv->last_rendering_seqno = 0; 1534 obj_priv->last_rendering_seqno = 0;
1490} 1535}
1491 1536
1537/* Immediately discard the backing storage */
1538static void
1539i915_gem_object_truncate(struct drm_gem_object *obj)
1540{
1541 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1542 struct inode *inode;
1543
1544 inode = obj->filp->f_path.dentry->d_inode;
1545 if (inode->i_op->truncate)
1546 inode->i_op->truncate (inode);
1547
1548 obj_priv->madv = __I915_MADV_PURGED;
1549}
1550
1551static inline int
1552i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1553{
1554 return obj_priv->madv == I915_MADV_DONTNEED;
1555}
1556
1492static void 1557static void
1493i915_gem_object_move_to_inactive(struct drm_gem_object *obj) 1558i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1494{ 1559{
@@ -1577,15 +1642,24 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1577 1642
1578 if ((obj->write_domain & flush_domains) == 1643 if ((obj->write_domain & flush_domains) ==
1579 obj->write_domain) { 1644 obj->write_domain) {
1645 uint32_t old_write_domain = obj->write_domain;
1646
1580 obj->write_domain = 0; 1647 obj->write_domain = 0;
1581 i915_gem_object_move_to_active(obj, seqno); 1648 i915_gem_object_move_to_active(obj, seqno);
1649
1650 trace_i915_gem_object_change_domain(obj,
1651 obj->read_domains,
1652 old_write_domain);
1582 } 1653 }
1583 } 1654 }
1584 1655
1585 } 1656 }
1586 1657
1587 if (was_empty && !dev_priv->mm.suspended) 1658 if (!dev_priv->mm.suspended) {
1588 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); 1659 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1660 if (was_empty)
1661 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1662 }
1589 return seqno; 1663 return seqno;
1590} 1664}
1591 1665
@@ -1623,6 +1697,8 @@ i915_gem_retire_request(struct drm_device *dev,
1623{ 1697{
1624 drm_i915_private_t *dev_priv = dev->dev_private; 1698 drm_i915_private_t *dev_priv = dev->dev_private;
1625 1699
1700 trace_i915_gem_request_retire(dev, request->seqno);
1701
1626 /* Move any buffers on the active list that are no longer referenced 1702 /* Move any buffers on the active list that are no longer referenced
1627 * by the ringbuffer to the flushing/inactive lists as appropriate. 1703 * by the ringbuffer to the flushing/inactive lists as appropriate.
1628 */ 1704 */
@@ -1671,7 +1747,7 @@ out:
1671/** 1747/**
1672 * Returns true if seq1 is later than seq2. 1748 * Returns true if seq1 is later than seq2.
1673 */ 1749 */
1674static int 1750bool
1675i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1751i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1676{ 1752{
1677 return (int32_t)(seq1 - seq2) >= 0; 1753 return (int32_t)(seq1 - seq2) >= 0;
@@ -1709,7 +1785,7 @@ i915_gem_retire_requests(struct drm_device *dev)
1709 retiring_seqno = request->seqno; 1785 retiring_seqno = request->seqno;
1710 1786
1711 if (i915_seqno_passed(seqno, retiring_seqno) || 1787 if (i915_seqno_passed(seqno, retiring_seqno) ||
1712 dev_priv->mm.wedged) { 1788 atomic_read(&dev_priv->mm.wedged)) {
1713 i915_gem_retire_request(dev, request); 1789 i915_gem_retire_request(dev, request);
1714 1790
1715 list_del(&request->list); 1791 list_del(&request->list);
@@ -1751,6 +1827,9 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
1751 1827
1752 BUG_ON(seqno == 0); 1828 BUG_ON(seqno == 0);
1753 1829
1830 if (atomic_read(&dev_priv->mm.wedged))
1831 return -EIO;
1832
1754 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { 1833 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1755 if (IS_IGDNG(dev)) 1834 if (IS_IGDNG(dev))
1756 ier = I915_READ(DEIER) | I915_READ(GTIER); 1835 ier = I915_READ(DEIER) | I915_READ(GTIER);
@@ -1763,16 +1842,20 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
1763 i915_driver_irq_postinstall(dev); 1842 i915_driver_irq_postinstall(dev);
1764 } 1843 }
1765 1844
1845 trace_i915_gem_request_wait_begin(dev, seqno);
1846
1766 dev_priv->mm.waiting_gem_seqno = seqno; 1847 dev_priv->mm.waiting_gem_seqno = seqno;
1767 i915_user_irq_get(dev); 1848 i915_user_irq_get(dev);
1768 ret = wait_event_interruptible(dev_priv->irq_queue, 1849 ret = wait_event_interruptible(dev_priv->irq_queue,
1769 i915_seqno_passed(i915_get_gem_seqno(dev), 1850 i915_seqno_passed(i915_get_gem_seqno(dev),
1770 seqno) || 1851 seqno) ||
1771 dev_priv->mm.wedged); 1852 atomic_read(&dev_priv->mm.wedged));
1772 i915_user_irq_put(dev); 1853 i915_user_irq_put(dev);
1773 dev_priv->mm.waiting_gem_seqno = 0; 1854 dev_priv->mm.waiting_gem_seqno = 0;
1855
1856 trace_i915_gem_request_wait_end(dev, seqno);
1774 } 1857 }
1775 if (dev_priv->mm.wedged) 1858 if (atomic_read(&dev_priv->mm.wedged))
1776 ret = -EIO; 1859 ret = -EIO;
1777 1860
1778 if (ret && ret != -ERESTARTSYS) 1861 if (ret && ret != -ERESTARTSYS)
@@ -1803,6 +1886,8 @@ i915_gem_flush(struct drm_device *dev,
1803 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, 1886 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1804 invalidate_domains, flush_domains); 1887 invalidate_domains, flush_domains);
1805#endif 1888#endif
1889 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1890 invalidate_domains, flush_domains);
1806 1891
1807 if (flush_domains & I915_GEM_DOMAIN_CPU) 1892 if (flush_domains & I915_GEM_DOMAIN_CPU)
1808 drm_agp_chipset_flush(dev); 1893 drm_agp_chipset_flush(dev);
@@ -1915,6 +2000,12 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
1915 return -EINVAL; 2000 return -EINVAL;
1916 } 2001 }
1917 2002
2003 /* blow away mappings if mapped through GTT */
2004 i915_gem_release_mmap(obj);
2005
2006 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2007 i915_gem_clear_fence_reg(obj);
2008
1918 /* Move the object to the CPU domain to ensure that 2009 /* Move the object to the CPU domain to ensure that
1919 * any possible CPU writes while it's not in the GTT 2010 * any possible CPU writes while it's not in the GTT
1920 * are flushed when we go to remap it. This will 2011 * are flushed when we go to remap it. This will
@@ -1928,21 +2019,16 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
1928 return ret; 2019 return ret;
1929 } 2020 }
1930 2021
2022 BUG_ON(obj_priv->active);
2023
1931 if (obj_priv->agp_mem != NULL) { 2024 if (obj_priv->agp_mem != NULL) {
1932 drm_unbind_agp(obj_priv->agp_mem); 2025 drm_unbind_agp(obj_priv->agp_mem);
1933 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); 2026 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1934 obj_priv->agp_mem = NULL; 2027 obj_priv->agp_mem = NULL;
1935 } 2028 }
1936 2029
1937 BUG_ON(obj_priv->active);
1938
1939 /* blow away mappings if mapped through GTT */
1940 i915_gem_release_mmap(obj);
1941
1942 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1943 i915_gem_clear_fence_reg(obj);
1944
1945 i915_gem_object_put_pages(obj); 2030 i915_gem_object_put_pages(obj);
2031 BUG_ON(obj_priv->pages_refcount);
1946 2032
1947 if (obj_priv->gtt_space) { 2033 if (obj_priv->gtt_space) {
1948 atomic_dec(&dev->gtt_count); 2034 atomic_dec(&dev->gtt_count);
@@ -1956,40 +2042,113 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
1956 if (!list_empty(&obj_priv->list)) 2042 if (!list_empty(&obj_priv->list))
1957 list_del_init(&obj_priv->list); 2043 list_del_init(&obj_priv->list);
1958 2044
2045 if (i915_gem_object_is_purgeable(obj_priv))
2046 i915_gem_object_truncate(obj);
2047
2048 trace_i915_gem_object_unbind(obj);
2049
1959 return 0; 2050 return 0;
1960} 2051}
1961 2052
2053static struct drm_gem_object *
2054i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2055{
2056 drm_i915_private_t *dev_priv = dev->dev_private;
2057 struct drm_i915_gem_object *obj_priv;
2058 struct drm_gem_object *best = NULL;
2059 struct drm_gem_object *first = NULL;
2060
2061 /* Try to find the smallest clean object */
2062 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2063 struct drm_gem_object *obj = obj_priv->obj;
2064 if (obj->size >= min_size) {
2065 if ((!obj_priv->dirty ||
2066 i915_gem_object_is_purgeable(obj_priv)) &&
2067 (!best || obj->size < best->size)) {
2068 best = obj;
2069 if (best->size == min_size)
2070 return best;
2071 }
2072 if (!first)
2073 first = obj;
2074 }
2075 }
2076
2077 return best ? best : first;
2078}
2079
1962static int 2080static int
1963i915_gem_evict_something(struct drm_device *dev) 2081i915_gem_evict_everything(struct drm_device *dev)
2082{
2083 drm_i915_private_t *dev_priv = dev->dev_private;
2084 uint32_t seqno;
2085 int ret;
2086 bool lists_empty;
2087
2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
2091 list_empty(&dev_priv->mm.active_list));
2092 spin_unlock(&dev_priv->mm.active_list_lock);
2093
2094 if (lists_empty)
2095 return -ENOSPC;
2096
2097 /* Flush everything (on to the inactive lists) and evict */
2098 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2099 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2100 if (seqno == 0)
2101 return -ENOMEM;
2102
2103 ret = i915_wait_request(dev, seqno);
2104 if (ret)
2105 return ret;
2106
2107 ret = i915_gem_evict_from_inactive_list(dev);
2108 if (ret)
2109 return ret;
2110
2111 spin_lock(&dev_priv->mm.active_list_lock);
2112 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2113 list_empty(&dev_priv->mm.flushing_list) &&
2114 list_empty(&dev_priv->mm.active_list));
2115 spin_unlock(&dev_priv->mm.active_list_lock);
2116 BUG_ON(!lists_empty);
2117
2118 return 0;
2119}
2120
2121static int
2122i915_gem_evict_something(struct drm_device *dev, int min_size)
1964{ 2123{
1965 drm_i915_private_t *dev_priv = dev->dev_private; 2124 drm_i915_private_t *dev_priv = dev->dev_private;
1966 struct drm_gem_object *obj; 2125 struct drm_gem_object *obj;
1967 struct drm_i915_gem_object *obj_priv; 2126 int ret;
1968 int ret = 0;
1969 2127
1970 for (;;) { 2128 for (;;) {
2129 i915_gem_retire_requests(dev);
2130
1971 /* If there's an inactive buffer available now, grab it 2131 /* If there's an inactive buffer available now, grab it
1972 * and be done. 2132 * and be done.
1973 */ 2133 */
1974 if (!list_empty(&dev_priv->mm.inactive_list)) { 2134 obj = i915_gem_find_inactive_object(dev, min_size);
1975 obj_priv = list_first_entry(&dev_priv->mm.inactive_list, 2135 if (obj) {
1976 struct drm_i915_gem_object, 2136 struct drm_i915_gem_object *obj_priv;
1977 list); 2137
1978 obj = obj_priv->obj;
1979 BUG_ON(obj_priv->pin_count != 0);
1980#if WATCH_LRU 2138#if WATCH_LRU
1981 DRM_INFO("%s: evicting %p\n", __func__, obj); 2139 DRM_INFO("%s: evicting %p\n", __func__, obj);
1982#endif 2140#endif
2141 obj_priv = obj->driver_private;
2142 BUG_ON(obj_priv->pin_count != 0);
1983 BUG_ON(obj_priv->active); 2143 BUG_ON(obj_priv->active);
1984 2144
1985 /* Wait on the rendering and unbind the buffer. */ 2145 /* Wait on the rendering and unbind the buffer. */
1986 ret = i915_gem_object_unbind(obj); 2146 return i915_gem_object_unbind(obj);
1987 break;
1988 } 2147 }
1989 2148
1990 /* If we didn't get anything, but the ring is still processing 2149 /* If we didn't get anything, but the ring is still processing
1991 * things, wait for one of those things to finish and hopefully 2150 * things, wait for the next to finish and hopefully leave us
1992 * leave us a buffer to evict. 2151 * a buffer to evict.
1993 */ 2152 */
1994 if (!list_empty(&dev_priv->mm.request_list)) { 2153 if (!list_empty(&dev_priv->mm.request_list)) {
1995 struct drm_i915_gem_request *request; 2154 struct drm_i915_gem_request *request;
@@ -2000,16 +2159,9 @@ i915_gem_evict_something(struct drm_device *dev)
2000 2159
2001 ret = i915_wait_request(dev, request->seqno); 2160 ret = i915_wait_request(dev, request->seqno);
2002 if (ret) 2161 if (ret)
2003 break; 2162 return ret;
2004 2163
2005 /* if waiting caused an object to become inactive, 2164 continue;
2006 * then loop around and wait for it. Otherwise, we
2007 * assume that waiting freed and unbound something,
2008 * so there should now be some space in the GTT
2009 */
2010 if (!list_empty(&dev_priv->mm.inactive_list))
2011 continue;
2012 break;
2013 } 2165 }
2014 2166
2015 /* If we didn't have anything on the request list but there 2167 /* If we didn't have anything on the request list but there
@@ -2018,46 +2170,44 @@ i915_gem_evict_something(struct drm_device *dev)
2018 * will get moved to inactive. 2170 * will get moved to inactive.
2019 */ 2171 */
2020 if (!list_empty(&dev_priv->mm.flushing_list)) { 2172 if (!list_empty(&dev_priv->mm.flushing_list)) {
2021 obj_priv = list_first_entry(&dev_priv->mm.flushing_list, 2173 struct drm_i915_gem_object *obj_priv;
2022 struct drm_i915_gem_object,
2023 list);
2024 obj = obj_priv->obj;
2025 2174
2026 i915_gem_flush(dev, 2175 /* Find an object that we can immediately reuse */
2027 obj->write_domain, 2176 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2028 obj->write_domain); 2177 obj = obj_priv->obj;
2029 i915_add_request(dev, NULL, obj->write_domain); 2178 if (obj->size >= min_size)
2179 break;
2030 2180
2031 obj = NULL; 2181 obj = NULL;
2032 continue; 2182 }
2033 }
2034 2183
2035 DRM_ERROR("inactive empty %d request empty %d " 2184 if (obj != NULL) {
2036 "flushing empty %d\n", 2185 uint32_t seqno;
2037 list_empty(&dev_priv->mm.inactive_list),
2038 list_empty(&dev_priv->mm.request_list),
2039 list_empty(&dev_priv->mm.flushing_list));
2040 /* If we didn't do any of the above, there's nothing to be done
2041 * and we just can't fit it in.
2042 */
2043 return -ENOSPC;
2044 }
2045 return ret;
2046}
2047 2186
2048static int 2187 i915_gem_flush(dev,
2049i915_gem_evict_everything(struct drm_device *dev) 2188 obj->write_domain,
2050{ 2189 obj->write_domain);
2051 int ret; 2190 seqno = i915_add_request(dev, NULL, obj->write_domain);
2191 if (seqno == 0)
2192 return -ENOMEM;
2052 2193
2053 for (;;) { 2194 ret = i915_wait_request(dev, seqno);
2054 ret = i915_gem_evict_something(dev); 2195 if (ret)
2055 if (ret != 0) 2196 return ret;
2056 break; 2197
2198 continue;
2199 }
2200 }
2201
2202 /* If we didn't do any of the above, there's no single buffer
2203 * large enough to swap out for the new one, so just evict
2204 * everything and start again. (This should be rare.)
2205 */
2206 if (!list_empty (&dev_priv->mm.inactive_list))
2207 return i915_gem_evict_from_inactive_list(dev);
2208 else
2209 return i915_gem_evict_everything(dev);
2057 } 2210 }
2058 if (ret == -ENOSPC)
2059 return 0;
2060 return ret;
2061} 2211}
2062 2212
2063int 2213int
@@ -2080,7 +2230,6 @@ i915_gem_object_get_pages(struct drm_gem_object *obj)
2080 BUG_ON(obj_priv->pages != NULL); 2230 BUG_ON(obj_priv->pages != NULL);
2081 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); 2231 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2082 if (obj_priv->pages == NULL) { 2232 if (obj_priv->pages == NULL) {
2083 DRM_ERROR("Faled to allocate page list\n");
2084 obj_priv->pages_refcount--; 2233 obj_priv->pages_refcount--;
2085 return -ENOMEM; 2234 return -ENOMEM;
2086 } 2235 }
@@ -2091,7 +2240,6 @@ i915_gem_object_get_pages(struct drm_gem_object *obj)
2091 page = read_mapping_page(mapping, i, NULL); 2240 page = read_mapping_page(mapping, i, NULL);
2092 if (IS_ERR(page)) { 2241 if (IS_ERR(page)) {
2093 ret = PTR_ERR(page); 2242 ret = PTR_ERR(page);
2094 DRM_ERROR("read_mapping_page failed: %d\n", ret);
2095 i915_gem_object_put_pages(obj); 2243 i915_gem_object_put_pages(obj);
2096 return ret; 2244 return ret;
2097 } 2245 }
@@ -2328,6 +2476,8 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2328 else 2476 else
2329 i830_write_fence_reg(reg); 2477 i830_write_fence_reg(reg);
2330 2478
2479 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2480
2331 return 0; 2481 return 0;
2332} 2482}
2333 2483
@@ -2410,10 +2560,17 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2410 drm_i915_private_t *dev_priv = dev->dev_private; 2560 drm_i915_private_t *dev_priv = dev->dev_private;
2411 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2561 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2412 struct drm_mm_node *free_space; 2562 struct drm_mm_node *free_space;
2413 int page_count, ret; 2563 bool retry_alloc = false;
2564 int ret;
2414 2565
2415 if (dev_priv->mm.suspended) 2566 if (dev_priv->mm.suspended)
2416 return -EBUSY; 2567 return -EBUSY;
2568
2569 if (obj_priv->madv != I915_MADV_WILLNEED) {
2570 DRM_ERROR("Attempting to bind a purgeable object\n");
2571 return -EINVAL;
2572 }
2573
2417 if (alignment == 0) 2574 if (alignment == 0)
2418 alignment = i915_gem_get_gtt_alignment(obj); 2575 alignment = i915_gem_get_gtt_alignment(obj);
2419 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { 2576 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
@@ -2433,30 +2590,16 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2433 } 2590 }
2434 } 2591 }
2435 if (obj_priv->gtt_space == NULL) { 2592 if (obj_priv->gtt_space == NULL) {
2436 bool lists_empty;
2437
2438 /* If the gtt is empty and we're still having trouble 2593 /* If the gtt is empty and we're still having trouble
2439 * fitting our object in, we're out of memory. 2594 * fitting our object in, we're out of memory.
2440 */ 2595 */
2441#if WATCH_LRU 2596#if WATCH_LRU
2442 DRM_INFO("%s: GTT full, evicting something\n", __func__); 2597 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2443#endif 2598#endif
2444 spin_lock(&dev_priv->mm.active_list_lock); 2599 ret = i915_gem_evict_something(dev, obj->size);
2445 lists_empty = (list_empty(&dev_priv->mm.inactive_list) && 2600 if (ret)
2446 list_empty(&dev_priv->mm.flushing_list) &&
2447 list_empty(&dev_priv->mm.active_list));
2448 spin_unlock(&dev_priv->mm.active_list_lock);
2449 if (lists_empty) {
2450 DRM_ERROR("GTT full, but LRU list empty\n");
2451 return -ENOSPC;
2452 }
2453
2454 ret = i915_gem_evict_something(dev);
2455 if (ret != 0) {
2456 if (ret != -ERESTARTSYS)
2457 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2458 return ret; 2601 return ret;
2459 } 2602
2460 goto search_free; 2603 goto search_free;
2461 } 2604 }
2462 2605
@@ -2464,27 +2607,56 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2464 DRM_INFO("Binding object of size %zd at 0x%08x\n", 2607 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2465 obj->size, obj_priv->gtt_offset); 2608 obj->size, obj_priv->gtt_offset);
2466#endif 2609#endif
2610 if (retry_alloc) {
2611 i915_gem_object_set_page_gfp_mask (obj,
2612 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2613 }
2467 ret = i915_gem_object_get_pages(obj); 2614 ret = i915_gem_object_get_pages(obj);
2615 if (retry_alloc) {
2616 i915_gem_object_set_page_gfp_mask (obj,
2617 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2618 }
2468 if (ret) { 2619 if (ret) {
2469 drm_mm_put_block(obj_priv->gtt_space); 2620 drm_mm_put_block(obj_priv->gtt_space);
2470 obj_priv->gtt_space = NULL; 2621 obj_priv->gtt_space = NULL;
2622
2623 if (ret == -ENOMEM) {
2624 /* first try to clear up some space from the GTT */
2625 ret = i915_gem_evict_something(dev, obj->size);
2626 if (ret) {
2627 /* now try to shrink everyone else */
2628 if (! retry_alloc) {
2629 retry_alloc = true;
2630 goto search_free;
2631 }
2632
2633 return ret;
2634 }
2635
2636 goto search_free;
2637 }
2638
2471 return ret; 2639 return ret;
2472 } 2640 }
2473 2641
2474 page_count = obj->size / PAGE_SIZE;
2475 /* Create an AGP memory structure pointing at our pages, and bind it 2642 /* Create an AGP memory structure pointing at our pages, and bind it
2476 * into the GTT. 2643 * into the GTT.
2477 */ 2644 */
2478 obj_priv->agp_mem = drm_agp_bind_pages(dev, 2645 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2479 obj_priv->pages, 2646 obj_priv->pages,
2480 page_count, 2647 obj->size >> PAGE_SHIFT,
2481 obj_priv->gtt_offset, 2648 obj_priv->gtt_offset,
2482 obj_priv->agp_type); 2649 obj_priv->agp_type);
2483 if (obj_priv->agp_mem == NULL) { 2650 if (obj_priv->agp_mem == NULL) {
2484 i915_gem_object_put_pages(obj); 2651 i915_gem_object_put_pages(obj);
2485 drm_mm_put_block(obj_priv->gtt_space); 2652 drm_mm_put_block(obj_priv->gtt_space);
2486 obj_priv->gtt_space = NULL; 2653 obj_priv->gtt_space = NULL;
2487 return -ENOMEM; 2654
2655 ret = i915_gem_evict_something(dev, obj->size);
2656 if (ret)
2657 return ret;
2658
2659 goto search_free;
2488 } 2660 }
2489 atomic_inc(&dev->gtt_count); 2661 atomic_inc(&dev->gtt_count);
2490 atomic_add(obj->size, &dev->gtt_memory); 2662 atomic_add(obj->size, &dev->gtt_memory);
@@ -2496,6 +2668,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2496 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); 2668 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2497 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); 2669 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2498 2670
2671 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2672
2499 return 0; 2673 return 0;
2500} 2674}
2501 2675
@@ -2511,15 +2685,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
2511 if (obj_priv->pages == NULL) 2685 if (obj_priv->pages == NULL)
2512 return; 2686 return;
2513 2687
2514 /* XXX: The 865 in particular appears to be weird in how it handles 2688 trace_i915_gem_object_clflush(obj);
2515 * cache flushing. We haven't figured it out, but the
2516 * clflush+agp_chipset_flush doesn't appear to successfully get the
2517 * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2518 */
2519 if (IS_I865G(obj->dev)) {
2520 wbinvd();
2521 return;
2522 }
2523 2689
2524 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); 2690 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2525} 2691}
@@ -2530,21 +2696,29 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2530{ 2696{
2531 struct drm_device *dev = obj->dev; 2697 struct drm_device *dev = obj->dev;
2532 uint32_t seqno; 2698 uint32_t seqno;
2699 uint32_t old_write_domain;
2533 2700
2534 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) 2701 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2535 return; 2702 return;
2536 2703
2537 /* Queue the GPU write cache flushing we need. */ 2704 /* Queue the GPU write cache flushing we need. */
2705 old_write_domain = obj->write_domain;
2538 i915_gem_flush(dev, 0, obj->write_domain); 2706 i915_gem_flush(dev, 0, obj->write_domain);
2539 seqno = i915_add_request(dev, NULL, obj->write_domain); 2707 seqno = i915_add_request(dev, NULL, obj->write_domain);
2540 obj->write_domain = 0; 2708 obj->write_domain = 0;
2541 i915_gem_object_move_to_active(obj, seqno); 2709 i915_gem_object_move_to_active(obj, seqno);
2710
2711 trace_i915_gem_object_change_domain(obj,
2712 obj->read_domains,
2713 old_write_domain);
2542} 2714}
2543 2715
2544/** Flushes the GTT write domain for the object if it's dirty. */ 2716/** Flushes the GTT write domain for the object if it's dirty. */
2545static void 2717static void
2546i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) 2718i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2547{ 2719{
2720 uint32_t old_write_domain;
2721
2548 if (obj->write_domain != I915_GEM_DOMAIN_GTT) 2722 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2549 return; 2723 return;
2550 2724
@@ -2552,7 +2726,12 @@ i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2552 * to it immediately go to main memory as far as we know, so there's 2726 * to it immediately go to main memory as far as we know, so there's
2553 * no chipset flush. It also doesn't land in render cache. 2727 * no chipset flush. It also doesn't land in render cache.
2554 */ 2728 */
2729 old_write_domain = obj->write_domain;
2555 obj->write_domain = 0; 2730 obj->write_domain = 0;
2731
2732 trace_i915_gem_object_change_domain(obj,
2733 obj->read_domains,
2734 old_write_domain);
2556} 2735}
2557 2736
2558/** Flushes the CPU write domain for the object if it's dirty. */ 2737/** Flushes the CPU write domain for the object if it's dirty. */
@@ -2560,13 +2739,19 @@ static void
2560i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) 2739i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2561{ 2740{
2562 struct drm_device *dev = obj->dev; 2741 struct drm_device *dev = obj->dev;
2742 uint32_t old_write_domain;
2563 2743
2564 if (obj->write_domain != I915_GEM_DOMAIN_CPU) 2744 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2565 return; 2745 return;
2566 2746
2567 i915_gem_clflush_object(obj); 2747 i915_gem_clflush_object(obj);
2568 drm_agp_chipset_flush(dev); 2748 drm_agp_chipset_flush(dev);
2749 old_write_domain = obj->write_domain;
2569 obj->write_domain = 0; 2750 obj->write_domain = 0;
2751
2752 trace_i915_gem_object_change_domain(obj,
2753 obj->read_domains,
2754 old_write_domain);
2570} 2755}
2571 2756
2572/** 2757/**
@@ -2579,6 +2764,7 @@ int
2579i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) 2764i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2580{ 2765{
2581 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2766 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2767 uint32_t old_write_domain, old_read_domains;
2582 int ret; 2768 int ret;
2583 2769
2584 /* Not valid to be called on unbound objects. */ 2770 /* Not valid to be called on unbound objects. */
@@ -2591,6 +2777,9 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2591 if (ret != 0) 2777 if (ret != 0)
2592 return ret; 2778 return ret;
2593 2779
2780 old_write_domain = obj->write_domain;
2781 old_read_domains = obj->read_domains;
2782
2594 /* If we're writing through the GTT domain, then CPU and GPU caches 2783 /* If we're writing through the GTT domain, then CPU and GPU caches
2595 * will need to be invalidated at next use. 2784 * will need to be invalidated at next use.
2596 */ 2785 */
@@ -2609,6 +2798,10 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2609 obj_priv->dirty = 1; 2798 obj_priv->dirty = 1;
2610 } 2799 }
2611 2800
2801 trace_i915_gem_object_change_domain(obj,
2802 old_read_domains,
2803 old_write_domain);
2804
2612 return 0; 2805 return 0;
2613} 2806}
2614 2807
@@ -2621,6 +2814,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2621static int 2814static int
2622i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) 2815i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2623{ 2816{
2817 uint32_t old_write_domain, old_read_domains;
2624 int ret; 2818 int ret;
2625 2819
2626 i915_gem_object_flush_gpu_write_domain(obj); 2820 i915_gem_object_flush_gpu_write_domain(obj);
@@ -2636,6 +2830,9 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2636 */ 2830 */
2637 i915_gem_object_set_to_full_cpu_read_domain(obj); 2831 i915_gem_object_set_to_full_cpu_read_domain(obj);
2638 2832
2833 old_write_domain = obj->write_domain;
2834 old_read_domains = obj->read_domains;
2835
2639 /* Flush the CPU cache if it's still invalid. */ 2836 /* Flush the CPU cache if it's still invalid. */
2640 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { 2837 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2641 i915_gem_clflush_object(obj); 2838 i915_gem_clflush_object(obj);
@@ -2656,6 +2853,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2656 obj->write_domain = I915_GEM_DOMAIN_CPU; 2853 obj->write_domain = I915_GEM_DOMAIN_CPU;
2657 } 2854 }
2658 2855
2856 trace_i915_gem_object_change_domain(obj,
2857 old_read_domains,
2858 old_write_domain);
2859
2659 return 0; 2860 return 0;
2660} 2861}
2661 2862
@@ -2777,6 +2978,7 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2777 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2978 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2778 uint32_t invalidate_domains = 0; 2979 uint32_t invalidate_domains = 0;
2779 uint32_t flush_domains = 0; 2980 uint32_t flush_domains = 0;
2981 uint32_t old_read_domains;
2780 2982
2781 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); 2983 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2782 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); 2984 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
@@ -2823,6 +3025,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2823 i915_gem_clflush_object(obj); 3025 i915_gem_clflush_object(obj);
2824 } 3026 }
2825 3027
3028 old_read_domains = obj->read_domains;
3029
2826 /* The actual obj->write_domain will be updated with 3030 /* The actual obj->write_domain will be updated with
2827 * pending_write_domain after we emit the accumulated flush for all 3031 * pending_write_domain after we emit the accumulated flush for all
2828 * of our domain changes in execbuffers (which clears objects' 3032 * of our domain changes in execbuffers (which clears objects'
@@ -2841,6 +3045,10 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2841 obj->read_domains, obj->write_domain, 3045 obj->read_domains, obj->write_domain,
2842 dev->invalidate_domains, dev->flush_domains); 3046 dev->invalidate_domains, dev->flush_domains);
2843#endif 3047#endif
3048
3049 trace_i915_gem_object_change_domain(obj,
3050 old_read_domains,
3051 obj->write_domain);
2844} 3052}
2845 3053
2846/** 3054/**
@@ -2893,6 +3101,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2893 uint64_t offset, uint64_t size) 3101 uint64_t offset, uint64_t size)
2894{ 3102{
2895 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3103 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3104 uint32_t old_read_domains;
2896 int i, ret; 3105 int i, ret;
2897 3106
2898 if (offset == 0 && size == obj->size) 3107 if (offset == 0 && size == obj->size)
@@ -2939,8 +3148,13 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2939 */ 3148 */
2940 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); 3149 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2941 3150
3151 old_read_domains = obj->read_domains;
2942 obj->read_domains |= I915_GEM_DOMAIN_CPU; 3152 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2943 3153
3154 trace_i915_gem_object_change_domain(obj,
3155 old_read_domains,
3156 obj->write_domain);
3157
2944 return 0; 3158 return 0;
2945} 3159}
2946 3160
@@ -2984,6 +3198,21 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2984 } 3198 }
2985 target_obj_priv = target_obj->driver_private; 3199 target_obj_priv = target_obj->driver_private;
2986 3200
3201#if WATCH_RELOC
3202 DRM_INFO("%s: obj %p offset %08x target %d "
3203 "read %08x write %08x gtt %08x "
3204 "presumed %08x delta %08x\n",
3205 __func__,
3206 obj,
3207 (int) reloc->offset,
3208 (int) reloc->target_handle,
3209 (int) reloc->read_domains,
3210 (int) reloc->write_domain,
3211 (int) target_obj_priv->gtt_offset,
3212 (int) reloc->presumed_offset,
3213 reloc->delta);
3214#endif
3215
2987 /* The target buffer should have appeared before us in the 3216 /* The target buffer should have appeared before us in the
2988 * exec_object list, so it should have a GTT space bound by now. 3217 * exec_object list, so it should have a GTT space bound by now.
2989 */ 3218 */
@@ -2995,25 +3224,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2995 return -EINVAL; 3224 return -EINVAL;
2996 } 3225 }
2997 3226
2998 if (reloc->offset > obj->size - 4) { 3227 /* Validate that the target is in a valid r/w GPU domain */
2999 DRM_ERROR("Relocation beyond object bounds: "
3000 "obj %p target %d offset %d size %d.\n",
3001 obj, reloc->target_handle,
3002 (int) reloc->offset, (int) obj->size);
3003 drm_gem_object_unreference(target_obj);
3004 i915_gem_object_unpin(obj);
3005 return -EINVAL;
3006 }
3007 if (reloc->offset & 3) {
3008 DRM_ERROR("Relocation not 4-byte aligned: "
3009 "obj %p target %d offset %d.\n",
3010 obj, reloc->target_handle,
3011 (int) reloc->offset);
3012 drm_gem_object_unreference(target_obj);
3013 i915_gem_object_unpin(obj);
3014 return -EINVAL;
3015 }
3016
3017 if (reloc->write_domain & I915_GEM_DOMAIN_CPU || 3228 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3018 reloc->read_domains & I915_GEM_DOMAIN_CPU) { 3229 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3019 DRM_ERROR("reloc with read/write CPU domains: " 3230 DRM_ERROR("reloc with read/write CPU domains: "
@@ -3027,7 +3238,6 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3027 i915_gem_object_unpin(obj); 3238 i915_gem_object_unpin(obj);
3028 return -EINVAL; 3239 return -EINVAL;
3029 } 3240 }
3030
3031 if (reloc->write_domain && target_obj->pending_write_domain && 3241 if (reloc->write_domain && target_obj->pending_write_domain &&
3032 reloc->write_domain != target_obj->pending_write_domain) { 3242 reloc->write_domain != target_obj->pending_write_domain) {
3033 DRM_ERROR("Write domain conflict: " 3243 DRM_ERROR("Write domain conflict: "
@@ -3042,21 +3252,6 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3042 return -EINVAL; 3252 return -EINVAL;
3043 } 3253 }
3044 3254
3045#if WATCH_RELOC
3046 DRM_INFO("%s: obj %p offset %08x target %d "
3047 "read %08x write %08x gtt %08x "
3048 "presumed %08x delta %08x\n",
3049 __func__,
3050 obj,
3051 (int) reloc->offset,
3052 (int) reloc->target_handle,
3053 (int) reloc->read_domains,
3054 (int) reloc->write_domain,
3055 (int) target_obj_priv->gtt_offset,
3056 (int) reloc->presumed_offset,
3057 reloc->delta);
3058#endif
3059
3060 target_obj->pending_read_domains |= reloc->read_domains; 3255 target_obj->pending_read_domains |= reloc->read_domains;
3061 target_obj->pending_write_domain |= reloc->write_domain; 3256 target_obj->pending_write_domain |= reloc->write_domain;
3062 3257
@@ -3068,6 +3263,37 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3068 continue; 3263 continue;
3069 } 3264 }
3070 3265
3266 /* Check that the relocation address is valid... */
3267 if (reloc->offset > obj->size - 4) {
3268 DRM_ERROR("Relocation beyond object bounds: "
3269 "obj %p target %d offset %d size %d.\n",
3270 obj, reloc->target_handle,
3271 (int) reloc->offset, (int) obj->size);
3272 drm_gem_object_unreference(target_obj);
3273 i915_gem_object_unpin(obj);
3274 return -EINVAL;
3275 }
3276 if (reloc->offset & 3) {
3277 DRM_ERROR("Relocation not 4-byte aligned: "
3278 "obj %p target %d offset %d.\n",
3279 obj, reloc->target_handle,
3280 (int) reloc->offset);
3281 drm_gem_object_unreference(target_obj);
3282 i915_gem_object_unpin(obj);
3283 return -EINVAL;
3284 }
3285
3286 /* and points to somewhere within the target object. */
3287 if (reloc->delta >= target_obj->size) {
3288 DRM_ERROR("Relocation beyond target object bounds: "
3289 "obj %p target %d delta %d size %d.\n",
3290 obj, reloc->target_handle,
3291 (int) reloc->delta, (int) target_obj->size);
3292 drm_gem_object_unreference(target_obj);
3293 i915_gem_object_unpin(obj);
3294 return -EINVAL;
3295 }
3296
3071 ret = i915_gem_object_set_to_gtt_domain(obj, 1); 3297 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3072 if (ret != 0) { 3298 if (ret != 0) {
3073 drm_gem_object_unreference(target_obj); 3299 drm_gem_object_unreference(target_obj);
@@ -3126,6 +3352,8 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
3126 exec_start = (uint32_t) exec_offset + exec->batch_start_offset; 3352 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3127 exec_len = (uint32_t) exec->batch_len; 3353 exec_len = (uint32_t) exec->batch_len;
3128 3354
3355 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3356
3129 count = nbox ? nbox : 1; 3357 count = nbox ? nbox : 1;
3130 3358
3131 for (i = 0; i < count; i++) { 3359 for (i = 0; i < count; i++) {
@@ -3363,7 +3591,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3363 3591
3364 i915_verify_inactive(dev, __FILE__, __LINE__); 3592 i915_verify_inactive(dev, __FILE__, __LINE__);
3365 3593
3366 if (dev_priv->mm.wedged) { 3594 if (atomic_read(&dev_priv->mm.wedged)) {
3367 DRM_ERROR("Execbuf while wedged\n"); 3595 DRM_ERROR("Execbuf while wedged\n");
3368 mutex_unlock(&dev->struct_mutex); 3596 mutex_unlock(&dev->struct_mutex);
3369 ret = -EIO; 3597 ret = -EIO;
@@ -3421,8 +3649,23 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3421 3649
3422 /* error other than GTT full, or we've already tried again */ 3650 /* error other than GTT full, or we've already tried again */
3423 if (ret != -ENOSPC || pin_tries >= 1) { 3651 if (ret != -ENOSPC || pin_tries >= 1) {
3424 if (ret != -ERESTARTSYS) 3652 if (ret != -ERESTARTSYS) {
3425 DRM_ERROR("Failed to pin buffers %d\n", ret); 3653 unsigned long long total_size = 0;
3654 for (i = 0; i < args->buffer_count; i++)
3655 total_size += object_list[i]->size;
3656 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3657 pinned+1, args->buffer_count,
3658 total_size, ret);
3659 DRM_ERROR("%d objects [%d pinned], "
3660 "%d object bytes [%d pinned], "
3661 "%d/%d gtt bytes\n",
3662 atomic_read(&dev->object_count),
3663 atomic_read(&dev->pin_count),
3664 atomic_read(&dev->object_memory),
3665 atomic_read(&dev->pin_memory),
3666 atomic_read(&dev->gtt_memory),
3667 dev->gtt_total);
3668 }
3426 goto err; 3669 goto err;
3427 } 3670 }
3428 3671
@@ -3433,7 +3676,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3433 3676
3434 /* evict everyone we can from the aperture */ 3677 /* evict everyone we can from the aperture */
3435 ret = i915_gem_evict_everything(dev); 3678 ret = i915_gem_evict_everything(dev);
3436 if (ret) 3679 if (ret && ret != -ENOSPC)
3437 goto err; 3680 goto err;
3438 } 3681 }
3439 3682
@@ -3489,8 +3732,12 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3489 3732
3490 for (i = 0; i < args->buffer_count; i++) { 3733 for (i = 0; i < args->buffer_count; i++) {
3491 struct drm_gem_object *obj = object_list[i]; 3734 struct drm_gem_object *obj = object_list[i];
3735 uint32_t old_write_domain = obj->write_domain;
3492 3736
3493 obj->write_domain = obj->pending_write_domain; 3737 obj->write_domain = obj->pending_write_domain;
3738 trace_i915_gem_object_change_domain(obj,
3739 obj->read_domains,
3740 old_write_domain);
3494 } 3741 }
3495 3742
3496 i915_verify_inactive(dev, __FILE__, __LINE__); 3743 i915_verify_inactive(dev, __FILE__, __LINE__);
@@ -3607,11 +3854,8 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3607 i915_verify_inactive(dev, __FILE__, __LINE__); 3854 i915_verify_inactive(dev, __FILE__, __LINE__);
3608 if (obj_priv->gtt_space == NULL) { 3855 if (obj_priv->gtt_space == NULL) {
3609 ret = i915_gem_object_bind_to_gtt(obj, alignment); 3856 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3610 if (ret != 0) { 3857 if (ret)
3611 if (ret != -EBUSY && ret != -ERESTARTSYS)
3612 DRM_ERROR("Failure to bind: %d\n", ret);
3613 return ret; 3858 return ret;
3614 }
3615 } 3859 }
3616 /* 3860 /*
3617 * Pre-965 chips need a fence register set up in order to 3861 * Pre-965 chips need a fence register set up in order to
@@ -3691,6 +3935,13 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3691 } 3935 }
3692 obj_priv = obj->driver_private; 3936 obj_priv = obj->driver_private;
3693 3937
3938 if (obj_priv->madv != I915_MADV_WILLNEED) {
3939 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3940 drm_gem_object_unreference(obj);
3941 mutex_unlock(&dev->struct_mutex);
3942 return -EINVAL;
3943 }
3944
3694 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { 3945 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3695 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", 3946 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3696 args->handle); 3947 args->handle);
@@ -3803,6 +4054,56 @@ i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3803 return i915_gem_ring_throttle(dev, file_priv); 4054 return i915_gem_ring_throttle(dev, file_priv);
3804} 4055}
3805 4056
4057int
4058i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4059 struct drm_file *file_priv)
4060{
4061 struct drm_i915_gem_madvise *args = data;
4062 struct drm_gem_object *obj;
4063 struct drm_i915_gem_object *obj_priv;
4064
4065 switch (args->madv) {
4066 case I915_MADV_DONTNEED:
4067 case I915_MADV_WILLNEED:
4068 break;
4069 default:
4070 return -EINVAL;
4071 }
4072
4073 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4074 if (obj == NULL) {
4075 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4076 args->handle);
4077 return -EBADF;
4078 }
4079
4080 mutex_lock(&dev->struct_mutex);
4081 obj_priv = obj->driver_private;
4082
4083 if (obj_priv->pin_count) {
4084 drm_gem_object_unreference(obj);
4085 mutex_unlock(&dev->struct_mutex);
4086
4087 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4088 return -EINVAL;
4089 }
4090
4091 if (obj_priv->madv != __I915_MADV_PURGED)
4092 obj_priv->madv = args->madv;
4093
4094 /* if the object is no longer bound, discard its backing storage */
4095 if (i915_gem_object_is_purgeable(obj_priv) &&
4096 obj_priv->gtt_space == NULL)
4097 i915_gem_object_truncate(obj);
4098
4099 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4100
4101 drm_gem_object_unreference(obj);
4102 mutex_unlock(&dev->struct_mutex);
4103
4104 return 0;
4105}
4106
3806int i915_gem_init_object(struct drm_gem_object *obj) 4107int i915_gem_init_object(struct drm_gem_object *obj)
3807{ 4108{
3808 struct drm_i915_gem_object *obj_priv; 4109 struct drm_i915_gem_object *obj_priv;
@@ -3827,6 +4128,9 @@ int i915_gem_init_object(struct drm_gem_object *obj)
3827 obj_priv->fence_reg = I915_FENCE_REG_NONE; 4128 obj_priv->fence_reg = I915_FENCE_REG_NONE;
3828 INIT_LIST_HEAD(&obj_priv->list); 4129 INIT_LIST_HEAD(&obj_priv->list);
3829 INIT_LIST_HEAD(&obj_priv->fence_list); 4130 INIT_LIST_HEAD(&obj_priv->fence_list);
4131 obj_priv->madv = I915_MADV_WILLNEED;
4132
4133 trace_i915_gem_object_create(obj);
3830 4134
3831 return 0; 4135 return 0;
3832} 4136}
@@ -3836,6 +4140,8 @@ void i915_gem_free_object(struct drm_gem_object *obj)
3836 struct drm_device *dev = obj->dev; 4140 struct drm_device *dev = obj->dev;
3837 struct drm_i915_gem_object *obj_priv = obj->driver_private; 4141 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3838 4142
4143 trace_i915_gem_object_destroy(obj);
4144
3839 while (obj_priv->pin_count > 0) 4145 while (obj_priv->pin_count > 0)
3840 i915_gem_object_unpin(obj); 4146 i915_gem_object_unpin(obj);
3841 4147
@@ -3844,43 +4150,35 @@ void i915_gem_free_object(struct drm_gem_object *obj)
3844 4150
3845 i915_gem_object_unbind(obj); 4151 i915_gem_object_unbind(obj);
3846 4152
3847 i915_gem_free_mmap_offset(obj); 4153 if (obj_priv->mmap_offset)
4154 i915_gem_free_mmap_offset(obj);
3848 4155
3849 kfree(obj_priv->page_cpu_valid); 4156 kfree(obj_priv->page_cpu_valid);
3850 kfree(obj_priv->bit_17); 4157 kfree(obj_priv->bit_17);
3851 kfree(obj->driver_private); 4158 kfree(obj->driver_private);
3852} 4159}
3853 4160
3854/** Unbinds all objects that are on the given buffer list. */ 4161/** Unbinds all inactive objects. */
3855static int 4162static int
3856i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) 4163i915_gem_evict_from_inactive_list(struct drm_device *dev)
3857{ 4164{
3858 struct drm_gem_object *obj; 4165 drm_i915_private_t *dev_priv = dev->dev_private;
3859 struct drm_i915_gem_object *obj_priv;
3860 int ret;
3861 4166
3862 while (!list_empty(head)) { 4167 while (!list_empty(&dev_priv->mm.inactive_list)) {
3863 obj_priv = list_first_entry(head, 4168 struct drm_gem_object *obj;
3864 struct drm_i915_gem_object, 4169 int ret;
3865 list);
3866 obj = obj_priv->obj;
3867 4170
3868 if (obj_priv->pin_count != 0) { 4171 obj = list_first_entry(&dev_priv->mm.inactive_list,
3869 DRM_ERROR("Pinned object in unbind list\n"); 4172 struct drm_i915_gem_object,
3870 mutex_unlock(&dev->struct_mutex); 4173 list)->obj;
3871 return -EINVAL;
3872 }
3873 4174
3874 ret = i915_gem_object_unbind(obj); 4175 ret = i915_gem_object_unbind(obj);
3875 if (ret != 0) { 4176 if (ret != 0) {
3876 DRM_ERROR("Error unbinding object in LeaveVT: %d\n", 4177 DRM_ERROR("Error unbinding object: %d\n", ret);
3877 ret);
3878 mutex_unlock(&dev->struct_mutex);
3879 return ret; 4178 return ret;
3880 } 4179 }
3881 } 4180 }
3882 4181
3883
3884 return 0; 4182 return 0;
3885} 4183}
3886 4184
@@ -3902,6 +4200,7 @@ i915_gem_idle(struct drm_device *dev)
3902 * We need to replace this with a semaphore, or something. 4200 * We need to replace this with a semaphore, or something.
3903 */ 4201 */
3904 dev_priv->mm.suspended = 1; 4202 dev_priv->mm.suspended = 1;
4203 del_timer(&dev_priv->hangcheck_timer);
3905 4204
3906 /* Cancel the retire work handler, wait for it to finish if running 4205 /* Cancel the retire work handler, wait for it to finish if running
3907 */ 4206 */
@@ -3931,7 +4230,7 @@ i915_gem_idle(struct drm_device *dev)
3931 if (last_seqno == cur_seqno) { 4230 if (last_seqno == cur_seqno) {
3932 if (stuck++ > 100) { 4231 if (stuck++ > 100) {
3933 DRM_ERROR("hardware wedged\n"); 4232 DRM_ERROR("hardware wedged\n");
3934 dev_priv->mm.wedged = 1; 4233 atomic_set(&dev_priv->mm.wedged, 1);
3935 DRM_WAKEUP(&dev_priv->irq_queue); 4234 DRM_WAKEUP(&dev_priv->irq_queue);
3936 break; 4235 break;
3937 } 4236 }
@@ -3944,7 +4243,7 @@ i915_gem_idle(struct drm_device *dev)
3944 i915_gem_retire_requests(dev); 4243 i915_gem_retire_requests(dev);
3945 4244
3946 spin_lock(&dev_priv->mm.active_list_lock); 4245 spin_lock(&dev_priv->mm.active_list_lock);
3947 if (!dev_priv->mm.wedged) { 4246 if (!atomic_read(&dev_priv->mm.wedged)) {
3948 /* Active and flushing should now be empty as we've 4247 /* Active and flushing should now be empty as we've
3949 * waited for a sequence higher than any pending execbuffer 4248 * waited for a sequence higher than any pending execbuffer
3950 */ 4249 */
@@ -3962,29 +4261,41 @@ i915_gem_idle(struct drm_device *dev)
3962 * the GPU domains and just stuff them onto inactive. 4261 * the GPU domains and just stuff them onto inactive.
3963 */ 4262 */
3964 while (!list_empty(&dev_priv->mm.active_list)) { 4263 while (!list_empty(&dev_priv->mm.active_list)) {
3965 struct drm_i915_gem_object *obj_priv; 4264 struct drm_gem_object *obj;
4265 uint32_t old_write_domain;
3966 4266
3967 obj_priv = list_first_entry(&dev_priv->mm.active_list, 4267 obj = list_first_entry(&dev_priv->mm.active_list,
3968 struct drm_i915_gem_object, 4268 struct drm_i915_gem_object,
3969 list); 4269 list)->obj;
3970 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; 4270 old_write_domain = obj->write_domain;
3971 i915_gem_object_move_to_inactive(obj_priv->obj); 4271 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4272 i915_gem_object_move_to_inactive(obj);
4273
4274 trace_i915_gem_object_change_domain(obj,
4275 obj->read_domains,
4276 old_write_domain);
3972 } 4277 }
3973 spin_unlock(&dev_priv->mm.active_list_lock); 4278 spin_unlock(&dev_priv->mm.active_list_lock);
3974 4279
3975 while (!list_empty(&dev_priv->mm.flushing_list)) { 4280 while (!list_empty(&dev_priv->mm.flushing_list)) {
3976 struct drm_i915_gem_object *obj_priv; 4281 struct drm_gem_object *obj;
4282 uint32_t old_write_domain;
3977 4283
3978 obj_priv = list_first_entry(&dev_priv->mm.flushing_list, 4284 obj = list_first_entry(&dev_priv->mm.flushing_list,
3979 struct drm_i915_gem_object, 4285 struct drm_i915_gem_object,
3980 list); 4286 list)->obj;
3981 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; 4287 old_write_domain = obj->write_domain;
3982 i915_gem_object_move_to_inactive(obj_priv->obj); 4288 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4289 i915_gem_object_move_to_inactive(obj);
4290
4291 trace_i915_gem_object_change_domain(obj,
4292 obj->read_domains,
4293 old_write_domain);
3983 } 4294 }
3984 4295
3985 4296
3986 /* Move all inactive buffers out of the GTT. */ 4297 /* Move all inactive buffers out of the GTT. */
3987 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); 4298 ret = i915_gem_evict_from_inactive_list(dev);
3988 WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); 4299 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3989 if (ret) { 4300 if (ret) {
3990 mutex_unlock(&dev->struct_mutex); 4301 mutex_unlock(&dev->struct_mutex);
@@ -4206,9 +4517,9 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4206 if (drm_core_check_feature(dev, DRIVER_MODESET)) 4517 if (drm_core_check_feature(dev, DRIVER_MODESET))
4207 return 0; 4518 return 0;
4208 4519
4209 if (dev_priv->mm.wedged) { 4520 if (atomic_read(&dev_priv->mm.wedged)) {
4210 DRM_ERROR("Reenabling wedged hardware, good luck\n"); 4521 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4211 dev_priv->mm.wedged = 0; 4522 atomic_set(&dev_priv->mm.wedged, 0);
4212 } 4523 }
4213 4524
4214 mutex_lock(&dev->struct_mutex); 4525 mutex_lock(&dev->struct_mutex);
@@ -4274,6 +4585,10 @@ i915_gem_load(struct drm_device *dev)
4274 i915_gem_retire_work_handler); 4585 i915_gem_retire_work_handler);
4275 dev_priv->mm.next_gem_seqno = 1; 4586 dev_priv->mm.next_gem_seqno = 1;
4276 4587
4588 spin_lock(&shrink_list_lock);
4589 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4590 spin_unlock(&shrink_list_lock);
4591
4277 /* Old X drivers will take 0-2 for front, back, depth buffers */ 4592 /* Old X drivers will take 0-2 for front, back, depth buffers */
4278 dev_priv->fence_reg_start = 3; 4593 dev_priv->fence_reg_start = 3;
4279 4594
@@ -4491,3 +4806,116 @@ void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4491 list_del_init(i915_file_priv->mm.request_list.next); 4806 list_del_init(i915_file_priv->mm.request_list.next);
4492 mutex_unlock(&dev->struct_mutex); 4807 mutex_unlock(&dev->struct_mutex);
4493} 4808}
4809
4810static int
4811i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4812{
4813 drm_i915_private_t *dev_priv, *next_dev;
4814 struct drm_i915_gem_object *obj_priv, *next_obj;
4815 int cnt = 0;
4816 int would_deadlock = 1;
4817
4818 /* "fast-path" to count number of available objects */
4819 if (nr_to_scan == 0) {
4820 spin_lock(&shrink_list_lock);
4821 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4822 struct drm_device *dev = dev_priv->dev;
4823
4824 if (mutex_trylock(&dev->struct_mutex)) {
4825 list_for_each_entry(obj_priv,
4826 &dev_priv->mm.inactive_list,
4827 list)
4828 cnt++;
4829 mutex_unlock(&dev->struct_mutex);
4830 }
4831 }
4832 spin_unlock(&shrink_list_lock);
4833
4834 return (cnt / 100) * sysctl_vfs_cache_pressure;
4835 }
4836
4837 spin_lock(&shrink_list_lock);
4838
4839 /* first scan for clean buffers */
4840 list_for_each_entry_safe(dev_priv, next_dev,
4841 &shrink_list, mm.shrink_list) {
4842 struct drm_device *dev = dev_priv->dev;
4843
4844 if (! mutex_trylock(&dev->struct_mutex))
4845 continue;
4846
4847 spin_unlock(&shrink_list_lock);
4848
4849 i915_gem_retire_requests(dev);
4850
4851 list_for_each_entry_safe(obj_priv, next_obj,
4852 &dev_priv->mm.inactive_list,
4853 list) {
4854 if (i915_gem_object_is_purgeable(obj_priv)) {
4855 i915_gem_object_unbind(obj_priv->obj);
4856 if (--nr_to_scan <= 0)
4857 break;
4858 }
4859 }
4860
4861 spin_lock(&shrink_list_lock);
4862 mutex_unlock(&dev->struct_mutex);
4863
4864 would_deadlock = 0;
4865
4866 if (nr_to_scan <= 0)
4867 break;
4868 }
4869
4870 /* second pass, evict/count anything still on the inactive list */
4871 list_for_each_entry_safe(dev_priv, next_dev,
4872 &shrink_list, mm.shrink_list) {
4873 struct drm_device *dev = dev_priv->dev;
4874
4875 if (! mutex_trylock(&dev->struct_mutex))
4876 continue;
4877
4878 spin_unlock(&shrink_list_lock);
4879
4880 list_for_each_entry_safe(obj_priv, next_obj,
4881 &dev_priv->mm.inactive_list,
4882 list) {
4883 if (nr_to_scan > 0) {
4884 i915_gem_object_unbind(obj_priv->obj);
4885 nr_to_scan--;
4886 } else
4887 cnt++;
4888 }
4889
4890 spin_lock(&shrink_list_lock);
4891 mutex_unlock(&dev->struct_mutex);
4892
4893 would_deadlock = 0;
4894 }
4895
4896 spin_unlock(&shrink_list_lock);
4897
4898 if (would_deadlock)
4899 return -1;
4900 else if (cnt > 0)
4901 return (cnt / 100) * sysctl_vfs_cache_pressure;
4902 else
4903 return 0;
4904}
4905
4906static struct shrinker shrinker = {
4907 .shrink = i915_gem_shrink,
4908 .seeks = DEFAULT_SEEKS,
4909};
4910
4911__init void
4912i915_gem_shrinker_init(void)
4913{
4914 register_shrinker(&shrinker);
4915}
4916
4917__exit void
4918i915_gem_shrinker_exit(void)
4919{
4920 unregister_shrinker(&shrinker);
4921}