diff options
author | Keith Packard <keithp@keithp.com> | 2010-11-22 04:24:22 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-22 04:26:22 -0500 |
commit | 5f75377db4d8d81ca4465b54d3c339c70c6a0fa2 (patch) | |
tree | 2549b235627ccc1010e1c4dca26505c7f552a461 /drivers/gpu/drm/i915/i915_drv.h | |
parent | cff458c21063de960bde0e39770a0f4cd0477d95 (diff) |
drm/i915: Fix restore of 965 fence regs since the register tracing change.
We were reading our 64-bit value in I915_READ64 and returning 32 bits
of it. The restoration of fence regs at resume then had a zero end
value, and the fence had no effect.
Version 2: Split register access functions into per-size versions
Sharing code between different sizes seemed reasonable when we only
needed a single copy, but as 64-bit access requires its own version,
it makes sense to just split them out for each size.
Reported-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
[ickle: use a macro to create the various read/write routines]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 68 |
1 files changed, 36 insertions, 32 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4c20ad92c0f..db79df376b8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1245,45 +1245,49 @@ extern void intel_display_print_error_state(struct seq_file *m, | |||
1245 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ | 1245 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ |
1246 | } while (0) | 1246 | } while (0) |
1247 | 1247 | ||
1248 | #define I915_READ(reg) i915_read(dev_priv, (reg), 4) | ||
1249 | #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4) | ||
1250 | #define I915_READ16(reg) i915_read(dev_priv, (reg), 2) | ||
1251 | #define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2) | ||
1252 | #define I915_READ8(reg) i915_read(dev_priv, (reg), 1) | ||
1253 | #define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1) | ||
1254 | #define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8) | ||
1255 | #define I915_READ64(reg) i915_read(dev_priv, (reg), 8) | ||
1256 | 1248 | ||
1249 | #define __i915_read(x, y) \ | ||
1250 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | ||
1251 | u##x val = read##y(dev_priv->regs + reg); \ | ||
1252 | trace_i915_reg_rw('R', reg, val, sizeof(val)); \ | ||
1253 | return val; \ | ||
1254 | } | ||
1255 | __i915_read(8, b) | ||
1256 | __i915_read(16, w) | ||
1257 | __i915_read(32, l) | ||
1258 | __i915_read(64, q) | ||
1259 | #undef __i915_read | ||
1260 | |||
1261 | #define __i915_write(x, y) \ | ||
1262 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | ||
1263 | trace_i915_reg_rw('W', reg, val, sizeof(val)); \ | ||
1264 | write##y(val, dev_priv->regs + reg); \ | ||
1265 | } | ||
1266 | __i915_write(8, b) | ||
1267 | __i915_write(16, w) | ||
1268 | __i915_write(32, l) | ||
1269 | __i915_write(64, q) | ||
1270 | #undef __i915_write | ||
1271 | |||
1272 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | ||
1273 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | ||
1274 | |||
1275 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | ||
1276 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | ||
1277 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | ||
1278 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | ||
1279 | |||
1280 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | ||
1281 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | ||
1257 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) | 1282 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1258 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | 1283 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
1259 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | 1284 | |
1260 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | 1285 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
1286 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | ||
1261 | 1287 | ||
1262 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | 1288 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
1263 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | 1289 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
1264 | 1290 | ||
1265 | static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len) | ||
1266 | { | ||
1267 | u64 val = 0; | ||
1268 | |||
1269 | switch (len) { | ||
1270 | case 8: | ||
1271 | val = readq(dev_priv->regs + reg); | ||
1272 | break; | ||
1273 | case 4: | ||
1274 | val = readl(dev_priv->regs + reg); | ||
1275 | break; | ||
1276 | case 2: | ||
1277 | val = readw(dev_priv->regs + reg); | ||
1278 | break; | ||
1279 | case 1: | ||
1280 | val = readb(dev_priv->regs + reg); | ||
1281 | break; | ||
1282 | } | ||
1283 | trace_i915_reg_rw('R', reg, val, len); | ||
1284 | |||
1285 | return val; | ||
1286 | } | ||
1287 | 1291 | ||
1288 | /* On SNB platform, before reading ring registers forcewake bit | 1292 | /* On SNB platform, before reading ring registers forcewake bit |
1289 | * must be set to prevent GT core from power down and stale values being | 1293 | * must be set to prevent GT core from power down and stale values being |