drm/exynos: fixed wrong pageflip finish event for interlace mode

Pageflip finish event for interlace mode has bug on checking top
field vsync because of comparing between dma address converted
by start coordinates and non-converted dma address.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

1 files changed, 7 insertions, 5 deletions

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 2f6727a4e76..3bc01a6b5e9 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -886,7 +886,7 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
         struct exynos_drm_hdmi_context *drm_hdmi_ctx = arg;
         struct mixer_context *ctx = drm_hdmi_ctx->ctx;
         struct mixer_resources *res = &ctx->mixer_res;
-        u32 val, val_base;
+        u32 val, base, shadow;
 
         spin_lock(&res->reg_slock);
 
@@ -897,12 +897,14 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
         if (val & MXR_INT_STATUS_VSYNC) {
                 /* interlace scan need to check shadow register */
                 if (ctx->interlace) {
-                        val_base = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
-                        if (ctx->win_data[0].dma_addr != val_base)
+                        base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
+                        shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
+                        if (base != shadow)
                                 goto out;
 
-                        val_base = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
-                        if (ctx->win_data[1].dma_addr != val_base)
+                        base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
+                        shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
+                        if (base != shadow)
                                 goto out;
                 }