Patched in Tegra support.

80 files changed, 2126 insertions, 16839 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 682de754d63..d539efd96d4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -2,14 +2,6 @@
 # GPIO infrastructure and drivers
 #
 
-config ARCH_HAVE_CUSTOM_GPIO_H
-        bool
-        help
-          Selecting this config option from the architecture Kconfig allows
-          the architecture to provide a custom asm/gpio.h implementation
-          overriding the default implementations.  New uses of this are
-          strongly discouraged.
-
 config ARCH_WANT_OPTIONAL_GPIOLIB
         bool
         help
@@ -45,14 +37,6 @@ menuconfig GPIOLIB
 
 if GPIOLIB
 
-config OF_GPIO
-        def_bool y
-        depends on OF
-
-config GPIO_ACPI
-        def_bool y
-        depends on ACPI
-
 config DEBUG_GPIO
         bool "Debug GPIO calls"
         depends on DEBUG_KERNEL
@@ -90,26 +74,11 @@ config GPIO_DA9052
         help
           Say yes here to enable the GPIO driver for the DA9052 chip.
 
-config GPIO_DA9055
-        tristate "Dialog Semiconductor DA9055 GPIO"
-        depends on MFD_DA9055
-        help
-          Say yes here to enable the GPIO driver for the DA9055 chip.
-
-          The Dialog DA9055 PMIC chip has 3 GPIO pins that can be
-          be controller by this driver.
-
-          If driver is built as a module it will be called gpio-da9055.
-
 config GPIO_MAX730X
         tristate
 
 comment "Memory mapped GPIO drivers:"
 
-config GPIO_CLPS711X
-        def_bool y
-        depends on ARCH_CLPS711X
-
 config GPIO_GENERIC_PLATFORM
         tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
         select GPIO_GENERIC
@@ -118,44 +87,25 @@ config GPIO_GENERIC_PLATFORM
 
 config GPIO_IT8761E
         tristate "IT8761E GPIO support"
-        depends on X86  # unconditional access to IO space.
         help
           Say yes here to support GPIO functionality of IT8761E super I/O chip.
 
-config GPIO_EM
-        tristate "Emma Mobile GPIO"
-        depends on ARM
-        help
-          Say yes here to support GPIO on Renesas Emma Mobile SoCs.
-
 config GPIO_EP93XX
         def_bool y
         depends on ARCH_EP93XX
         select GPIO_GENERIC
 
-config GPIO_MM_LANTIQ
-        bool "Lantiq Memory mapped GPIOs"
-        depends on LANTIQ && SOC_XWAY
-        help
-          This enables support for memory mapped GPIOs on the External Bus Unit
-          (EBU) found on Lantiq SoCs. The gpios are output only as they are
-          created by attaching a 16bit latch to the bus.
+config GPIO_EXYNOS4
+        def_bool y
+        depends on CPU_EXYNOS4210
 
 config GPIO_MPC5200
         def_bool y
         depends on PPC_MPC52xx
 
-config GPIO_MPC8XXX
-        bool "MPC512x/MPC8xxx GPIO support"
-        depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
-                   FSL_SOC_BOOKE || PPC_86xx
-        help
-          Say Y here if you're going to use hardware that connects to the
-          MPC512x/831x/834x/837x/8572/8610 GPIOs.
-
 config GPIO_MSM_V1
         tristate "Qualcomm MSM GPIO v1"
-        depends on GPIOLIB && ARCH_MSM && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
+        depends on GPIOLIB && ARCH_MSM
         help
           Say yes here to support the GPIO interface on ARM v6 based
           Qualcomm MSM chips.  Most of the pins on the MSM can be
@@ -169,13 +119,6 @@ config GPIO_MSM_V2
           Qualcomm MSM chips.  Most of the pins on the MSM can be
           selected for GPIO, and are controlled by this driver.
 
-config GPIO_MVEBU
-        def_bool y
-        depends on PLAT_ORION
-        depends on OF
-        select GPIO_GENERIC
-        select GENERIC_IRQ_CHIP
-
 config GPIO_MXC
         def_bool y
         depends on ARCH_MXC
@@ -188,47 +131,23 @@ config GPIO_MXS
         select GPIO_GENERIC
         select GENERIC_IRQ_CHIP
 
-config GPIO_PL061
-        bool "PrimeCell PL061 GPIO support"
-        depends on ARM && ARM_AMBA
-        select GENERIC_IRQ_CHIP
-        help
-          Say yes here to support the PrimeCell PL061 GPIO device
-
-config GPIO_PXA
-        bool "PXA GPIO support"
-        depends on ARCH_PXA || ARCH_MMP
-        help
-          Say yes here to support the PXA GPIO device
-
-config GPIO_SPEAR_SPICS
-        bool "ST SPEAr13xx SPI Chip Select as GPIO support"
-        depends on PLAT_SPEAR
-        select GENERIC_IRQ_CHIP
-        help
-          Say yes here to support ST SPEAr SPI Chip Select as GPIO device
+config GPIO_PLAT_SAMSUNG
+        def_bool y
+        depends on SAMSUNG_GPIOLIB_4BIT
 
-config GPIO_STA2X11
-        bool "STA2x11/ConneXt GPIO support"
-        depends on MFD_STA2X11
-        select GENERIC_IRQ_CHIP
-        help
-          Say yes here to support the STA2x11/ConneXt GPIO device.
-          The GPIO module has 128 GPIO pins with alternate functions.
+config GPIO_S5PC100
+        def_bool y
+        depends on CPU_S5PC100
 
-config GPIO_TS5500
-        tristate "TS-5500 DIO blocks and compatibles"
-        help
-          This driver supports Digital I/O exposed by pin blocks found on some
-          Technologic Systems platforms. It includes, but is not limited to, 3
-          blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600
-          LCD port.
+config GPIO_S5PV210
+        def_bool y
+        depends on CPU_S5PV210
 
-config GPIO_VT8500
-        bool "VIA/Wondermedia SoC GPIO Support"
-        depends on ARCH_VT8500
+config GPIO_PL061
+        bool "PrimeCell PL061 GPIO support"
+        depends on ARM_AMBA
         help
-          Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+          Say yes here to support the PrimeCell PL061 GPIO device
 
 config GPIO_XILINX
         bool "Xilinx GPIO support"
@@ -243,13 +162,13 @@ config GPIO_VR41XX
           Say yes here to support the NEC VR4100 series General-purpose I/O Uint
 
 config GPIO_SCH
-        tristate "Intel SCH/TunnelCreek/Centerton GPIO"
+        tristate "Intel SCH/TunnelCreek GPIO"
         depends on PCI && X86
         select MFD_CORE
         select LPC_SCH
         help
-          Say yes here to support GPIO interface on Intel Poulsbo SCH,
-          Intel Tunnel Creek processor or Intel Centerton processor.
+          Say yes here to support GPIO interface on Intel Poulsbo SCH
+          or Intel Tunnel Creek processor.
           The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
           powered by the core power rail and are turned off during sleep
           modes (S3 and higher). The remaining four GPIOs are powered by
@@ -258,26 +177,10 @@ config GPIO_SCH
           system from the Suspend-to-RAM state.
           The Intel Tunnel Creek processor has 5 GPIOs powered by the
           core power rail and 9 from suspend power supply.
-          The Intel Centerton processor has a total of 30 GPIO pins.
-          Twenty-one are powered by the core power rail and 9 from the
-          suspend power supply.
-
-config GPIO_ICH
-        tristate "Intel ICH GPIO"
-        depends on PCI && X86
-        select MFD_CORE
-        select LPC_ICH
-        help
-          Say yes here to support the GPIO functionality of a number of Intel
-          ICH-based chipsets.  Currently supported devices: ICH6, ICH7, ICH8
-          ICH9, ICH10, Series 5/3400 (eg Ibex Peak), Series 6/C200 (eg
-          Cougar Point), NM10 (Tiger Point), and 3100 (Whitmore Lake).
-
-          If unsure, say N.
 
 config GPIO_VX855
         tristate "VIA VX855/VX875 GPIO"
-        depends on PCI
+        depends on MFD_SUPPORT && PCI
         select MFD_CORE
         select MFD_VX855
         help
@@ -287,25 +190,8 @@ config GPIO_VX855
           additional drivers must be enabled in order to use the
           functionality of the device.
 
-config GPIO_GE_FPGA
-        bool "GE FPGA based GPIO"
-        depends on GE_FPGA
-        help
-          Support for common GPIO functionality provided on some GE Single Board
-          Computers.
-
-          This driver provides basic support (configure as input or output, read
-          and write pin state) for GPIO implemented in a number of GE single
-          board computers.
-
 comment "I2C GPIO expanders:"
 
-config GPIO_ARIZONA
-        tristate "Wolfson Microelectronics Arizona class devices"
-        depends on MFD_ARIZONA
-        help
-          Support for GPIOs on Wolfson Arizona class devices.
-
 config GPIO_MAX7300
         tristate "Maxim MAX7300 GPIO expander"
         depends on I2C
@@ -339,14 +225,8 @@ config GPIO_MAX732X_IRQ
           Say yes here to enable the max732x to be used as an interrupt
           controller. It requires the driver to be built in the kernel.
 
-config GPIO_MC9S08DZ60
-        bool "MX35 3DS BOARD MC9S08DZ60 GPIO functions"
-        depends on I2C=y && MACH_MX35_3DS
-        help
-          Select this to enable the MC9S08DZ60 GPIO driver
-
 config GPIO_PCA953X
-        tristate "PCA953x, PCA955x, PCA957x, TCA64xx, and MAX7310 I/O ports"
+        tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
         depends on I2C
         help
           Say yes here to provide access to several register-oriented
@@ -355,11 +235,10 @@ config GPIO_PCA953X
 
           4 bits:       pca9536, pca9537
 
-          8 bits:       max7310, max7315, pca6107, pca9534, pca9538, pca9554,
-                        pca9556, pca9557, pca9574, tca6408
+          8 bits:       max7310, pca9534, pca9538, pca9554, pca9557,
+                        tca6408
 
-          16 bits:      max7312, max7313, pca9535, pca9539, pca9555, pca9575,
-                        tca6416
+          16 bits:      pca9535, pca9539, pca9555, tca6416
 
 config GPIO_PCA953X_IRQ
         bool "Interrupt controller support for PCA953x"
@@ -371,7 +250,6 @@ config GPIO_PCA953X_IRQ
 config GPIO_PCF857X
         tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders"
         depends on I2C
-        select IRQ_DOMAIN
         help
           Say yes here to provide access to most "quasi-bidirectional" I2C
           GPIO expanders used for additional digital outputs or inputs.
@@ -393,15 +271,6 @@ config GPIO_PCF857X
           This driver provides an in-kernel interface to those GPIOs using
           platform-neutral GPIO calls.
 
-config GPIO_RC5T583
-        bool "RICOH RC5T583 GPIO"
-        depends on MFD_RC5T583
-        help
-          Select this option to enable GPIO driver for the Ricoh RC5T583
-          chip family.
-          This driver provides the support for driving/reading the gpio pins
-          of RC5T583 device through standard gpio library.
-
 config GPIO_SX150X
         bool "Semtech SX150x I2C GPIO expander"
         depends on I2C=y
@@ -420,16 +289,6 @@ config GPIO_STMPE
           This enables support for the GPIOs found on the STMPE I/O
           Expanders.
 
-config GPIO_STP_XWAY
-        bool "XWAY STP GPIOs"
-        depends on SOC_XWAY
-        help
-          This enables support for the Serial To Parallel (STP) unit found on
-          XWAY SoC. The STP allows the SoC to drive a shift registers cascade,
-          that can be up to 24 bit. This peripheral is aimed at driving leds.
-          Some of the gpios/leds can be auto updated by the soc with dsl and
-          phy status.
-
 config GPIO_TC3589X
         bool "TC3589X GPIOs"
         depends on MFD_TC3589X
@@ -450,13 +309,6 @@ config GPIO_TWL4030
           Say yes here to access the GPIO signals of various multi-function
           power management chips from Texas Instruments.
 
-config GPIO_TWL6040
-        tristate "TWL6040 GPO"
-        depends on TWL6040_CORE
-        help
-          Say yes here to access the GPO signals of twl6040
-          audio chip from Texas Instruments.
-
 config GPIO_WM831X
         tristate "WM831x GPIOs"
         depends on MFD_WM831X
@@ -499,22 +351,11 @@ config GPIO_ADP5588_IRQ
           Say yes here to enable the adp5588 to be used as an interrupt
           controller. It requires the driver to be built in the kernel.
 
-config GPIO_ADNP
-        tristate "Avionic Design N-bit GPIO expander"
-        depends on I2C && OF_GPIO
-        help
-          This option enables support for N GPIOs found on Avionic Design
-          I2C GPIO expanders. The register space will be extended by powers
-          of two, so the controller will need to accommodate for that. For
-          example: if a controller provides 48 pins, 6 registers will be
-          enough to represent all pins, but the driver will assume a
-          register layout for 64 pins (8 registers).
-
 comment "PCI GPIO expanders:"
 
 config GPIO_CS5535
         tristate "AMD CS5535/CS5536 GPIO support"
-        depends on PCI && X86 && MFD_CS5535
+        depends on PCI && X86 && !CS5535_GPIO && MFD_CS5535
         help
           The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
           can be used for quite a number of things.  The CS5535/6 is found on
@@ -538,59 +379,35 @@ config GPIO_BT8XX
 
           If unsure, say N.
 
-config GPIO_AMD8111
-        tristate "AMD 8111 GPIO driver"
-        depends on PCI
-        help
-          The AMD 8111 south bridge contains 32 GPIO pins which can be used.
-
-          Note, that usually system firmware/ACPI handles GPIO pins on their
-          own and users might easily break their systems with uncarefull usage
-          of this driver!
-
-          If unsure, say N
-
 config GPIO_LANGWELL
         bool "Intel Langwell/Penwell GPIO support"
         depends on PCI && X86
-        select IRQ_DOMAIN
         help
           Say Y here to support Intel Langwell/Penwell GPIO.
 
 config GPIO_PCH
-        tristate "Intel EG20T PCH/LAPIS Semiconductor IOH(ML7223/ML7831) GPIO"
+        tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO"
         depends on PCI && X86
-        select GENERIC_IRQ_CHIP
         help
           This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff
           which is an IOH(Input/Output Hub) for x86 embedded processor.
           This driver can access PCH GPIO device.
 
-          This driver also can be used for LAPIS Semiconductor IOH(Input/
-          Output Hub), ML7223 and ML7831.
+          This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+          Output Hub), ML7223.
           ML7223 IOH is for MP(Media Phone) use.
-          ML7831 IOH is for general purpose use.
-          ML7223/ML7831 is companion chip for Intel Atom E6xx series.
-          ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+          ML7223 is companion chip for Intel Atom E6xx series.
+          ML7223 is completely compatible for Intel EG20T PCH.
 
 config GPIO_ML_IOH
         tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
         depends on PCI
-        select GENERIC_IRQ_CHIP
         help
           ML7213 is companion chip for Intel Atom E6xx series.
           This driver can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/Output
           Hub) which is for IVI(In-Vehicle Infotainment) use.
           This driver can access the IOH's GPIO device.
 
-config GPIO_SODAVILLE
-        bool "Intel Sodaville GPIO support"
-        depends on X86 && PCI && OF
-        select GPIO_GENERIC
-        select GENERIC_IRQ_CHIP
-        help
-          Say Y here to support Intel Sodaville GPIO.
-
 config GPIO_TIMBERDALE
         bool "Support for timberdale GPIO IP"
         depends on MFD_TIMBERDALE && HAS_IOMEM
@@ -600,6 +417,7 @@ config GPIO_TIMBERDALE
 config GPIO_RDC321X
         tristate "RDC R-321x GPIO support"
         depends on PCI
+        select MFD_SUPPORT
         select MFD_CORE
         select MFD_RDC321X
         help
@@ -663,38 +481,10 @@ config GPIO_AB8500
         help
           Select this to enable the AB8500 IC GPIO driver
 
-config GPIO_TPS6586X
-        bool "TPS6586X GPIO"
-        depends on MFD_TPS6586X
-        help
-          Select this option to enable GPIO driver for the TPS6586X
-          chip family.
-
 config GPIO_TPS65910
         bool "TPS65910 GPIO"
         depends on MFD_TPS65910
         help
           Select this option to enable GPIO driver for the TPS65910
           chip family.
-
-config GPIO_MSIC
-        bool "Intel MSIC mixed signal gpio support"
-        depends on MFD_INTEL_MSIC
-        help
-          Enable support for GPIO on intel MSIC controllers found in
-          intel MID devices
-
-comment "USB GPIO expanders:"
-
-config GPIO_VIPERBOARD
-        tristate "Viperboard GPIO a & b support"
-        depends on MFD_VIPERBOARD && USB
-        help
-          Say yes here to access the GPIO signals of Nano River
-          Technologies Viperboard. There are two GPIO chips on the
-          board: gpioa and gpiob.
-          See viperboard API specification and Nano
-          River Tech's viperboard.h for detailed meaning
-          of the module parameters.
-
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c5aebd008dd..9588948c96f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -2,83 +2,59 @@
 
 ccflags-$(CONFIG_DEBUG_GPIO)    += -DDEBUG
 
-obj-$(CONFIG_GPIOLIB)           += gpiolib.o devres.o
-obj-$(CONFIG_OF_GPIO)           += gpiolib-of.o
-obj-$(CONFIG_GPIO_ACPI)         += gpiolib-acpi.o
+obj-$(CONFIG_GPIOLIB)           += gpiolib.o
 
 # Device drivers. Generally keep list sorted alphabetically
 obj-$(CONFIG_GPIO_GENERIC)      += gpio-generic.o
 
 obj-$(CONFIG_GPIO_74X164)       += gpio-74x164.o
 obj-$(CONFIG_GPIO_AB8500)       += gpio-ab8500.o
-obj-$(CONFIG_GPIO_ADNP)         += gpio-adnp.o
 obj-$(CONFIG_GPIO_ADP5520)      += gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)      += gpio-adp5588.o
-obj-$(CONFIG_GPIO_AMD8111)      += gpio-amd8111.o
-obj-$(CONFIG_GPIO_ARIZONA)      += gpio-arizona.o
 obj-$(CONFIG_GPIO_BT8XX)        += gpio-bt8xx.o
-obj-$(CONFIG_GPIO_CLPS711X)     += gpio-clps711x.o
 obj-$(CONFIG_GPIO_CS5535)       += gpio-cs5535.o
 obj-$(CONFIG_GPIO_DA9052)       += gpio-da9052.o
-obj-$(CONFIG_GPIO_DA9055)       += gpio-da9055.o
-obj-$(CONFIG_ARCH_DAVINCI)      += gpio-davinci.o
-obj-$(CONFIG_GPIO_EM)           += gpio-em.o
 obj-$(CONFIG_GPIO_EP93XX)       += gpio-ep93xx.o
-obj-$(CONFIG_GPIO_GE_FPGA)      += gpio-ge.o
-obj-$(CONFIG_GPIO_ICH)          += gpio-ich.o
+obj-$(CONFIG_GPIO_EXYNOS4)      += gpio-exynos4.o
 obj-$(CONFIG_GPIO_IT8761E)      += gpio-it8761e.o
 obj-$(CONFIG_GPIO_JANZ_TTL)     += gpio-janz-ttl.o
-obj-$(CONFIG_ARCH_KS8695)       += gpio-ks8695.o
 obj-$(CONFIG_GPIO_LANGWELL)     += gpio-langwell.o
-obj-$(CONFIG_ARCH_LPC32XX)      += gpio-lpc32xx.o
 obj-$(CONFIG_GPIO_MAX730X)      += gpio-max730x.o
 obj-$(CONFIG_GPIO_MAX7300)      += gpio-max7300.o
 obj-$(CONFIG_GPIO_MAX7301)      += gpio-max7301.o
 obj-$(CONFIG_GPIO_MAX732X)      += gpio-max732x.o
 obj-$(CONFIG_GPIO_MC33880)      += gpio-mc33880.o
-obj-$(CONFIG_GPIO_MC9S08DZ60)   += gpio-mc9s08dz60.o
 obj-$(CONFIG_GPIO_MCP23S08)     += gpio-mcp23s08.o
 obj-$(CONFIG_GPIO_ML_IOH)       += gpio-ml-ioh.o
-obj-$(CONFIG_GPIO_MM_LANTIQ)    += gpio-mm-lantiq.o
 obj-$(CONFIG_GPIO_MPC5200)      += gpio-mpc5200.o
-obj-$(CONFIG_GPIO_MPC8XXX)      += gpio-mpc8xxx.o
-obj-$(CONFIG_GPIO_MSIC)         += gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)       += gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)       += gpio-msm-v2.o
-obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)          += gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)          += gpio-mxs.o
+obj-$(CONFIG_PLAT_NOMADIK)      += gpio-nomadik.o
 obj-$(CONFIG_ARCH_OMAP)         += gpio-omap.o
 obj-$(CONFIG_GPIO_PCA953X)      += gpio-pca953x.o
 obj-$(CONFIG_GPIO_PCF857X)      += gpio-pcf857x.o
 obj-$(CONFIG_GPIO_PCH)          += gpio-pch.o
 obj-$(CONFIG_GPIO_PL061)        += gpio-pl061.o
-obj-$(CONFIG_GPIO_PXA)          += gpio-pxa.o
-obj-$(CONFIG_GPIO_RC5T583)      += gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)      += gpio-rdc321x.o
-obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
-obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
+
+obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
+obj-$(CONFIG_GPIO_S5PC100)      += gpio-s5pc100.o
+obj-$(CONFIG_GPIO_S5PV210)      += gpio-s5pv210.o
+
 obj-$(CONFIG_GPIO_SCH)          += gpio-sch.o
-obj-$(CONFIG_GPIO_SODAVILLE)    += gpio-sodaville.o
-obj-$(CONFIG_GPIO_SPEAR_SPICS)  += gpio-spear-spics.o
-obj-$(CONFIG_GPIO_STA2X11)      += gpio-sta2x11.o
 obj-$(CONFIG_GPIO_STMPE)        += gpio-stmpe.o
-obj-$(CONFIG_GPIO_STP_XWAY)     += gpio-stp-xway.o
 obj-$(CONFIG_GPIO_SX150X)       += gpio-sx150x.o
 obj-$(CONFIG_GPIO_TC3589X)      += gpio-tc3589x.o
 obj-$(CONFIG_ARCH_TEGRA)        += gpio-tegra.o
 obj-$(CONFIG_GPIO_TIMBERDALE)   += gpio-timberdale.o
-obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o
-obj-$(CONFIG_GPIO_TPS6586X)     += gpio-tps6586x.o
 obj-$(CONFIG_GPIO_TPS65910)     += gpio-tps65910.o
 obj-$(CONFIG_GPIO_TPS65912)     += gpio-tps65912.o
-obj-$(CONFIG_GPIO_TS5500)       += gpio-ts5500.o
 obj-$(CONFIG_GPIO_TWL4030)      += gpio-twl4030.o
-obj-$(CONFIG_GPIO_TWL6040)      += gpio-twl6040.o
+obj-$(CONFIG_MACH_U300)         += gpio-u300.o
 obj-$(CONFIG_GPIO_UCB1400)      += gpio-ucb1400.o
-obj-$(CONFIG_GPIO_VIPERBOARD)   += gpio-viperboard.o
 obj-$(CONFIG_GPIO_VR41XX)       += gpio-vr41xx.o
-obj-$(CONFIG_GPIO_VT8500)       += gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)        += gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)       += gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)       += gpio-wm8350.o
diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c
deleted file mode 100644
index 1077754f828..00000000000
--- a/drivers/gpio/devres.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * drivers/gpio/devres.c - managed gpio resources
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * This file is based on kernel/irq/devres.c
- *
- * Copyright (c) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/device.h>
-#include <linux/gfp.h>
-
-static void devm_gpio_release(struct device *dev, void *res)
-{
-        unsigned *gpio = res;
-
-        gpio_free(*gpio);
-}
-
-static int devm_gpio_match(struct device *dev, void *res, void *data)
-{
-        unsigned *this = res, *gpio = data;
-
-        return *this == *gpio;
-}
-
-/**
- *      devm_gpio_request - request a gpio for a managed device
- *      @dev: device to request the gpio for
- *      @gpio: gpio to allocate
- *      @label: the name of the requested gpio
- *
- *      Except for the extra @dev argument, this function takes the
- *      same arguments and performs the same function as
- *      gpio_request().  GPIOs requested with this function will be
- *      automatically freed on driver detach.
- *
- *      If an GPIO allocated with this function needs to be freed
- *      separately, devm_gpio_free() must be used.
- */
-
-int devm_gpio_request(struct device *dev, unsigned gpio, const char *label)
-{
-        unsigned *dr;
-        int rc;
-
-        dr = devres_alloc(devm_gpio_release, sizeof(unsigned), GFP_KERNEL);
-        if (!dr)
-                return -ENOMEM;
-
-        rc = gpio_request(gpio, label);
-        if (rc) {
-                devres_free(dr);
-                return rc;
-        }
-
-        *dr = gpio;
-        devres_add(dev, dr);
-
-        return 0;
-}
-EXPORT_SYMBOL(devm_gpio_request);
-
-/**
- *      devm_gpio_request_one - request a single GPIO with initial setup
- *      @dev:   device to request for
- *      @gpio:  the GPIO number
- *      @flags: GPIO configuration as specified by GPIOF_*
- *      @label: a literal description string of this GPIO
- */
-int devm_gpio_request_one(struct device *dev, unsigned gpio,
-                          unsigned long flags, const char *label)
-{
-        unsigned *dr;
-        int rc;
-
-        dr = devres_alloc(devm_gpio_release, sizeof(unsigned), GFP_KERNEL);
-        if (!dr)
-                return -ENOMEM;
-
-        rc = gpio_request_one(gpio, flags, label);
-        if (rc) {
-                devres_free(dr);
-                return rc;
-        }
-
-        *dr = gpio;
-        devres_add(dev, dr);
-
-        return 0;
-}
-EXPORT_SYMBOL(devm_gpio_request_one);
-
-/**
- *      devm_gpio_free - free an interrupt
- *      @dev: device to free gpio for
- *      @gpio: gpio to free
- *
- *      Except for the extra @dev argument, this function takes the
- *      same arguments and performs the same function as gpio_free().
- *      This function instead of gpio_free() should be used to manually
- *      free GPIOs allocated with devm_gpio_request().
- */
-void devm_gpio_free(struct device *dev, unsigned int gpio)
-{
-
-        WARN_ON(devres_release(dev, devm_gpio_release, devm_gpio_match,
-                &gpio));
-}
-EXPORT_SYMBOL(devm_gpio_free);
diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c
index 464be961f60..ff525c0958d 100644
--- a/drivers/gpio/gpio-74x164.c
+++ b/drivers/gpio/gpio-74x164.c
@@ -14,18 +14,13 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/74x164.h>
 #include <linux/gpio.h>
-#include <linux/of_gpio.h>
 #include <linux/slab.h>
-#include <linux/module.h>
-
-#define GEN_74X164_NUMBER_GPIOS 8
 
 struct gen_74x164_chip {
         struct spi_device       *spi;
-        u8                      *buffer;
         struct gpio_chip        gpio_chip;
         struct mutex            lock;
-        u32                     registers;
+        u8                      port_config;
 };
 
 static struct gen_74x164_chip *gpio_to_74x164_chip(struct gpio_chip *gc)
@@ -35,47 +30,17 @@ static struct gen_74x164_chip *gpio_to_74x164_chip(struct gpio_chip *gc)
 
 static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
 {
-        struct spi_message message;
-        struct spi_transfer *msg_buf;
-        int i, ret = 0;
-
-        msg_buf = kzalloc(chip->registers * sizeof(struct spi_transfer),
-                        GFP_KERNEL);
-        if (!msg_buf)
-                return -ENOMEM;
-
-        spi_message_init(&message);
-
-        /*
-         * Since the registers are chained, every byte sent will make
-         * the previous byte shift to the next register in the
-         * chain. Thus, the first byte send will end up in the last
-         * register at the end of the transfer. So, to have a logical
-         * numbering, send the bytes in reverse order so that the last
-         * byte of the buffer will end up in the last register.
-         */
-        for (i = chip->registers - 1; i >= 0; i--) {
-                msg_buf[i].tx_buf = chip->buffer +i;
-                msg_buf[i].len = sizeof(u8);
-                spi_message_add_tail(msg_buf + i, &message);
-        }
-
-        ret = spi_sync(chip->spi, &message);
-
-        kfree(msg_buf);
-
-        return ret;
+        return spi_write(chip->spi,
+                         &chip->port_config, sizeof(chip->port_config));
 }
 
 static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
 {
         struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
-        u8 bank = offset / 8;
-        u8 pin = offset % 8;
         int ret;
 
         mutex_lock(&chip->lock);
-        ret = (chip->buffer[bank] >> pin) & 0x1;
+        ret = (chip->port_config >> offset) & 0x1;
         mutex_unlock(&chip->lock);
 
         return ret;
@@ -85,14 +50,12 @@ static void gen_74x164_set_value(struct gpio_chip *gc,
                 unsigned offset, int val)
 {
         struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
-        u8 bank = offset / 8;
-        u8 pin = offset % 8;
 
         mutex_lock(&chip->lock);
         if (val)
-                chip->buffer[bank] |= (1 << pin);
+                chip->port_config |= (1 << offset);
         else
-                chip->buffer[bank] &= ~(1 << pin);
+                chip->port_config &= ~(1 << offset);
 
         __gen_74x164_write_config(chip);
         mutex_unlock(&chip->lock);
@@ -105,14 +68,15 @@ static int gen_74x164_direction_output(struct gpio_chip *gc,
         return 0;
 }
 
-static int gen_74x164_probe(struct spi_device *spi)
+static int __devinit gen_74x164_probe(struct spi_device *spi)
 {
         struct gen_74x164_chip *chip;
         struct gen_74x164_chip_platform_data *pdata;
         int ret;
 
-        if (!spi->dev.of_node) {
-                dev_err(&spi->dev, "No device tree data available.\n");
+        pdata = spi->dev.platform_data;
+        if (!pdata || !pdata->base) {
+                dev_dbg(&spi->dev, "incorrect or missing platform data\n");
                 return -EINVAL;
         }
 
@@ -125,16 +89,10 @@ static int gen_74x164_probe(struct spi_device *spi)
         if (ret < 0)
                 return ret;
 
-        chip = devm_kzalloc(&spi->dev, sizeof(*chip), GFP_KERNEL);
+        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
         if (!chip)
                 return -ENOMEM;
 
-        pdata = spi->dev.platform_data;
-        if (pdata && pdata->base)
-                chip->gpio_chip.base = pdata->base;
-        else
-                chip->gpio_chip.base = -1;
-
         mutex_init(&chip->lock);
 
         dev_set_drvdata(&spi->dev, chip);
@@ -145,20 +103,8 @@ static int gen_74x164_probe(struct spi_device *spi)
         chip->gpio_chip.direction_output = gen_74x164_direction_output;
         chip->gpio_chip.get = gen_74x164_get_value;
         chip->gpio_chip.set = gen_74x164_set_value;
-
-        if (of_property_read_u32(spi->dev.of_node, "registers-number", &chip->registers)) {
-                dev_err(&spi->dev, "Missing registers-number property in the DT.\n");
-                ret = -EINVAL;
-                goto exit_destroy;
-        }
-
-        chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
-        chip->buffer = devm_kzalloc(&spi->dev, chip->registers, GFP_KERNEL);
-        if (!chip->buffer) {
-                ret = -ENOMEM;
-                goto exit_destroy;
-        }
-
+        chip->gpio_chip.base = pdata->base;
+        chip->gpio_chip.ngpio = 8;
         chip->gpio_chip.can_sleep = 1;
         chip->gpio_chip.dev = &spi->dev;
         chip->gpio_chip.owner = THIS_MODULE;
@@ -178,10 +124,11 @@ static int gen_74x164_probe(struct spi_device *spi)
 exit_destroy:
         dev_set_drvdata(&spi->dev, NULL);
         mutex_destroy(&chip->lock);
+        kfree(chip);
         return ret;
 }
 
-static int gen_74x164_remove(struct spi_device *spi)
+static int __devexit gen_74x164_remove(struct spi_device *spi)
 {
         struct gen_74x164_chip *chip;
         int ret;
@@ -193,31 +140,36 @@ static int gen_74x164_remove(struct spi_device *spi)
         dev_set_drvdata(&spi->dev, NULL);
 
         ret = gpiochip_remove(&chip->gpio_chip);
-        if (!ret)
+        if (!ret) {
                 mutex_destroy(&chip->lock);
-        else
+                kfree(chip);
+        } else
                 dev_err(&spi->dev, "Failed to remove the GPIO controller: %d\n",
                                 ret);
 
         return ret;
 }
 
-static const struct of_device_id gen_74x164_dt_ids[] = {
-        { .compatible = "fairchild,74hc595" },
-        {},
-};
-MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
-
 static struct spi_driver gen_74x164_driver = {
         .driver = {
                 .name           = "74x164",
                 .owner          = THIS_MODULE,
-                .of_match_table = of_match_ptr(gen_74x164_dt_ids),
         },
         .probe          = gen_74x164_probe,
-        .remove         = gen_74x164_remove,
+        .remove         = __devexit_p(gen_74x164_remove),
 };
-module_spi_driver(gen_74x164_driver);
+
+static int __init gen_74x164_init(void)
+{
+        return spi_register_driver(&gen_74x164_driver);
+}
+subsys_initcall(gen_74x164_init);
+
+static void __exit gen_74x164_exit(void)
+{
+        spi_unregister_driver(&gen_74x164_driver);
+}
+module_exit(gen_74x164_exit);
 
 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
diff --git a/drivers/gpio/gpio-ab8500.c b/drivers/gpio/gpio-ab8500.c
index 983ad425f0a..050c05d9189 100644
--- a/drivers/gpio/gpio-ab8500.c
+++ b/drivers/gpio/gpio-ab8500.c
@@ -402,7 +402,7 @@ static void ab8500_gpio_irq_remove(struct ab8500_gpio *ab8500_gpio)
         }
 }
 
-static int ab8500_gpio_probe(struct platform_device *pdev)
+static int __devinit ab8500_gpio_probe(struct platform_device *pdev)
 {
         struct ab8500_platform_data *ab8500_pdata =
                                 dev_get_platdata(pdev->dev.parent);
@@ -474,7 +474,7 @@ out_free:
  * ab8500_gpio_remove() - remove Ab8500-gpio driver
  * @pdev :      Platform device registered
  */
-static int ab8500_gpio_remove(struct platform_device *pdev)
+static int __devexit ab8500_gpio_remove(struct platform_device *pdev)
 {
         struct ab8500_gpio *ab8500_gpio = platform_get_drvdata(pdev);
         int ret;
@@ -499,7 +499,7 @@ static struct platform_driver ab8500_gpio_driver = {
                 .owner = THIS_MODULE,
         },
         .probe = ab8500_gpio_probe,
-        .remove = ab8500_gpio_remove,
+        .remove = __devexit_p(ab8500_gpio_remove),
 };
 
 static int __init ab8500_gpio_init(void)
diff --git a/drivers/gpio/gpio-adnp.c b/drivers/gpio/gpio-adnp.c
deleted file mode 100644
index e60567fc507..00000000000
--- a/drivers/gpio/gpio-adnp.c
+++ /dev/null
@@ -1,611 +0,0 @@
-/*
- * Copyright (C) 2011-2012 Avionic Design GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/irqdomain.h>
-#include <linux/module.h>
-#include <linux/of_irq.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-
-#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
-#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
-#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
-#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
-#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
-
-struct adnp {
-        struct i2c_client *client;
-        struct gpio_chip gpio;
-        unsigned int reg_shift;
-
-        struct mutex i2c_lock;
-
-        struct irq_domain *domain;
-        struct mutex irq_lock;
-
-        u8 *irq_enable;
-        u8 *irq_level;
-        u8 *irq_rise;
-        u8 *irq_fall;
-        u8 *irq_high;
-        u8 *irq_low;
-};
-
-static inline struct adnp *to_adnp(struct gpio_chip *chip)
-{
-        return container_of(chip, struct adnp, gpio);
-}
-
-static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
-{
-        int err;
-
-        err = i2c_smbus_read_byte_data(adnp->client, offset);
-        if (err < 0) {
-                dev_err(adnp->gpio.dev, "%s failed: %d\n",
-                        "i2c_smbus_read_byte_data()", err);
-                return err;
-        }
-
-        *value = err;
-        return 0;
-}
-
-static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
-{
-        int err;
-
-        err = i2c_smbus_write_byte_data(adnp->client, offset, value);
-        if (err < 0) {
-                dev_err(adnp->gpio.dev, "%s failed: %d\n",
-                        "i2c_smbus_write_byte_data()", err);
-                return err;
-        }
-
-        return 0;
-}
-
-static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct adnp *adnp = to_adnp(chip);
-        unsigned int reg = offset >> adnp->reg_shift;
-        unsigned int pos = offset & 7;
-        u8 value;
-        int err;
-
-        err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
-        if (err < 0)
-                return err;
-
-        return (value & BIT(pos)) ? 1 : 0;
-}
-
-static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
-{
-        unsigned int reg = offset >> adnp->reg_shift;
-        unsigned int pos = offset & 7;
-        int err;
-        u8 val;
-
-        err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
-        if (err < 0)
-                return;
-
-        if (value)
-                val |= BIT(pos);
-        else
-                val &= ~BIT(pos);
-
-        adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
-}
-
-static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct adnp *adnp = to_adnp(chip);
-
-        mutex_lock(&adnp->i2c_lock);
-        __adnp_gpio_set(adnp, offset, value);
-        mutex_unlock(&adnp->i2c_lock);
-}
-
-static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct adnp *adnp = to_adnp(chip);
-        unsigned int reg = offset >> adnp->reg_shift;
-        unsigned int pos = offset & 7;
-        u8 value;
-        int err;
-
-        mutex_lock(&adnp->i2c_lock);
-
-        err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
-        if (err < 0)
-                goto out;
-
-        value &= ~BIT(pos);
-
-        err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
-        if (err < 0)
-                goto out;
-
-        err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
-        if (err < 0)
-                goto out;
-
-        if (err & BIT(pos))
-                err = -EACCES;
-
-        err = 0;
-
-out:
-        mutex_unlock(&adnp->i2c_lock);
-        return err;
-}
-
-static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                      int value)
-{
-        struct adnp *adnp = to_adnp(chip);
-        unsigned int reg = offset >> adnp->reg_shift;
-        unsigned int pos = offset & 7;
-        int err;
-        u8 val;
-
-        mutex_lock(&adnp->i2c_lock);
-
-        err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
-        if (err < 0)
-                goto out;
-
-        val |= BIT(pos);
-
-        err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
-        if (err < 0)
-                goto out;
-
-        err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
-        if (err < 0)
-                goto out;
-
-        if (!(val & BIT(pos))) {
-                err = -EPERM;
-                goto out;
-        }
-
-        __adnp_gpio_set(adnp, offset, value);
-        err = 0;
-
-out:
-        mutex_unlock(&adnp->i2c_lock);
-        return err;
-}
-
-static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
-        struct adnp *adnp = to_adnp(chip);
-        unsigned int num_regs = 1 << adnp->reg_shift, i, j;
-        int err;
-
-        for (i = 0; i < num_regs; i++) {
-                u8 ddr, plr, ier, isr;
-
-                mutex_lock(&adnp->i2c_lock);
-
-                err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        return;
-                }
-
-                err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        return;
-                }
-
-                err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        return;
-                }
-
-                err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        return;
-                }
-
-                mutex_unlock(&adnp->i2c_lock);
-
-                for (j = 0; j < 8; j++) {
-                        unsigned int bit = (i << adnp->reg_shift) + j;
-                        const char *direction = "input ";
-                        const char *level = "low ";
-                        const char *interrupt = "disabled";
-                        const char *pending = "";
-
-                        if (ddr & BIT(j))
-                                direction = "output";
-
-                        if (plr & BIT(j))
-                                level = "high";
-
-                        if (ier & BIT(j))
-                                interrupt = "enabled ";
-
-                        if (isr & BIT(j))
-                                pending = "pending";
-
-                        seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
-                                   direction, level, interrupt, pending);
-                }
-        }
-}
-
-static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
-{
-        struct gpio_chip *chip = &adnp->gpio;
-
-        adnp->reg_shift = get_count_order(num_gpios) - 3;
-
-        chip->direction_input = adnp_gpio_direction_input;
-        chip->direction_output = adnp_gpio_direction_output;
-        chip->get = adnp_gpio_get;
-        chip->set = adnp_gpio_set;
-        chip->can_sleep = 1;
-
-        if (IS_ENABLED(CONFIG_DEBUG_FS))
-                chip->dbg_show = adnp_gpio_dbg_show;
-
-        chip->base = -1;
-        chip->ngpio = num_gpios;
-        chip->label = adnp->client->name;
-        chip->dev = &adnp->client->dev;
-        chip->of_node = chip->dev->of_node;
-        chip->owner = THIS_MODULE;
-
-        return 0;
-}
-
-static irqreturn_t adnp_irq(int irq, void *data)
-{
-        struct adnp *adnp = data;
-        unsigned int num_regs, i;
-
-        num_regs = 1 << adnp->reg_shift;
-
-        for (i = 0; i < num_regs; i++) {
-                unsigned int base = i << adnp->reg_shift, bit;
-                u8 changed, level, isr, ier;
-                unsigned long pending;
-                int err;
-
-                mutex_lock(&adnp->i2c_lock);
-
-                err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        continue;
-                }
-
-                err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        continue;
-                }
-
-                err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
-                if (err < 0) {
-                        mutex_unlock(&adnp->i2c_lock);
-                        continue;
-                }
-
-                mutex_unlock(&adnp->i2c_lock);
-
-                /* determine pins that changed levels */
-                changed = level ^ adnp->irq_level[i];
-
-                /* compute edge-triggered interrupts */
-                pending = changed & ((adnp->irq_fall[i] & ~level) |
-                                     (adnp->irq_rise[i] & level));
-
-                /* add in level-triggered interrupts */
-                pending |= (adnp->irq_high[i] & level) |
-                           (adnp->irq_low[i] & ~level);
-
-                /* mask out non-pending and disabled interrupts */
-                pending &= isr & ier;
-
-                for_each_set_bit(bit, &pending, 8) {
-                        unsigned int virq;
-                        virq = irq_find_mapping(adnp->domain, base + bit);
-                        handle_nested_irq(virq);
-                }
-        }
-
-        return IRQ_HANDLED;
-}
-
-static int adnp_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct adnp *adnp = to_adnp(chip);
-        return irq_create_mapping(adnp->domain, offset);
-}
-
-static void adnp_irq_mask(struct irq_data *data)
-{
-        struct adnp *adnp = irq_data_get_irq_chip_data(data);
-        unsigned int reg = data->hwirq >> adnp->reg_shift;
-        unsigned int pos = data->hwirq & 7;
-
-        adnp->irq_enable[reg] &= ~BIT(pos);
-}
-
-static void adnp_irq_unmask(struct irq_data *data)
-{
-        struct adnp *adnp = irq_data_get_irq_chip_data(data);
-        unsigned int reg = data->hwirq >> adnp->reg_shift;
-        unsigned int pos = data->hwirq & 7;
-
-        adnp->irq_enable[reg] |= BIT(pos);
-}
-
-static int adnp_irq_set_type(struct irq_data *data, unsigned int type)
-{
-        struct adnp *adnp = irq_data_get_irq_chip_data(data);
-        unsigned int reg = data->hwirq >> adnp->reg_shift;
-        unsigned int pos = data->hwirq & 7;
-
-        if (type & IRQ_TYPE_EDGE_RISING)
-                adnp->irq_rise[reg] |= BIT(pos);
-        else
-                adnp->irq_rise[reg] &= ~BIT(pos);
-
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                adnp->irq_fall[reg] |= BIT(pos);
-        else
-                adnp->irq_fall[reg] &= ~BIT(pos);
-
-        if (type & IRQ_TYPE_LEVEL_HIGH)
-                adnp->irq_high[reg] |= BIT(pos);
-        else
-                adnp->irq_high[reg] &= ~BIT(pos);
-
-        if (type & IRQ_TYPE_LEVEL_LOW)
-                adnp->irq_low[reg] |= BIT(pos);
-        else
-                adnp->irq_low[reg] &= ~BIT(pos);
-
-        return 0;
-}
-
-static void adnp_irq_bus_lock(struct irq_data *data)
-{
-        struct adnp *adnp = irq_data_get_irq_chip_data(data);
-
-        mutex_lock(&adnp->irq_lock);
-}
-
-static void adnp_irq_bus_unlock(struct irq_data *data)
-{
-        struct adnp *adnp = irq_data_get_irq_chip_data(data);
-        unsigned int num_regs = 1 << adnp->reg_shift, i;
-
-        mutex_lock(&adnp->i2c_lock);
-
-        for (i = 0; i < num_regs; i++)
-                adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
-
-        mutex_unlock(&adnp->i2c_lock);
-        mutex_unlock(&adnp->irq_lock);
-}
-
-static struct irq_chip adnp_irq_chip = {
-        .name = "gpio-adnp",
-        .irq_mask = adnp_irq_mask,
-        .irq_unmask = adnp_irq_unmask,
-        .irq_set_type = adnp_irq_set_type,
-        .irq_bus_lock = adnp_irq_bus_lock,
-        .irq_bus_sync_unlock = adnp_irq_bus_unlock,
-};
-
-static int adnp_irq_map(struct irq_domain *domain, unsigned int irq,
-                        irq_hw_number_t hwirq)
-{
-        irq_set_chip_data(irq, domain->host_data);
-        irq_set_chip(irq, &adnp_irq_chip);
-        irq_set_nested_thread(irq, true);
-
-#ifdef CONFIG_ARM
-        set_irq_flags(irq, IRQF_VALID);
-#else
-        irq_set_noprobe(irq);
-#endif
-
-        return 0;
-}
-
-static const struct irq_domain_ops adnp_irq_domain_ops = {
-        .map = adnp_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
-static int adnp_irq_setup(struct adnp *adnp)
-{
-        unsigned int num_regs = 1 << adnp->reg_shift, i;
-        struct gpio_chip *chip = &adnp->gpio;
-        int err;
-
-        mutex_init(&adnp->irq_lock);
-
-        /*
-         * Allocate memory to keep track of the current level and trigger
-         * modes of the interrupts. To avoid multiple allocations, a single
-         * large buffer is allocated and pointers are setup to point at the
-         * corresponding offsets. For consistency, the layout of the buffer
-         * is chosen to match the register layout of the hardware in that
-         * each segment contains the corresponding bits for all interrupts.
-         */
-        adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL);
-        if (!adnp->irq_enable)
-                return -ENOMEM;
-
-        adnp->irq_level = adnp->irq_enable + (num_regs * 1);
-        adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
-        adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
-        adnp->irq_high = adnp->irq_enable + (num_regs * 4);
-        adnp->irq_low = adnp->irq_enable + (num_regs * 5);
-
-        for (i = 0; i < num_regs; i++) {
-                /*
-                 * Read the initial level of all pins to allow the emulation
-                 * of edge triggered interrupts.
-                 */
-                err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
-                if (err < 0)
-                        return err;
-
-                /* disable all interrupts */
-                err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
-                if (err < 0)
-                        return err;
-
-                adnp->irq_enable[i] = 0x00;
-        }
-
-        adnp->domain = irq_domain_add_linear(chip->of_node, chip->ngpio,
-                                             &adnp_irq_domain_ops, adnp);
-
-        err = request_threaded_irq(adnp->client->irq, NULL, adnp_irq,
-                                   IRQF_TRIGGER_RISING | IRQF_ONESHOT,
-                                   dev_name(chip->dev), adnp);
-        if (err != 0) {
-                dev_err(chip->dev, "can't request IRQ#%d: %d\n",
-                        adnp->client->irq, err);
-                goto error;
-        }
-
-        chip->to_irq = adnp_gpio_to_irq;
-        return 0;
-
-error:
-        irq_domain_remove(adnp->domain);
-        return err;
-}
-
-static void adnp_irq_teardown(struct adnp *adnp)
-{
-        unsigned int irq, i;
-
-        free_irq(adnp->client->irq, adnp);
-
-        for (i = 0; i < adnp->gpio.ngpio; i++) {
-                irq = irq_find_mapping(adnp->domain, i);
-                if (irq > 0)
-                        irq_dispose_mapping(irq);
-        }
-
-        irq_domain_remove(adnp->domain);
-}
-
-static int adnp_i2c_probe(struct i2c_client *client,
-                                    const struct i2c_device_id *id)
-{
-        struct device_node *np = client->dev.of_node;
-        struct adnp *adnp;
-        u32 num_gpios;
-        int err;
-
-        err = of_property_read_u32(np, "nr-gpios", &num_gpios);
-        if (err < 0)
-                return err;
-
-        client->irq = irq_of_parse_and_map(np, 0);
-        if (!client->irq)
-                return -EPROBE_DEFER;
-
-        adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
-        if (!adnp)
-                return -ENOMEM;
-
-        mutex_init(&adnp->i2c_lock);
-        adnp->client = client;
-
-        err = adnp_gpio_setup(adnp, num_gpios);
-        if (err < 0)
-                return err;
-
-        if (of_find_property(np, "interrupt-controller", NULL)) {
-                err = adnp_irq_setup(adnp);
-                if (err < 0)
-                        goto teardown;
-        }
-
-        err = gpiochip_add(&adnp->gpio);
-        if (err < 0)
-                goto teardown;
-
-        i2c_set_clientdata(client, adnp);
-        return 0;
-
-teardown:
-        if (of_find_property(np, "interrupt-controller", NULL))
-                adnp_irq_teardown(adnp);
-
-        return err;
-}
-
-static int adnp_i2c_remove(struct i2c_client *client)
-{
-        struct adnp *adnp = i2c_get_clientdata(client);
-        struct device_node *np = client->dev.of_node;
-        int err;
-
-        err = gpiochip_remove(&adnp->gpio);
-        if (err < 0) {
-                dev_err(&client->dev, "%s failed: %d\n", "gpiochip_remove()",
-                        err);
-                return err;
-        }
-
-        if (of_find_property(np, "interrupt-controller", NULL))
-                adnp_irq_teardown(adnp);
-
-        return 0;
-}
-
-static const struct i2c_device_id adnp_i2c_id[] = {
-        { "gpio-adnp" },
-        { },
-};
-MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
-
-static const struct of_device_id adnp_of_match[] = {
-        { .compatible = "ad,gpio-adnp", },
-        { },
-};
-MODULE_DEVICE_TABLE(of, adnp_of_match);
-
-static struct i2c_driver adnp_i2c_driver = {
-        .driver = {
-                .name = "gpio-adnp",
-                .owner = THIS_MODULE,
-                .of_match_table = of_match_ptr(adnp_of_match),
-        },
-        .probe = adnp_i2c_probe,
-        .remove = adnp_i2c_remove,
-        .id_table = adnp_i2c_id,
-};
-module_i2c_driver(adnp_i2c_driver);
-
-MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
-MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-adp5520.c b/drivers/gpio/gpio-adp5520.c
index 8afa95f831b..9f278153700 100644
--- a/drivers/gpio/gpio-adp5520.c
+++ b/drivers/gpio/gpio-adp5520.c
@@ -87,7 +87,7 @@ static int adp5520_gpio_direction_output(struct gpio_chip *chip,
         return ret;
 }
 
-static int adp5520_gpio_probe(struct platform_device *pdev)
+static int __devinit adp5520_gpio_probe(struct platform_device *pdev)
 {
         struct adp5520_gpio_platform_data *pdata = pdev->dev.platform_data;
         struct adp5520_gpio *dev;
@@ -167,7 +167,7 @@ err:
         return ret;
 }
 
-static int adp5520_gpio_remove(struct platform_device *pdev)
+static int __devexit adp5520_gpio_remove(struct platform_device *pdev)
 {
         struct adp5520_gpio *dev;
         int ret;
@@ -190,10 +190,20 @@ static struct platform_driver adp5520_gpio_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe          = adp5520_gpio_probe,
-        .remove         = adp5520_gpio_remove,
+        .remove         = __devexit_p(adp5520_gpio_remove),
 };
 
-module_platform_driver(adp5520_gpio_driver);
+static int __init adp5520_gpio_init(void)
+{
+        return platform_driver_register(&adp5520_gpio_driver);
+}
+module_init(adp5520_gpio_init);
+
+static void __exit adp5520_gpio_exit(void)
+{
+        platform_driver_unregister(&adp5520_gpio_driver);
+}
+module_exit(adp5520_gpio_exit);
 
 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 MODULE_DESCRIPTION("GPIO ADP5520 Driver");
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index 2ba56987db0..3525ad91877 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -252,7 +252,7 @@ static irqreturn_t adp5588_irq_handler(int irq, void *devid)
                 if (ret < 0)
                         memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
 
-                for (bank = 0, bit = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
+                for (bank = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
                         bank++, bit = 0) {
                         pending = dev->irq_stat[bank] & dev->irq_mask[bank];
 
@@ -346,7 +346,7 @@ static void adp5588_irq_teardown(struct adp5588_gpio *dev)
 }
 #endif /* CONFIG_GPIO_ADP5588_IRQ */
 
-static int adp5588_gpio_probe(struct i2c_client *client,
+static int __devinit adp5588_gpio_probe(struct i2c_client *client,
                                         const struct i2c_device_id *id)
 {
         struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
@@ -418,8 +418,9 @@ static int adp5588_gpio_probe(struct i2c_client *client,
         if (ret)
                 goto err_irq;
 
-        dev_info(&client->dev, "IRQ Base: %d Rev.: %d\n",
-                        pdata->irq_base, revid);
+        dev_info(&client->dev, "gpios %d..%d (IRQ Base %d) on a %s Rev. %d\n",
+                        gc->base, gc->base + gc->ngpio - 1,
+                        pdata->irq_base, client->name, revid);
 
         if (pdata->setup) {
                 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
@@ -438,7 +439,7 @@ err:
         return ret;
 }
 
-static int adp5588_gpio_remove(struct i2c_client *client)
+static int __devexit adp5588_gpio_remove(struct i2c_client *client)
 {
         struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
         struct adp5588_gpio *dev = i2c_get_clientdata(client);
@@ -479,11 +480,23 @@ static struct i2c_driver adp5588_gpio_driver = {
                    .name = DRV_NAME,
                    },
         .probe = adp5588_gpio_probe,
-        .remove = adp5588_gpio_remove,
+        .remove = __devexit_p(adp5588_gpio_remove),
         .id_table = adp5588_gpio_id,
 };
 
-module_i2c_driver(adp5588_gpio_driver);
+static int __init adp5588_gpio_init(void)
+{
+        return i2c_add_driver(&adp5588_gpio_driver);
+}
+
+module_init(adp5588_gpio_init);
+
+static void __exit adp5588_gpio_exit(void)
+{
+        i2c_del_driver(&adp5588_gpio_driver);
+}
+
+module_exit(adp5588_gpio_exit);
 
 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 MODULE_DESCRIPTION("GPIO ADP5588 Driver");
diff --git a/drivers/gpio/gpio-amd8111.c b/drivers/gpio/gpio-amd8111.c
deleted file mode 100644
index 710fafcdd1b..00000000000
--- a/drivers/gpio/gpio-amd8111.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * GPIO driver for AMD 8111 south bridges
- *
- * Copyright (c) 2012 Dmitry Eremin-Solenikov
- *
- * Based on the AMD RNG driver:
- * Copyright 2005 (c) MontaVista Software, Inc.
- * with the majority of the code coming from:
- *
- * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
- * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
- *
- * derived from
- *
- * Hardware driver for the AMD 768 Random Number Generator (RNG)
- * (c) Copyright 2001 Red Hat Inc
- *
- * derived from
- *
- * Hardware driver for Intel i810 Random Number Generator (RNG)
- * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
- * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/pci.h>
-#include <linux/spinlock.h>
-
-#define PMBASE_OFFSET 0xb0
-#define PMBASE_SIZE   0x30
-
-#define AMD_REG_GPIO(i) (0x10 + (i))
-
-#define AMD_GPIO_LTCH_STS       0x40 /* Latch status, w1 */
-#define AMD_GPIO_RTIN           0x20 /* Real Time in, ro */
-#define AMD_GPIO_DEBOUNCE       0x10 /* Debounce, rw */
-#define AMD_GPIO_MODE_MASK      0x0c /* Pin Mode Select, rw */
-#define AMD_GPIO_MODE_IN        0x00
-#define AMD_GPIO_MODE_OUT       0x04
-/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
-#define AMD_GPIO_MODE_ALTFN     0x08 /* Or 0x09 */
-#define AMD_GPIO_X_MASK         0x03 /* In/Out specific, rw */
-#define AMD_GPIO_X_IN_ACTIVEHI  0x01 /* Active High */
-#define AMD_GPIO_X_IN_LATCH     0x02 /* Latched version is selected */
-#define AMD_GPIO_X_OUT_LOW      0x00
-#define AMD_GPIO_X_OUT_HI       0x01
-#define AMD_GPIO_X_OUT_CLK0     0x02
-#define AMD_GPIO_X_OUT_CLK1     0x03
-
-/*
- * Data for PCI driver interface
- *
- * This data only exists for exporting the supported
- * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
- * register a pci_driver, because someone else might one day
- * want to register another driver on the same PCI id.
- */
-static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
-        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
-        { 0, }, /* terminate list */
-};
-MODULE_DEVICE_TABLE(pci, pci_tbl);
-
-struct amd_gpio {
-        struct gpio_chip        chip;
-        u32                     pmbase;
-        void __iomem            *pm;
-        struct pci_dev          *pdev;
-        spinlock_t              lock; /* guards hw registers and orig table */
-        u8                      orig[32];
-};
-
-#define to_agp(chip)    container_of(chip, struct amd_gpio, chip)
-
-static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct amd_gpio *agp = to_agp(chip);
-
-        agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
-                (AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
-
-        dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
-
-        return 0;
-}
-
-static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct amd_gpio *agp = to_agp(chip);
-
-        dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
-
-        iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
-}
-
-static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct amd_gpio *agp = to_agp(chip);
-        u8 temp;
-        unsigned long flags;
-
-        spin_lock_irqsave(&agp->lock, flags);
-        temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
-        temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
-        iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
-        spin_unlock_irqrestore(&agp->lock, flags);
-
-        dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
-}
-
-static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct amd_gpio *agp = to_agp(chip);
-        u8 temp;
-
-        temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
-
-        dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
-
-        return (temp & AMD_GPIO_RTIN) ? 1 : 0;
-}
-
-static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct amd_gpio *agp = to_agp(chip);
-        u8 temp;
-        unsigned long flags;
-
-        spin_lock_irqsave(&agp->lock, flags);
-        temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
-        temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
-        iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
-        spin_unlock_irqrestore(&agp->lock, flags);
-
-        dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
-
-        return 0;
-}
-
-static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
-{
-        struct amd_gpio *agp = to_agp(chip);
-        u8 temp;
-        unsigned long flags;
-
-        spin_lock_irqsave(&agp->lock, flags);
-        temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
-        temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
-        iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
-        spin_unlock_irqrestore(&agp->lock, flags);
-
-        dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
-
-        return 0;
-}
-
-static struct amd_gpio gp = {
-        .chip = {
-                .label          = "AMD GPIO",
-                .owner          = THIS_MODULE,
-                .base           = -1,
-                .ngpio          = 32,
-                .request        = amd_gpio_request,
-                .free           = amd_gpio_free,
-                .set            = amd_gpio_set,
-                .get            = amd_gpio_get,
-                .direction_output = amd_gpio_dirout,
-                .direction_input = amd_gpio_dirin,
-        },
-};
-
-static int __init amd_gpio_init(void)
-{
-        int err = -ENODEV;
-        struct pci_dev *pdev = NULL;
-        const struct pci_device_id *ent;
-
-
-        /* We look for our device - AMD South Bridge
-         * I don't know about a system with two such bridges,
-         * so we can assume that there is max. one device.
-         *
-         * We can't use plain pci_driver mechanism,
-         * as the device is really a multiple function device,
-         * main driver that binds to the pci_device is an smbus
-         * driver and have to find & bind to the device this way.
-         */
-        for_each_pci_dev(pdev) {
-                ent = pci_match_id(pci_tbl, pdev);
-                if (ent)
-                        goto found;
-        }
-        /* Device not found. */
-        goto out;
-
-found:
-        err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
-        if (err)
-                goto out;
-        err = -EIO;
-        gp.pmbase &= 0x0000FF00;
-        if (gp.pmbase == 0)
-                goto out;
-        if (!request_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE, "AMD GPIO")) {
-                dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
-                        gp.pmbase + PMBASE_OFFSET);
-                err = -EBUSY;
-                goto out;
-        }
-        gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
-        gp.pdev = pdev;
-        gp.chip.dev = &pdev->dev;
-
-        spin_lock_init(&gp.lock);
-
-        printk(KERN_INFO "AMD-8111 GPIO detected\n");
-        err = gpiochip_add(&gp.chip);
-        if (err) {
-                printk(KERN_ERR "GPIO registering failed (%d)\n",
-                       err);
-                release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
-                goto out;
-        }
-out:
-        return err;
-}
-
-static void __exit amd_gpio_exit(void)
-{
-        int err = gpiochip_remove(&gp.chip);
-        WARN_ON(err);
-        ioport_unmap(gp.pm);
-        release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
-}
-
-module_init(amd_gpio_init);
-module_exit(amd_gpio_exit);
-
-MODULE_AUTHOR("The Linux Kernel team");
-MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-arizona.c b/drivers/gpio/gpio-arizona.c
deleted file mode 100644
index 0ea853f68db..00000000000
--- a/drivers/gpio/gpio-arizona.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * gpiolib support for Wolfson Arizona class devices
- *
- * Copyright 2012 Wolfson Microelectronics PLC.
- *
- * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/seq_file.h>
-
-#include <linux/mfd/arizona/core.h>
-#include <linux/mfd/arizona/pdata.h>
-#include <linux/mfd/arizona/registers.h>
-
-struct arizona_gpio {
-        struct arizona *arizona;
-        struct gpio_chip gpio_chip;
-};
-
-static inline struct arizona_gpio *to_arizona_gpio(struct gpio_chip *chip)
-{
-        return container_of(chip, struct arizona_gpio, gpio_chip);
-}
-
-static int arizona_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
-{
-        struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip);
-        struct arizona *arizona = arizona_gpio->arizona;
-
-        return regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset,
-                                  ARIZONA_GPN_DIR, ARIZONA_GPN_DIR);
-}
-
-static int arizona_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip);
-        struct arizona *arizona = arizona_gpio->arizona;
-        unsigned int val;
-        int ret;
-
-        ret = regmap_read(arizona->regmap, ARIZONA_GPIO1_CTRL + offset, &val);
-        if (ret < 0)
-                return ret;
-
-        if (val & ARIZONA_GPN_LVL)
-                return 1;
-        else
-                return 0;
-}
-
-static int arizona_gpio_direction_out(struct gpio_chip *chip,
-                                     unsigned offset, int value)
-{
-        struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip);
-        struct arizona *arizona = arizona_gpio->arizona;
-
-        if (value)
-                value = ARIZONA_GPN_LVL;
-
-        return regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset,
-                                  ARIZONA_GPN_DIR | ARIZONA_GPN_LVL, value);
-}
-
-static void arizona_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip);
-        struct arizona *arizona = arizona_gpio->arizona;
-
-        if (value)
-                value = ARIZONA_GPN_LVL;
-
-        regmap_update_bits(arizona->regmap, ARIZONA_GPIO1_CTRL + offset,
-                           ARIZONA_GPN_LVL, value);
-}
-
-static struct gpio_chip template_chip = {
-        .label                  = "arizona",
-        .owner                  = THIS_MODULE,
-        .direction_input        = arizona_gpio_direction_in,
-        .get                    = arizona_gpio_get,
-        .direction_output       = arizona_gpio_direction_out,
-        .set                    = arizona_gpio_set,
-        .can_sleep              = 1,
-};
-
-static int arizona_gpio_probe(struct platform_device *pdev)
-{
-        struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
-        struct arizona_pdata *pdata = arizona->dev->platform_data;
-        struct arizona_gpio *arizona_gpio;
-        int ret;
-
-        arizona_gpio = devm_kzalloc(&pdev->dev, sizeof(*arizona_gpio),
-                                    GFP_KERNEL);
-        if (arizona_gpio == NULL)
-                return -ENOMEM;
-
-        arizona_gpio->arizona = arizona;
-        arizona_gpio->gpio_chip = template_chip;
-        arizona_gpio->gpio_chip.dev = &pdev->dev;
-
-        switch (arizona->type) {
-        case WM5102:
-        case WM5110:
-                arizona_gpio->gpio_chip.ngpio = 5;
-                break;
-        default:
-                dev_err(&pdev->dev, "Unknown chip variant %d\n",
-                        arizona->type);
-                return -EINVAL;
-        }
-
-        if (pdata && pdata->gpio_base)
-                arizona_gpio->gpio_chip.base = pdata->gpio_base;
-        else
-                arizona_gpio->gpio_chip.base = -1;
-
-        ret = gpiochip_add(&arizona_gpio->gpio_chip);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
-                        ret);
-                goto err;
-        }
-
-        platform_set_drvdata(pdev, arizona_gpio);
-
-        return ret;
-
-err:
-        return ret;
-}
-
-static int arizona_gpio_remove(struct platform_device *pdev)
-{
-        struct arizona_gpio *arizona_gpio = platform_get_drvdata(pdev);
-
-        return gpiochip_remove(&arizona_gpio->gpio_chip);
-}
-
-static struct platform_driver arizona_gpio_driver = {
-        .driver.name    = "arizona-gpio",
-        .driver.owner   = THIS_MODULE,
-        .probe          = arizona_gpio_probe,
-        .remove         = arizona_gpio_remove,
-};
-
-module_platform_driver(arizona_gpio_driver);
-
-MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
-MODULE_DESCRIPTION("GPIO interface for Arizona devices");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:arizona-gpio");
diff --git a/drivers/gpio/gpio-bt8xx.c b/drivers/gpio/gpio-bt8xx.c
index 7d9d7cb35f2..ec57936aef6 100644
--- a/drivers/gpio/gpio-bt8xx.c
+++ b/drivers/gpio/gpio-bt8xx.c
@@ -50,7 +50,7 @@
 #include <linux/slab.h>
 
 /* Steal the hardware definitions from the bttv driver. */
-#include "../media/pci/bt8xx/bt848.h"
+#include "../media/video/bt8xx/bt848.h"
 
 
 #define BT8XXGPIO_NR_GPIOS              24 /* We have 24 GPIO pins */
@@ -223,6 +223,9 @@ static int bt8xxgpio_probe(struct pci_dev *dev,
                 goto err_release_mem;
         }
 
+        printk(KERN_INFO "bt8xxgpio: Abusing BT8xx card for GPIOs %d to %d\n",
+               bg->gpio.base, bg->gpio.base + BT8XXGPIO_NR_GPIOS - 1);
+
         return 0;
 
 err_release_mem:
@@ -310,7 +313,7 @@ static int bt8xxgpio_resume(struct pci_dev *pdev)
 #define bt8xxgpio_resume NULL
 #endif /* CONFIG_PM */
 
-static DEFINE_PCI_DEVICE_TABLE(bt8xxgpio_pci_tbl) = {
+static struct pci_device_id bt8xxgpio_pci_tbl[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_BROOKTREE, PCI_DEVICE_ID_BT848) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROOKTREE, PCI_DEVICE_ID_BT849) },
         { PCI_DEVICE(PCI_VENDOR_ID_BROOKTREE, PCI_DEVICE_ID_BT878) },
@@ -328,7 +331,17 @@ static struct pci_driver bt8xxgpio_pci_driver = {
         .resume         = bt8xxgpio_resume,
 };
 
-module_pci_driver(bt8xxgpio_pci_driver);
+static int __init bt8xxgpio_init(void)
+{
+        return pci_register_driver(&bt8xxgpio_pci_driver);
+}
+module_init(bt8xxgpio_init)
+
+static void __exit bt8xxgpio_exit(void)
+{
+        pci_unregister_driver(&bt8xxgpio_pci_driver);
+}
+module_exit(bt8xxgpio_exit)
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Michael Buesch");
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
deleted file mode 100644
index ce63b75b13f..00000000000
--- a/drivers/gpio/gpio-clps711x.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- *  CLPS711X GPIO driver
- *
- *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/platform_device.h>
-
-#include <mach/hardware.h>
-
-#define CLPS711X_GPIO_PORTS     5
-#define CLPS711X_GPIO_NAME      "gpio-clps711x"
-
-struct clps711x_gpio {
-        struct gpio_chip        chip[CLPS711X_GPIO_PORTS];
-        spinlock_t              lock;
-};
-
-static void __iomem *clps711x_ports[] = {
-        CLPS711X_VIRT_BASE + PADR,
-        CLPS711X_VIRT_BASE + PBDR,
-        CLPS711X_VIRT_BASE + PCDR,
-        CLPS711X_VIRT_BASE + PDDR,
-        CLPS711X_VIRT_BASE + PEDR,
-};
-
-static void __iomem *clps711x_pdirs[] = {
-        CLPS711X_VIRT_BASE + PADDR,
-        CLPS711X_VIRT_BASE + PBDDR,
-        CLPS711X_VIRT_BASE + PCDDR,
-        CLPS711X_VIRT_BASE + PDDDR,
-        CLPS711X_VIRT_BASE + PEDDR,
-};
-
-#define clps711x_port(x)        clps711x_ports[x->base / 8]
-#define clps711x_pdir(x)        clps711x_pdirs[x->base / 8]
-
-static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
-{
-        return !!(readb(clps711x_port(chip)) & (1 << offset));
-}
-
-static void gpio_clps711x_set(struct gpio_chip *chip, unsigned offset,
-                              int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-}
-
-static int gpio_clps711x_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
-
-static int gpio_clps711x_dir_out(struct gpio_chip *chip, unsigned offset,
-                                 int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
-
-static int gpio_clps711x_dir_in_inv(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
-
-static int gpio_clps711x_dir_out_inv(struct gpio_chip *chip, unsigned offset,
-                                     int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
-
-static struct {
-        char    *name;
-        int     nr;
-        int     inv_dir;
-} clps711x_gpio_ports[] __initconst = {
-        { "PORTA", 8, 0, },
-        { "PORTB", 8, 0, },
-        { "PORTC", 8, 0, },
-        { "PORTD", 8, 1, },
-        { "PORTE", 3, 0, },
-};
-
-static int __init gpio_clps711x_init(void)
-{
-        int i;
-        struct platform_device *pdev;
-        struct clps711x_gpio *gpio;
-
-        pdev = platform_device_alloc(CLPS711X_GPIO_NAME, 0);
-        if (!pdev) {
-                pr_err("Cannot create platform device: %s\n",
-                       CLPS711X_GPIO_NAME);
-                return -ENOMEM;
-        }
-
-        platform_device_add(pdev);
-
-        gpio = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_gpio),
-                            GFP_KERNEL);
-        if (!gpio) {
-                dev_err(&pdev->dev, "GPIO allocating memory error\n");
-                platform_device_unregister(pdev);
-                return -ENOMEM;
-        }
-
-        platform_set_drvdata(pdev, gpio);
-
-        spin_lock_init(&gpio->lock);
-
-        for (i = 0; i < CLPS711X_GPIO_PORTS; i++) {
-                gpio->chip[i].owner             = THIS_MODULE;
-                gpio->chip[i].dev               = &pdev->dev;
-                gpio->chip[i].label             = clps711x_gpio_ports[i].name;
-                gpio->chip[i].base              = i * 8;
-                gpio->chip[i].ngpio             = clps711x_gpio_ports[i].nr;
-                gpio->chip[i].get               = gpio_clps711x_get;
-                gpio->chip[i].set               = gpio_clps711x_set;
-                if (!clps711x_gpio_ports[i].inv_dir) {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out;
-                } else {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in_inv;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out_inv;
-                }
-                WARN_ON(gpiochip_add(&gpio->chip[i]));
-        }
-
-        dev_info(&pdev->dev, "GPIO driver initialized\n");
-
-        return 0;
-}
-arch_initcall(gpio_clps711x_init);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
-MODULE_DESCRIPTION("CLPS711X GPIO driver");
diff --git a/drivers/gpio/gpio-cs5535.c b/drivers/gpio/gpio-cs5535.c
index c0a3aeba6f2..6e16cba56ad 100644
--- a/drivers/gpio/gpio-cs5535.c
+++ b/drivers/gpio/gpio-cs5535.c
@@ -300,7 +300,7 @@ static struct cs5535_gpio_chip cs5535_gpio_chip = {
         },
 };
 
-static int cs5535_gpio_probe(struct platform_device *pdev)
+static int __devinit cs5535_gpio_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int err = -EIO;
@@ -347,6 +347,7 @@ static int cs5535_gpio_probe(struct platform_device *pdev)
         if (err)
                 goto release_region;
 
+        dev_info(&pdev->dev, "GPIO support successfully loaded.\n");
         return 0;
 
 release_region:
@@ -355,7 +356,7 @@ done:
         return err;
 }
 
-static int cs5535_gpio_remove(struct platform_device *pdev)
+static int __devexit cs5535_gpio_remove(struct platform_device *pdev)
 {
         struct resource *r;
         int err;
@@ -378,10 +379,21 @@ static struct platform_driver cs5535_gpio_driver = {
                 .owner = THIS_MODULE,
         },
         .probe = cs5535_gpio_probe,
-        .remove = cs5535_gpio_remove,
+        .remove = __devexit_p(cs5535_gpio_remove),
 };
 
-module_platform_driver(cs5535_gpio_driver);
+static int __init cs5535_gpio_init(void)
+{
+        return platform_driver_register(&cs5535_gpio_driver);
+}
+
+static void __exit cs5535_gpio_exit(void)
+{
+        platform_driver_unregister(&cs5535_gpio_driver);
+}
+
+module_init(cs5535_gpio_init);
+module_exit(cs5535_gpio_exit);
 
 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c
index 29b11e9b6a7..038f5eb8b13 100644
--- a/drivers/gpio/gpio-da9052.c
+++ b/drivers/gpio/gpio-da9052.c
@@ -22,6 +22,7 @@
 #include <linux/mfd/da9052/da9052.h>
 #include <linux/mfd/da9052/reg.h>
 #include <linux/mfd/da9052/pdata.h>
+#include <linux/mfd/da9052/gpio.h>
 
 #define DA9052_INPUT                            1
 #define DA9052_OUTPUT_OPENDRAIN         2
@@ -42,9 +43,6 @@
 #define DA9052_GPIO_MASK_UPPER_NIBBLE           0xF0
 #define DA9052_GPIO_MASK_LOWER_NIBBLE           0x0F
 #define DA9052_GPIO_NIBBLE_SHIFT                4
-#define DA9052_IRQ_GPI0                 16
-#define DA9052_GPIO_ODD_SHIFT                   7
-#define DA9052_GPIO_EVEN_SHIFT                  3
 
 struct da9052_gpio {
         struct da9052 *da9052;
@@ -106,26 +104,33 @@ static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
 static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 {
         struct da9052_gpio *gpio = to_da9052_gpio(gc);
+        unsigned char register_value = 0;
         int ret;
 
         if (da9052_gpio_port_odd(offset)) {
+                if (value) {
+                        register_value = DA9052_GPIO_ODD_PORT_MODE;
                         ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
                                                 DA9052_GPIO_0_1_REG,
                                                 DA9052_GPIO_ODD_PORT_MODE,
-                                                value << DA9052_GPIO_ODD_SHIFT);
+                                                register_value);
                         if (ret != 0)
                                 dev_err(gpio->da9052->dev,
                                         "Failed to updated gpio odd reg,%d",
                                         ret);
+                }
         } else {
+                if (value) {
+                        register_value = DA9052_GPIO_EVEN_PORT_MODE;
                         ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
                                                 DA9052_GPIO_0_1_REG,
                                                 DA9052_GPIO_EVEN_PORT_MODE,
-                                                value << DA9052_GPIO_EVEN_SHIFT);
+                                                register_value);
                         if (ret != 0)
                                 dev_err(gpio->da9052->dev,
                                         "Failed to updated gpio even reg,%d",
                                         ret);
+                }
         }
 }
 
@@ -185,14 +190,10 @@ static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset)
         struct da9052_gpio *gpio = to_da9052_gpio(gc);
         struct da9052 *da9052 = gpio->da9052;
 
-        int irq;
-
-        irq = regmap_irq_get_virq(da9052->irq_data, DA9052_IRQ_GPI0 + offset);
-
-        return irq;
+        return da9052->irq_base + DA9052_IRQ_GPI0 + offset;
 }
 
-static struct gpio_chip reference_gp = {
+static struct gpio_chip reference_gp __devinitdata = {
         .label = "da9052-gpio",
         .owner = THIS_MODULE,
         .get = da9052_gpio_get,
@@ -200,18 +201,18 @@ static struct gpio_chip reference_gp = {
         .direction_input = da9052_gpio_direction_input,
         .direction_output = da9052_gpio_direction_output,
         .to_irq = da9052_gpio_to_irq,
-        .can_sleep = 1,
-        .ngpio = 16,
-        .base = -1,
+        .can_sleep = 1;
+        .ngpio = 16;
+        .base = -1;
 };
 
-static int da9052_gpio_probe(struct platform_device *pdev)
+static int __devinit da9052_gpio_probe(struct platform_device *pdev)
 {
         struct da9052_gpio *gpio;
         struct da9052_pdata *pdata;
         int ret;
 
-        gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+        gpio = kzalloc(sizeof(*gpio), GFP_KERNEL);
         if (gpio == NULL)
                 return -ENOMEM;
 
@@ -225,31 +226,50 @@ static int da9052_gpio_probe(struct platform_device *pdev)
         ret = gpiochip_add(&gpio->gp);
         if (ret < 0) {
                 dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                return ret;
+                goto err_mem;
         }
 
         platform_set_drvdata(pdev, gpio);
 
         return 0;
+
+err_mem:
+        kfree(gpio);
+        return ret;
 }
 
-static int da9052_gpio_remove(struct platform_device *pdev)
+static int __devexit da9052_gpio_remove(struct platform_device *pdev)
 {
         struct da9052_gpio *gpio = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = gpiochip_remove(&gpio->gp);
+        if (ret == 0)
+                kfree(gpio);
 
-        return gpiochip_remove(&gpio->gp);
+        return ret;
 }
 
 static struct platform_driver da9052_gpio_driver = {
         .probe = da9052_gpio_probe,
-        .remove = da9052_gpio_remove,
+        .remove = __devexit_p(da9052_gpio_remove),
         .driver = {
                 .name   = "da9052-gpio",
                 .owner  = THIS_MODULE,
         },
 };
 
-module_platform_driver(da9052_gpio_driver);
+static int __init da9052_gpio_init(void)
+{
+        return platform_driver_register(&da9052_gpio_driver);
+}
+module_init(da9052_gpio_init);
+
+static void __exit da9052_gpio_exit(void)
+{
+        return platform_driver_unregister(&da9052_gpio_driver);
+}
+module_exit(da9052_gpio_exit);
 
 MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
 MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
diff --git a/drivers/gpio/gpio-da9055.c b/drivers/gpio/gpio-da9055.c
deleted file mode 100644
index fd6dfe382f1..00000000000
--- a/drivers/gpio/gpio-da9055.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * GPIO Driver for Dialog DA9055 PMICs.
- *
- * Copyright(c) 2012 Dialog Semiconductor Ltd.
- *
- * Author: David Dajun Chen <dchen@diasemi.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <linux/mfd/da9055/core.h>
-#include <linux/mfd/da9055/reg.h>
-#include <linux/mfd/da9055/pdata.h>
-
-#define DA9055_VDD_IO                   0x0
-#define DA9055_PUSH_PULL                0x3
-#define DA9055_ACT_LOW                  0x0
-#define DA9055_GPI                      0x1
-#define DA9055_PORT_MASK                0x3
-#define DA9055_PORT_SHIFT(offset)       (4 * (offset % 2))
-
-#define DA9055_INPUT                    DA9055_GPI
-#define DA9055_OUTPUT                   DA9055_PUSH_PULL
-#define DA9055_IRQ_GPI0                 3
-
-struct da9055_gpio {
-        struct da9055 *da9055;
-        struct gpio_chip gp;
-};
-
-static inline struct da9055_gpio *to_da9055_gpio(struct gpio_chip *chip)
-{
-        return container_of(chip, struct da9055_gpio, gp);
-}
-
-static int da9055_gpio_get(struct gpio_chip *gc, unsigned offset)
-{
-        struct da9055_gpio *gpio = to_da9055_gpio(gc);
-        int gpio_direction = 0;
-        int ret;
-
-        /* Get GPIO direction */
-        ret = da9055_reg_read(gpio->da9055, (offset >> 1) + DA9055_REG_GPIO0_1);
-        if (ret < 0)
-                return ret;
-
-        gpio_direction = ret & (DA9055_PORT_MASK) << DA9055_PORT_SHIFT(offset);
-        gpio_direction >>= DA9055_PORT_SHIFT(offset);
-        switch (gpio_direction) {
-        case DA9055_INPUT:
-                ret = da9055_reg_read(gpio->da9055, DA9055_REG_STATUS_B);
-                if (ret < 0)
-                        return ret;
-                break;
-        case DA9055_OUTPUT:
-                ret = da9055_reg_read(gpio->da9055, DA9055_REG_GPIO_MODE0_2);
-                if (ret < 0)
-                        return ret;
-        }
-
-        return ret & (1 << offset);
-
-}
-
-static void da9055_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
-{
-        struct da9055_gpio *gpio = to_da9055_gpio(gc);
-
-        da9055_reg_update(gpio->da9055,
-                        DA9055_REG_GPIO_MODE0_2,
-                        1 << offset,
-                        value << offset);
-}
-
-static int da9055_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
-{
-        struct da9055_gpio *gpio = to_da9055_gpio(gc);
-        unsigned char reg_byte;
-
-        reg_byte = (DA9055_ACT_LOW | DA9055_GPI)
-                                << DA9055_PORT_SHIFT(offset);
-
-        return da9055_reg_update(gpio->da9055, (offset >> 1) +
-                                DA9055_REG_GPIO0_1,
-                                DA9055_PORT_MASK <<
-                                DA9055_PORT_SHIFT(offset),
-                                reg_byte);
-}
-
-static int da9055_gpio_direction_output(struct gpio_chip *gc,
-                                        unsigned offset, int value)
-{
-        struct da9055_gpio *gpio = to_da9055_gpio(gc);
-        unsigned char reg_byte;
-        int ret;
-
-        reg_byte = (DA9055_VDD_IO | DA9055_PUSH_PULL)
-                                        << DA9055_PORT_SHIFT(offset);
-
-        ret = da9055_reg_update(gpio->da9055, (offset >> 1) +
-                                DA9055_REG_GPIO0_1,
-                                DA9055_PORT_MASK <<
-                                DA9055_PORT_SHIFT(offset),
-                                reg_byte);
-        if (ret < 0)
-                return ret;
-
-        da9055_gpio_set(gc, offset, value);
-
-        return 0;
-}
-
-static int da9055_gpio_to_irq(struct gpio_chip *gc, u32 offset)
-{
-        struct da9055_gpio *gpio = to_da9055_gpio(gc);
-        struct da9055 *da9055 = gpio->da9055;
-
-        return regmap_irq_get_virq(da9055->irq_data,
-                                  DA9055_IRQ_GPI0 + offset);
-}
-
-static struct gpio_chip reference_gp = {
-        .label = "da9055-gpio",
-        .owner = THIS_MODULE,
-        .get = da9055_gpio_get,
-        .set = da9055_gpio_set,
-        .direction_input = da9055_gpio_direction_input,
-        .direction_output = da9055_gpio_direction_output,
-        .to_irq = da9055_gpio_to_irq,
-        .can_sleep = 1,
-        .ngpio = 3,
-        .base = -1,
-};
-
-static int da9055_gpio_probe(struct platform_device *pdev)
-{
-        struct da9055_gpio *gpio;
-        struct da9055_pdata *pdata;
-        int ret;
-
-        gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
-        if (gpio == NULL)
-                return -ENOMEM;
-
-        gpio->da9055 = dev_get_drvdata(pdev->dev.parent);
-        pdata = gpio->da9055->dev->platform_data;
-
-        gpio->gp = reference_gp;
-        if (pdata && pdata->gpio_base)
-                gpio->gp.base = pdata->gpio_base;
-
-        ret = gpiochip_add(&gpio->gp);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                goto err_mem;
-        }
-
-        platform_set_drvdata(pdev, gpio);
-
-        return 0;
-
-err_mem:
-        return ret;
-}
-
-static int da9055_gpio_remove(struct platform_device *pdev)
-{
-        struct da9055_gpio *gpio = platform_get_drvdata(pdev);
-
-        return gpiochip_remove(&gpio->gp);
-}
-
-static struct platform_driver da9055_gpio_driver = {
-        .probe = da9055_gpio_probe,
-        .remove = da9055_gpio_remove,
-        .driver = {
-                .name   = "da9055-gpio",
-                .owner  = THIS_MODULE,
-        },
-};
-
-static int __init da9055_gpio_init(void)
-{
-        return platform_driver_register(&da9055_gpio_driver);
-}
-subsys_initcall(da9055_gpio_init);
-
-static void __exit da9055_gpio_exit(void)
-{
-        platform_driver_unregister(&da9055_gpio_driver);
-}
-module_exit(da9055_gpio_exit);
-
-MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
-MODULE_DESCRIPTION("DA9055 GPIO Device Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:da9055-gpio");
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
deleted file mode 100644
index 17df6db5dca..00000000000
--- a/drivers/gpio/gpio-davinci.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * TI DaVinci GPIO Support
- *
- * Copyright (c) 2006-2007 David Brownell
- * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/mach/irq.h>
-
-struct davinci_gpio_regs {
-        u32     dir;
-        u32     out_data;
-        u32     set_data;
-        u32     clr_data;
-        u32     in_data;
-        u32     set_rising;
-        u32     clr_rising;
-        u32     set_falling;
-        u32     clr_falling;
-        u32     intstat;
-};
-
-#define chip2controller(chip)   \
-        container_of(chip, struct davinci_gpio_controller, chip)
-
-static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
-static void __iomem *gpio_base;
-
-static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
-{
-        void __iomem *ptr;
-
-        if (gpio < 32 * 1)
-                ptr = gpio_base + 0x10;
-        else if (gpio < 32 * 2)
-                ptr = gpio_base + 0x38;
-        else if (gpio < 32 * 3)
-                ptr = gpio_base + 0x60;
-        else if (gpio < 32 * 4)
-                ptr = gpio_base + 0x88;
-        else if (gpio < 32 * 5)
-                ptr = gpio_base + 0xb0;
-        else
-                ptr = NULL;
-        return ptr;
-}
-
-static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
-{
-        struct davinci_gpio_regs __iomem *g;
-
-        g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
-
-        return g;
-}
-
-static int __init davinci_gpio_irq_setup(void);
-
-/*--------------------------------------------------------------------------*/
-
-/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
-static inline int __davinci_direction(struct gpio_chip *chip,
-                        unsigned offset, bool out, int value)
-{
-        struct davinci_gpio_controller *d = chip2controller(chip);
-        struct davinci_gpio_regs __iomem *g = d->regs;
-        unsigned long flags;
-        u32 temp;
-        u32 mask = 1 << offset;
-
-        spin_lock_irqsave(&d->lock, flags);
-        temp = __raw_readl(&g->dir);
-        if (out) {
-                temp &= ~mask;
-                __raw_writel(mask, value ? &g->set_data : &g->clr_data);
-        } else {
-                temp |= mask;
-        }
-        __raw_writel(temp, &g->dir);
-        spin_unlock_irqrestore(&d->lock, flags);
-
-        return 0;
-}
-
-static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
-{
-        return __davinci_direction(chip, offset, false, 0);
-}
-
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-        return __davinci_direction(chip, offset, true, value);
-}
-
-/*
- * Read the pin's value (works even if it's set up as output);
- * returns zero/nonzero.
- *
- * Note that changes are synched to the GPIO clock, so reading values back
- * right after you've set them may give old values.
- */
-static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *d = chip2controller(chip);
-        struct davinci_gpio_regs __iomem *g = d->regs;
-
-        return (1 << offset) & __raw_readl(&g->in_data);
-}
-
-/*
- * Assuming the pin is muxed as a gpio output, set its output value.
- */
-static void
-davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct davinci_gpio_controller *d = chip2controller(chip);
-        struct davinci_gpio_regs __iomem *g = d->regs;
-
-        __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
-}
-
-static int __init davinci_gpio_setup(void)
-{
-        int i, base;
-        unsigned ngpio;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct davinci_gpio_regs *regs;
-
-        if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
-                return 0;
-
-        /*
-         * The gpio banks conceptually expose a segmented bitmap,
-         * and "ngpio" is one more than the largest zero-based
-         * bit index that's valid.
-         */
-        ngpio = soc_info->gpio_num;
-        if (ngpio == 0) {
-                pr_err("GPIO setup:  how many GPIOs?\n");
-                return -EINVAL;
-        }
-
-        if (WARN_ON(DAVINCI_N_GPIO < ngpio))
-                ngpio = DAVINCI_N_GPIO;
-
-        gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
-        if (WARN_ON(!gpio_base))
-                return -ENOMEM;
-
-        for (i = 0, base = 0; base < ngpio; i++, base += 32) {
-                chips[i].chip.label = "DaVinci";
-
-                chips[i].chip.direction_input = davinci_direction_in;
-                chips[i].chip.get = davinci_gpio_get;
-                chips[i].chip.direction_output = davinci_direction_out;
-                chips[i].chip.set = davinci_gpio_set;
-
-                chips[i].chip.base = base;
-                chips[i].chip.ngpio = ngpio - base;
-                if (chips[i].chip.ngpio > 32)
-                        chips[i].chip.ngpio = 32;
-
-                spin_lock_init(&chips[i].lock);
-
-                regs = gpio2regs(base);
-                chips[i].regs = regs;
-                chips[i].set_data = &regs->set_data;
-                chips[i].clr_data = &regs->clr_data;
-                chips[i].in_data = &regs->in_data;
-
-                gpiochip_add(&chips[i].chip);
-        }
-
-        soc_info->gpio_ctlrs = chips;
-        soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
-
-        davinci_gpio_irq_setup();
-        return 0;
-}
-pure_initcall(davinci_gpio_setup);
-
-/*--------------------------------------------------------------------------*/
-/*
- * We expect irqs will normally be set up as input pins, but they can also be
- * used as output pins ... which is convenient for testing.
- *
- * NOTE:  The first few GPIOs also have direct INTC hookups in addition
- * to their GPIOBNK0 irq, with a bit less overhead.
- *
- * All those INTC hookups (direct, plus several IRQ banks) can also
- * serve as EDMA event triggers.
- */
-
-static void gpio_irq_disable(struct irq_data *d)
-{
-        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_handler_data(d);
-
-        __raw_writel(mask, &g->clr_falling);
-        __raw_writel(mask, &g->clr_rising);
-}
-
-static void gpio_irq_enable(struct irq_data *d)
-{
-        struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_handler_data(d);
-        unsigned status = irqd_get_trigger_type(d);
-
-        status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
-        if (!status)
-                status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
-
-        if (status & IRQ_TYPE_EDGE_FALLING)
-                __raw_writel(mask, &g->set_falling);
-        if (status & IRQ_TYPE_EDGE_RISING)
-                __raw_writel(mask, &g->set_rising);
-}
-
-static int gpio_irq_type(struct irq_data *d, unsigned trigger)
-{
-        if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                return -EINVAL;
-
-        return 0;
-}
-
-static struct irq_chip gpio_irqchip = {
-        .name           = "GPIO",
-        .irq_enable     = gpio_irq_enable,
-        .irq_disable    = gpio_irq_disable,
-        .irq_set_type   = gpio_irq_type,
-        .flags          = IRQCHIP_SET_TYPE_MASKED,
-};
-
-static void
-gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-{
-        struct davinci_gpio_regs __iomem *g;
-        u32 mask = 0xffff;
-        struct davinci_gpio_controller *d;
-
-        d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
-        g = (struct davinci_gpio_regs __iomem *)d->regs;
-
-        /* we only care about one bank */
-        if (irq & 1)
-                mask <<= 16;
-
-        /* temporarily mask (level sensitive) parent IRQ */
-        desc->irq_data.chip->irq_mask(&desc->irq_data);
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        while (1) {
-                u32             status;
-                int             n;
-                int             res;
-
-                /* ack any irqs */
-                status = __raw_readl(&g->intstat) & mask;
-                if (!status)
-                        break;
-                __raw_writel(status, &g->intstat);
-
-                /* now demux them to the right lowlevel handler */
-                n = d->irq_base;
-                if (irq & 1) {
-                        n += 16;
-                        status >>= 16;
-                }
-
-                while (status) {
-                        res = ffs(status);
-                        n += res;
-                        generic_handle_irq(n - 1);
-                        status >>= res;
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-        /* now it may re-trigger */
-}
-
-static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *d = chip2controller(chip);
-
-        if (d->irq_base >= 0)
-                return d->irq_base + offset;
-        else
-                return -ENODEV;
-}
-
-static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-        /* NOTE:  we assume for now that only irqs in the first gpio_chip
-         * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
-         */
-        if (offset < soc_info->gpio_unbanked)
-                return soc_info->gpio_irq + offset;
-        else
-                return -ENODEV;
-}
-
-static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
-{
-        struct davinci_gpio_controller *d;
-        struct davinci_gpio_regs __iomem *g;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        u32 mask;
-
-        d = (struct davinci_gpio_controller *)data->handler_data;
-        g = (struct davinci_gpio_regs __iomem *)d->regs;
-        mask = __gpio_mask(data->irq - soc_info->gpio_irq);
-
-        if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                return -EINVAL;
-
-        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
-                     ? &g->set_falling : &g->clr_falling);
-        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
-                     ? &g->set_rising : &g->clr_rising);
-
-        return 0;
-}
-
-/*
- * NOTE:  for suspend/resume, probably best to make a platform_device with
- * suspend_late/resume_resume calls hooking into results of the set_wake()
- * calls ... so if no gpios are wakeup events the clock can be disabled,
- * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
- * (dm6446) can be set appropriately for GPIOV33 pins.
- */
-
-static int __init davinci_gpio_irq_setup(void)
-{
-        unsigned        gpio, irq, bank;
-        struct clk      *clk;
-        u32             binten = 0;
-        unsigned        ngpio, bank_irq;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct davinci_gpio_regs        __iomem *g;
-
-        ngpio = soc_info->gpio_num;
-
-        bank_irq = soc_info->gpio_irq;
-        if (bank_irq == 0) {
-                printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
-                return -EINVAL;
-        }
-
-        clk = clk_get(NULL, "gpio");
-        if (IS_ERR(clk)) {
-                printk(KERN_ERR "Error %ld getting gpio clock?\n",
-                       PTR_ERR(clk));
-                return PTR_ERR(clk);
-        }
-        clk_prepare_enable(clk);
-
-        /* Arrange gpio_to_irq() support, handling either direct IRQs or
-         * banked IRQs.  Having GPIOs in the first GPIO bank use direct
-         * IRQs, while the others use banked IRQs, would need some setup
-         * tweaks to recognize hardware which can do that.
-         */
-        for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
-                chips[bank].chip.to_irq = gpio_to_irq_banked;
-                chips[bank].irq_base = soc_info->gpio_unbanked
-                        ? -EINVAL
-                        : (soc_info->intc_irq_num + gpio);
-        }
-
-        /*
-         * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
-         * controller only handling trigger modes.  We currently assume no
-         * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
-         */
-        if (soc_info->gpio_unbanked) {
-                static struct irq_chip_type gpio_unbanked;
-
-                /* pass "bank 0" GPIO IRQs to AINTC */
-                chips[0].chip.to_irq = gpio_to_irq_unbanked;
-                binten = BIT(0);
-
-                /* AINTC handles mask/unmask; GPIO handles triggering */
-                irq = bank_irq;
-                gpio_unbanked = *container_of(irq_get_chip(irq),
-                                              struct irq_chip_type, chip);
-                gpio_unbanked.chip.name = "GPIO-AINTC";
-                gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
-
-                /* default trigger: both edges */
-                g = gpio2regs(0);
-                __raw_writel(~0, &g->set_falling);
-                __raw_writel(~0, &g->set_rising);
-
-                /* set the direct IRQs up to use that irqchip */
-                for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
-                        irq_set_chip(irq, &gpio_unbanked.chip);
-                        irq_set_handler_data(irq, &chips[gpio / 32]);
-                        irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
-                }
-
-                goto done;
-        }
-
-        /*
-         * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
-         * then chain through our own handler.
-         */
-        for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
-                        gpio < ngpio;
-                        bank++, bank_irq++) {
-                unsigned                i;
-
-                /* disabled by default, enabled only as needed */
-                g = gpio2regs(gpio);
-                __raw_writel(~0, &g->clr_falling);
-                __raw_writel(~0, &g->clr_rising);
-
-                /* set up all irqs in this bank */
-                irq_set_chained_handler(bank_irq, gpio_irq_handler);
-
-                /*
-                 * Each chip handles 32 gpios, and each irq bank consists of 16
-                 * gpio irqs. Pass the irq bank's corresponding controller to
-                 * the chained irq handler.
-                 */
-                irq_set_handler_data(bank_irq, &chips[gpio / 32]);
-
-                for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
-                        irq_set_chip(irq, &gpio_irqchip);
-                        irq_set_chip_data(irq, (__force void *)g);
-                        irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
-                        irq_set_handler(irq, handle_simple_irq);
-                        set_irq_flags(irq, IRQF_VALID);
-                }
-
-                binten |= BIT(bank);
-        }
-
-done:
-        /* BINTEN -- per-bank interrupt enable. genirq would also let these
-         * bits be set/cleared dynamically.
-         */
-        __raw_writel(binten, gpio_base + 0x08);
-
-        printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
-
-        return 0;
-}
diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
deleted file mode 100644
index bdc8302e711..00000000000
--- a/drivers/gpio/gpio-em.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * Emma Mobile GPIO Support - GIO
- *
- *  Copyright (C) 2012 Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/platform_data/gpio-em.h>
-
-struct em_gio_priv {
-        void __iomem *base0;
-        void __iomem *base1;
-        spinlock_t sense_lock;
-        struct platform_device *pdev;
-        struct gpio_chip gpio_chip;
-        struct irq_chip irq_chip;
-        struct irq_domain *irq_domain;
-};
-
-#define GIO_E1 0x00
-#define GIO_E0 0x04
-#define GIO_EM 0x04
-#define GIO_OL 0x08
-#define GIO_OH 0x0c
-#define GIO_I 0x10
-#define GIO_IIA 0x14
-#define GIO_IEN 0x18
-#define GIO_IDS 0x1c
-#define GIO_IIM 0x1c
-#define GIO_RAW 0x20
-#define GIO_MST 0x24
-#define GIO_IIR 0x28
-
-#define GIO_IDT0 0x40
-#define GIO_IDT1 0x44
-#define GIO_IDT2 0x48
-#define GIO_IDT3 0x4c
-#define GIO_RAWBL 0x50
-#define GIO_RAWBH 0x54
-#define GIO_IRBL 0x58
-#define GIO_IRBH 0x5c
-
-#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
-
-static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
-{
-        if (offs < GIO_IDT0)
-                return ioread32(p->base0 + offs);
-        else
-                return ioread32(p->base1 + (offs - GIO_IDT0));
-}
-
-static inline void em_gio_write(struct em_gio_priv *p, int offs,
-                                unsigned long value)
-{
-        if (offs < GIO_IDT0)
-                iowrite32(value, p->base0 + offs);
-        else
-                iowrite32(value, p->base1 + (offs - GIO_IDT0));
-}
-
-static void em_gio_irq_disable(struct irq_data *d)
-{
-        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
-
-        em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
-}
-
-static void em_gio_irq_enable(struct irq_data *d)
-{
-        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
-
-        em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
-}
-
-#define GIO_ASYNC(x) (x + 8)
-
-static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
-        [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
-        [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
-        [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
-        [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
-        [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
-};
-
-static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
-{
-        unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
-        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
-        unsigned int reg, offset, shift;
-        unsigned long flags;
-        unsigned long tmp;
-
-        if (!value)
-                return -EINVAL;
-
-        offset = irqd_to_hwirq(d);
-
-        pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
-
-        /* 8 x 4 bit fields in 4 IDT registers */
-        reg = GIO_IDT(offset >> 3);
-        shift = (offset & 0x07) << 4;
-
-        spin_lock_irqsave(&p->sense_lock, flags);
-
-        /* disable the interrupt in IIA */
-        tmp = em_gio_read(p, GIO_IIA);
-        tmp &= ~BIT(offset);
-        em_gio_write(p, GIO_IIA, tmp);
-
-        /* change the sense setting in IDT */
-        tmp = em_gio_read(p, reg);
-        tmp &= ~(0xf << shift);
-        tmp |= value << shift;
-        em_gio_write(p, reg, tmp);
-
-        /* clear pending interrupts */
-        em_gio_write(p, GIO_IIR, BIT(offset));
-
-        /* enable the interrupt in IIA */
-        tmp = em_gio_read(p, GIO_IIA);
-        tmp |= BIT(offset);
-        em_gio_write(p, GIO_IIA, tmp);
-
-        spin_unlock_irqrestore(&p->sense_lock, flags);
-
-        return 0;
-}
-
-static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
-{
-        struct em_gio_priv *p = dev_id;
-        unsigned long pending;
-        unsigned int offset, irqs_handled = 0;
-
-        while ((pending = em_gio_read(p, GIO_MST))) {
-                offset = __ffs(pending);
-                em_gio_write(p, GIO_IIR, BIT(offset));
-                generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
-                irqs_handled++;
-        }
-
-        return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
-}
-
-static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
-{
-        return container_of(chip, struct em_gio_priv, gpio_chip);
-}
-
-static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
-        return 0;
-}
-
-static int em_gio_get(struct gpio_chip *chip, unsigned offset)
-{
-        return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
-}
-
-static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
-                         unsigned shift, int value)
-{
-        /* upper 16 bits contains mask and lower 16 actual value */
-        em_gio_write(gpio_to_priv(chip), reg,
-                     (1 << (shift + 16)) | (value << shift));
-}
-
-static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        /* output is split into two registers */
-        if (offset < 16)
-                __em_gio_set(chip, GIO_OL, offset, value);
-        else
-                __em_gio_set(chip, GIO_OH, offset - 16, value);
-}
-
-static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                   int value)
-{
-        /* write GPIO value to output before selecting output mode of pin */
-        em_gio_set(chip, offset, value);
-        em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
-        return 0;
-}
-
-static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
-}
-
-static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
-                                 irq_hw_number_t hw)
-{
-        struct em_gio_priv *p = h->host_data;
-
-        pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
-
-        irq_set_chip_data(virq, h->host_data);
-        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
-        set_irq_flags(virq, IRQF_VALID); /* kill me now */
-        return 0;
-}
-
-static struct irq_domain_ops em_gio_irq_domain_ops = {
-        .map    = em_gio_irq_domain_map,
-};
-
-static int em_gio_probe(struct platform_device *pdev)
-{
-        struct gpio_em_config *pdata = pdev->dev.platform_data;
-        struct em_gio_priv *p;
-        struct resource *io[2], *irq[2];
-        struct gpio_chip *gpio_chip;
-        struct irq_chip *irq_chip;
-        const char *name = dev_name(&pdev->dev);
-        int ret;
-
-        p = kzalloc(sizeof(*p), GFP_KERNEL);
-        if (!p) {
-                dev_err(&pdev->dev, "failed to allocate driver data\n");
-                ret = -ENOMEM;
-                goto err0;
-        }
-
-        p->pdev = pdev;
-        platform_set_drvdata(pdev, p);
-        spin_lock_init(&p->sense_lock);
-
-        io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-
-        if (!io[0] || !io[1] || !irq[0] || !irq[1] || !pdata) {
-                dev_err(&pdev->dev, "missing IRQ, IOMEM or configuration\n");
-                ret = -EINVAL;
-                goto err1;
-        }
-
-        p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0]));
-        if (!p->base0) {
-                dev_err(&pdev->dev, "failed to remap low I/O memory\n");
-                ret = -ENXIO;
-                goto err1;
-        }
-
-        p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1]));
-        if (!p->base1) {
-                dev_err(&pdev->dev, "failed to remap high I/O memory\n");
-                ret = -ENXIO;
-                goto err2;
-        }
-
-        gpio_chip = &p->gpio_chip;
-        gpio_chip->direction_input = em_gio_direction_input;
-        gpio_chip->get = em_gio_get;
-        gpio_chip->direction_output = em_gio_direction_output;
-        gpio_chip->set = em_gio_set;
-        gpio_chip->to_irq = em_gio_to_irq;
-        gpio_chip->label = name;
-        gpio_chip->owner = THIS_MODULE;
-        gpio_chip->base = pdata->gpio_base;
-        gpio_chip->ngpio = pdata->number_of_pins;
-
-        irq_chip = &p->irq_chip;
-        irq_chip->name = name;
-        irq_chip->irq_mask = em_gio_irq_disable;
-        irq_chip->irq_unmask = em_gio_irq_enable;
-        irq_chip->irq_enable = em_gio_irq_enable;
-        irq_chip->irq_disable = em_gio_irq_disable;
-        irq_chip->irq_set_type = em_gio_irq_set_type;
-        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
-
-        p->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
-                                              pdata->number_of_pins,
-                                              &em_gio_irq_domain_ops, p);
-        if (!p->irq_domain) {
-                ret = -ENXIO;
-                dev_err(&pdev->dev, "cannot initialize irq domain\n");
-                goto err3;
-        }
-
-        if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) {
-                dev_err(&pdev->dev, "failed to request low IRQ\n");
-                ret = -ENOENT;
-                goto err4;
-        }
-
-        if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) {
-                dev_err(&pdev->dev, "failed to request high IRQ\n");
-                ret = -ENOENT;
-                goto err5;
-        }
-
-        ret = gpiochip_add(gpio_chip);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to add GPIO controller\n");
-                goto err6;
-        }
-        return 0;
-
-err6:
-        free_irq(irq[1]->start, pdev);
-err5:
-        free_irq(irq[0]->start, pdev);
-err4:
-        irq_domain_remove(p->irq_domain);
-err3:
-        iounmap(p->base1);
-err2:
-        iounmap(p->base0);
-err1:
-        kfree(p);
-err0:
-        return ret;
-}
-
-static int em_gio_remove(struct platform_device *pdev)
-{
-        struct em_gio_priv *p = platform_get_drvdata(pdev);
-        struct resource *irq[2];
-        int ret;
-
-        ret = gpiochip_remove(&p->gpio_chip);
-        if (ret)
-                return ret;
-
-        irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-
-        free_irq(irq[1]->start, pdev);
-        free_irq(irq[0]->start, pdev);
-        irq_domain_remove(p->irq_domain);
-        iounmap(p->base1);
-        iounmap(p->base0);
-        kfree(p);
-        return 0;
-}
-
-static struct platform_driver em_gio_device_driver = {
-        .probe          = em_gio_probe,
-        .remove         = em_gio_remove,
-        .driver         = {
-                .name   = "em_gio",
-        }
-};
-
-module_platform_driver(em_gio_device_driver);
-
-MODULE_AUTHOR("Magnus Damm");
-MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 56b98eebe1f..72fb9c66532 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -12,8 +12,9 @@
  *  published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -22,9 +23,6 @@
 #include <linux/basic_mmio_gpio.h>
 
 #include <mach/hardware.h>
-#include <mach/gpio-ep93xx.h>
-
-#define irq_to_gpio(irq)        ((irq) - gpio_to_irq(0))
 
 struct ep93xx_gpio {
         void __iomem            *mmio_base;
@@ -63,6 +61,11 @@ static void ep93xx_gpio_update_int_params(unsigned port)
                 EP93XX_GPIO_REG(int_en_register_offset[port]));
 }
 
+static inline void ep93xx_gpio_int_mask(unsigned line)
+{
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+}
+
 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
 {
         int line = irq_to_gpio(irq);
@@ -205,6 +208,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
                 handler = handle_edge_irq;
                 break;
         default:
+                pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
                 return -EINVAL;
         }
 
@@ -303,21 +307,6 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
         return 0;
 }
 
-/*
- * Map GPIO A0..A7  (0..7)  to irq 64..71,
- *          B0..B7  (7..15) to irq 72..79, and
- *          F0..F7 (16..24) to irq 80..87.
- */
-static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        int gpio = chip->base + offset;
-
-        if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
-                return -EINVAL;
-
-        return 64 + gpio;
-}
-
 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
         void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
 {
@@ -325,22 +314,20 @@ static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
         void __iomem *dir =  mmio_base + bank->dir;
         int err;
 
-        err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
+        err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
         if (err)
                 return err;
 
         bgc->gc.label = bank->label;
         bgc->gc.base = bank->base;
 
-        if (bank->has_debounce) {
+        if (bank->has_debounce)
                 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
-                bgc->gc.to_irq = ep93xx_gpio_to_irq;
-        }
 
         return gpiochip_add(&bgc->gc);
 }
 
-static int ep93xx_gpio_probe(struct platform_device *pdev)
+static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
 {
         struct ep93xx_gpio *ep93xx_gpio;
         struct resource *res;
@@ -370,6 +357,13 @@ static int ep93xx_gpio_probe(struct platform_device *pdev)
         }
         ep93xx_gpio->mmio_base = mmio;
 
+        /* Default all ports to GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+                               EP93XX_SYSCON_DEVCFG_GONK |
+                               EP93XX_SYSCON_DEVCFG_EONIDE |
+                               EP93XX_SYSCON_DEVCFG_GONIDE |
+                               EP93XX_SYSCON_DEVCFG_HONIDE);
+
         for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
                 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
                 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
diff --git a/drivers/gpio/gpio-ge.c b/drivers/gpio/gpio-ge.c
deleted file mode 100644
index 7b95a4a8318..00000000000
--- a/drivers/gpio/gpio-ge.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Driver for GE FPGA based GPIO
- *
- * Author: Martyn Welch <martyn.welch@ge.com>
- *
- * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/* TODO
- *
- * Configuration of output modes (totem-pole/open-drain)
- * Interrupt configuration - interrupts are always generated the FPGA relies on
- * the I/O interrupt controllers mask to stop them propergating
- */
-
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-
-#define GEF_GPIO_DIRECT         0x00
-#define GEF_GPIO_IN             0x04
-#define GEF_GPIO_OUT            0x08
-#define GEF_GPIO_TRIG           0x0C
-#define GEF_GPIO_POLAR_A        0x10
-#define GEF_GPIO_POLAR_B        0x14
-#define GEF_GPIO_INT_STAT       0x18
-#define GEF_GPIO_OVERRUN        0x1C
-#define GEF_GPIO_MODE           0x20
-
-static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
-{
-        unsigned int data;
-
-        data = ioread32be(reg);
-        /* value: 0=low; 1=high */
-        if (value & 0x1)
-                data = data | (0x1 << offset);
-        else
-                data = data & ~(0x1 << offset);
-
-        iowrite32be(data, reg);
-}
-
-
-static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned int data;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
-        data = data | (0x1 << offset);
-        iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
-        return 0;
-}
-
-static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-        unsigned int data;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        /* Set direction before switching to input */
-        _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
-        data = data & ~(0x1 << offset);
-        iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
-        return 0;
-}
-
-static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned int data;
-        int state = 0;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_IN);
-        state = (int)((data >> offset) & 0x1);
-
-        return state;
-}
-
-static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-}
-
-static int __init gef_gpio_init(void)
-{
-        struct device_node *np;
-        int retval;
-        struct of_mm_gpio_chip *gef_gpio_chip;
-
-        for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
-
-                pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
-                /* Allocate chip structure */
-                gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
-                if (!gef_gpio_chip) {
-                        pr_err("%s: Unable to allocate structure\n",
-                                np->full_name);
-                        continue;
-                }
-
-                /* Setup pointers to chip functions */
-                gef_gpio_chip->gc.of_gpio_n_cells = 2;
-                gef_gpio_chip->gc.ngpio = 19;
-                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->gc.get = gef_gpio_get;
-                gef_gpio_chip->gc.set = gef_gpio_set;
-
-                /* This function adds a memory mapped GPIO chip */
-                retval = of_mm_gpiochip_add(np, gef_gpio_chip);
-                if (retval) {
-                        kfree(gef_gpio_chip);
-                        pr_err("%s: Unable to add GPIO\n", np->full_name);
-                }
-        }
-
-        for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
-
-                pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
-                /* Allocate chip structure */
-                gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
-                if (!gef_gpio_chip) {
-                        pr_err("%s: Unable to allocate structure\n",
-                                np->full_name);
-                        continue;
-                }
-
-                /* Setup pointers to chip functions */
-                gef_gpio_chip->gc.of_gpio_n_cells = 2;
-                gef_gpio_chip->gc.ngpio = 6;
-                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->gc.get = gef_gpio_get;
-                gef_gpio_chip->gc.set = gef_gpio_set;
-
-                /* This function adds a memory mapped GPIO chip */
-                retval = of_mm_gpiochip_add(np, gef_gpio_chip);
-                if (retval) {
-                        kfree(gef_gpio_chip);
-                        pr_err("%s: Unable to add GPIO\n", np->full_name);
-                }
-        }
-
-        for_each_compatible_node(np, NULL, "ge,imp3a-gpio") {
-
-                pr_debug("%s: Initialising GE GPIO\n", np->full_name);
-
-                /* Allocate chip structure */
-                gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
-                if (!gef_gpio_chip) {
-                        pr_err("%s: Unable to allocate structure\n",
-                                np->full_name);
-                        continue;
-                }
-
-                /* Setup pointers to chip functions */
-                gef_gpio_chip->gc.of_gpio_n_cells = 2;
-                gef_gpio_chip->gc.ngpio = 16;
-                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->gc.get = gef_gpio_get;
-                gef_gpio_chip->gc.set = gef_gpio_set;
-
-                /* This function adds a memory mapped GPIO chip */
-                retval = of_mm_gpiochip_add(np, gef_gpio_chip);
-                if (retval) {
-                        kfree(gef_gpio_chip);
-                        pr_err("%s: Unable to add GPIO\n", np->full_name);
-                }
-        }
-
-        return 0;
-};
-arch_initcall(gef_gpio_init);
-
-MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
-MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-generic.c b/drivers/gpio/gpio-generic.c
index 05fcc0f247c..4e24436b0f8 100644
--- a/drivers/gpio/gpio-generic.c
+++ b/drivers/gpio/gpio-generic.c
@@ -364,7 +364,7 @@ EXPORT_SYMBOL_GPL(bgpio_remove);
 int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
                unsigned long sz, void __iomem *dat, void __iomem *set,
                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
-               unsigned long flags)
+               bool big_endian)
 {
         int ret;
 
@@ -385,7 +385,7 @@ int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
         if (ret)
                 return ret;
 
-        ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN);
+        ret = bgpio_setup_accessors(dev, bgc, big_endian);
         if (ret)
                 return ret;
 
@@ -394,11 +394,6 @@ int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
                 return ret;
 
         bgc->data = bgc->read_reg(bgc->reg_dat);
-        if (bgc->gc.set == bgpio_set_set &&
-                        !(flags & BGPIOF_UNREADABLE_REG_SET))
-                bgc->data = bgc->read_reg(bgc->reg_set);
-        if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
-                bgc->dir = bgc->read_reg(bgc->reg_dir);
 
         return ret;
 }
@@ -444,7 +439,7 @@ static void __iomem *bgpio_map(struct platform_device *pdev,
         return ret;
 }
 
-static int bgpio_pdev_probe(struct platform_device *pdev)
+static int __devinit bgpio_pdev_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct resource *r;
@@ -454,7 +449,7 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
         void __iomem *dirout;
         void __iomem *dirin;
         unsigned long sz;
-        unsigned long flags = 0;
+        bool be;
         int err;
         struct bgpio_chip *bgc;
         struct bgpio_pdata *pdata = dev_get_platdata(dev);
@@ -485,14 +480,13 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
         if (err)
                 return err;
 
-        if (!strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be"))
-                flags |= BGPIOF_BIG_ENDIAN;
+        be = !strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be");
 
         bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
         if (!bgc)
                 return -ENOMEM;
 
-        err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
+        err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, be);
         if (err)
                 return err;
 
@@ -507,7 +501,7 @@ static int bgpio_pdev_probe(struct platform_device *pdev)
         return gpiochip_add(&bgc->gc);
 }
 
-static int bgpio_pdev_remove(struct platform_device *pdev)
+static int __devexit bgpio_pdev_remove(struct platform_device *pdev)
 {
         struct bgpio_chip *bgc = platform_get_drvdata(pdev);
 
@@ -527,10 +521,20 @@ static struct platform_driver bgpio_driver = {
         },
         .id_table = bgpio_id_table,
         .probe = bgpio_pdev_probe,
-        .remove = bgpio_pdev_remove,
+        .remove = __devexit_p(bgpio_pdev_remove),
 };
 
-module_platform_driver(bgpio_driver);
+static int __init bgpio_platform_init(void)
+{
+        return platform_driver_register(&bgpio_driver);
+}
+module_init(bgpio_platform_init);
+
+static void __exit bgpio_platform_exit(void)
+{
+        platform_driver_unregister(&bgpio_driver);
+}
+module_exit(bgpio_platform_exit);
 
 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
deleted file mode 100644
index 6f2306db859..00000000000
--- a/drivers/gpio/gpio-ich.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * Intel ICH6-10, Series 5 and 6 GPIO driver
- *
- * Copyright (C) 2010 Extreme Engineering Solutions.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/lpc_ich.h>
-
-#define DRV_NAME "gpio_ich"
-
-/*
- * GPIO register offsets in GPIO I/O space.
- * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
- * LVLx registers.  Logic in the read/write functions takes a register and
- * an absolute bit number and determines the proper register offset and bit
- * number in that register.  For example, to read the value of GPIO bit 50
- * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
- * bit 18 (50%32).
- */
-enum GPIO_REG {
-        GPIO_USE_SEL = 0,
-        GPIO_IO_SEL,
-        GPIO_LVL,
-};
-
-static const u8 ichx_regs[3][3] = {
-        {0x00, 0x30, 0x40},     /* USE_SEL[1-3] offsets */
-        {0x04, 0x34, 0x44},     /* IO_SEL[1-3] offsets */
-        {0x0c, 0x38, 0x48},     /* LVL[1-3] offsets */
-};
-
-static const u8 ichx_reglen[3] = {
-        0x30, 0x10, 0x10,
-};
-
-#define ICHX_WRITE(val, reg, base_res)  outl(val, (reg) + (base_res)->start)
-#define ICHX_READ(reg, base_res)        inl((reg) + (base_res)->start)
-
-struct ichx_desc {
-        /* Max GPIO pins the chipset can have */
-        uint ngpio;
-
-        /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
-        bool uses_gpe0;
-
-        /* USE_SEL is bogus on some chipsets, eg 3100 */
-        u32 use_sel_ignore[3];
-
-        /* Some chipsets have quirks, let these use their own request/get */
-        int (*request)(struct gpio_chip *chip, unsigned offset);
-        int (*get)(struct gpio_chip *chip, unsigned offset);
-};
-
-static struct {
-        spinlock_t lock;
-        struct platform_device *dev;
-        struct gpio_chip chip;
-        struct resource *gpio_base;     /* GPIO IO base */
-        struct resource *pm_base;       /* Power Mangagment IO base */
-        struct ichx_desc *desc; /* Pointer to chipset-specific description */
-        u32 orig_gpio_ctrl;     /* Orig CTRL value, used to restore on exit */
-        u8 use_gpio;            /* Which GPIO groups are usable */
-} ichx_priv;
-
-static int modparam_gpiobase = -1;      /* dynamic */
-module_param_named(gpiobase, modparam_gpiobase, int, 0444);
-MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
-                           "which is the default.");
-
-static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
-{
-        unsigned long flags;
-        u32 data, tmp;
-        int reg_nr = nr / 32;
-        int bit = nr & 0x1f;
-        int ret = 0;
-
-        spin_lock_irqsave(&ichx_priv.lock, flags);
-
-        data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
-        if (val)
-                data |= 1 << bit;
-        else
-                data &= ~(1 << bit);
-        ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
-        tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
-        if (verify && data != tmp)
-                ret = -EPERM;
-
-        spin_unlock_irqrestore(&ichx_priv.lock, flags);
-
-        return ret;
-}
-
-static int ichx_read_bit(int reg, unsigned nr)
-{
-        unsigned long flags;
-        u32 data;
-        int reg_nr = nr / 32;
-        int bit = nr & 0x1f;
-
-        spin_lock_irqsave(&ichx_priv.lock, flags);
-
-        data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
-
-        spin_unlock_irqrestore(&ichx_priv.lock, flags);
-
-        return data & (1 << bit) ? 1 : 0;
-}
-
-static int ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
-{
-        return (ichx_priv.use_gpio & (1 << (nr / 32))) ? 0 : -ENXIO;
-}
-
-static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
-{
-        if (!ichx_gpio_check_available(gpio, nr))
-                return -ENXIO;
-
-        /*
-         * Try setting pin as an input and verify it worked since many pins
-         * are output-only.
-         */
-        if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
-                return -EINVAL;
-
-        return 0;
-}
-
-static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
-                                        int val)
-{
-        if (!ichx_gpio_check_available(gpio, nr))
-                return -ENXIO;
-
-        /* Set GPIO output value. */
-        ichx_write_bit(GPIO_LVL, nr, val, 0);
-
-        /*
-         * Try setting pin as an output and verify it worked since many pins
-         * are input-only.
-         */
-        if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
-                return -EINVAL;
-
-        return 0;
-}
-
-static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
-{
-        if (!ichx_gpio_check_available(chip, nr))
-                return -ENXIO;
-
-        return ichx_read_bit(GPIO_LVL, nr);
-}
-
-static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
-{
-        unsigned long flags;
-        u32 data;
-
-        if (!ichx_gpio_check_available(chip, nr))
-                return -ENXIO;
-
-        /*
-         * GPI 0 - 15 need to be read from the power management registers on
-         * a ICH6/3100 bridge.
-         */
-        if (nr < 16) {
-                if (!ichx_priv.pm_base)
-                        return -ENXIO;
-
-                spin_lock_irqsave(&ichx_priv.lock, flags);
-
-                /* GPI 0 - 15 are latched, write 1 to clear*/
-                ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
-                data = ICHX_READ(0, ichx_priv.pm_base);
-
-                spin_unlock_irqrestore(&ichx_priv.lock, flags);
-
-                return (data >> 16) & (1 << nr) ? 1 : 0;
-        } else {
-                return ichx_gpio_get(chip, nr);
-        }
-}
-
-static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
-{
-        /*
-         * Note we assume the BIOS properly set a bridge's USE value.  Some
-         * chips (eg Intel 3100) have bogus USE values though, so first see if
-         * the chipset's USE value can be trusted for this specific bit.
-         * If it can't be trusted, assume that the pin can be used as a GPIO.
-         */
-        if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
-                return 1;
-
-        return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
-}
-
-static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
-{
-        /*
-         * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
-         * bridge as they are controlled by USE register bits 0 and 1.  See
-         * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
-         * additional info.
-         */
-        if (nr == 16 || nr == 17)
-                nr -= 16;
-
-        return ichx_gpio_request(chip, nr);
-}
-
-static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
-{
-        ichx_write_bit(GPIO_LVL, nr, val, 0);
-}
-
-static void ichx_gpiolib_setup(struct gpio_chip *chip)
-{
-        chip->owner = THIS_MODULE;
-        chip->label = DRV_NAME;
-        chip->dev = &ichx_priv.dev->dev;
-
-        /* Allow chip-specific overrides of request()/get() */
-        chip->request = ichx_priv.desc->request ?
-                ichx_priv.desc->request : ichx_gpio_request;
-        chip->get = ichx_priv.desc->get ?
-                ichx_priv.desc->get : ichx_gpio_get;
-
-        chip->set = ichx_gpio_set;
-        chip->direction_input = ichx_gpio_direction_input;
-        chip->direction_output = ichx_gpio_direction_output;
-        chip->base = modparam_gpiobase;
-        chip->ngpio = ichx_priv.desc->ngpio;
-        chip->can_sleep = 0;
-        chip->dbg_show = NULL;
-}
-
-/* ICH6-based, 631xesb-based */
-static struct ichx_desc ich6_desc = {
-        /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
-        .request = ich6_gpio_request,
-        .get = ich6_gpio_get,
-
-        /* GPIO 0-15 are read in the GPE0_STS PM register */
-        .uses_gpe0 = true,
-
-        .ngpio = 50,
-};
-
-/* Intel 3100 */
-static struct ichx_desc i3100_desc = {
-        /*
-         * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
-         * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
-         * Datasheet for more info.
-         */
-        .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
-
-        /* The 3100 needs fixups for GPIO 0 - 17 */
-        .request = ich6_gpio_request,
-        .get = ich6_gpio_get,
-
-        /* GPIO 0-15 are read in the GPE0_STS PM register */
-        .uses_gpe0 = true,
-
-        .ngpio = 50,
-};
-
-/* ICH7 and ICH8-based */
-static struct ichx_desc ich7_desc = {
-        .ngpio = 50,
-};
-
-/* ICH9-based */
-static struct ichx_desc ich9_desc = {
-        .ngpio = 61,
-};
-
-/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
-static struct ichx_desc ich10_cons_desc = {
-        .ngpio = 61,
-};
-static struct ichx_desc ich10_corp_desc = {
-        .ngpio = 72,
-};
-
-/* Intel 5 series, 6 series, 3400 series, and C200 series */
-static struct ichx_desc intel5_desc = {
-        .ngpio = 76,
-};
-
-static int ichx_gpio_request_regions(struct resource *res_base,
-                                                const char *name, u8 use_gpio)
-{
-        int i;
-
-        if (!res_base || !res_base->start || !res_base->end)
-                return -ENODEV;
-
-        for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
-                if (!(use_gpio & (1 << i)))
-                        continue;
-                if (!request_region(res_base->start + ichx_regs[0][i],
-                                    ichx_reglen[i], name))
-                        goto request_err;
-        }
-        return 0;
-
-request_err:
-        /* Clean up: release already requested regions, if any */
-        for (i--; i >= 0; i--) {
-                if (!(use_gpio & (1 << i)))
-                        continue;
-                release_region(res_base->start + ichx_regs[0][i],
-                               ichx_reglen[i]);
-        }
-        return -EBUSY;
-}
-
-static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
-                if (!(use_gpio & (1 << i)))
-                        continue;
-                release_region(res_base->start + ichx_regs[0][i],
-                               ichx_reglen[i]);
-        }
-}
-
-static int ichx_gpio_probe(struct platform_device *pdev)
-{
-        struct resource *res_base, *res_pm;
-        int err;
-        struct lpc_ich_info *ich_info = pdev->dev.platform_data;
-
-        if (!ich_info)
-                return -ENODEV;
-
-        ichx_priv.dev = pdev;
-
-        switch (ich_info->gpio_version) {
-        case ICH_I3100_GPIO:
-                ichx_priv.desc = &i3100_desc;
-                break;
-        case ICH_V5_GPIO:
-                ichx_priv.desc = &intel5_desc;
-                break;
-        case ICH_V6_GPIO:
-                ichx_priv.desc = &ich6_desc;
-                break;
-        case ICH_V7_GPIO:
-                ichx_priv.desc = &ich7_desc;
-                break;
-        case ICH_V9_GPIO:
-                ichx_priv.desc = &ich9_desc;
-                break;
-        case ICH_V10CORP_GPIO:
-                ichx_priv.desc = &ich10_corp_desc;
-                break;
-        case ICH_V10CONS_GPIO:
-                ichx_priv.desc = &ich10_cons_desc;
-                break;
-        default:
-                return -ENODEV;
-        }
-
-        spin_lock_init(&ichx_priv.lock);
-        res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
-        ichx_priv.use_gpio = ich_info->use_gpio;
-        err = ichx_gpio_request_regions(res_base, pdev->name,
-                                        ichx_priv.use_gpio);
-        if (err)
-                return err;
-
-        ichx_priv.gpio_base = res_base;
-
-        /*
-         * If necessary, determine the I/O address of ACPI/power management
-         * registers which are needed to read the the GPE0 register for GPI pins
-         * 0 - 15 on some chipsets.
-         */
-        if (!ichx_priv.desc->uses_gpe0)
-                goto init;
-
-        res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
-        if (!res_pm) {
-                pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
-                goto init;
-        }
-
-        if (!request_region(res_pm->start, resource_size(res_pm),
-                        pdev->name)) {
-                pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
-                goto init;
-        }
-
-        ichx_priv.pm_base = res_pm;
-
-init:
-        ichx_gpiolib_setup(&ichx_priv.chip);
-        err = gpiochip_add(&ichx_priv.chip);
-        if (err) {
-                pr_err("Failed to register GPIOs\n");
-                goto add_err;
-        }
-
-        pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
-               ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
-
-        return 0;
-
-add_err:
-        ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
-        if (ichx_priv.pm_base)
-                release_region(ichx_priv.pm_base->start,
-                                resource_size(ichx_priv.pm_base));
-        return err;
-}
-
-static int ichx_gpio_remove(struct platform_device *pdev)
-{
-        int err;
-
-        err = gpiochip_remove(&ichx_priv.chip);
-        if (err) {
-                dev_err(&pdev->dev, "%s failed, %d\n",
-                                "gpiochip_remove()", err);
-                return err;
-        }
-
-        ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
-        if (ichx_priv.pm_base)
-                release_region(ichx_priv.pm_base->start,
-                                resource_size(ichx_priv.pm_base));
-
-        return 0;
-}
-
-static struct platform_driver ichx_gpio_driver = {
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .name   = DRV_NAME,
-        },
-        .probe          = ichx_gpio_probe,
-        .remove         = ichx_gpio_remove,
-};
-
-module_platform_driver(ichx_gpio_driver);
-
-MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
-MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:"DRV_NAME);
diff --git a/drivers/gpio/gpio-janz-ttl.c b/drivers/gpio/gpio-janz-ttl.c
index 7d0a04169a3..813ac077e5d 100644
--- a/drivers/gpio/gpio-janz-ttl.c
+++ b/drivers/gpio/gpio-janz-ttl.c
@@ -108,13 +108,13 @@ static void ttl_set_value(struct gpio_chip *gpio, unsigned offset, int value)
         spin_unlock(&mod->lock);
 }
 
-static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
+static void __devinit ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val)
 {
         iowrite16be(reg, &mod->regs->control);
         iowrite16be(val, &mod->regs->control);
 }
 
-static void ttl_setup_device(struct ttl_module *mod)
+static void __devinit ttl_setup_device(struct ttl_module *mod)
 {
         /* reset the device to a known state */
         iowrite16be(0x0000, &mod->regs->control);
@@ -140,7 +140,7 @@ static void ttl_setup_device(struct ttl_module *mod)
         ttl_write_reg(mod, MASTER_CONF_CTL, CONF_PAE | CONF_PBE | CONF_PCE);
 }
 
-static int ttl_probe(struct platform_device *pdev)
+static int __devinit ttl_probe(struct platform_device *pdev)
 {
         struct janz_platform_data *pdata;
         struct device *dev = &pdev->dev;
@@ -201,6 +201,8 @@ static int ttl_probe(struct platform_device *pdev)
                 goto out_iounmap_regs;
         }
 
+        dev_info(&pdev->dev, "module %d: registered GPIO device\n",
+                             pdata->modno);
         return 0;
 
 out_iounmap_regs:
@@ -211,7 +213,7 @@ out_return:
         return ret;
 }
 
-static int ttl_remove(struct platform_device *pdev)
+static int __devexit ttl_remove(struct platform_device *pdev)
 {
         struct ttl_module *mod = platform_get_drvdata(pdev);
         struct device *dev = &pdev->dev;
@@ -234,12 +236,23 @@ static struct platform_driver ttl_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe          = ttl_probe,
-        .remove         = ttl_remove,
+        .remove         = __devexit_p(ttl_remove),
 };
 
-module_platform_driver(ttl_driver);
+static int __init ttl_init(void)
+{
+        return platform_driver_register(&ttl_driver);
+}
+
+static void __exit ttl_exit(void)
+{
+        platform_driver_unregister(&ttl_driver);
+}
 
 MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
 MODULE_DESCRIPTION("Janz MODULbus VMOD-TTL Driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:janz-ttl");
+
+module_init(ttl_init);
+module_exit(ttl_exit);
diff --git a/drivers/gpio/gpio-ks8695.c b/drivers/gpio/gpio-ks8695.c
deleted file mode 100644
index a3ac66ea364..00000000000
--- a/drivers/gpio/gpio-ks8695.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * arch/arm/mach-ks8695/gpio.c
- *
- * Copyright (C) 2006 Andrew Victor
- * Updated to GPIOLIB, Copyright 2008 Simtec Electronics
- *                     Daniel Silverstone <dsilvers@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/mach/irq.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/gpio-ks8695.h>
-
-/*
- * Configure a GPIO line for either GPIO function, or its internal
- * function (Interrupt, Timer, etc).
- */
-static void ks8695_gpio_mode(unsigned int pin, short gpio)
-{
-        unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN };
-        unsigned long x, flags;
-
-        if (pin > KS8695_GPIO_5)        /* only GPIO 0..5 have internal functions */
-                return;
-
-        local_irq_save(flags);
-
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
-        if (gpio)                       /* GPIO: set bit to 0 */
-                x &= ~enable[pin];
-        else                            /* Internal function: set bit to 1 */
-                x |= enable[pin];
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPC);
-
-        local_irq_restore(flags);
-}
-
-
-static unsigned short gpio_irq[] = { KS8695_IRQ_EXTERN0, KS8695_IRQ_EXTERN1, KS8695_IRQ_EXTERN2, KS8695_IRQ_EXTERN3 };
-
-/*
- * Configure GPIO pin as external interrupt source.
- */
-int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
-{
-        unsigned long x, flags;
-
-        if (pin > KS8695_GPIO_3)        /* only GPIO 0..3 can generate IRQ */
-                return -EINVAL;
-
-        local_irq_save(flags);
-
-        /* set pin as input */
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x &= ~IOPM(pin);
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
-
-        local_irq_restore(flags);
-
-        /* Set IRQ triggering type */
-        irq_set_irq_type(gpio_irq[pin], type);
-
-        /* enable interrupt mode */
-        ks8695_gpio_mode(pin, 0);
-
-        return 0;
-}
-EXPORT_SYMBOL(ks8695_gpio_interrupt);
-
-
-
-/* .... Generic GPIO interface .............................................. */
-
-/*
- * Configure the GPIO line as an input.
- */
-static int ks8695_gpio_direction_input(struct gpio_chip *gc, unsigned int pin)
-{
-        unsigned long x, flags;
-
-        if (pin > KS8695_GPIO_15)
-                return -EINVAL;
-
-        /* set pin to GPIO mode */
-        ks8695_gpio_mode(pin, 1);
-
-        local_irq_save(flags);
-
-        /* set pin as input */
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x &= ~IOPM(pin);
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-
-/*
- * Configure the GPIO line as an output, with default state.
- */
-static int ks8695_gpio_direction_output(struct gpio_chip *gc,
-                                        unsigned int pin, int state)
-{
-        unsigned long x, flags;
-
-        if (pin > KS8695_GPIO_15)
-                return -EINVAL;
-
-        /* set pin to GPIO mode */
-        ks8695_gpio_mode(pin, 1);
-
-        local_irq_save(flags);
-
-        /* set line state */
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
-        if (state)
-                x |= IOPD(pin);
-        else
-                x &= ~IOPD(pin);
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
-
-        /* set pin as output */
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x |= IOPM(pin);
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-
-/*
- * Set the state of an output GPIO line.
- */
-static void ks8695_gpio_set_value(struct gpio_chip *gc,
-                                  unsigned int pin, int state)
-{
-        unsigned long x, flags;
-
-        if (pin > KS8695_GPIO_15)
-                return;
-
-        local_irq_save(flags);
-
-        /* set output line state */
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
-        if (state)
-                x |= IOPD(pin);
-        else
-                x &= ~IOPD(pin);
-        __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
-
-        local_irq_restore(flags);
-}
-
-
-/*
- * Read the state of a GPIO line.
- */
-static int ks8695_gpio_get_value(struct gpio_chip *gc, unsigned int pin)
-{
-        unsigned long x;
-
-        if (pin > KS8695_GPIO_15)
-                return -EINVAL;
-
-        x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
-        return (x & IOPD(pin)) != 0;
-}
-
-
-/*
- * Map GPIO line to IRQ number.
- */
-static int ks8695_gpio_to_irq(struct gpio_chip *gc, unsigned int pin)
-{
-        if (pin > KS8695_GPIO_3)        /* only GPIO 0..3 can generate IRQ */
-                return -EINVAL;
-
-        return gpio_irq[pin];
-}
-
-/*
- * Map IRQ number to GPIO line.
- */
-int irq_to_gpio(unsigned int irq)
-{
-        if ((irq < KS8695_IRQ_EXTERN0) || (irq > KS8695_IRQ_EXTERN3))
-                return -EINVAL;
-
-        return (irq - KS8695_IRQ_EXTERN0);
-}
-EXPORT_SYMBOL(irq_to_gpio);
-
-/* GPIOLIB interface */
-
-static struct gpio_chip ks8695_gpio_chip = {
-        .label                  = "KS8695",
-        .direction_input        = ks8695_gpio_direction_input,
-        .direction_output       = ks8695_gpio_direction_output,
-        .get                    = ks8695_gpio_get_value,
-        .set                    = ks8695_gpio_set_value,
-        .to_irq                 = ks8695_gpio_to_irq,
-        .base                   = 0,
-        .ngpio                  = 16,
-        .can_sleep              = 0,
-};
-
-/* Register the GPIOs */
-void ks8695_register_gpios(void)
-{
-        if (gpiochip_add(&ks8695_gpio_chip))
-                printk(KERN_ERR "Unable to register core GPIOs\n");
-}
-
-/* .... Debug interface ..................................................... */
-
-#ifdef CONFIG_DEBUG_FS
-
-static int ks8695_gpio_show(struct seq_file *s, void *unused)
-{
-        unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN };
-        unsigned int intmask[] = { IOPC_IOEINT0TM, IOPC_IOEINT1TM, IOPC_IOEINT2TM, IOPC_IOEINT3TM };
-        unsigned long mode, ctrl, data;
-        int i;
-
-        mode = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
-        data = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
-
-        seq_printf(s, "Pin\tI/O\tFunction\tState\n\n");
-
-        for (i = KS8695_GPIO_0; i <= KS8695_GPIO_15 ; i++) {
-                seq_printf(s, "%i:\t", i);
-
-                seq_printf(s, "%s\t", (mode & IOPM(i)) ? "Output" : "Input");
-
-                if (i <= KS8695_GPIO_3) {
-                        if (ctrl & enable[i]) {
-                                seq_printf(s, "EXT%i ", i);
-
-                                switch ((ctrl & intmask[i]) >> (4 * i)) {
-                                        case IOPC_TM_LOW:
-                                                seq_printf(s, "(Low)");         break;
-                                        case IOPC_TM_HIGH:
-                                                seq_printf(s, "(High)");        break;
-                                        case IOPC_TM_RISING:
-                                                seq_printf(s, "(Rising)");      break;
-                                        case IOPC_TM_FALLING:
-                                                seq_printf(s, "(Falling)");     break;
-                                        case IOPC_TM_EDGE:
-                                                seq_printf(s, "(Edges)");       break;
-                                }
-                        }
-                        else
-                                seq_printf(s, "GPIO\t");
-                }
-                else if (i <= KS8695_GPIO_5) {
-                        if (ctrl & enable[i])
-                                seq_printf(s, "TOUT%i\t", i - KS8695_GPIO_4);
-                        else
-                                seq_printf(s, "GPIO\t");
-                }
-                else
-                        seq_printf(s, "GPIO\t");
-
-                seq_printf(s, "\t");
-
-                seq_printf(s, "%i\n", (data & IOPD(i)) ? 1 : 0);
-        }
-        return 0;
-}
-
-static int ks8695_gpio_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, ks8695_gpio_show, NULL);
-}
-
-static const struct file_operations ks8695_gpio_operations = {
-        .open           = ks8695_gpio_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init ks8695_gpio_debugfs_init(void)
-{
-        /* /sys/kernel/debug/ks8695_gpio */
-        (void) debugfs_create_file("ks8695_gpio", S_IFREG | S_IRUGO, NULL, NULL, &ks8695_gpio_operations);
-        return 0;
-}
-postcore_initcall(ks8695_gpio_debugfs_init);
-
-#endif
diff --git a/drivers/gpio/gpio-langwell.c b/drivers/gpio/gpio-langwell.c
index e77b2b3e94a..d2eb57c60e0 100644
--- a/drivers/gpio/gpio-langwell.c
+++ b/drivers/gpio/gpio-langwell.c
@@ -36,7 +36,6 @@
 #include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
-#include <linux/irqdomain.h>
 
 /*
  * Langwell chip has 64 pins and thus there are 2 32bit registers to control
@@ -60,15 +59,14 @@ enum GPIO_REG {
         GRER,           /* rising edge detect */
         GFER,           /* falling edge detect */
         GEDR,           /* edge detect result */
-        GAFR,           /* alt function */
 };
 
 struct lnw_gpio {
         struct gpio_chip                chip;
         void                            *reg_base;
         spinlock_t                      lock;
+        unsigned                        irq_base;
         struct pci_dev                  *pdev;
-        struct irq_domain               *domain;
 };
 
 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
@@ -83,31 +81,6 @@ static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
         return ptr;
 }
 
-static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
-                                   enum GPIO_REG reg_type)
-{
-        struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-        unsigned nreg = chip->ngpio / 32;
-        u8 reg = offset / 16;
-        void __iomem *ptr;
-
-        ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
-        return ptr;
-}
-
-static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
-        u32 value = readl(gafr);
-        int shift = (offset % 16) << 1, af = (value >> shift) & 3;
-
-        if (af) {
-                value &= ~(3 << shift);
-                writel(value, gafr);
-        }
-        return 0;
-}
-
 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
@@ -177,13 +150,13 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
-        return irq_create_mapping(lnw->domain, offset);
+        return lnw->irq_base + offset;
 }
 
 static int lnw_irq_type(struct irq_data *d, unsigned type)
 {
         struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
-        u32 gpio = irqd_to_hwirq(d);
+        u32 gpio = d->irq - lnw->irq_base;
         unsigned long flags;
         u32 value;
         void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
@@ -250,55 +223,20 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
         /* check GPIO controller to check which pin triggered the interrupt */
         for (base = 0; base < lnw->chip.ngpio; base += 32) {
                 gedr = gpio_reg(&lnw->chip, base, GEDR);
-                while ((pending = readl(gedr))) {
+                pending = readl(gedr);
+                while (pending) {
                         gpio = __ffs(pending);
                         mask = BIT(gpio);
+                        pending &= ~mask;
                         /* Clear before handling so we can't lose an edge */
                         writel(mask, gedr);
-                        generic_handle_irq(irq_find_mapping(lnw->domain,
-                                                            base + gpio));
+                        generic_handle_irq(lnw->irq_base + base + gpio);
                 }
         }
 
         chip->irq_eoi(data);
 }
 
-static void lnw_irq_init_hw(struct lnw_gpio *lnw)
-{
-        void __iomem *reg;
-        unsigned base;
-
-        for (base = 0; base < lnw->chip.ngpio; base += 32) {
-                /* Clear the rising-edge detect register */
-                reg = gpio_reg(&lnw->chip, base, GRER);
-                writel(0, reg);
-                /* Clear the falling-edge detect register */
-                reg = gpio_reg(&lnw->chip, base, GFER);
-                writel(0, reg);
-                /* Clear the edge detect status register */
-                reg = gpio_reg(&lnw->chip, base, GEDR);
-                writel(~0, reg);
-        }
-}
-
-static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
-                            irq_hw_number_t hw)
-{
-        struct lnw_gpio *lnw = d->host_data;
-
-        irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
-                                      "demux");
-        irq_set_chip_data(virq, lnw);
-        irq_set_irq_type(virq, IRQ_TYPE_NONE);
-
-        return 0;
-}
-
-static const struct irq_domain_ops lnw_gpio_irq_ops = {
-        .map = lnw_gpio_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
 #ifdef CONFIG_PM
 static int lnw_gpio_runtime_resume(struct device *dev)
 {
@@ -332,96 +270,95 @@ static const struct dev_pm_ops lnw_gpio_pm_ops = {
         .runtime_idle = lnw_gpio_runtime_idle,
 };
 
-static int lnw_gpio_probe(struct pci_dev *pdev,
+static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
                         const struct pci_device_id *id)
 {
         void *base;
+        int i;
         resource_size_t start, len;
         struct lnw_gpio *lnw;
+        u32 irq_base;
         u32 gpio_base;
-        int retval;
-        int ngpio = id->driver_data;
+        int retval = 0;
 
         retval = pci_enable_device(pdev);
         if (retval)
-                return retval;
+                goto done;
 
         retval = pci_request_regions(pdev, "langwell_gpio");
         if (retval) {
                 dev_err(&pdev->dev, "error requesting resources\n");
                 goto err2;
         }
-        /* get the gpio_base from bar1 */
+        /* get the irq_base from bar1 */
         start = pci_resource_start(pdev, 1);
         len = pci_resource_len(pdev, 1);
         base = ioremap_nocache(start, len);
         if (!base) {
                 dev_err(&pdev->dev, "error mapping bar1\n");
-                retval = -EFAULT;
                 goto err3;
         }
+        irq_base = *(u32 *)base;
         gpio_base = *((u32 *)base + 1);
         /* release the IO mapping, since we already get the info from bar1 */
         iounmap(base);
         /* get the register base from bar0 */
         start = pci_resource_start(pdev, 0);
         len = pci_resource_len(pdev, 0);
-        base = devm_ioremap_nocache(&pdev->dev, start, len);
+        base = ioremap_nocache(start, len);
         if (!base) {
                 dev_err(&pdev->dev, "error mapping bar0\n");
                 retval = -EFAULT;
                 goto err3;
         }
 
-        lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
+        lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
         if (!lnw) {
                 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
                 retval = -ENOMEM;
-                goto err3;
+                goto err4;
         }
-
-        lnw->domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
-                                            &lnw_gpio_irq_ops, lnw);
-        if (!lnw->domain) {
-                retval = -ENOMEM;
-                goto err3;
-        }
-
         lnw->reg_base = base;
+        lnw->irq_base = irq_base;
         lnw->chip.label = dev_name(&pdev->dev);
-        lnw->chip.request = lnw_gpio_request;
         lnw->chip.direction_input = lnw_gpio_direction_input;
         lnw->chip.direction_output = lnw_gpio_direction_output;
         lnw->chip.get = lnw_gpio_get;
         lnw->chip.set = lnw_gpio_set;
         lnw->chip.to_irq = lnw_gpio_to_irq;
         lnw->chip.base = gpio_base;
-        lnw->chip.ngpio = ngpio;
+        lnw->chip.ngpio = id->driver_data;
         lnw->chip.can_sleep = 0;
         lnw->pdev = pdev;
         pci_set_drvdata(pdev, lnw);
         retval = gpiochip_add(&lnw->chip);
         if (retval) {
                 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
-                goto err3;
+                goto err5;
         }
-
-        lnw_irq_init_hw(lnw);
-
         irq_set_handler_data(pdev->irq, lnw);
         irq_set_chained_handler(pdev->irq, lnw_irq_handler);
+        for (i = 0; i < lnw->chip.ngpio; i++) {
+                irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
+                                              handle_simple_irq, "demux");
+                irq_set_chip_data(i + lnw->irq_base, lnw);
+        }
 
         spin_lock_init(&lnw->lock);
 
         pm_runtime_put_noidle(&pdev->dev);
         pm_runtime_allow(&pdev->dev);
 
-        return 0;
-
+        goto done;
+err5:
+        kfree(lnw);
+err4:
+        iounmap(base);
 err3:
         pci_release_regions(pdev);
 err2:
         pci_disable_device(pdev);
+done:
         return retval;
 }
 
@@ -435,7 +372,7 @@ static struct pci_driver lnw_gpio_driver = {
 };
 
 
-static int wp_gpio_probe(struct platform_device *pdev)
+static int __devinit wp_gpio_probe(struct platform_device *pdev)
 {
         struct lnw_gpio *lnw;
         struct gpio_chip *gc;
@@ -484,7 +421,7 @@ err_kmalloc:
         return retval;
 }
 
-static int wp_gpio_remove(struct platform_device *pdev)
+static int __devexit wp_gpio_remove(struct platform_device *pdev)
 {
         struct lnw_gpio *lnw = platform_get_drvdata(pdev);
         int err;
@@ -499,7 +436,7 @@ static int wp_gpio_remove(struct platform_device *pdev)
 
 static struct platform_driver wp_gpio_driver = {
         .probe          = wp_gpio_probe,
-        .remove         = wp_gpio_remove,
+        .remove         = __devexit_p(wp_gpio_remove),
         .driver         = {
                 .name   = "wp_gpio",
                 .owner  = THIS_MODULE,
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
deleted file mode 100644
index 36d7dee07b2..00000000000
--- a/drivers/gpio/gpio-lpc32xx.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/*
- * GPIO driver for LPC32xx SoC
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/gpio.h>
-#include <linux/of_gpio.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-lpc32xx.h>
-#include <mach/irqs.h>
-
-#define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
-#define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
-#define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
-#define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
-#define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
-#define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
-#define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
-#define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
-#define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
-#define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
-#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
-#define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
-#define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
-#define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
-#define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
-#define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
-#define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
-#define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
-#define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
-#define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
-#define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
-#define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
-#define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
-#define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
-#define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
-
-#define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
-#define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
-#define GPO3_PIN_TO_BIT(x)                      (1 << (x))
-#define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
-#define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
-#define GPIO3_PIN_IN_SEL(x, y)                  (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
-#define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
-#define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
-#define GPO3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
-
-struct gpio_regs {
-        void __iomem *inp_state;
-        void __iomem *outp_state;
-        void __iomem *outp_set;
-        void __iomem *outp_clr;
-        void __iomem *dir_set;
-        void __iomem *dir_clr;
-};
-
-/*
- * GPIO names
- */
-static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
-        "p0.0", "p0.1", "p0.2", "p0.3",
-        "p0.4", "p0.5", "p0.6", "p0.7"
-};
-
-static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
-        "p1.0", "p1.1", "p1.2", "p1.3",
-        "p1.4", "p1.5", "p1.6", "p1.7",
-        "p1.8", "p1.9", "p1.10", "p1.11",
-        "p1.12", "p1.13", "p1.14", "p1.15",
-        "p1.16", "p1.17", "p1.18", "p1.19",
-        "p1.20", "p1.21", "p1.22", "p1.23",
-};
-
-static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
-        "p2.0", "p2.1", "p2.2", "p2.3",
-        "p2.4", "p2.5", "p2.6", "p2.7",
-        "p2.8", "p2.9", "p2.10", "p2.11",
-        "p2.12"
-};
-
-static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
-        "gpio00", "gpio01", "gpio02", "gpio03",
-        "gpio04", "gpio05"
-};
-
-static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
-        "gpi00", "gpi01", "gpi02", "gpi03",
-        "gpi04", "gpi05", "gpi06", "gpi07",
-        "gpi08", "gpi09",  NULL,    NULL,
-         NULL,    NULL,    NULL,   "gpi15",
-        "gpi16", "gpi17", "gpi18", "gpi19",
-        "gpi20", "gpi21", "gpi22", "gpi23",
-        "gpi24", "gpi25", "gpi26", "gpi27",
-        "gpi28"
-};
-
-static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
-        "gpo00", "gpo01", "gpo02", "gpo03",
-        "gpo04", "gpo05", "gpo06", "gpo07",
-        "gpo08", "gpo09", "gpo10", "gpo11",
-        "gpo12", "gpo13", "gpo14", "gpo15",
-        "gpo16", "gpo17", "gpo18", "gpo19",
-        "gpo20", "gpo21", "gpo22", "gpo23"
-};
-
-static struct gpio_regs gpio_grp_regs_p0 = {
-        .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
-        .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
-        .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
-        .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
-        .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
-};
-
-static struct gpio_regs gpio_grp_regs_p1 = {
-        .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
-        .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
-        .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
-        .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
-        .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
-};
-
-static struct gpio_regs gpio_grp_regs_p2 = {
-        .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
-        .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
-        .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
-        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
-        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
-};
-
-static struct gpio_regs gpio_grp_regs_p3 = {
-        .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
-        .outp_state     = LPC32XX_GPIO_P3_OUTP_STATE,
-        .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
-        .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
-        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
-        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
-};
-
-struct lpc32xx_gpio_chip {
-        struct gpio_chip        chip;
-        struct gpio_regs        *gpio_grp;
-};
-
-static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
-        struct gpio_chip *gpc)
-{
-        return container_of(gpc, struct lpc32xx_gpio_chip, chip);
-}
-
-static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
-        unsigned pin, int input)
-{
-        if (input)
-                __raw_writel(GPIO012_PIN_TO_BIT(pin),
-                        group->gpio_grp->dir_clr);
-        else
-                __raw_writel(GPIO012_PIN_TO_BIT(pin),
-                        group->gpio_grp->dir_set);
-}
-
-static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin, int input)
-{
-        u32 u = GPIO3_PIN_TO_BIT(pin);
-
-        if (input)
-                __raw_writel(u, group->gpio_grp->dir_clr);
-        else
-                __raw_writel(u, group->gpio_grp->dir_set);
-}
-
-static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
-        unsigned pin, int high)
-{
-        if (high)
-                __raw_writel(GPIO012_PIN_TO_BIT(pin),
-                        group->gpio_grp->outp_set);
-        else
-                __raw_writel(GPIO012_PIN_TO_BIT(pin),
-                        group->gpio_grp->outp_clr);
-}
-
-static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin, int high)
-{
-        u32 u = GPIO3_PIN_TO_BIT(pin);
-
-        if (high)
-                __raw_writel(u, group->gpio_grp->outp_set);
-        else
-                __raw_writel(u, group->gpio_grp->outp_clr);
-}
-
-static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin, int high)
-{
-        if (high)
-                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
-        else
-                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
-}
-
-static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
-        unsigned pin)
-{
-        return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
-                pin);
-}
-
-static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin)
-{
-        int state = __raw_readl(group->gpio_grp->inp_state);
-
-        /*
-         * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
-         * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
-         */
-        return GPIO3_PIN_IN_SEL(state, pin);
-}
-
-static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin)
-{
-        return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
-}
-
-static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
-        unsigned pin)
-{
-        return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
-}
-
-/*
- * GENERIC_GPIO primitives.
- */
-static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
-        unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_dir_p012(group, pin, 1);
-
-        return 0;
-}
-
-static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
-        unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_dir_p3(group, pin, 1);
-
-        return 0;
-}
-
-static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
-        unsigned pin)
-{
-        return 0;
-}
-
-static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        return __get_gpio_state_p012(group, pin);
-}
-
-static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        return __get_gpio_state_p3(group, pin);
-}
-
-static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        return __get_gpi_state_p3(group, pin);
-}
-
-static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_level_p012(group, pin, value);
-        __set_gpio_dir_p012(group, pin, 0);
-
-        return 0;
-}
-
-static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_level_p3(group, pin, value);
-        __set_gpio_dir_p3(group, pin, 0);
-
-        return 0;
-}
-
-static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpo_level_p3(group, pin, value);
-        return 0;
-}
-
-static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_level_p012(group, pin, value);
-}
-
-static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpio_level_p3(group, pin, value);
-}
-
-static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
-        int value)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        __set_gpo_level_p3(group, pin, value);
-}
-
-static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
-{
-        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
-
-        return __get_gpo_state_p3(group, pin);
-}
-
-static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
-{
-        if (pin < chip->ngpio)
-                return 0;
-
-        return -EINVAL;
-}
-
-static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
-{
-        return IRQ_LPC32XX_P0_P1_IRQ;
-}
-
-static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
-        IRQ_LPC32XX_GPIO_00,
-        IRQ_LPC32XX_GPIO_01,
-        IRQ_LPC32XX_GPIO_02,
-        IRQ_LPC32XX_GPIO_03,
-        IRQ_LPC32XX_GPIO_04,
-        IRQ_LPC32XX_GPIO_05,
-};
-
-static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
-                return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
-        return -ENXIO;
-}
-
-static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
-        IRQ_LPC32XX_GPI_00,
-        IRQ_LPC32XX_GPI_01,
-        IRQ_LPC32XX_GPI_02,
-        IRQ_LPC32XX_GPI_03,
-        IRQ_LPC32XX_GPI_04,
-        IRQ_LPC32XX_GPI_05,
-        IRQ_LPC32XX_GPI_06,
-        IRQ_LPC32XX_GPI_07,
-        IRQ_LPC32XX_GPI_08,
-        IRQ_LPC32XX_GPI_09,
-        -ENXIO, /* 10 */
-        -ENXIO, /* 11 */
-        -ENXIO, /* 12 */
-        -ENXIO, /* 13 */
-        -ENXIO, /* 14 */
-        -ENXIO, /* 15 */
-        -ENXIO, /* 16 */
-        -ENXIO, /* 17 */
-        -ENXIO, /* 18 */
-        IRQ_LPC32XX_GPI_19,
-        -ENXIO, /* 20 */
-        -ENXIO, /* 21 */
-        -ENXIO, /* 22 */
-        -ENXIO, /* 23 */
-        -ENXIO, /* 24 */
-        -ENXIO, /* 25 */
-        -ENXIO, /* 26 */
-        -ENXIO, /* 27 */
-        IRQ_LPC32XX_GPI_28,
-};
-
-static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
-                return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
-        return -ENXIO;
-}
-
-static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
-        {
-                .chip = {
-                        .label                  = "gpio_p0",
-                        .direction_input        = lpc32xx_gpio_dir_input_p012,
-                        .get                    = lpc32xx_gpio_get_value_p012,
-                        .direction_output       = lpc32xx_gpio_dir_output_p012,
-                        .set                    = lpc32xx_gpio_set_value_p012,
-                        .request                = lpc32xx_gpio_request,
-                        .to_irq                 = lpc32xx_gpio_to_irq_p01,
-                        .base                   = LPC32XX_GPIO_P0_GRP,
-                        .ngpio                  = LPC32XX_GPIO_P0_MAX,
-                        .names                  = gpio_p0_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p0,
-        },
-        {
-                .chip = {
-                        .label                  = "gpio_p1",
-                        .direction_input        = lpc32xx_gpio_dir_input_p012,
-                        .get                    = lpc32xx_gpio_get_value_p012,
-                        .direction_output       = lpc32xx_gpio_dir_output_p012,
-                        .set                    = lpc32xx_gpio_set_value_p012,
-                        .request                = lpc32xx_gpio_request,
-                        .to_irq                 = lpc32xx_gpio_to_irq_p01,
-                        .base                   = LPC32XX_GPIO_P1_GRP,
-                        .ngpio                  = LPC32XX_GPIO_P1_MAX,
-                        .names                  = gpio_p1_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p1,
-        },
-        {
-                .chip = {
-                        .label                  = "gpio_p2",
-                        .direction_input        = lpc32xx_gpio_dir_input_p012,
-                        .get                    = lpc32xx_gpio_get_value_p012,
-                        .direction_output       = lpc32xx_gpio_dir_output_p012,
-                        .set                    = lpc32xx_gpio_set_value_p012,
-                        .request                = lpc32xx_gpio_request,
-                        .base                   = LPC32XX_GPIO_P2_GRP,
-                        .ngpio                  = LPC32XX_GPIO_P2_MAX,
-                        .names                  = gpio_p2_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p2,
-        },
-        {
-                .chip = {
-                        .label                  = "gpio_p3",
-                        .direction_input        = lpc32xx_gpio_dir_input_p3,
-                        .get                    = lpc32xx_gpio_get_value_p3,
-                        .direction_output       = lpc32xx_gpio_dir_output_p3,
-                        .set                    = lpc32xx_gpio_set_value_p3,
-                        .request                = lpc32xx_gpio_request,
-                        .to_irq                 = lpc32xx_gpio_to_irq_gpio_p3,
-                        .base                   = LPC32XX_GPIO_P3_GRP,
-                        .ngpio                  = LPC32XX_GPIO_P3_MAX,
-                        .names                  = gpio_p3_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p3,
-        },
-        {
-                .chip = {
-                        .label                  = "gpi_p3",
-                        .direction_input        = lpc32xx_gpio_dir_in_always,
-                        .get                    = lpc32xx_gpi_get_value,
-                        .request                = lpc32xx_gpio_request,
-                        .to_irq                 = lpc32xx_gpio_to_irq_gpi_p3,
-                        .base                   = LPC32XX_GPI_P3_GRP,
-                        .ngpio                  = LPC32XX_GPI_P3_MAX,
-                        .names                  = gpi_p3_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p3,
-        },
-        {
-                .chip = {
-                        .label                  = "gpo_p3",
-                        .direction_output       = lpc32xx_gpio_dir_out_always,
-                        .set                    = lpc32xx_gpo_set_value,
-                        .get                    = lpc32xx_gpo_get_value,
-                        .request                = lpc32xx_gpio_request,
-                        .base                   = LPC32XX_GPO_P3_GRP,
-                        .ngpio                  = LPC32XX_GPO_P3_MAX,
-                        .names                  = gpo_p3_names,
-                        .can_sleep              = 0,
-                },
-                .gpio_grp = &gpio_grp_regs_p3,
-        },
-};
-
-static int lpc32xx_of_xlate(struct gpio_chip *gc,
-                            const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        /* Is this the correct bank? */
-        u32 bank = gpiospec->args[0];
-        if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
-            (gc != &lpc32xx_gpiochip[bank].chip)))
-                return -EINVAL;
-
-        if (flags)
-                *flags = gpiospec->args[2];
-        return gpiospec->args[1];
-}
-
-static int lpc32xx_gpio_probe(struct platform_device *pdev)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
-                if (pdev->dev.of_node) {
-                        lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
-                        lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
-                        lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
-                }
-                gpiochip_add(&lpc32xx_gpiochip[i].chip);
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_OF
-static struct of_device_id lpc32xx_gpio_of_match[] = {
-        { .compatible = "nxp,lpc3220-gpio", },
-        { },
-};
-#endif
-
-static struct platform_driver lpc32xx_gpio_driver = {
-        .driver         = {
-                .name   = "lpc32xx-gpio",
-                .owner  = THIS_MODULE,
-                .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
-        },
-        .probe          = lpc32xx_gpio_probe,
-};
-
-module_platform_driver(lpc32xx_gpio_driver);
diff --git a/drivers/gpio/gpio-max7300.c b/drivers/gpio/gpio-max7300.c
index 4b6b9a04e32..a5ca0ab1b37 100644
--- a/drivers/gpio/gpio-max7300.c
+++ b/drivers/gpio/gpio-max7300.c
@@ -31,7 +31,7 @@ static int max7300_i2c_read(struct device *dev, unsigned int reg)
         return i2c_smbus_read_byte_data(client, reg);
 }
 
-static int max7300_probe(struct i2c_client *client,
+static int __devinit max7300_probe(struct i2c_client *client,
                          const struct i2c_device_id *id)
 {
         struct max7301 *ts;
@@ -55,7 +55,7 @@ static int max7300_probe(struct i2c_client *client,
         return ret;
 }
 
-static int max7300_remove(struct i2c_client *client)
+static int __devexit max7300_remove(struct i2c_client *client)
 {
         return __max730x_remove(&client->dev);
 }
@@ -72,7 +72,7 @@ static struct i2c_driver max7300_driver = {
                 .owner = THIS_MODULE,
         },
         .probe = max7300_probe,
-        .remove = max7300_remove,
+        .remove = __devexit_p(max7300_remove),
         .id_table = max7300_id,
 };
 
diff --git a/drivers/gpio/gpio-max7301.c b/drivers/gpio/gpio-max7301.c
index c6c535c1310..741acfcbe76 100644
--- a/drivers/gpio/gpio-max7301.c
+++ b/drivers/gpio/gpio-max7301.c
@@ -50,7 +50,7 @@ static int max7301_spi_read(struct device *dev, unsigned int reg)
         return word & 0xff;
 }
 
-static int max7301_probe(struct spi_device *spi)
+static int __devinit max7301_probe(struct spi_device *spi)
 {
         struct max7301 *ts;
         int ret;
@@ -75,7 +75,7 @@ static int max7301_probe(struct spi_device *spi)
         return ret;
 }
 
-static int max7301_remove(struct spi_device *spi)
+static int __devexit max7301_remove(struct spi_device *spi)
 {
         return __max730x_remove(&spi->dev);
 }
@@ -92,7 +92,7 @@ static struct spi_driver max7301_driver = {
                 .owner = THIS_MODULE,
         },
         .probe = max7301_probe,
-        .remove = max7301_remove,
+        .remove = __devexit_p(max7301_remove),
         .id_table = max7301_id,
 };
 
diff --git a/drivers/gpio/gpio-max730x.c b/drivers/gpio/gpio-max730x.c
index 00092342b84..05e2dac60b3 100644
--- a/drivers/gpio/gpio-max730x.c
+++ b/drivers/gpio/gpio-max730x.c
@@ -160,13 +160,17 @@ static void max7301_set(struct gpio_chip *chip, unsigned offset, int value)
         mutex_unlock(&ts->lock);
 }
 
-int __max730x_probe(struct max7301 *ts)
+int __devinit __max730x_probe(struct max7301 *ts)
 {
         struct device *dev = ts->dev;
         struct max7301_platform_data *pdata;
         int i, ret;
 
         pdata = dev->platform_data;
+        if (!pdata || !pdata->base) {
+                dev_err(dev, "incorrect or missing platform data\n");
+                return -EINVAL;
+        }
 
         mutex_init(&ts->lock);
         dev_set_drvdata(dev, ts);
@@ -174,12 +178,7 @@ int __max730x_probe(struct max7301 *ts)
         /* Power up the chip and disable IRQ output */
         ts->write(dev, 0x04, 0x01);
 
-        if (pdata) {
-                ts->input_pullup_active = pdata->input_pullup_active;
-                ts->chip.base = pdata->base;
-        } else {
-                ts->chip.base = -1;
-        }
+        ts->input_pullup_active = pdata->input_pullup_active;
         ts->chip.label = dev->driver->name;
 
         ts->chip.direction_input = max7301_direction_input;
@@ -187,6 +186,7 @@ int __max730x_probe(struct max7301 *ts)
         ts->chip.direction_output = max7301_direction_output;
         ts->chip.set = max7301_set;
 
+        ts->chip.base = pdata->base;
         ts->chip.ngpio = PIN_NUMBER;
         ts->chip.can_sleep = 1;
         ts->chip.dev = dev;
@@ -226,7 +226,7 @@ exit_destroy:
 }
 EXPORT_SYMBOL_GPL(__max730x_probe);
 
-int __max730x_remove(struct device *dev)
+int __devexit __max730x_remove(struct device *dev)
 {
         struct max7301 *ts = dev_get_drvdata(dev);
         int ret;
diff --git a/drivers/gpio/gpio-max732x.c b/drivers/gpio/gpio-max732x.c
index 1e0467ce4c3..9504120812a 100644
--- a/drivers/gpio/gpio-max732x.c
+++ b/drivers/gpio/gpio-max732x.c
@@ -526,7 +526,7 @@ static void max732x_irq_teardown(struct max732x_chip *chip)
 }
 #endif
 
-static int max732x_setup_gpio(struct max732x_chip *chip,
+static int __devinit max732x_setup_gpio(struct max732x_chip *chip,
                                         const struct i2c_device_id *id,
                                         unsigned gpio_start)
 {
@@ -574,7 +574,7 @@ static int max732x_setup_gpio(struct max732x_chip *chip,
         return port;
 }
 
-static int max732x_probe(struct i2c_client *client,
+static int __devinit max732x_probe(struct i2c_client *client,
                                    const struct i2c_device_id *id)
 {
         struct max732x_platform_data *pdata;
@@ -651,7 +651,7 @@ out_failed:
         return ret;
 }
 
-static int max732x_remove(struct i2c_client *client)
+static int __devexit max732x_remove(struct i2c_client *client)
 {
         struct max732x_platform_data *pdata = client->dev.platform_data;
         struct max732x_chip *chip = i2c_get_clientdata(client);
@@ -690,7 +690,7 @@ static struct i2c_driver max732x_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe          = max732x_probe,
-        .remove         = max732x_remove,
+        .remove         = __devexit_p(max732x_remove),
         .id_table       = max732x_id,
 };
 
diff --git a/drivers/gpio/gpio-mc33880.c b/drivers/gpio/gpio-mc33880.c
index 6a8fdc26ae6..b3b4652e89e 100644
--- a/drivers/gpio/gpio-mc33880.c
+++ b/drivers/gpio/gpio-mc33880.c
@@ -26,7 +26,6 @@
 #include <linux/spi/mc33880.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
-#include <linux/module.h>
 
 #define DRIVER_NAME "mc33880"
 
@@ -80,7 +79,7 @@ static void mc33880_set(struct gpio_chip *chip, unsigned offset, int value)
         mutex_unlock(&mc->lock);
 }
 
-static int mc33880_probe(struct spi_device *spi)
+static int __devinit mc33880_probe(struct spi_device *spi)
 {
         struct mc33880 *mc;
         struct mc33880_platform_data *pdata;
@@ -147,7 +146,7 @@ exit_destroy:
         return ret;
 }
 
-static int mc33880_remove(struct spi_device *spi)
+static int __devexit mc33880_remove(struct spi_device *spi)
 {
         struct mc33880 *mc;
         int ret;
@@ -175,7 +174,7 @@ static struct spi_driver mc33880_driver = {
                 .owner          = THIS_MODULE,
         },
         .probe          = mc33880_probe,
-        .remove         = mc33880_remove,
+        .remove         = __devexit_p(mc33880_remove),
 };
 
 static int __init mc33880_init(void)
diff --git a/drivers/gpio/gpio-mc9s08dz60.c b/drivers/gpio/gpio-mc9s08dz60.c
deleted file mode 100644
index 0ab700046a2..00000000000
--- a/drivers/gpio/gpio-mc9s08dz60.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Wu Guoxing <b39297@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-
-#define GPIO_GROUP_NUM 2
-#define GPIO_NUM_PER_GROUP 8
-#define GPIO_NUM (GPIO_GROUP_NUM*GPIO_NUM_PER_GROUP)
-
-struct mc9s08dz60 {
-        struct i2c_client *client;
-        struct gpio_chip chip;
-};
-
-static inline struct mc9s08dz60 *to_mc9s08dz60(struct gpio_chip *gc)
-{
-        return container_of(gc, struct mc9s08dz60, chip);
-}
-
-
-static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit)
-{
-        *reg = 0x20 + offset / GPIO_NUM_PER_GROUP;
-        *bit = offset % GPIO_NUM_PER_GROUP;
-}
-
-static int mc9s08dz60_get_value(struct gpio_chip *gc, unsigned offset)
-{
-        u8 reg, bit;
-        s32 value;
-        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
-
-        mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
-        value = i2c_smbus_read_byte_data(mc9s->client, reg);
-
-        return (value >= 0) ? (value >> bit) & 0x1 : 0;
-}
-
-static int mc9s08dz60_set(struct mc9s08dz60 *mc9s, unsigned offset, int val)
-{
-        u8 reg, bit;
-        s32 value;
-
-        mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
-        value = i2c_smbus_read_byte_data(mc9s->client, reg);
-        if (value >= 0) {
-                if (val)
-                        value |= 1 << bit;
-                else
-                        value &= ~(1 << bit);
-
-                return i2c_smbus_write_byte_data(mc9s->client, reg, value);
-        } else
-                return value;
-
-}
-
-
-static void mc9s08dz60_set_value(struct gpio_chip *gc, unsigned offset, int val)
-{
-        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
-
-        mc9s08dz60_set(mc9s, offset, val);
-}
-
-static int mc9s08dz60_direction_output(struct gpio_chip *gc,
-                                       unsigned offset, int val)
-{
-        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
-
-        return mc9s08dz60_set(mc9s, offset, val);
-}
-
-static int mc9s08dz60_probe(struct i2c_client *client,
-                            const struct i2c_device_id *id)
-{
-        struct mc9s08dz60 *mc9s;
-
-        mc9s = devm_kzalloc(&client->dev, sizeof(*mc9s), GFP_KERNEL);
-        if (!mc9s)
-                return -ENOMEM;
-
-        mc9s->chip.label = client->name;
-        mc9s->chip.base = -1;
-        mc9s->chip.dev = &client->dev;
-        mc9s->chip.owner = THIS_MODULE;
-        mc9s->chip.ngpio = GPIO_NUM;
-        mc9s->chip.can_sleep = 1;
-        mc9s->chip.get = mc9s08dz60_get_value;
-        mc9s->chip.set = mc9s08dz60_set_value;
-        mc9s->chip.direction_output = mc9s08dz60_direction_output;
-        mc9s->client = client;
-        i2c_set_clientdata(client, mc9s);
-
-        return gpiochip_add(&mc9s->chip);
-}
-
-static int mc9s08dz60_remove(struct i2c_client *client)
-{
-        struct mc9s08dz60 *mc9s;
-
-        mc9s = i2c_get_clientdata(client);
-
-        return gpiochip_remove(&mc9s->chip);
-}
-
-static const struct i2c_device_id mc9s08dz60_id[] = {
-        {"mc9s08dz60", 0},
-        {},
-};
-
-MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id);
-
-static struct i2c_driver mc9s08dz60_i2c_driver = {
-        .driver = {
-                .owner = THIS_MODULE,
-                .name = "mc9s08dz60",
-        },
-        .probe = mc9s08dz60_probe,
-        .remove = mc9s08dz60_remove,
-        .id_table = mc9s08dz60_id,
-};
-
-module_i2c_driver(mc9s08dz60_i2c_driver);
-
-MODULE_AUTHOR("Freescale Semiconductor, Inc. "
-                "Wu Guoxing <b39297@freescale.com>");
-MODULE_DESCRIPTION("mc9s08dz60 gpio function on mx35 3ds board");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index 3cea0ea79e8..1ef46e6c2a2 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -5,7 +5,6 @@
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/mutex.h>
-#include <linux/module.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
@@ -77,7 +76,7 @@ struct mcp23s08_driver_data {
 
 /*----------------------------------------------------------------------*/
 
-#if IS_ENABLED(CONFIG_I2C)
+#ifdef CONFIG_I2C
 
 static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
 {
@@ -353,7 +352,7 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                         chip->base + t, bank, t, label,
                         (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
                         (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
-                        (mcp->cache[MCP_GPPU] & mask) ? "up" : "  ");
+                        (mcp->cache[MCP_GPPU] & mask) ? "  " : "up");
                 /* NOTE:  ignoring the irq-related registers */
                 seq_printf(s, "\n");
         }
@@ -399,7 +398,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
                 break;
 #endif /* CONFIG_SPI_MASTER */
 
-#if IS_ENABLED(CONFIG_I2C)
+#ifdef CONFIG_I2C
         case MCP_TYPE_008:
                 mcp->ops = &mcp23008_ops;
                 mcp->chip.ngpio = 8;
@@ -473,9 +472,9 @@ fail:
 
 /*----------------------------------------------------------------------*/
 
-#if IS_ENABLED(CONFIG_I2C)
+#ifdef CONFIG_I2C
 
-static int mcp230xx_probe(struct i2c_client *client,
+static int __devinit mcp230xx_probe(struct i2c_client *client,
                                     const struct i2c_device_id *id)
 {
         struct mcp23s08_platform_data *pdata;
@@ -508,7 +507,7 @@ fail:
         return status;
 }
 
-static int mcp230xx_remove(struct i2c_client *client)
+static int __devexit mcp230xx_remove(struct i2c_client *client)
 {
         struct mcp23s08 *mcp = i2c_get_clientdata(client);
         int status;
@@ -533,7 +532,7 @@ static struct i2c_driver mcp230xx_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe          = mcp230xx_probe,
-        .remove         = mcp230xx_remove,
+        .remove         = __devexit_p(mcp230xx_remove),
         .id_table       = mcp230xx_id,
 };
 
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index b73366523fa..a9016f56ed7 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -14,22 +14,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#define IOH_EDGE_FALLING        0
-#define IOH_EDGE_RISING         BIT(0)
-#define IOH_LEVEL_L             BIT(1)
-#define IOH_LEVEL_H             (BIT(0) | BIT(1))
-#define IOH_EDGE_BOTH           BIT(2)
-#define IOH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
-
-#define IOH_IRQ_BASE            0
 
 #define PCI_VENDOR_ID_ROHM             0x10DB
 
@@ -58,22 +46,12 @@ struct ioh_regs {
 
 /**
  * struct ioh_gpio_reg_data - The register store data.
- * @ien_reg     To store contents of interrupt enable register.
- * @imask_reg:  To store contents of interrupt mask regist
  * @po_reg:     To store contents of PO register.
  * @pm_reg:     To store contents of PM register.
- * @im0_reg:    To store contents of interrupt mode regist0
- * @im1_reg:    To store contents of interrupt mode regist1
- * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
  */
 struct ioh_gpio_reg_data {
-        u32 ien_reg;
-        u32 imask_reg;
         u32 po_reg;
         u32 pm_reg;
-        u32 im0_reg;
-        u32 im1_reg;
-        u32 use_sel_reg;
 };
 
 /**
@@ -84,10 +62,7 @@ struct ioh_gpio_reg_data {
  * @gpio:                       Data for GPIO infrastructure.
  * @ioh_gpio_reg:               Memory mapped Register data is saved here
  *                              when suspend.
- * @gpio_use_sel:               Save GPIO_USE_SEL1~4 register for PM
  * @ch:                         Indicate GPIO channel
- * @irq_base:           Save base of IRQ number for interrupt
- * @spinlock:           Used for register access protection
  */
 struct ioh_gpio {
         void __iomem *base;
@@ -95,10 +70,8 @@ struct ioh_gpio {
         struct device *dev;
         struct gpio_chip gpio;
         struct ioh_gpio_reg_data ioh_gpio_reg;
-        u32 gpio_use_sel;
+        struct mutex lock;
         int ch;
-        int irq_base;
-        spinlock_t spinlock;
 };
 
 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
@@ -107,9 +80,8 @@ static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
 {
         u32 reg_val;
         struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
+        mutex_lock(&chip->lock);
         reg_val = ioread32(&chip->reg->regs[chip->ch].po);
         if (val)
                 reg_val |= (1 << nr);
@@ -117,7 +89,7 @@ static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
                 reg_val &= ~(1 << nr);
 
         iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        mutex_unlock(&chip->lock);
 }
 
 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
@@ -133,9 +105,8 @@ static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
         struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
         u32 pm;
         u32 reg_val;
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
+        mutex_lock(&chip->lock);
         pm = ioread32(&chip->reg->regs[chip->ch].pm) &
                                         ((1 << num_ports[chip->ch]) - 1);
         pm |= (1 << nr);
@@ -148,7 +119,7 @@ static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
                 reg_val &= ~(1 << nr);
         iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
 
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        mutex_unlock(&chip->lock);
 
         return 0;
 }
@@ -157,14 +128,13 @@ static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 {
         struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
         u32 pm;
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
+        mutex_lock(&chip->lock);
         pm = ioread32(&chip->reg->regs[chip->ch].pm) &
                                 ((1 << num_ports[chip->ch]) - 1);
         pm &= ~(1 << nr);
         iowrite32(pm, &chip->reg->regs[chip->ch].pm);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        mutex_unlock(&chip->lock);
 
         return 0;
 }
@@ -175,25 +145,8 @@ static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  */
 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
 {
-        int i;
-
-        for (i = 0; i < 8; i ++, chip++) {
-                chip->ioh_gpio_reg.po_reg =
-                                        ioread32(&chip->reg->regs[chip->ch].po);
-                chip->ioh_gpio_reg.pm_reg =
-                                        ioread32(&chip->reg->regs[chip->ch].pm);
-                chip->ioh_gpio_reg.ien_reg =
-                                       ioread32(&chip->reg->regs[chip->ch].ien);
-                chip->ioh_gpio_reg.imask_reg =
-                                     ioread32(&chip->reg->regs[chip->ch].imask);
-                chip->ioh_gpio_reg.im0_reg =
-                                      ioread32(&chip->reg->regs[chip->ch].im_0);
-                chip->ioh_gpio_reg.im1_reg =
-                                      ioread32(&chip->reg->regs[chip->ch].im_1);
-                if (i < 4)
-                        chip->ioh_gpio_reg.use_sel_reg =
-                                           ioread32(&chip->reg->ioh_sel_reg[i]);
-        }
+        chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
+        chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
 }
 
 /*
@@ -201,34 +154,13 @@ static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  */
 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
 {
-        int i;
-
-        for (i = 0; i < 8; i ++, chip++) {
-                iowrite32(chip->ioh_gpio_reg.po_reg,
-                          &chip->reg->regs[chip->ch].po);
-                iowrite32(chip->ioh_gpio_reg.pm_reg,
-                          &chip->reg->regs[chip->ch].pm);
-                iowrite32(chip->ioh_gpio_reg.ien_reg,
-                          &chip->reg->regs[chip->ch].ien);
-                iowrite32(chip->ioh_gpio_reg.imask_reg,
-                          &chip->reg->regs[chip->ch].imask);
-                iowrite32(chip->ioh_gpio_reg.im0_reg,
-                          &chip->reg->regs[chip->ch].im_0);
-                iowrite32(chip->ioh_gpio_reg.im1_reg,
-                          &chip->reg->regs[chip->ch].im_1);
-                if (i < 4)
-                        iowrite32(chip->ioh_gpio_reg.use_sel_reg,
-                                  &chip->reg->ioh_sel_reg[i]);
-        }
+        /* to store contents of PO register */
+        iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
+        /* to store contents of PM register */
+        iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
 }
 #endif
 
-static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
-{
-        struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
-        return chip->irq_base + offset;
-}
-
 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
 {
         struct gpio_chip *gpio = &chip->gpio;
@@ -243,178 +175,16 @@ static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
         gpio->base = -1;
         gpio->ngpio = num_port;
         gpio->can_sleep = 0;
-        gpio->to_irq = ioh_gpio_to_irq;
 }
 
-static int ioh_irq_type(struct irq_data *d, unsigned int type)
-{
-        u32 im;
-        void __iomem *im_reg;
-        u32 ien;
-        u32 im_pos;
-        int ch;
-        unsigned long flags;
-        u32 val;
-        int irq = d->irq;
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct ioh_gpio *chip = gc->private;
-
-        ch = irq - chip->irq_base;
-        if (irq <= chip->irq_base + 7) {
-                im_reg = &chip->reg->regs[chip->ch].im_0;
-                im_pos = ch;
-        } else {
-                im_reg = &chip->reg->regs[chip->ch].im_1;
-                im_pos = ch - 8;
-        }
-        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
-                __func__, irq, type, ch, im_pos, type);
-
-        spin_lock_irqsave(&chip->spinlock, flags);
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                val = IOH_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                val = IOH_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                val = IOH_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                val = IOH_LEVEL_H;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                val = IOH_LEVEL_L;
-                break;
-        case IRQ_TYPE_PROBE:
-                goto end;
-        default:
-                dev_warn(chip->dev, "%s: unknown type(%dd)",
-                        __func__, type);
-                goto end;
-        }
-
-        /* Set interrupt mode */
-        im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
-        iowrite32(im | (val << (im_pos * 4)), im_reg);
-
-        /* iclr */
-        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
-
-        /* IMASKCLR */
-        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
-
-        /* Enable interrupt */
-        ien = ioread32(&chip->reg->regs[chip->ch].ien);
-        iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
-end:
-        spin_unlock_irqrestore(&chip->spinlock, flags);
-
-        return 0;
-}
-
-static void ioh_irq_unmask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct ioh_gpio *chip = gc->private;
-
-        iowrite32(1 << (d->irq - chip->irq_base),
-                  &chip->reg->regs[chip->ch].imaskclr);
-}
-
-static void ioh_irq_mask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct ioh_gpio *chip = gc->private;
-
-        iowrite32(1 << (d->irq - chip->irq_base),
-                  &chip->reg->regs[chip->ch].imask);
-}
-
-static void ioh_irq_disable(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct ioh_gpio *chip = gc->private;
-        unsigned long flags;
-        u32 ien;
-
-        spin_lock_irqsave(&chip->spinlock, flags);
-        ien = ioread32(&chip->reg->regs[chip->ch].ien);
-        ien &= ~(1 << (d->irq - chip->irq_base));
-        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
-}
-
-static void ioh_irq_enable(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct ioh_gpio *chip = gc->private;
-        unsigned long flags;
-        u32 ien;
-
-        spin_lock_irqsave(&chip->spinlock, flags);
-        ien = ioread32(&chip->reg->regs[chip->ch].ien);
-        ien |= 1 << (d->irq - chip->irq_base);
-        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
-}
-
-static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
-{
-        struct ioh_gpio *chip = dev_id;
-        u32 reg_val;
-        int i, j;
-        int ret = IRQ_NONE;
-
-        for (i = 0; i < 8; i++, chip++) {
-                reg_val = ioread32(&chip->reg->regs[i].istatus);
-                for (j = 0; j < num_ports[i]; j++) {
-                        if (reg_val & BIT(j)) {
-                                dev_dbg(chip->dev,
-                                        "%s:[%d]:irq=%d status=0x%x\n",
-                                        __func__, j, irq, reg_val);
-                                iowrite32(BIT(j),
-                                          &chip->reg->regs[chip->ch].iclr);
-                                generic_handle_irq(chip->irq_base + j);
-                                ret = IRQ_HANDLED;
-                        }
-                }
-        }
-        return ret;
-}
-
-static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
-                                unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
-                                    handle_simple_irq);
-        gc->private = chip;
-        ct = gc->chip_types;
-
-        ct->chip.irq_mask = ioh_irq_mask;
-        ct->chip.irq_unmask = ioh_irq_unmask;
-        ct->chip.irq_set_type = ioh_irq_type;
-        ct->chip.irq_disable = ioh_irq_disable;
-        ct->chip.irq_enable = ioh_irq_enable;
-
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-}
-
-static int ioh_gpio_probe(struct pci_dev *pdev,
+static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
                                     const struct pci_device_id *id)
 {
         int ret;
-        int i, j;
+        int i;
         struct ioh_gpio *chip;
         void __iomem *base;
-        void *chip_save;
-        int irq_base;
+        void __iomem *chip_save;
 
         ret = pci_enable_device(pdev);
         if (ret) {
@@ -429,7 +199,7 @@ static int ioh_gpio_probe(struct pci_dev *pdev,
         }
 
         base = pci_iomap(pdev, 1, 0);
-        if (!base) {
+        if (base == 0) {
                 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
                 ret = -ENOMEM;
                 goto err_iomap;
@@ -448,7 +218,7 @@ static int ioh_gpio_probe(struct pci_dev *pdev,
                 chip->base = base;
                 chip->reg = chip->base;
                 chip->ch = i;
-                spin_lock_init(&chip->spinlock);
+                mutex_init(&chip->lock);
                 ioh_gpio_setup(chip, num_ports[i]);
                 ret = gpiochip_add(&chip->gpio);
                 if (ret) {
@@ -458,41 +228,10 @@ static int ioh_gpio_probe(struct pci_dev *pdev,
         }
 
         chip = chip_save;
-        for (j = 0; j < 8; j++, chip++) {
-                irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
-                                           NUMA_NO_NODE);
-                if (irq_base < 0) {
-                        dev_warn(&pdev->dev,
-                                "ml_ioh_gpio: Failed to get IRQ base num\n");
-                        chip->irq_base = -1;
-                        goto err_irq_alloc_descs;
-                }
-                chip->irq_base = irq_base;
-                ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
-        }
-
-        chip = chip_save;
-        ret = request_irq(pdev->irq, ioh_gpio_handler,
-                             IRQF_SHARED, KBUILD_MODNAME, chip);
-        if (ret != 0) {
-                dev_err(&pdev->dev,
-                        "%s request_irq failed\n", __func__);
-                goto err_request_irq;
-        }
-
         pci_set_drvdata(pdev, chip);
 
         return 0;
 
-err_request_irq:
-        chip = chip_save;
-err_irq_alloc_descs:
-        while (--j >= 0) {
-                chip--;
-                irq_free_descs(chip->irq_base, num_ports[j]);
-        }
-
-        chip = chip_save;
 err_gpiochip_add:
         while (--i >= 0) {
                 chip--;
@@ -517,19 +256,15 @@ err_pci_enable:
         return ret;
 }
 
-static void ioh_gpio_remove(struct pci_dev *pdev)
+static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
 {
         int err;
         int i;
         struct ioh_gpio *chip = pci_get_drvdata(pdev);
-        void *chip_save;
+        void __iomem *chip_save;
 
         chip_save = chip;
-
-        free_irq(pdev->irq, chip);
-
         for (i = 0; i < 8; i++, chip++) {
-                irq_free_descs(chip->irq_base, num_ports[i]);
                 err = gpiochip_remove(&chip->gpio);
                 if (err)
                         dev_err(&pdev->dev, "Failed gpiochip_remove\n");
@@ -547,11 +282,9 @@ static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 {
         s32 ret;
         struct ioh_gpio *chip = pci_get_drvdata(pdev);
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
         ioh_gpio_save_reg_conf(chip);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        ioh_gpio_restore_reg_conf(chip);
 
         ret = pci_save_state(pdev);
         if (ret) {
@@ -571,7 +304,6 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
 {
         s32 ret;
         struct ioh_gpio *chip = pci_get_drvdata(pdev);
-        unsigned long flags;
 
         ret = pci_enable_wake(pdev, PCI_D0, 0);
 
@@ -583,11 +315,9 @@ static int ioh_gpio_resume(struct pci_dev *pdev)
         }
         pci_restore_state(pdev);
 
-        spin_lock_irqsave(&chip->spinlock, flags);
         iowrite32(0x01, &chip->reg->srst);
         iowrite32(0x00, &chip->reg->srst);
         ioh_gpio_restore_reg_conf(chip);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
 
         return 0;
 }
@@ -606,12 +336,22 @@ static struct pci_driver ioh_gpio_driver = {
         .name = "ml_ioh_gpio",
         .id_table = ioh_gpio_pcidev_id,
         .probe = ioh_gpio_probe,
-        .remove = ioh_gpio_remove,
+        .remove = __devexit_p(ioh_gpio_remove),
         .suspend = ioh_gpio_suspend,
         .resume = ioh_gpio_resume
 };
 
-module_pci_driver(ioh_gpio_driver);
+static int __init ioh_gpio_pci_init(void)
+{
+        return pci_register_driver(&ioh_gpio_driver);
+}
+module_init(ioh_gpio_pci_init);
+
+static void __exit ioh_gpio_pci_exit(void)
+{
+        pci_unregister_driver(&ioh_gpio_driver);
+}
+module_exit(ioh_gpio_pci_exit);
 
 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-mm-lantiq.c b/drivers/gpio/gpio-mm-lantiq.c
deleted file mode 100644
index 2983dfbd066..00000000000
--- a/drivers/gpio/gpio-mm-lantiq.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/mutex.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <linux/of_gpio.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <lantiq_soc.h>
-
-/*
- * By attaching hardware latches to the EBU it is possible to create output
- * only gpios. This driver configures a special memory address, which when
- * written to outputs 16 bit to the latches.
- */
-
-#define LTQ_EBU_BUSCON  0x1e7ff         /* 16 bit access, slowest timing */
-#define LTQ_EBU_WP      0x80000000      /* write protect bit */
-
-struct ltq_mm {
-        struct of_mm_gpio_chip mmchip;
-        u16 shadow;     /* shadow the latches state */
-};
-
-/**
- * ltq_mm_apply() - write the shadow value to the ebu address.
- * @chip:     Pointer to our private data structure.
- *
- * Write the shadow value to the EBU to set the gpios. We need to set the
- * global EBU lock to make sure that PCI/MTD dont break.
- */
-static void ltq_mm_apply(struct ltq_mm *chip)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ebu_lock, flags);
-        ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
-        __raw_writew(chip->shadow, chip->mmchip.regs);
-        ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
-        spin_unlock_irqrestore(&ebu_lock, flags);
-}
-
-/**
- * ltq_mm_set() - gpio_chip->set - set gpios.
- * @gc:     Pointer to gpio_chip device structure.
- * @gpio:   GPIO signal number.
- * @val:    Value to be written to specified signal.
- *
- * Set the shadow value and call ltq_mm_apply.
- */
-static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value)
-{
-        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
-        struct ltq_mm *chip =
-                container_of(mm_gc, struct ltq_mm, mmchip);
-
-        if (value)
-                chip->shadow |= (1 << offset);
-        else
-                chip->shadow &= ~(1 << offset);
-        ltq_mm_apply(chip);
-}
-
-/**
- * ltq_mm_dir_out() - gpio_chip->dir_out - set gpio direction.
- * @gc:     Pointer to gpio_chip device structure.
- * @gpio:   GPIO signal number.
- * @val:    Value to be written to specified signal.
- *
- * Same as ltq_mm_set, always returns 0.
- */
-static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value)
-{
-        ltq_mm_set(gc, offset, value);
-
-        return 0;
-}
-
-/**
- * ltq_mm_save_regs() - Set initial values of GPIO pins
- * @mm_gc: pointer to memory mapped GPIO chip structure
- */
-static void ltq_mm_save_regs(struct of_mm_gpio_chip *mm_gc)
-{
-        struct ltq_mm *chip =
-                container_of(mm_gc, struct ltq_mm, mmchip);
-
-        /* tell the ebu controller which memory address we will be using */
-        ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1);
-
-        ltq_mm_apply(chip);
-}
-
-static int ltq_mm_probe(struct platform_device *pdev)
-{
-        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        struct ltq_mm *chip;
-        const __be32 *shadow;
-        int ret = 0;
-
-        if (!res) {
-                dev_err(&pdev->dev, "failed to get memory resource\n");
-                return -ENOENT;
-        }
-
-        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
-        if (!chip)
-                return -ENOMEM;
-
-        chip->mmchip.gc.ngpio = 16;
-        chip->mmchip.gc.label = "gpio-mm-ltq";
-        chip->mmchip.gc.direction_output = ltq_mm_dir_out;
-        chip->mmchip.gc.set = ltq_mm_set;
-        chip->mmchip.save_regs = ltq_mm_save_regs;
-
-        /* store the shadow value if one was passed by the devicetree */
-        shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
-        if (shadow)
-                chip->shadow = be32_to_cpu(*shadow);
-
-        ret = of_mm_gpiochip_add(pdev->dev.of_node, &chip->mmchip);
-        if (ret)
-                kfree(chip);
-        return ret;
-}
-
-static const struct of_device_id ltq_mm_match[] = {
-        { .compatible = "lantiq,gpio-mm" },
-        {},
-};
-MODULE_DEVICE_TABLE(of, ltq_mm_match);
-
-static struct platform_driver ltq_mm_driver = {
-        .probe = ltq_mm_probe,
-        .driver = {
-                .name = "gpio-mm-ltq",
-                .owner = THIS_MODULE,
-                .of_match_table = ltq_mm_match,
-        },
-};
-
-static int __init ltq_mm_init(void)
-{
-        return platform_driver_register(&ltq_mm_driver);
-}
-
-subsys_initcall(ltq_mm_init);
diff --git a/drivers/gpio/gpio-mpc5200.c b/drivers/gpio/gpio-mpc5200.c
index 42647f26c9e..52d3ed20810 100644
--- a/drivers/gpio/gpio-mpc5200.c
+++ b/drivers/gpio/gpio-mpc5200.c
@@ -23,7 +23,6 @@
 #include <linux/of_gpio.h>
 #include <linux/io.h>
 #include <linux/of_platform.h>
-#include <linux/module.h>
 
 #include <asm/gpio.h>
 #include <asm/mpc52xx.h>
@@ -148,7 +147,7 @@ mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         return 0;
 }
 
-static int mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
+static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
 {
         struct mpc52xx_gpiochip *chip;
         struct mpc52xx_gpio_wkup __iomem *regs;
@@ -308,7 +307,7 @@ mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         return 0;
 }
 
-static int mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
+static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
 {
         struct mpc52xx_gpiochip *chip;
         struct gpio_chip *gc;
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
deleted file mode 100644
index 9ae29cc0d17..00000000000
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ /dev/null
@@ -1,389 +0,0 @@
-/*
- * GPIOs on MPC512x/8349/8572/8610 and compatible
- *
- * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_gpio.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/irq.h>
-
-#define MPC8XXX_GPIO_PINS       32
-
-#define GPIO_DIR                0x00
-#define GPIO_ODR                0x04
-#define GPIO_DAT                0x08
-#define GPIO_IER                0x0c
-#define GPIO_IMR                0x10
-#define GPIO_ICR                0x14
-#define GPIO_ICR2               0x18
-
-struct mpc8xxx_gpio_chip {
-        struct of_mm_gpio_chip mm_gc;
-        spinlock_t lock;
-
-        /*
-         * shadowed data register to be able to clear/set output pins in
-         * open drain mode safely
-         */
-        u32 data;
-        struct irq_domain *irq;
-        const void *of_dev_id_data;
-};
-
-static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
-{
-        return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
-}
-
-static inline struct mpc8xxx_gpio_chip *
-to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
-{
-        return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
-}
-
-static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-
-        mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
-}
-
-/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
- * defined as output cannot be determined by reading GPDAT register,
- * so we use shadow data register instead. The status of input pins
- * is determined by reading GPDAT register.
- */
-static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
-{
-        u32 val;
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-
-        val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
-
-        return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
-}
-
-static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-
-        return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
-}
-
-static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-        unsigned long flags;
-
-        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-
-        if (val)
-                mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
-        else
-                mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
-
-        out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
-
-        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-}
-
-static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
-{
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-        unsigned long flags;
-
-        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-
-        clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
-
-        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-
-        return 0;
-}
-
-static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-        unsigned long flags;
-
-        mpc8xxx_gpio_set(gc, gpio, val);
-
-        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-
-        setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
-
-        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-
-        return 0;
-}
-
-static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
-{
-        /* GPIO 28..31 are input only on MPC5121 */
-        if (gpio >= 28)
-                return -EINVAL;
-
-        return mpc8xxx_gpio_dir_out(gc, gpio, val);
-}
-
-static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-        struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
-
-        if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
-                return irq_create_mapping(mpc8xxx_gc->irq, offset);
-        else
-                return -ENXIO;
-}
-
-static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-        unsigned int mask;
-
-        mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
-        if (mask)
-                generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
-                                                     32 - ffs(mask)));
-        if (chip->irq_eoi)
-                chip->irq_eoi(&desc->irq_data);
-}
-
-static void mpc8xxx_irq_unmask(struct irq_data *d)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-
-        setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
-
-        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-}
-
-static void mpc8xxx_irq_mask(struct irq_data *d)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-        unsigned long flags;
-
-        spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-
-        clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
-
-        spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-}
-
-static void mpc8xxx_irq_ack(struct irq_data *d)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-
-        out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
-}
-
-static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-        unsigned long flags;
-
-        switch (flow_type) {
-        case IRQ_TYPE_EDGE_FALLING:
-                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-                setbits32(mm->regs + GPIO_ICR,
-                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
-                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-                clrbits32(mm->regs + GPIO_ICR,
-                          mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
-                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
-        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
-        unsigned long gpio = irqd_to_hwirq(d);
-        void __iomem *reg;
-        unsigned int shift;
-        unsigned long flags;
-
-        if (gpio < 16) {
-                reg = mm->regs + GPIO_ICR;
-                shift = (15 - gpio) * 2;
-        } else {
-                reg = mm->regs + GPIO_ICR2;
-                shift = (15 - (gpio % 16)) * 2;
-        }
-
-        switch (flow_type) {
-        case IRQ_TYPE_EDGE_FALLING:
-        case IRQ_TYPE_LEVEL_LOW:
-                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-                clrsetbits_be32(reg, 3 << shift, 2 << shift);
-                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-                break;
-
-        case IRQ_TYPE_EDGE_RISING:
-        case IRQ_TYPE_LEVEL_HIGH:
-                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-                clrsetbits_be32(reg, 3 << shift, 1 << shift);
-                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
-                clrbits32(reg, 3 << shift);
-                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct irq_chip mpc8xxx_irq_chip = {
-        .name           = "mpc8xxx-gpio",
-        .irq_unmask     = mpc8xxx_irq_unmask,
-        .irq_mask       = mpc8xxx_irq_mask,
-        .irq_ack        = mpc8xxx_irq_ack,
-        .irq_set_type   = mpc8xxx_irq_set_type,
-};
-
-static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-                                irq_hw_number_t hw)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
-
-        if (mpc8xxx_gc->of_dev_id_data)
-                mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
-
-        irq_set_chip_data(virq, h->host_data);
-        irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
-        irq_set_irq_type(virq, IRQ_TYPE_NONE);
-
-        return 0;
-}
-
-static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
-        .map    = mpc8xxx_gpio_irq_map,
-        .xlate  = irq_domain_xlate_twocell,
-};
-
-static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
-        { .compatible = "fsl,mpc8349-gpio", },
-        { .compatible = "fsl,mpc8572-gpio", },
-        { .compatible = "fsl,mpc8610-gpio", },
-        { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
-        { .compatible = "fsl,pq3-gpio",     },
-        { .compatible = "fsl,qoriq-gpio",   },
-        {}
-};
-
-static void __init mpc8xxx_add_controller(struct device_node *np)
-{
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc;
-        struct of_mm_gpio_chip *mm_gc;
-        struct gpio_chip *gc;
-        const struct of_device_id *id;
-        unsigned hwirq;
-        int ret;
-
-        mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
-        if (!mpc8xxx_gc) {
-                ret = -ENOMEM;
-                goto err;
-        }
-
-        spin_lock_init(&mpc8xxx_gc->lock);
-
-        mm_gc = &mpc8xxx_gc->mm_gc;
-        gc = &mm_gc->gc;
-
-        mm_gc->save_regs = mpc8xxx_gpio_save_regs;
-        gc->ngpio = MPC8XXX_GPIO_PINS;
-        gc->direction_input = mpc8xxx_gpio_dir_in;
-        gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
-                mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
-        gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
-                mpc8572_gpio_get : mpc8xxx_gpio_get;
-        gc->set = mpc8xxx_gpio_set;
-        gc->to_irq = mpc8xxx_gpio_to_irq;
-
-        ret = of_mm_gpiochip_add(np, mm_gc);
-        if (ret)
-                goto err;
-
-        hwirq = irq_of_parse_and_map(np, 0);
-        if (hwirq == NO_IRQ)
-                goto skip_irq;
-
-        mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
-                                        &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
-        if (!mpc8xxx_gc->irq)
-                goto skip_irq;
-
-        id = of_match_node(mpc8xxx_gpio_ids, np);
-        if (id)
-                mpc8xxx_gc->of_dev_id_data = id->data;
-
-        /* ack and mask all irqs */
-        out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
-        out_be32(mm_gc->regs + GPIO_IMR, 0);
-
-        irq_set_handler_data(hwirq, mpc8xxx_gc);
-        irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
-
-skip_irq:
-        return;
-
-err:
-        pr_err("%s: registration failed with status %d\n",
-               np->full_name, ret);
-        kfree(mpc8xxx_gc);
-
-        return;
-}
-
-static int __init mpc8xxx_add_gpiochips(void)
-{
-        struct device_node *np;
-
-        for_each_matching_node(np, mpc8xxx_gpio_ids)
-                mpc8xxx_add_controller(np);
-
-        return 0;
-}
-arch_initcall(mpc8xxx_add_gpiochips);
diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c
deleted file mode 100644
index 27ea7b9257f..00000000000
--- a/drivers/gpio/gpio-msic.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * Intel Medfield MSIC GPIO driver>
- * Copyright (c) 2011, Intel Corporation.
- *
- * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
- * Based on intel_pmic_gpio.c
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/intel_msic.h>
-
-/* the offset for the mapping of global gpio pin to irq */
-#define MSIC_GPIO_IRQ_OFFSET    0x100
-
-#define MSIC_GPIO_DIR_IN        0
-#define MSIC_GPIO_DIR_OUT       BIT(5)
-#define MSIC_GPIO_TRIG_FALL     BIT(1)
-#define MSIC_GPIO_TRIG_RISE     BIT(2)
-
-/* masks for msic gpio output GPIOxxxxCTLO registers */
-#define MSIC_GPIO_DIR_MASK      BIT(5)
-#define MSIC_GPIO_DRV_MASK      BIT(4)
-#define MSIC_GPIO_REN_MASK      BIT(3)
-#define MSIC_GPIO_RVAL_MASK     (BIT(2) | BIT(1))
-#define MSIC_GPIO_DOUT_MASK     BIT(0)
-
-/* masks for msic gpio input GPIOxxxxCTLI registers */
-#define MSIC_GPIO_GLBYP_MASK    BIT(5)
-#define MSIC_GPIO_DBNC_MASK     (BIT(4) | BIT(3))
-#define MSIC_GPIO_INTCNT_MASK   (BIT(2) | BIT(1))
-#define MSIC_GPIO_DIN_MASK      BIT(0)
-
-#define MSIC_NUM_GPIO           24
-
-struct msic_gpio {
-        struct platform_device  *pdev;
-        struct mutex            buslock;
-        struct gpio_chip        chip;
-        int                     irq;
-        unsigned                irq_base;
-        unsigned long           trig_change_mask;
-        unsigned                trig_type;
-};
-
-/*
- * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
- * Both the high and low voltage gpios are divided in two banks.
- * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
- * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
- * GPIO1LV0..GPIO1LV7: low voltage, bank 1,  gpio_base + 8
- * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
- * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
- */
-
-static int msic_gpio_to_ireg(unsigned offset)
-{
-        if (offset >= MSIC_NUM_GPIO)
-                return -EINVAL;
-
-        if (offset < 8)
-                return INTEL_MSIC_GPIO0LV0CTLI - offset;
-        if (offset < 16)
-                return INTEL_MSIC_GPIO1LV0CTLI - offset + 8;
-        if (offset < 20)
-                return INTEL_MSIC_GPIO0HV0CTLI - offset + 16;
-
-        return INTEL_MSIC_GPIO1HV0CTLI - offset + 20;
-}
-
-static int msic_gpio_to_oreg(unsigned offset)
-{
-        if (offset >= MSIC_NUM_GPIO)
-                return -EINVAL;
-
-        if (offset < 8)
-                return INTEL_MSIC_GPIO0LV0CTLO - offset;
-        if (offset < 16)
-                return INTEL_MSIC_GPIO1LV0CTLO - offset + 8;
-        if (offset < 20)
-                return INTEL_MSIC_GPIO0HV0CTLO - offset + 16;
-
-        return INTEL_MSIC_GPIO1HV0CTLO - offset + 20;
-}
-
-static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        int reg;
-
-        reg = msic_gpio_to_oreg(offset);
-        if (reg < 0)
-                return reg;
-
-        return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK);
-}
-
-static int msic_gpio_direction_output(struct gpio_chip *chip,
-                        unsigned offset, int value)
-{
-        int reg;
-        unsigned mask;
-
-        value = (!!value) | MSIC_GPIO_DIR_OUT;
-        mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK;
-
-        reg = msic_gpio_to_oreg(offset);
-        if (reg < 0)
-                return reg;
-
-        return intel_msic_reg_update(reg, value, mask);
-}
-
-static int msic_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        u8 r;
-        int ret;
-        int reg;
-
-        reg = msic_gpio_to_ireg(offset);
-        if (reg < 0)
-                return reg;
-
-        ret = intel_msic_reg_read(reg, &r);
-        if (ret < 0)
-                return ret;
-
-        return r & MSIC_GPIO_DIN_MASK;
-}
-
-static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        int reg;
-
-        reg = msic_gpio_to_oreg(offset);
-        if (reg < 0)
-                return;
-
-        intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK);
-}
-
-/*
- * This is called from genirq with mg->buslock locked and
- * irq_desc->lock held. We can not access the scu bus here, so we
- * store the change and update in the bus_sync_unlock() function below
- */
-static int msic_irq_type(struct irq_data *data, unsigned type)
-{
-        struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
-        u32 gpio = data->irq - mg->irq_base;
-
-        if (gpio >= mg->chip.ngpio)
-                return -EINVAL;
-
-        /* mark for which gpio the trigger changed, protected by buslock */
-        mg->trig_change_mask |= (1 << gpio);
-        mg->trig_type = type;
-
-        return 0;
-}
-
-static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct msic_gpio *mg = container_of(chip, struct msic_gpio, chip);
-        return mg->irq_base + offset;
-}
-
-static void msic_bus_lock(struct irq_data *data)
-{
-        struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
-        mutex_lock(&mg->buslock);
-}
-
-static void msic_bus_sync_unlock(struct irq_data *data)
-{
-        struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
-        int offset;
-        int reg;
-        u8 trig = 0;
-
-        /* We can only get one change at a time as the buslock covers the
-           entire transaction. The irq_desc->lock is dropped before we are
-           called but that is fine */
-        if (mg->trig_change_mask) {
-                offset = __ffs(mg->trig_change_mask);
-
-                reg = msic_gpio_to_ireg(offset);
-                if (reg < 0)
-                        goto out;
-
-                if (mg->trig_type & IRQ_TYPE_EDGE_RISING)
-                        trig |= MSIC_GPIO_TRIG_RISE;
-                if (mg->trig_type & IRQ_TYPE_EDGE_FALLING)
-                        trig |= MSIC_GPIO_TRIG_FALL;
-
-                intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK);
-                mg->trig_change_mask = 0;
-        }
-out:
-        mutex_unlock(&mg->buslock);
-}
-
-/* Firmware does all the masking and unmasking for us, no masking here. */
-static void msic_irq_unmask(struct irq_data *data) { }
-
-static void msic_irq_mask(struct irq_data *data) { }
-
-static struct irq_chip msic_irqchip = {
-        .name                   = "MSIC-GPIO",
-        .irq_mask               = msic_irq_mask,
-        .irq_unmask             = msic_irq_unmask,
-        .irq_set_type           = msic_irq_type,
-        .irq_bus_lock           = msic_bus_lock,
-        .irq_bus_sync_unlock    = msic_bus_sync_unlock,
-};
-
-static void msic_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-{
-        struct irq_data *data = irq_desc_get_irq_data(desc);
-        struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
-        struct irq_chip *chip = irq_data_get_irq_chip(data);
-        struct intel_msic *msic = pdev_to_intel_msic(mg->pdev);
-        int i;
-        int bitnr;
-        u8 pin;
-        unsigned long pending = 0;
-
-        for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) {
-                intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin);
-                pending = pin;
-
-                if (pending) {
-                        for_each_set_bit(bitnr, &pending, BITS_PER_BYTE)
-                                generic_handle_irq(mg->irq_base +
-                                                   (i * BITS_PER_BYTE) + bitnr);
-                }
-        }
-        chip->irq_eoi(data);
-}
-
-static int platform_msic_gpio_probe(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-        struct intel_msic_gpio_pdata *pdata = dev->platform_data;
-        struct msic_gpio *mg;
-        int irq = platform_get_irq(pdev, 0);
-        int retval;
-        int i;
-
-        if (irq < 0) {
-                dev_err(dev, "no IRQ line\n");
-                return -EINVAL;
-        }
-
-        if (!pdata || !pdata->gpio_base) {
-                dev_err(dev, "incorrect or missing platform data\n");
-                return -EINVAL;
-        }
-
-        mg = kzalloc(sizeof(*mg), GFP_KERNEL);
-        if (!mg)
-                return -ENOMEM;
-
-        dev_set_drvdata(dev, mg);
-
-        mg->pdev = pdev;
-        mg->irq = irq;
-        mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET;
-        mg->chip.label = "msic_gpio";
-        mg->chip.direction_input = msic_gpio_direction_input;
-        mg->chip.direction_output = msic_gpio_direction_output;
-        mg->chip.get = msic_gpio_get;
-        mg->chip.set = msic_gpio_set;
-        mg->chip.to_irq = msic_gpio_to_irq;
-        mg->chip.base = pdata->gpio_base;
-        mg->chip.ngpio = MSIC_NUM_GPIO;
-        mg->chip.can_sleep = 1;
-        mg->chip.dev = dev;
-
-        mutex_init(&mg->buslock);
-
-        retval = gpiochip_add(&mg->chip);
-        if (retval) {
-                dev_err(dev, "Adding MSIC gpio chip failed\n");
-                goto err;
-        }
-
-        for (i = 0; i < mg->chip.ngpio; i++) {
-                irq_set_chip_data(i + mg->irq_base, mg);
-                irq_set_chip_and_handler_name(i + mg->irq_base,
-                                              &msic_irqchip,
-                                              handle_simple_irq,
-                                              "demux");
-        }
-        irq_set_chained_handler(mg->irq, msic_gpio_irq_handler);
-        irq_set_handler_data(mg->irq, mg);
-
-        return 0;
-err:
-        kfree(mg);
-        return retval;
-}
-
-static struct platform_driver platform_msic_gpio_driver = {
-        .driver = {
-                .name           = "msic_gpio",
-                .owner          = THIS_MODULE,
-        },
-        .probe          = platform_msic_gpio_probe,
-};
-
-static int __init platform_msic_gpio_init(void)
-{
-        return platform_driver_register(&platform_msic_gpio_driver);
-}
-
-subsys_initcall(platform_msic_gpio_init);
-
-MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
-MODULE_DESCRIPTION("Intel Medfield MSIC GPIO driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
index 55a7e7769af..5cb1227d69c 100644
--- a/drivers/gpio/gpio-msm-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -317,7 +317,9 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         chained_irq_enter(chip, desc);
 
-        for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
+        for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
+             i < NR_GPIO_IRQS;
+             i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
                 if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
                         generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
                                                            i));
@@ -352,7 +354,7 @@ static struct irq_chip msm_gpio_irq_chip = {
         .irq_set_wake   = msm_gpio_irq_set_wake,
 };
 
-static int msm_gpio_probe(struct platform_device *dev)
+static int __devinit msm_gpio_probe(struct platform_device *dev)
 {
         int i, irq, ret;
 
@@ -376,7 +378,7 @@ static int msm_gpio_probe(struct platform_device *dev)
         return 0;
 }
 
-static int msm_gpio_remove(struct platform_device *dev)
+static int __devexit msm_gpio_remove(struct platform_device *dev)
 {
         int ret = gpiochip_remove(&msm_gpio.gpio_chip);
 
@@ -390,7 +392,7 @@ static int msm_gpio_remove(struct platform_device *dev)
 
 static struct platform_driver msm_gpio_driver = {
         .probe = msm_gpio_probe,
-        .remove = msm_gpio_remove,
+        .remove = __devexit_p(msm_gpio_remove),
         .driver = {
                 .name = "msmgpio",
                 .owner = THIS_MODULE,
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
deleted file mode 100644
index 7d9bd94be8d..00000000000
--- a/drivers/gpio/gpio-mvebu.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/*
- * GPIO driver for Marvell SoCs
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- * Andrew Lunn <andrew@lunn.ch>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- *
- * This driver is a fairly straightforward GPIO driver for the
- * complete family of Marvell EBU SoC platforms (Orion, Dove,
- * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
- * driver is the different register layout that exists between the
- * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
- * platforms (MV78200 from the Discovery family and the Armada
- * XP). Therefore, this driver handles three variants of the GPIO
- * block:
- * - the basic variant, called "orion-gpio", with the simplest
- *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
- *   non-SMP Discovery systems
- * - the mv78200 variant for MV78200 Discovery systems. This variant
- *   turns the edge mask and level mask registers into CPU0 edge
- *   mask/level mask registers, and adds CPU1 edge mask/level mask
- *   registers.
- * - the armadaxp variant for Armada XP systems. This variant keeps
- *   the normal cause/edge mask/level mask registers when the global
- *   interrupts are used, but adds per-CPU cause/edge mask/level mask
- *   registers n a separate memory area for the per-CPU GPIO
- *   interrupts.
- */
-
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/of_irq.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/consumer.h>
-
-/*
- * GPIO unit register offsets.
- */
-#define GPIO_OUT_OFF            0x0000
-#define GPIO_IO_CONF_OFF        0x0004
-#define GPIO_BLINK_EN_OFF       0x0008
-#define GPIO_IN_POL_OFF         0x000c
-#define GPIO_DATA_IN_OFF        0x0010
-#define GPIO_EDGE_CAUSE_OFF     0x0014
-#define GPIO_EDGE_MASK_OFF      0x0018
-#define GPIO_LEVEL_MASK_OFF     0x001c
-
-/* The MV78200 has per-CPU registers for edge mask and level mask */
-#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
-#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
-
-/* The Armada XP has per-CPU registers for interrupt cause, interrupt
- * mask and interrupt level mask. Those are relative to the
- * percpu_membase. */
-#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
-#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
-#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
-
-#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
-#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
-#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
-
-#define MVEBU_MAX_GPIO_PER_BANK         32
-
-struct mvebu_gpio_chip {
-        struct gpio_chip   chip;
-        spinlock_t         lock;
-        void __iomem      *membase;
-        void __iomem      *percpu_membase;
-        unsigned int       irqbase;
-        struct irq_domain *domain;
-        int                soc_variant;
-};
-
-/*
- * Functions returning addresses of individual registers for a given
- * GPIO controller.
- */
-static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
-{
-        return mvchip->membase + GPIO_OUT_OFF;
-}
-
-static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
-{
-        return mvchip->membase + GPIO_BLINK_EN_OFF;
-}
-
-static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
-{
-        return mvchip->membase + GPIO_IO_CONF_OFF;
-}
-
-static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
-{
-        return mvchip->membase + GPIO_IN_POL_OFF;
-}
-
-static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
-{
-        return mvchip->membase + GPIO_DATA_IN_OFF;
-}
-
-static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
-{
-        int cpu;
-
-        switch(mvchip->soc_variant) {
-        case MVEBU_GPIO_SOC_VARIANT_ORION:
-        case MVEBU_GPIO_SOC_VARIANT_MV78200:
-                return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
-        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
-                cpu = smp_processor_id();
-                return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
-        default:
-                BUG();
-        }
-}
-
-static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
-{
-        int cpu;
-
-        switch(mvchip->soc_variant) {
-        case MVEBU_GPIO_SOC_VARIANT_ORION:
-                return mvchip->membase + GPIO_EDGE_MASK_OFF;
-        case MVEBU_GPIO_SOC_VARIANT_MV78200:
-                cpu = smp_processor_id();
-                return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
-        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
-                cpu = smp_processor_id();
-                return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
-        default:
-                BUG();
-        }
-}
-
-static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
-{
-        int cpu;
-
-        switch(mvchip->soc_variant) {
-        case MVEBU_GPIO_SOC_VARIANT_ORION:
-                return mvchip->membase + GPIO_LEVEL_MASK_OFF;
-        case MVEBU_GPIO_SOC_VARIANT_MV78200:
-                cpu = smp_processor_id();
-                return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
-        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
-                cpu = smp_processor_id();
-                return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
-        default:
-                BUG();
-        }
-}
-
-/*
- * Functions implementing the gpio_chip methods
- */
-
-static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
-{
-        return pinctrl_request_gpio(chip->base + pin);
-}
-
-static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
-{
-        pinctrl_free_gpio(chip->base + pin);
-}
-
-static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        unsigned long flags;
-        u32 u;
-
-        spin_lock_irqsave(&mvchip->lock, flags);
-        u = readl_relaxed(mvebu_gpioreg_out(mvchip));
-        if (value)
-                u |= 1 << pin;
-        else
-                u &= ~(1 << pin);
-        writel_relaxed(u, mvebu_gpioreg_out(mvchip));
-        spin_unlock_irqrestore(&mvchip->lock, flags);
-}
-
-static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        u32 u;
-
-        if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
-                u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
-                        readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
-        } else {
-                u = readl_relaxed(mvebu_gpioreg_out(mvchip));
-        }
-
-        return (u >> pin) & 1;
-}
-
-static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        unsigned long flags;
-        u32 u;
-
-        spin_lock_irqsave(&mvchip->lock, flags);
-        u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
-        if (value)
-                u |= 1 << pin;
-        else
-                u &= ~(1 << pin);
-        writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
-        spin_unlock_irqrestore(&mvchip->lock, flags);
-}
-
-static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        unsigned long flags;
-        int ret;
-        u32 u;
-
-        /* Check with the pinctrl driver whether this pin is usable as
-         * an input GPIO */
-        ret = pinctrl_gpio_direction_input(chip->base + pin);
-        if (ret)
-                return ret;
-
-        spin_lock_irqsave(&mvchip->lock, flags);
-        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
-        u |= 1 << pin;
-        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
-        spin_unlock_irqrestore(&mvchip->lock, flags);
-
-        return 0;
-}
-
-static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
-                                       int value)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        unsigned long flags;
-        int ret;
-        u32 u;
-
-        /* Check with the pinctrl driver whether this pin is usable as
-         * an output GPIO */
-        ret = pinctrl_gpio_direction_output(chip->base + pin);
-        if (ret)
-                return ret;
-
-        mvebu_gpio_blink(chip, pin, 0);
-        mvebu_gpio_set(chip, pin, value);
-
-        spin_lock_irqsave(&mvchip->lock, flags);
-        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
-        u &= ~(1 << pin);
-        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
-        spin_unlock_irqrestore(&mvchip->lock, flags);
-
-        return 0;
-}
-
-static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-{
-        struct mvebu_gpio_chip *mvchip =
-                container_of(chip, struct mvebu_gpio_chip, chip);
-        return irq_create_mapping(mvchip->domain, pin);
-}
-
-/*
- * Functions implementing the irq_chip methods
- */
-static void mvebu_gpio_irq_ack(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        u32 mask = ~(1 << (d->irq - gc->irq_base));
-
-        irq_gc_lock(gc);
-        writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
-        irq_gc_unlock(gc);
-}
-
-static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        u32 mask = 1 << (d->irq - gc->irq_base);
-
-        irq_gc_lock(gc);
-        gc->mask_cache &= ~mask;
-        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
-        irq_gc_unlock(gc);
-}
-
-static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        u32 mask = 1 << (d->irq - gc->irq_base);
-
-        irq_gc_lock(gc);
-        gc->mask_cache |= mask;
-        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
-        irq_gc_unlock(gc);
-}
-
-static void mvebu_gpio_level_irq_mask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        u32 mask = 1 << (d->irq - gc->irq_base);
-
-        irq_gc_lock(gc);
-        gc->mask_cache &= ~mask;
-        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
-        irq_gc_unlock(gc);
-}
-
-static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        u32 mask = 1 << (d->irq - gc->irq_base);
-
-        irq_gc_lock(gc);
-        gc->mask_cache |= mask;
-        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
-        irq_gc_unlock(gc);
-}
-
-/*****************************************************************************
- * MVEBU GPIO IRQ
- *
- * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
- * value of the line or the opposite value.
- *
- * Level IRQ handlers: DATA_IN is used directly as cause register.
- *                     Interrupt are masked by LEVEL_MASK registers.
- * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
- *                     Interrupt are masked by EDGE_MASK registers.
- * Both-edge handlers: Similar to regular Edge handlers, but also swaps
- *                     the polarity to catch the next line transaction.
- *                     This is a race condition that might not perfectly
- *                     work on some use cases.
- *
- * Every eight GPIO lines are grouped (OR'ed) before going up to main
- * cause register.
- *
- *                    EDGE  cause    mask
- *        data-in   /--------| |-----| |----\
- *     -----| |-----                         ---- to main cause reg
- *           X      \----------------| |----/
- *        polarity    LEVEL          mask
- *
- ****************************************************************************/
-
-static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-        struct mvebu_gpio_chip *mvchip = gc->private;
-        int pin;
-        u32 u;
-
-        pin = d->hwirq;
-
-        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
-        if (!u) {
-                return -EINVAL;
-        }
-
-        type &= IRQ_TYPE_SENSE_MASK;
-        if (type == IRQ_TYPE_NONE)
-                return -EINVAL;
-
-        /* Check if we need to change chip and handler */
-        if (!(ct->type & type))
-                if (irq_setup_alt_chip(d, type))
-                        return -EINVAL;
-
-        /*
-         * Configure interrupt polarity.
-         */
-        switch(type) {
-        case IRQ_TYPE_EDGE_RISING:
-        case IRQ_TYPE_LEVEL_HIGH:
-                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
-                u &= ~(1 << pin);
-                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-        case IRQ_TYPE_LEVEL_LOW:
-                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
-                u |= 1 << pin;
-                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
-                break;
-        case IRQ_TYPE_EDGE_BOTH: {
-                u32 v;
-
-                v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
-                        readl_relaxed(mvebu_gpioreg_data_in(mvchip));
-
-                /*
-                 * set initial polarity based on current input level
-                 */
-                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
-                if (v & (1 << pin))
-                        u |= 1 << pin;          /* falling */
-                else
-                        u &= ~(1 << pin);       /* rising */
-                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
-                break;
-        }
-        }
-        return 0;
-}
-
-static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
-        u32 cause, type;
-        int i;
-
-        if (mvchip == NULL)
-                return;
-
-        cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
-                readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
-        cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
-                readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
-
-        for (i = 0; i < mvchip->chip.ngpio; i++) {
-                int irq;
-
-                irq = mvchip->irqbase + i;
-
-                if (!(cause & (1 << i)))
-                        continue;
-
-                type = irqd_get_trigger_type(irq_get_irq_data(irq));
-                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-                        /* Swap polarity (race with GPIO line) */
-                        u32 polarity;
-
-                        polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
-                        polarity ^= 1 << i;
-                        writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
-                }
-                generic_handle_irq(irq);
-        }
-}
-
-static struct of_device_id mvebu_gpio_of_match[] = {
-        {
-                .compatible = "marvell,orion-gpio",
-                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
-        },
-        {
-                .compatible = "marvell,mv78200-gpio",
-                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
-        },
-        {
-                .compatible = "marvell,armadaxp-gpio",
-                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
-        },
-        {
-                /* sentinel */
-        },
-};
-MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
-
-static int mvebu_gpio_probe(struct platform_device *pdev)
-{
-        struct mvebu_gpio_chip *mvchip;
-        const struct of_device_id *match;
-        struct device_node *np = pdev->dev.of_node;
-        struct resource *res;
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-        unsigned int ngpios;
-        int soc_variant;
-        int i, cpu, id;
-
-        match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
-        if (match)
-                soc_variant = (int) match->data;
-        else
-                soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (! res) {
-                dev_err(&pdev->dev, "Cannot get memory resource\n");
-                return -ENODEV;
-        }
-
-        mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
-        if (! mvchip){
-                dev_err(&pdev->dev, "Cannot allocate memory\n");
-                return -ENOMEM;
-        }
-
-        if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
-                dev_err(&pdev->dev, "Missing ngpios OF property\n");
-                return -ENODEV;
-        }
-
-        id = of_alias_get_id(pdev->dev.of_node, "gpio");
-        if (id < 0) {
-                dev_err(&pdev->dev, "Couldn't get OF id\n");
-                return id;
-        }
-
-        mvchip->soc_variant = soc_variant;
-        mvchip->chip.label = dev_name(&pdev->dev);
-        mvchip->chip.dev = &pdev->dev;
-        mvchip->chip.request = mvebu_gpio_request;
-        mvchip->chip.free = mvebu_gpio_free;
-        mvchip->chip.direction_input = mvebu_gpio_direction_input;
-        mvchip->chip.get = mvebu_gpio_get;
-        mvchip->chip.direction_output = mvebu_gpio_direction_output;
-        mvchip->chip.set = mvebu_gpio_set;
-        mvchip->chip.to_irq = mvebu_gpio_to_irq;
-        mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
-        mvchip->chip.ngpio = ngpios;
-        mvchip->chip.can_sleep = 0;
-        mvchip->chip.of_node = np;
-
-        spin_lock_init(&mvchip->lock);
-        mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
-        if (! mvchip->membase) {
-                dev_err(&pdev->dev, "Cannot ioremap\n");
-                kfree(mvchip->chip.label);
-                return -ENOMEM;
-        }
-
-        /* The Armada XP has a second range of registers for the
-         * per-CPU registers */
-        if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-                if (! res) {
-                        dev_err(&pdev->dev, "Cannot get memory resource\n");
-                        kfree(mvchip->chip.label);
-                        return -ENODEV;
-                }
-
-                mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
-                if (! mvchip->percpu_membase) {
-                        dev_err(&pdev->dev, "Cannot ioremap\n");
-                        kfree(mvchip->chip.label);
-                        return -ENOMEM;
-                }
-        }
-
-        /*
-         * Mask and clear GPIO interrupts.
-         */
-        switch(soc_variant) {
-        case MVEBU_GPIO_SOC_VARIANT_ORION:
-                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
-                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
-                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
-                break;
-        case MVEBU_GPIO_SOC_VARIANT_MV78200:
-                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
-                for (cpu = 0; cpu < 2; cpu++) {
-                        writel_relaxed(0, mvchip->membase +
-                                       GPIO_EDGE_MASK_MV78200_OFF(cpu));
-                        writel_relaxed(0, mvchip->membase +
-                                       GPIO_LEVEL_MASK_MV78200_OFF(cpu));
-                }
-                break;
-        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
-                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
-                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
-                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
-                for (cpu = 0; cpu < 4; cpu++) {
-                        writel_relaxed(0, mvchip->percpu_membase +
-                                       GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
-                        writel_relaxed(0, mvchip->percpu_membase +
-                                       GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
-                        writel_relaxed(0, mvchip->percpu_membase +
-                                       GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
-                }
-                break;
-        default:
-                BUG();
-        }
-
-        gpiochip_add(&mvchip->chip);
-
-        /* Some gpio controllers do not provide irq support */
-        if (!of_irq_count(np))
-                return 0;
-
-        /* Setup the interrupt handlers. Each chip can have up to 4
-         * interrupt handlers, with each handler dealing with 8 GPIO
-         * pins. */
-        for (i = 0; i < 4; i++) {
-                int irq;
-                irq = platform_get_irq(pdev, i);
-                if (irq < 0)
-                        continue;
-                irq_set_handler_data(irq, mvchip);
-                irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
-        }
-
-        mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
-        if (mvchip->irqbase < 0) {
-                dev_err(&pdev->dev, "no irqs\n");
-                kfree(mvchip->chip.label);
-                return -ENOMEM;
-        }
-
-        gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
-                                    mvchip->membase, handle_level_irq);
-        if (! gc) {
-                dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
-                kfree(mvchip->chip.label);
-                return -ENOMEM;
-        }
-
-        gc->private = mvchip;
-        ct = &gc->chip_types[0];
-        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
-        ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
-        ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
-        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
-        ct->chip.name = mvchip->chip.label;
-
-        ct = &gc->chip_types[1];
-        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-        ct->chip.irq_ack = mvebu_gpio_irq_ack;
-        ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
-        ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
-        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
-        ct->handler = handle_edge_irq;
-        ct->chip.name = mvchip->chip.label;
-
-        irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
-                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
-
-        /* Setup irq domain on top of the generic chip. */
-        mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
-                                               mvchip->irqbase,
-                                               &irq_domain_simple_ops,
-                                               mvchip);
-        if (!mvchip->domain) {
-                dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
-                        mvchip->chip.label);
-                irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
-                                        IRQ_LEVEL | IRQ_NOPROBE);
-                kfree(gc);
-                kfree(mvchip->chip.label);
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
-static struct platform_driver mvebu_gpio_driver = {
-        .driver         = {
-                .name           = "mvebu-gpio",
-                .owner          = THIS_MODULE,
-                .of_match_table = mvebu_gpio_of_match,
-        },
-        .probe          = mvebu_gpio_probe,
-};
-
-static int __init mvebu_gpio_init(void)
-{
-        return platform_driver_register(&mvebu_gpio_driver);
-}
-postcore_initcall(mvebu_gpio_init);
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 7877335c4cc..4340acae3bd 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -23,22 +23,18 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/basic_mmio_gpio.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
-#include <linux/module.h>
 #include <asm-generic/bug.h>
-#include <asm/mach/irq.h>
 
 enum mxc_gpio_hwtype {
         IMX1_GPIO,      /* runs on i.mx1 */
         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
-        IMX31_GPIO,     /* runs on i.mx31 */
-        IMX35_GPIO,     /* runs on all other i.mx */
+        IMX31_GPIO,     /* runs on all other i.mx */
 };
 
 /* device type dependent stuff */
@@ -50,7 +46,6 @@ struct mxc_gpio_hwdata {
         unsigned icr2_reg;
         unsigned imr_reg;
         unsigned isr_reg;
-        int edge_sel_reg;
         unsigned low_level;
         unsigned high_level;
         unsigned rise_edge;
@@ -62,7 +57,7 @@ struct mxc_gpio_port {
         void __iomem *base;
         int irq;
         int irq_high;
-        struct irq_domain *domain;
+        int virtual_irq_start;
         struct bgpio_chip bgc;
         u32 both_edges;
 };
@@ -75,7 +70,6 @@ static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
         .icr2_reg       = 0x2c,
         .imr_reg        = 0x30,
         .isr_reg        = 0x34,
-        .edge_sel_reg   = -EINVAL,
         .low_level      = 0x03,
         .high_level     = 0x02,
         .rise_edge      = 0x00,
@@ -90,22 +84,6 @@ static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
         .icr2_reg       = 0x10,
         .imr_reg        = 0x14,
         .isr_reg        = 0x18,
-        .edge_sel_reg   = -EINVAL,
-        .low_level      = 0x00,
-        .high_level     = 0x01,
-        .rise_edge      = 0x02,
-        .fall_edge      = 0x03,
-};
-
-static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
-        .dr_reg         = 0x00,
-        .gdir_reg       = 0x04,
-        .psr_reg        = 0x08,
-        .icr1_reg       = 0x0c,
-        .icr2_reg       = 0x10,
-        .imr_reg        = 0x14,
-        .isr_reg        = 0x18,
-        .edge_sel_reg   = 0x1c,
         .low_level      = 0x00,
         .high_level     = 0x01,
         .rise_edge      = 0x02,
@@ -122,13 +100,12 @@ static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
-#define GPIO_EDGE_SEL           (mxc_gpio_hwdata->edge_sel_reg)
 
 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
-#define GPIO_INT_BOTH_EDGES     0x4
+#define GPIO_INT_NONE           0x4
 
 static struct platform_device_id mxc_gpio_devtype[] = {
         {
@@ -141,9 +118,6 @@ static struct platform_device_id mxc_gpio_devtype[] = {
                 .name = "imx31-gpio",
                 .driver_data = IMX31_GPIO,
         }, {
-                .name = "imx35-gpio",
-                .driver_data = IMX35_GPIO,
-        }, {
                 /* sentinel */
         }
 };
@@ -152,7 +126,6 @@ static const struct of_device_id mxc_gpio_dt_ids[] = {
         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
-        { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
         { /* sentinel */ }
 };
 
@@ -167,15 +140,14 @@ static LIST_HEAD(mxc_gpio_ports);
 
 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 {
+        u32 gpio = irq_to_gpio(d->irq);
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
         struct mxc_gpio_port *port = gc->private;
         u32 bit, val;
-        u32 gpio_idx = d->hwirq;
-        u32 gpio = port->bgc.gc.base + gpio_idx;
         int edge;
         void __iomem *reg = port->base;
 
-        port->both_edges &= ~(1 << gpio_idx);
+        port->both_edges &= ~(1 << (gpio & 31));
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
                 edge = GPIO_INT_RISE_EDGE;
@@ -184,19 +156,15 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
                 edge = GPIO_INT_FALL_EDGE;
                 break;
         case IRQ_TYPE_EDGE_BOTH:
-                if (GPIO_EDGE_SEL >= 0) {
-                        edge = GPIO_INT_BOTH_EDGES;
+                val = gpio_get_value(gpio);
+                if (val) {
+                        edge = GPIO_INT_LOW_LEV;
+                        pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
                 } else {
-                        val = gpio_get_value(gpio);
-                        if (val) {
-                                edge = GPIO_INT_LOW_LEV;
-                                pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
-                        } else {
-                                edge = GPIO_INT_HIGH_LEV;
-                                pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
-                        }
-                        port->both_edges |= 1 << gpio_idx;
+                        edge = GPIO_INT_HIGH_LEV;
+                        pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
                 }
+                port->both_edges |= 1 << (gpio & 31);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
                 edge = GPIO_INT_LOW_LEV;
@@ -208,24 +176,11 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
                 return -EINVAL;
         }
 
-        if (GPIO_EDGE_SEL >= 0) {
-                val = readl(port->base + GPIO_EDGE_SEL);
-                if (edge == GPIO_INT_BOTH_EDGES)
-                        writel(val | (1 << gpio_idx),
-                                port->base + GPIO_EDGE_SEL);
-                else
-                        writel(val & ~(1 << gpio_idx),
-                                port->base + GPIO_EDGE_SEL);
-        }
-
-        if (edge != GPIO_INT_BOTH_EDGES) {
-                reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
-                bit = gpio_idx & 0xf;
-                val = readl(reg) & ~(0x3 << (bit << 1));
-                writel(val | (edge << (bit << 1)), reg);
-        }
-
-        writel(1 << gpio_idx, port->base + GPIO_ISR);
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = readl(reg) & ~(0x3 << (bit << 1));
+        writel(val | (edge << (bit << 1)), reg);
+        writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
 
         return 0;
 }
@@ -258,13 +213,15 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 /* handle 32 interrupts in one status register */
 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 {
+        u32 gpio_irq_no_base = port->virtual_irq_start;
+
         while (irq_stat != 0) {
                 int irqoffset = fls(irq_stat) - 1;
 
                 if (port->both_edges & (1 << irqoffset))
                         mxc_flip_edge(port, irqoffset);
 
-                generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
 
                 irq_stat &= ~(1 << irqoffset);
         }
@@ -275,15 +232,10 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
         struct mxc_gpio_port *port = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-
-        chained_irq_enter(chip, desc);
 
         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 
         mxc_gpio_irq_handler(port, irq_stat);
-
-        chained_irq_exit(chip, desc);
 }
 
 /* MX2 has one interrupt *for all* gpio ports */
@@ -315,9 +267,10 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
  */
 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 {
+        u32 gpio = irq_to_gpio(d->irq);
+        u32 gpio_idx = gpio & 0x1F;
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
         struct mxc_gpio_port *port = gc->private;
-        u32 gpio_idx = d->hwirq;
 
         if (enable) {
                 if (port->irq_high && (gpio_idx >= 16))
@@ -334,12 +287,12 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
         return 0;
 }
 
-static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
+static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
 {
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
 
-        gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
+        gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
                                     port->base, handle_level_irq);
         gc->private = port;
 
@@ -356,7 +309,7 @@ static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
                                IRQ_NOREQUEST, 0);
 }
 
-static void mxc_gpio_get_hw(struct platform_device *pdev)
+static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
 {
         const struct of_device_id *of_id =
                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
@@ -376,9 +329,7 @@ static void mxc_gpio_get_hw(struct platform_device *pdev)
                 return;
         }
 
-        if (hwtype == IMX35_GPIO)
-                mxc_gpio_hwdata = &imx35_gpio_hwdata;
-        else if (hwtype == IMX31_GPIO)
+        if (hwtype == IMX31_GPIO)
                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
         else
                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
@@ -386,21 +337,11 @@ static void mxc_gpio_get_hw(struct platform_device *pdev)
         mxc_gpio_hwtype = hwtype;
 }
 
-static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-        struct bgpio_chip *bgc = to_bgpio_chip(gc);
-        struct mxc_gpio_port *port =
-                container_of(bgc, struct mxc_gpio_port, bgc);
-
-        return irq_find_mapping(port->domain, offset);
-}
-
-static int mxc_gpio_probe(struct platform_device *pdev)
+static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 {
         struct device_node *np = pdev->dev.of_node;
         struct mxc_gpio_port *port;
         struct resource *iores;
-        int irq_base;
         int err;
 
         mxc_gpio_get_hw(pdev);
@@ -439,12 +380,10 @@ static int mxc_gpio_probe(struct platform_device *pdev)
         writel(~0, port->base + GPIO_ISR);
 
         if (mxc_gpio_hwtype == IMX21_GPIO) {
-                /*
-                 * Setup one handler for all GPIO interrupts. Actually setting
-                 * the handler is needed only once, but doing it for every port
-                 * is more robust and easier.
-                 */
-                irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
+                /* setup one handler for all GPIO interrupts */
+                if (pdev->id == 0)
+                        irq_set_chained_handler(port->irq,
+                                                mx2_gpio_irq_handler);
         } else {
                 /* setup one handler for each entry */
                 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
@@ -460,42 +399,32 @@ static int mxc_gpio_probe(struct platform_device *pdev)
         err = bgpio_init(&port->bgc, &pdev->dev, 4,
                          port->base + GPIO_PSR,
                          port->base + GPIO_DR, NULL,
-                         port->base + GPIO_GDIR, NULL, 0);
+                         port->base + GPIO_GDIR, NULL, false);
         if (err)
                 goto out_iounmap;
 
-        port->bgc.gc.to_irq = mxc_gpio_to_irq;
-        port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
-                                             pdev->id * 32;
+        port->bgc.gc.base = pdev->id * 32;
+        port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
+        port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
 
         err = gpiochip_add(&port->bgc.gc);
         if (err)
                 goto out_bgpio_remove;
 
-        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
-        if (irq_base < 0) {
-                err = irq_base;
-                goto out_gpiochip_remove;
-        }
-
-        port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
-                                             &irq_domain_simple_ops, NULL);
-        if (!port->domain) {
-                err = -ENODEV;
-                goto out_irqdesc_free;
-        }
+        /*
+         * In dt case, we use gpio number range dynamically
+         * allocated by gpio core.
+         */
+        port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
+                                                             pdev->id * 32);
 
         /* gpio-mxc can be a generic irq chip */
-        mxc_gpio_init_gc(port, irq_base);
+        mxc_gpio_init_gc(port);
 
         list_add_tail(&port->node, &mxc_gpio_ports);
 
         return 0;
 
-out_irqdesc_free:
-        irq_free_descs(irq_base, 32);
-out_gpiochip_remove:
-        WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
 out_bgpio_remove:
         bgpio_remove(&port->bgc);
 out_iounmap:
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index fa2a63cad32..af55a8577c2 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -24,27 +24,23 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/gpio.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/basic_mmio_gpio.h>
-#include <linux/module.h>
+#include <mach/mxs.h>
 
 #define MXS_SET         0x4
 #define MXS_CLR         0x8
 
-#define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
-#define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
-#define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
-#define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
-#define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
-#define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
-#define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
-#define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
+#define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
+#define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
+#define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
+#define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
+#define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
+#define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
+#define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
+#define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
 
 #define GPIO_INT_FALL_EDGE      0x0
 #define GPIO_INT_LOW_LEV        0x1
@@ -53,35 +49,20 @@
 #define GPIO_INT_LEV_MASK       (1 << 0)
 #define GPIO_INT_POL_MASK       (1 << 1)
 
-enum mxs_gpio_id {
-        IMX23_GPIO,
-        IMX28_GPIO,
-};
-
 struct mxs_gpio_port {
         void __iomem *base;
         int id;
         int irq;
-        struct irq_domain *domain;
+        int virtual_irq_start;
         struct bgpio_chip bgc;
-        enum mxs_gpio_id devid;
 };
 
-static inline int is_imx23_gpio(struct mxs_gpio_port *port)
-{
-        return port->devid == IMX23_GPIO;
-}
-
-static inline int is_imx28_gpio(struct mxs_gpio_port *port)
-{
-        return port->devid == IMX28_GPIO;
-}
-
 /* Note: This driver assumes 32 GPIOs are handled in one register */
 
 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
-        u32 pin_mask = 1 << d->hwirq;
+        u32 gpio = irq_to_gpio(d->irq);
+        u32 pin_mask = 1 << (gpio & 31);
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
         struct mxs_gpio_port *port = gc->private;
         void __iomem *pin_addr;
@@ -105,21 +86,21 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
         }
 
         /* set level or edge */
-        pin_addr = port->base + PINCTRL_IRQLEV(port);
+        pin_addr = port->base + PINCTRL_IRQLEV(port->id);
         if (edge & GPIO_INT_LEV_MASK)
                 writel(pin_mask, pin_addr + MXS_SET);
         else
                 writel(pin_mask, pin_addr + MXS_CLR);
 
         /* set polarity */
-        pin_addr = port->base + PINCTRL_IRQPOL(port);
+        pin_addr = port->base + PINCTRL_IRQPOL(port->id);
         if (edge & GPIO_INT_POL_MASK)
                 writel(pin_mask, pin_addr + MXS_SET);
         else
                 writel(pin_mask, pin_addr + MXS_CLR);
 
-        writel(pin_mask,
-               port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
+        writel(1 << (gpio & 0x1f),
+               port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 
         return 0;
 }
@@ -129,15 +110,16 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
         struct mxs_gpio_port *port = irq_get_handler_data(irq);
+        u32 gpio_irq_no_base = port->virtual_irq_start;
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-        irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
-                        readl(port->base + PINCTRL_IRQEN(port));
+        irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+                        readl(port->base + PINCTRL_IRQEN(port->id));
 
         while (irq_stat != 0) {
                 int irqoffset = fls(irq_stat) - 1;
-                generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
                 irq_stat &= ~(1 << irqoffset);
         }
 }
@@ -164,12 +146,12 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
         return 0;
 }
 
-static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
+static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 {
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
 
-        gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
+        gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
                                     port->base, handle_level_irq);
         gc->private = port;
 
@@ -179,8 +161,8 @@ static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
-        ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
-        ct->regs.mask = PINCTRL_IRQEN(port);
+        ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
+        ct->regs.mask = PINCTRL_IRQEN(port->id);
 
         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
@@ -191,111 +173,77 @@ static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
         struct mxs_gpio_port *port =
                 container_of(bgc, struct mxs_gpio_port, bgc);
 
-        return irq_find_mapping(port->domain, offset);
+        return port->virtual_irq_start + offset;
 }
 
-static struct platform_device_id mxs_gpio_ids[] = {
-        {
-                .name = "imx23-gpio",
-                .driver_data = IMX23_GPIO,
-        }, {
-                .name = "imx28-gpio",
-                .driver_data = IMX28_GPIO,
-        }, {
-                /* sentinel */
-        }
-};
-MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
-
-static const struct of_device_id mxs_gpio_dt_ids[] = {
-        { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
-        { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
-        { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
-
-static int mxs_gpio_probe(struct platform_device *pdev)
+static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 {
-        const struct of_device_id *of_id =
-                        of_match_device(mxs_gpio_dt_ids, &pdev->dev);
-        struct device_node *np = pdev->dev.of_node;
-        struct device_node *parent;
         static void __iomem *base;
         struct mxs_gpio_port *port;
         struct resource *iores = NULL;
-        int irq_base;
         int err;
 
-        port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
+        port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
         if (!port)
                 return -ENOMEM;
 
-        if (np) {
-                port->id = of_alias_get_id(np, "gpio");
-                if (port->id < 0)
-                        return port->id;
-                port->devid = (enum mxs_gpio_id) of_id->data;
-        } else {
-                port->id = pdev->id;
-                port->devid = pdev->id_entry->driver_data;
-        }
-
-        port->irq = platform_get_irq(pdev, 0);
-        if (port->irq < 0)
-                return port->irq;
+        port->id = pdev->id;
+        port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 
         /*
          * map memory region only once, as all the gpio ports
          * share the same one
          */
         if (!base) {
-                if (np) {
-                        parent = of_get_parent(np);
-                        base = of_iomap(parent, 0);
-                        of_node_put(parent);
-                } else {
-                        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                        base = devm_request_and_ioremap(&pdev->dev, iores);
+                iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (!iores) {
+                        err = -ENODEV;
+                        goto out_kfree;
+                }
+
+                if (!request_mem_region(iores->start, resource_size(iores),
+                                        pdev->name)) {
+                        err = -EBUSY;
+                        goto out_kfree;
+                }
+
+                base = ioremap(iores->start, resource_size(iores));
+                if (!base) {
+                        err = -ENOMEM;
+                        goto out_release_mem;
                 }
-                if (!base)
-                        return -EADDRNOTAVAIL;
         }
         port->base = base;
 
+        port->irq = platform_get_irq(pdev, 0);
+        if (port->irq < 0) {
+                err = -EINVAL;
+                goto out_iounmap;
+        }
+
         /*
          * select the pin interrupt functionality but initially
          * disable the interrupts
          */
-        writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
-        writel(0, port->base + PINCTRL_IRQEN(port));
+        writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
+        writel(0, port->base + PINCTRL_IRQEN(port->id));
 
         /* clear address has to be used to clear IRQSTAT bits */
-        writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
-
-        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
-        if (irq_base < 0)
-                return irq_base;
-
-        port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
-                                             &irq_domain_simple_ops, NULL);
-        if (!port->domain) {
-                err = -ENODEV;
-                goto out_irqdesc_free;
-        }
+        writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 
         /* gpio-mxs can be a generic irq chip */
-        mxs_gpio_init_gc(port, irq_base);
+        mxs_gpio_init_gc(port);
 
         /* setup one handler for each entry */
         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
         irq_set_handler_data(port->irq, port);
 
         err = bgpio_init(&port->bgc, &pdev->dev, 4,
-                         port->base + PINCTRL_DIN(port),
-                         port->base + PINCTRL_DOUT(port), NULL,
-                         port->base + PINCTRL_DOE(port), NULL, 0);
+                         port->base + PINCTRL_DIN(port->id),
+                         port->base + PINCTRL_DOUT(port->id), NULL,
+                         port->base + PINCTRL_DOE(port->id), NULL, false);
         if (err)
-                goto out_irqdesc_free;
+                goto out_iounmap;
 
         port->bgc.gc.to_irq = mxs_gpio_to_irq;
         port->bgc.gc.base = port->id * 32;
@@ -308,8 +256,15 @@ static int mxs_gpio_probe(struct platform_device *pdev)
 
 out_bgpio_remove:
         bgpio_remove(&port->bgc);
-out_irqdesc_free:
-        irq_free_descs(irq_base, 32);
+out_iounmap:
+        if (iores)
+                iounmap(port->base);
+out_release_mem:
+        if (iores)
+                release_mem_region(iores->start, resource_size(iores));
+out_kfree:
+        kfree(port);
+        dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
         return err;
 }
 
@@ -317,10 +272,8 @@ static struct platform_driver mxs_gpio_driver = {
         .driver         = {
                 .name   = "gpio-mxs",
                 .owner  = THIS_MODULE,
-                .of_match_table = mxs_gpio_dt_ids,
         },
         .probe          = mxs_gpio_probe,
-        .id_table       = mxs_gpio_ids,
 };
 
 static int __init mxs_gpio_init(void)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f1fbedb2a6f..118ec12d2d5 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -19,46 +19,31 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/device.h>
+#include <linux/slab.h>
 #include <linux/pm_runtime.h>
-#include <linux/pm.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/irqdomain.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/gpio-omap.h>
 
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
 #include <asm/mach/irq.h>
 
-#define OFF_MODE        1
-
-static LIST_HEAD(omap_gpio_list);
-
-struct gpio_regs {
-        u32 irqenable1;
-        u32 irqenable2;
-        u32 wake_en;
-        u32 ctrl;
-        u32 oe;
-        u32 leveldetect0;
-        u32 leveldetect1;
-        u32 risingdetect;
-        u32 fallingdetect;
-        u32 dataout;
-        u32 debounce;
-        u32 debounce_en;
-};
-
 struct gpio_bank {
-        struct list_head node;
+        unsigned long pbase;
         void __iomem *base;
         u16 irq;
-        int irq_base;
-        struct irq_domain *domain;
+        u16 virtual_irq_start;
+        int method;
+        u32 suspend_wakeup;
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+        u32 saved_wakeup;
+#endif
         u32 non_wakeup_gpios;
         u32 enabled_non_wakeup_gpios;
-        struct gpio_regs context;
+
         u32 saved_datain;
+        u32 saved_fallingdetect;
+        u32 saved_risingdetect;
         u32 level_mask;
         u32 toggle_mask;
         spinlock_t lock;
@@ -66,31 +51,44 @@ struct gpio_bank {
         struct clk *dbck;
         u32 mod_usage;
         u32 dbck_enable_mask;
-        bool dbck_enabled;
         struct device *dev;
-        bool is_mpuio;
         bool dbck_flag;
-        bool loses_context;
         int stride;
         u32 width;
-        int context_loss_count;
-        int power_mode;
-        bool workaround_enabled;
 
         void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
-        int (*get_context_loss_count)(struct device *dev);
 
         struct omap_gpio_reg_offs *regs;
 };
 
+#ifdef CONFIG_ARCH_OMAP3
+struct omap3_gpio_regs {
+        u32 irqenable1;
+        u32 irqenable2;
+        u32 wake_en;
+        u32 ctrl;
+        u32 oe;
+        u32 leveldetect0;
+        u32 leveldetect1;
+        u32 risingdetect;
+        u32 fallingdetect;
+        u32 dataout;
+};
+
+static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
+#endif
+
+/*
+ * TODO: Cleanup gpio_bank usage as it is having information
+ * related to all instances of the device
+ */
+static struct gpio_bank *gpio_bank;
+
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+int gpio_bank_count;
+
 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
-#define GPIO_MOD_CTRL_BIT       BIT(0)
-
-static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
-{
-        return gpio_irq - bank->irq_base + bank->chip.base;
-}
 
 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 {
@@ -104,7 +102,6 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
         else
                 l &= ~(1 << gpio);
         __raw_writel(l, reg);
-        bank->context.oe = l;
 }
 
 
@@ -114,13 +111,10 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
         void __iomem *reg = bank->base;
         u32 l = GPIO_BIT(bank, gpio);
 
-        if (enable) {
+        if (enable)
                 reg += bank->regs->set_dataout;
-                bank->context.dataout |= l;
-        } else {
+        else
                 reg += bank->regs->clr_dataout;
-                bank->context.dataout &= ~l;
-        }
 
         __raw_writel(l, reg);
 }
@@ -138,60 +132,29 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
         else
                 l &= ~gpio_bit;
         __raw_writel(l, reg);
-        bank->context.dataout = l;
 }
 
-static int _get_gpio_datain(struct gpio_bank *bank, int offset)
+static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
 {
         void __iomem *reg = bank->base + bank->regs->datain;
 
-        return (__raw_readl(reg) & (1 << offset)) != 0;
+        return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
 }
 
-static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
+static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
 {
         void __iomem *reg = bank->base + bank->regs->dataout;
 
-        return (__raw_readl(reg) & (1 << offset)) != 0;
+        return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
 }
 
-static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
-{
-        int l = __raw_readl(base + reg);
-
-        if (set)
-                l |= mask;
-        else
-                l &= ~mask;
-
-        __raw_writel(l, base + reg);
-}
-
-static inline void _gpio_dbck_enable(struct gpio_bank *bank)
-{
-        if (bank->dbck_enable_mask && !bank->dbck_enabled) {
-                clk_enable(bank->dbck);
-                bank->dbck_enabled = true;
-
-                __raw_writel(bank->dbck_enable_mask,
-                             bank->base + bank->regs->debounce_en);
-        }
-}
-
-static inline void _gpio_dbck_disable(struct gpio_bank *bank)
-{
-        if (bank->dbck_enable_mask && bank->dbck_enabled) {
-                /*
-                 * Disable debounce before cutting it's clock. If debounce is
-                 * enabled but the clock is not, GPIO module seems to be unable
-                 * to detect events and generate interrupts at least on OMAP3.
-                 */
-                __raw_writel(0, bank->base + bank->regs->debounce_en);
-
-                clk_disable(bank->dbck);
-                bank->dbck_enabled = false;
-        }
-}
+#define MOD_REG_BIT(reg, bit_mask, set) \
+do {    \
+        int l = __raw_readl(base + reg); \
+        if (set) l |= bit_mask; \
+        else l &= ~bit_mask; \
+        __raw_writel(l, base + reg); \
+} while(0)
 
 /**
  * _set_gpio_debounce - low level gpio debounce time
@@ -221,108 +184,70 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 
         l = GPIO_BIT(bank, gpio);
 
-        clk_enable(bank->dbck);
         reg = bank->base + bank->regs->debounce;
         __raw_writel(debounce, reg);
 
         reg = bank->base + bank->regs->debounce_en;
         val = __raw_readl(reg);
 
-        if (debounce)
+        if (debounce) {
                 val |= l;
-        else
+                clk_enable(bank->dbck);
+        } else {
                 val &= ~l;
+                clk_disable(bank->dbck);
+        }
         bank->dbck_enable_mask = val;
 
         __raw_writel(val, reg);
-        clk_disable(bank->dbck);
-        /*
-         * Enable debounce clock per module.
-         * This call is mandatory because in omap_gpio_request() when
-         * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
-         * runtime callbck fails to turn on dbck because dbck_enable_mask
-         * used within _gpio_dbck_enable() is still not initialized at
-         * that point. Therefore we have to enable dbck here.
-         */
-        _gpio_dbck_enable(bank);
-        if (bank->dbck_enable_mask) {
-                bank->context.debounce = debounce;
-                bank->context.debounce_en = val;
-        }
-}
-
-/**
- * _clear_gpio_debounce - clear debounce settings for a gpio
- * @bank: the gpio bank we're acting upon
- * @gpio: the gpio number on this @gpio
- *
- * If a gpio is using debounce, then clear the debounce enable bit and if
- * this is the only gpio in this bank using debounce, then clear the debounce
- * time too. The debounce clock will also be disabled when calling this function
- * if this is the only gpio in the bank using debounce.
- */
-static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
-{
-        u32 gpio_bit = GPIO_BIT(bank, gpio);
-
-        if (!bank->dbck_flag)
-                return;
-
-        if (!(bank->dbck_enable_mask & gpio_bit))
-                return;
-
-        bank->dbck_enable_mask &= ~gpio_bit;
-        bank->context.debounce_en &= ~gpio_bit;
-        __raw_writel(bank->context.debounce_en,
-                     bank->base + bank->regs->debounce_en);
-
-        if (!bank->dbck_enable_mask) {
-                bank->context.debounce = 0;
-                __raw_writel(bank->context.debounce, bank->base +
-                             bank->regs->debounce);
-                clk_disable(bank->dbck);
-                bank->dbck_enabled = false;
-        }
 }
 
-static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
-                                                unsigned trigger)
+#ifdef CONFIG_ARCH_OMAP2PLUS
+static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+                                                int trigger)
 {
         void __iomem *base = bank->base;
         u32 gpio_bit = 1 << gpio;
 
-        _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
-                  trigger & IRQ_TYPE_LEVEL_LOW);
-        _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
-                  trigger & IRQ_TYPE_LEVEL_HIGH);
-        _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
-                  trigger & IRQ_TYPE_EDGE_RISING);
-        _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
-                  trigger & IRQ_TYPE_EDGE_FALLING);
-
-        bank->context.leveldetect0 =
-                        __raw_readl(bank->base + bank->regs->leveldetect0);
-        bank->context.leveldetect1 =
-                        __raw_readl(bank->base + bank->regs->leveldetect1);
-        bank->context.risingdetect =
-                        __raw_readl(bank->base + bank->regs->risingdetect);
-        bank->context.fallingdetect =
-                        __raw_readl(bank->base + bank->regs->fallingdetect);
-
+        if (cpu_is_omap44xx()) {
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        } else {
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        }
         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
-                bank->context.wake_en =
-                        __raw_readl(bank->base + bank->regs->wkup_en);
+                if (cpu_is_omap44xx()) {
+                        MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
+                                trigger != 0);
+                } else {
+                        /*
+                         * GPIO wakeup request can only be generated on edge
+                         * transitions
+                         */
+                        if (trigger & IRQ_TYPE_EDGE_BOTH)
+                                __raw_writel(1 << gpio, bank->base
+                                        + OMAP24XX_GPIO_SETWKUENA);
+                        else
+                                __raw_writel(1 << gpio, bank->base
+                                        + OMAP24XX_GPIO_CLEARWKUENA);
+                }
         }
-
         /* This part needs to be executed always for OMAP{34xx, 44xx} */
-        if (!bank->regs->irqctrl) {
-                /* On omap24xx proceed only when valid GPIO bit is set */
-                if (bank->non_wakeup_gpios) {
-                        if (!(bank->non_wakeup_gpios & gpio_bit))
-                                goto exit;
-                }
-
+        if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
+                        (bank->non_wakeup_gpios & gpio_bit)) {
                 /*
                  * Log the edge gpio and manually trigger the IRQ
                  * after resume if the input level changes
@@ -335,11 +260,17 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
         }
 
-exit:
-        bank->level_mask =
-                __raw_readl(bank->base + bank->regs->leveldetect0) |
-                __raw_readl(bank->base + bank->regs->leveldetect1);
+        if (cpu_is_omap44xx()) {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+        } else {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        }
 }
+#endif
 
 #ifdef CONFIG_ARCH_OMAP1
 /*
@@ -351,10 +282,23 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
         void __iomem *reg = bank->base;
         u32 l = 0;
 
-        if (!bank->regs->irqctrl)
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
+                break;
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_INT_CONTROL;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
+                break;
+#endif
+        default:
                 return;
-
-        reg += bank->regs->irqctrl;
+        }
 
         l = __raw_readl(reg);
         if ((l >> gpio) & 1)
@@ -364,22 +308,17 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 
         __raw_writel(l, reg);
 }
-#else
-static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 #endif
 
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
-                                                        unsigned trigger)
+static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 {
         void __iomem *reg = bank->base;
-        void __iomem *base = bank->base;
         u32 l = 0;
 
-        if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
-                set_gpio_trigger(bank, gpio, trigger);
-        } else if (bank->regs->irqctrl) {
-                reg += bank->regs->irqctrl;
-
+        switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP1
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
                 l = __raw_readl(reg);
                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                         bank->toggle_mask |= 1 << gpio;
@@ -388,15 +327,29 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
                         l &= ~(1 << gpio);
                 else
-                        return -EINVAL;
-
-                __raw_writel(l, reg);
-        } else if (bank->regs->edgectrl1) {
+                        goto bad;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_INT_CONTROL;
+                l = __raw_readl(reg);
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
+                if (trigger & IRQ_TYPE_EDGE_RISING)
+                        l |= 1 << gpio;
+                else if (trigger & IRQ_TYPE_EDGE_FALLING)
+                        l &= ~(1 << gpio);
+                else
+                        goto bad;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+        case METHOD_GPIO_1610:
                 if (gpio & 0x08)
-                        reg += bank->regs->edgectrl2;
+                        reg += OMAP1610_GPIO_EDGE_CTRL2;
                 else
-                        reg += bank->regs->edgectrl1;
-
+                        reg += OMAP1610_GPIO_EDGE_CTRL1;
                 gpio &= 0x07;
                 l = __raw_readl(reg);
                 l &= ~(3 << (gpio << 1));
@@ -404,38 +357,63 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
                         l |= 2 << (gpio << 1);
                 if (trigger & IRQ_TYPE_EDGE_FALLING)
                         l |= 1 << (gpio << 1);
-
-                /* Enable wake-up during idle for dynamic tick */
-                _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
-                bank->context.wake_en =
-                        __raw_readl(bank->base + bank->regs->wkup_en);
-                __raw_writel(l, reg);
+                if (trigger)
+                        /* Enable wake-up during idle for dynamic tick */
+                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
+                else
+                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        case METHOD_GPIO_7XX:
+                reg += OMAP7XX_GPIO_INT_CONTROL;
+                l = __raw_readl(reg);
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                        bank->toggle_mask |= 1 << gpio;
+                if (trigger & IRQ_TYPE_EDGE_RISING)
+                        l |= 1 << gpio;
+                else if (trigger & IRQ_TYPE_EDGE_FALLING)
+                        l &= ~(1 << gpio);
+                else
+                        goto bad;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP2PLUS
+        case METHOD_GPIO_24XX:
+        case METHOD_GPIO_44XX:
+                set_24xx_gpio_triggering(bank, gpio, trigger);
+                return 0;
+#endif
+        default:
+                goto bad;
         }
+        __raw_writel(l, reg);
         return 0;
+bad:
+        return -EINVAL;
 }
 
 static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned gpio = 0;
+        struct gpio_bank *bank;
+        unsigned gpio;
         int retval;
         unsigned long flags;
 
-#ifdef CONFIG_ARCH_OMAP1
-        if (d->irq > IH_MPUIO_BASE)
+        if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
                 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-#endif
-
-        if (!gpio)
-                gpio = irq_to_gpio(bank, d->irq);
+        else
+                gpio = d->irq - IH_GPIO_BASE;
 
         if (type & ~IRQ_TYPE_SENSE_MASK)
                 return -EINVAL;
 
-        if (!bank->regs->leveldetect0 &&
-                (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
+        /* OMAP1 allows only only edge triggering */
+        if (!cpu_class_is_omap2()
+                        && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
                 return -EINVAL;
 
+        bank = irq_data_get_irq_chip_data(d);
         spin_lock_irqsave(&bank->lock, flags);
         retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
         spin_unlock_irqrestore(&bank->lock, flags);
@@ -492,7 +470,6 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         if (bank->regs->set_irqenable) {
                 reg += bank->regs->set_irqenable;
                 l = gpio_mask;
-                bank->context.irqenable1 |= gpio_mask;
         } else {
                 reg += bank->regs->irqenable;
                 l = __raw_readl(reg);
@@ -500,7 +477,6 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                         l &= ~gpio_mask;
                 else
                         l |= gpio_mask;
-                bank->context.irqenable1 = l;
         }
 
         __raw_writel(l, reg);
@@ -514,7 +490,6 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         if (bank->regs->clr_irqenable) {
                 reg += bank->regs->clr_irqenable;
                 l = gpio_mask;
-                bank->context.irqenable1 &= ~gpio_mask;
         } else {
                 reg += bank->regs->irqenable;
                 l = __raw_readl(reg);
@@ -522,7 +497,6 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                         l |= gpio_mask;
                 else
                         l &= ~gpio_mask;
-                bank->context.irqenable1 = l;
         }
 
         __raw_writel(l, reg);
@@ -530,10 +504,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 {
-        if (enable)
-                _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
-        else
-                _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+        _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 }
 
 /*
@@ -550,18 +521,17 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
         unsigned long flags;
 
         if (bank->non_wakeup_gpios & gpio_bit) {
-                dev_err(bank->dev,
+                dev_err(bank->dev, 
                         "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
                 return -EINVAL;
         }
 
         spin_lock_irqsave(&bank->lock, flags);
         if (enable)
-                bank->context.wake_en |= gpio_bit;
+                bank->suspend_wakeup |= gpio_bit;
         else
-                bank->context.wake_en &= ~gpio_bit;
+                bank->suspend_wakeup &= ~gpio_bit;
 
-        __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -573,16 +543,19 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
         _set_gpio_irqenable(bank, gpio, 0);
         _clear_gpio_irqstatus(bank, gpio);
         _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
-        _clear_gpio_debounce(bank, gpio);
 }
 
 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int gpio = irq_to_gpio(bank, d->irq);
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
+        struct gpio_bank *bank;
+        int retval;
 
-        return _set_gpio_wakeup(bank, gpio, enable);
+        bank = irq_data_get_irq_chip_data(d);
+        retval = _set_gpio_wakeup(bank, gpio, enable);
+
+        return retval;
 }
 
 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -590,39 +563,38 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
         unsigned long flags;
 
-        /*
-         * If this is the first gpio_request for the bank,
-         * enable the bank module.
-         */
-        if (!bank->mod_usage)
-                pm_runtime_get_sync(bank->dev);
-
         spin_lock_irqsave(&bank->lock, flags);
+
         /* Set trigger to none. You need to enable the desired trigger with
          * request_irq() or set_irq_type().
          */
         _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 
-        if (bank->regs->pinctrl) {
-                void __iomem *reg = bank->base + bank->regs->pinctrl;
+#ifdef CONFIG_ARCH_OMAP15XX
+        if (bank->method == METHOD_GPIO_1510) {
+                void __iomem *reg;
 
                 /* Claim the pin for MPU */
+                reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
                 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
         }
-
-        if (bank->regs->ctrl && !bank->mod_usage) {
-                void __iomem *reg = bank->base + bank->regs->ctrl;
-                u32 ctrl;
-
-                ctrl = __raw_readl(reg);
-                /* Module is enabled, clocks are not gated */
-                ctrl &= ~GPIO_MOD_CTRL_BIT;
-                __raw_writel(ctrl, reg);
-                bank->context.ctrl = ctrl;
+#endif
+        if (!cpu_class_is_omap1()) {
+                if (!bank->mod_usage) {
+                        void __iomem *reg = bank->base;
+                        u32 ctrl;
+
+                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                                reg += OMAP24XX_GPIO_CTRL;
+                        else if (cpu_is_omap44xx())
+                                reg += OMAP4_GPIO_CTRL;
+                        ctrl = __raw_readl(reg);
+                        /* Module is enabled, clocks are not gated */
+                        ctrl &= 0xFFFFFFFE;
+                        __raw_writel(ctrl, reg);
+                }
+                bank->mod_usage |= 1 << offset;
         }
-
-        bank->mod_usage |= 1 << offset;
-
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -631,40 +603,48 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 {
         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-        void __iomem *base = bank->base;
         unsigned long flags;
 
         spin_lock_irqsave(&bank->lock, flags);
-
-        if (bank->regs->wkup_en) {
+#ifdef CONFIG_ARCH_OMAP16XX
+        if (bank->method == METHOD_GPIO_1610) {
                 /* Disable wake-up during idle for dynamic tick */
-                _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
-                bank->context.wake_en =
-                        __raw_readl(bank->base + bank->regs->wkup_en);
+                void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                __raw_writel(1 << offset, reg);
         }
-
-        bank->mod_usage &= ~(1 << offset);
-
-        if (bank->regs->ctrl && !bank->mod_usage) {
-                void __iomem *reg = bank->base + bank->regs->ctrl;
-                u32 ctrl;
-
-                ctrl = __raw_readl(reg);
-                /* Module is disabled, clocks are gated */
-                ctrl |= GPIO_MOD_CTRL_BIT;
-                __raw_writel(ctrl, reg);
-                bank->context.ctrl = ctrl;
+#endif
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+        if (bank->method == METHOD_GPIO_24XX) {
+                /* Disable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+                __raw_writel(1 << offset, reg);
+        }
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        if (bank->method == METHOD_GPIO_44XX) {
+                /* Disable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                __raw_writel(1 << offset, reg);
+        }
+#endif
+        if (!cpu_class_is_omap1()) {
+                bank->mod_usage &= ~(1 << offset);
+                if (!bank->mod_usage) {
+                        void __iomem *reg = bank->base;
+                        u32 ctrl;
+
+                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                                reg += OMAP24XX_GPIO_CTRL;
+                        else if (cpu_is_omap44xx())
+                                reg += OMAP4_GPIO_CTRL;
+                        ctrl = __raw_readl(reg);
+                        /* Module is disabled, clocks are gated */
+                        ctrl |= 1;
+                        __raw_writel(ctrl, reg);
+                }
         }
-
         _reset_gpio(bank, bank->chip.base + offset);
         spin_unlock_irqrestore(&bank->lock, flags);
-
-        /*
-         * If this is the last gpio to be freed in the bank,
-         * disable the bank module.
-         */
-        if (!bank->mod_usage)
-                pm_runtime_put(bank->dev);
 }
 
 /*
@@ -682,6 +662,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         u32 isr;
         unsigned int gpio_irq, gpio_index;
         struct gpio_bank *bank;
+        u32 retrigger = 0;
         int unmasked = 0;
         struct irq_chip *chip = irq_desc_get_chip(desc);
 
@@ -689,7 +670,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         bank = irq_get_handler_data(irq);
         isr_reg = bank->base + bank->regs->irqstatus;
-        pm_runtime_get_sync(bank->dev);
 
         if (WARN_ON(!isr_reg))
                 goto exit;
@@ -701,8 +681,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 enabled = _get_gpio_irqbank_mask(bank);
                 isr_saved = isr = __raw_readl(isr_reg) & enabled;
 
-                if (bank->level_mask)
+                if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
+                        isr &= 0x0000ffff;
+
+                if (cpu_class_is_omap2()) {
                         level_mask = bank->level_mask & enabled;
+                }
 
                 /* clear edge sensitive interrupts before handler(s) are
                 called so that we don't miss any interrupt occurred while
@@ -718,18 +702,19 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         chained_irq_exit(chip, desc);
                 }
 
+                isr |= retrigger;
+                retrigger = 0;
                 if (!isr)
                         break;
 
-                gpio_irq = bank->irq_base;
+                gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
-                        int gpio = irq_to_gpio(bank, gpio_irq);
+                        gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
 
                         if (!(isr & 1))
                                 continue;
 
-                        gpio_index = GPIO_INDEX(bank, gpio);
-
+#ifdef CONFIG_ARCH_OMAP1
                         /*
                          * Some chips can't respond to both rising and falling
                          * at the same time.  If this irq was requested with
@@ -739,6 +724,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                          */
                         if (bank->toggle_mask & (1 << gpio_index))
                                 _toggle_gpio_edge_triggering(bank, gpio_index);
+#endif
 
                         generic_handle_irq(gpio_irq);
                 }
@@ -750,13 +736,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 exit:
         if (!unmasked)
                 chained_irq_exit(chip, desc);
-        pm_runtime_put(bank->dev);
 }
 
 static void gpio_irq_shutdown(struct irq_data *d)
 {
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int gpio = irq_to_gpio(bank, d->irq);
         unsigned long flags;
 
         spin_lock_irqsave(&bank->lock, flags);
@@ -766,16 +751,16 @@ static void gpio_irq_shutdown(struct irq_data *d)
 
 static void gpio_ack_irq(struct irq_data *d)
 {
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int gpio = irq_to_gpio(bank, d->irq);
 
         _clear_gpio_irqstatus(bank, gpio);
 }
 
 static void gpio_mask_irq(struct irq_data *d)
 {
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int gpio = irq_to_gpio(bank, d->irq);
         unsigned long flags;
 
         spin_lock_irqsave(&bank->lock, flags);
@@ -786,8 +771,8 @@ static void gpio_mask_irq(struct irq_data *d)
 
 static void gpio_unmask_irq(struct irq_data *d)
 {
+        unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int gpio = irq_to_gpio(bank, d->irq);
         unsigned int irq_mask = GPIO_BIT(bank, gpio);
         u32 trigger = irqd_get_trigger_type(d);
         unsigned long flags;
@@ -819,6 +804,14 @@ static struct irq_chip gpio_irq_chip = {
 
 /*---------------------------------------------------------------------*/
 
+#ifdef CONFIG_ARCH_OMAP1
+
+#define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
+
+#ifdef CONFIG_ARCH_OMAP16XX
+
+#include <linux/platform_device.h>
+
 static int omap_mpuio_suspend_noirq(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
@@ -828,7 +821,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
         unsigned long           flags;
 
         spin_lock_irqsave(&bank->lock, flags);
-        __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
+        bank->saved_wakeup = __raw_readl(mask_reg);
+        __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -843,7 +837,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
         unsigned long           flags;
 
         spin_lock_irqsave(&bank->lock, flags);
-        __raw_writel(bank->context.wake_en, mask_reg);
+        __raw_writel(bank->saved_wakeup, mask_reg);
         spin_unlock_irqrestore(&bank->lock, flags);
 
         return 0;
@@ -871,16 +865,32 @@ static struct platform_device omap_mpuio_device = {
         /* could list the /proc/iomem resources */
 };
 
-static inline void mpuio_init(struct gpio_bank *bank)
+static inline void mpuio_init(void)
 {
+        struct gpio_bank *bank = &gpio_bank[0];
         platform_set_drvdata(&omap_mpuio_device, bank);
 
         if (platform_driver_register(&omap_mpuio_driver) == 0)
                 (void) platform_device_register(&omap_mpuio_device);
 }
 
+#else
+static inline void mpuio_init(void) {}
+#endif  /* 16xx */
+
+#else
+
+#define bank_is_mpuio(bank)     0
+static inline void mpuio_init(void) {}
+
+#endif
+
 /*---------------------------------------------------------------------*/
 
+/* REVISIT these are stupid implementations!  replace by ones that
+ * don't switch on METHOD_* and which mostly avoid spinlocks
+ */
+
 static int gpio_input(struct gpio_chip *chip, unsigned offset)
 {
         struct gpio_bank *bank;
@@ -903,15 +913,19 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
         struct gpio_bank *bank;
+        void __iomem *reg;
+        int gpio;
         u32 mask;
 
+        gpio = chip->base + offset;
         bank = container_of(chip, struct gpio_bank, chip);
-        mask = (1 << offset);
+        reg = bank->base;
+        mask = GPIO_BIT(bank, gpio);
 
         if (gpio_is_input(bank, mask))
-                return _get_gpio_datain(bank, offset);
+                return _get_gpio_datain(bank, gpio);
         else
-                return _get_gpio_dataout(bank, offset);
+                return _get_gpio_dataout(bank, gpio);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -935,6 +949,12 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
 
         bank = container_of(chip, struct gpio_bank, chip);
 
+        if (!bank->dbck) {
+                bank->dbck = clk_get(bank->dev, "dbclk");
+                if (IS_ERR(bank->dbck))
+                        dev_err(bank->dev, "Could not get gpio dbck\n");
+        }
+
         spin_lock_irqsave(&bank->lock, flags);
         _set_gpio_debounce(bank, offset, debounce);
         spin_unlock_irqrestore(&bank->lock, flags);
@@ -958,7 +978,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
         struct gpio_bank *bank;
 
         bank = container_of(chip, struct gpio_bank, chip);
-        return bank->irq_base + offset;
+        return bank->virtual_irq_start + offset;
 }
 
 /*---------------------------------------------------------------------*/
@@ -983,36 +1003,81 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
  */
 static struct lock_class_key gpio_lock_class;
 
-static void omap_gpio_mod_init(struct gpio_bank *bank)
+static inline int init_gpio_info(struct platform_device *pdev)
 {
-        void __iomem *base = bank->base;
-        u32 l = 0xffffffff;
-
-        if (bank->width == 16)
-                l = 0xffff;
-
-        if (bank->is_mpuio) {
-                __raw_writel(l, bank->base + bank->regs->irqenable);
-                return;
+        /* TODO: Analyze removing gpio_bank_count usage from driver code */
+        gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
+                                GFP_KERNEL);
+        if (!gpio_bank) {
+                dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
+                return -ENOMEM;
         }
+        return 0;
+}
 
-        _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
-        _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
-        if (bank->regs->debounce_en)
-                __raw_writel(0, base + bank->regs->debounce_en);
-
-        /* Save OE default value (0xffffffff) in the context */
-        bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
-         /* Initialize interface clk ungated, module enabled */
-        if (bank->regs->ctrl)
-                __raw_writel(0, base + bank->regs->ctrl);
+/* TODO: Cleanup cpu_is_* checks */
+static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+{
+        if (cpu_class_is_omap2()) {
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(0xffffffff, bank->base +
+                                        OMAP4_GPIO_IRQSTATUSCLR0);
+                        __raw_writel(0x00000000, bank->base +
+                                         OMAP4_GPIO_DEBOUNCENABLE);
+                        /* Initialize interface clk ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                } else if (cpu_is_omap34xx()) {
+                        __raw_writel(0x00000000, bank->base +
+                                        OMAP24XX_GPIO_IRQENABLE1);
+                        __raw_writel(0xffffffff, bank->base +
+                                        OMAP24XX_GPIO_IRQSTATUS1);
+                        __raw_writel(0x00000000, bank->base +
+                                        OMAP24XX_GPIO_DEBOUNCE_EN);
+
+                        /* Initialize interface clk ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+                } else if (cpu_is_omap24xx()) {
+                        static const u32 non_wakeup_gpios[] = {
+                                0xe203ffc0, 0x08700040
+                        };
+                        if (id < ARRAY_SIZE(non_wakeup_gpios))
+                                bank->non_wakeup_gpios = non_wakeup_gpios[id];
+                }
+        } else if (cpu_class_is_omap1()) {
+                if (bank_is_mpuio(bank))
+                        __raw_writew(0xffff, bank->base +
+                                OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+                if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
+                        __raw_writew(0xffff, bank->base
+                                                + OMAP1510_GPIO_INT_MASK);
+                        __raw_writew(0x0000, bank->base
+                                                + OMAP1510_GPIO_INT_STATUS);
+                }
+                if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
+                        __raw_writew(0x0000, bank->base
+                                                + OMAP1610_GPIO_IRQENABLE1);
+                        __raw_writew(0xffff, bank->base
+                                                + OMAP1610_GPIO_IRQSTATUS1);
+                        __raw_writew(0x0014, bank->base
+                                                + OMAP1610_GPIO_SYSCONFIG);
 
-        bank->dbck = clk_get(bank->dev, "dbclk");
-        if (IS_ERR(bank->dbck))
-                dev_err(bank->dev, "Could not get gpio dbck\n");
+                        /*
+                         * Enable system clock for GPIO module.
+                         * The CAM_CLK_CTRL *is* really the right place.
+                         */
+                        omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+                                                ULPD_CAM_CLK_CTRL);
+                }
+                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+                        __raw_writel(0xffffffff, bank->base
+                                                + OMAP7XX_GPIO_INT_MASK);
+                        __raw_writel(0x00000000, bank->base
+                                                + OMAP7XX_GPIO_INT_STATUS);
+                }
+        }
 }
 
-static void
+static __init void
 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
                     unsigned int num)
 {
@@ -1021,19 +1086,14 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
 
         gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
                                     handle_simple_irq);
-        if (!gc) {
-                dev_err(bank->dev, "Memory alloc failed for gc\n");
-                return;
-        }
-
         ct = gc->chip_types;
 
         /* NOTE: No ack required, reading IRQ status clears it. */
         ct->chip.irq_mask = irq_gc_mask_set_bit;
         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
         ct->chip.irq_set_type = gpio_irq_type;
-
-        if (bank->regs->wkup_en)
+        /* REVISIT: assuming only 16xx supports MPUIO wake events */
+        if (cpu_is_omap16xx())
                 ct->chip.irq_set_wake = gpio_wake_enable,
 
         ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
@@ -1041,11 +1101,12 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-static void omap_gpio_chip_init(struct gpio_bank *bank)
+static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
 {
         int j;
         static int gpio;
 
+        bank->mod_usage = 0;
         /*
          * REVISIT eventually switch from OMAP-specific gpio structs
          * over to the generic ones
@@ -1058,10 +1119,11 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
         bank->chip.set_debounce = gpio_debounce;
         bank->chip.set = gpio_set;
         bank->chip.to_irq = gpio_2irq;
-        if (bank->is_mpuio) {
+        if (bank_is_mpuio(bank)) {
                 bank->chip.label = "mpuio";
-                if (bank->regs->wkup_en)
-                        bank->chip.dev = &omap_mpuio_device.dev;
+#ifdef CONFIG_ARCH_OMAP16XX
+                bank->chip.dev = &omap_mpuio_device.dev;
+#endif
                 bank->chip.base = OMAP_MPUIO(0);
         } else {
                 bank->chip.label = "gpio";
@@ -1072,10 +1134,11 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
 
         gpiochip_add(&bank->chip);
 
-        for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
+        for (j = bank->virtual_irq_start;
+                     j < bank->virtual_irq_start + bank->width; j++) {
                 irq_set_lockdep_class(j, &gpio_lock_class);
                 irq_set_chip_data(j, bank);
-                if (bank->is_mpuio) {
+                if (bank_is_mpuio(bank)) {
                         omap_mpuio_alloc_gc(bank, j, bank->width);
                 } else {
                         irq_set_chip(j, &gpio_irq_chip);
@@ -1087,57 +1150,45 @@ static void omap_gpio_chip_init(struct gpio_bank *bank)
         irq_set_handler_data(bank->irq, bank);
 }
 
-static const struct of_device_id omap_gpio_match[];
-
-static int omap_gpio_probe(struct platform_device *pdev)
+static int __devinit omap_gpio_probe(struct platform_device *pdev)
 {
-        struct device *dev = &pdev->dev;
-        struct device_node *node = dev->of_node;
-        const struct of_device_id *match;
-        const struct omap_gpio_platform_data *pdata;
+        static int gpio_init_done;
+        struct omap_gpio_platform_data *pdata;
         struct resource *res;
+        int id;
         struct gpio_bank *bank;
-        int ret = 0;
 
-        match = of_match_device(of_match_ptr(omap_gpio_match), dev);
-
-        pdata = match ? match->data : dev->platform_data;
-        if (!pdata)
+        if (!pdev->dev.platform_data)
                 return -EINVAL;
 
-        bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
-        if (!bank) {
-                dev_err(dev, "Memory alloc failed\n");
-                return -ENOMEM;
+        pdata = pdev->dev.platform_data;
+
+        if (!gpio_init_done) {
+                int ret;
+
+                ret = init_gpio_info(pdev);
+                if (ret)
+                        return ret;
         }
 
+        id = pdev->id;
+        bank = &gpio_bank[id];
+
         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (unlikely(!res)) {
-                dev_err(dev, "Invalid IRQ resource\n");
+                dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
                 return -ENODEV;
         }
 
         bank->irq = res->start;
-        bank->dev = dev;
+        bank->virtual_irq_start = pdata->virtual_irq_start;
+        bank->method = pdata->bank_type;
+        bank->dev = &pdev->dev;
         bank->dbck_flag = pdata->dbck_flag;
         bank->stride = pdata->bank_stride;
         bank->width = pdata->bank_width;
-        bank->is_mpuio = pdata->is_mpuio;
-        bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
-        bank->loses_context = pdata->loses_context;
-        bank->regs = pdata->regs;
-#ifdef CONFIG_OF_GPIO
-        bank->chip.of_node = of_node_get(node);
-#endif
 
-        bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
-        if (bank->irq_base < 0) {
-                dev_err(dev, "Couldn't allocate IRQ numbers\n");
-                return -ENODEV;
-        }
-
-        bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
-                                             0, &irq_domain_simple_ops, NULL);
+        bank->regs = pdata->regs;
 
         if (bank->regs->set_dataout && bank->regs->clr_dataout)
                 bank->set_dataout = _set_gpio_dataout_reg;
@@ -1149,375 +1200,369 @@ static int omap_gpio_probe(struct platform_device *pdev)
         /* Static mapping, never released */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (unlikely(!res)) {
-                dev_err(dev, "Invalid mem resource\n");
+                dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
                 return -ENODEV;
         }
 
-        if (!devm_request_mem_region(dev, res->start, resource_size(res),
-                                     pdev->name)) {
-                dev_err(dev, "Region already claimed\n");
-                return -EBUSY;
-        }
-
-        bank->base = devm_ioremap(dev, res->start, resource_size(res));
+        bank->base = ioremap(res->start, resource_size(res));
         if (!bank->base) {
-                dev_err(dev, "Could not ioremap\n");
+                dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
                 return -ENOMEM;
         }
 
-        platform_set_drvdata(pdev, bank);
-
         pm_runtime_enable(bank->dev);
-        pm_runtime_irq_safe(bank->dev);
         pm_runtime_get_sync(bank->dev);
 
-        if (bank->is_mpuio)
-                mpuio_init(bank);
-
-        omap_gpio_mod_init(bank);
+        omap_gpio_mod_init(bank, id);
         omap_gpio_chip_init(bank);
         omap_gpio_show_rev(bank);
 
-        if (bank->loses_context)
-                bank->get_context_loss_count = pdata->get_context_loss_count;
-
-        pm_runtime_put(bank->dev);
+        if (!gpio_init_done)
+                gpio_init_done = 1;
 
-        list_add_tail(&bank->node, &omap_gpio_list);
-
-        return ret;
+        return 0;
 }
 
-#ifdef CONFIG_ARCH_OMAP2PLUS
-
-#if defined(CONFIG_PM_RUNTIME)
-static void omap_gpio_restore_context(struct gpio_bank *bank);
-
-static int omap_gpio_runtime_suspend(struct device *dev)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+static int omap_gpio_suspend(void)
 {
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank *bank = platform_get_drvdata(pdev);
-        u32 l1 = 0, l2 = 0;
-        unsigned long flags;
-        u32 wake_low, wake_hi;
-
-        spin_lock_irqsave(&bank->lock, flags);
+        int i;
 
-        /*
-         * Only edges can generate a wakeup event to the PRCM.
-         *
-         * Therefore, ensure any wake-up capable GPIOs have
-         * edge-detection enabled before going idle to ensure a wakeup
-         * to the PRCM is generated on a GPIO transition. (c.f. 34xx
-         * NDA TRM 25.5.3.1)
-         *
-         * The normal values will be restored upon ->runtime_resume()
-         * by writing back the values saved in bank->context.
-         */
-        wake_low = bank->context.leveldetect0 & bank->context.wake_en;
-        if (wake_low)
-                __raw_writel(wake_low | bank->context.fallingdetect,
-                             bank->base + bank->regs->fallingdetect);
-        wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
-        if (wake_hi)
-                __raw_writel(wake_hi | bank->context.risingdetect,
-                             bank->base + bank->regs->risingdetect);
-
-        if (!bank->enabled_non_wakeup_gpios)
-                goto update_gpio_context_count;
-
-        if (bank->power_mode != OFF_MODE) {
-                bank->power_mode = 0;
-                goto update_gpio_context_count;
-        }
-        /*
-         * If going to OFF, remove triggering for all
-         * non-wakeup GPIOs.  Otherwise spurious IRQs will be
-         * generated.  See OMAP2420 Errata item 1.101.
-         */
-        bank->saved_datain = __raw_readl(bank->base +
-                                                bank->regs->datain);
-        l1 = bank->context.fallingdetect;
-        l2 = bank->context.risingdetect;
-
-        l1 &= ~bank->enabled_non_wakeup_gpios;
-        l2 &= ~bank->enabled_non_wakeup_gpios;
-
-        __raw_writel(l1, bank->base + bank->regs->fallingdetect);
-        __raw_writel(l2, bank->base + bank->regs->risingdetect);
-
-        bank->workaround_enabled = true;
+        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
+                return 0;
 
-update_gpio_context_count:
-        if (bank->get_context_loss_count)
-                bank->context_loss_count =
-                                bank->get_context_loss_count(bank->dev);
+        for (i = 0; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                void __iomem *wake_status;
+                void __iomem *wake_clear;
+                void __iomem *wake_set;
+                unsigned long flags;
+
+                switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP16XX
+                case METHOD_GPIO_1610:
+                        wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
+                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                        break;
+#endif
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+                case METHOD_GPIO_24XX:
+                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
+                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+                        break;
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_44XX:
+                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
+                default:
+                        continue;
+                }
 
-        _gpio_dbck_disable(bank);
-        spin_unlock_irqrestore(&bank->lock, flags);
+                spin_lock_irqsave(&bank->lock, flags);
+                bank->saved_wakeup = __raw_readl(wake_status);
+                __raw_writel(0xffffffff, wake_clear);
+                __raw_writel(bank->suspend_wakeup, wake_set);
+                spin_unlock_irqrestore(&bank->lock, flags);
+        }
 
         return 0;
 }
 
-static int omap_gpio_runtime_resume(struct device *dev)
+static void omap_gpio_resume(void)
 {
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank *bank = platform_get_drvdata(pdev);
-        int context_lost_cnt_after;
-        u32 l = 0, gen, gen0, gen1;
-        unsigned long flags;
+        int i;
 
-        spin_lock_irqsave(&bank->lock, flags);
-        _gpio_dbck_enable(bank);
+        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
+                return;
 
-        /*
-         * In ->runtime_suspend(), level-triggered, wakeup-enabled
-         * GPIOs were set to edge trigger also in order to be able to
-         * generate a PRCM wakeup.  Here we restore the
-         * pre-runtime_suspend() values for edge triggering.
-         */
-        __raw_writel(bank->context.fallingdetect,
-                     bank->base + bank->regs->fallingdetect);
-        __raw_writel(bank->context.risingdetect,
-                     bank->base + bank->regs->risingdetect);
-
-        if (bank->get_context_loss_count) {
-                context_lost_cnt_after =
-                        bank->get_context_loss_count(bank->dev);
-                if (context_lost_cnt_after != bank->context_loss_count) {
-                        omap_gpio_restore_context(bank);
-                } else {
-                        spin_unlock_irqrestore(&bank->lock, flags);
-                        return 0;
+        for (i = 0; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                void __iomem *wake_clear;
+                void __iomem *wake_set;
+                unsigned long flags;
+
+                switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP16XX
+                case METHOD_GPIO_1610:
+                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                        break;
+#endif
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+                case METHOD_GPIO_24XX:
+                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+                        break;
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_44XX:
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
+                default:
+                        continue;
                 }
-        }
 
-        if (!bank->workaround_enabled) {
+                spin_lock_irqsave(&bank->lock, flags);
+                __raw_writel(0xffffffff, wake_clear);
+                __raw_writel(bank->saved_wakeup, wake_set);
                 spin_unlock_irqrestore(&bank->lock, flags);
-                return 0;
         }
+}
 
-        __raw_writel(bank->context.fallingdetect,
-                        bank->base + bank->regs->fallingdetect);
-        __raw_writel(bank->context.risingdetect,
-                        bank->base + bank->regs->risingdetect);
-        l = __raw_readl(bank->base + bank->regs->datain);
+static struct syscore_ops omap_gpio_syscore_ops = {
+        .suspend        = omap_gpio_suspend,
+        .resume         = omap_gpio_resume,
+};
 
-        /*
-         * Check if any of the non-wakeup interrupt GPIOs have changed
-         * state.  If so, generate an IRQ by software.  This is
-         * horribly racy, but it's the best we can do to work around
-         * this silicon bug.
-         */
-        l ^= bank->saved_datain;
-        l &= bank->enabled_non_wakeup_gpios;
+#endif
 
-        /*
-         * No need to generate IRQs for the rising edge for gpio IRQs
-         * configured with falling edge only; and vice versa.
-         */
-        gen0 = l & bank->context.fallingdetect;
-        gen0 &= bank->saved_datain;
+#ifdef CONFIG_ARCH_OMAP2PLUS
 
-        gen1 = l & bank->context.risingdetect;
-        gen1 &= ~(bank->saved_datain);
+static int workaround_enabled;
 
-        /* FIXME: Consider GPIO IRQs with level detections properly! */
-        gen = l & (~(bank->context.fallingdetect) &
-                                         ~(bank->context.risingdetect));
-        /* Consider all GPIO IRQs needed to be updated */
-        gen |= gen0 | gen1;
+void omap2_gpio_prepare_for_idle(int off_mode)
+{
+        int i, c = 0;
+        int min = 0;
 
-        if (gen) {
-                u32 old0, old1;
+        if (cpu_is_omap34xx())
+                min = 1;
 
-                old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
-                old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
+        for (i = min; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                u32 l1 = 0, l2 = 0;
+                int j;
 
-                if (!bank->regs->irqstatus_raw0) {
-                        __raw_writel(old0 | gen, bank->base +
-                                                bank->regs->leveldetect0);
-                        __raw_writel(old1 | gen, bank->base +
-                                                bank->regs->leveldetect1);
-                }
+                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+                        clk_disable(bank->dbck);
 
-                if (bank->regs->irqstatus_raw0) {
-                        __raw_writel(old0 | l, bank->base +
-                                                bank->regs->leveldetect0);
-                        __raw_writel(old1 | l, bank->base +
-                                                bank->regs->leveldetect1);
-                }
-                __raw_writel(old0, bank->base + bank->regs->leveldetect0);
-                __raw_writel(old1, bank->base + bank->regs->leveldetect1);
-        }
+                if (!off_mode)
+                        continue;
 
-        bank->workaround_enabled = false;
-        spin_unlock_irqrestore(&bank->lock, flags);
+                /* If going to OFF, remove triggering for all
+                 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
+                 * generated.  See OMAP2420 Errata item 1.101. */
+                if (!(bank->enabled_non_wakeup_gpios))
+                        continue;
 
-        return 0;
-}
-#endif /* CONFIG_PM_RUNTIME */
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
 
-void omap2_gpio_prepare_for_idle(int pwr_mode)
-{
-        struct gpio_bank *bank;
+                if (cpu_is_omap44xx()) {
+                        bank->saved_datain = __raw_readl(bank->base +
+                                                OMAP4_GPIO_DATAIN);
+                        l1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_FALLINGDETECT);
+                        l2 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_RISINGDETECT);
+                }
 
-        list_for_each_entry(bank, &omap_gpio_list, node) {
-                if (!bank->mod_usage || !bank->loses_context)
-                        continue;
+                bank->saved_fallingdetect = l1;
+                bank->saved_risingdetect = l2;
+                l1 &= ~bank->enabled_non_wakeup_gpios;
+                l2 &= ~bank->enabled_non_wakeup_gpios;
 
-                bank->power_mode = pwr_mode;
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(l1, bank->base +
+                                        OMAP24XX_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base +
+                                        OMAP24XX_GPIO_RISINGDETECT);
+                }
 
-                pm_runtime_put_sync_suspend(bank->dev);
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                        __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+                }
+
+                c++;
+        }
+        if (!c) {
+                workaround_enabled = 0;
+                return;
         }
+        workaround_enabled = 1;
 }
 
 void omap2_gpio_resume_after_idle(void)
 {
-        struct gpio_bank *bank;
+        int i;
+        int min = 0;
 
-        list_for_each_entry(bank, &omap_gpio_list, node) {
-                if (!bank->mod_usage || !bank->loses_context)
-                        continue;
+        if (cpu_is_omap34xx())
+                min = 1;
+        for (i = min; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                u32 l = 0, gen, gen0, gen1;
+                int j;
 
-                pm_runtime_get_sync(bank->dev);
-        }
-}
+                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+                        clk_enable(bank->dbck);
 
-#if defined(CONFIG_PM_RUNTIME)
-static void omap_gpio_restore_context(struct gpio_bank *bank)
-{
-        __raw_writel(bank->context.wake_en,
-                                bank->base + bank->regs->wkup_en);
-        __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
-        __raw_writel(bank->context.leveldetect0,
-                                bank->base + bank->regs->leveldetect0);
-        __raw_writel(bank->context.leveldetect1,
-                                bank->base + bank->regs->leveldetect1);
-        __raw_writel(bank->context.risingdetect,
-                                bank->base + bank->regs->risingdetect);
-        __raw_writel(bank->context.fallingdetect,
-                                bank->base + bank->regs->fallingdetect);
-        if (bank->regs->set_dataout && bank->regs->clr_dataout)
-                __raw_writel(bank->context.dataout,
-                                bank->base + bank->regs->set_dataout);
-        else
-                __raw_writel(bank->context.dataout,
-                                bank->base + bank->regs->dataout);
-        __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
-
-        if (bank->dbck_enable_mask) {
-                __raw_writel(bank->context.debounce, bank->base +
-                                        bank->regs->debounce);
-                __raw_writel(bank->context.debounce_en,
-                                        bank->base + bank->regs->debounce_en);
-        }
+                if (!workaround_enabled)
+                        continue;
 
-        __raw_writel(bank->context.irqenable1,
-                                bank->base + bank->regs->irqenable);
-        __raw_writel(bank->context.irqenable2,
-                                bank->base + bank->regs->irqenable2);
-}
-#endif /* CONFIG_PM_RUNTIME */
-#else
-#define omap_gpio_runtime_suspend NULL
-#define omap_gpio_runtime_resume NULL
-#endif
+                if (!(bank->enabled_non_wakeup_gpios))
+                        continue;
 
-static const struct dev_pm_ops gpio_pm_ops = {
-        SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
-                                                                        NULL)
-};
+                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
+                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                        __raw_writel(bank->saved_risingdetect,
+                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                        l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+                }
 
-#if defined(CONFIG_OF)
-static struct omap_gpio_reg_offs omap2_gpio_regs = {
-        .revision =             OMAP24XX_GPIO_REVISION,
-        .direction =            OMAP24XX_GPIO_OE,
-        .datain =               OMAP24XX_GPIO_DATAIN,
-        .dataout =              OMAP24XX_GPIO_DATAOUT,
-        .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
-        .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
-        .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
-        .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
-        .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
-        .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
-        .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
-        .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
-        .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
-        .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
-        .ctrl =                 OMAP24XX_GPIO_CTRL,
-        .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
-        .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
-        .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
-        .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
-        .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
-};
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(bank->saved_fallingdetect,
+                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
+                        __raw_writel(bank->saved_risingdetect,
+                                 bank->base + OMAP4_GPIO_RISINGDETECT);
+                        l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
+                }
 
-static struct omap_gpio_reg_offs omap4_gpio_regs = {
-        .revision =             OMAP4_GPIO_REVISION,
-        .direction =            OMAP4_GPIO_OE,
-        .datain =               OMAP4_GPIO_DATAIN,
-        .dataout =              OMAP4_GPIO_DATAOUT,
-        .set_dataout =          OMAP4_GPIO_SETDATAOUT,
-        .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
-        .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
-        .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
-        .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
-        .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
-        .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
-        .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
-        .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
-        .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
-        .ctrl =                 OMAP4_GPIO_CTRL,
-        .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
-        .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
-        .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
-        .risingdetect =         OMAP4_GPIO_RISINGDETECT,
-        .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
-};
+                /* Check if any of the non-wakeup interrupt GPIOs have changed
+                 * state.  If so, generate an IRQ by software.  This is
+                 * horribly racy, but it's the best we can do to work around
+                 * this silicon bug. */
+                l ^= bank->saved_datain;
+                l &= bank->enabled_non_wakeup_gpios;
 
-const static struct omap_gpio_platform_data omap2_pdata = {
-        .regs = &omap2_gpio_regs,
-        .bank_width = 32,
-        .dbck_flag = false,
-};
+                /*
+                 * No need to generate IRQs for the rising edge for gpio IRQs
+                 * configured with falling edge only; and vice versa.
+                 */
+                gen0 = l & bank->saved_fallingdetect;
+                gen0 &= bank->saved_datain;
+
+                gen1 = l & bank->saved_risingdetect;
+                gen1 &= ~(bank->saved_datain);
+
+                /* FIXME: Consider GPIO IRQs with level detections properly! */
+                gen = l & (~(bank->saved_fallingdetect) &
+                                ~(bank->saved_risingdetect));
+                /* Consider all GPIO IRQs needed to be updated */
+                gen |= gen0 | gen1;
+
+                if (gen) {
+                        u32 old0, old1;
+
+                        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                                old0 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                old1 = __raw_readl(bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                                __raw_writel(old0 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                __raw_writel(old1 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                                __raw_writel(old0, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                                __raw_writel(old1, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
+                        }
+
+                        if (cpu_is_omap44xx()) {
+                                old0 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                                old1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                                __raw_writel(old0 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                                __raw_writel(old1 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                                __raw_writel(old0, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                                __raw_writel(old1, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        }
+                }
+        }
 
-const static struct omap_gpio_platform_data omap3_pdata = {
-        .regs = &omap2_gpio_regs,
-        .bank_width = 32,
-        .dbck_flag = true,
-};
+}
 
-const static struct omap_gpio_platform_data omap4_pdata = {
-        .regs = &omap4_gpio_regs,
-        .bank_width = 32,
-        .dbck_flag = true,
-};
+#endif
 
-static const struct of_device_id omap_gpio_match[] = {
-        {
-                .compatible = "ti,omap4-gpio",
-                .data = &omap4_pdata,
-        },
-        {
-                .compatible = "ti,omap3-gpio",
-                .data = &omap3_pdata,
-        },
-        {
-                .compatible = "ti,omap2-gpio",
-                .data = &omap2_pdata,
-        },
-        { },
-};
-MODULE_DEVICE_TABLE(of, omap_gpio_match);
+#ifdef CONFIG_ARCH_OMAP3
+/* save the registers of bank 2-6 */
+void omap_gpio_save_context(void)
+{
+        int i;
+
+        /* saving banks from 2-6 only since GPIO1 is in WKUP */
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                gpio_context[i].irqenable1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                gpio_context[i].irqenable2 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                gpio_context[i].wake_en =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+                gpio_context[i].ctrl =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+                gpio_context[i].oe =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+                gpio_context[i].leveldetect0 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                gpio_context[i].leveldetect1 =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                gpio_context[i].risingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                gpio_context[i].fallingdetect =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                gpio_context[i].dataout =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+        }
+}
+
+/* restore the required registers of bank 2-6 */
+void omap_gpio_restore_context(void)
+{
+        int i;
+
+        for (i = 1; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                __raw_writel(gpio_context[i].irqenable1,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                __raw_writel(gpio_context[i].irqenable2,
+                                bank->base + OMAP24XX_GPIO_IRQENABLE2);
+                __raw_writel(gpio_context[i].wake_en,
+                                bank->base + OMAP24XX_GPIO_WAKE_EN);
+                __raw_writel(gpio_context[i].ctrl,
+                                bank->base + OMAP24XX_GPIO_CTRL);
+                __raw_writel(gpio_context[i].oe,
+                                bank->base + OMAP24XX_GPIO_OE);
+                __raw_writel(gpio_context[i].leveldetect0,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+                __raw_writel(gpio_context[i].leveldetect1,
+                                bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                __raw_writel(gpio_context[i].risingdetect,
+                                bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                __raw_writel(gpio_context[i].fallingdetect,
+                                bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+                __raw_writel(gpio_context[i].dataout,
+                                bank->base + OMAP24XX_GPIO_DATAOUT);
+        }
+}
 #endif
 
 static struct platform_driver omap_gpio_driver = {
         .probe          = omap_gpio_probe,
         .driver         = {
                 .name   = "omap_gpio",
-                .pm     = &gpio_pm_ops,
-                .of_match_table = of_match_ptr(omap_gpio_match),
         },
 };
 
@@ -1531,3 +1576,17 @@ static int __init omap_gpio_drv_reg(void)
         return platform_driver_register(&omap_gpio_driver);
 }
 postcore_initcall(omap_gpio_drv_reg);
+
+static int __init omap_gpio_sysinit(void)
+{
+        mpuio_init();
+
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
+        if (cpu_is_omap16xx() || cpu_class_is_omap2())
+                register_syscore_ops(&omap_gpio_syscore_ops);
+#endif
+
+        return 0;
+}
+
+arch_initcall(omap_gpio_sysinit);
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index cc102d25ee2..0550dcb8581 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -16,7 +16,6 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/slab.h>
@@ -29,8 +28,6 @@
 #define PCA953X_INVERT          2
 #define PCA953X_DIRECTION       3
 
-#define REG_ADDR_AI             0x80
-
 #define PCA957X_IN              0
 #define PCA957X_INVRT           1
 #define PCA957X_BKEN            2
@@ -66,25 +63,24 @@ static const struct i2c_device_id pca953x_id[] = {
         { "pca6107", 8  | PCA953X_TYPE | PCA_INT, },
         { "tca6408", 8  | PCA953X_TYPE | PCA_INT, },
         { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
-        { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
+        /* NYET:  { "tca6424", 24, }, */
         { }
 };
 MODULE_DEVICE_TABLE(i2c, pca953x_id);
 
 struct pca953x_chip {
         unsigned gpio_start;
-        u32 reg_output;
-        u32 reg_direction;
+        uint16_t reg_output;
+        uint16_t reg_direction;
         struct mutex i2c_lock;
 
 #ifdef CONFIG_GPIO_PCA953X_IRQ
         struct mutex irq_lock;
-        u32 irq_mask;
-        u32 irq_stat;
-        u32 irq_trig_raise;
-        u32 irq_trig_fall;
+        uint16_t irq_mask;
+        uint16_t irq_stat;
+        uint16_t irq_trig_raise;
+        uint16_t irq_trig_fall;
         int      irq_base;
-        struct irq_domain *domain;
 #endif
 
         struct i2c_client *client;
@@ -93,19 +89,12 @@ struct pca953x_chip {
         int     chip_type;
 };
 
-static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
+static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val)
 {
         int ret = 0;
 
         if (chip->gpio_chip.ngpio <= 8)
                 ret = i2c_smbus_write_byte_data(chip->client, reg, val);
-        else if (chip->gpio_chip.ngpio == 24) {
-                cpu_to_le32s(&val);
-                ret = i2c_smbus_write_i2c_block_data(chip->client,
-                                                (reg << 2) | REG_ADDR_AI,
-                                                3,
-                                                (u8 *) &val);
-        }
         else {
                 switch (chip->chip_type) {
                 case PCA953X_TYPE:
@@ -132,38 +121,28 @@ static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
         return 0;
 }
 
-static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val)
+static int pca953x_read_reg(struct pca953x_chip *chip, int reg, uint16_t *val)
 {
         int ret;
 
-        if (chip->gpio_chip.ngpio <= 8) {
+        if (chip->gpio_chip.ngpio <= 8)
                 ret = i2c_smbus_read_byte_data(chip->client, reg);
-                *val = ret;
-        }
-        else if (chip->gpio_chip.ngpio == 24) {
-                *val = 0;
-                ret = i2c_smbus_read_i2c_block_data(chip->client,
-                                                (reg << 2) | REG_ADDR_AI,
-                                                3,
-                                                (u8 *) val);
-                le32_to_cpus(val);
-        } else {
+        else
                 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
-                *val = ret;
-        }
 
         if (ret < 0) {
                 dev_err(&chip->client->dev, "failed reading register\n");
                 return ret;
         }
 
+        *val = (uint16_t)ret;
         return 0;
 }
 
 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
 {
         struct pca953x_chip *chip;
-        uint reg_val;
+        uint16_t reg_val;
         int ret, offset = 0;
 
         chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -194,7 +173,7 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
                 unsigned off, int val)
 {
         struct pca953x_chip *chip;
-        uint reg_val;
+        uint16_t reg_val;
         int ret, offset = 0;
 
         chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -244,7 +223,7 @@ exit:
 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
 {
         struct pca953x_chip *chip;
-        u32 reg_val;
+        uint16_t reg_val;
         int ret, offset = 0;
 
         chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -274,7 +253,7 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
 {
         struct pca953x_chip *chip;
-        u32 reg_val;
+        uint16_t reg_val;
         int ret, offset = 0;
 
         chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -335,14 +314,14 @@ static void pca953x_irq_mask(struct irq_data *d)
 {
         struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
 
-        chip->irq_mask &= ~(1 << d->hwirq);
+        chip->irq_mask &= ~(1 << (d->irq - chip->irq_base));
 }
 
 static void pca953x_irq_unmask(struct irq_data *d)
 {
         struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
 
-        chip->irq_mask |= 1 << d->hwirq;
+        chip->irq_mask |= 1 << (d->irq - chip->irq_base);
 }
 
 static void pca953x_irq_bus_lock(struct irq_data *d)
@@ -355,8 +334,8 @@ static void pca953x_irq_bus_lock(struct irq_data *d)
 static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
 {
         struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
-        u32 new_irqs;
-        u32 level;
+        uint16_t new_irqs;
+        uint16_t level;
 
         /* Look for any newly setup interrupt */
         new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
@@ -374,7 +353,8 @@ static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
 {
         struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
-        u32 mask = 1 << d->hwirq;
+        uint16_t level = d->irq - chip->irq_base;
+        uint16_t mask = 1 << level;
 
         if (!(type & IRQ_TYPE_EDGE_BOTH)) {
                 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
@@ -404,12 +384,12 @@ static struct irq_chip pca953x_irq_chip = {
         .irq_set_type           = pca953x_irq_set_type,
 };
 
-static u32 pca953x_irq_pending(struct pca953x_chip *chip)
+static uint16_t pca953x_irq_pending(struct pca953x_chip *chip)
 {
-        u32 cur_stat;
-        u32 old_stat;
-        u32 pending;
-        u32 trigger;
+        uint16_t cur_stat;
+        uint16_t old_stat;
+        uint16_t pending;
+        uint16_t trigger;
         int ret, offset = 0;
 
         switch (chip->chip_type) {
@@ -445,8 +425,8 @@ static u32 pca953x_irq_pending(struct pca953x_chip *chip)
 static irqreturn_t pca953x_irq_handler(int irq, void *devid)
 {
         struct pca953x_chip *chip = devid;
-        u32 pending;
-        u32 level;
+        uint16_t pending;
+        uint16_t level;
 
         pending = pca953x_irq_pending(chip);
 
@@ -455,7 +435,7 @@ static irqreturn_t pca953x_irq_handler(int irq, void *devid)
 
         do {
                 level = __ffs(pending);
-                handle_nested_irq(irq_find_mapping(chip->domain, level));
+                handle_nested_irq(level + chip->irq_base);
 
                 pending &= ~(1 << level);
         } while (pending);
@@ -469,7 +449,6 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
 {
         struct i2c_client *client = chip->client;
         int ret, offset = 0;
-        u32 temporary;
 
         if (irq_base != -1
                         && (id->driver_data & PCA_INT)) {
@@ -483,8 +462,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
                         offset = PCA957X_IN;
                         break;
                 }
-                ret = pca953x_read_reg(chip, offset, &temporary);
-                chip->irq_stat = temporary;
+                ret = pca953x_read_reg(chip, offset, &chip->irq_stat);
                 if (ret)
                         goto out_failed;
 
@@ -500,17 +478,6 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
                 if (chip->irq_base < 0)
                         goto out_failed;
 
-                chip->domain = irq_domain_add_legacy(client->dev.of_node,
-                                                chip->gpio_chip.ngpio,
-                                                chip->irq_base,
-                                                0,
-                                                &irq_domain_simple_ops,
-                                                NULL);
-                if (!chip->domain) {
-                        ret = -ENODEV;
-                        goto out_irqdesc_free;
-                }
-
                 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) {
                         int irq = lvl + chip->irq_base;
 
@@ -533,7 +500,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
                 if (ret) {
                         dev_err(&client->dev, "failed to request irq %d\n",
                                 client->irq);
-                        goto out_irqdesc_free;
+                        goto out_failed;
                 }
 
                 chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
@@ -541,8 +508,6 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
 
         return 0;
 
-out_irqdesc_free:
-        irq_free_descs(chip->irq_base, chip->gpio_chip.ngpio);
 out_failed:
         chip->irq_base = -1;
         return ret;
@@ -581,8 +546,8 @@ static void pca953x_irq_teardown(struct pca953x_chip *chip)
  * Translate OpenFirmware node properties into platform_data
  * WARNING: This is DEPRECATED and will be removed eventually!
  */
-static void
-pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
+void
+pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
 {
         struct device_node *node;
         const __be32 *val;
@@ -609,14 +574,14 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
                 *invert = *val;
 }
 #else
-static void
-pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
+void
+pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
 {
         *gpio_base = -1;
 }
 #endif
 
-static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
+static int __devinit device_pca953x_init(struct pca953x_chip *chip, int invert)
 {
         int ret;
 
@@ -631,14 +596,17 @@ static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
 
         /* set platform specific polarity inversion */
         ret = pca953x_write_reg(chip, PCA953X_INVERT, invert);
+        if (ret)
+                goto out;
+        return 0;
 out:
         return ret;
 }
 
-static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
+static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert)
 {
         int ret;
-        u32 val = 0;
+        uint16_t val = 0;
 
         /* Let every port in proper state, that could save power */
         pca953x_write_reg(chip, PCA957X_PUPD, 0x0);
@@ -666,14 +634,13 @@ out:
         return ret;
 }
 
-static int pca953x_probe(struct i2c_client *client,
+static int __devinit pca953x_probe(struct i2c_client *client,
                                    const struct i2c_device_id *id)
 {
         struct pca953x_platform_data *pdata;
         struct pca953x_chip *chip;
-        int irq_base = 0;
-        int ret;
-        u32 invert = 0;
+        int irq_base=0, invert=0;
+        int ret = 0;
 
         chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL);
         if (chip == NULL)
@@ -706,10 +673,10 @@ static int pca953x_probe(struct i2c_client *client,
         pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
 
         if (chip->chip_type == PCA953X_TYPE)
-                ret = device_pca953x_init(chip, invert);
+                device_pca953x_init(chip, invert);
+        else if (chip->chip_type == PCA957X_TYPE)
+                device_pca957x_init(chip, invert);
         else
-                ret = device_pca957x_init(chip, invert);
-        if (ret)
                 goto out_failed;
 
         ret = pca953x_irq_setup(chip, id, irq_base);
@@ -765,38 +732,9 @@ static int pca953x_remove(struct i2c_client *client)
         return 0;
 }
 
-static const struct of_device_id pca953x_dt_ids[] = {
-        { .compatible = "nxp,pca9534", },
-        { .compatible = "nxp,pca9535", },
-        { .compatible = "nxp,pca9536", },
-        { .compatible = "nxp,pca9537", },
-        { .compatible = "nxp,pca9538", },
-        { .compatible = "nxp,pca9539", },
-        { .compatible = "nxp,pca9554", },
-        { .compatible = "nxp,pca9555", },
-        { .compatible = "nxp,pca9556", },
-        { .compatible = "nxp,pca9557", },
-        { .compatible = "nxp,pca9574", },
-        { .compatible = "nxp,pca9575", },
-
-        { .compatible = "maxim,max7310", },
-        { .compatible = "maxim,max7312", },
-        { .compatible = "maxim,max7313", },
-        { .compatible = "maxim,max7315", },
-
-        { .compatible = "ti,pca6107", },
-        { .compatible = "ti,tca6408", },
-        { .compatible = "ti,tca6416", },
-        { .compatible = "ti,tca6424", },
-        { }
-};
-
-MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
-
 static struct i2c_driver pca953x_driver = {
         .driver = {
                 .name   = "pca953x",
-                .of_match_table = pca953x_dt_ids,
         },
         .probe          = pca953x_probe,
         .remove         = pca953x_remove,
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index a19b7457a72..7369fdda92b 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -23,12 +23,6 @@
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pcf857x.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
 
 
 static const struct i2c_device_id pcf857x_id[] = {
@@ -65,34 +59,62 @@ struct pcf857x {
         struct gpio_chip        chip;
         struct i2c_client       *client;
         struct mutex            lock;           /* protect 'out' */
-        struct work_struct      work;           /* irq demux work */
-        struct irq_domain       *irq_domain;    /* for irq demux  */
-        spinlock_t              slock;          /* protect irq demux */
         unsigned                out;            /* software latch */
-        unsigned                status;         /* current status */
-        int                     irq;            /* real irq number */
-
-        int (*write)(struct i2c_client *client, unsigned data);
-        int (*read)(struct i2c_client *client);
 };
 
 /*-------------------------------------------------------------------------*/
 
 /* Talk to 8-bit I/O expander */
 
-static int i2c_write_le8(struct i2c_client *client, unsigned data)
+static int pcf857x_input8(struct gpio_chip *chip, unsigned offset)
+{
+        struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
+        int             status;
+
+        mutex_lock(&gpio->lock);
+        gpio->out |= (1 << offset);
+        status = i2c_smbus_write_byte(gpio->client, gpio->out);
+        mutex_unlock(&gpio->lock);
+
+        return status;
+}
+
+static int pcf857x_get8(struct gpio_chip *chip, unsigned offset)
 {
-        return i2c_smbus_write_byte(client, data);
+        struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
+        s32             value;
+
+        value = i2c_smbus_read_byte(gpio->client);
+        return (value < 0) ? 0 : (value & (1 << offset));
+}
+
+static int pcf857x_output8(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
+        unsigned        bit = 1 << offset;
+        int             status;
+
+        mutex_lock(&gpio->lock);
+        if (value)
+                gpio->out |= bit;
+        else
+                gpio->out &= ~bit;
+        status = i2c_smbus_write_byte(gpio->client, gpio->out);
+        mutex_unlock(&gpio->lock);
+
+        return status;
 }
 
-static int i2c_read_le8(struct i2c_client *client)
+static void pcf857x_set8(struct gpio_chip *chip, unsigned offset, int value)
 {
-        return (int)i2c_smbus_read_byte(client);
+        pcf857x_output8(chip, offset, value);
 }
 
+/*-------------------------------------------------------------------------*/
+
 /* Talk to 16-bit I/O expander */
 
-static int i2c_write_le16(struct i2c_client *client, unsigned word)
+static int i2c_write_le16(struct i2c_client *client, u16 word)
 {
         u8 buf[2] = { word & 0xff, word >> 8, };
         int status;
@@ -112,31 +134,29 @@ static int i2c_read_le16(struct i2c_client *client)
         return (buf[1] << 8) | buf[0];
 }
 
-/*-------------------------------------------------------------------------*/
-
-static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
+static int pcf857x_input16(struct gpio_chip *chip, unsigned offset)
 {
         struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
         int             status;
 
         mutex_lock(&gpio->lock);
         gpio->out |= (1 << offset);
-        status = gpio->write(gpio->client, gpio->out);
+        status = i2c_write_le16(gpio->client, gpio->out);
         mutex_unlock(&gpio->lock);
 
         return status;
 }
 
-static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
+static int pcf857x_get16(struct gpio_chip *chip, unsigned offset)
 {
         struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
         int             value;
 
-        value = gpio->read(gpio->client);
+        value = i2c_read_le16(gpio->client);
         return (value < 0) ? 0 : (value & (1 << offset));
 }
 
-static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
+static int pcf857x_output16(struct gpio_chip *chip, unsigned offset, int value)
 {
         struct pcf857x  *gpio = container_of(chip, struct pcf857x, chip);
         unsigned        bit = 1 << offset;
@@ -147,109 +167,15 @@ static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
                 gpio->out |= bit;
         else
                 gpio->out &= ~bit;
-        status = gpio->write(gpio->client, gpio->out);
+        status = i2c_write_le16(gpio->client, gpio->out);
         mutex_unlock(&gpio->lock);
 
         return status;
 }
 
-static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
+static void pcf857x_set16(struct gpio_chip *chip, unsigned offset, int value)
 {
-        pcf857x_output(chip, offset, value);
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int pcf857x_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct pcf857x *gpio = container_of(chip, struct pcf857x, chip);
-
-        return irq_create_mapping(gpio->irq_domain, offset);
-}
-
-static void pcf857x_irq_demux_work(struct work_struct *work)
-{
-        struct pcf857x *gpio = container_of(work,
-                                               struct pcf857x,
-                                               work);
-        unsigned long change, i, status, flags;
-
-        status = gpio->read(gpio->client);
-
-        spin_lock_irqsave(&gpio->slock, flags);
-
-        change = gpio->status ^ status;
-        for_each_set_bit(i, &change, gpio->chip.ngpio)
-                generic_handle_irq(irq_find_mapping(gpio->irq_domain, i));
-        gpio->status = status;
-
-        spin_unlock_irqrestore(&gpio->slock, flags);
-}
-
-static irqreturn_t pcf857x_irq_demux(int irq, void *data)
-{
-        struct pcf857x  *gpio = data;
-
-        /*
-         * pcf857x can't read/write data here,
-         * since i2c data access might go to sleep.
-         */
-        schedule_work(&gpio->work);
-
-        return IRQ_HANDLED;
-}
-
-static int pcf857x_irq_domain_map(struct irq_domain *domain, unsigned int virq,
-                                 irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq,
-                                 &dummy_irq_chip,
-                                 handle_level_irq);
-        return 0;
-}
-
-static struct irq_domain_ops pcf857x_irq_domain_ops = {
-        .map    = pcf857x_irq_domain_map,
-};
-
-static void pcf857x_irq_domain_cleanup(struct pcf857x *gpio)
-{
-        if (gpio->irq_domain)
-                irq_domain_remove(gpio->irq_domain);
-
-        if (gpio->irq)
-                free_irq(gpio->irq, gpio);
-}
-
-static int pcf857x_irq_domain_init(struct pcf857x *gpio,
-                                   struct pcf857x_platform_data *pdata,
-                                   struct i2c_client *client)
-{
-        int status;
-
-        gpio->irq_domain = irq_domain_add_linear(client->dev.of_node,
-                                                 gpio->chip.ngpio,
-                                                 &pcf857x_irq_domain_ops,
-                                                 NULL);
-        if (!gpio->irq_domain)
-                goto fail;
-
-        /* enable real irq */
-        status = request_irq(client->irq, pcf857x_irq_demux, 0,
-                             dev_name(&client->dev), gpio);
-        if (status)
-                goto fail;
-
-        /* enable gpio_to_irq() */
-        INIT_WORK(&gpio->work, pcf857x_irq_demux_work);
-        gpio->chip.to_irq       = pcf857x_to_irq;
-        gpio->irq               = client->irq;
-
-        return 0;
-
-fail:
-        pcf857x_irq_domain_cleanup(gpio);
-        return -EINVAL;
+        pcf857x_output16(chip, offset, value);
 }
 
 /*-------------------------------------------------------------------------*/
@@ -272,26 +198,11 @@ static int pcf857x_probe(struct i2c_client *client,
                 return -ENOMEM;
 
         mutex_init(&gpio->lock);
-        spin_lock_init(&gpio->slock);
-
-        gpio->chip.base                 = pdata ? pdata->gpio_base : -1;
-        gpio->chip.can_sleep            = 1;
-        gpio->chip.dev                  = &client->dev;
-        gpio->chip.owner                = THIS_MODULE;
-        gpio->chip.get                  = pcf857x_get;
-        gpio->chip.set                  = pcf857x_set;
-        gpio->chip.direction_input      = pcf857x_input;
-        gpio->chip.direction_output     = pcf857x_output;
-        gpio->chip.ngpio                = id->driver_data;
-
-        /* enable gpio_to_irq() if platform has settings */
-        if (pdata && client->irq) {
-                status = pcf857x_irq_domain_init(gpio, pdata, client);
-                if (status < 0) {
-                        dev_err(&client->dev, "irq_domain init failed\n");
-                        goto fail;
-                }
-        }
+
+        gpio->chip.base = pdata ? pdata->gpio_base : -1;
+        gpio->chip.can_sleep = 1;
+        gpio->chip.dev = &client->dev;
+        gpio->chip.owner = THIS_MODULE;
 
         /* NOTE:  the OnSemi jlc1562b is also largely compatible with
          * these parts, notably for output.  It has a low-resolution
@@ -304,9 +215,12 @@ static int pcf857x_probe(struct i2c_client *client,
          *
          * NOTE: we don't distinguish here between *4 and *4a parts.
          */
+        gpio->chip.ngpio = id->driver_data;
         if (gpio->chip.ngpio == 8) {
-                gpio->write     = i2c_write_le8;
-                gpio->read      = i2c_read_le8;
+                gpio->chip.direction_input = pcf857x_input8;
+                gpio->chip.get = pcf857x_get8;
+                gpio->chip.direction_output = pcf857x_output8;
+                gpio->chip.set = pcf857x_set8;
 
                 if (!i2c_check_functionality(client->adapter,
                                 I2C_FUNC_SMBUS_BYTE))
@@ -323,8 +237,10 @@ static int pcf857x_probe(struct i2c_client *client,
          * NOTE: we don't distinguish here between '75 and '75c parts.
          */
         } else if (gpio->chip.ngpio == 16) {
-                gpio->write     = i2c_write_le16;
-                gpio->read      = i2c_read_le16;
+                gpio->chip.direction_input = pcf857x_input16;
+                gpio->chip.get = pcf857x_get16;
+                gpio->chip.direction_output = pcf857x_output16;
+                gpio->chip.set = pcf857x_set16;
 
                 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
                         status = -EIO;
@@ -362,12 +278,23 @@ static int pcf857x_probe(struct i2c_client *client,
          * all-ones reset state.  Otherwise it flags pins to be driven low.
          */
         gpio->out = pdata ? ~pdata->n_latch : ~0;
-        gpio->status = gpio->out;
 
         status = gpiochip_add(&gpio->chip);
         if (status < 0)
                 goto fail;
 
+        /* NOTE: these chips can issue "some pin-changed" IRQs, which we
+         * don't yet even try to use.  Among other issues, the relevant
+         * genirq state isn't available to modular drivers; and most irq
+         * methods can't be called from sleeping contexts.
+         */
+
+        dev_info(&client->dev, "gpios %d..%d on a %s%s\n",
+                        gpio->chip.base,
+                        gpio->chip.base + gpio->chip.ngpio - 1,
+                        client->name,
+                        client->irq ? " (irq ignored)" : "");
+
         /* Let platform code set up the GPIOs and their users.
          * Now is the first time anyone could use them.
          */
@@ -379,17 +306,11 @@ static int pcf857x_probe(struct i2c_client *client,
                         dev_warn(&client->dev, "setup --> %d\n", status);
         }
 
-        dev_info(&client->dev, "probed\n");
-
         return 0;
 
 fail:
         dev_dbg(&client->dev, "probe error %d for '%s'\n",
                         status, client->name);
-
-        if (pdata && client->irq)
-                pcf857x_irq_domain_cleanup(gpio);
-
         kfree(gpio);
         return status;
 }
@@ -411,9 +332,6 @@ static int pcf857x_remove(struct i2c_client *client)
                 }
         }
 
-        if (pdata && client->irq)
-                pcf857x_irq_domain_cleanup(gpio);
-
         status = gpiochip_remove(&gpio->chip);
         if (status == 0)
                 kfree(gpio);
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index cdf599687cf..36919e77c49 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,21 +14,12 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
 
-#define PCH_EDGE_FALLING        0
-#define PCH_EDGE_RISING         BIT(0)
-#define PCH_LEVEL_L             BIT(1)
-#define PCH_LEVEL_H             (BIT(0) | BIT(1))
-#define PCH_EDGE_BOTH           BIT(2)
-#define PCH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
-
-#define PCH_IRQ_BASE            24
+#define PCH_GPIO_ALL_PINS       0xfff /* Mask for GPIO pins 0 to 11 */
+#define GPIO_NUM_PINS   12      /* Specifies number of GPIO PINS GPIO0-GPIO11 */
 
 struct pch_regs {
         u32     ien;
@@ -42,43 +33,18 @@ struct pch_regs {
         u32     pm;
         u32     im0;
         u32     im1;
-        u32     reserved[3];
-        u32     gpio_use_sel;
+        u32     reserved[4];
         u32     reset;
 };
 
-enum pch_type_t {
-        INTEL_EG20T_PCH,
-        OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
-        OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
-};
-
-/* Specifies number of GPIO PINS */
-static int gpio_pins[] = {
-        [INTEL_EG20T_PCH] = 12,
-        [OKISEMI_ML7223m_IOH] = 8,
-        [OKISEMI_ML7223n_IOH] = 8,
-};
-
 /**
  * struct pch_gpio_reg_data - The register store data.
- * @ien_reg:    To store contents of IEN register.
- * @imask_reg:  To store contents of IMASK register.
  * @po_reg:     To store contents of PO register.
  * @pm_reg:     To store contents of PM register.
- * @im0_reg:    To store contents of IM0 register.
- * @im1_reg:    To store contents of IM1 register.
- * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
- *                     (Only ML7223 Bus-n)
  */
 struct pch_gpio_reg_data {
-        u32 ien_reg;
-        u32 imask_reg;
         u32 po_reg;
         u32 pm_reg;
-        u32 im0_reg;
-        u32 im1_reg;
-        u32 gpio_use_sel_reg;
 };
 
 /**
@@ -89,10 +55,6 @@ struct pch_gpio_reg_data {
  * @gpio:                       Data for GPIO infrastructure.
  * @pch_gpio_reg:               Memory mapped Register data is saved here
  *                              when suspend.
- * @lock:                       Used for register access protection
- * @irq_base:           Save base of IRQ number for interrupt
- * @ioh:                IOH ID
- * @spinlock:           Used for register access protection
  */
 struct pch_gpio {
         void __iomem *base;
@@ -100,18 +62,15 @@ struct pch_gpio {
         struct device *dev;
         struct gpio_chip gpio;
         struct pch_gpio_reg_data pch_gpio_reg;
-        int irq_base;
-        enum pch_type_t ioh;
-        spinlock_t spinlock;
+        struct mutex lock;
 };
 
 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
 {
         u32 reg_val;
         struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
+        mutex_lock(&chip->lock);
         reg_val = ioread32(&chip->reg->po);
         if (val)
                 reg_val |= (1 << nr);
@@ -119,7 +78,7 @@ static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
                 reg_val &= ~(1 << nr);
 
         iowrite32(reg_val, &chip->reg->po);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        mutex_unlock(&chip->lock);
 }
 
 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
@@ -135,10 +94,9 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
         struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
         u32 pm;
         u32 reg_val;
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
-        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
+        mutex_lock(&chip->lock);
+        pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
         pm |= (1 << nr);
         iowrite32(pm, &chip->reg->pm);
 
@@ -148,7 +106,8 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
         else
                 reg_val &= ~(1 << nr);
         iowrite32(reg_val, &chip->reg->po);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+
+        mutex_unlock(&chip->lock);
 
         return 0;
 }
@@ -157,13 +116,12 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 {
         struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
         u32 pm;
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
-        pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
+        mutex_lock(&chip->lock);
+        pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
         pm &= ~(1 << nr);
         iowrite32(pm, &chip->reg->pm);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        mutex_unlock(&chip->lock);
 
         return 0;
 }
@@ -173,16 +131,8 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  */
 static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
 {
-        chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
-        chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
         chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
         chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
-        chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
-        if (chip->ioh == INTEL_EG20T_PCH)
-                chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
-        if (chip->ioh == OKISEMI_ML7223n_IOH)
-                chip->pch_gpio_reg.gpio_use_sel_reg =\
-                                            ioread32(&chip->reg->gpio_use_sel);
 }
 
 /*
@@ -190,24 +140,10 @@ static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
  */
 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
 {
-        iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
-        iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
         /* to store contents of PO register */
         iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
         /* to store contents of PM register */
         iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
-        iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
-        if (chip->ioh == INTEL_EG20T_PCH)
-                iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
-        if (chip->ioh == OKISEMI_ML7223n_IOH)
-                iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
-                          &chip->reg->gpio_use_sel);
-}
-
-static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
-{
-        struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
-        return chip->irq_base + offset;
 }
 
 static void pch_gpio_setup(struct pch_gpio *chip)
@@ -215,7 +151,6 @@ static void pch_gpio_setup(struct pch_gpio *chip)
         struct gpio_chip *gpio = &chip->gpio;
 
         gpio->label = dev_name(chip->dev);
-        gpio->dev = chip->dev;
         gpio->owner = THIS_MODULE;
         gpio->direction_input = pch_gpio_direction_input;
         gpio->get = pch_gpio_get;
@@ -223,136 +158,15 @@ static void pch_gpio_setup(struct pch_gpio *chip)
         gpio->set = pch_gpio_set;
         gpio->dbg_show = NULL;
         gpio->base = -1;
-        gpio->ngpio = gpio_pins[chip->ioh];
+        gpio->ngpio = GPIO_NUM_PINS;
         gpio->can_sleep = 0;
-        gpio->to_irq = pch_gpio_to_irq;
-}
-
-static int pch_irq_type(struct irq_data *d, unsigned int type)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pch_gpio *chip = gc->private;
-        u32 im, im_pos, val;
-        u32 __iomem *im_reg;
-        unsigned long flags;
-        int ch, irq = d->irq;
-
-        ch = irq - chip->irq_base;
-        if (irq <= chip->irq_base + 7) {
-                im_reg = &chip->reg->im0;
-                im_pos = ch;
-        } else {
-                im_reg = &chip->reg->im1;
-                im_pos = ch - 8;
-        }
-        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
-                __func__, irq, type, ch, im_pos);
-
-        spin_lock_irqsave(&chip->spinlock, flags);
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                val = PCH_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                val = PCH_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                val = PCH_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                val = PCH_LEVEL_H;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                val = PCH_LEVEL_L;
-                break;
-        default:
-                goto unlock;
-        }
-
-        /* Set interrupt mode */
-        im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
-        iowrite32(im | (val << (im_pos * 4)), im_reg);
-
-        /* And the handler */
-        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-
-unlock:
-        spin_unlock_irqrestore(&chip->spinlock, flags);
-        return 0;
-}
-
-static void pch_irq_unmask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pch_gpio *chip = gc->private;
-
-        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
-}
-
-static void pch_irq_mask(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pch_gpio *chip = gc->private;
-
-        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
-}
-
-static void pch_irq_ack(struct irq_data *d)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pch_gpio *chip = gc->private;
-
-        iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
-}
-
-static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
-{
-        struct pch_gpio *chip = dev_id;
-        u32 reg_val = ioread32(&chip->reg->istatus);
-        int i, ret = IRQ_NONE;
-
-        for (i = 0; i < gpio_pins[chip->ioh]; i++) {
-                if (reg_val & BIT(i)) {
-                        dev_dbg(chip->dev, "%s:[%d]:irq=%d  status=0x%x\n",
-                                __func__, i, irq, reg_val);
-                        generic_handle_irq(chip->irq_base + i);
-                        ret = IRQ_HANDLED;
-                }
-        }
-        return ret;
 }
 
-static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
-                                unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
-                                    handle_simple_irq);
-        gc->private = chip;
-        ct = gc->chip_types;
-
-        ct->chip.irq_ack = pch_irq_ack;
-        ct->chip.irq_mask = pch_irq_mask;
-        ct->chip.irq_unmask = pch_irq_unmask;
-        ct->chip.irq_set_type = pch_irq_type;
-
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-}
-
-static int pch_gpio_probe(struct pci_dev *pdev,
+static int __devinit pch_gpio_probe(struct pci_dev *pdev,
                                     const struct pci_device_id *id)
 {
         s32 ret;
         struct pch_gpio *chip;
-        int irq_base;
-        u32 msk;
 
         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
         if (chip == NULL)
@@ -372,22 +186,15 @@ static int pch_gpio_probe(struct pci_dev *pdev,
         }
 
         chip->base = pci_iomap(pdev, 1, 0);
-        if (!chip->base) {
+        if (chip->base == 0) {
                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
                 ret = -ENOMEM;
                 goto err_iomap;
         }
 
-        if (pdev->device == 0x8803)
-                chip->ioh = INTEL_EG20T_PCH;
-        else if (pdev->device == 0x8014)
-                chip->ioh = OKISEMI_ML7223m_IOH;
-        else if (pdev->device == 0x8043)
-                chip->ioh = OKISEMI_ML7223n_IOH;
-
         chip->reg = chip->base;
         pci_set_drvdata(pdev, chip);
-        spin_lock_init(&chip->spinlock);
+        mutex_init(&chip->lock);
         pch_gpio_setup(chip);
         ret = gpiochip_add(&chip->gpio);
         if (ret) {
@@ -395,39 +202,8 @@ static int pch_gpio_probe(struct pci_dev *pdev,
                 goto err_gpiochip_add;
         }
 
-        irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
-        if (irq_base < 0) {
-                dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
-                chip->irq_base = -1;
-                goto end;
-        }
-        chip->irq_base = irq_base;
-
-        /* Mask all interrupts, but enable them */
-        msk = (1 << gpio_pins[chip->ioh]) - 1;
-        iowrite32(msk, &chip->reg->imask);
-        iowrite32(msk, &chip->reg->ien);
-
-        ret = request_irq(pdev->irq, pch_gpio_handler,
-                          IRQF_SHARED, KBUILD_MODNAME, chip);
-        if (ret != 0) {
-                dev_err(&pdev->dev,
-                        "%s request_irq failed\n", __func__);
-                goto err_request_irq;
-        }
-
-        pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
-
-end:
         return 0;
 
-err_request_irq:
-        irq_free_descs(irq_base, gpio_pins[chip->ioh]);
-
-        ret = gpiochip_remove(&chip->gpio);
-        if (ret)
-                dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
-
 err_gpiochip_add:
         pci_iounmap(pdev, chip->base);
 
@@ -443,17 +219,11 @@ err_pci_enable:
         return ret;
 }
 
-static void pch_gpio_remove(struct pci_dev *pdev)
+static void __devexit pch_gpio_remove(struct pci_dev *pdev)
 {
         int err;
         struct pch_gpio *chip = pci_get_drvdata(pdev);
 
-        if (chip->irq_base != -1) {
-                free_irq(pdev->irq, chip);
-
-                irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
-        }
-
         err = gpiochip_remove(&chip->gpio);
         if (err)
                 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
@@ -469,11 +239,9 @@ static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 {
         s32 ret;
         struct pch_gpio *chip = pci_get_drvdata(pdev);
-        unsigned long flags;
 
-        spin_lock_irqsave(&chip->spinlock, flags);
         pch_gpio_save_reg_conf(chip);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
+        pch_gpio_restore_reg_conf(chip);
 
         ret = pci_save_state(pdev);
         if (ret) {
@@ -493,7 +261,6 @@ static int pch_gpio_resume(struct pci_dev *pdev)
 {
         s32 ret;
         struct pch_gpio *chip = pci_get_drvdata(pdev);
-        unsigned long flags;
 
         ret = pci_enable_wake(pdev, PCI_D0, 0);
 
@@ -505,11 +272,9 @@ static int pch_gpio_resume(struct pci_dev *pdev)
         }
         pci_restore_state(pdev);
 
-        spin_lock_irqsave(&chip->spinlock, flags);
         iowrite32(0x01, &chip->reg->reset);
         iowrite32(0x00, &chip->reg->reset);
         pch_gpio_restore_reg_conf(chip);
-        spin_unlock_irqrestore(&chip->spinlock, flags);
 
         return 0;
 }
@@ -522,8 +287,6 @@ static int pch_gpio_resume(struct pci_dev *pdev)
 static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
         { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
-        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
-        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
         { 0, }
 };
 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
@@ -532,12 +295,22 @@ static struct pci_driver pch_gpio_driver = {
         .name = "pch_gpio",
         .id_table = pch_gpio_pcidev_id,
         .probe = pch_gpio_probe,
-        .remove = pch_gpio_remove,
+        .remove = __devexit_p(pch_gpio_remove),
         .suspend = pch_gpio_suspend,
         .resume = pch_gpio_resume
 };
 
-module_pci_driver(pch_gpio_driver);
+static int __init pch_gpio_pci_init(void)
+{
+        return pci_register_driver(&pch_gpio_driver);
+}
+module_init(pch_gpio_pci_init);
+
+static void __exit pch_gpio_pci_exit(void)
+{
+        pci_unregister_driver(&pch_gpio_driver);
+}
+module_exit(pch_gpio_pci_exit);
 
 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index c1720de18a4..2c5a18f32bf 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -12,6 +12,7 @@
 #include <linux/spinlock.h>
 #include <linux/errno.h>
 #include <linux/module.h>
+#include <linux/list.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/irq.h>
@@ -22,8 +23,6 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/slab.h>
-#include <linux/pm.h>
-#include <asm/mach/irq.h>
 
 #define GPIODIR 0x400
 #define GPIOIS  0x404
@@ -36,28 +35,25 @@
 
 #define PL061_GPIO_NR   8
 
-#ifdef CONFIG_PM
-struct pl061_context_save_regs {
-        u8 gpio_data;
-        u8 gpio_dir;
-        u8 gpio_is;
-        u8 gpio_ibe;
-        u8 gpio_iev;
-        u8 gpio_ie;
-};
-#endif
-
 struct pl061_gpio {
-        spinlock_t              lock;
+        /* We use a list of pl061_gpio structs for each trigger IRQ in the main
+         * interrupts controller of the system. We need this to support systems
+         * in which more that one PL061s are connected to the same IRQ. The ISR
+         * interates through this list to find the source of the interrupt.
+         */
+        struct list_head        list;
+
+        /* Each of the two spinlocks protects a different set of hardware
+         * regiters and data structurs. This decouples the code of the IRQ from
+         * the GPIO code. This also makes the case of a GPIO routine call from
+         * the IRQ code simpler.
+         */
+        spinlock_t              lock;           /* GPIO registers */
+        spinlock_t              irq_lock;       /* IRQ registers */
 
         void __iomem            *base;
-        int                     irq_base;
-        struct irq_chip_generic *irq_gc;
+        unsigned                irq_base;
         struct gpio_chip        gc;
-
-#ifdef CONFIG_PM
-        struct pl061_context_save_regs csave_regs;
-#endif
 };
 
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -122,16 +118,46 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
 {
         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 
-        if (chip->irq_base <= 0)
+        if (chip->irq_base == (unsigned) -1)
                 return -EINVAL;
 
         return chip->irq_base + offset;
 }
 
+/*
+ * PL061 GPIO IRQ
+ */
+static void pl061_irq_disable(struct irq_data *d)
+{
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+        int offset = d->irq - chip->irq_base;
+        unsigned long flags;
+        u8 gpioie;
+
+        spin_lock_irqsave(&chip->irq_lock, flags);
+        gpioie = readb(chip->base + GPIOIE);
+        gpioie &= ~(1 << offset);
+        writeb(gpioie, chip->base + GPIOIE);
+        spin_unlock_irqrestore(&chip->irq_lock, flags);
+}
+
+static void pl061_irq_enable(struct irq_data *d)
+{
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+        int offset = d->irq - chip->irq_base;
+        unsigned long flags;
+        u8 gpioie;
+
+        spin_lock_irqsave(&chip->irq_lock, flags);
+        gpioie = readb(chip->base + GPIOIE);
+        gpioie |= 1 << offset;
+        writeb(gpioie, chip->base + GPIOIE);
+        spin_unlock_irqrestore(&chip->irq_lock, flags);
+}
+
 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 {
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pl061_gpio *chip = gc->private;
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
         int offset = d->irq - chip->irq_base;
         unsigned long flags;
         u8 gpiois, gpioibe, gpioiev;
@@ -139,7 +165,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
         if (offset < 0 || offset >= PL061_GPIO_NR)
                 return -EINVAL;
 
-        raw_spin_lock_irqsave(&gc->lock, flags);
+        spin_lock_irqsave(&chip->irq_lock, flags);
 
         gpioiev = readb(chip->base + GPIOIEV);
 
@@ -168,178 +194,143 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 
         writeb(gpioiev, chip->base + GPIOIEV);
 
-        raw_spin_unlock_irqrestore(&gc->lock, flags);
+        spin_unlock_irqrestore(&chip->irq_lock, flags);
 
         return 0;
 }
 
+static struct irq_chip pl061_irqchip = {
+        .name           = "GPIO",
+        .irq_enable     = pl061_irq_enable,
+        .irq_disable    = pl061_irq_disable,
+        .irq_set_type   = pl061_irq_type,
+};
+
 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned long pending;
-        int offset;
-        struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
-        struct irq_chip *irqchip = irq_desc_get_chip(desc);
+        struct list_head *chip_list = irq_get_handler_data(irq);
+        struct list_head *ptr;
+        struct pl061_gpio *chip;
+
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        list_for_each(ptr, chip_list) {
+                unsigned long pending;
+                int offset;
 
-        chained_irq_enter(irqchip, desc);
+                chip = list_entry(ptr, struct pl061_gpio, list);
+                pending = readb(chip->base + GPIOMIS);
+                writeb(pending, chip->base + GPIOIC);
+
+                if (pending == 0)
+                        continue;
 
-        pending = readb(chip->base + GPIOMIS);
-        writeb(pending, chip->base + GPIOIC);
-        if (pending) {
                 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
                         generic_handle_irq(pl061_to_irq(&chip->gc, offset));
         }
-
-        chained_irq_exit(irqchip, desc);
-}
-
-static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
-{
-        struct irq_chip_type *ct;
-
-        chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
-                                              chip->base, handle_simple_irq);
-        chip->irq_gc->private = chip;
-
-        ct = chip->irq_gc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->chip.irq_set_type = pl061_irq_type;
-        ct->chip.irq_set_wake = irq_gc_set_wake;
-        ct->regs.mask = GPIOIE;
-
-        irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
-                               IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
+        desc->irq_data.chip->irq_unmask(&desc->irq_data);
 }
 
-static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
+static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
 {
-        struct device *dev = &adev->dev;
-        struct pl061_platform_data *pdata = dev->platform_data;
+        struct pl061_platform_data *pdata;
         struct pl061_gpio *chip;
+        struct list_head *chip_list;
         int ret, irq, i;
+        static DECLARE_BITMAP(init_irq, NR_IRQS);
 
-        chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+        pdata = dev->dev.platform_data;
+        if (pdata == NULL)
+                return -ENODEV;
+
+        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
         if (chip == NULL)
                 return -ENOMEM;
 
-        if (pdata) {
-                chip->gc.base = pdata->gpio_base;
-                chip->irq_base = pdata->irq_base;
-        } else if (adev->dev.of_node) {
-                chip->gc.base = -1;
-                chip->irq_base = 0;
-        } else
-                return -ENODEV;
-
-        if (!devm_request_mem_region(dev, adev->res.start,
-                                resource_size(&adev->res), "pl061"))
-                return -EBUSY;
+        if (!request_mem_region(dev->res.start,
+                                resource_size(&dev->res), "pl061")) {
+                ret = -EBUSY;
+                goto free_mem;
+        }
 
-        chip->base = devm_ioremap(dev, adev->res.start,
-                                resource_size(&adev->res));
-        if (chip->base == NULL)
-                return -ENOMEM;
+        chip->base = ioremap(dev->res.start, resource_size(&dev->res));
+        if (chip->base == NULL) {
+                ret = -ENOMEM;
+                goto release_region;
+        }
 
         spin_lock_init(&chip->lock);
+        spin_lock_init(&chip->irq_lock);
+        INIT_LIST_HEAD(&chip->list);
 
         chip->gc.direction_input = pl061_direction_input;
         chip->gc.direction_output = pl061_direction_output;
         chip->gc.get = pl061_get_value;
         chip->gc.set = pl061_set_value;
         chip->gc.to_irq = pl061_to_irq;
+        chip->gc.base = pdata->gpio_base;
         chip->gc.ngpio = PL061_GPIO_NR;
-        chip->gc.label = dev_name(dev);
-        chip->gc.dev = dev;
+        chip->gc.label = dev_name(&dev->dev);
+        chip->gc.dev = &dev->dev;
         chip->gc.owner = THIS_MODULE;
 
+        chip->irq_base = pdata->irq_base;
+
         ret = gpiochip_add(&chip->gc);
         if (ret)
-                return ret;
+                goto iounmap;
 
         /*
          * irq_chip support
          */
 
-        if (chip->irq_base <= 0)
+        if (chip->irq_base == (unsigned) -1)
                 return 0;
 
-        pl061_init_gc(chip, chip->irq_base);
-
         writeb(0, chip->base + GPIOIE); /* disable irqs */
-        irq = adev->irq[0];
-        if (irq < 0)
-                return -ENODEV;
-
+        irq = dev->irq[0];
+        if (irq < 0) {
+                ret = -ENODEV;
+                goto iounmap;
+        }
         irq_set_chained_handler(irq, pl061_irq_handler);
-        irq_set_handler_data(irq, chip);
-
-        for (i = 0; i < PL061_GPIO_NR; i++) {
-                if (pdata) {
-                        if (pdata->directions & (1 << i))
-                                pl061_direction_output(&chip->gc, i,
-                                                pdata->values & (1 << i));
-                        else
-                                pl061_direction_input(&chip->gc, i);
+        if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
+                chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
+                if (chip_list == NULL) {
+                        clear_bit(irq, init_irq);
+                        ret = -ENOMEM;
+                        goto iounmap;
                 }
-        }
-
-        amba_set_drvdata(adev, chip);
+                INIT_LIST_HEAD(chip_list);
+                irq_set_handler_data(irq, chip_list);
+        } else
+                chip_list = irq_get_handler_data(irq);
+        list_add(&chip->list, chip_list);
 
-        return 0;
-}
+        for (i = 0; i < PL061_GPIO_NR; i++) {
+                if (pdata->directions & (1 << i))
+                        pl061_direction_output(&chip->gc, i,
+                                        pdata->values & (1 << i));
+                else
+                        pl061_direction_input(&chip->gc, i);
 
-#ifdef CONFIG_PM
-static int pl061_suspend(struct device *dev)
-{
-        struct pl061_gpio *chip = dev_get_drvdata(dev);
-        int offset;
-
-        chip->csave_regs.gpio_data = 0;
-        chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
-        chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
-        chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
-        chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
-        chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
-
-        for (offset = 0; offset < PL061_GPIO_NR; offset++) {
-                if (chip->csave_regs.gpio_dir & (1 << offset))
-                        chip->csave_regs.gpio_data |=
-                                pl061_get_value(&chip->gc, offset) << offset;
+                irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip,
+                                         handle_simple_irq);
+                set_irq_flags(i+chip->irq_base, IRQF_VALID);
+                irq_set_chip_data(i + chip->irq_base, chip);
         }
 
         return 0;
-}
 
-static int pl061_resume(struct device *dev)
-{
-        struct pl061_gpio *chip = dev_get_drvdata(dev);
-        int offset;
-
-        for (offset = 0; offset < PL061_GPIO_NR; offset++) {
-                if (chip->csave_regs.gpio_dir & (1 << offset))
-                        pl061_direction_output(&chip->gc, offset,
-                                        chip->csave_regs.gpio_data &
-                                        (1 << offset));
-                else
-                        pl061_direction_input(&chip->gc, offset);
-        }
-
-        writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
-        writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
-        writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
-        writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
+iounmap:
+        iounmap(chip->base);
+release_region:
+        release_mem_region(dev->res.start, resource_size(&dev->res));
+free_mem:
+        kfree(chip);
 
-        return 0;
+        return ret;
 }
 
-static const struct dev_pm_ops pl061_dev_pm_ops = {
-        .suspend = pl061_suspend,
-        .resume = pl061_resume,
-        .freeze = pl061_suspend,
-        .restore = pl061_resume,
-};
-#endif
-
 static struct amba_id pl061_ids[] = {
         {
                 .id     = 0x00041061,
@@ -348,14 +339,9 @@ static struct amba_id pl061_ids[] = {
         { 0, 0 },
 };
 
-MODULE_DEVICE_TABLE(amba, pl061_ids);
-
 static struct amba_driver pl061_gpio_driver = {
         .drv = {
                 .name   = "pl061_gpio",
-#ifdef CONFIG_PM
-                .pm     = &pl061_dev_pm_ops,
-#endif
         },
         .id_table       = pl061_ids,
         .probe          = pl061_probe,
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
deleted file mode 100644
index 8325f580c0f..00000000000
--- a/drivers/gpio/gpio-pxa.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/*
- *  linux/arch/arm/plat-pxa/gpio.c
- *
- *  Generic PXA GPIO handling
- *
- *  Author:     Nicolas Pitre
- *  Created:    Jun 15, 2001
- *  Copyright:  MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/gpio-pxa.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/slab.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/irqs.h>
-
-/*
- * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
- * one set of registers. The register offsets are organized below:
- *
- *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
- * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
- * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
- * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
- *
- * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
- * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
- * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
- *
- * NOTE:
- *   BANK 3 is only available on PXA27x and later processors.
- *   BANK 4 and 5 are only available on PXA935
- */
-
-#define GPLR_OFFSET     0x00
-#define GPDR_OFFSET     0x0C
-#define GPSR_OFFSET     0x18
-#define GPCR_OFFSET     0x24
-#define GRER_OFFSET     0x30
-#define GFER_OFFSET     0x3C
-#define GEDR_OFFSET     0x48
-#define GAFR_OFFSET     0x54
-#define ED_MASK_OFFSET  0x9C    /* GPIO edge detection for AP side */
-
-#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-
-int pxa_last_gpio;
-static int irq_base;
-
-#ifdef CONFIG_OF
-static struct irq_domain *domain;
-static struct device_node *pxa_gpio_of_node;
-#endif
-
-struct pxa_gpio_chip {
-        struct gpio_chip chip;
-        void __iomem    *regbase;
-        char label[10];
-
-        unsigned long   irq_mask;
-        unsigned long   irq_edge_rise;
-        unsigned long   irq_edge_fall;
-        int (*set_wake)(unsigned int gpio, unsigned int on);
-
-#ifdef CONFIG_PM
-        unsigned long   saved_gplr;
-        unsigned long   saved_gpdr;
-        unsigned long   saved_grer;
-        unsigned long   saved_gfer;
-#endif
-};
-
-enum {
-        PXA25X_GPIO = 0,
-        PXA26X_GPIO,
-        PXA27X_GPIO,
-        PXA3XX_GPIO,
-        PXA93X_GPIO,
-        MMP_GPIO = 0x10,
-};
-
-static DEFINE_SPINLOCK(gpio_lock);
-static struct pxa_gpio_chip *pxa_gpio_chips;
-static int gpio_type;
-static void __iomem *gpio_reg_base;
-
-#define for_each_gpio_chip(i, c)                        \
-        for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
-
-static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
-{
-        return container_of(c, struct pxa_gpio_chip, chip)->regbase;
-}
-
-static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
-{
-        return &pxa_gpio_chips[gpio_to_bank(gpio)];
-}
-
-static inline int gpio_is_pxa_type(int type)
-{
-        return (type & MMP_GPIO) == 0;
-}
-
-static inline int gpio_is_mmp_type(int type)
-{
-        return (type & MMP_GPIO) != 0;
-}
-
-/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
- * as well as their Alternate Function value being '1' for GPIO in GAFRx.
- */
-static inline int __gpio_is_inverted(int gpio)
-{
-        if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
-                return 1;
-        return 0;
-}
-
-/*
- * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
- * function of a GPIO, and GPDRx cannot be altered once configured. It
- * is attributed as "occupied" here (I know this terminology isn't
- * accurate, you are welcome to propose a better one :-)
- */
-static inline int __gpio_is_occupied(unsigned gpio)
-{
-        struct pxa_gpio_chip *pxachip;
-        void __iomem *base;
-        unsigned long gafr = 0, gpdr = 0;
-        int ret, af = 0, dir = 0;
-
-        pxachip = gpio_to_pxachip(gpio);
-        base = gpio_chip_base(&pxachip->chip);
-        gpdr = readl_relaxed(base + GPDR_OFFSET);
-
-        switch (gpio_type) {
-        case PXA25X_GPIO:
-        case PXA26X_GPIO:
-        case PXA27X_GPIO:
-                gafr = readl_relaxed(base + GAFR_OFFSET);
-                af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
-                dir = gpdr & GPIO_bit(gpio);
-
-                if (__gpio_is_inverted(gpio))
-                        ret = (af != 1) || (dir == 0);
-                else
-                        ret = (af != 0) || (dir != 0);
-                break;
-        default:
-                ret = gpdr & GPIO_bit(gpio);
-                break;
-        }
-        return ret;
-}
-
-static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        return chip->base + offset + irq_base;
-}
-
-int pxa_irq_to_gpio(int irq)
-{
-        return irq - irq_base;
-}
-
-static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        void __iomem *base = gpio_chip_base(chip);
-        uint32_t value, mask = 1 << offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        value = readl_relaxed(base + GPDR_OFFSET);
-        if (__gpio_is_inverted(chip->base + offset))
-                value |= mask;
-        else
-                value &= ~mask;
-        writel_relaxed(value, base + GPDR_OFFSET);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-        return 0;
-}
-
-static int pxa_gpio_direction_output(struct gpio_chip *chip,
-                                     unsigned offset, int value)
-{
-        void __iomem *base = gpio_chip_base(chip);
-        uint32_t tmp, mask = 1 << offset;
-        unsigned long flags;
-
-        writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        tmp = readl_relaxed(base + GPDR_OFFSET);
-        if (__gpio_is_inverted(chip->base + offset))
-                tmp &= ~mask;
-        else
-                tmp |= mask;
-        writel_relaxed(tmp, base + GPDR_OFFSET);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
-        return 0;
-}
-
-static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
-}
-
-static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        writel_relaxed(1 << offset, gpio_chip_base(chip) +
-                                (value ? GPSR_OFFSET : GPCR_OFFSET));
-}
-
-#ifdef CONFIG_OF_GPIO
-static int pxa_gpio_of_xlate(struct gpio_chip *gc,
-                             const struct of_phandle_args *gpiospec,
-                             u32 *flags)
-{
-        if (gpiospec->args[0] > pxa_last_gpio)
-                return -EINVAL;
-
-        if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
-                return -EINVAL;
-
-        if (flags)
-                *flags = gpiospec->args[1];
-
-        return gpiospec->args[0] % 32;
-}
-#endif
-
-static int pxa_init_gpio_chip(int gpio_end,
-                                        int (*set_wake)(unsigned int, unsigned int))
-{
-        int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
-        struct pxa_gpio_chip *chips;
-
-        chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
-        if (chips == NULL) {
-                pr_err("%s: failed to allocate GPIO chips\n", __func__);
-                return -ENOMEM;
-        }
-
-        for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
-                struct gpio_chip *c = &chips[i].chip;
-
-                sprintf(chips[i].label, "gpio-%d", i);
-                chips[i].regbase = gpio_reg_base + BANK_OFF(i);
-                chips[i].set_wake = set_wake;
-
-                c->base  = gpio;
-                c->label = chips[i].label;
-
-                c->direction_input  = pxa_gpio_direction_input;
-                c->direction_output = pxa_gpio_direction_output;
-                c->get = pxa_gpio_get;
-                c->set = pxa_gpio_set;
-                c->to_irq = pxa_gpio_to_irq;
-#ifdef CONFIG_OF_GPIO
-                c->of_node = pxa_gpio_of_node;
-                c->of_xlate = pxa_gpio_of_xlate;
-                c->of_gpio_n_cells = 2;
-#endif
-
-                /* number of GPIOs on last bank may be less than 32 */
-                c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
-                gpiochip_add(c);
-        }
-        pxa_gpio_chips = chips;
-        return 0;
-}
-
-/* Update only those GRERx and GFERx edge detection register bits if those
- * bits are set in c->irq_mask
- */
-static inline void update_edge_detect(struct pxa_gpio_chip *c)
-{
-        uint32_t grer, gfer;
-
-        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
-        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
-        grer |= c->irq_edge_rise & c->irq_mask;
-        gfer |= c->irq_edge_fall & c->irq_mask;
-        writel_relaxed(grer, c->regbase + GRER_OFFSET);
-        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
-}
-
-static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
-        struct pxa_gpio_chip *c;
-        int gpio = pxa_irq_to_gpio(d->irq);
-        unsigned long gpdr, mask = GPIO_bit(gpio);
-
-        c = gpio_to_pxachip(gpio);
-
-        if (type == IRQ_TYPE_PROBE) {
-                /* Don't mess with enabled GPIOs using preconfigured edges or
-                 * GPIOs set to alternate function or to output during probe
-                 */
-                if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
-                        return 0;
-
-                if (__gpio_is_occupied(gpio))
-                        return 0;
-
-                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-        }
-
-        gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
-
-        if (__gpio_is_inverted(gpio))
-                writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
-        else
-                writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
-
-        if (type & IRQ_TYPE_EDGE_RISING)
-                c->irq_edge_rise |= mask;
-        else
-                c->irq_edge_rise &= ~mask;
-
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                c->irq_edge_fall |= mask;
-        else
-                c->irq_edge_fall &= ~mask;
-
-        update_edge_detect(c);
-
-        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
-                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
-                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
-        return 0;
-}
-
-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
-        struct pxa_gpio_chip *c;
-        int loop, gpio, gpio_base, n;
-        unsigned long gedr;
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-
-        chained_irq_enter(chip, desc);
-
-        do {
-                loop = 0;
-                for_each_gpio_chip(gpio, c) {
-                        gpio_base = c->chip.base;
-
-                        gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
-                        gedr = gedr & c->irq_mask;
-                        writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
-
-                        for_each_set_bit(n, &gedr, BITS_PER_LONG) {
-                                loop = 1;
-
-                                generic_handle_irq(gpio_to_irq(gpio_base + n));
-                        }
-                }
-        } while (loop);
-
-        chained_irq_exit(chip, desc);
-}
-
-static void pxa_ack_muxed_gpio(struct irq_data *d)
-{
-        int gpio = pxa_irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
-
-        writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
-}
-
-static void pxa_mask_muxed_gpio(struct irq_data *d)
-{
-        int gpio = pxa_irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
-        uint32_t grer, gfer;
-
-        c->irq_mask &= ~GPIO_bit(gpio);
-
-        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
-        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
-        writel_relaxed(grer, c->regbase + GRER_OFFSET);
-        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
-}
-
-static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
-{
-        int gpio = pxa_irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
-
-        if (c->set_wake)
-                return c->set_wake(gpio, on);
-        else
-                return 0;
-}
-
-static void pxa_unmask_muxed_gpio(struct irq_data *d)
-{
-        int gpio = pxa_irq_to_gpio(d->irq);
-        struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
-
-        c->irq_mask |= GPIO_bit(gpio);
-        update_edge_detect(c);
-}
-
-static struct irq_chip pxa_muxed_gpio_chip = {
-        .name           = "GPIO",
-        .irq_ack        = pxa_ack_muxed_gpio,
-        .irq_mask       = pxa_mask_muxed_gpio,
-        .irq_unmask     = pxa_unmask_muxed_gpio,
-        .irq_set_type   = pxa_gpio_irq_type,
-        .irq_set_wake   = pxa_gpio_set_wake,
-};
-
-static int pxa_gpio_nums(void)
-{
-        int count = 0;
-
-#ifdef CONFIG_ARCH_PXA
-        if (cpu_is_pxa25x()) {
-#ifdef CONFIG_CPU_PXA26x
-                count = 89;
-                gpio_type = PXA26X_GPIO;
-#elif defined(CONFIG_PXA25x)
-                count = 84;
-                gpio_type = PXA26X_GPIO;
-#endif /* CONFIG_CPU_PXA26x */
-        } else if (cpu_is_pxa27x()) {
-                count = 120;
-                gpio_type = PXA27X_GPIO;
-        } else if (cpu_is_pxa93x()) {
-                count = 191;
-                gpio_type = PXA93X_GPIO;
-        } else if (cpu_is_pxa3xx()) {
-                count = 127;
-                gpio_type = PXA3XX_GPIO;
-        }
-#endif /* CONFIG_ARCH_PXA */
-
-#ifdef CONFIG_ARCH_MMP
-        if (cpu_is_pxa168() || cpu_is_pxa910()) {
-                count = 127;
-                gpio_type = MMP_GPIO;
-        } else if (cpu_is_mmp2()) {
-                count = 191;
-                gpio_type = MMP_GPIO;
-        }
-#endif /* CONFIG_ARCH_MMP */
-        return count;
-}
-
-#ifdef CONFIG_OF
-static struct of_device_id pxa_gpio_dt_ids[] = {
-        { .compatible = "mrvl,pxa-gpio" },
-        { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
-        {}
-};
-
-static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
-                              irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                 handle_edge_irq);
-        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        return 0;
-}
-
-const struct irq_domain_ops pxa_irq_domain_ops = {
-        .map    = pxa_irq_domain_map,
-        .xlate  = irq_domain_xlate_twocell,
-};
-
-static int pxa_gpio_probe_dt(struct platform_device *pdev)
-{
-        int ret, nr_banks, nr_gpios;
-        struct device_node *prev, *next, *np = pdev->dev.of_node;
-        const struct of_device_id *of_id =
-                                of_match_device(pxa_gpio_dt_ids, &pdev->dev);
-
-        if (!of_id) {
-                dev_err(&pdev->dev, "Failed to find gpio controller\n");
-                return -EFAULT;
-        }
-        gpio_type = (int)of_id->data;
-
-        next = of_get_next_child(np, NULL);
-        prev = next;
-        if (!next) {
-                dev_err(&pdev->dev, "Failed to find child gpio node\n");
-                ret = -EINVAL;
-                goto err;
-        }
-        for (nr_banks = 1; ; nr_banks++) {
-                next = of_get_next_child(np, prev);
-                if (!next)
-                        break;
-                prev = next;
-        }
-        of_node_put(prev);
-        nr_gpios = nr_banks << 5;
-        pxa_last_gpio = nr_gpios - 1;
-
-        irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
-        if (irq_base < 0) {
-                dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
-                goto err;
-        }
-        domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
-                                       &pxa_irq_domain_ops, NULL);
-        pxa_gpio_of_node = np;
-        return 0;
-err:
-        iounmap(gpio_reg_base);
-        return ret;
-}
-#else
-#define pxa_gpio_probe_dt(pdev)         (-1)
-#endif
-
-static int pxa_gpio_probe(struct platform_device *pdev)
-{
-        struct pxa_gpio_chip *c;
-        struct resource *res;
-        struct clk *clk;
-        struct pxa_gpio_platform_data *info;
-        int gpio, irq, ret, use_of = 0;
-        int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
-
-        ret = pxa_gpio_probe_dt(pdev);
-        if (ret < 0) {
-                pxa_last_gpio = pxa_gpio_nums();
-#ifdef CONFIG_ARCH_PXA
-                if (gpio_is_pxa_type(gpio_type))
-                        irq_base = PXA_GPIO_TO_IRQ(0);
-#endif
-#ifdef CONFIG_ARCH_MMP
-                if (gpio_is_mmp_type(gpio_type))
-                        irq_base = MMP_GPIO_TO_IRQ(0);
-#endif
-        } else {
-                use_of = 1;
-        }
-
-        if (!pxa_last_gpio)
-                return -EINVAL;
-
-        irq0 = platform_get_irq_byname(pdev, "gpio0");
-        irq1 = platform_get_irq_byname(pdev, "gpio1");
-        irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
-        if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
-                || (irq_mux <= 0))
-                return -EINVAL;
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                return -EINVAL;
-        gpio_reg_base = ioremap(res->start, resource_size(res));
-        if (!gpio_reg_base)
-                return -EINVAL;
-
-        if (irq0 > 0)
-                gpio_offset = 2;
-
-        clk = clk_get(&pdev->dev, NULL);
-        if (IS_ERR(clk)) {
-                dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
-                        PTR_ERR(clk));
-                iounmap(gpio_reg_base);
-                return PTR_ERR(clk);
-        }
-        ret = clk_prepare_enable(clk);
-        if (ret) {
-                clk_put(clk);
-                iounmap(gpio_reg_base);
-                return ret;
-        }
-
-        /* Initialize GPIO chips */
-        info = dev_get_platdata(&pdev->dev);
-        pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
-
-        /* clear all GPIO edge detects */
-        for_each_gpio_chip(gpio, c) {
-                writel_relaxed(0, c->regbase + GFER_OFFSET);
-                writel_relaxed(0, c->regbase + GRER_OFFSET);
-                writel_relaxed(~0,c->regbase + GEDR_OFFSET);
-                /* unmask GPIO edge detect for AP side */
-                if (gpio_is_mmp_type(gpio_type))
-                        writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
-        }
-
-        if (!use_of) {
-#ifdef CONFIG_ARCH_PXA
-                irq = gpio_to_irq(0);
-                irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
-
-                irq = gpio_to_irq(1);
-                irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
-#endif
-
-                for (irq  = gpio_to_irq(gpio_offset);
-                        irq <= gpio_to_irq(pxa_last_gpio); irq++) {
-                        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
-                                                 handle_edge_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-
-        irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
-        return 0;
-}
-
-static struct platform_driver pxa_gpio_driver = {
-        .probe          = pxa_gpio_probe,
-        .driver         = {
-                .name   = "pxa-gpio",
-                .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
-        },
-};
-
-static int __init pxa_gpio_init(void)
-{
-        return platform_driver_register(&pxa_gpio_driver);
-}
-postcore_initcall(pxa_gpio_init);
-
-#ifdef CONFIG_PM
-static int pxa_gpio_suspend(void)
-{
-        struct pxa_gpio_chip *c;
-        int gpio;
-
-        for_each_gpio_chip(gpio, c) {
-                c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
-                c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
-                c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
-                c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
-
-                /* Clear GPIO transition detect bits */
-                writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
-        }
-        return 0;
-}
-
-static void pxa_gpio_resume(void)
-{
-        struct pxa_gpio_chip *c;
-        int gpio;
-
-        for_each_gpio_chip(gpio, c) {
-                /* restore level with set/clear */
-                writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
-                writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
-
-                writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
-                writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
-                writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
-        }
-}
-#else
-#define pxa_gpio_suspend        NULL
-#define pxa_gpio_resume         NULL
-#endif
-
-struct syscore_ops pxa_gpio_syscore_ops = {
-        .suspend        = pxa_gpio_suspend,
-        .resume         = pxa_gpio_resume,
-};
-
-static int __init pxa_gpio_sysinit(void)
-{
-        register_syscore_ops(&pxa_gpio_syscore_ops);
-        return 0;
-}
-postcore_initcall(pxa_gpio_sysinit);
diff --git a/drivers/gpio/gpio-rc5t583.c b/drivers/gpio/gpio-rc5t583.c
deleted file mode 100644
index e63d6a397e1..00000000000
--- a/drivers/gpio/gpio-rc5t583.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * GPIO driver for RICOH583 power management chip.
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- * Author: Laxman dewangan <ldewangan@nvidia.com>
- *
- * Based on code
- *      Copyright (C) 2011 RICOH COMPANY,LTD
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/mfd/rc5t583.h>
-
-struct rc5t583_gpio {
-        struct gpio_chip gpio_chip;
-        struct rc5t583 *rc5t583;
-};
-
-static inline struct rc5t583_gpio *to_rc5t583_gpio(struct gpio_chip *chip)
-{
-        return container_of(chip, struct rc5t583_gpio, gpio_chip);
-}
-
-static int rc5t583_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-        struct device *parent = rc5t583_gpio->rc5t583->dev;
-        uint8_t val = 0;
-        int ret;
-
-        ret = rc5t583_read(parent, RC5T583_GPIO_MON_IOIN, &val);
-        if (ret < 0)
-                return ret;
-
-        return !!(val & BIT(offset));
-}
-
-static void rc5t583_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-        struct device *parent = rc5t583_gpio->rc5t583->dev;
-        if (val)
-                rc5t583_set_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
-        else
-                rc5t583_clear_bits(parent, RC5T583_GPIO_IOOUT, BIT(offset));
-}
-
-static int rc5t583_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-        struct device *parent = rc5t583_gpio->rc5t583->dev;
-        int ret;
-
-        ret = rc5t583_clear_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
-        if (ret < 0)
-                return ret;
-
-        /* Set pin to gpio mode */
-        return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
-}
-
-static int rc5t583_gpio_dir_output(struct gpio_chip *gc, unsigned offset,
-                        int value)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-        struct device *parent = rc5t583_gpio->rc5t583->dev;
-        int ret;
-
-        rc5t583_gpio_set(gc, offset, value);
-        ret = rc5t583_set_bits(parent, RC5T583_GPIO_IOSEL, BIT(offset));
-        if (ret < 0)
-                return ret;
-
-        /* Set pin to gpio mode */
-        return rc5t583_clear_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
-}
-
-static int rc5t583_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-
-        if ((offset >= 0) && (offset < 8))
-                return rc5t583_gpio->rc5t583->irq_base +
-                                RC5T583_IRQ_GPIO0 + offset;
-        return -EINVAL;
-}
-
-static void rc5t583_gpio_free(struct gpio_chip *gc, unsigned offset)
-{
-        struct rc5t583_gpio *rc5t583_gpio = to_rc5t583_gpio(gc);
-        struct device *parent = rc5t583_gpio->rc5t583->dev;
-
-        rc5t583_set_bits(parent, RC5T583_GPIO_PGSEL, BIT(offset));
-}
-
-static int rc5t583_gpio_probe(struct platform_device *pdev)
-{
-        struct rc5t583 *rc5t583 = dev_get_drvdata(pdev->dev.parent);
-        struct rc5t583_platform_data *pdata = dev_get_platdata(rc5t583->dev);
-        struct rc5t583_gpio *rc5t583_gpio;
-
-        rc5t583_gpio = devm_kzalloc(&pdev->dev, sizeof(*rc5t583_gpio),
-                                        GFP_KERNEL);
-        if (!rc5t583_gpio) {
-                dev_warn(&pdev->dev, "Mem allocation for rc5t583_gpio failed");
-                return -ENOMEM;
-        }
-
-        rc5t583_gpio->gpio_chip.label = "gpio-rc5t583",
-        rc5t583_gpio->gpio_chip.owner = THIS_MODULE,
-        rc5t583_gpio->gpio_chip.free = rc5t583_gpio_free,
-        rc5t583_gpio->gpio_chip.direction_input = rc5t583_gpio_dir_input,
-        rc5t583_gpio->gpio_chip.direction_output = rc5t583_gpio_dir_output,
-        rc5t583_gpio->gpio_chip.set = rc5t583_gpio_set,
-        rc5t583_gpio->gpio_chip.get = rc5t583_gpio_get,
-        rc5t583_gpio->gpio_chip.to_irq = rc5t583_gpio_to_irq,
-        rc5t583_gpio->gpio_chip.ngpio = RC5T583_MAX_GPIO,
-        rc5t583_gpio->gpio_chip.can_sleep = 1,
-        rc5t583_gpio->gpio_chip.dev = &pdev->dev;
-        rc5t583_gpio->gpio_chip.base = -1;
-        rc5t583_gpio->rc5t583 = rc5t583;
-
-        if (pdata && pdata->gpio_base)
-                rc5t583_gpio->gpio_chip.base = pdata->gpio_base;
-
-        platform_set_drvdata(pdev, rc5t583_gpio);
-
-        return gpiochip_add(&rc5t583_gpio->gpio_chip);
-}
-
-static int rc5t583_gpio_remove(struct platform_device *pdev)
-{
-        struct rc5t583_gpio *rc5t583_gpio = platform_get_drvdata(pdev);
-
-        return gpiochip_remove(&rc5t583_gpio->gpio_chip);
-}
-
-static struct platform_driver rc5t583_gpio_driver = {
-        .driver = {
-                .name    = "rc5t583-gpio",
-                .owner   = THIS_MODULE,
-        },
-        .probe          = rc5t583_gpio_probe,
-        .remove         = rc5t583_gpio_remove,
-};
-
-static int __init rc5t583_gpio_init(void)
-{
-        return platform_driver_register(&rc5t583_gpio_driver);
-}
-subsys_initcall(rc5t583_gpio_init);
-
-static void __exit rc5t583_gpio_exit(void)
-{
-        platform_driver_unregister(&rc5t583_gpio_driver);
-}
-module_exit(rc5t583_gpio_exit);
-
-MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
-MODULE_DESCRIPTION("GPIO interface for RC5T583");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:rc5t583-gpio");
diff --git a/drivers/gpio/gpio-rdc321x.c b/drivers/gpio/gpio-rdc321x.c
index 1bf55f67f7a..2762698e020 100644
--- a/drivers/gpio/gpio-rdc321x.c
+++ b/drivers/gpio/gpio-rdc321x.c
@@ -128,7 +128,7 @@ static int rdc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 /*
  * Cache the initial value of both GPIO data registers
  */
-static int rdc321x_gpio_probe(struct platform_device *pdev)
+static int __devinit rdc321x_gpio_probe(struct platform_device *pdev)
 {
         int err;
         struct resource *r;
@@ -170,7 +170,6 @@ static int rdc321x_gpio_probe(struct platform_device *pdev)
         rdc321x_gpio_dev->reg2_data_base = r->start + 0x4;
 
         rdc321x_gpio_dev->chip.label = "rdc321x-gpio";
-        rdc321x_gpio_dev->chip.owner = THIS_MODULE;
         rdc321x_gpio_dev->chip.direction_input = rdc_gpio_direction_input;
         rdc321x_gpio_dev->chip.direction_output = rdc_gpio_config;
         rdc321x_gpio_dev->chip.get = rdc_gpio_get_value;
@@ -206,7 +205,7 @@ out_free:
         return err;
 }
 
-static int rdc321x_gpio_remove(struct platform_device *pdev)
+static int __devexit rdc321x_gpio_remove(struct platform_device *pdev)
 {
         int ret;
         struct rdc321x_gpio *rdc321x_gpio_dev = platform_get_drvdata(pdev);
@@ -225,10 +224,21 @@ static struct platform_driver rdc321x_gpio_driver = {
         .driver.name    = "rdc321x-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = rdc321x_gpio_probe,
-        .remove         = rdc321x_gpio_remove,
+        .remove         = __devexit_p(rdc321x_gpio_remove),
 };
 
-module_platform_driver(rdc321x_gpio_driver);
+static int __init rdc321x_gpio_init(void)
+{
+        return platform_driver_register(&rdc321x_gpio_driver);
+}
+
+static void __exit rdc321x_gpio_exit(void)
+{
+        platform_driver_unregister(&rdc321x_gpio_driver);
+}
+
+module_init(rdc321x_gpio_init);
+module_exit(rdc321x_gpio_exit);
 
 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 MODULE_DESCRIPTION("RDC321x GPIO driver");
diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c
deleted file mode 100644
index 8ea3b33d4b4..00000000000
--- a/drivers/gpio/gpio-sa1100.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/gpio.c
- *
- * Generic SA-1100 GPIO handling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-
-static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        return GPLR & GPIO_GPIO(offset);
-}
-
-static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        if (value)
-                GPSR = GPIO_GPIO(offset);
-        else
-                GPCR = GPIO_GPIO(offset);
-}
-
-static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        GPDR &= ~GPIO_GPIO(offset);
-        local_irq_restore(flags);
-        return 0;
-}
-
-static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        sa1100_gpio_set(chip, offset, value);
-        GPDR |= GPIO_GPIO(offset);
-        local_irq_restore(flags);
-        return 0;
-}
-
-static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        return offset < 11 ? (IRQ_GPIO0 + offset) : (IRQ_GPIO11 - 11 + offset);
-}
-
-static struct gpio_chip sa1100_gpio_chip = {
-        .label                  = "gpio",
-        .direction_input        = sa1100_direction_input,
-        .direction_output       = sa1100_direction_output,
-        .set                    = sa1100_gpio_set,
-        .get                    = sa1100_gpio_get,
-        .to_irq                 = sa1100_to_irq,
-        .base                   = 0,
-        .ngpio                  = GPIO_MAX + 1,
-};
-
-void __init sa1100_init_gpio(void)
-{
-        gpiochip_add(&sa1100_gpio_chip);
-}
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
deleted file mode 100644
index 01f7fe95559..00000000000
--- a/drivers/gpio/gpio-samsung.c
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * SAMSUNG - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/of_address.h>
-
-#include <asm/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <plat/gpio-fns.h>
-#include <plat/pm.h>
-
-int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
-                                unsigned int off, samsung_gpio_pull_t pull)
-{
-        void __iomem *reg = chip->base + 0x08;
-        int shift = off * 2;
-        u32 pup;
-
-        pup = __raw_readl(reg);
-        pup &= ~(3 << shift);
-        pup |= pull << shift;
-        __raw_writel(pup, reg);
-
-        return 0;
-}
-
-samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
-                                                unsigned int off)
-{
-        void __iomem *reg = chip->base + 0x08;
-        int shift = off * 2;
-        u32 pup = __raw_readl(reg);
-
-        pup >>= shift;
-        pup &= 0x3;
-
-        return (__force samsung_gpio_pull_t)pup;
-}
-
-int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
-                         unsigned int off, samsung_gpio_pull_t pull)
-{
-        switch (pull) {
-        case S3C_GPIO_PULL_NONE:
-                pull = 0x01;
-                break;
-        case S3C_GPIO_PULL_UP:
-                pull = 0x00;
-                break;
-        case S3C_GPIO_PULL_DOWN:
-                pull = 0x02;
-                break;
-        }
-        return samsung_gpio_setpull_updown(chip, off, pull);
-}
-
-samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
-                                         unsigned int off)
-{
-        samsung_gpio_pull_t pull;
-
-        pull = samsung_gpio_getpull_updown(chip, off);
-
-        switch (pull) {
-        case 0x00:
-                pull = S3C_GPIO_PULL_UP;
-                break;
-        case 0x01:
-        case 0x03:
-                pull = S3C_GPIO_PULL_NONE;
-                break;
-        case 0x02:
-                pull = S3C_GPIO_PULL_DOWN;
-                break;
-        }
-
-        return pull;
-}
-
-static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
-                                  unsigned int off, samsung_gpio_pull_t pull,
-                                  samsung_gpio_pull_t updown)
-{
-        void __iomem *reg = chip->base + 0x08;
-        u32 pup = __raw_readl(reg);
-
-        if (pull == updown)
-                pup &= ~(1 << off);
-        else if (pull == S3C_GPIO_PULL_NONE)
-                pup |= (1 << off);
-        else
-                return -EINVAL;
-
-        __raw_writel(pup, reg);
-        return 0;
-}
-
-static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
-                                                  unsigned int off,
-                                                  samsung_gpio_pull_t updown)
-{
-        void __iomem *reg = chip->base + 0x08;
-        u32 pup = __raw_readl(reg);
-
-        pup &= (1 << off);
-        return pup ? S3C_GPIO_PULL_NONE : updown;
-}
-
-samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
-                                             unsigned int off)
-{
-        return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
-}
-
-int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
-                             unsigned int off, samsung_gpio_pull_t pull)
-{
-        return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
-}
-
-samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
-                                               unsigned int off)
-{
-        return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
-}
-
-int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
-                               unsigned int off, samsung_gpio_pull_t pull)
-{
-        return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
-}
-
-static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
-                                unsigned int off, samsung_gpio_pull_t pull)
-{
-        if (pull == S3C_GPIO_PULL_UP)
-                pull = 3;
-
-        return samsung_gpio_setpull_updown(chip, off, pull);
-}
-
-static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
-                                                unsigned int off)
-{
-        samsung_gpio_pull_t pull;
-
-        pull = samsung_gpio_getpull_updown(chip, off);
-
-        if (pull == 3)
-                pull = S3C_GPIO_PULL_UP;
-
-        return pull;
-}
-
-/*
- * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has two bits of configuration per gpio, which have the following
- * functions:
- *      00 = input
- *      01 = output
- *      1x = special function
- */
-
-static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
-                                    unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = off * 2;
-        u32 con;
-
-        if (samsung_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                if (cfg > 3)
-                        return -EINVAL;
-
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0x3 << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-/*
- * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
- * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
- * S3C_GPIO_SPECIAL() macro.
- */
-
-static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
-                                             unsigned int off)
-{
-        u32 con;
-
-        con = __raw_readl(chip->base);
-        con >>= off * 2;
-        con &= 3;
-
-        /* this conversion works for IN and OUT as well as special mode */
-        return S3C_GPIO_SPECIAL(con);
-}
-
-/*
- * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register has 4 bits
- * of control per GPIO, generally in the form of:
- *      0000 = Input
- *      0001 = Output
- *      others = Special functions (dependent on bank)
- *
- * Note, since the code to deal with the case where there are two control
- * registers instead of one, we do not have a separate set of functions for
- * each case.
- */
-
-static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
-                                    unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = (off & 7) * 4;
-        u32 con;
-
-        if (off < 8 && chip->chip.ngpio > 8)
-                reg -= 4;
-
-        if (samsung_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-/*
- * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
- * register setting into a value the software can use, such as could be passed
- * to samsung_gpio_setcfg_4bit().
- *
- * @sa samsung_gpio_getcfg_2bit
- */
-
-static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
-                                         unsigned int off)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = (off & 7) * 4;
-        u32 con;
-
-        if (off < 8 && chip->chip.ngpio > 8)
-                reg -= 4;
-
-        con = __raw_readl(reg);
-        con >>= shift;
-        con &= 0xf;
-
-        /* this conversion works for IN and OUT as well as special mode */
-        return S3C_GPIO_SPECIAL(con);
-}
-
-#ifdef CONFIG_PLAT_S3C24XX
-/*
- * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has one bit of configuration for the gpio, where setting the bit
- * means the pin is in special function mode and unset means output.
- */
-
-static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
-                                     unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = off;
-        u32 con;
-
-        if (samsung_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-
-                /* Map output to 0, and SFN2 to 1 */
-                cfg -= 1;
-                if (cfg > 1)
-                        return -EINVAL;
-
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0x1 << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-/*
- * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
- * GPIO configuration value.
- *
- * @sa samsung_gpio_getcfg_2bit
- * @sa samsung_gpio_getcfg_4bit
- */
-
-static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
-                                          unsigned int off)
-{
-        u32 con;
-
-        con = __raw_readl(chip->base);
-        con >>= off;
-        con &= 1;
-        con++;
-
-        return S3C_GPIO_SFN(con);
-}
-#endif
-
-#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
-static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
-                                     unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift;
-        u32 con;
-
-        switch (off) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                shift = (off & 7) * 4;
-                reg -= 4;
-                break;
-        case 6:
-                shift = ((off + 1) & 7) * 4;
-                reg -= 4;
-        default:
-                shift = ((off + 1) & 7) * 4;
-                break;
-        }
-
-        if (samsung_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-#endif
-
-static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
-                                           int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chipcfg++) {
-                if (!chipcfg->set_config)
-                        chipcfg->set_config = samsung_gpio_setcfg_4bit;
-                if (!chipcfg->get_config)
-                        chipcfg->get_config = samsung_gpio_getcfg_4bit;
-                if (!chipcfg->set_pull)
-                        chipcfg->set_pull = samsung_gpio_setpull_updown;
-                if (!chipcfg->get_pull)
-                        chipcfg->get_pull = samsung_gpio_getpull_updown;
-        }
-}
-
-struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
-        .set_config     = samsung_gpio_setcfg_2bit,
-        .get_config     = samsung_gpio_getcfg_2bit,
-};
-
-#ifdef CONFIG_PLAT_S3C24XX
-static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
-        .set_config     = s3c24xx_gpio_setcfg_abank,
-        .get_config     = s3c24xx_gpio_getcfg_abank,
-};
-#endif
-
-#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
-static struct samsung_gpio_cfg exynos_gpio_cfg = {
-        .set_pull       = exynos_gpio_setpull,
-        .get_pull       = exynos_gpio_getpull,
-        .set_config     = samsung_gpio_setcfg_4bit,
-        .get_config     = samsung_gpio_getcfg_4bit,
-};
-#endif
-
-#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
-static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
-        .cfg_eint       = 0x3,
-        .set_config     = s5p64x0_gpio_setcfg_rbank,
-        .get_config     = samsung_gpio_getcfg_4bit,
-        .set_pull       = samsung_gpio_setpull_updown,
-        .get_pull       = samsung_gpio_getpull_updown,
-};
-#endif
-
-static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
-        [0] = {
-                .cfg_eint       = 0x0,
-        },
-        [1] = {
-                .cfg_eint       = 0x3,
-        },
-        [2] = {
-                .cfg_eint       = 0x7,
-        },
-        [3] = {
-                .cfg_eint       = 0xF,
-        },
-        [4] = {
-                .cfg_eint       = 0x0,
-                .set_config     = samsung_gpio_setcfg_2bit,
-                .get_config     = samsung_gpio_getcfg_2bit,
-        },
-        [5] = {
-                .cfg_eint       = 0x2,
-                .set_config     = samsung_gpio_setcfg_2bit,
-                .get_config     = samsung_gpio_getcfg_2bit,
-        },
-        [6] = {
-                .cfg_eint       = 0x3,
-                .set_config     = samsung_gpio_setcfg_2bit,
-                .get_config     = samsung_gpio_getcfg_2bit,
-        },
-        [7] = {
-                .set_config     = samsung_gpio_setcfg_2bit,
-                .get_config     = samsung_gpio_getcfg_2bit,
-        },
-        [8] = {
-                .set_pull       = exynos_gpio_setpull,
-                .get_pull       = exynos_gpio_getpull,
-        },
-        [9] = {
-                .cfg_eint       = 0x3,
-                .set_pull       = exynos_gpio_setpull,
-                .get_pull       = exynos_gpio_getpull,
-        }
-};
-
-/*
- * Default routines for controlling GPIO, based on the original S3C24XX
- * GPIO functions which deal with the case where each gpio bank of the
- * chip is as following:
- *
- * base + 0x00: Control register, 2 bits per gpio
- *              gpio n: 2 bits starting at (2*n)
- *              00 = input, 01 = output, others mean special-function
- * base + 0x04: Data register, 1 bit per gpio
- *              bit n: data bit n
-*/
-
-static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long con;
-
-        samsung_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(base + 0x00);
-        con &= ~(3 << (offset * 2));
-
-        __raw_writel(con, base + 0x00);
-
-        samsung_gpio_unlock(ourchip, flags);
-        return 0;
-}
-
-static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
-                                       unsigned offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-        unsigned long con;
-
-        samsung_gpio_lock(ourchip, flags);
-
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-        __raw_writel(dat, base + 0x04);
-
-        con = __raw_readl(base + 0x00);
-        con &= ~(3 << (offset * 2));
-        con |= 1 << (offset * 2);
-
-        __raw_writel(con, base + 0x00);
-        __raw_writel(dat, base + 0x04);
-
-        samsung_gpio_unlock(ourchip, flags);
-        return 0;
-}
-
-/*
- * The samsung_gpiolib_4bit routines are to control the gpio banks where
- * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
- * following example:
- *
- * base + 0x00: Control register, 4 bits per gpio
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x04: Data register, 1 bit per gpio
- *              bit n: data bit n
- *
- * Note, since the data register is one bit per gpio and is at base + 0x4
- * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
- * state of the output.
- */
-
-static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
-                                      unsigned int offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long con;
-
-        con = __raw_readl(base + GPIOCON_OFF);
-        if (ourchip->bitmap_gpio_int & BIT(offset))
-                con |= 0xf << con_4bit_shift(offset);
-        else
-                con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, base + GPIOCON_OFF);
-
-        pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
-
-        return 0;
-}
-
-static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
-                                       unsigned int offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long con;
-        unsigned long dat;
-
-        con = __raw_readl(base + GPIOCON_OFF);
-        con &= ~(0xf << con_4bit_shift(offset));
-        con |= 0x1 << con_4bit_shift(offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(dat, base + GPIODAT_OFF);
-        __raw_writel(con, base + GPIOCON_OFF);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
-
-        return 0;
-}
-
-/*
- * The next set of routines are for the case where the GPIO configuration
- * registers are 4 bits per GPIO but there is more than one register (the
- * bank has more than 8 GPIOs.
- *
- * This case is the similar to the 4 bit case, but the registers are as
- * follows:
- *
- * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x08: Data register, 1 bit per gpio
- *              bit n: data bit n
- *
- * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
- * routines we store the 'base + 0x4' address so that these routines see
- * the data register at ourchip->base + 0x04.
- */
-
-static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
-                                       unsigned int offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-
-        if (offset > 7)
-                offset -= 8;
-        else
-                regcon -= 4;
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-
-        pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
-
-        return 0;
-}
-
-static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
-                                        unsigned int offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned con_offset = offset;
-
-        if (con_offset > 7)
-                con_offset -= 8;
-        else
-                regcon -= 4;
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(dat, base + GPIODAT_OFF);
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
-
-        return 0;
-}
-
-#ifdef CONFIG_PLAT_S3C24XX
-/* The next set of routines are for the case of s3c24xx bank a */
-
-static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
-{
-        return -EINVAL;
-}
-
-static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-        unsigned long con;
-
-        local_irq_save(flags);
-
-        con = __raw_readl(base + 0x00);
-        dat = __raw_readl(base + 0x04);
-
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-
-        __raw_writel(dat, base + 0x04);
-
-        con &= ~(1 << offset);
-
-        __raw_writel(con, base + 0x00);
-        __raw_writel(dat, base + 0x04);
-
-        local_irq_restore(flags);
-        return 0;
-}
-#endif
-
-/* The next set of routines are for the case of s5p64x0 bank r */
-
-static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
-                                       unsigned int offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long flags;
-
-        switch (offset) {
-        case 6:
-                offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                offset -= 7;
-                break;
-        }
-
-        samsung_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-
-        samsung_gpio_unlock(ourchip, flags);
-
-        return 0;
-}
-
-static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
-                                        unsigned int offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned long flags;
-        unsigned con_offset  = offset;
-
-        switch (con_offset) {
-        case 6:
-                con_offset += 1;
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-                regcon -= 4;
-                break;
-        default:
-                con_offset -= 7;
-                break;
-        }
-
-        samsung_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        samsung_gpio_unlock(ourchip, flags);
-
-        return 0;
-}
-
-static void samsung_gpiolib_set(struct gpio_chip *chip,
-                                unsigned offset, int value)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-
-        samsung_gpio_lock(ourchip, flags);
-
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-        __raw_writel(dat, base + 0x04);
-
-        samsung_gpio_unlock(ourchip, flags);
-}
-
-static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
-        unsigned long val;
-
-        val = __raw_readl(ourchip->base + 0x04);
-        val >>= offset;
-        val &= 1;
-
-        return val;
-}
-
-/*
- * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
- * for use with the configuration calls, and other parts of the s3c gpiolib
- * support code.
- *
- * Not all s3c support code will need this, as some configurations of cpu
- * may only support one or two different configuration options and have an
- * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
- * the machine support file should provide its own samsung_gpiolib_getchip()
- * and any other necessary functions.
- */
-
-#ifdef CONFIG_S3C_GPIO_TRACK
-struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
-
-static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
-{
-        unsigned int gpn;
-        int i;
-
-        gpn = chip->chip.base;
-        for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
-                BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
-                s3c_gpios[gpn] = chip;
-        }
-}
-#endif /* CONFIG_S3C_GPIO_TRACK */
-
-/*
- * samsung_gpiolib_add() - add the Samsung gpio_chip.
- * @chip: The chip to register
- *
- * This is a wrapper to gpiochip_add() that takes our specific gpio chip
- * information and makes the necessary alterations for the platform and
- * notes the information for use with the configuration systems and any
- * other parts of the system.
- */
-
-static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
-{
-        struct gpio_chip *gc = &chip->chip;
-        int ret;
-
-        BUG_ON(!chip->base);
-        BUG_ON(!gc->label);
-        BUG_ON(!gc->ngpio);
-
-        spin_lock_init(&chip->lock);
-
-        if (!gc->direction_input)
-                gc->direction_input = samsung_gpiolib_2bit_input;
-        if (!gc->direction_output)
-                gc->direction_output = samsung_gpiolib_2bit_output;
-        if (!gc->set)
-                gc->set = samsung_gpiolib_set;
-        if (!gc->get)
-                gc->get = samsung_gpiolib_get;
-
-#ifdef CONFIG_PM
-        if (chip->pm != NULL) {
-                if (!chip->pm->save || !chip->pm->resume)
-                        pr_err("gpio: %s has missing PM functions\n",
-                               gc->label);
-        } else
-                pr_err("gpio: %s has no PM function\n", gc->label);
-#endif
-
-        /* gpiochip_add() prints own failure message on error. */
-        ret = gpiochip_add(gc);
-        if (ret >= 0)
-                s3c_gpiolib_track(chip);
-}
-
-#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
-static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
-                        const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        unsigned int pin;
-
-        if (WARN_ON(gc->of_gpio_n_cells < 3))
-                return -EINVAL;
-
-        if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
-                return -EINVAL;
-
-        if (gpiospec->args[0] > gc->ngpio)
-                return -EINVAL;
-
-        pin = gc->base + gpiospec->args[0];
-
-        if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
-                pr_warn("gpio_xlate: failed to set pin function\n");
-        if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
-                pr_warn("gpio_xlate: failed to set pin pull up/down\n");
-
-        if (flags)
-                *flags = gpiospec->args[2] >> 16;
-
-        return gpiospec->args[0];
-}
-
-static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
-        { .compatible = "samsung,s3c24xx-gpio", },
-        {}
-};
-
-static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
-                                                 u64 base, u64 offset)
-{
-        struct gpio_chip *gc =  &chip->chip;
-        u64 address;
-
-        if (!of_have_populated_dt())
-                return;
-
-        address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
-        gc->of_node = of_find_matching_node_by_address(NULL,
-                        s3c24xx_gpio_dt_match, address);
-        if (!gc->of_node) {
-                pr_info("gpio: device tree node not found for gpio controller"
-                        " with base address %08llx\n", address);
-                return;
-        }
-        gc->of_gpio_n_cells = 3;
-        gc->of_xlate = s3c24xx_gpio_xlate;
-}
-#else
-static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
-                                                 u64 base, u64 offset)
-{
-        return;
-}
-#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
-
-static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
-                                             int nr_chips, void __iomem *base)
-{
-        int i;
-        struct gpio_chip *gc = &chip->chip;
-
-        for (i = 0 ; i < nr_chips; i++, chip++) {
-                /* skip banks not present on SoC */
-                if (chip->chip.base >= S3C_GPIO_END)
-                        continue;
-
-                if (!chip->config)
-                        chip->config = &s3c24xx_gpiocfg_default;
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
-                if ((base != NULL) && (chip->base == NULL))
-                        chip->base = base + ((i) * 0x10);
-
-                if (!gc->direction_input)
-                        gc->direction_input = samsung_gpiolib_2bit_input;
-                if (!gc->direction_output)
-                        gc->direction_output = samsung_gpiolib_2bit_output;
-
-                samsung_gpiolib_add(chip);
-
-                s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
-        }
-}
-
-static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
-                                                  int nr_chips, void __iomem *base,
-                                                  unsigned int offset)
-{
-        int i;
-
-        for (i = 0 ; i < nr_chips; i++, chip++) {
-                chip->chip.direction_input = samsung_gpiolib_2bit_input;
-                chip->chip.direction_output = samsung_gpiolib_2bit_output;
-
-                if (!chip->config)
-                        chip->config = &samsung_gpio_cfgs[7];
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
-                if ((base != NULL) && (chip->base == NULL))
-                        chip->base = base + ((i) * offset);
-
-                samsung_gpiolib_add(chip);
-        }
-}
-
-/*
- * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
- * @chip: The gpio chip that is being configured.
- * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
- *
- * This helper deal with the GPIO cases where the control register has 4 bits
- * of control per GPIO, generally in the form of:
- * 0000 = Input
- * 0001 = Output
- * others = Special functions (dependent on bank)
- *
- * Note, since the code to deal with the case where there are two control
- * registers instead of one, we do not have a separate set of function
- * (samsung_gpiolib_add_4bit2_chips)for each case.
- */
-
-static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
-                                                  int nr_chips, void __iomem *base)
-{
-        int i;
-
-        for (i = 0 ; i < nr_chips; i++, chip++) {
-                chip->chip.direction_input = samsung_gpiolib_4bit_input;
-                chip->chip.direction_output = samsung_gpiolib_4bit_output;
-
-                if (!chip->config)
-                        chip->config = &samsung_gpio_cfgs[2];
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
-                if ((base != NULL) && (chip->base == NULL))
-                        chip->base = base + ((i) * 0x20);
-
-                chip->bitmap_gpio_int = 0;
-
-                samsung_gpiolib_add(chip);
-        }
-}
-
-static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
-                                                   int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = samsung_gpiolib_4bit2_input;
-                chip->chip.direction_output = samsung_gpiolib_4bit2_output;
-
-                if (!chip->config)
-                        chip->config = &samsung_gpio_cfgs[2];
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
-
-                samsung_gpiolib_add(chip);
-        }
-}
-
-static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
-                                             int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
-                chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
-
-                if (!chip->pm)
-                        chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
-
-                samsung_gpiolib_add(chip);
-        }
-}
-
-int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-        struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
-
-        return samsung_chip->irq_base + offset;
-}
-
-#ifdef CONFIG_PLAT_S3C24XX
-static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset < 4)
-                return IRQ_EINT0 + offset;
-
-        if (offset < 8)
-                return IRQ_EINT4 + offset - 4;
-
-        return -EINVAL;
-}
-#endif
-
-#ifdef CONFIG_PLAT_S3C64XX
-static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
-{
-        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
-}
-
-static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
-{
-        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
-}
-#endif
-
-struct samsung_gpio_chip s3c24xx_gpios[] = {
-#ifdef CONFIG_PLAT_S3C24XX
-        {
-                .config = &s3c24xx_gpiocfg_banka,
-                .chip   = {
-                        .base                   = S3C2410_GPA(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOA",
-                        .ngpio                  = 24,
-                        .direction_input        = s3c24xx_gpiolib_banka_input,
-                        .direction_output       = s3c24xx_gpiolib_banka_output,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPB(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOB",
-                        .ngpio  = 16,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPC(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOC",
-                        .ngpio  = 16,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPD(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOD",
-                        .ngpio  = 16,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPE(0),
-                        .label  = "GPIOE",
-                        .owner  = THIS_MODULE,
-                        .ngpio  = 16,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPF(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOF",
-                        .ngpio  = 8,
-                        .to_irq = s3c24xx_gpiolib_fbank_to_irq,
-                },
-        }, {
-                .irq_base = IRQ_EINT8,
-                .chip   = {
-                        .base   = S3C2410_GPG(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOG",
-                        .ngpio  = 16,
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C2410_GPH(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOH",
-                        .ngpio  = 11,
-                },
-        },
-                /* GPIOS for the S3C2443 and later devices. */
-        {
-                .base   = S3C2440_GPJCON,
-                .chip   = {
-                        .base   = S3C2410_GPJ(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOJ",
-                        .ngpio  = 16,
-                },
-        }, {
-                .base   = S3C2443_GPKCON,
-                .chip   = {
-                        .base   = S3C2410_GPK(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOK",
-                        .ngpio  = 16,
-                },
-        }, {
-                .base   = S3C2443_GPLCON,
-                .chip   = {
-                        .base   = S3C2410_GPL(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOL",
-                        .ngpio  = 15,
-                },
-        }, {
-                .base   = S3C2443_GPMCON,
-                .chip   = {
-                        .base   = S3C2410_GPM(0),
-                        .owner  = THIS_MODULE,
-                        .label  = "GPIOM",
-                        .ngpio  = 2,
-                },
-        },
-#endif
-};
-
-/*
- * GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    8       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    5       4Bit    Yes     3
- * E    5       4Bit    Yes     None
- * F    16      2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    16      4Bit[2] No      None
- * L    15      4Bit[2] No      None
- * M    6       4Bit    No      IRQ_EINT
- * N    16      2Bit    No      IRQ_EINT
- * O    16      2Bit    Yes     7
- * P    15      2Bit    Yes     8
- * Q    9       2Bit    Yes     9
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-
-static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
-#ifdef CONFIG_PLAT_S3C64XX
-        {
-                .chip   = {
-                        .base   = S3C64XX_GPA(0),
-                        .ngpio  = S3C64XX_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C64XX_GPB(0),
-                        .ngpio  = S3C64XX_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C64XX_GPC(0),
-                        .ngpio  = S3C64XX_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S3C64XX_GPD(0),
-                        .ngpio  = S3C64XX_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[0],
-                .chip   = {
-                        .base   = S3C64XX_GPE(0),
-                        .ngpio  = S3C64XX_GPIO_E_NR,
-                        .label  = "GPE",
-                },
-        }, {
-                .base   = S3C64XX_GPG_BASE,
-                .chip   = {
-                        .base   = S3C64XX_GPG(0),
-                        .ngpio  = S3C64XX_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S3C64XX_GPM_BASE,
-                .config = &samsung_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S3C64XX_GPM(0),
-                        .ngpio  = S3C64XX_GPIO_M_NR,
-                        .label  = "GPM",
-                        .to_irq = s3c64xx_gpiolib_mbank_to_irq,
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
-#ifdef CONFIG_PLAT_S3C64XX
-        {
-                .base   = S3C64XX_GPH_BASE + 0x4,
-                .chip   = {
-                        .base   = S3C64XX_GPH(0),
-                        .ngpio  = S3C64XX_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        }, {
-                .base   = S3C64XX_GPK_BASE + 0x4,
-                .config = &samsung_gpio_cfgs[0],
-                .chip   = {
-                        .base   = S3C64XX_GPK(0),
-                        .ngpio  = S3C64XX_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        }, {
-                .base   = S3C64XX_GPL_BASE + 0x4,
-                .config = &samsung_gpio_cfgs[1],
-                .chip   = {
-                        .base   = S3C64XX_GPL(0),
-                        .ngpio  = S3C64XX_GPIO_L_NR,
-                        .label  = "GPL",
-                        .to_irq = s3c64xx_gpiolib_lbank_to_irq,
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
-#ifdef CONFIG_PLAT_S3C64XX
-        {
-                .base   = S3C64XX_GPF_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S3C64XX_GPF(0),
-                        .ngpio  = S3C64XX_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[7],
-                .chip   = {
-                        .base   = S3C64XX_GPI(0),
-                        .ngpio  = S3C64XX_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[7],
-                .chip   = {
-                        .base   = S3C64XX_GPJ(0),
-                        .ngpio  = S3C64XX_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S3C64XX_GPO(0),
-                        .ngpio  = S3C64XX_GPIO_O_NR,
-                        .label  = "GPO",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S3C64XX_GPP(0),
-                        .ngpio  = S3C64XX_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S3C64XX_GPQ(0),
-                        .ngpio  = S3C64XX_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        }, {
-                .base   = S3C64XX_GPN_BASE,
-                .irq_base = IRQ_EINT(0),
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S3C64XX_GPN(0),
-                        .ngpio  = S3C64XX_GPIO_N_NR,
-                        .label  = "GPN",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-#endif
-};
-
-/*
- * S5P6440 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * F    2       2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    8       2Bit    Yes     8
- * R    15      4Bit[2] Yes     8
- */
-
-static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .chip   = {
-                        .base   = S5P6440_GPA(0),
-                        .ngpio  = S5P6440_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6440_GPB(0),
-                        .ngpio  = S5P6440_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6440_GPC(0),
-                        .ngpio  = S5P6440_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S5P64X0_GPG_BASE,
-                .chip   = {
-                        .base   = S5P6440_GPG(0),
-                        .ngpio  = S5P6440_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6440_GPH(0),
-                        .ngpio  = S5P6440_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfg_rbank,
-                .chip   = {
-                        .base   = S5P6440_GPR(0),
-                        .ngpio  = S5P6440_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
-#ifdef CONFIG_CPU_S5P6440
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6440_GPF(0),
-                        .ngpio  = S5P6440_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPI(0),
-                        .ngpio  = S5P6440_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6440_GPJ(0),
-                        .ngpio  = S5P6440_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6440_GPN(0),
-                        .ngpio  = S5P6440_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6440_GPP(0),
-                        .ngpio  = S5P6440_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        },
-#endif
-};
-
-/*
- * S5P6450 GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    6       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    8       4Bit    Yes     None
- * F    2       2Bit    Yes     None
- * G    14      4Bit[2] Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    5       4Bit    Yes     None
- * N    16      2Bit    No      IRQ_EINT
- * P    11      2Bit    Yes     8
- * Q    14      2Bit    Yes     None
- * R    15      4Bit[2] Yes     None
- * S    8       2Bit    Yes     None
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-
-static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .chip   = {
-                        .base   = S5P6450_GPA(0),
-                        .ngpio  = S5P6450_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPB(0),
-                        .ngpio  = S5P6450_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPC(0),
-                        .ngpio  = S5P6450_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5P6450_GPD(0),
-                        .ngpio  = S5P6450_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .base   = S5P6450_GPK_BASE,
-                .chip   = {
-                        .base   = S5P6450_GPK(0),
-                        .ngpio  = S5P6450_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPG_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6450_GPG(0),
-                        .ngpio  = S5P6450_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S5P64X0_GPH_BASE + 0x4,
-                .chip   = {
-                        .base   = S5P6450_GPH(0),
-                        .ngpio  = S5P6450_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPR_BASE + 0x4,
-                .config = &s5p64x0_gpio_cfg_rbank,
-                .chip   = {
-                        .base   = S5P6450_GPR(0),
-                        .ngpio  = S5P6450_GPIO_R_NR,
-                        .label  = "GPR",
-                },
-        },
-#endif
-};
-
-static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
-#ifdef CONFIG_CPU_S5P6450
-        {
-                .base   = S5P64X0_GPF_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPF(0),
-                        .ngpio  = S5P6450_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S5P64X0_GPI_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPI(0),
-                        .ngpio  = S5P6450_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S5P64X0_GPJ_BASE,
-                .config = &samsung_gpio_cfgs[4],
-                .chip   = {
-                        .base   = S5P6450_GPJ(0),
-                        .ngpio  = S5P6450_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S5P64X0_GPN_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPN(0),
-                        .ngpio  = S5P6450_GPIO_N_NR,
-                        .label  = "GPN",
-                },
-        }, {
-                .base   = S5P64X0_GPP_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPP(0),
-                        .ngpio  = S5P6450_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .base   = S5P6450_GPQ_BASE,
-                .config = &samsung_gpio_cfgs[5],
-                .chip   = {
-                        .base   = S5P6450_GPQ(0),
-                        .ngpio  = S5P6450_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        }, {
-                .base   = S5P6450_GPS_BASE,
-                .config = &samsung_gpio_cfgs[6],
-                .chip   = {
-                        .base   = S5P6450_GPS(0),
-                        .ngpio  = S5P6450_GPIO_S_NR,
-                        .label  = "GPS",
-                },
-        },
-#endif
-};
-
-/*
- * S5PC100 GPIO bank summary:
- *
- * Bank GPIOs   Style   INT Type
- * A0   8       4Bit    GPIO_INT0
- * A1   5       4Bit    GPIO_INT1
- * B    8       4Bit    GPIO_INT2
- * C    5       4Bit    GPIO_INT3
- * D    7       4Bit    GPIO_INT4
- * E0   8       4Bit    GPIO_INT5
- * E1   6       4Bit    GPIO_INT6
- * F0   8       4Bit    GPIO_INT7
- * F1   8       4Bit    GPIO_INT8
- * F2   8       4Bit    GPIO_INT9
- * F3   4       4Bit    GPIO_INT10
- * G0   8       4Bit    GPIO_INT11
- * G1   3       4Bit    GPIO_INT12
- * G2   7       4Bit    GPIO_INT13
- * G3   7       4Bit    GPIO_INT14
- * H0   8       4Bit    WKUP_INT
- * H1   8       4Bit    WKUP_INT
- * H2   8       4Bit    WKUP_INT
- * H3   8       4Bit    WKUP_INT
- * I    8       4Bit    GPIO_INT15
- * J0   8       4Bit    GPIO_INT16
- * J1   5       4Bit    GPIO_INT17
- * J2   8       4Bit    GPIO_INT18
- * J3   8       4Bit    GPIO_INT19
- * J4   4       4Bit    GPIO_INT20
- * K0   8       4Bit    None
- * K1   6       4Bit    None
- * K2   8       4Bit    None
- * K3   8       4Bit    None
- * L0   8       4Bit    None
- * L1   8       4Bit    None
- * L2   8       4Bit    None
- * L3   8       4Bit    None
- */
-
-static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5PC100
-        {
-                .chip   = {
-                        .base   = S5PC100_GPA0(0),
-                        .ngpio  = S5PC100_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPA1(0),
-                        .ngpio  = S5PC100_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPB(0),
-                        .ngpio  = S5PC100_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPC(0),
-                        .ngpio  = S5PC100_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPD(0),
-                        .ngpio  = S5PC100_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE0(0),
-                        .ngpio  = S5PC100_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE1(0),
-                        .ngpio  = S5PC100_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF0(0),
-                        .ngpio  = S5PC100_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF1(0),
-                        .ngpio  = S5PC100_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF2(0),
-                        .ngpio  = S5PC100_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF3(0),
-                        .ngpio  = S5PC100_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG0(0),
-                        .ngpio  = S5PC100_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG1(0),
-                        .ngpio  = S5PC100_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG2(0),
-                        .ngpio  = S5PC100_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG3(0),
-                        .ngpio  = S5PC100_GPIO_G3_NR,
-                        .label  = "GPG3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPI(0),
-                        .ngpio  = S5PC100_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ0(0),
-                        .ngpio  = S5PC100_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ1(0),
-                        .ngpio  = S5PC100_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ2(0),
-                        .ngpio  = S5PC100_GPIO_J2_NR,
-                        .label  = "GPJ2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ3(0),
-                        .ngpio  = S5PC100_GPIO_J3_NR,
-                        .label  = "GPJ3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ4(0),
-                        .ngpio  = S5PC100_GPIO_J4_NR,
-                        .label  = "GPJ4",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK0(0),
-                        .ngpio  = S5PC100_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK1(0),
-                        .ngpio  = S5PC100_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK2(0),
-                        .ngpio  = S5PC100_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPK3(0),
-                        .ngpio  = S5PC100_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL0(0),
-                        .ngpio  = S5PC100_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL1(0),
-                        .ngpio  = S5PC100_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL2(0),
-                        .ngpio  = S5PC100_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL3(0),
-                        .ngpio  = S5PC100_GPIO_L3_NR,
-                        .label  = "GPL3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPL4(0),
-                        .ngpio  = S5PC100_GPIO_L4_NR,
-                        .label  = "GPL4",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC00),
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PC100_GPH0(0),
-                        .ngpio  = S5PC100_GPIO_H0_NR,
-                        .label  = "GPH0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC20),
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PC100_GPH1(0),
-                        .ngpio  = S5PC100_GPIO_H1_NR,
-                        .label  = "GPH1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC40),
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PC100_GPH2(0),
-                        .ngpio  = S5PC100_GPIO_H2_NR,
-                        .label  = "GPH2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC60),
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PC100_GPH3(0),
-                        .ngpio  = S5PC100_GPIO_H3_NR,
-                        .label  = "GPH3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-#endif
-};
-
-/*
- * Followings are the gpio banks in S5PV210/S5PC110
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure samsung_gpio_cfgs[3] in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of samsung_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-
-static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5PV210
-        {
-                .chip   = {
-                        .base   = S5PV210_GPA0(0),
-                        .ngpio  = S5PV210_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPA1(0),
-                        .ngpio  = S5PV210_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPB(0),
-                        .ngpio  = S5PV210_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPC0(0),
-                        .ngpio  = S5PV210_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPC1(0),
-                        .ngpio  = S5PV210_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPD0(0),
-                        .ngpio  = S5PV210_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPD1(0),
-                        .ngpio  = S5PV210_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPE0(0),
-                        .ngpio  = S5PV210_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPE1(0),
-                        .ngpio  = S5PV210_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF0(0),
-                        .ngpio  = S5PV210_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF1(0),
-                        .ngpio  = S5PV210_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF2(0),
-                        .ngpio  = S5PV210_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF3(0),
-                        .ngpio  = S5PV210_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG0(0),
-                        .ngpio  = S5PV210_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG1(0),
-                        .ngpio  = S5PV210_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG2(0),
-                        .ngpio  = S5PV210_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG3(0),
-                        .ngpio  = S5PV210_GPIO_G3_NR,
-                        .label  = "GPG3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPI(0),
-                        .ngpio  = S5PV210_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ0(0),
-                        .ngpio  = S5PV210_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ1(0),
-                        .ngpio  = S5PV210_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ2(0),
-                        .ngpio  = S5PV210_GPIO_J2_NR,
-                        .label  = "GPJ2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ3(0),
-                        .ngpio  = S5PV210_GPIO_J3_NR,
-                        .label  = "GPJ3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ4(0),
-                        .ngpio  = S5PV210_GPIO_J4_NR,
-                        .label  = "GPJ4",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_MP01(0),
-                        .ngpio  = S5PV210_GPIO_MP01_NR,
-                        .label  = "MP01",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_MP02(0),
-                        .ngpio  = S5PV210_GPIO_MP02_NR,
-                        .label  = "MP02",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_MP03(0),
-                        .ngpio  = S5PV210_GPIO_MP03_NR,
-                        .label  = "MP03",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_MP04(0),
-                        .ngpio  = S5PV210_GPIO_MP04_NR,
-                        .label  = "MP04",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_MP05(0),
-                        .ngpio  = S5PV210_GPIO_MP05_NR,
-                        .label  = "MP05",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC00),
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PV210_GPH0(0),
-                        .ngpio  = S5PV210_GPIO_H0_NR,
-                        .label  = "GPH0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC20),
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PV210_GPH1(0),
-                        .ngpio  = S5PV210_GPIO_H1_NR,
-                        .label  = "GPH1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC40),
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PV210_GPH2(0),
-                        .ngpio  = S5PV210_GPIO_H2_NR,
-                        .label  = "GPH2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC60),
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PV210_GPH3(0),
-                        .ngpio  = S5PV210_GPIO_H3_NR,
-                        .label  = "GPH3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-#endif
-};
-
-/*
- * Followings are the gpio banks in EXYNOS SoCs
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure exynos_gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of samsung_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_1[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPA0(0),
-                        .ngpio  = EXYNOS4_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPA1(0),
-                        .ngpio  = EXYNOS4_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPB(0),
-                        .ngpio  = EXYNOS4_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPC0(0),
-                        .ngpio  = EXYNOS4_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPC1(0),
-                        .ngpio  = EXYNOS4_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPD0(0),
-                        .ngpio  = EXYNOS4_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPD1(0),
-                        .ngpio  = EXYNOS4_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE0(0),
-                        .ngpio  = EXYNOS4_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE1(0),
-                        .ngpio  = EXYNOS4_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE2(0),
-                        .ngpio  = EXYNOS4_GPIO_E2_NR,
-                        .label  = "GPE2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE3(0),
-                        .ngpio  = EXYNOS4_GPIO_E3_NR,
-                        .label  = "GPE3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE4(0),
-                        .ngpio  = EXYNOS4_GPIO_E4_NR,
-                        .label  = "GPE4",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF0(0),
-                        .ngpio  = EXYNOS4_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF1(0),
-                        .ngpio  = EXYNOS4_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF2(0),
-                        .ngpio  = EXYNOS4_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF3(0),
-                        .ngpio  = EXYNOS4_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_2[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPJ0(0),
-                        .ngpio  = EXYNOS4_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPJ1(0),
-                        .ngpio  = EXYNOS4_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK0(0),
-                        .ngpio  = EXYNOS4_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK1(0),
-                        .ngpio  = EXYNOS4_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK2(0),
-                        .ngpio  = EXYNOS4_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK3(0),
-                        .ngpio  = EXYNOS4_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL0(0),
-                        .ngpio  = EXYNOS4_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL1(0),
-                        .ngpio  = EXYNOS4_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL2(0),
-                        .ngpio  = EXYNOS4_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY0(0),
-                        .ngpio  = EXYNOS4_GPIO_Y0_NR,
-                        .label  = "GPY0",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY1(0),
-                        .ngpio  = EXYNOS4_GPIO_Y1_NR,
-                        .label  = "GPY1",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY2(0),
-                        .ngpio  = EXYNOS4_GPIO_Y2_NR,
-                        .label  = "GPY2",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY3(0),
-                        .ngpio  = EXYNOS4_GPIO_Y3_NR,
-                        .label  = "GPY3",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY4(0),
-                        .ngpio  = EXYNOS4_GPIO_Y4_NR,
-                        .label  = "GPY4",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY5(0),
-                        .ngpio  = EXYNOS4_GPIO_Y5_NR,
-                        .label  = "GPY5",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[8],
-                .chip   = {
-                        .base   = EXYNOS4_GPY6(0),
-                        .ngpio  = EXYNOS4_GPIO_Y6_NR,
-                        .label  = "GPY6",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = EXYNOS4_GPX0(0),
-                        .ngpio  = EXYNOS4_GPIO_X0_NR,
-                        .label  = "GPX0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = EXYNOS4_GPX1(0),
-                        .ngpio  = EXYNOS4_GPIO_X1_NR,
-                        .label  = "GPX1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = EXYNOS4_GPX2(0),
-                        .ngpio  = EXYNOS4_GPIO_X2_NR,
-                        .label  = "GPX2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = EXYNOS4_GPX3(0),
-                        .ngpio  = EXYNOS4_GPIO_X3_NR,
-                        .label  = "GPX3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_3[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPZ(0),
-                        .ngpio  = EXYNOS4_GPIO_Z_NR,
-                        .label  = "GPZ",
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-static struct samsung_gpio_chip exynos5_gpios_1[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS5_GPA0(0),
-                        .ngpio  = EXYNOS5_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPA1(0),
-                        .ngpio  = EXYNOS5_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPA2(0),
-                        .ngpio  = EXYNOS5_GPIO_A2_NR,
-                        .label  = "GPA2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPB0(0),
-                        .ngpio  = EXYNOS5_GPIO_B0_NR,
-                        .label  = "GPB0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPB1(0),
-                        .ngpio  = EXYNOS5_GPIO_B1_NR,
-                        .label  = "GPB1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPB2(0),
-                        .ngpio  = EXYNOS5_GPIO_B2_NR,
-                        .label  = "GPB2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPB3(0),
-                        .ngpio  = EXYNOS5_GPIO_B3_NR,
-                        .label  = "GPB3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPC0(0),
-                        .ngpio  = EXYNOS5_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPC1(0),
-                        .ngpio  = EXYNOS5_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPC2(0),
-                        .ngpio  = EXYNOS5_GPIO_C2_NR,
-                        .label  = "GPC2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPC3(0),
-                        .ngpio  = EXYNOS5_GPIO_C3_NR,
-                        .label  = "GPC3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPD0(0),
-                        .ngpio  = EXYNOS5_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPD1(0),
-                        .ngpio  = EXYNOS5_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY0(0),
-                        .ngpio  = EXYNOS5_GPIO_Y0_NR,
-                        .label  = "GPY0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY1(0),
-                        .ngpio  = EXYNOS5_GPIO_Y1_NR,
-                        .label  = "GPY1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY2(0),
-                        .ngpio  = EXYNOS5_GPIO_Y2_NR,
-                        .label  = "GPY2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY3(0),
-                        .ngpio  = EXYNOS5_GPIO_Y3_NR,
-                        .label  = "GPY3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY4(0),
-                        .ngpio  = EXYNOS5_GPIO_Y4_NR,
-                        .label  = "GPY4",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY5(0),
-                        .ngpio  = EXYNOS5_GPIO_Y5_NR,
-                        .label  = "GPY5",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPY6(0),
-                        .ngpio  = EXYNOS5_GPIO_Y6_NR,
-                        .label  = "GPY6",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPC4(0),
-                        .ngpio  = EXYNOS5_GPIO_C4_NR,
-                        .label  = "GPC4",
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = EXYNOS5_GPX0(0),
-                        .ngpio  = EXYNOS5_GPIO_X0_NR,
-                        .label  = "GPX0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = EXYNOS5_GPX1(0),
-                        .ngpio  = EXYNOS5_GPIO_X1_NR,
-                        .label  = "GPX1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = EXYNOS5_GPX2(0),
-                        .ngpio  = EXYNOS5_GPIO_X2_NR,
-                        .label  = "GPX2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .config = &samsung_gpio_cfgs[9],
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = EXYNOS5_GPX3(0),
-                        .ngpio  = EXYNOS5_GPIO_X3_NR,
-                        .label  = "GPX3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-static struct samsung_gpio_chip exynos5_gpios_2[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS5_GPE0(0),
-                        .ngpio  = EXYNOS5_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPE1(0),
-                        .ngpio  = EXYNOS5_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPF0(0),
-                        .ngpio  = EXYNOS5_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPF1(0),
-                        .ngpio  = EXYNOS5_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPG0(0),
-                        .ngpio  = EXYNOS5_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPG1(0),
-                        .ngpio  = EXYNOS5_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPG2(0),
-                        .ngpio  = EXYNOS5_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPH0(0),
-                        .ngpio  = EXYNOS5_GPIO_H0_NR,
-                        .label  = "GPH0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPH1(0),
-                        .ngpio  = EXYNOS5_GPIO_H1_NR,
-                        .label  = "GPH1",
-
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-static struct samsung_gpio_chip exynos5_gpios_3[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS5_GPV0(0),
-                        .ngpio  = EXYNOS5_GPIO_V0_NR,
-                        .label  = "GPV0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPV1(0),
-                        .ngpio  = EXYNOS5_GPIO_V1_NR,
-                        .label  = "GPV1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPV2(0),
-                        .ngpio  = EXYNOS5_GPIO_V2_NR,
-                        .label  = "GPV2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPV3(0),
-                        .ngpio  = EXYNOS5_GPIO_V3_NR,
-                        .label  = "GPV3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS5_GPV4(0),
-                        .ngpio  = EXYNOS5_GPIO_V4_NR,
-                        .label  = "GPV4",
-                },
-        },
-};
-#endif
-
-#ifdef CONFIG_ARCH_EXYNOS5
-static struct samsung_gpio_chip exynos5_gpios_4[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS5_GPZ(0),
-                        .ngpio  = EXYNOS5_GPIO_Z_NR,
-                        .label  = "GPZ",
-                },
-        },
-};
-#endif
-
-
-#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
-static int exynos_gpio_xlate(struct gpio_chip *gc,
-                        const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        unsigned int pin;
-
-        if (WARN_ON(gc->of_gpio_n_cells < 4))
-                return -EINVAL;
-
-        if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
-                return -EINVAL;
-
-        if (gpiospec->args[0] > gc->ngpio)
-                return -EINVAL;
-
-        pin = gc->base + gpiospec->args[0];
-
-        if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
-                pr_warn("gpio_xlate: failed to set pin function\n");
-        if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
-                pr_warn("gpio_xlate: failed to set pin pull up/down\n");
-        if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
-                pr_warn("gpio_xlate: failed to set pin drive strength\n");
-
-        if (flags)
-                *flags = gpiospec->args[2] >> 16;
-
-        return gpiospec->args[0];
-}
-
-static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
-        { .compatible = "samsung,exynos4-gpio", },
-        {}
-};
-
-static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
-                                                u64 base, u64 offset)
-{
-        struct gpio_chip *gc =  &chip->chip;
-        u64 address;
-
-        if (!of_have_populated_dt())
-                return;
-
-        address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
-        gc->of_node = of_find_matching_node_by_address(NULL,
-                        exynos_gpio_dt_match, address);
-        if (!gc->of_node) {
-                pr_info("gpio: device tree node not found for gpio controller"
-                        " with base address %08llx\n", address);
-                return;
-        }
-        gc->of_gpio_n_cells = 4;
-        gc->of_xlate = exynos_gpio_xlate;
-}
-#elif defined(CONFIG_ARCH_EXYNOS)
-static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
-                                                u64 base, u64 offset)
-{
-        return;
-}
-#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
-
-static __init void exynos4_gpiolib_init(void)
-{
-#ifdef CONFIG_CPU_EXYNOS4210
-        struct samsung_gpio_chip *chip;
-        int i, nr_chips;
-        void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
-        int group = 0;
-        void __iomem *gpx_base;
-
-        /* gpio part1 */
-        gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
-        if (gpio_base1 == NULL) {
-                pr_err("unable to ioremap for gpio_base1\n");
-                goto err_ioremap1;
-        }
-
-        chip = exynos4_gpios_1;
-        nr_chips = ARRAY_SIZE(exynos4_gpios_1);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS4_PA_GPIO1, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
-                                       nr_chips, gpio_base1);
-
-        /* gpio part2 */
-        gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-        if (gpio_base2 == NULL) {
-                pr_err("unable to ioremap for gpio_base2\n");
-                goto err_ioremap2;
-        }
-
-        /* need to set base address for gpx */
-        chip = &exynos4_gpios_2[16];
-        gpx_base = gpio_base2 + 0xC00;
-        for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
-                chip->base = gpx_base;
-
-        chip = exynos4_gpios_2;
-        nr_chips = ARRAY_SIZE(exynos4_gpios_2);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS4_PA_GPIO2, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
-                                       nr_chips, gpio_base2);
-
-        /* gpio part3 */
-        gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
-        if (gpio_base3 == NULL) {
-                pr_err("unable to ioremap for gpio_base3\n");
-                goto err_ioremap3;
-        }
-
-        chip = exynos4_gpios_3;
-        nr_chips = ARRAY_SIZE(exynos4_gpios_3);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS4_PA_GPIO3, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
-                                       nr_chips, gpio_base3);
-
-#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
-        s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
-        s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
-#endif
-
-        return;
-
-err_ioremap3:
-        iounmap(gpio_base2);
-err_ioremap2:
-        iounmap(gpio_base1);
-err_ioremap1:
-        return;
-#endif  /* CONFIG_CPU_EXYNOS4210 */
-}
-
-static __init void exynos5_gpiolib_init(void)
-{
-#ifdef CONFIG_SOC_EXYNOS5250
-        struct samsung_gpio_chip *chip;
-        int i, nr_chips;
-        void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
-        int group = 0;
-        void __iomem *gpx_base;
-
-        /* gpio part1 */
-        gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-        if (gpio_base1 == NULL) {
-                pr_err("unable to ioremap for gpio_base1\n");
-                goto err_ioremap1;
-        }
-
-        /* need to set base address for gpc4 */
-        exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
-
-        /* need to set base address for gpx */
-        chip = &exynos5_gpios_1[21];
-        gpx_base = gpio_base1 + 0xC00;
-        for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
-                chip->base = gpx_base;
-
-        chip = exynos5_gpios_1;
-        nr_chips = ARRAY_SIZE(exynos5_gpios_1);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS5_PA_GPIO1, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
-                                       nr_chips, gpio_base1);
-
-        /* gpio part2 */
-        gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
-        if (gpio_base2 == NULL) {
-                pr_err("unable to ioremap for gpio_base2\n");
-                goto err_ioremap2;
-        }
-
-        chip = exynos5_gpios_2;
-        nr_chips = ARRAY_SIZE(exynos5_gpios_2);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS5_PA_GPIO2, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
-                                       nr_chips, gpio_base2);
-
-        /* gpio part3 */
-        gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
-        if (gpio_base3 == NULL) {
-                pr_err("unable to ioremap for gpio_base3\n");
-                goto err_ioremap3;
-        }
-
-        /* need to set base address for gpv */
-        exynos5_gpios_3[0].base = gpio_base3;
-        exynos5_gpios_3[1].base = gpio_base3 + 0x20;
-        exynos5_gpios_3[2].base = gpio_base3 + 0x60;
-        exynos5_gpios_3[3].base = gpio_base3 + 0x80;
-        exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
-
-        chip = exynos5_gpios_3;
-        nr_chips = ARRAY_SIZE(exynos5_gpios_3);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS5_PA_GPIO3, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
-                                       nr_chips, gpio_base3);
-
-        /* gpio part4 */
-        gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
-        if (gpio_base4 == NULL) {
-                pr_err("unable to ioremap for gpio_base4\n");
-                goto err_ioremap4;
-        }
-
-        chip = exynos5_gpios_4;
-        nr_chips = ARRAY_SIZE(exynos5_gpios_4);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (!chip->config) {
-                        chip->config = &exynos_gpio_cfg;
-                        chip->group = group++;
-                }
-                exynos_gpiolib_attach_ofnode(chip,
-                                EXYNOS5_PA_GPIO4, i * 0x20);
-        }
-        samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
-                                       nr_chips, gpio_base4);
-        return;
-
-err_ioremap4:
-        iounmap(gpio_base3);
-err_ioremap3:
-        iounmap(gpio_base2);
-err_ioremap2:
-        iounmap(gpio_base1);
-err_ioremap1:
-        return;
-
-#endif  /* CONFIG_SOC_EXYNOS5250 */
-}
-
-/* TODO: cleanup soc_is_* */
-static __init int samsung_gpiolib_init(void)
-{
-        struct samsung_gpio_chip *chip;
-        int i, nr_chips;
-        int group = 0;
-
-#ifdef CONFIG_PINCTRL_SAMSUNG
-        /*
-        * This gpio driver includes support for device tree support and there
-        * are platforms using it. In order to maintain compatibility with those
-        * platforms, and to allow non-dt Exynos4210 platforms to use this
-        * gpiolib support, a check is added to find out if there is a active
-        * pin-controller driver support available. If it is available, this
-        * gpiolib support is ignored and the gpiolib support available in
-        * pin-controller driver is used. This is a temporary check and will go
-        * away when all of the Exynos4210 platforms have switched to using
-        * device tree and the pin-ctrl driver.
-        */
-        struct device_node *pctrl_np;
-        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,pinctrl-exynos4210", },
-                { .compatible = "samsung,pinctrl-exynos4x12", },
-        };
-        for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
-                if (pctrl_np && of_device_is_available(pctrl_np))
-                        return -ENODEV;
-#endif
-
-        samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
-
-        if (soc_is_s3c24xx()) {
-                s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
-                                ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
-        } else if (soc_is_s3c64xx()) {
-                samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
-                                ARRAY_SIZE(s3c64xx_gpios_2bit),
-                                S3C64XX_VA_GPIO + 0xE0, 0x20);
-                samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
-                                ARRAY_SIZE(s3c64xx_gpios_4bit),
-                                S3C64XX_VA_GPIO);
-                samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
-                                ARRAY_SIZE(s3c64xx_gpios_4bit2));
-        } else if (soc_is_s5p6440()) {
-                samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
-                                ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
-                samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
-                                ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
-                samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
-                                ARRAY_SIZE(s5p6440_gpios_4bit2));
-                s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
-                                ARRAY_SIZE(s5p6440_gpios_rbank));
-        } else if (soc_is_s5p6450()) {
-                samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
-                                ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
-                samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
-                                ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
-                samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
-                                ARRAY_SIZE(s5p6450_gpios_4bit2));
-                s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
-                                ARRAY_SIZE(s5p6450_gpios_rbank));
-        } else if (soc_is_s5pc100()) {
-                group = 0;
-                chip = s5pc100_gpios_4bit;
-                nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
-
-                for (i = 0; i < nr_chips; i++, chip++) {
-                        if (!chip->config) {
-                                chip->config = &samsung_gpio_cfgs[3];
-                                chip->group = group++;
-                        }
-                }
-                samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
-#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
-                s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
-#endif
-        } else if (soc_is_s5pv210()) {
-                group = 0;
-                chip = s5pv210_gpios_4bit;
-                nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
-
-                for (i = 0; i < nr_chips; i++, chip++) {
-                        if (!chip->config) {
-                                chip->config = &samsung_gpio_cfgs[3];
-                                chip->group = group++;
-                        }
-                }
-                samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
-#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
-                s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
-#endif
-        } else if (soc_is_exynos4210()) {
-                exynos4_gpiolib_init();
-        } else if (soc_is_exynos5250()) {
-                exynos5_gpiolib_init();
-        } else {
-                WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
-                return -ENODEV;
-        }
-
-        return 0;
-}
-core_initcall(samsung_gpiolib_init);
-
-int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset;
-        int ret;
-
-        if (!chip)
-                return -EINVAL;
-
-        offset = pin - chip->chip.base;
-
-        samsung_gpio_lock(chip, flags);
-        ret = samsung_gpio_do_setcfg(chip, offset, config);
-        samsung_gpio_unlock(chip, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_cfgpin);
-
-int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
-                          unsigned int cfg)
-{
-        int ret;
-
-        for (; nr > 0; nr--, start++) {
-                ret = s3c_gpio_cfgpin(start, cfg);
-                if (ret != 0)
-                        return ret;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
-
-int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
-                          unsigned int cfg, samsung_gpio_pull_t pull)
-{
-        int ret;
-
-        for (; nr > 0; nr--, start++) {
-                s3c_gpio_setpull(start, pull);
-                ret = s3c_gpio_cfgpin(start, cfg);
-                if (ret != 0)
-                        return ret;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
-
-unsigned s3c_gpio_getcfg(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long flags;
-        unsigned ret = 0;
-        int offset;
-
-        if (chip) {
-                offset = pin - chip->chip.base;
-
-                samsung_gpio_lock(chip, flags);
-                ret = samsung_gpio_do_getcfg(chip, offset);
-                samsung_gpio_unlock(chip, flags);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_getcfg);
-
-int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset, ret;
-
-        if (!chip)
-                return -EINVAL;
-
-        offset = pin - chip->chip.base;
-
-        samsung_gpio_lock(chip, flags);
-        ret = samsung_gpio_do_setpull(chip, offset, pull);
-        samsung_gpio_unlock(chip, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_setpull);
-
-samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset;
-        u32 pup = 0;
-
-        if (chip) {
-                offset = pin - chip->chip.base;
-
-                samsung_gpio_lock(chip, flags);
-                pup = samsung_gpio_do_getpull(chip, offset);
-                samsung_gpio_unlock(chip, flags);
-        }
-
-        return (__force samsung_gpio_pull_t)pup;
-}
-EXPORT_SYMBOL(s3c_gpio_getpull);
-
-#ifdef CONFIG_S5P_GPIO_DRVSTR
-s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned int off;
-        void __iomem *reg;
-        int shift;
-        u32 drvstr;
-
-        if (!chip)
-                return -EINVAL;
-
-        off = pin - chip->chip.base;
-        shift = off * 2;
-        reg = chip->base + 0x0C;
-
-        drvstr = __raw_readl(reg);
-        drvstr = drvstr >> shift;
-        drvstr &= 0x3;
-
-        return (__force s5p_gpio_drvstr_t)drvstr;
-}
-EXPORT_SYMBOL(s5p_gpio_get_drvstr);
-
-int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
-{
-        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-        unsigned int off;
-        void __iomem *reg;
-        int shift;
-        u32 tmp;
-
-        if (!chip)
-                return -EINVAL;
-
-        off = pin - chip->chip.base;
-        shift = off * 2;
-        reg = chip->base + 0x0C;
-
-        tmp = __raw_readl(reg);
-        tmp &= ~(0x3 << shift);
-        tmp |= drvstr << shift;
-
-        __raw_writel(tmp, reg);
-
-        return 0;
-}
-EXPORT_SYMBOL(s5p_gpio_set_drvstr);
-#endif  /* CONFIG_S5P_GPIO_DRVSTR */
-
-#ifdef CONFIG_PLAT_S3C24XX
-unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
-{
-        unsigned long flags;
-        unsigned long misccr;
-
-        local_irq_save(flags);
-        misccr = __raw_readl(S3C24XX_MISCCR);
-        misccr &= ~clear;
-        misccr ^= change;
-        __raw_writel(misccr, S3C24XX_MISCCR);
-        local_irq_restore(flags);
-
-        return misccr;
-}
-EXPORT_SYMBOL(s3c2410_modify_misccr);
-#endif
diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
index edae963f462..16351584549 100644
--- a/drivers/gpio/gpio-sch.c
+++ b/drivers/gpio/gpio-sch.c
@@ -185,7 +185,7 @@ static struct gpio_chip sch_gpio_resume = {
         .set                    = sch_gpio_resume_set,
 };
 
-static int sch_gpio_probe(struct platform_device *pdev)
+static int __devinit sch_gpio_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int err, id;
@@ -232,17 +232,8 @@ static int sch_gpio_probe(struct platform_device *pdev)
                         sch_gpio_resume.ngpio = 9;
                         break;
 
-                case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
-                        sch_gpio_core.base = 0;
-                        sch_gpio_core.ngpio = 21;
-
-                        sch_gpio_resume.base = 21;
-                        sch_gpio_resume.ngpio = 9;
-                        break;
-
                 default:
-                        err = -ENODEV;
-                        goto err_sch_gpio_core;
+                        return -ENODEV;
         }
 
         sch_gpio_core.dev = &pdev->dev;
@@ -271,7 +262,7 @@ err_sch_gpio_core:
         return err;
 }
 
-static int sch_gpio_remove(struct platform_device *pdev)
+static int __devexit sch_gpio_remove(struct platform_device *pdev)
 {
         struct resource *res;
         if (gpio_ba) {
@@ -303,10 +294,21 @@ static struct platform_driver sch_gpio_driver = {
                 .owner = THIS_MODULE,
         },
         .probe          = sch_gpio_probe,
-        .remove         = sch_gpio_remove,
+        .remove         = __devexit_p(sch_gpio_remove),
 };
 
-module_platform_driver(sch_gpio_driver);
+static int __init sch_gpio_init(void)
+{
+        return platform_driver_register(&sch_gpio_driver);
+}
+
+static void __exit sch_gpio_exit(void)
+{
+        platform_driver_unregister(&sch_gpio_driver);
+}
+
+module_init(sch_gpio_init);
+module_exit(sch_gpio_exit);
 
 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
deleted file mode 100644
index 88f374ac775..00000000000
--- a/drivers/gpio/gpio-sodaville.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- *  GPIO interface for Intel Sodaville SoCs.
- *
- *  Copyright (c) 2010, 2011 Intel Corporation
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License 2 as published
- *  by the Free Software Foundation.
- *
- */
-
-#include <linux/errno.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/platform_device.h>
-#include <linux/of_irq.h>
-#include <linux/basic_mmio_gpio.h>
-
-#define DRV_NAME                "sdv_gpio"
-#define SDV_NUM_PUB_GPIOS       12
-#define PCI_DEVICE_ID_SDV_GPIO  0x2e67
-#define GPIO_BAR                0
-
-#define GPOUTR          0x00
-#define GPOER           0x04
-#define GPINR           0x08
-
-#define GPSTR           0x0c
-#define GPIT1R0         0x10
-#define GPIO_INT        0x14
-#define GPIT1R1         0x18
-
-#define GPMUXCTL        0x1c
-
-struct sdv_gpio_chip_data {
-        int irq_base;
-        void __iomem *gpio_pub_base;
-        struct irq_domain *id;
-        struct irq_chip_generic *gc;
-        struct bgpio_chip bgpio;
-};
-
-static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct sdv_gpio_chip_data *sd = gc->private;
-        void __iomem *type_reg;
-        u32 reg;
-
-        if (d->hwirq < 8)
-                type_reg = sd->gpio_pub_base + GPIT1R0;
-        else
-                type_reg = sd->gpio_pub_base + GPIT1R1;
-
-        reg = readl(type_reg);
-
-        switch (type) {
-        case IRQ_TYPE_LEVEL_HIGH:
-                reg &= ~BIT(4 * (d->hwirq % 8));
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                reg |= BIT(4 * (d->hwirq % 8));
-                break;
-
-        default:
-                return -EINVAL;
-        }
-
-        writel(reg, type_reg);
-        return 0;
-}
-
-static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
-{
-        struct sdv_gpio_chip_data *sd = data;
-        u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
-
-        irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
-        if (!irq_stat)
-                return IRQ_NONE;
-
-        while (irq_stat) {
-                u32 irq_bit = __fls(irq_stat);
-
-                irq_stat &= ~BIT(irq_bit);
-                generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
-        }
-
-        return IRQ_HANDLED;
-}
-
-static int sdv_xlate(struct irq_domain *h, struct device_node *node,
-                const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
-                u32 *out_type)
-{
-        u32 line, type;
-
-        if (node != h->of_node)
-                return -EINVAL;
-
-        if (intsize < 2)
-                return -EINVAL;
-
-        line = *intspec;
-        *out_hwirq = line;
-
-        intspec++;
-        type = *intspec;
-
-        switch (type) {
-        case IRQ_TYPE_LEVEL_LOW:
-        case IRQ_TYPE_LEVEL_HIGH:
-                *out_type = type;
-                break;
-        default:
-                return -EINVAL;
-        }
-        return 0;
-}
-
-static struct irq_domain_ops irq_domain_sdv_ops = {
-        .xlate = sdv_xlate,
-};
-
-static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
-                struct pci_dev *pdev)
-{
-        struct irq_chip_type *ct;
-        int ret;
-
-        sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
-        if (sd->irq_base < 0)
-                return sd->irq_base;
-
-        /* mask + ACK all interrupt sources */
-        writel(0, sd->gpio_pub_base + GPIO_INT);
-        writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
-
-        ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
-                        "sdv_gpio", sd);
-        if (ret)
-                goto out_free_desc;
-
-        /*
-         * This gpio irq controller latches level irqs. Testing shows that if
-         * we unmask & ACK the IRQ before the source of the interrupt is gone
-         * then the interrupt is active again.
-         */
-        sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
-                        sd->gpio_pub_base, handle_fasteoi_irq);
-        if (!sd->gc) {
-                ret = -ENOMEM;
-                goto out_free_irq;
-        }
-
-        sd->gc->private = sd;
-        ct = sd->gc->chip_types;
-        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
-        ct->regs.eoi = GPSTR;
-        ct->regs.mask = GPIO_INT;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->chip.irq_eoi = irq_gc_eoi;
-        ct->chip.irq_set_type = sdv_gpio_pub_set_type;
-
-        irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
-                        IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
-                        IRQ_LEVEL | IRQ_NOPROBE);
-
-        sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
-                                sd->irq_base, 0, &irq_domain_sdv_ops, sd);
-        if (!sd->id)
-                goto out_free_irq;
-        return 0;
-out_free_irq:
-        free_irq(pdev->irq, sd);
-out_free_desc:
-        irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
-        return ret;
-}
-
-static int sdv_gpio_probe(struct pci_dev *pdev,
-                                        const struct pci_device_id *pci_id)
-{
-        struct sdv_gpio_chip_data *sd;
-        unsigned long addr;
-        const void *prop;
-        int len;
-        int ret;
-        u32 mux_val;
-
-        sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
-        if (!sd)
-                return -ENOMEM;
-        ret = pci_enable_device(pdev);
-        if (ret) {
-                dev_err(&pdev->dev, "can't enable device.\n");
-                goto done;
-        }
-
-        ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
-        if (ret) {
-                dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
-                goto disable_pci;
-        }
-
-        addr = pci_resource_start(pdev, GPIO_BAR);
-        if (!addr)
-                goto release_reg;
-        sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
-
-        prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
-        if (prop && len == 4) {
-                mux_val = of_read_number(prop, 1);
-                writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
-        }
-
-        ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
-                        sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
-                        NULL, sd->gpio_pub_base + GPOER, NULL, 0);
-        if (ret)
-                goto unmap;
-        sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
-
-        ret = gpiochip_add(&sd->bgpio.gc);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "gpiochip_add() failed.\n");
-                goto unmap;
-        }
-
-        ret = sdv_register_irqsupport(sd, pdev);
-        if (ret)
-                goto unmap;
-
-        pci_set_drvdata(pdev, sd);
-        dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
-        return 0;
-
-unmap:
-        iounmap(sd->gpio_pub_base);
-release_reg:
-        pci_release_region(pdev, GPIO_BAR);
-disable_pci:
-        pci_disable_device(pdev);
-done:
-        kfree(sd);
-        return ret;
-}
-
-static void sdv_gpio_remove(struct pci_dev *pdev)
-{
-        struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
-
-        free_irq(pdev->irq, sd);
-        irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
-
-        if (gpiochip_remove(&sd->bgpio.gc))
-                dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
-
-        pci_release_region(pdev, GPIO_BAR);
-        iounmap(sd->gpio_pub_base);
-        pci_disable_device(pdev);
-        kfree(sd);
-}
-
-static DEFINE_PCI_DEVICE_TABLE(sdv_gpio_pci_ids) = {
-        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
-        { 0, },
-};
-
-static struct pci_driver sdv_gpio_driver = {
-        .name = DRV_NAME,
-        .id_table = sdv_gpio_pci_ids,
-        .probe = sdv_gpio_probe,
-        .remove = sdv_gpio_remove,
-};
-
-module_pci_driver(sdv_gpio_driver);
-
-MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
-MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-spear-spics.c b/drivers/gpio/gpio-spear-spics.c
deleted file mode 100644
index 5f45fc4ed5d..00000000000
--- a/drivers/gpio/gpio-spear-spics.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * SPEAr platform SPI chipselect abstraction over gpiolib
- *
- * Copyright (C) 2012 ST Microelectronics
- * Shiraz Hashim <shiraz.hashim@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-/* maximum chipselects */
-#define NUM_OF_GPIO     4
-
-/*
- * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
- * through system registers. This register lies outside spi (pl022)
- * address space into system registers.
- *
- * It provides control for spi chip select lines so that any chipselect
- * (out of 4 possible chipselects in pl022) can be made low to select
- * the particular slave.
- */
-
-/**
- * struct spear_spics - represents spi chip select control
- * @base: base address
- * @perip_cfg: configuration register
- * @sw_enable_bit: bit to enable s/w control over chipselects
- * @cs_value_bit: bit to program high or low chipselect
- * @cs_enable_mask: mask to select bits required to select chipselect
- * @cs_enable_shift: bit pos of cs_enable_mask
- * @use_count: use count of a spi controller cs lines
- * @last_off: stores last offset caller of set_value()
- * @chip: gpio_chip abstraction
- */
-struct spear_spics {
-        void __iomem            *base;
-        u32                     perip_cfg;
-        u32                     sw_enable_bit;
-        u32                     cs_value_bit;
-        u32                     cs_enable_mask;
-        u32                     cs_enable_shift;
-        unsigned long           use_count;
-        int                     last_off;
-        struct gpio_chip        chip;
-};
-
-/* gpio framework specific routines */
-static int spics_get_value(struct gpio_chip *chip, unsigned offset)
-{
-        return -ENXIO;
-}
-
-static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct spear_spics *spics = container_of(chip, struct spear_spics,
-                        chip);
-        u32 tmp;
-
-        /* select chip select from register */
-        tmp = readl_relaxed(spics->base + spics->perip_cfg);
-        if (spics->last_off != offset) {
-                spics->last_off = offset;
-                tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
-                tmp |= offset << spics->cs_enable_shift;
-        }
-
-        /* toggle chip select line */
-        tmp &= ~(0x1 << spics->cs_value_bit);
-        tmp |= value << spics->cs_value_bit;
-        writel_relaxed(tmp, spics->base + spics->perip_cfg);
-}
-
-static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        return -ENXIO;
-}
-
-static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
-                int value)
-{
-        spics_set_value(chip, offset, value);
-        return 0;
-}
-
-static int spics_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct spear_spics *spics = container_of(chip, struct spear_spics,
-                        chip);
-        u32 tmp;
-
-        if (!spics->use_count++) {
-                tmp = readl_relaxed(spics->base + spics->perip_cfg);
-                tmp |= 0x1 << spics->sw_enable_bit;
-                tmp |= 0x1 << spics->cs_value_bit;
-                writel_relaxed(tmp, spics->base + spics->perip_cfg);
-        }
-
-        return 0;
-}
-
-static void spics_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct spear_spics *spics = container_of(chip, struct spear_spics,
-                        chip);
-        u32 tmp;
-
-        if (!--spics->use_count) {
-                tmp = readl_relaxed(spics->base + spics->perip_cfg);
-                tmp &= ~(0x1 << spics->sw_enable_bit);
-                writel_relaxed(tmp, spics->base + spics->perip_cfg);
-        }
-}
-
-static int spics_gpio_probe(struct platform_device *pdev)
-{
-        struct device_node *np = pdev->dev.of_node;
-        struct spear_spics *spics;
-        struct resource *res;
-        int ret;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
-                return -EBUSY;
-        }
-
-        spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
-        if (!spics) {
-                dev_err(&pdev->dev, "memory allocation fail\n");
-                return -ENOMEM;
-        }
-
-        spics->base = devm_request_and_ioremap(&pdev->dev, res);
-        if (!spics->base) {
-                dev_err(&pdev->dev, "request and ioremap fail\n");
-                return -ENOMEM;
-        }
-
-        if (of_property_read_u32(np, "st-spics,peripcfg-reg",
-                                &spics->perip_cfg))
-                goto err_dt_data;
-        if (of_property_read_u32(np, "st-spics,sw-enable-bit",
-                                &spics->sw_enable_bit))
-                goto err_dt_data;
-        if (of_property_read_u32(np, "st-spics,cs-value-bit",
-                                &spics->cs_value_bit))
-                goto err_dt_data;
-        if (of_property_read_u32(np, "st-spics,cs-enable-mask",
-                                &spics->cs_enable_mask))
-                goto err_dt_data;
-        if (of_property_read_u32(np, "st-spics,cs-enable-shift",
-                                &spics->cs_enable_shift))
-                goto err_dt_data;
-
-        platform_set_drvdata(pdev, spics);
-
-        spics->chip.ngpio = NUM_OF_GPIO;
-        spics->chip.base = -1;
-        spics->chip.request = spics_request;
-        spics->chip.free = spics_free;
-        spics->chip.direction_input = spics_direction_input;
-        spics->chip.direction_output = spics_direction_output;
-        spics->chip.get = spics_get_value;
-        spics->chip.set = spics_set_value;
-        spics->chip.label = dev_name(&pdev->dev);
-        spics->chip.dev = &pdev->dev;
-        spics->chip.owner = THIS_MODULE;
-        spics->last_off = -1;
-
-        ret = gpiochip_add(&spics->chip);
-        if (ret) {
-                dev_err(&pdev->dev, "unable to add gpio chip\n");
-                return ret;
-        }
-
-        dev_info(&pdev->dev, "spear spics registered\n");
-        return 0;
-
-err_dt_data:
-        dev_err(&pdev->dev, "DT probe failed\n");
-        return -EINVAL;
-}
-
-static const struct of_device_id spics_gpio_of_match[] = {
-        { .compatible = "st,spear-spics-gpio" },
-        {}
-};
-MODULE_DEVICE_TABLE(of, spics_gpio_of_match);
-
-static struct platform_driver spics_gpio_driver = {
-        .probe = spics_gpio_probe,
-        .driver = {
-                .owner = THIS_MODULE,
-                .name = "spear-spics-gpio",
-                .of_match_table = spics_gpio_of_match,
-        },
-};
-
-static int __init spics_gpio_init(void)
-{
-        return platform_driver_register(&spics_gpio_driver);
-}
-subsys_initcall(spics_gpio_init);
-
-MODULE_AUTHOR("Shiraz Hashim <shiraz.hashim@st.com>");
-MODULE_DESCRIPTION("ST Microlectronics SPEAr SPI Chip Select Abstraction");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-sta2x11.c b/drivers/gpio/gpio-sta2x11.c
deleted file mode 100644
index 558542552aa..00000000000
--- a/drivers/gpio/gpio-sta2x11.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * STMicroelectronics ConneXt (STA2X11) GPIO driver
- *
- * Copyright 2012 ST Microelectronics (Alessandro Rubini)
- * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
- * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/pci.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/sta2x11-mfd.h>
-
-struct gsta_regs {
-        u32 dat;                /* 0x00 */
-        u32 dats;
-        u32 datc;
-        u32 pdis;
-        u32 dir;                /* 0x10 */
-        u32 dirs;
-        u32 dirc;
-        u32 unused_1c;
-        u32 afsela;             /* 0x20 */
-        u32 unused_24[7];
-        u32 rimsc;              /* 0x40 */
-        u32 fimsc;
-        u32 is;
-        u32 ic;
-};
-
-struct gsta_gpio {
-        spinlock_t                      lock;
-        struct device                   *dev;
-        void __iomem                    *reg_base;
-        struct gsta_regs __iomem        *regs[GSTA_NR_BLOCKS];
-        struct gpio_chip                gpio;
-        int                             irq_base;
-        /* FIXME: save the whole config here (AF, ...) */
-        unsigned                        irq_type[GSTA_NR_GPIO];
-};
-
-static inline struct gsta_regs __iomem *__regs(struct gsta_gpio *chip, int nr)
-{
-        return chip->regs[nr / GSTA_GPIO_PER_BLOCK];
-}
-
-static inline u32 __bit(int nr)
-{
-        return 1U << (nr % GSTA_GPIO_PER_BLOCK);
-}
-
-/*
- * gpio methods
- */
-
-static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
-{
-        struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-
-        if (val)
-                writel(bit, &regs->dats);
-        else
-                writel(bit, &regs->datc);
-}
-
-static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
-{
-        struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-
-        return readl(&regs->dat) & bit;
-}
-
-static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
-                                      int val)
-{
-        struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-
-        writel(bit, &regs->dirs);
-        /* Data register after direction, otherwise pullup/down is selected */
-        if (val)
-                writel(bit, &regs->dats);
-        else
-                writel(bit, &regs->datc);
-        return 0;
-}
-
-static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
-{
-        struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-
-        writel(bit, &regs->dirc);
-        return 0;
-}
-
-static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
-{
-        struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
-        return chip->irq_base + offset;
-}
-
-static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
-{
-        struct gpio_chip *gpio = &chip->gpio;
-
-        /*
-         * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
-         * from the end. However, for compatibility, we need the first
-         * ConneXt device to start from gpio 0: it's the main chipset
-         * on most boards so documents and drivers assume gpio0..gpio127
-         */
-        static int gpio_base;
-
-        gpio->label = dev_name(chip->dev);
-        gpio->owner = THIS_MODULE;
-        gpio->direction_input = gsta_gpio_direction_input;
-        gpio->get = gsta_gpio_get;
-        gpio->direction_output = gsta_gpio_direction_output;
-        gpio->set = gsta_gpio_set;
-        gpio->dbg_show = NULL;
-        gpio->base = gpio_base;
-        gpio->ngpio = GSTA_NR_GPIO;
-        gpio->can_sleep = 0;
-        gpio->to_irq = gsta_gpio_to_irq;
-
-        /*
-         * After the first device, turn to dynamic gpio numbers.
-         * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
-         */
-        if (!gpio_base)
-                gpio_base = -1;
-}
-
-/*
- * Special method: alternate functions and pullup/pulldown. This is only
- * invoked on startup to configure gpio's according to platform data.
- * FIXME : this functionality shall be managed (and exported to other drivers)
- * via the pin control subsystem.
- */
-static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
-{
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        unsigned long flags;
-        u32 bit = __bit(nr);
-        u32 val;
-        int err = 0;
-
-        pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
-
-        if (cfg == PINMUX_TYPE_NONE)
-                return;
-
-        /* Alternate function or not? */
-        spin_lock_irqsave(&chip->lock, flags);
-        val = readl(&regs->afsela);
-        if (cfg == PINMUX_TYPE_FUNCTION)
-                val |= bit;
-        else
-                val &= ~bit;
-        writel(val | bit, &regs->afsela);
-        if (cfg == PINMUX_TYPE_FUNCTION) {
-                spin_unlock_irqrestore(&chip->lock, flags);
-                return;
-        }
-
-        /* not alternate function: set details */
-        switch (cfg) {
-        case PINMUX_TYPE_OUTPUT_LOW:
-                writel(bit, &regs->dirs);
-                writel(bit, &regs->datc);
-                break;
-        case PINMUX_TYPE_OUTPUT_HIGH:
-                writel(bit, &regs->dirs);
-                writel(bit, &regs->dats);
-                break;
-        case PINMUX_TYPE_INPUT:
-                writel(bit, &regs->dirc);
-                val = readl(&regs->pdis) | bit;
-                writel(val, &regs->pdis);
-                break;
-        case PINMUX_TYPE_INPUT_PULLUP:
-                writel(bit, &regs->dirc);
-                val = readl(&regs->pdis) & ~bit;
-                writel(val, &regs->pdis);
-                writel(bit, &regs->dats);
-                break;
-        case PINMUX_TYPE_INPUT_PULLDOWN:
-                writel(bit, &regs->dirc);
-                val = readl(&regs->pdis) & ~bit;
-                writel(val, &regs->pdis);
-                writel(bit, &regs->datc);
-                break;
-        default:
-                err = 1;
-        }
-        spin_unlock_irqrestore(&chip->lock, flags);
-        if (err)
-                pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
-                       __func__, chip, nr, cfg);
-}
-
-/*
- * Irq methods
- */
-
-static void gsta_irq_disable(struct irq_data *data)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-        struct gsta_gpio *chip = gc->private;
-        int nr = data->irq - chip->irq_base;
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-        u32 val;
-        unsigned long flags;
-
-        spin_lock_irqsave(&chip->lock, flags);
-        if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
-                val = readl(&regs->rimsc) & ~bit;
-                writel(val, &regs->rimsc);
-        }
-        if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
-                val = readl(&regs->fimsc) & ~bit;
-                writel(val, &regs->fimsc);
-        }
-        spin_unlock_irqrestore(&chip->lock, flags);
-        return;
-}
-
-static void gsta_irq_enable(struct irq_data *data)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-        struct gsta_gpio *chip = gc->private;
-        int nr = data->irq - chip->irq_base;
-        struct gsta_regs __iomem *regs = __regs(chip, nr);
-        u32 bit = __bit(nr);
-        u32 val;
-        int type;
-        unsigned long flags;
-
-        type = chip->irq_type[nr];
-
-        spin_lock_irqsave(&chip->lock, flags);
-        val = readl(&regs->rimsc);
-        if (type & IRQ_TYPE_EDGE_RISING)
-                writel(val | bit, &regs->rimsc);
-        else
-                writel(val & ~bit, &regs->rimsc);
-        val = readl(&regs->rimsc);
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                writel(val | bit, &regs->fimsc);
-        else
-                writel(val & ~bit, &regs->fimsc);
-        spin_unlock_irqrestore(&chip->lock, flags);
-        return;
-}
-
-static int gsta_irq_type(struct irq_data *d, unsigned int type)
-{
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct gsta_gpio *chip = gc->private;
-        int nr = d->irq - chip->irq_base;
-
-        /* We only support edge interrupts */
-        if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
-                pr_debug("%s: unsupported type 0x%x\n", __func__, type);
-                return -EINVAL;
-        }
-
-        chip->irq_type[nr] = type; /* used for enable/disable */
-
-        gsta_irq_enable(d);
-        return 0;
-}
-
-static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
-{
-        struct gsta_gpio *chip = dev_id;
-        struct gsta_regs __iomem *regs;
-        u32 is;
-        int i, nr, base;
-        irqreturn_t ret = IRQ_NONE;
-
-        for (i = 0; i < GSTA_NR_BLOCKS; i++) {
-                regs = chip->regs[i];
-                base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
-                while ((is = readl(&regs->is))) {
-                        nr = __ffs(is);
-                        irq = base + nr;
-                        generic_handle_irq(irq);
-                        writel(1 << nr, &regs->ic);
-                        ret = IRQ_HANDLED;
-                }
-        }
-        return ret;
-}
-
-static void gsta_alloc_irq_chip(struct gsta_gpio *chip)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip(KBUILD_MODNAME, 1, chip->irq_base,
-                                     chip->reg_base, handle_simple_irq);
-        gc->private = chip;
-        ct = gc->chip_types;
-
-        ct->chip.irq_set_type = gsta_irq_type;
-        ct->chip.irq_disable = gsta_irq_disable;
-        ct->chip.irq_enable = gsta_irq_enable;
-
-        /* FIXME: this makes at most 32 interrupts. Request 0 by now */
-        irq_setup_generic_chip(gc, 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */, 0,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-
-        /* Set up all all 128 interrupts: code from setup_generic_chip */
-        {
-                struct irq_chip_type *ct = gc->chip_types;
-                int i, j;
-                for (j = 0; j < GSTA_NR_GPIO; j++) {
-                        i = chip->irq_base + j;
-                        irq_set_chip_and_handler(i, &ct->chip, ct->handler);
-                        irq_set_chip_data(i, gc);
-                        irq_modify_status(i, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-                }
-                gc->irq_cnt = i - gc->irq_base;
-        }
-}
-
-/* The platform device used here is instantiated by the MFD device */
-static int gsta_probe(struct platform_device *dev)
-{
-        int i, err;
-        struct pci_dev *pdev;
-        struct sta2x11_gpio_pdata *gpio_pdata;
-        struct gsta_gpio *chip;
-        struct resource *res;
-
-        pdev = *(struct pci_dev **)(dev->dev.platform_data);
-        gpio_pdata = dev_get_platdata(&pdev->dev);
-
-        if (gpio_pdata == NULL)
-                dev_err(&dev->dev, "no gpio config\n");
-        pr_debug("gpio config: %p\n", gpio_pdata);
-
-        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-
-        chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
-        chip->dev = &dev->dev;
-        chip->reg_base = devm_request_and_ioremap(&dev->dev, res);
-
-        for (i = 0; i < GSTA_NR_BLOCKS; i++) {
-                chip->regs[i] = chip->reg_base + i * 4096;
-                /* disable all irqs */
-                writel(0, &chip->regs[i]->rimsc);
-                writel(0, &chip->regs[i]->fimsc);
-                writel(~0, &chip->regs[i]->ic);
-        }
-        spin_lock_init(&chip->lock);
-        gsta_gpio_setup(chip);
-        if (gpio_pdata)
-                for (i = 0; i < GSTA_NR_GPIO; i++)
-                        gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
-
-        /* 384 was used in previous code: be compatible for other drivers */
-        err = irq_alloc_descs(-1, 384, GSTA_NR_GPIO, NUMA_NO_NODE);
-        if (err < 0) {
-                dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
-                         -err);
-                return err;
-        }
-        chip->irq_base = err;
-        gsta_alloc_irq_chip(chip);
-
-        err = request_irq(pdev->irq, gsta_gpio_handler,
-                             IRQF_SHARED, KBUILD_MODNAME, chip);
-        if (err < 0) {
-                dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
-                        -err);
-                goto err_free_descs;
-        }
-
-        err = gpiochip_add(&chip->gpio);
-        if (err < 0) {
-                dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
-                        -err);
-                goto err_free_irq;
-        }
-
-        platform_set_drvdata(dev, chip);
-        return 0;
-
-err_free_irq:
-        free_irq(pdev->irq, chip);
-err_free_descs:
-        irq_free_descs(chip->irq_base, GSTA_NR_GPIO);
-        return err;
-}
-
-static struct platform_driver sta2x11_gpio_platform_driver = {
-        .driver = {
-                .name   = "sta2x11-gpio",
-                .owner  = THIS_MODULE,
-        },
-        .probe = gsta_probe,
-};
-
-module_platform_driver(sta2x11_gpio_platform_driver);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("sta2x11_gpio GPIO driver");
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 770476a9da8..4c980b57332 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -11,9 +11,7 @@
 #include <linux/slab.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
-#include <linux/of.h>
 #include <linux/mfd/stmpe.h>
 
 /*
@@ -30,7 +28,6 @@ struct stmpe_gpio {
         struct stmpe *stmpe;
         struct device *dev;
         struct mutex irq_lock;
-        struct irq_domain *domain;
 
         int irq_base;
         unsigned norequest_mask;
@@ -57,7 +54,7 @@ static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
         if (ret < 0)
                 return ret;
 
-        return !!(ret & mask);
+        return ret & mask;
 }
 
 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -68,14 +65,7 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
         u8 reg = stmpe->regs[which] - (offset / 8);
         u8 mask = 1 << (offset % 8);
 
-        /*
-         * Some variants have single register for gpio set/clear functionality.
-         * For them we need to write 0 to clear and 1 to set.
-         */
-        if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
-                stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
-        else
-                stmpe_reg_write(stmpe, reg, mask);
+        stmpe_reg_write(stmpe, reg, mask);
 }
 
 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
@@ -106,7 +96,7 @@ static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
         struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 
-        return irq_create_mapping(stmpe_gpio->domain, offset);
+        return stmpe_gpio->irq_base + offset;
 }
 
 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -135,17 +125,13 @@ static struct gpio_chip template_chip = {
 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - stmpe_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
         if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
                 return -EINVAL;
 
-        /* STMPE801 doesn't have RE and FE registers */
-        if (stmpe_gpio->stmpe->partnum == STMPE801)
-                return 0;
-
         if (type == IRQ_TYPE_EDGE_RISING)
                 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
         else
@@ -179,11 +165,6 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
         int i, j;
 
         for (i = 0; i < CACHE_NR_REGS; i++) {
-                /* STMPE801 doesn't have RE and FE registers */
-                if ((stmpe->partnum == STMPE801) &&
-                                (i != REG_IE))
-                        continue;
-
                 for (j = 0; j < num_banks; j++) {
                         u8 old = stmpe_gpio->oldregs[i][j];
                         u8 new = stmpe_gpio->regs[i][j];
@@ -202,7 +183,7 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 static void stmpe_gpio_irq_mask(struct irq_data *d)
 {
         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - stmpe_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
@@ -212,7 +193,7 @@ static void stmpe_gpio_irq_mask(struct irq_data *d)
 static void stmpe_gpio_irq_unmask(struct irq_data *d)
 {
         struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - stmpe_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
@@ -254,86 +235,66 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
                 while (stat) {
                         int bit = __ffs(stat);
                         int line = bank * 8 + bit;
-                        int virq = irq_find_mapping(stmpe_gpio->domain, line);
 
-                        handle_nested_irq(virq);
+                        handle_nested_irq(stmpe_gpio->irq_base + line);
                         stat &= ~(1 << bit);
                 }
 
                 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
-
-                /* Edge detect register is not present on 801 */
-                if (stmpe->partnum != STMPE801)
-                        stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
-                                        + i, status[i]);
+                stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
+                                status[i]);
         }
 
         return IRQ_HANDLED;
 }
 
-int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int virq,
-                       irq_hw_number_t hwirq)
+static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
 {
-        struct stmpe_gpio *stmpe_gpio = d->host_data;
-
-        if (!stmpe_gpio)
-                return -EINVAL;
+        int base = stmpe_gpio->irq_base;
+        int irq;
 
-        irq_set_chip_data(hwirq, stmpe_gpio);
-        irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip,
-                                 handle_simple_irq);
-        irq_set_nested_thread(hwirq, 1);
+        for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
+                irq_set_chip_data(irq, stmpe_gpio);
+                irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
+                                         handle_simple_irq);
+                irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
-        set_irq_flags(hwirq, IRQF_VALID);
+                set_irq_flags(irq, IRQF_VALID);
 #else
-        irq_set_noprobe(hwirq);
+                irq_set_noprobe(irq);
 #endif
+        }
 
         return 0;
 }
 
-void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
-{
-#ifdef CONFIG_ARM
-        set_irq_flags(virq, 0);
-#endif
-        irq_set_chip_and_handler(virq, NULL, NULL);
-        irq_set_chip_data(virq, NULL);
-}
-
-static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
-        .unmap = stmpe_gpio_irq_unmap,
-        .map = stmpe_gpio_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
-static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
+static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
 {
         int base = stmpe_gpio->irq_base;
+        int irq;
 
-        stmpe_gpio->domain = irq_domain_add_simple(NULL,
-                                stmpe_gpio->chip.ngpio, base,
-                                &stmpe_gpio_irq_simple_ops, stmpe_gpio);
-        if (!stmpe_gpio->domain) {
-                dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
-                return -ENOSYS;
+        for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
+#ifdef CONFIG_ARM
+                set_irq_flags(irq, 0);
+#endif
+                irq_set_chip_and_handler(irq, NULL, NULL);
+                irq_set_chip_data(irq, NULL);
         }
-
-        return 0;
 }
 
-static int stmpe_gpio_probe(struct platform_device *pdev)
+static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
 {
         struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
-        struct device_node *np = pdev->dev.of_node;
         struct stmpe_gpio_platform_data *pdata;
         struct stmpe_gpio *stmpe_gpio;
         int ret;
-        int irq = 0;
+        int irq;
 
         pdata = stmpe->pdata->gpio;
 
         irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return irq;
 
         stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
         if (!stmpe_gpio)
@@ -343,39 +304,28 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
 
         stmpe_gpio->dev = &pdev->dev;
         stmpe_gpio->stmpe = stmpe;
+        stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
+
         stmpe_gpio->chip = template_chip;
         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
         stmpe_gpio->chip.dev = &pdev->dev;
         stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
 
-        if (pdata)
-                stmpe_gpio->norequest_mask = pdata->norequest_mask;
-        else if (np)
-                of_property_read_u32(np, "st,norequest-mask",
-                                &stmpe_gpio->norequest_mask);
-
-        if (irq >= 0)
-                stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
-        else
-                dev_info(&pdev->dev,
-                        "device configured in no-irq mode; "
-                        "irqs are not available\n");
+        stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
 
         ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
         if (ret)
                 goto out_free;
 
-        if (irq >= 0) {
-                ret = stmpe_gpio_irq_init(stmpe_gpio);
-                if (ret)
-                        goto out_disable;
+        ret = stmpe_gpio_irq_init(stmpe_gpio);
+        if (ret)
+                goto out_disable;
 
-                ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
-                                IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
-                if (ret) {
-                        dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
-                        goto out_disable;
-                }
+        ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
+                                   "stmpe-gpio", stmpe_gpio);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
+                goto out_removeirq;
         }
 
         ret = gpiochip_add(&stmpe_gpio->chip);
@@ -392,8 +342,9 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
         return 0;
 
 out_freeirq:
-        if (irq >= 0)
-                free_irq(irq, stmpe_gpio);
+        free_irq(irq, stmpe_gpio);
+out_removeirq:
+        stmpe_gpio_irq_remove(stmpe_gpio);
 out_disable:
         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 out_free:
@@ -401,7 +352,7 @@ out_free:
         return ret;
 }
 
-static int stmpe_gpio_remove(struct platform_device *pdev)
+static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
 {
         struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
         struct stmpe *stmpe = stmpe_gpio->stmpe;
@@ -421,9 +372,8 @@ static int stmpe_gpio_remove(struct platform_device *pdev)
 
         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 
-        if (irq >= 0)
-                free_irq(irq, stmpe_gpio);
-
+        free_irq(irq, stmpe_gpio);
+        stmpe_gpio_irq_remove(stmpe_gpio);
         platform_set_drvdata(pdev, NULL);
         kfree(stmpe_gpio);
 
@@ -434,7 +384,7 @@ static struct platform_driver stmpe_gpio_driver = {
         .driver.name    = "stmpe-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = stmpe_gpio_probe,
-        .remove         = stmpe_gpio_remove,
+        .remove         = __devexit_p(stmpe_gpio_remove),
 };
 
 static int __init stmpe_gpio_init(void)
diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
deleted file mode 100644
index 85841ee70b1..00000000000
--- a/drivers/gpio/gpio-stp-xway.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
- *
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/of_platform.h>
-#include <linux/mutex.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/of_gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <lantiq_soc.h>
-
-/*
- * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
- * peripheral controller used to drive external shift register cascades. At most
- * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
- * to drive the 2 LSBs of the cascade automatically.
- */
-
-/* control register 0 */
-#define XWAY_STP_CON0           0x00
-/* control register 1 */
-#define XWAY_STP_CON1           0x04
-/* data register 0 */
-#define XWAY_STP_CPU0           0x08
-/* data register 1 */
-#define XWAY_STP_CPU1           0x0C
-/* access register */
-#define XWAY_STP_AR             0x10
-
-/* software or hardware update select bit */
-#define XWAY_STP_CON_SWU        BIT(31)
-
-/* automatic update rates */
-#define XWAY_STP_2HZ            0
-#define XWAY_STP_4HZ            BIT(23)
-#define XWAY_STP_8HZ            BIT(24)
-#define XWAY_STP_10HZ           (BIT(24) | BIT(23))
-#define XWAY_STP_SPEED_MASK     (0xf << 23)
-
-/* clock source for automatic update */
-#define XWAY_STP_UPD_FPI        BIT(31)
-#define XWAY_STP_UPD_MASK       (BIT(31) | BIT(30))
-
-/* let the adsl core drive the 2 LSBs */
-#define XWAY_STP_ADSL_SHIFT     24
-#define XWAY_STP_ADSL_MASK      0x3
-
-/* 2 groups of 3 bits can be driven by the phys */
-#define XWAY_STP_PHY_MASK       0x3
-#define XWAY_STP_PHY1_SHIFT     27
-#define XWAY_STP_PHY2_SHIFT     15
-
-/* STP has 3 groups of 8 bits */
-#define XWAY_STP_GROUP0         BIT(0)
-#define XWAY_STP_GROUP1         BIT(1)
-#define XWAY_STP_GROUP2         BIT(2)
-#define XWAY_STP_GROUP_MASK     (0x7)
-
-/* Edge configuration bits */
-#define XWAY_STP_FALLING        BIT(26)
-#define XWAY_STP_EDGE_MASK      BIT(26)
-
-#define xway_stp_r32(m, reg)            __raw_readl(m + reg)
-#define xway_stp_w32(m, val, reg)       __raw_writel(val, m + reg)
-#define xway_stp_w32_mask(m, clear, set, reg) \
-                ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
-                m + reg)
-
-struct xway_stp {
-        struct gpio_chip gc;
-        void __iomem *virt;
-        u32 edge;       /* rising or falling edge triggered shift register */
-        u32 shadow;     /* shadow the shift registers state */
-        u8 groups;      /* we can drive 1-3 groups of 8bit each */
-        u8 dsl;         /* the 2 LSBs can be driven by the dsl core */
-        u8 phy1;        /* 3 bits can be driven by phy1 */
-        u8 phy2;        /* 3 bits can be driven by phy2 */
-        u8 reserved;    /* mask out the hw driven bits in gpio_request */
-};
-
-/**
- * xway_stp_set() - gpio_chip->set - set gpios.
- * @gc:     Pointer to gpio_chip device structure.
- * @gpio:   GPIO signal number.
- * @val:    Value to be written to specified signal.
- *
- * Set the shadow value and call ltq_ebu_apply.
- */
-static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
-{
-        struct xway_stp *chip =
-                container_of(gc, struct xway_stp, gc);
-
-        if (val)
-                chip->shadow |= BIT(gpio);
-        else
-                chip->shadow &= ~BIT(gpio);
-        xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
-        xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
-}
-
-/**
- * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
- * @gc:     Pointer to gpio_chip device structure.
- * @gpio:   GPIO signal number.
- * @val:    Value to be written to specified signal.
- *
- * Same as xway_stp_set, always returns 0.
- */
-static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
-{
-        xway_stp_set(gc, gpio, val);
-
-        return 0;
-}
-
-/**
- * xway_stp_request() - gpio_chip->request
- * @gc:     Pointer to gpio_chip device structure.
- * @gpio:   GPIO signal number.
- *
- * We mask out the HW driven pins
- */
-static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
-{
-        struct xway_stp *chip =
-                container_of(gc, struct xway_stp, gc);
-
-        if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
-                dev_err(gc->dev, "GPIO %d is driven by hardware\n", gpio);
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
-/**
- * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
- * @virt: pointer to the remapped register range
- */
-static int xway_stp_hw_init(struct xway_stp *chip)
-{
-        /* sane defaults */
-        xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
-        xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
-        xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
-        xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
-        xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
-
-        /* apply edge trigger settings for the shift register */
-        xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
-                                chip->edge, XWAY_STP_CON0);
-
-        /* apply led group settings */
-        xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
-                                chip->groups, XWAY_STP_CON1);
-
-        /* tell the hardware which pins are controlled by the dsl modem */
-        xway_stp_w32_mask(chip->virt,
-                        XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
-                        chip->dsl << XWAY_STP_ADSL_SHIFT,
-                        XWAY_STP_CON0);
-
-        /* tell the hardware which pins are controlled by the phys */
-        xway_stp_w32_mask(chip->virt,
-                        XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
-                        chip->phy1 << XWAY_STP_PHY1_SHIFT,
-                        XWAY_STP_CON0);
-        xway_stp_w32_mask(chip->virt,
-                        XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
-                        chip->phy2 << XWAY_STP_PHY2_SHIFT,
-                        XWAY_STP_CON1);
-
-        /* mask out the hw driven bits in gpio_request */
-        chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
-
-        /*
-         * if we have pins that are driven by hw, we need to tell the stp what
-         * clock to use as a timer.
-         */
-        if (chip->reserved)
-                xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
-                        XWAY_STP_UPD_FPI, XWAY_STP_CON1);
-
-        return 0;
-}
-
-static int xway_stp_probe(struct platform_device *pdev)
-{
-        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        const __be32 *shadow, *groups, *dsl, *phy;
-        struct xway_stp *chip;
-        struct clk *clk;
-        int ret = 0;
-
-        if (!res) {
-                dev_err(&pdev->dev, "failed to request STP resource\n");
-                return -ENOENT;
-        }
-
-        chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
-        if (!chip)
-                return -ENOMEM;
-
-        chip->virt = devm_request_and_ioremap(&pdev->dev, res);
-        if (!chip->virt) {
-                dev_err(&pdev->dev, "failed to remap STP memory\n");
-                return -ENOMEM;
-        }
-        chip->gc.dev = &pdev->dev;
-        chip->gc.label = "stp-xway";
-        chip->gc.direction_output = xway_stp_dir_out;
-        chip->gc.set = xway_stp_set;
-        chip->gc.request = xway_stp_request;
-        chip->gc.base = -1;
-        chip->gc.owner = THIS_MODULE;
-
-        /* store the shadow value if one was passed by the devicetree */
-        shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
-        if (shadow)
-                chip->shadow = be32_to_cpu(*shadow);
-
-        /* find out which gpio groups should be enabled */
-        groups = of_get_property(pdev->dev.of_node, "lantiq,groups", NULL);
-        if (groups)
-                chip->groups = be32_to_cpu(*groups) & XWAY_STP_GROUP_MASK;
-        else
-                chip->groups = XWAY_STP_GROUP0;
-        chip->gc.ngpio = fls(chip->groups) * 8;
-
-        /* find out which gpios are controlled by the dsl core */
-        dsl = of_get_property(pdev->dev.of_node, "lantiq,dsl", NULL);
-        if (dsl)
-                chip->dsl = be32_to_cpu(*dsl) & XWAY_STP_ADSL_MASK;
-
-        /* find out which gpios are controlled by the phys */
-        if (of_machine_is_compatible("lantiq,ar9") ||
-                        of_machine_is_compatible("lantiq,gr9") ||
-                        of_machine_is_compatible("lantiq,vr9")) {
-                phy = of_get_property(pdev->dev.of_node, "lantiq,phy1", NULL);
-                if (phy)
-                        chip->phy1 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
-                phy = of_get_property(pdev->dev.of_node, "lantiq,phy2", NULL);
-                if (phy)
-                        chip->phy2 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
-        }
-
-        /* check which edge trigger we should use, default to a falling edge */
-        if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
-                chip->edge = XWAY_STP_FALLING;
-
-        clk = clk_get(&pdev->dev, NULL);
-        if (IS_ERR(clk)) {
-                dev_err(&pdev->dev, "Failed to get clock\n");
-                return PTR_ERR(clk);
-        }
-        clk_enable(clk);
-
-        ret = xway_stp_hw_init(chip);
-        if (!ret)
-                ret = gpiochip_add(&chip->gc);
-
-        if (!ret)
-                dev_info(&pdev->dev, "Init done\n");
-
-        return ret;
-}
-
-static const struct of_device_id xway_stp_match[] = {
-        { .compatible = "lantiq,gpio-stp-xway" },
-        {},
-};
-MODULE_DEVICE_TABLE(of, xway_stp_match);
-
-static struct platform_driver xway_stp_driver = {
-        .probe = xway_stp_probe,
-        .driver = {
-                .name = "gpio-stp-xway",
-                .owner = THIS_MODULE,
-                .of_match_table = xway_stp_match,
-        },
-};
-
-int __init xway_stp_init(void)
-{
-        return platform_driver_register(&xway_stp_driver);
-}
-
-subsys_initcall(xway_stp_init);
diff --git a/drivers/gpio/gpio-sx150x.c b/drivers/gpio/gpio-sx150x.c
index 796b6c42fa7..a4f73534394 100644
--- a/drivers/gpio/gpio-sx150x.c
+++ b/drivers/gpio/gpio-sx150x.c
@@ -311,9 +311,11 @@ static int sx150x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 
 static void sx150x_irq_mask(struct irq_data *d)
 {
-        struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
+        struct irq_chip *ic = irq_data_get_irq_chip(d);
+        struct sx150x_chip *chip;
         unsigned n;
 
+        chip = container_of(ic, struct sx150x_chip, irq_chip);
         n = d->irq - chip->irq_base;
         chip->irq_masked |= (1 << n);
         chip->irq_update = n;
@@ -321,22 +323,27 @@ static void sx150x_irq_mask(struct irq_data *d)
 
 static void sx150x_irq_unmask(struct irq_data *d)
 {
-        struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
+        struct irq_chip *ic = irq_data_get_irq_chip(d);
+        struct sx150x_chip *chip;
         unsigned n;
 
+        chip = container_of(ic, struct sx150x_chip, irq_chip);
         n = d->irq - chip->irq_base;
+
         chip->irq_masked &= ~(1 << n);
         chip->irq_update = n;
 }
 
 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
+        struct irq_chip *ic = irq_data_get_irq_chip(d);
+        struct sx150x_chip *chip;
         unsigned n, val = 0;
 
         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
                 return -EINVAL;
 
+        chip = container_of(ic, struct sx150x_chip, irq_chip);
         n = d->irq - chip->irq_base;
 
         if (flow_type & IRQ_TYPE_EDGE_RISING)
@@ -384,16 +391,22 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
 
 static void sx150x_irq_bus_lock(struct irq_data *d)
 {
-        struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
+        struct irq_chip *ic = irq_data_get_irq_chip(d);
+        struct sx150x_chip *chip;
+
+        chip = container_of(ic, struct sx150x_chip, irq_chip);
 
         mutex_lock(&chip->lock);
 }
 
 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
 {
-        struct sx150x_chip *chip = irq_data_get_irq_chip_data(d);
+        struct irq_chip *ic = irq_data_get_irq_chip(d);
+        struct sx150x_chip *chip;
         unsigned n;
 
+        chip = container_of(ic, struct sx150x_chip, irq_chip);
+
         if (chip->irq_update == NO_UPDATE_PENDING)
                 goto out;
 
@@ -538,7 +551,6 @@ static int sx150x_install_irq_chip(struct sx150x_chip *chip,
 
         for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
                 irq = irq_base + n;
-                irq_set_chip_data(irq, chip);
                 irq_set_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
                 irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
@@ -575,7 +587,7 @@ static void sx150x_remove_irq_chip(struct sx150x_chip *chip)
         }
 }
 
-static int sx150x_probe(struct i2c_client *client,
+static int __devinit sx150x_probe(struct i2c_client *client,
                                 const struct i2c_device_id *id)
 {
         static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
@@ -622,7 +634,7 @@ probe_fail_pre_gpiochip_add:
         return rc;
 }
 
-static int sx150x_remove(struct i2c_client *client)
+static int __devexit sx150x_remove(struct i2c_client *client)
 {
         struct sx150x_chip *chip;
         int rc;
@@ -646,7 +658,7 @@ static struct i2c_driver sx150x_driver = {
                 .owner = THIS_MODULE
         },
         .probe    = sx150x_probe,
-        .remove   = sx150x_remove,
+        .remove   = __devexit_p(sx150x_remove),
         .id_table = sx150x_id,
 };
 
diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c
index c0595bbf326..2a82e8999a4 100644
--- a/drivers/gpio/gpio-tc3589x.c
+++ b/drivers/gpio/gpio-tc3589x.c
@@ -11,9 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/gpio.h>
-#include <linux/of.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
 #include <linux/mfd/tc3589x.h>
 
@@ -31,7 +29,6 @@ struct tc3589x_gpio {
         struct tc3589x *tc3589x;
         struct device *dev;
         struct mutex irq_lock;
-        struct irq_domain *domain;
 
         int irq_base;
 
@@ -95,28 +92,11 @@ static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
         return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
 }
 
-/**
- * tc3589x_gpio_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
- *
- * @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
- * @irq: index of the interrupt requested in the chip IRQs
- *
- * Useful for drivers to request their own IRQs.
- */
-static int tc3589x_gpio_irq_get_virq(struct tc3589x_gpio *tc3589x_gpio,
-                                     int irq)
-{
-        if (!tc3589x_gpio)
-                return -EINVAL;
-
-        return irq_create_mapping(tc3589x_gpio->domain, irq);
-}
-
 static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
         struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
 
-        return tc3589x_gpio_irq_get_virq(tc3589x_gpio, offset);
+        return tc3589x_gpio->irq_base + offset;
 }
 
 static struct gpio_chip template_chip = {
@@ -133,7 +113,7 @@ static struct gpio_chip template_chip = {
 static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
         struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - tc3589x_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
@@ -195,7 +175,7 @@ static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
 static void tc3589x_gpio_irq_mask(struct irq_data *d)
 {
         struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - tc3589x_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
@@ -205,7 +185,7 @@ static void tc3589x_gpio_irq_mask(struct irq_data *d)
 static void tc3589x_gpio_irq_unmask(struct irq_data *d)
 {
         struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
-        int offset = d->hwirq;
+        int offset = d->irq - tc3589x_gpio->irq_base;
         int regoffset = offset / 8;
         int mask = 1 << (offset % 8);
 
@@ -242,9 +222,8 @@ static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
                 while (stat) {
                         int bit = __ffs(stat);
                         int line = i * 8 + bit;
-                        int virq = tc3589x_gpio_irq_get_virq(tc3589x_gpio, line);
 
-                        handle_nested_irq(virq);
+                        handle_nested_irq(tc3589x_gpio->irq_base + line);
                         stat &= ~(1 << bit);
                 }
 
@@ -254,76 +233,51 @@ static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
         return IRQ_HANDLED;
 }
 
-static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int virq,
-                                irq_hw_number_t hwirq)
+static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio)
 {
-        struct tc3589x *tc3589x_gpio = d->host_data;
+        int base = tc3589x_gpio->irq_base;
+        int irq;
 
-        irq_set_chip_data(virq, tc3589x_gpio);
-        irq_set_chip_and_handler(virq, &tc3589x_gpio_irq_chip,
-                                handle_simple_irq);
-        irq_set_nested_thread(virq, 1);
+        for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
+                irq_set_chip_data(irq, tc3589x_gpio);
+                irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
+                                         handle_simple_irq);
+                irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
-        set_irq_flags(virq, IRQF_VALID);
+                set_irq_flags(irq, IRQF_VALID);
 #else
-        irq_set_noprobe(virq);
+                irq_set_noprobe(irq);
 #endif
+        }
 
         return 0;
 }
 
-static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
-{
-#ifdef CONFIG_ARM
-        set_irq_flags(virq, 0);
-#endif
-        irq_set_chip_and_handler(virq, NULL, NULL);
-        irq_set_chip_data(virq, NULL);
-}
-
-static struct irq_domain_ops tc3589x_irq_ops = {
-        .map    = tc3589x_gpio_irq_map,
-        .unmap  = tc3589x_gpio_irq_unmap,
-        .xlate  = irq_domain_xlate_twocell,
-};
-
-static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio,
-                                struct device_node *np)
+static void tc3589x_gpio_irq_remove(struct tc3589x_gpio *tc3589x_gpio)
 {
         int base = tc3589x_gpio->irq_base;
+        int irq;
 
-        /*
-         * If this results in a linear domain, irq_create_mapping() will
-         * take care of allocating IRQ descriptors at runtime. When a base
-         * is provided, the IRQ descriptors will be allocated when the
-         * domain is instantiated.
-         */
-        tc3589x_gpio->domain = irq_domain_add_simple(np,
-                        tc3589x_gpio->chip.ngpio, base, &tc3589x_irq_ops,
-                        tc3589x_gpio);
-        if (!tc3589x_gpio->domain) {
-                dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
-                return -ENOSYS;
+        for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
+#ifdef CONFIG_ARM
+                set_irq_flags(irq, 0);
+#endif
+                irq_set_chip_and_handler(irq, NULL, NULL);
+                irq_set_chip_data(irq, NULL);
         }
-
-        return 0;
 }
 
-static int tc3589x_gpio_probe(struct platform_device *pdev)
+static int __devinit tc3589x_gpio_probe(struct platform_device *pdev)
 {
         struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
         struct tc3589x_gpio_platform_data *pdata;
-        struct device_node *np = pdev->dev.of_node;
         struct tc3589x_gpio *tc3589x_gpio;
         int ret;
         int irq;
 
         pdata = tc3589x->pdata->gpio;
-
-        if (!(pdata || np)) {
-                dev_err(&pdev->dev, "No platform data or Device Tree found\n");
-                return -EINVAL;
-        }
+        if (!pdata)
+                return -ENODEV;
 
         irq = platform_get_irq(pdev, 0);
         if (irq < 0)
@@ -341,14 +295,9 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
         tc3589x_gpio->chip = template_chip;
         tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
         tc3589x_gpio->chip.dev = &pdev->dev;
-        tc3589x_gpio->chip.base = (pdata) ? pdata->gpio_base : -1;
+        tc3589x_gpio->chip.base = pdata->gpio_base;
 
-#ifdef CONFIG_OF_GPIO
-        tc3589x_gpio->chip.of_node = np;
-#endif
-
-        tc3589x_gpio->irq_base = tc3589x->irq_base ?
-                tc3589x->irq_base + TC3589x_INT_GPIO(0) : 0;
+        tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0);
 
         /* Bring the GPIO module out of reset */
         ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
@@ -356,7 +305,7 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
         if (ret < 0)
                 goto out_free;
 
-        ret = tc3589x_gpio_irq_init(tc3589x_gpio, np);
+        ret = tc3589x_gpio_irq_init(tc3589x_gpio);
         if (ret)
                 goto out_free;
 
@@ -364,7 +313,7 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
                                    "tc3589x-gpio", tc3589x_gpio);
         if (ret) {
                 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
-                goto out_free;
+                goto out_removeirq;
         }
 
         ret = gpiochip_add(&tc3589x_gpio->chip);
@@ -373,7 +322,7 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
                 goto out_freeirq;
         }
 
-        if (pdata && pdata->setup)
+        if (pdata->setup)
                 pdata->setup(tc3589x, tc3589x_gpio->chip.base);
 
         platform_set_drvdata(pdev, tc3589x_gpio);
@@ -382,12 +331,14 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
 
 out_freeirq:
         free_irq(irq, tc3589x_gpio);
+out_removeirq:
+        tc3589x_gpio_irq_remove(tc3589x_gpio);
 out_free:
         kfree(tc3589x_gpio);
         return ret;
 }
 
-static int tc3589x_gpio_remove(struct platform_device *pdev)
+static int __devexit tc3589x_gpio_remove(struct platform_device *pdev)
 {
         struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
         struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
@@ -395,7 +346,7 @@ static int tc3589x_gpio_remove(struct platform_device *pdev)
         int irq = platform_get_irq(pdev, 0);
         int ret;
 
-        if (pdata && pdata->remove)
+        if (pdata->remove)
                 pdata->remove(tc3589x, tc3589x_gpio->chip.base);
 
         ret = gpiochip_remove(&tc3589x_gpio->chip);
@@ -406,6 +357,7 @@ static int tc3589x_gpio_remove(struct platform_device *pdev)
         }
 
         free_irq(irq, tc3589x_gpio);
+        tc3589x_gpio_irq_remove(tc3589x_gpio);
 
         platform_set_drvdata(pdev, NULL);
         kfree(tc3589x_gpio);
@@ -417,7 +369,7 @@ static struct platform_driver tc3589x_gpio_driver = {
         .driver.name    = "tc3589x-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = tc3589x_gpio_probe,
-        .remove         = tc3589x_gpio_remove,
+        .remove         = __devexit_p(tc3589x_gpio_remove),
 };
 
 static int __init tc3589x_gpio_init(void)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 63cb643d4b5..3a0893f9cdc 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -6,6 +6,8 @@
  * Author:
  *      Erik Gilling <konkers@google.com>
  *
+ * Copyright (c) 2011 NVIDIA Corporation.
+ *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -20,24 +22,24 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
+
 #include <linux/io.h>
 #include <linux/gpio.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/irqdomain.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/syscore_ops.h>
 
 #include <asm/mach/irq.h>
 
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+
+#include "../../../arch/arm/mach-tegra/pm-irq.h"
+
 #define GPIO_BANK(x)            ((x) >> 5)
 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
 #define GPIO_BIT(x)             ((x) & 0x7)
 
-#define GPIO_REG(x)             (GPIO_BANK(x) * tegra_gpio_bank_stride + \
-                                        GPIO_PORT(x) * 4)
-
 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
@@ -47,12 +49,29 @@
 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
 
-#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
-#define GPIO_MSK_OE(x)          (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
-#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
-#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
-#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
-#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
+                                 GPIO_BANK(x) * 0x80 +          \
+                                 GPIO_PORT(x) * 4)
+
+#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
+#define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
+#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
+#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
+#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
+#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
+#else
+#define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
+                                 GPIO_BANK(x) * 0x100 +         \
+                                 GPIO_PORT(x) * 4)
+
+#define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x80)
+#define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x90)
+#define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0XA0)
+#define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0xC0)
+#define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0xD0)
+#define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0xE0)
+#endif
 
 #define GPIO_INT_LVL_MASK               0x010101
 #define GPIO_INT_LVL_EDGE_RISING        0x000101
@@ -74,26 +93,28 @@ struct tegra_gpio_bank {
 #endif
 };
 
-static struct irq_domain *irq_domain;
-static void __iomem *regs;
-static u32 tegra_gpio_bank_count;
-static u32 tegra_gpio_bank_stride;
-static u32 tegra_gpio_upper_offset;
-static struct tegra_gpio_bank *tegra_gpio_banks;
-
-static inline void tegra_gpio_writel(u32 val, u32 reg)
-{
-        __raw_writel(val, regs + reg);
-}
+static struct tegra_gpio_bank tegra_gpio_banks[] = {
+        {.bank = 0, .irq = INT_GPIO1},
+        {.bank = 1, .irq = INT_GPIO2},
+        {.bank = 2, .irq = INT_GPIO3},
+        {.bank = 3, .irq = INT_GPIO4},
+        {.bank = 4, .irq = INT_GPIO5},
+        {.bank = 5, .irq = INT_GPIO6},
+        {.bank = 6, .irq = INT_GPIO7},
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        {.bank = 7, .irq = INT_GPIO8},
+#endif
+};
 
-static inline u32 tegra_gpio_readl(u32 reg)
+static int tegra_gpio_compose(int bank, int port, int bit)
 {
-        return __raw_readl(regs + reg);
+        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
 }
 
-static int tegra_gpio_compose(int bank, int port, int bit)
+void tegra_gpio_set_tristate(int gpio_nr, enum tegra_tristate ts)
 {
-        return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
+        int pin_group  =  tegra_pinmux_get_pingroup(gpio_nr);
+        tegra_pinmux_set_tristate(pin_group, ts);
 }
 
 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
@@ -103,28 +124,55 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
         val = 0x100 << GPIO_BIT(gpio);
         if (value)
                 val |= 1 << GPIO_BIT(gpio);
-        tegra_gpio_writel(val, reg);
+        __raw_writel(val, reg);
 }
 
-static void tegra_gpio_enable(int gpio)
+int tegra_gpio_get_bank_int_nr(int gpio)
 {
-        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
+        int bank;
+        int irq;
+        if (gpio >= TEGRA_NR_GPIOS) {
+                pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
+                return -EINVAL;
+        }
+        bank = gpio >> 5;
+        irq = tegra_gpio_banks[bank].irq;
+        return irq;
 }
 
-static void tegra_gpio_disable(int gpio)
+void tegra_gpio_enable(int gpio)
 {
-        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
+        if (gpio >= TEGRA_NR_GPIOS) {
+                pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
+                return;
+        }
+        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
+EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 
-static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+void tegra_gpio_disable(int gpio)
 {
-        return pinctrl_request_gpio(offset);
+        if (gpio >= TEGRA_NR_GPIOS) {
+                pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
+                return;
+        }
+        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 }
+EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 
-static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
+void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value)
 {
-        pinctrl_free_gpio(offset);
-        tegra_gpio_disable(offset);
+        if (gpio >= TEGRA_NR_GPIOS) {
+                pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
+                return;
+        }
+        if (is_input) {
+                tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
+        } else {
+                tegra_gpio_mask_write(GPIO_MSK_OUT(gpio), gpio, value);
+                tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 1);
+        }
+        tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
 
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -134,18 +182,15 @@ static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 
 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        /* If gpio is in output mode then read from the out value */
-        if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
-                return (tegra_gpio_readl(GPIO_OUT(offset)) >>
-                                GPIO_BIT(offset)) & 0x1;
-
-        return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
+        if ((__raw_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 0x1)
+                return (__raw_readl(GPIO_OUT(offset)) >>
+                        GPIO_BIT(offset)) & 0x1;
+        return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 }
 
 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
-        tegra_gpio_enable(offset);
         return 0;
 }
 
@@ -154,51 +199,65 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 {
         tegra_gpio_set(chip, offset, value);
         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
-        tegra_gpio_enable(offset);
         return 0;
 }
 
+static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
+                                unsigned debounce)
+{
+        return -ENOSYS;
+}
+
 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        return irq_find_mapping(irq_domain, offset);
+        return TEGRA_GPIO_TO_IRQ(offset);
 }
 
 static struct gpio_chip tegra_gpio_chip = {
         .label                  = "tegra-gpio",
-        .request                = tegra_gpio_request,
-        .free                   = tegra_gpio_free,
         .direction_input        = tegra_gpio_direction_input,
         .get                    = tegra_gpio_get,
         .direction_output       = tegra_gpio_direction_output,
         .set                    = tegra_gpio_set,
+        .set_debounce           = tegra_gpio_set_debounce,
         .to_irq                 = tegra_gpio_to_irq,
         .base                   = 0,
+        .ngpio                  = TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(struct irq_data *d)
 {
-        int gpio = d->hwirq;
+        int gpio = d->irq - INT_GPIO_BASE;
+
+        __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 
-        tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
+#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+        /* FPGA platforms have a serializer between the GPIO
+           block and interrupt controller. Allow time for
+           clearing of the GPIO interrupt to propagate to the
+           interrupt controller before re-enabling the IRQ
+           to prevent double interrupts. */
+        udelay(15);
+#endif
 }
 
 static void tegra_gpio_irq_mask(struct irq_data *d)
 {
-        int gpio = d->hwirq;
+        int gpio = d->irq - INT_GPIO_BASE;
 
         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 }
 
 static void tegra_gpio_irq_unmask(struct irq_data *d)
 {
-        int gpio = d->hwirq;
+        int gpio = d->irq - INT_GPIO_BASE;
 
         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 }
 
 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
-        int gpio = d->hwirq;
+        int gpio = d->irq - INT_GPIO_BASE;
         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
         int port = GPIO_PORT(gpio);
         int lvl_type;
@@ -232,21 +291,20 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 
         spin_lock_irqsave(&bank->lvl_lock[port], flags);
 
-        val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+        val = __raw_readl(GPIO_INT_LVL(gpio));
         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
         val |= lvl_type << GPIO_BIT(gpio);
-        tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
+        __raw_writel(val, GPIO_INT_LVL(gpio));
 
         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 
-        tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
-        tegra_gpio_enable(gpio);
-
         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
                 __irq_set_handler_locked(d->irq, handle_level_irq);
         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 
+        tegra_pm_irq_set_wake_type(d->irq, type);
+
         return 0;
 }
 
@@ -255,7 +313,6 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         struct tegra_gpio_bank *bank;
         int port;
         int pin;
-        int unmasked = 0;
         struct irq_chip *chip = irq_desc_get_chip(desc);
 
         chained_irq_enter(chip, desc);
@@ -264,33 +321,19 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         for (port = 0; port < 4; port++) {
                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
-                unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
-                        tegra_gpio_readl(GPIO_INT_ENB(gpio));
-                u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
-
-                for_each_set_bit(pin, &sta, 8) {
-                        tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
-
-                        /* if gpio is edge triggered, clear condition
-                         * before executing the hander so that we don't
-                         * miss edges
-                         */
-                        if (lvl & (0x100 << pin)) {
-                                unmasked = 1;
-                                chained_irq_exit(chip, desc);
-                        }
+                unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
+                        __raw_readl(GPIO_INT_ENB(gpio));
 
+                for_each_set_bit(pin, &sta, 8)
                         generic_handle_irq(gpio_to_irq(gpio + pin));
-                }
         }
 
-        if (!unmasked)
-                chained_irq_exit(chip, desc);
+        chained_irq_exit(chip, desc);
 
 }
 
 #ifdef CONFIG_PM_SLEEP
-static int tegra_gpio_resume(struct device *dev)
+static void tegra_gpio_resume(void)
 {
         unsigned long flags;
         int b;
@@ -298,179 +341,125 @@ static int tegra_gpio_resume(struct device *dev)
 
         local_irq_save(flags);
 
-        for (b = 0; b < tegra_gpio_bank_count; b++) {
+        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 
                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
                         unsigned int gpio = (b<<5) | (p<<3);
-                        tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
-                        tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
-                        tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
-                        tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
-                        tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
+                        __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
+                        __raw_writel(bank->out[p], GPIO_OUT(gpio));
+                        __raw_writel(bank->oe[p], GPIO_OE(gpio));
+                        __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
+                        __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
                 }
         }
 
         local_irq_restore(flags);
-        return 0;
 }
 
-static int tegra_gpio_suspend(struct device *dev)
+static int tegra_gpio_suspend(void)
 {
         unsigned long flags;
         int b;
         int p;
 
         local_irq_save(flags);
-        for (b = 0; b < tegra_gpio_bank_count; b++) {
+        for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 
                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
                         unsigned int gpio = (b<<5) | (p<<3);
-                        bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
-                        bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
-                        bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
-                        bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
-                        bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
+                        bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
+                        bank->out[p] = __raw_readl(GPIO_OUT(gpio));
+                        bank->oe[p] = __raw_readl(GPIO_OE(gpio));
+                        bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
+                        bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
                 }
         }
         local_irq_restore(flags);
+
         return 0;
 }
 
-static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
+static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 {
         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        return irq_set_irq_wake(bank->irq, enable);
+        int ret = 0;
+
+        ret = tegra_pm_irq_set_wake(d->irq, enable);
+
+        if (ret)
+                return ret;
+
+        ret = irq_set_irq_wake(bank->irq, enable);
+
+        if (ret)
+                tegra_pm_irq_set_wake(d->irq, !enable);
+
+        return ret;
 }
+#else
+#define tegra_gpio_irq_set_wake NULL
+#define tegra_gpio_suspend NULL
+#define tegra_gpio_resume NULL
 #endif
 
+static struct syscore_ops tegra_gpio_syscore_ops = {
+        .suspend = tegra_gpio_suspend,
+        .resume = tegra_gpio_resume,
+};
+
+int tegra_gpio_resume_init(void)
+{
+        register_syscore_ops(&tegra_gpio_syscore_ops);
+
+        return 0;
+}
+
 static struct irq_chip tegra_gpio_irq_chip = {
         .name           = "GPIO",
         .irq_ack        = tegra_gpio_irq_ack,
         .irq_mask       = tegra_gpio_irq_mask,
         .irq_unmask     = tegra_gpio_irq_unmask,
         .irq_set_type   = tegra_gpio_irq_set_type,
-#ifdef CONFIG_PM_SLEEP
-        .irq_set_wake   = tegra_gpio_wake_enable,
-#endif
-};
-
-static const struct dev_pm_ops tegra_gpio_pm_ops = {
-        SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
-};
-
-struct tegra_gpio_soc_config {
-        u32 bank_stride;
-        u32 upper_offset;
-};
-
-static struct tegra_gpio_soc_config tegra20_gpio_config = {
-        .bank_stride = 0x80,
-        .upper_offset = 0x800,
-};
-
-static struct tegra_gpio_soc_config tegra30_gpio_config = {
-        .bank_stride = 0x100,
-        .upper_offset = 0x80,
+        .irq_set_wake   = tegra_gpio_irq_set_wake,
+        .flags          = IRQCHIP_MASK_ON_SUSPEND,
 };
 
-static struct of_device_id tegra_gpio_of_match[] = {
-        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
-        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
-        { },
-};
 
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
  */
 static struct lock_class_key gpio_lock_class;
 
-static int tegra_gpio_probe(struct platform_device *pdev)
+static int __init tegra_gpio_init(void)
 {
-        const struct of_device_id *match;
-        struct tegra_gpio_soc_config *config;
-        struct resource *res;
         struct tegra_gpio_bank *bank;
         int gpio;
         int i;
         int j;
 
-        match = of_match_device(tegra_gpio_of_match, &pdev->dev);
-        if (match)
-                config = (struct tegra_gpio_soc_config *)match->data;
-        else
-                config = &tegra20_gpio_config;
-
-        tegra_gpio_bank_stride = config->bank_stride;
-        tegra_gpio_upper_offset = config->upper_offset;
-
-        for (;;) {
-                res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
-                if (!res)
-                        break;
-                tegra_gpio_bank_count++;
-        }
-        if (!tegra_gpio_bank_count) {
-                dev_err(&pdev->dev, "Missing IRQ resource\n");
-                return -ENODEV;
-        }
-
-        tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
-
-        tegra_gpio_banks = devm_kzalloc(&pdev->dev,
-                        tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
-                        GFP_KERNEL);
-        if (!tegra_gpio_banks) {
-                dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
-                return -ENODEV;
-        }
-
-        irq_domain = irq_domain_add_linear(pdev->dev.of_node,
-                                           tegra_gpio_chip.ngpio,
-                                           &irq_domain_simple_ops, NULL);
-        if (!irq_domain)
-                return -ENODEV;
-
-        for (i = 0; i < tegra_gpio_bank_count; i++) {
-                res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
-                if (!res) {
-                        dev_err(&pdev->dev, "Missing IRQ resource\n");
-                        return -ENODEV;
-                }
-
-                bank = &tegra_gpio_banks[i];
-                bank->bank = i;
-                bank->irq = res->start;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "Missing MEM resource\n");
-                return -ENODEV;
-        }
-
-        regs = devm_request_and_ioremap(&pdev->dev, res);
-        if (!regs) {
-                dev_err(&pdev->dev, "Couldn't ioremap regs\n");
-                return -ENODEV;
-        }
-
-        for (i = 0; i < tegra_gpio_bank_count; i++) {
+        for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
                 for (j = 0; j < 4; j++) {
                         int gpio = tegra_gpio_compose(i, j, 0);
-                        tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
+                        __raw_writel(0x00, GPIO_INT_ENB(gpio));
+                        __raw_writel(0x00, GPIO_INT_STA(gpio));
                 }
         }
 
 #ifdef CONFIG_OF_GPIO
-        tegra_gpio_chip.of_node = pdev->dev.of_node;
-#endif
+        /*
+         * This isn't ideal, but it gets things hooked up until this
+         * driver is converted into a platform_device
+         */
+        tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
+                                                "nvidia,tegra20-gpio");
+#endif /* CONFIG_OF_GPIO */
 
         gpiochip_add(&tegra_gpio_chip);
 
-        for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
-                int irq = irq_create_mapping(irq_domain, gpio);
+        for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
+                int irq = TEGRA_GPIO_TO_IRQ(gpio);
                 /* No validity check; all Tegra GPIOs are valid IRQs */
 
                 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
@@ -482,34 +471,35 @@ static int tegra_gpio_probe(struct platform_device *pdev)
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        for (i = 0; i < tegra_gpio_bank_count; i++) {
+        for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
                 bank = &tegra_gpio_banks[i];
 
-                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
-                irq_set_handler_data(bank->irq, bank);
-
                 for (j = 0; j < 4; j++)
                         spin_lock_init(&bank->lvl_lock[j]);
+
+                irq_set_handler_data(bank->irq, bank);
+                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
+
         }
 
         return 0;
 }
 
-static struct platform_driver tegra_gpio_driver = {
-        .driver         = {
-                .name   = "tegra-gpio",
-                .owner  = THIS_MODULE,
-                .pm     = &tegra_gpio_pm_ops,
-                .of_match_table = tegra_gpio_of_match,
-        },
-        .probe          = tegra_gpio_probe,
-};
+postcore_initcall(tegra_gpio_init);
 
-static int __init tegra_gpio_init(void)
+void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
 {
-        return platform_driver_register(&tegra_gpio_driver);
+        int i;
+
+        for (i = 0; i < num; i++) {
+                int gpio = table[i].gpio;
+
+                if (table[i].enable)
+                        tegra_gpio_enable(gpio);
+                else
+                        tegra_gpio_disable(gpio);
+        }
 }
-postcore_initcall(tegra_gpio_init);
 
 #ifdef  CONFIG_DEBUG_FS
 
@@ -521,19 +511,20 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
         int i;
         int j;
 
-        for (i = 0; i < tegra_gpio_bank_count; i++) {
+        seq_printf(s, "Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL\n");
+        for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
                 for (j = 0; j < 4; j++) {
                         int gpio = tegra_gpio_compose(i, j, 0);
                         seq_printf(s,
                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
                                 i, j,
-                                tegra_gpio_readl(GPIO_CNF(gpio)),
-                                tegra_gpio_readl(GPIO_OE(gpio)),
-                                tegra_gpio_readl(GPIO_OUT(gpio)),
-                                tegra_gpio_readl(GPIO_IN(gpio)),
-                                tegra_gpio_readl(GPIO_INT_STA(gpio)),
-                                tegra_gpio_readl(GPIO_INT_ENB(gpio)),
-                                tegra_gpio_readl(GPIO_INT_LVL(gpio)));
+                                __raw_readl(GPIO_CNF(gpio)),
+                                __raw_readl(GPIO_OE(gpio)),
+                                __raw_readl(GPIO_OUT(gpio)),
+                                __raw_readl(GPIO_IN(gpio)),
+                                __raw_readl(GPIO_INT_STA(gpio)),
+                                __raw_readl(GPIO_INT_ENB(gpio)),
+                                __raw_readl(GPIO_INT_LVL(gpio)));
                 }
         }
         return 0;
diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c
index 702cca9284f..c593bd46bfb 100644
--- a/drivers/gpio/gpio-timberdale.c
+++ b/drivers/gpio/gpio-timberdale.c
@@ -116,7 +116,7 @@ static void timbgpio_irq_disable(struct irq_data *d)
         unsigned long flags;
 
         spin_lock_irqsave(&tgpio->lock, flags);
-        tgpio->last_ier &= ~(1UL << offset);
+        tgpio->last_ier &= ~(1 << offset);
         iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
         spin_unlock_irqrestore(&tgpio->lock, flags);
 }
@@ -128,7 +128,7 @@ static void timbgpio_irq_enable(struct irq_data *d)
         unsigned long flags;
 
         spin_lock_irqsave(&tgpio->lock, flags);
-        tgpio->last_ier |= 1UL << offset;
+        tgpio->last_ier |= 1 << offset;
         iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
         spin_unlock_irqrestore(&tgpio->lock, flags);
 }
@@ -222,7 +222,7 @@ static struct irq_chip timbgpio_irqchip = {
         .irq_set_type   = timbgpio_irq_type,
 };
 
-static int timbgpio_probe(struct platform_device *pdev)
+static int __devinit timbgpio_probe(struct platform_device *pdev)
 {
         int err, i;
         struct gpio_chip *gc;
@@ -316,7 +316,7 @@ err_mem:
         return err;
 }
 
-static int timbgpio_remove(struct platform_device *pdev)
+static int __devexit timbgpio_remove(struct platform_device *pdev)
 {
         int err;
         struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
@@ -359,7 +359,18 @@ static struct platform_driver timbgpio_platform_driver = {
 
 /*--------------------------------------------------------------------------*/
 
-module_platform_driver(timbgpio_platform_driver);
+static int __init timbgpio_init(void)
+{
+        return platform_driver_register(&timbgpio_platform_driver);
+}
+
+static void __exit timbgpio_exit(void)
+{
+        platform_driver_unregister(&timbgpio_platform_driver);
+}
+
+module_init(timbgpio_init);
+module_exit(timbgpio_exit);
 
 MODULE_DESCRIPTION("Timberdale GPIO driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-tnetv107x.c b/drivers/gpio/gpio-tnetv107x.c
deleted file mode 100644
index 3fa3e2867e1..00000000000
--- a/drivers/gpio/gpio-tnetv107x.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Texas Instruments TNETV107X GPIO Controller
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-
-#include <mach/common.h>
-#include <mach/tnetv107x.h>
-
-struct tnetv107x_gpio_regs {
-        u32     idver;
-        u32     data_in[3];
-        u32     data_out[3];
-        u32     direction[3];
-        u32     enable[3];
-};
-
-#define gpio_reg_index(gpio)    ((gpio) >> 5)
-#define gpio_reg_bit(gpio)      BIT((gpio) & 0x1f)
-
-#define gpio_reg_rmw(reg, mask, val)    \
-        __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
-
-#define gpio_reg_set_bit(reg, gpio)     \
-        gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
-
-#define gpio_reg_clear_bit(reg, gpio)   \
-        gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
-
-#define gpio_reg_get_bit(reg, gpio)     \
-        (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
-
-#define chip2controller(chip)           \
-        container_of(chip, struct davinci_gpio_controller, chip)
-
-#define TNETV107X_GPIO_CTLRS    DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
-
-static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
-
-static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ctlr->lock, flags);
-
-        gpio_reg_set_bit(regs->enable, gpio);
-
-        spin_unlock_irqrestore(&ctlr->lock, flags);
-
-        return 0;
-}
-
-static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ctlr->lock, flags);
-
-        gpio_reg_clear_bit(regs->enable, gpio);
-
-        spin_unlock_irqrestore(&ctlr->lock, flags);
-}
-
-static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ctlr->lock, flags);
-
-        gpio_reg_set_bit(regs->direction, gpio);
-
-        spin_unlock_irqrestore(&ctlr->lock, flags);
-
-        return 0;
-}
-
-static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
-                unsigned offset, int value)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ctlr->lock, flags);
-
-        if (value)
-                gpio_reg_set_bit(regs->data_out, gpio);
-        else
-                gpio_reg_clear_bit(regs->data_out, gpio);
-
-        gpio_reg_clear_bit(regs->direction, gpio);
-
-        spin_unlock_irqrestore(&ctlr->lock, flags);
-
-        return 0;
-}
-
-static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        int ret;
-
-        ret = gpio_reg_get_bit(regs->data_in, gpio);
-
-        return ret ? 1 : 0;
-}
-
-static void tnetv107x_gpio_set(struct gpio_chip *chip,
-                unsigned offset, int value)
-{
-        struct davinci_gpio_controller *ctlr = chip2controller(chip);
-        struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
-        unsigned gpio = chip->base + offset;
-        unsigned long flags;
-
-        spin_lock_irqsave(&ctlr->lock, flags);
-
-        if (value)
-                gpio_reg_set_bit(regs->data_out, gpio);
-        else
-                gpio_reg_clear_bit(regs->data_out, gpio);
-
-        spin_unlock_irqrestore(&ctlr->lock, flags);
-}
-
-static int __init tnetv107x_gpio_setup(void)
-{
-        int i, base;
-        unsigned ngpio;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct tnetv107x_gpio_regs *regs;
-        struct davinci_gpio_controller *ctlr;
-
-        if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
-                return 0;
-
-        ngpio = soc_info->gpio_num;
-        if (ngpio == 0) {
-                pr_err("GPIO setup:  how many GPIOs?\n");
-                return -EINVAL;
-        }
-
-        if (WARN_ON(TNETV107X_N_GPIO < ngpio))
-                ngpio = TNETV107X_N_GPIO;
-
-        regs = ioremap(soc_info->gpio_base, SZ_4K);
-        if (WARN_ON(!regs))
-                return -EINVAL;
-
-        for (i = 0, base = 0; base < ngpio; i++, base += 32) {
-                ctlr = &chips[i];
-
-                ctlr->chip.label        = "tnetv107x";
-                ctlr->chip.can_sleep    = 0;
-                ctlr->chip.base         = base;
-                ctlr->chip.ngpio        = ngpio - base;
-                if (ctlr->chip.ngpio > 32)
-                        ctlr->chip.ngpio = 32;
-
-                ctlr->chip.request              = tnetv107x_gpio_request;
-                ctlr->chip.free                 = tnetv107x_gpio_free;
-                ctlr->chip.direction_input      = tnetv107x_gpio_dir_in;
-                ctlr->chip.get                  = tnetv107x_gpio_get;
-                ctlr->chip.direction_output     = tnetv107x_gpio_dir_out;
-                ctlr->chip.set                  = tnetv107x_gpio_set;
-
-                spin_lock_init(&ctlr->lock);
-
-                ctlr->regs      = regs;
-                ctlr->set_data  = &regs->data_out[i];
-                ctlr->clr_data  = &regs->data_out[i];
-                ctlr->in_data   = &regs->data_in[i];
-
-                gpiochip_add(&ctlr->chip);
-        }
-
-        soc_info->gpio_ctlrs = chips;
-        soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
-        return 0;
-}
-pure_initcall(tnetv107x_gpio_setup);
diff --git a/drivers/gpio/gpio-tps6586x.c b/drivers/gpio/gpio-tps6586x.c
deleted file mode 100644
index 29e8e750bd4..00000000000
--- a/drivers/gpio/gpio-tps6586x.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * TI TPS6586x GPIO driver
- *
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- * Author: Laxman dewangan <ldewangan@nvidia.com>
- *
- * Based on tps6586x.c
- * Copyright (c) 2010 CompuLab Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/errno.h>
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-/* GPIO control registers */
-#define TPS6586X_GPIOSET1       0x5d
-#define TPS6586X_GPIOSET2       0x5e
-
-struct tps6586x_gpio {
-        struct gpio_chip gpio_chip;
-        struct device *parent;
-};
-
-static inline struct tps6586x_gpio *to_tps6586x_gpio(struct gpio_chip *chip)
-{
-        return container_of(chip, struct tps6586x_gpio, gpio_chip);
-}
-
-static int tps6586x_gpio_get(struct gpio_chip *gc, unsigned offset)
-{
-        struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
-        uint8_t val;
-        int ret;
-
-        ret = tps6586x_read(tps6586x_gpio->parent, TPS6586X_GPIOSET2, &val);
-        if (ret)
-                return ret;
-
-        return !!(val & (1 << offset));
-}
-
-static void tps6586x_gpio_set(struct gpio_chip *gc, unsigned offset,
-                              int value)
-{
-        struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
-
-        tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET2,
-                        value << offset, 1 << offset);
-}
-
-static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
-                                int value)
-{
-        struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
-        uint8_t val, mask;
-
-        tps6586x_gpio_set(gc, offset, value);
-
-        val = 0x1 << (offset * 2);
-        mask = 0x3 << (offset * 2);
-
-        return tps6586x_update(tps6586x_gpio->parent, TPS6586X_GPIOSET1,
-                                val, mask);
-}
-
-static int tps6586x_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-        struct tps6586x_gpio *tps6586x_gpio = to_tps6586x_gpio(gc);
-
-        return tps6586x_irq_get_virq(tps6586x_gpio->parent,
-                                TPS6586X_INT_PLDO_0 + offset);
-}
-
-static int tps6586x_gpio_probe(struct platform_device *pdev)
-{
-        struct tps6586x_platform_data *pdata;
-        struct tps6586x_gpio *tps6586x_gpio;
-        int ret;
-
-        pdata = dev_get_platdata(pdev->dev.parent);
-        tps6586x_gpio = devm_kzalloc(&pdev->dev,
-                                sizeof(*tps6586x_gpio), GFP_KERNEL);
-        if (!tps6586x_gpio) {
-                dev_err(&pdev->dev, "Could not allocate tps6586x_gpio\n");
-                return -ENOMEM;
-        }
-
-        tps6586x_gpio->parent = pdev->dev.parent;
-
-        tps6586x_gpio->gpio_chip.owner = THIS_MODULE;
-        tps6586x_gpio->gpio_chip.label = pdev->name;
-        tps6586x_gpio->gpio_chip.dev = &pdev->dev;
-        tps6586x_gpio->gpio_chip.ngpio = 4;
-        tps6586x_gpio->gpio_chip.can_sleep = 1;
-
-        /* FIXME: add handling of GPIOs as dedicated inputs */
-        tps6586x_gpio->gpio_chip.direction_output = tps6586x_gpio_output;
-        tps6586x_gpio->gpio_chip.set    = tps6586x_gpio_set;
-        tps6586x_gpio->gpio_chip.get    = tps6586x_gpio_get;
-        tps6586x_gpio->gpio_chip.to_irq = tps6586x_gpio_to_irq;
-
-#ifdef CONFIG_OF_GPIO
-        tps6586x_gpio->gpio_chip.of_node = pdev->dev.parent->of_node;
-#endif
-        if (pdata && pdata->gpio_base)
-                tps6586x_gpio->gpio_chip.base = pdata->gpio_base;
-        else
-                tps6586x_gpio->gpio_chip.base = -1;
-
-        ret = gpiochip_add(&tps6586x_gpio->gpio_chip);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                return ret;
-        }
-
-        platform_set_drvdata(pdev, tps6586x_gpio);
-
-        return ret;
-}
-
-static int tps6586x_gpio_remove(struct platform_device *pdev)
-{
-        struct tps6586x_gpio *tps6586x_gpio = platform_get_drvdata(pdev);
-
-        return gpiochip_remove(&tps6586x_gpio->gpio_chip);
-}
-
-static struct platform_driver tps6586x_gpio_driver = {
-        .driver.name    = "tps6586x-gpio",
-        .driver.owner   = THIS_MODULE,
-        .probe          = tps6586x_gpio_probe,
-        .remove         = tps6586x_gpio_remove,
-};
-
-static int __init tps6586x_gpio_init(void)
-{
-        return platform_driver_register(&tps6586x_gpio_driver);
-}
-subsys_initcall(tps6586x_gpio_init);
-
-static void __exit tps6586x_gpio_exit(void)
-{
-        platform_driver_unregister(&tps6586x_gpio_driver);
-}
-module_exit(tps6586x_gpio_exit);
-
-MODULE_ALIAS("platform:tps6586x-gpio");
-MODULE_DESCRIPTION("GPIO interface for TPS6586X PMIC");
-MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-tps65910.c b/drivers/gpio/gpio-tps65910.c
index 5083825a034..7eef648a335 100644
--- a/drivers/gpio/gpio-tps65910.c
+++ b/drivers/gpio/gpio-tps65910.c
@@ -18,27 +18,14 @@
 #include <linux/errno.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
-#include <linux/platform_device.h>
 #include <linux/mfd/tps65910.h>
-#include <linux/of_device.h>
-
-struct tps65910_gpio {
-        struct gpio_chip gpio_chip;
-        struct tps65910 *tps65910;
-};
-
-static inline struct tps65910_gpio *to_tps65910_gpio(struct gpio_chip *chip)
-{
-        return container_of(chip, struct tps65910_gpio, gpio_chip);
-}
 
 static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset)
 {
-        struct tps65910_gpio *tps65910_gpio = to_tps65910_gpio(gc);
-        struct tps65910 *tps65910 = tps65910_gpio->tps65910;
-        unsigned int val;
+        struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
+        uint8_t val;
 
-        tps65910_reg_read(tps65910, TPS65910_GPIO0 + offset, &val);
+        tps65910->read(tps65910, TPS65910_GPIO0 + offset, 1, &val);
 
         if (val & GPIO_STS_MASK)
                 return 1;
@@ -49,173 +36,83 @@ static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset)
 static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset,
                               int value)
 {
-        struct tps65910_gpio *tps65910_gpio = to_tps65910_gpio(gc);
-        struct tps65910 *tps65910 = tps65910_gpio->tps65910;
+        struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
 
         if (value)
-                tps65910_reg_set_bits(tps65910, TPS65910_GPIO0 + offset,
+                tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
                                                 GPIO_SET_MASK);
         else
-                tps65910_reg_clear_bits(tps65910, TPS65910_GPIO0 + offset,
+                tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
                                                 GPIO_SET_MASK);
 }
 
 static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
                                 int value)
 {
-        struct tps65910_gpio *tps65910_gpio = to_tps65910_gpio(gc);
-        struct tps65910 *tps65910 = tps65910_gpio->tps65910;
+        struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
 
         /* Set the initial value */
         tps65910_gpio_set(gc, offset, value);
 
-        return tps65910_reg_set_bits(tps65910, TPS65910_GPIO0 + offset,
+        return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
                                                 GPIO_CFG_MASK);
 }
 
 static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
 {
-        struct tps65910_gpio *tps65910_gpio = to_tps65910_gpio(gc);
-        struct tps65910 *tps65910 = tps65910_gpio->tps65910;
+        struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
 
-        return tps65910_reg_clear_bits(tps65910, TPS65910_GPIO0 + offset,
+        return tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
                                                 GPIO_CFG_MASK);
 }
 
-#ifdef CONFIG_OF
-static struct tps65910_board *tps65910_parse_dt_for_gpio(struct device *dev,
-                struct tps65910 *tps65910, int chip_ngpio)
+void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
 {
-        struct tps65910_board *tps65910_board = tps65910->of_plat_data;
-        unsigned int prop_array[TPS6591X_MAX_NUM_GPIO];
-        int ngpio = min(chip_ngpio, TPS6591X_MAX_NUM_GPIO);
         int ret;
-        int idx;
-
-        tps65910_board->gpio_base = -1;
-        ret = of_property_read_u32_array(tps65910->dev->of_node,
-                        "ti,en-gpio-sleep", prop_array, ngpio);
-        if (ret < 0) {
-                dev_dbg(dev, "ti,en-gpio-sleep not specified\n");
-                return tps65910_board;
-        }
+        struct tps65910_board *board_data;
 
-        for (idx = 0; idx < ngpio; idx++)
-                tps65910_board->en_gpio_sleep[idx] = (prop_array[idx] != 0);
+        if (!gpio_base)
+                return;
 
-        return tps65910_board;
-}
-#else
-static struct tps65910_board *tps65910_parse_dt_for_gpio(struct device *dev,
-                struct tps65910 *tps65910, int chip_ngpio)
-{
-        return NULL;
-}
-#endif
-
-static int tps65910_gpio_probe(struct platform_device *pdev)
-{
-        struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
-        struct tps65910_board *pdata = dev_get_platdata(tps65910->dev);
-        struct tps65910_gpio *tps65910_gpio;
-        int ret;
-        int i;
-
-        tps65910_gpio = devm_kzalloc(&pdev->dev,
-                                sizeof(*tps65910_gpio), GFP_KERNEL);
-        if (!tps65910_gpio) {
-                dev_err(&pdev->dev, "Could not allocate tps65910_gpio\n");
-                return -ENOMEM;
-        }
-
-        tps65910_gpio->tps65910 = tps65910;
-
-        tps65910_gpio->gpio_chip.owner = THIS_MODULE;
-        tps65910_gpio->gpio_chip.label = tps65910->i2c_client->name;
+        tps65910->gpio.owner            = THIS_MODULE;
+        tps65910->gpio.label            = tps65910->i2c_client->name;
+        tps65910->gpio.dev              = tps65910->dev;
+        tps65910->gpio.base             = gpio_base;
 
         switch(tps65910_chip_id(tps65910)) {
         case TPS65910:
-                tps65910_gpio->gpio_chip.ngpio = TPS65910_NUM_GPIO;
+                tps65910->gpio.ngpio    = TPS65910_NUM_GPIO;
                 break;
         case TPS65911:
-                tps65910_gpio->gpio_chip.ngpio = TPS65911_NUM_GPIO;
+                tps65910->gpio.ngpio    = TPS65911_NUM_GPIO;
                 break;
         default:
-                return -EINVAL;
-        }
-        tps65910_gpio->gpio_chip.can_sleep = 1;
-        tps65910_gpio->gpio_chip.direction_input = tps65910_gpio_input;
-        tps65910_gpio->gpio_chip.direction_output = tps65910_gpio_output;
-        tps65910_gpio->gpio_chip.set    = tps65910_gpio_set;
-        tps65910_gpio->gpio_chip.get    = tps65910_gpio_get;
-        tps65910_gpio->gpio_chip.dev = &pdev->dev;
-#ifdef CONFIG_OF_GPIO
-        tps65910_gpio->gpio_chip.of_node = tps65910->dev->of_node;
-#endif
-        if (pdata && pdata->gpio_base)
-                tps65910_gpio->gpio_chip.base = pdata->gpio_base;
-        else
-                tps65910_gpio->gpio_chip.base = -1;
-
-        if (!pdata && tps65910->dev->of_node)
-                pdata = tps65910_parse_dt_for_gpio(&pdev->dev, tps65910,
-                        tps65910_gpio->gpio_chip.ngpio);
-
-        if (!pdata)
-                goto skip_init;
-
-        /* Configure sleep control for gpios if provided */
-        for (i = 0; i < tps65910_gpio->gpio_chip.ngpio; ++i) {
-                if (!pdata->en_gpio_sleep[i])
-                        continue;
-
-                ret = tps65910_reg_set_bits(tps65910,
-                        TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
-                if (ret < 0)
-                        dev_warn(tps65910->dev,
-                                "GPIO Sleep setting failed with err %d\n", ret);
+                return;
         }
-
-skip_init:
-        ret = gpiochip_add(&tps65910_gpio->gpio_chip);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                return ret;
+        tps65910->gpio.can_sleep        = 1;
+
+        tps65910->gpio.direction_input  = tps65910_gpio_input;
+        tps65910->gpio.direction_output = tps65910_gpio_output;
+        tps65910->gpio.set              = tps65910_gpio_set;
+        tps65910->gpio.get              = tps65910_gpio_get;
+
+        /* Configure sleep control for gpios */
+        board_data = dev_get_platdata(tps65910->dev);
+        if (board_data) {
+                int i;
+                for (i = 0; i < tps65910->gpio.ngpio; ++i) {
+                        if (board_data->en_gpio_sleep[i]) {
+                                ret = tps65910_set_bits(tps65910,
+                                        TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
+                                if (ret < 0)
+                                        dev_warn(tps65910->dev,
+                                                "GPIO Sleep setting failed\n");
+                        }
+                }
         }
 
-        platform_set_drvdata(pdev, tps65910_gpio);
-
-        return ret;
-}
-
-static int tps65910_gpio_remove(struct platform_device *pdev)
-{
-        struct tps65910_gpio *tps65910_gpio = platform_get_drvdata(pdev);
+        ret = gpiochip_add(&tps65910->gpio);
 
-        return gpiochip_remove(&tps65910_gpio->gpio_chip);
+        if (ret)
+                dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret);
 }
-
-static struct platform_driver tps65910_gpio_driver = {
-        .driver.name    = "tps65910-gpio",
-        .driver.owner   = THIS_MODULE,
-        .probe          = tps65910_gpio_probe,
-        .remove         = tps65910_gpio_remove,
-};
-
-static int __init tps65910_gpio_init(void)
-{
-        return platform_driver_register(&tps65910_gpio_driver);
-}
-subsys_initcall(tps65910_gpio_init);
-
-static void __exit tps65910_gpio_exit(void)
-{
-        platform_driver_unregister(&tps65910_gpio_driver);
-}
-module_exit(tps65910_gpio_exit);
-
-MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
-MODULE_AUTHOR("Jorge Eduardo Candelaria jedu@slimlogic.co.uk>");
-MODULE_DESCRIPTION("GPIO interface for TPS65910/TPS6511 PMICs");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:tps65910-gpio");
diff --git a/drivers/gpio/gpio-tps65912.c b/drivers/gpio/gpio-tps65912.c
index 30a5844a7dc..79e66c00235 100644
--- a/drivers/gpio/gpio-tps65912.c
+++ b/drivers/gpio/gpio-tps65912.c
@@ -70,6 +70,7 @@ static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset)
 
         return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset,
                                                                 GPIO_CFG_MASK);
+
 }
 
 static struct gpio_chip template_chip = {
@@ -84,15 +85,14 @@ static struct gpio_chip template_chip = {
         .base                   = -1,
 };
 
-static int tps65912_gpio_probe(struct platform_device *pdev)
+static int __devinit tps65912_gpio_probe(struct platform_device *pdev)
 {
         struct tps65912 *tps65912 = dev_get_drvdata(pdev->dev.parent);
         struct tps65912_board *pdata = tps65912->dev->platform_data;
         struct tps65912_gpio_data *tps65912_gpio;
         int ret;
 
-        tps65912_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps65912_gpio),
-                                     GFP_KERNEL);
+        tps65912_gpio = kzalloc(sizeof(*tps65912_gpio), GFP_KERNEL);
         if (tps65912_gpio == NULL)
                 return -ENOMEM;
 
@@ -105,19 +105,28 @@ static int tps65912_gpio_probe(struct platform_device *pdev)
         ret = gpiochip_add(&tps65912_gpio->gpio_chip);
         if (ret < 0) {
                 dev_err(&pdev->dev, "Failed to register gpiochip, %d\n", ret);
-                return ret;
+                goto err;
         }
 
         platform_set_drvdata(pdev, tps65912_gpio);
 
         return ret;
+
+err:
+        kfree(tps65912_gpio);
+        return ret;
 }
 
-static int tps65912_gpio_remove(struct platform_device *pdev)
+static int __devexit tps65912_gpio_remove(struct platform_device *pdev)
 {
         struct tps65912_gpio_data  *tps65912_gpio = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = gpiochip_remove(&tps65912_gpio->gpio_chip);
+        if (ret == 0)
+                kfree(tps65912_gpio);
 
-        return gpiochip_remove(&tps65912_gpio->gpio_chip);
+        return ret;
 }
 
 static struct platform_driver tps65912_gpio_driver = {
@@ -126,7 +135,7 @@ static struct platform_driver tps65912_gpio_driver = {
                 .owner = THIS_MODULE,
         },
         .probe = tps65912_gpio_probe,
-        .remove = tps65912_gpio_remove,
+        .remove = __devexit_p(tps65912_gpio_remove),
 };
 
 static int __init tps65912_gpio_init(void)
diff --git a/drivers/gpio/gpio-ts5500.c b/drivers/gpio/gpio-ts5500.c
deleted file mode 100644
index cc53cab8df2..00000000000
--- a/drivers/gpio/gpio-ts5500.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/*
- * Digital I/O driver for Technologic Systems TS-5500
- *
- * Copyright (c) 2012 Savoir-faire Linux Inc.
- *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
- *
- * Technologic Systems platforms have pin blocks, exposing several Digital
- * Input/Output lines (DIO). This driver aims to support single pin blocks.
- * In that sense, the support is not limited to the TS-5500 blocks.
- * Actually, the following platforms have DIO support:
- *
- * TS-5500:
- *   Documentation: http://wiki.embeddedarm.com/wiki/TS-5500
- *   Blocks: DIO1, DIO2 and LCD port.
- *
- * TS-5600:
- *   Documentation: http://wiki.embeddedarm.com/wiki/TS-5600
- *   Blocks: LCD port (identical to TS-5500 LCD).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/bitops.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_data/gpio-ts5500.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-/* List of supported Technologic Systems platforms DIO blocks */
-enum ts5500_blocks { TS5500_DIO1, TS5500_DIO2, TS5500_LCD, TS5600_LCD };
-
-struct ts5500_priv {
-        const struct ts5500_dio *pinout;
-        struct gpio_chip gpio_chip;
-        spinlock_t lock;
-        bool strap;
-        u8 hwirq;
-};
-
-/*
- * Hex 7D is used to control several blocks (e.g. DIO2 and LCD port).
- * This flag ensures that the region has been requested by this driver.
- */
-static bool hex7d_reserved;
-
-/*
- * This structure is used to describe capabilities of DIO lines,
- * such as available directions and connected interrupt (if any).
- */
-struct ts5500_dio {
-        const u8 value_addr;
-        const u8 value_mask;
-        const u8 control_addr;
-        const u8 control_mask;
-        const bool no_input;
-        const bool no_output;
-        const u8 irq;
-};
-
-#define TS5500_DIO_IN_OUT(vaddr, vbit, caddr, cbit)     \
-        {                                               \
-                .value_addr = vaddr,                    \
-                .value_mask = BIT(vbit),                \
-                .control_addr = caddr,                  \
-                .control_mask = BIT(cbit),              \
-        }
-
-#define TS5500_DIO_IN(addr, bit)                \
-        {                                       \
-                .value_addr = addr,             \
-                .value_mask = BIT(bit),         \
-                .no_output = true,              \
-        }
-
-#define TS5500_DIO_IN_IRQ(addr, bit, _irq)      \
-        {                                       \
-                .value_addr = addr,             \
-                .value_mask = BIT(bit),         \
-                .no_output = true,              \
-                .irq = _irq,                    \
-        }
-
-#define TS5500_DIO_OUT(addr, bit)               \
-        {                                       \
-                .value_addr = addr,             \
-                .value_mask = BIT(bit),         \
-                .no_input = true,               \
-        }
-
-/*
- * Input/Output DIO lines are programmed in groups of 4. Their values are
- * available through 4 consecutive bits in a value port, whereas the direction
- * of these 4 lines is driven by only 1 bit in a control port.
- */
-#define TS5500_DIO_GROUP(vaddr, vbitfrom, caddr, cbit)          \
-        TS5500_DIO_IN_OUT(vaddr, vbitfrom + 0, caddr, cbit),    \
-        TS5500_DIO_IN_OUT(vaddr, vbitfrom + 1, caddr, cbit),    \
-        TS5500_DIO_IN_OUT(vaddr, vbitfrom + 2, caddr, cbit),    \
-        TS5500_DIO_IN_OUT(vaddr, vbitfrom + 3, caddr, cbit)
-
-/*
- * TS-5500 DIO1 block
- *
- *  value    control  dir    hw
- *  addr bit addr bit in out irq name     pin offset
- *
- *  0x7b  0  0x7a  0  x   x      DIO1_0   1   0
- *  0x7b  1  0x7a  0  x   x      DIO1_1   3   1
- *  0x7b  2  0x7a  0  x   x      DIO1_2   5   2
- *  0x7b  3  0x7a  0  x   x      DIO1_3   7   3
- *  0x7b  4  0x7a  1  x   x      DIO1_4   9   4
- *  0x7b  5  0x7a  1  x   x      DIO1_5   11  5
- *  0x7b  6  0x7a  1  x   x      DIO1_6   13  6
- *  0x7b  7  0x7a  1  x   x      DIO1_7   15  7
- *  0x7c  0  0x7a  5  x   x      DIO1_8   4   8
- *  0x7c  1  0x7a  5  x   x      DIO1_9   6   9
- *  0x7c  2  0x7a  5  x   x      DIO1_10  8   10
- *  0x7c  3  0x7a  5  x   x      DIO1_11  10  11
- *  0x7c  4           x          DIO1_12  12  12
- *  0x7c  5           x      7   DIO1_13  14  13
- */
-static const struct ts5500_dio ts5500_dio1[] = {
-        TS5500_DIO_GROUP(0x7b, 0, 0x7a, 0),
-        TS5500_DIO_GROUP(0x7b, 4, 0x7a, 1),
-        TS5500_DIO_GROUP(0x7c, 0, 0x7a, 5),
-        TS5500_DIO_IN(0x7c, 4),
-        TS5500_DIO_IN_IRQ(0x7c, 5, 7),
-};
-
-/*
- * TS-5500 DIO2 block
- *
- *  value    control  dir    hw
- *  addr bit addr bit in out irq name     pin offset
- *
- *  0x7e  0  0x7d  0  x   x      DIO2_0   1   0
- *  0x7e  1  0x7d  0  x   x      DIO2_1   3   1
- *  0x7e  2  0x7d  0  x   x      DIO2_2   5   2
- *  0x7e  3  0x7d  0  x   x      DIO2_3   7   3
- *  0x7e  4  0x7d  1  x   x      DIO2_4   9   4
- *  0x7e  5  0x7d  1  x   x      DIO2_5   11  5
- *  0x7e  6  0x7d  1  x   x      DIO2_6   13  6
- *  0x7e  7  0x7d  1  x   x      DIO2_7   15  7
- *  0x7f  0  0x7d  5  x   x      DIO2_8   4   8
- *  0x7f  1  0x7d  5  x   x      DIO2_9   6   9
- *  0x7f  2  0x7d  5  x   x      DIO2_10  8   10
- *  0x7f  3  0x7d  5  x   x      DIO2_11  10  11
- *  0x7f  4           x      6   DIO2_13  14  12
- */
-static const struct ts5500_dio ts5500_dio2[] = {
-        TS5500_DIO_GROUP(0x7e, 0, 0x7d, 0),
-        TS5500_DIO_GROUP(0x7e, 4, 0x7d, 1),
-        TS5500_DIO_GROUP(0x7f, 0, 0x7d, 5),
-        TS5500_DIO_IN_IRQ(0x7f, 4, 6),
-};
-
-/*
- * TS-5500 LCD port used as DIO block
- * TS-5600 LCD port is identical
- *
- *  value    control  dir    hw
- *  addr bit addr bit in out irq name    pin offset
- *
- *  0x72  0  0x7d  2  x   x      LCD_0   8   0
- *  0x72  1  0x7d  2  x   x      LCD_1   7   1
- *  0x72  2  0x7d  2  x   x      LCD_2   10  2
- *  0x72  3  0x7d  2  x   x      LCD_3   9   3
- *  0x72  4  0x7d  3  x   x      LCD_4   12  4
- *  0x72  5  0x7d  3  x   x      LCD_5   11  5
- *  0x72  6  0x7d  3  x   x      LCD_6   14  6
- *  0x72  7  0x7d  3  x   x      LCD_7   13  7
- *  0x73  0               x      LCD_EN  5   8
- *  0x73  6           x          LCD_WR  6   9
- *  0x73  7           x      1   LCD_RS  3   10
- */
-static const struct ts5500_dio ts5500_lcd[] = {
-        TS5500_DIO_GROUP(0x72, 0, 0x7d, 2),
-        TS5500_DIO_GROUP(0x72, 4, 0x7d, 3),
-        TS5500_DIO_OUT(0x73, 0),
-        TS5500_DIO_IN(0x73, 6),
-        TS5500_DIO_IN_IRQ(0x73, 7, 1),
-};
-
-static inline struct ts5500_priv *ts5500_gc_to_priv(struct gpio_chip *chip)
-{
-        return container_of(chip, struct ts5500_priv, gpio_chip);
-}
-
-static inline void ts5500_set_mask(u8 mask, u8 addr)
-{
-        u8 val = inb(addr);
-        val |= mask;
-        outb(val, addr);
-}
-
-static inline void ts5500_clear_mask(u8 mask, u8 addr)
-{
-        u8 val = inb(addr);
-        val &= ~mask;
-        outb(val, addr);
-}
-
-static int ts5500_gpio_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct ts5500_priv *priv = ts5500_gc_to_priv(chip);
-        const struct ts5500_dio line = priv->pinout[offset];
-        unsigned long flags;
-
-        if (line.no_input)
-                return -ENXIO;
-
-        if (line.no_output)
-                return 0;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        ts5500_clear_mask(line.control_mask, line.control_addr);
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        return 0;
-}
-
-static int ts5500_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct ts5500_priv *priv = ts5500_gc_to_priv(chip);
-        const struct ts5500_dio line = priv->pinout[offset];
-
-        return !!(inb(line.value_addr) & line.value_mask);
-}
-
-static int ts5500_gpio_output(struct gpio_chip *chip, unsigned offset, int val)
-{
-        struct ts5500_priv *priv = ts5500_gc_to_priv(chip);
-        const struct ts5500_dio line = priv->pinout[offset];
-        unsigned long flags;
-
-        if (line.no_output)
-                return -ENXIO;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        if (!line.no_input)
-                ts5500_set_mask(line.control_mask, line.control_addr);
-
-        if (val)
-                ts5500_set_mask(line.value_mask, line.value_addr);
-        else
-                ts5500_clear_mask(line.value_mask, line.value_addr);
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        return 0;
-}
-
-static void ts5500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-        struct ts5500_priv *priv = ts5500_gc_to_priv(chip);
-        const struct ts5500_dio line = priv->pinout[offset];
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        if (val)
-                ts5500_set_mask(line.value_mask, line.value_addr);
-        else
-                ts5500_clear_mask(line.value_mask, line.value_addr);
-        spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static int ts5500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct ts5500_priv *priv = ts5500_gc_to_priv(chip);
-        const struct ts5500_dio *block = priv->pinout;
-        const struct ts5500_dio line = block[offset];
-
-        /* Only one pin is connected to an interrupt */
-        if (line.irq)
-                return line.irq;
-
-        /* As this pin is input-only, we may strap it to another in/out pin */
-        if (priv->strap)
-                return priv->hwirq;
-
-        return -ENXIO;
-}
-
-static int ts5500_enable_irq(struct ts5500_priv *priv)
-{
-        int ret = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        if (priv->hwirq == 7)
-                ts5500_set_mask(BIT(7), 0x7a); /* DIO1_13 on IRQ7 */
-        else if (priv->hwirq == 6)
-                ts5500_set_mask(BIT(7), 0x7d); /* DIO2_13 on IRQ6 */
-        else if (priv->hwirq == 1)
-                ts5500_set_mask(BIT(6), 0x7d); /* LCD_RS on IRQ1 */
-        else
-                ret = -EINVAL;
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        return ret;
-}
-
-static void ts5500_disable_irq(struct ts5500_priv *priv)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        if (priv->hwirq == 7)
-                ts5500_clear_mask(BIT(7), 0x7a); /* DIO1_13 on IRQ7 */
-        else if (priv->hwirq == 6)
-                ts5500_clear_mask(BIT(7), 0x7d); /* DIO2_13 on IRQ6 */
-        else if (priv->hwirq == 1)
-                ts5500_clear_mask(BIT(6), 0x7d); /* LCD_RS on IRQ1 */
-        else
-                dev_err(priv->gpio_chip.dev, "invalid hwirq %d\n", priv->hwirq);
-        spin_unlock_irqrestore(&priv->lock, flags);
-}
-
-static int ts5500_dio_probe(struct platform_device *pdev)
-{
-        enum ts5500_blocks block = platform_get_device_id(pdev)->driver_data;
-        struct ts5500_dio_platform_data *pdata = pdev->dev.platform_data;
-        struct device *dev = &pdev->dev;
-        const char *name = dev_name(dev);
-        struct ts5500_priv *priv;
-        struct resource *res;
-        unsigned long flags;
-        int ret;
-
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (!res) {
-                dev_err(dev, "missing IRQ resource\n");
-                return -EINVAL;
-        }
-
-        priv = devm_kzalloc(dev, sizeof(struct ts5500_priv), GFP_KERNEL);
-        if (!priv)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, priv);
-        priv->hwirq = res->start;
-        spin_lock_init(&priv->lock);
-
-        priv->gpio_chip.owner = THIS_MODULE;
-        priv->gpio_chip.label = name;
-        priv->gpio_chip.dev = dev;
-        priv->gpio_chip.direction_input = ts5500_gpio_input;
-        priv->gpio_chip.direction_output = ts5500_gpio_output;
-        priv->gpio_chip.get = ts5500_gpio_get;
-        priv->gpio_chip.set = ts5500_gpio_set;
-        priv->gpio_chip.to_irq = ts5500_gpio_to_irq;
-        priv->gpio_chip.base = -1;
-        if (pdata) {
-                priv->gpio_chip.base = pdata->base;
-                priv->strap = pdata->strap;
-        }
-
-        switch (block) {
-        case TS5500_DIO1:
-                priv->pinout = ts5500_dio1;
-                priv->gpio_chip.ngpio = ARRAY_SIZE(ts5500_dio1);
-
-                if (!devm_request_region(dev, 0x7a, 3, name)) {
-                        dev_err(dev, "failed to request %s ports\n", name);
-                        return -EBUSY;
-                }
-                break;
-        case TS5500_DIO2:
-                priv->pinout = ts5500_dio2;
-                priv->gpio_chip.ngpio = ARRAY_SIZE(ts5500_dio2);
-
-                if (!devm_request_region(dev, 0x7e, 2, name)) {
-                        dev_err(dev, "failed to request %s ports\n", name);
-                        return -EBUSY;
-                }
-
-                if (hex7d_reserved)
-                        break;
-
-                if (!devm_request_region(dev, 0x7d, 1, name)) {
-                        dev_err(dev, "failed to request %s 7D\n", name);
-                        return -EBUSY;
-                }
-
-                hex7d_reserved = true;
-                break;
-        case TS5500_LCD:
-        case TS5600_LCD:
-                priv->pinout = ts5500_lcd;
-                priv->gpio_chip.ngpio = ARRAY_SIZE(ts5500_lcd);
-
-                if (!devm_request_region(dev, 0x72, 2, name)) {
-                        dev_err(dev, "failed to request %s ports\n", name);
-                        return -EBUSY;
-                }
-
-                if (!hex7d_reserved) {
-                        if (!devm_request_region(dev, 0x7d, 1, name)) {
-                                dev_err(dev, "failed to request %s 7D\n", name);
-                                return -EBUSY;
-                        }
-
-                        hex7d_reserved = true;
-                }
-
-                /* Ensure usage of LCD port as DIO */
-                spin_lock_irqsave(&priv->lock, flags);
-                ts5500_clear_mask(BIT(4), 0x7d);
-                spin_unlock_irqrestore(&priv->lock, flags);
-                break;
-        }
-
-        ret = gpiochip_add(&priv->gpio_chip);
-        if (ret) {
-                dev_err(dev, "failed to register the gpio chip\n");
-                return ret;
-        }
-
-        ret = ts5500_enable_irq(priv);
-        if (ret) {
-                dev_err(dev, "invalid interrupt %d\n", priv->hwirq);
-                goto cleanup;
-        }
-
-        return 0;
-cleanup:
-        if (gpiochip_remove(&priv->gpio_chip))
-                dev_err(dev, "failed to remove gpio chip\n");
-        return ret;
-}
-
-static int ts5500_dio_remove(struct platform_device *pdev)
-{
-        struct ts5500_priv *priv = platform_get_drvdata(pdev);
-
-        ts5500_disable_irq(priv);
-        return gpiochip_remove(&priv->gpio_chip);
-}
-
-static struct platform_device_id ts5500_dio_ids[] = {
-        { "ts5500-dio1", TS5500_DIO1 },
-        { "ts5500-dio2", TS5500_DIO2 },
-        { "ts5500-dio-lcd", TS5500_LCD },
-        { "ts5600-dio-lcd", TS5600_LCD },
-        { }
-};
-MODULE_DEVICE_TABLE(platform, ts5500_dio_ids);
-
-static struct platform_driver ts5500_dio_driver = {
-        .driver = {
-                .name = "ts5500-dio",
-                .owner = THIS_MODULE,
-        },
-        .probe = ts5500_dio_probe,
-        .remove = ts5500_dio_remove,
-        .id_table = ts5500_dio_ids,
-};
-
-module_platform_driver(ts5500_dio_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Savoir-faire Linux Inc. <kernel@savoirfairelinux.com>");
-MODULE_DESCRIPTION("Technologic Systems TS-5500 Digital I/O driver");
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 9572aa137e6..b8b4f228757 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -32,8 +32,6 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/irqdomain.h>
 
 #include <linux/i2c/twl.h>
 
@@ -51,7 +49,6 @@
 
 
 static struct gpio_chip twl_gpiochip;
-static int twl4030_gpio_base;
 static int twl4030_gpio_irq_base;
 
 /* genirq interfaces are not available to modules */
@@ -88,15 +85,11 @@ static inline int gpio_twl4030_write(u8 address, u8 data)
 /*----------------------------------------------------------------------*/
 
 /*
- * LED register offsets from TWL_MODULE_LED base
+ * LED register offsets (use TWL4030_MODULE_{LED,PWMA,PWMB}))
  * PWMs A and B are dedicated to LEDs A and B, respectively.
  */
 
-#define TWL4030_LED_LEDEN_REG   0x00
-#define TWL4030_PWMAON_REG      0x01
-#define TWL4030_PWMAOFF_REG     0x02
-#define TWL4030_PWMBON_REG      0x03
-#define TWL4030_PWMBOFF_REG     0x04
+#define TWL4030_LED_LEDEN       0x0
 
 /* LEDEN bits */
 #define LEDEN_LEDAON            BIT(0)
@@ -108,6 +101,9 @@ static inline int gpio_twl4030_write(u8 address, u8 data)
 #define LEDEN_PWM_LENGTHA       BIT(6)
 #define LEDEN_PWM_LENGTHB       BIT(7)
 
+#define TWL4030_PWMx_PWMxON     0x0
+#define TWL4030_PWMx_PWMxOFF    0x1
+
 #define PWMxON_LENGTH           BIT(7)
 
 /*----------------------------------------------------------------------*/
@@ -146,7 +142,7 @@ static void twl4030_led_set_value(int led, int value)
         else
                 cached_leden |= mask;
         status = twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
-                                  TWL4030_LED_LEDEN_REG);
+                        TWL4030_LED_LEDEN);
         mutex_unlock(&gpio_lock);
 }
 
@@ -217,33 +213,33 @@ static int twl_request(struct gpio_chip *chip, unsigned offset)
         if (offset >= TWL4030_GPIO_MAX) {
                 u8      ledclr_mask = LEDEN_LEDAON | LEDEN_LEDAEXT
                                 | LEDEN_LEDAPWM | LEDEN_PWM_LENGTHA;
-                u8      reg = TWL4030_PWMAON_REG;
+                u8      module = TWL4030_MODULE_PWMA;
 
                 offset -= TWL4030_GPIO_MAX;
                 if (offset) {
                         ledclr_mask <<= 1;
-                        reg = TWL4030_PWMBON_REG;
+                        module = TWL4030_MODULE_PWMB;
                 }
 
                 /* initialize PWM to always-drive */
-                /* Configure PWM OFF register first */
-                status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg + 1);
+                status = twl_i2c_write_u8(module, 0x7f,
+                                TWL4030_PWMx_PWMxOFF);
                 if (status < 0)
                         goto done;
-
-                /* Followed by PWM ON register */
-                status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg);
+                status = twl_i2c_write_u8(module, 0x7f,
+                                TWL4030_PWMx_PWMxON);
                 if (status < 0)
                         goto done;
 
                 /* init LED to not-driven (high) */
-                status = twl_i2c_read_u8(TWL4030_MODULE_LED, &cached_leden,
-                                         TWL4030_LED_LEDEN_REG);
+                module = TWL4030_MODULE_LED;
+                status = twl_i2c_read_u8(module, &cached_leden,
+                                TWL4030_LED_LEDEN);
                 if (status < 0)
                         goto done;
                 cached_leden &= ~ledclr_mask;
-                status = twl_i2c_write_u8(TWL4030_MODULE_LED, cached_leden,
-                                          TWL4030_LED_LEDEN_REG);
+                status = twl_i2c_write_u8(module, cached_leden,
+                                TWL4030_LED_LEDEN);
                 if (status < 0)
                         goto done;
 
@@ -260,8 +256,7 @@ static int twl_request(struct gpio_chip *chip, unsigned offset)
                  * and vMMC2 power supplies based on card presence.
                  */
                 pdata = chip->dev->platform_data;
-                if (pdata)
-                        value |= pdata->mmc_cd & 0x03;
+                value |= pdata->mmc_cd & 0x03;
 
                 status = gpio_twl4030_write(REG_GPIO_CTRL, value);
         }
@@ -353,15 +348,15 @@ static struct gpio_chip twl_gpiochip = {
 
 /*----------------------------------------------------------------------*/
 
-static int gpio_twl4030_pulls(u32 ups, u32 downs)
+static int __devinit gpio_twl4030_pulls(u32 ups, u32 downs)
 {
-        u8              message[5];
+        u8              message[6];
         unsigned        i, gpio_bit;
 
         /* For most pins, a pulldown was enabled by default.
          * We should have data that's specific to this board.
          */
-        for (gpio_bit = 1, i = 0; i < 5; i++) {
+        for (gpio_bit = 1, i = 1; i < 6; i++) {
                 u8              bit_mask;
                 unsigned        j;
 
@@ -378,18 +373,18 @@ static int gpio_twl4030_pulls(u32 ups, u32 downs)
                                 REG_GPIOPUPDCTR1, 5);
 }
 
-static int gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
+static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
 {
-        u8              message[3];
+        u8              message[4];
 
         /* 30 msec of debouncing is always used for MMC card detect,
          * and is optional for everything else.
          */
-        message[0] = (debounce & 0xff) | (mmc_cd & 0x03);
+        message[1] = (debounce & 0xff) | (mmc_cd & 0x03);
         debounce >>= 8;
-        message[1] = (debounce & 0xff);
+        message[2] = (debounce & 0xff);
         debounce >>= 8;
-        message[2] = (debounce & 0x03);
+        message[3] = (debounce & 0x03);
 
         return twl_i2c_write(TWL4030_MODULE_GPIO, message,
                                 REG_GPIO_DEBEN1, 3);
@@ -397,69 +392,26 @@ static int gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
 
 static int gpio_twl4030_remove(struct platform_device *pdev);
 
-static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
-{
-        struct twl4030_gpio_platform_data *omap_twl_info;
-
-        omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
-        if (!omap_twl_info)
-                return NULL;
-
-        omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
-                        "ti,use-leds");
-
-        of_property_read_u32(dev->of_node, "ti,debounce",
-                             &omap_twl_info->debounce);
-        of_property_read_u32(dev->of_node, "ti,mmc-cd",
-                             (u32 *)&omap_twl_info->mmc_cd);
-        of_property_read_u32(dev->of_node, "ti,pullups",
-                             &omap_twl_info->pullups);
-        of_property_read_u32(dev->of_node, "ti,pulldowns",
-                             &omap_twl_info->pulldowns);
-
-        return omap_twl_info;
-}
-
-static int gpio_twl4030_probe(struct platform_device *pdev)
+static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
         struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
-        struct device_node *node = pdev->dev.of_node;
-        int ret, irq_base;
+        int ret;
 
         /* maybe setup IRQs */
-        if (is_module()) {
-                dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
-                goto no_irqs;
-        }
-
-        irq_base = irq_alloc_descs(-1, 0, TWL4030_GPIO_MAX, 0);
-        if (irq_base < 0) {
-                dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
-                return irq_base;
+        if (pdata->irq_base) {
+                if (is_module()) {
+                        dev_err(&pdev->dev,
+                                "can't dispatch IRQs from modules\n");
+                        goto no_irqs;
+                }
+                ret = twl4030_sih_setup(TWL4030_MODULE_GPIO);
+                if (ret < 0)
+                        return ret;
+                WARN_ON(ret != pdata->irq_base);
+                twl4030_gpio_irq_base = ret;
         }
 
-        irq_domain_add_legacy(node, TWL4030_GPIO_MAX, irq_base, 0,
-                              &irq_domain_simple_ops, NULL);
-
-        ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
-        if (ret < 0)
-                return ret;
-
-        twl4030_gpio_irq_base = irq_base;
-
 no_irqs:
-        twl_gpiochip.base = -1;
-        twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
-        twl_gpiochip.dev = &pdev->dev;
-
-        if (node)
-                pdata = of_gpio_twl4030(&pdev->dev);
-
-        if (pdata == NULL) {
-                dev_err(&pdev->dev, "Platform data is missing\n");
-                return -ENXIO;
-        }
-
         /*
          * NOTE:  boards may waste power if they don't set pullups
          * and pulldowns correctly ... default for non-ULPI pins is
@@ -469,15 +421,20 @@ no_irqs:
         ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
         if (ret)
                 dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
-                        pdata->pullups, pdata->pulldowns, ret);
+                                pdata->pullups, pdata->pulldowns,
+                                ret);
 
         ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
         if (ret)
                 dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
-                        pdata->debounce, pdata->mmc_cd, ret);
+                                pdata->debounce, pdata->mmc_cd,
+                                ret);
 
-        /*
-         * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
+        twl_gpiochip.base = pdata->gpio_base;
+        twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
+        twl_gpiochip.dev = &pdev->dev;
+
+        /* NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
          * is (still) clear if use_leds is set.
          */
         if (pdata->use_leds)
@@ -485,36 +442,32 @@ no_irqs:
 
         ret = gpiochip_add(&twl_gpiochip);
         if (ret < 0) {
-                dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
+                dev_err(&pdev->dev,
+                                "could not register gpiochip, %d\n",
+                                ret);
                 twl_gpiochip.ngpio = 0;
                 gpio_twl4030_remove(pdev);
-                goto out;
-        }
-
-        twl4030_gpio_base = twl_gpiochip.base;
-
-        if (pdata && pdata->setup) {
+        } else if (pdata->setup) {
                 int status;
 
                 status = pdata->setup(&pdev->dev,
-                                twl4030_gpio_base, TWL4030_GPIO_MAX);
+                                pdata->gpio_base, TWL4030_GPIO_MAX);
                 if (status)
                         dev_dbg(&pdev->dev, "setup --> %d\n", status);
         }
 
-out:
         return ret;
 }
 
-/* Cannot use as gpio_twl4030_probe() calls us */
+/* Cannot use __devexit as gpio_twl4030_probe() calls us */
 static int gpio_twl4030_remove(struct platform_device *pdev)
 {
         struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
         int status;
 
-        if (pdata && pdata->teardown) {
+        if (pdata->teardown) {
                 status = pdata->teardown(&pdev->dev,
-                                twl4030_gpio_base, TWL4030_GPIO_MAX);
+                                pdata->gpio_base, TWL4030_GPIO_MAX);
                 if (status) {
                         dev_dbg(&pdev->dev, "teardown --> %d\n", status);
                         return status;
@@ -533,21 +486,12 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
         return -EIO;
 }
 
-static const struct of_device_id twl_gpio_match[] = {
-        { .compatible = "ti,twl4030-gpio", },
-        { },
-};
-MODULE_DEVICE_TABLE(of, twl_gpio_match);
-
 /* Note:  this hardware lives inside an I2C-based multi-function device. */
 MODULE_ALIAS("platform:twl4030_gpio");
 
 static struct platform_driver gpio_twl4030_driver = {
-        .driver = {
-                .name   = "twl4030_gpio",
-                .owner  = THIS_MODULE,
-                .of_match_table = of_match_ptr(twl_gpio_match),
-        },
+        .driver.name    = "twl4030_gpio",
+        .driver.owner   = THIS_MODULE,
         .probe          = gpio_twl4030_probe,
         .remove         = gpio_twl4030_remove,
 };
diff --git a/drivers/gpio/gpio-twl6040.c b/drivers/gpio/gpio-twl6040.c
deleted file mode 100644
index 0be82c6dd79..00000000000
--- a/drivers/gpio/gpio-twl6040.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Access to GPOs on TWL6040 chip
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- *
- * Authors:
- *      Sergio Aguirre <saaguirre@ti.com>
- *      Peter Ujfalusi <peter.ujfalusi@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kthread.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-
-#include <linux/mfd/twl6040.h>
-
-static struct gpio_chip twl6040gpo_chip;
-
-static int twl6040gpo_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct twl6040 *twl6040 = dev_get_drvdata(chip->dev->parent);
-        int ret = 0;
-
-        ret = twl6040_reg_read(twl6040, TWL6040_REG_GPOCTL);
-        if (ret < 0)
-                return ret;
-
-        return (ret >> offset) & 1;
-}
-
-static int twl6040gpo_direction_out(struct gpio_chip *chip, unsigned offset,
-                                    int value)
-{
-        /* This only drives GPOs, and can't change direction */
-        return 0;
-}
-
-static void twl6040gpo_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct twl6040 *twl6040 = dev_get_drvdata(chip->dev->parent);
-        int ret;
-        u8 gpoctl;
-
-        ret = twl6040_reg_read(twl6040, TWL6040_REG_GPOCTL);
-        if (ret < 0)
-                return;
-
-        if (value)
-                gpoctl = ret | (1 << offset);
-        else
-                gpoctl = ret & ~(1 << offset);
-
-        twl6040_reg_write(twl6040, TWL6040_REG_GPOCTL, gpoctl);
-}
-
-static struct gpio_chip twl6040gpo_chip = {
-        .label                  = "twl6040",
-        .owner                  = THIS_MODULE,
-        .get                    = twl6040gpo_get,
-        .direction_output       = twl6040gpo_direction_out,
-        .set                    = twl6040gpo_set,
-        .can_sleep              = 1,
-};
-
-/*----------------------------------------------------------------------*/
-
-static int gpo_twl6040_probe(struct platform_device *pdev)
-{
-        struct twl6040_gpo_data *pdata = pdev->dev.platform_data;
-        struct device *twl6040_core_dev = pdev->dev.parent;
-        struct twl6040 *twl6040 = dev_get_drvdata(twl6040_core_dev);
-        int ret;
-
-        if (pdata)
-                twl6040gpo_chip.base = pdata->gpio_base;
-        else
-                twl6040gpo_chip.base = -1;
-
-        if (twl6040_get_revid(twl6040) < TWL6041_REV_ES2_0)
-                twl6040gpo_chip.ngpio = 3; /* twl6040 have 3 GPO */
-        else
-                twl6040gpo_chip.ngpio = 1; /* twl6041 have 1 GPO */
-
-        twl6040gpo_chip.dev = &pdev->dev;
-#ifdef CONFIG_OF_GPIO
-        twl6040gpo_chip.of_node = twl6040_core_dev->of_node;
-#endif
-
-        ret = gpiochip_add(&twl6040gpo_chip);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
-                twl6040gpo_chip.ngpio = 0;
-        }
-
-        return ret;
-}
-
-static int gpo_twl6040_remove(struct platform_device *pdev)
-{
-        return gpiochip_remove(&twl6040gpo_chip);
-}
-
-/* Note:  this hardware lives inside an I2C-based multi-function device. */
-MODULE_ALIAS("platform:twl6040-gpo");
-
-static struct platform_driver gpo_twl6040_driver = {
-        .driver = {
-                .name   = "twl6040-gpo",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = gpo_twl6040_probe,
-        .remove         = gpo_twl6040_remove,
-};
-
-module_platform_driver(gpo_twl6040_driver);
-
-MODULE_AUTHOR("Texas Instruments, Inc.");
-MODULE_DESCRIPTION("GPO interface for TWL6040");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-ucb1400.c b/drivers/gpio/gpio-ucb1400.c
index 26405efe0f9..50e6bd1392c 100644
--- a/drivers/gpio/gpio-ucb1400.c
+++ b/drivers/gpio/gpio-ucb1400.c
@@ -103,12 +103,23 @@ static struct platform_driver ucb1400_gpio_driver = {
         },
 };
 
+static int __init ucb1400_gpio_init(void)
+{
+        return platform_driver_register(&ucb1400_gpio_driver);
+}
+
+static void __exit ucb1400_gpio_exit(void)
+{
+        platform_driver_unregister(&ucb1400_gpio_driver);
+}
+
 void __init ucb1400_gpio_set_data(struct ucb1400_gpio_data *data)
 {
         ucbdata = data;
 }
 
-module_platform_driver(ucb1400_gpio_driver);
+module_init(ucb1400_gpio_init);
+module_exit(ucb1400_gpio_exit);
 
 MODULE_DESCRIPTION("Philips UCB1400 GPIO driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-viperboard.c b/drivers/gpio/gpio-viperboard.c
deleted file mode 100644
index 59d72391de2..00000000000
--- a/drivers/gpio/gpio-viperboard.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- *  Nano River Technologies viperboard GPIO lib driver
- *
- *  (C) 2012 by Lemonage GmbH
- *  Author: Lars Poeschel <poeschel@lemonage.de>
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-
-#include <linux/usb.h>
-#include <linux/gpio.h>
-
-#include <linux/mfd/viperboard.h>
-
-#define VPRBRD_GPIOA_CLK_1MHZ           0
-#define VPRBRD_GPIOA_CLK_100KHZ         1
-#define VPRBRD_GPIOA_CLK_10KHZ          2
-#define VPRBRD_GPIOA_CLK_1KHZ           3
-#define VPRBRD_GPIOA_CLK_100HZ          4
-#define VPRBRD_GPIOA_CLK_10HZ           5
-
-#define VPRBRD_GPIOA_FREQ_DEFAULT       1000
-
-#define VPRBRD_GPIOA_CMD_CONT           0x00
-#define VPRBRD_GPIOA_CMD_PULSE          0x01
-#define VPRBRD_GPIOA_CMD_PWM            0x02
-#define VPRBRD_GPIOA_CMD_SETOUT         0x03
-#define VPRBRD_GPIOA_CMD_SETIN          0x04
-#define VPRBRD_GPIOA_CMD_SETINT         0x05
-#define VPRBRD_GPIOA_CMD_GETIN          0x06
-
-#define VPRBRD_GPIOB_CMD_SETDIR         0x00
-#define VPRBRD_GPIOB_CMD_SETVAL         0x01
-
-struct vprbrd_gpioa_msg {
-        u8 cmd;
-        u8 clk;
-        u8 offset;
-        u8 t1;
-        u8 t2;
-        u8 invert;
-        u8 pwmlevel;
-        u8 outval;
-        u8 risefall;
-        u8 answer;
-        u8 __fill;
-} __packed;
-
-struct vprbrd_gpiob_msg {
-        u8 cmd;
-        u16 val;
-        u16 mask;
-} __packed;
-
-struct vprbrd_gpio {
-        struct gpio_chip gpioa; /* gpio a related things */
-        u32 gpioa_out;
-        u32 gpioa_val;
-        struct gpio_chip gpiob; /* gpio b related things */
-        u32 gpiob_out;
-        u32 gpiob_val;
-        struct vprbrd *vb;
-};
-
-/* gpioa sampling clock module parameter */
-static unsigned char gpioa_clk;
-static unsigned int gpioa_freq = VPRBRD_GPIOA_FREQ_DEFAULT;
-module_param(gpioa_freq, uint, 0);
-MODULE_PARM_DESC(gpioa_freq,
-        "gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 1000000");
-
-/* ----- begin of gipo a chip -------------------------------------------- */
-
-static int vprbrd_gpioa_get(struct gpio_chip *chip,
-                unsigned offset)
-{
-        int ret, answer, error = 0;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpioa);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
-
-        /* if io is set to output, just return the saved value */
-        if (gpio->gpioa_out & (1 << offset))
-                return gpio->gpioa_val & (1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        gamsg->cmd = VPRBRD_GPIOA_CMD_GETIN;
-        gamsg->clk = 0x00;
-        gamsg->offset = offset;
-        gamsg->t1 = 0x00;
-        gamsg->t2 = 0x00;
-        gamsg->invert = 0x00;
-        gamsg->pwmlevel = 0x00;
-        gamsg->outval = 0x00;
-        gamsg->risefall = 0x00;
-        gamsg->answer = 0x00;
-        gamsg->__fill = 0x00;
-
-        ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
-                0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-        if (ret != sizeof(struct vprbrd_gpioa_msg))
-                error = -EREMOTEIO;
-
-        ret = usb_control_msg(vb->usb_dev, usb_rcvctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_IN, 0x0000,
-                0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-        answer = gamsg->answer & 0x01;
-
-        mutex_unlock(&vb->lock);
-
-        if (ret != sizeof(struct vprbrd_gpioa_msg))
-                error = -EREMOTEIO;
-
-        if (error)
-                return error;
-
-        return answer;
-}
-
-static void vprbrd_gpioa_set(struct gpio_chip *chip,
-                unsigned offset, int value)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpioa);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
-
-        if (gpio->gpioa_out & (1 << offset)) {
-                if (value)
-                        gpio->gpioa_val |= (1 << offset);
-                else
-                        gpio->gpioa_val &= ~(1 << offset);
-
-                mutex_lock(&vb->lock);
-
-                gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
-                gamsg->clk = 0x00;
-                gamsg->offset = offset;
-                gamsg->t1 = 0x00;
-                gamsg->t2 = 0x00;
-                gamsg->invert = 0x00;
-                gamsg->pwmlevel = 0x00;
-                gamsg->outval = value;
-                gamsg->risefall = 0x00;
-                gamsg->answer = 0x00;
-                gamsg->__fill = 0x00;
-
-                ret = usb_control_msg(vb->usb_dev,
-                        usb_sndctrlpipe(vb->usb_dev, 0),
-                        VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT,
-                        0x0000, 0x0000, gamsg,
-                        sizeof(struct vprbrd_gpioa_msg), VPRBRD_USB_TIMEOUT_MS);
-
-                mutex_unlock(&vb->lock);
-
-                if (ret != sizeof(struct vprbrd_gpioa_msg))
-                        dev_err(chip->dev, "usb error setting pin value\n");
-        }
-}
-
-static int vprbrd_gpioa_direction_input(struct gpio_chip *chip,
-                        unsigned offset)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpioa);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
-
-        gpio->gpioa_out &= ~(1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        gamsg->cmd = VPRBRD_GPIOA_CMD_SETIN;
-        gamsg->clk = gpioa_clk;
-        gamsg->offset = offset;
-        gamsg->t1 = 0x00;
-        gamsg->t2 = 0x00;
-        gamsg->invert = 0x00;
-        gamsg->pwmlevel = 0x00;
-        gamsg->outval = 0x00;
-        gamsg->risefall = 0x00;
-        gamsg->answer = 0x00;
-        gamsg->__fill = 0x00;
-
-        ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
-                0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-
-        mutex_unlock(&vb->lock);
-
-        if (ret != sizeof(struct vprbrd_gpioa_msg))
-                return -EREMOTEIO;
-
-        return 0;
-}
-
-static int vprbrd_gpioa_direction_output(struct gpio_chip *chip,
-                        unsigned offset, int value)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpioa);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf;
-
-        gpio->gpioa_out |= (1 << offset);
-        if (value)
-                gpio->gpioa_val |= (1 << offset);
-        else
-                gpio->gpioa_val &= ~(1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        gamsg->cmd = VPRBRD_GPIOA_CMD_SETOUT;
-        gamsg->clk = 0x00;
-        gamsg->offset = offset;
-        gamsg->t1 = 0x00;
-        gamsg->t2 = 0x00;
-        gamsg->invert = 0x00;
-        gamsg->pwmlevel = 0x00;
-        gamsg->outval = value;
-        gamsg->risefall = 0x00;
-        gamsg->answer = 0x00;
-        gamsg->__fill = 0x00;
-
-        ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOA, VPRBRD_USB_TYPE_OUT, 0x0000,
-                0x0000, gamsg, sizeof(struct vprbrd_gpioa_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-
-        mutex_unlock(&vb->lock);
-
-        if (ret != sizeof(struct vprbrd_gpioa_msg))
-                return -EREMOTEIO;
-
-        return 0;
-}
-
-/* ----- end of gpio a chip ---------------------------------------------- */
-
-/* ----- begin of gipo b chip -------------------------------------------- */
-
-static int vprbrd_gpiob_setdir(struct vprbrd *vb, unsigned offset,
-        unsigned dir)
-{
-        struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
-        int ret;
-
-        gbmsg->cmd = VPRBRD_GPIOB_CMD_SETDIR;
-        gbmsg->val = cpu_to_be16(dir << offset);
-        gbmsg->mask = cpu_to_be16(0x0001 << offset);
-
-        ret = usb_control_msg(vb->usb_dev, usb_sndctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT, 0x0000,
-                0x0000, gbmsg, sizeof(struct vprbrd_gpiob_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-
-        if (ret != sizeof(struct vprbrd_gpiob_msg))
-                return -EREMOTEIO;
-
-        return 0;
-}
-
-static int vprbrd_gpiob_get(struct gpio_chip *chip,
-                unsigned offset)
-{
-        int ret;
-        u16 val;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpiob);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
-
-        /* if io is set to output, just return the saved value */
-        if (gpio->gpiob_out & (1 << offset))
-                return gpio->gpiob_val & (1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        ret = usb_control_msg(vb->usb_dev, usb_rcvctrlpipe(vb->usb_dev, 0),
-                VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_IN, 0x0000,
-                0x0000, gbmsg,  sizeof(struct vprbrd_gpiob_msg),
-                VPRBRD_USB_TIMEOUT_MS);
-        val = gbmsg->val;
-
-        mutex_unlock(&vb->lock);
-
-        if (ret != sizeof(struct vprbrd_gpiob_msg))
-                return ret;
-
-        /* cache the read values */
-        gpio->gpiob_val = be16_to_cpu(val);
-
-        return (gpio->gpiob_val >> offset) & 0x1;
-}
-
-static void vprbrd_gpiob_set(struct gpio_chip *chip,
-                unsigned offset, int value)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpiob);
-        struct vprbrd *vb = gpio->vb;
-        struct vprbrd_gpiob_msg *gbmsg = (struct vprbrd_gpiob_msg *)vb->buf;
-
-        if (gpio->gpiob_out & (1 << offset)) {
-                if (value)
-                        gpio->gpiob_val |= (1 << offset);
-                else
-                        gpio->gpiob_val &= ~(1 << offset);
-
-                mutex_lock(&vb->lock);
-
-                gbmsg->cmd = VPRBRD_GPIOB_CMD_SETVAL;
-                gbmsg->val = cpu_to_be16(value << offset);
-                gbmsg->mask = cpu_to_be16(0x0001 << offset);
-
-                ret = usb_control_msg(vb->usb_dev,
-                        usb_sndctrlpipe(vb->usb_dev, 0),
-                        VPRBRD_USB_REQUEST_GPIOB, VPRBRD_USB_TYPE_OUT,
-                        0x0000, 0x0000, gbmsg,
-                        sizeof(struct vprbrd_gpiob_msg), VPRBRD_USB_TIMEOUT_MS);
-
-                mutex_unlock(&vb->lock);
-
-                if (ret != sizeof(struct vprbrd_gpiob_msg))
-                        dev_err(chip->dev, "usb error setting pin value\n");
-        }
-}
-
-static int vprbrd_gpiob_direction_input(struct gpio_chip *chip,
-                        unsigned offset)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpiob);
-        struct vprbrd *vb = gpio->vb;
-
-        gpio->gpiob_out &= ~(1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        ret = vprbrd_gpiob_setdir(vb, offset, 0);
-
-        mutex_unlock(&vb->lock);
-
-        if (ret)
-                dev_err(chip->dev, "usb error setting pin to input\n");
-
-        return ret;
-}
-
-static int vprbrd_gpiob_direction_output(struct gpio_chip *chip,
-                        unsigned offset, int value)
-{
-        int ret;
-        struct vprbrd_gpio *gpio =
-                        container_of(chip, struct vprbrd_gpio, gpiob);
-        struct vprbrd *vb = gpio->vb;
-
-        gpio->gpiob_out |= (1 << offset);
-        if (value)
-                gpio->gpiob_val |= (1 << offset);
-        else
-                gpio->gpiob_val &= ~(1 << offset);
-
-        mutex_lock(&vb->lock);
-
-        ret = vprbrd_gpiob_setdir(vb, offset, 1);
-        if (ret)
-                dev_err(chip->dev, "usb error setting pin to output\n");
-
-        mutex_unlock(&vb->lock);
-
-        vprbrd_gpiob_set(chip, offset, value);
-
-        return ret;
-}
-
-/* ----- end of gpio b chip ---------------------------------------------- */
-
-static int vprbrd_gpio_probe(struct platform_device *pdev)
-{
-        struct vprbrd *vb = dev_get_drvdata(pdev->dev.parent);
-        struct vprbrd_gpio *vb_gpio;
-        int ret;
-
-        vb_gpio = devm_kzalloc(&pdev->dev, sizeof(*vb_gpio), GFP_KERNEL);
-        if (vb_gpio == NULL)
-                return -ENOMEM;
-
-        vb_gpio->vb = vb;
-        /* registering gpio a */
-        vb_gpio->gpioa.label = "viperboard gpio a";
-        vb_gpio->gpioa.dev = &pdev->dev;
-        vb_gpio->gpioa.owner = THIS_MODULE;
-        vb_gpio->gpioa.base = -1;
-        vb_gpio->gpioa.ngpio = 16;
-        vb_gpio->gpioa.can_sleep = 1;
-        vb_gpio->gpioa.set = vprbrd_gpioa_set;
-        vb_gpio->gpioa.get = vprbrd_gpioa_get;
-        vb_gpio->gpioa.direction_input = vprbrd_gpioa_direction_input;
-        vb_gpio->gpioa.direction_output = vprbrd_gpioa_direction_output;
-        ret = gpiochip_add(&vb_gpio->gpioa);
-        if (ret < 0) {
-                dev_err(vb_gpio->gpioa.dev, "could not add gpio a");
-                goto err_gpioa;
-        }
-
-        /* registering gpio b */
-        vb_gpio->gpiob.label = "viperboard gpio b";
-        vb_gpio->gpiob.dev = &pdev->dev;
-        vb_gpio->gpiob.owner = THIS_MODULE;
-        vb_gpio->gpiob.base = -1;
-        vb_gpio->gpiob.ngpio = 16;
-        vb_gpio->gpiob.can_sleep = 1;
-        vb_gpio->gpiob.set = vprbrd_gpiob_set;
-        vb_gpio->gpiob.get = vprbrd_gpiob_get;
-        vb_gpio->gpiob.direction_input = vprbrd_gpiob_direction_input;
-        vb_gpio->gpiob.direction_output = vprbrd_gpiob_direction_output;
-        ret = gpiochip_add(&vb_gpio->gpiob);
-        if (ret < 0) {
-                dev_err(vb_gpio->gpiob.dev, "could not add gpio b");
-                goto err_gpiob;
-        }
-
-        platform_set_drvdata(pdev, vb_gpio);
-
-        return ret;
-
-err_gpiob:
-        ret = gpiochip_remove(&vb_gpio->gpioa);
-
-err_gpioa:
-        return ret;
-}
-
-static int vprbrd_gpio_remove(struct platform_device *pdev)
-{
-        struct vprbrd_gpio *vb_gpio = platform_get_drvdata(pdev);
-        int ret;
-
-        ret = gpiochip_remove(&vb_gpio->gpiob);
-        if (ret == 0)
-                ret = gpiochip_remove(&vb_gpio->gpioa);
-
-        return ret;
-}
-
-static struct platform_driver vprbrd_gpio_driver = {
-        .driver.name    = "viperboard-gpio",
-        .driver.owner   = THIS_MODULE,
-        .probe          = vprbrd_gpio_probe,
-        .remove         = vprbrd_gpio_remove,
-};
-
-static int __init vprbrd_gpio_init(void)
-{
-        switch (gpioa_freq) {
-        case 1000000:
-                gpioa_clk = VPRBRD_GPIOA_CLK_1MHZ;
-                break;
-        case 100000:
-                gpioa_clk = VPRBRD_GPIOA_CLK_100KHZ;
-                break;
-        case 10000:
-                gpioa_clk = VPRBRD_GPIOA_CLK_10KHZ;
-                break;
-        case 1000:
-                gpioa_clk = VPRBRD_GPIOA_CLK_1KHZ;
-                break;
-        case 100:
-                gpioa_clk = VPRBRD_GPIOA_CLK_100HZ;
-                break;
-        case 10:
-                gpioa_clk = VPRBRD_GPIOA_CLK_10HZ;
-                break;
-        default:
-                pr_warn("invalid gpioa_freq (%d)\n", gpioa_freq);
-                gpioa_clk = VPRBRD_GPIOA_CLK_1KHZ;
-        }
-
-        return platform_driver_register(&vprbrd_gpio_driver);
-}
-subsys_initcall(vprbrd_gpio_init);
-
-static void __exit vprbrd_gpio_exit(void)
-{
-        platform_driver_unregister(&vprbrd_gpio_driver);
-}
-module_exit(vprbrd_gpio_exit);
-
-MODULE_AUTHOR("Lars Poeschel <poeschel@lemonage.de>");
-MODULE_DESCRIPTION("GPIO driver for Nano River Techs Viperboard");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:viperboard-gpio");
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 9902732a382..98723cb9ac6 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -490,7 +490,7 @@ static struct gpio_chip vr41xx_gpio_chip = {
         .to_irq                 = vr41xx_gpio_to_irq,
 };
 
-static int giu_probe(struct platform_device *pdev)
+static int __devinit giu_probe(struct platform_device *pdev)
 {
         struct resource *res;
         unsigned int trigger, i, pin;
@@ -552,7 +552,7 @@ static int giu_probe(struct platform_device *pdev)
         return cascade_irq(irq, giu_get_irq);
 }
 
-static int giu_remove(struct platform_device *pdev)
+static int __devexit giu_remove(struct platform_device *pdev)
 {
         if (giu_base) {
                 iounmap(giu_base);
@@ -564,11 +564,22 @@ static int giu_remove(struct platform_device *pdev)
 
 static struct platform_driver giu_device_driver = {
         .probe          = giu_probe,
-        .remove         = giu_remove,
+        .remove         = __devexit_p(giu_remove),
         .driver         = {
                 .name   = "GIU",
                 .owner  = THIS_MODULE,
         },
 };
 
-module_platform_driver(giu_device_driver);
+static int __init vr41xx_giu_init(void)
+{
+        return platform_driver_register(&giu_device_driver);
+}
+
+static void __exit vr41xx_giu_exit(void)
+{
+        platform_driver_unregister(&giu_device_driver);
+}
+
+module_init(vr41xx_giu_init);
+module_exit(vr41xx_giu_exit);
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
deleted file mode 100644
index b53320a16fc..00000000000
--- a/drivers/gpio/gpio-vt8500.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/* drivers/gpio/gpio-vt8500.c
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- * Based on arch/arm/mach-vt8500/gpio.c:
- * - Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/bitops.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_device.h>
-
-/*
-        We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
-        by one set of registers (although not all may be valid).
-
-        Because different SoC's have different register offsets, we pass the
-        register offsets as data in vt8500_gpio_dt_ids[].
-
-        A value of NO_REG is used to indicate that this register is not
-        supported. Only used for ->en at the moment.
-*/
-
-#define NO_REG  0xFFFF
-
-/*
- * struct vt8500_gpio_bank_regoffsets
- * @en: offset to enable register of the bank
- * @dir: offset to direction register of the bank
- * @data_out: offset to the data out register of the bank
- * @data_in: offset to the data in register of the bank
- * @ngpio: highest valid pin in this bank
- */
-
-struct vt8500_gpio_bank_regoffsets {
-        unsigned int    en;
-        unsigned int    dir;
-        unsigned int    data_out;
-        unsigned int    data_in;
-        unsigned char   ngpio;
-};
-
-struct vt8500_gpio_data {
-        unsigned int                            num_banks;
-        struct vt8500_gpio_bank_regoffsets      banks[];
-};
-
-#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)          \
-{                                                               \
-        .en = __en,                                             \
-        .dir = __dir,                                           \
-        .data_out = __out,                                      \
-        .data_in = __in,                                        \
-        .ngpio = __ngpio,                                       \
-}
-
-static struct vt8500_gpio_data vt8500_data = {
-        .num_banks      = 7,
-        .banks  = {
-                VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
-                VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
-                VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
-                VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
-                VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
-                VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
-                VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
-        },
-};
-
-static struct vt8500_gpio_data wm8505_data = {
-        .num_banks      = 10,
-        .banks  = {
-                VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
-                VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
-                VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
-                VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
-                VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
-                VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
-                VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
-                VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
-                VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
-                VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
-                VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
-        },
-};
-
-/*
- * No information about which bits are valid so we just make
- * them all available until its figured out.
- */
-static struct vt8500_gpio_data wm8650_data = {
-        .num_banks      = 9,
-        .banks  = {
-                VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
-                VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
-                VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
-                VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
-                VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
-                VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
-                VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
-                VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
-                VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
-                VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
-        },
-};
-
-struct vt8500_gpio_chip {
-        struct gpio_chip                chip;
-
-        const struct vt8500_gpio_bank_regoffsets *regs;
-        void __iomem    *base;
-};
-
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        u32 val;
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        if (vt8500_chip->regs->en == NO_REG)
-                return 0;
-
-        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
-        val |= BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
-
-        return 0;
-}
-
-static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        u32 val;
-
-        if (vt8500_chip->regs->en == NO_REG)
-                return;
-
-        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
-        val &= ~BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
-}
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
-        val &= ~BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
-
-        return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                                                int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
-        val |= BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
-
-        if (value) {
-                val = readl_relaxed(vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-                val |= BIT(offset);
-                writel_relaxed(val, vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-        }
-        return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        return (readl_relaxed(vt8500_chip->base + vt8500_chip->regs->data_in) >>
-                                                                offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
-                                                                int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-        if (value)
-                val |= BIT(offset);
-        else
-                val &= ~BIT(offset);
-
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->data_out);
-}
-
-static int vt8500_of_xlate(struct gpio_chip *gc,
-                            const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        /* bank if specificed in gpiospec->args[0] */
-        if (flags)
-                *flags = gpiospec->args[2];
-
-        return gpiospec->args[1];
-}
-
-static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
-                                const struct vt8500_gpio_data *data)
-{
-        struct vt8500_gpio_chip *vtchip;
-        struct gpio_chip *chip;
-        int i;
-        int pin_cnt = 0;
-
-        vtchip = devm_kzalloc(&pdev->dev,
-                        sizeof(struct vt8500_gpio_chip) * data->num_banks,
-                        GFP_KERNEL);
-        if (!vtchip) {
-                pr_err("%s: failed to allocate chip memory\n", __func__);
-                return -ENOMEM;
-        }
-
-        for (i = 0; i < data->num_banks; i++) {
-                vtchip[i].base = base;
-                vtchip[i].regs = &data->banks[i];
-
-                chip = &vtchip[i].chip;
-
-                chip->of_xlate = vt8500_of_xlate;
-                chip->of_gpio_n_cells = 3;
-                chip->of_node = pdev->dev.of_node;
-
-                chip->request = vt8500_gpio_request;
-                chip->free = vt8500_gpio_free;
-                chip->direction_input = vt8500_gpio_direction_input;
-                chip->direction_output = vt8500_gpio_direction_output;
-                chip->get = vt8500_gpio_get_value;
-                chip->set = vt8500_gpio_set_value;
-                chip->can_sleep = 0;
-                chip->base = pin_cnt;
-                chip->ngpio = data->banks[i].ngpio;
-
-                pin_cnt += data->banks[i].ngpio;
-
-                gpiochip_add(chip);
-        }
-        return 0;
-}
-
-static struct of_device_id vt8500_gpio_dt_ids[] = {
-        { .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
-        { .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
-        { .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
-        { /* Sentinel */ },
-};
-
-static int vt8500_gpio_probe(struct platform_device *pdev)
-{
-        void __iomem *gpio_base;
-        struct device_node *np;
-        const struct of_device_id *of_id =
-                                of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
-
-        if (!of_id) {
-                dev_err(&pdev->dev, "Failed to find gpio controller\n");
-                return -ENODEV;
-        }
-
-        np = pdev->dev.of_node;
-        if (!np) {
-                dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
-                return -EFAULT;
-        }
-
-        gpio_base = of_iomap(np, 0);
-        if (!gpio_base) {
-                dev_err(&pdev->dev, "Unable to map GPIO registers\n");
-                of_node_put(np);
-                return -ENOMEM;
-        }
-
-        vt8500_add_chips(pdev, gpio_base, of_id->data);
-
-        return 0;
-}
-
-static struct platform_driver vt8500_gpio_driver = {
-        .probe          = vt8500_gpio_probe,
-        .driver         = {
-                .name   = "vt8500-gpio",
-                .owner  = THIS_MODULE,
-                .of_match_table = vt8500_gpio_dt_ids,
-        },
-};
-
-module_platform_driver(vt8500_gpio_driver);
-
-MODULE_DESCRIPTION("VT8500 GPIO Driver");
-MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
diff --git a/drivers/gpio/gpio-vx855.c b/drivers/gpio/gpio-vx855.c
index 2b7252cb242..ef5aabd8b8b 100644
--- a/drivers/gpio/gpio-vx855.c
+++ b/drivers/gpio/gpio-vx855.c
@@ -219,7 +219,7 @@ static void vx855gpio_gpio_setup(struct vx855_gpio *vg)
 }
 
 /* This platform device is ordinarily registered by the vx855 mfd driver */
-static int vx855gpio_probe(struct platform_device *pdev)
+static __devinit int vx855gpio_probe(struct platform_device *pdev)
 {
         struct resource *res_gpi;
         struct resource *res_gpo;
@@ -284,7 +284,7 @@ out_release:
         return ret;
 }
 
-static int vx855gpio_remove(struct platform_device *pdev)
+static int __devexit vx855gpio_remove(struct platform_device *pdev)
 {
         struct vx855_gpio *vg = platform_get_drvdata(pdev);
         struct resource *res;
@@ -312,10 +312,20 @@ static struct platform_driver vx855gpio_driver = {
                 .owner  = THIS_MODULE,
         },
         .probe          = vx855gpio_probe,
-        .remove         = vx855gpio_remove,
+        .remove         = __devexit_p(vx855gpio_remove),
 };
 
-module_platform_driver(vx855gpio_driver);
+static int vx855gpio_init(void)
+{
+        return platform_driver_register(&vx855gpio_driver);
+}
+module_init(vx855gpio_init);
+
+static void vx855gpio_exit(void)
+{
+        platform_driver_unregister(&vx855gpio_driver);
+}
+module_exit(vx855gpio_exit);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Harald Welte <HaraldWelte@viatech.com>");
diff --git a/drivers/gpio/gpio-wm831x.c b/drivers/gpio/gpio-wm831x.c
index 2a743e10ecb..deb949e75ec 100644
--- a/drivers/gpio/gpio-wm831x.c
+++ b/drivers/gpio/gpio-wm831x.c
@@ -102,8 +102,10 @@ static int wm831x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
         struct wm831x_gpio *wm831x_gpio = to_wm831x_gpio(chip);
         struct wm831x *wm831x = wm831x_gpio->wm831x;
 
-        return irq_create_mapping(wm831x->irq_domain,
-                                  WM831X_IRQ_GPIO_1 + offset);
+        if (!wm831x->irq_base)
+                return -EINVAL;
+
+        return wm831x->irq_base + WM831X_IRQ_GPIO_1 + offset;
 }
 
 static int wm831x_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
@@ -243,15 +245,14 @@ static struct gpio_chip template_chip = {
         .can_sleep              = 1,
 };
 
-static int wm831x_gpio_probe(struct platform_device *pdev)
+static int __devinit wm831x_gpio_probe(struct platform_device *pdev)
 {
         struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
         struct wm831x_pdata *pdata = wm831x->dev->platform_data;
         struct wm831x_gpio *wm831x_gpio;
         int ret;
 
-        wm831x_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm831x_gpio),
-                                   GFP_KERNEL);
+        wm831x_gpio = kzalloc(sizeof(*wm831x_gpio), GFP_KERNEL);
         if (wm831x_gpio == NULL)
                 return -ENOMEM;
 
@@ -266,27 +267,37 @@ static int wm831x_gpio_probe(struct platform_device *pdev)
 
         ret = gpiochip_add(&wm831x_gpio->gpio_chip);
         if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                return ret;
+                dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
+                        ret);
+                goto err;
         }
 
         platform_set_drvdata(pdev, wm831x_gpio);
 
         return ret;
+
+err:
+        kfree(wm831x_gpio);
+        return ret;
 }
 
-static int wm831x_gpio_remove(struct platform_device *pdev)
+static int __devexit wm831x_gpio_remove(struct platform_device *pdev)
 {
         struct wm831x_gpio *wm831x_gpio = platform_get_drvdata(pdev);
+        int ret;
 
-        return  gpiochip_remove(&wm831x_gpio->gpio_chip);
+        ret = gpiochip_remove(&wm831x_gpio->gpio_chip);
+        if (ret == 0)
+                kfree(wm831x_gpio);
+
+        return ret;
 }
 
 static struct platform_driver wm831x_gpio_driver = {
         .driver.name    = "wm831x-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = wm831x_gpio_probe,
-        .remove         = wm831x_gpio_remove,
+        .remove         = __devexit_p(wm831x_gpio_remove),
 };
 
 static int __init wm831x_gpio_init(void)
diff --git a/drivers/gpio/gpio-wm8350.c b/drivers/gpio/gpio-wm8350.c
index 0b598cf3df9..a06af515483 100644
--- a/drivers/gpio/gpio-wm8350.c
+++ b/drivers/gpio/gpio-wm8350.c
@@ -109,15 +109,14 @@ static struct gpio_chip template_chip = {
         .can_sleep              = 1,
 };
 
-static int wm8350_gpio_probe(struct platform_device *pdev)
+static int __devinit wm8350_gpio_probe(struct platform_device *pdev)
 {
         struct wm8350 *wm8350 = dev_get_drvdata(pdev->dev.parent);
         struct wm8350_platform_data *pdata = wm8350->dev->platform_data;
         struct wm8350_gpio_data *wm8350_gpio;
         int ret;
 
-        wm8350_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm8350_gpio),
-                                   GFP_KERNEL);
+        wm8350_gpio = kzalloc(sizeof(*wm8350_gpio), GFP_KERNEL);
         if (wm8350_gpio == NULL)
                 return -ENOMEM;
 
@@ -132,27 +131,37 @@ static int wm8350_gpio_probe(struct platform_device *pdev)
 
         ret = gpiochip_add(&wm8350_gpio->gpio_chip);
         if (ret < 0) {
-                dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
-                return ret;
+                dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
+                        ret);
+                goto err;
         }
 
         platform_set_drvdata(pdev, wm8350_gpio);
 
         return ret;
+
+err:
+        kfree(wm8350_gpio);
+        return ret;
 }
 
-static int wm8350_gpio_remove(struct platform_device *pdev)
+static int __devexit wm8350_gpio_remove(struct platform_device *pdev)
 {
         struct wm8350_gpio_data *wm8350_gpio = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = gpiochip_remove(&wm8350_gpio->gpio_chip);
+        if (ret == 0)
+                kfree(wm8350_gpio);
 
-        return gpiochip_remove(&wm8350_gpio->gpio_chip);
+        return ret;
 }
 
 static struct platform_driver wm8350_gpio_driver = {
         .driver.name    = "wm8350-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = wm8350_gpio_probe,
-        .remove         = wm8350_gpio_remove,
+        .remove         = __devexit_p(wm8350_gpio_remove),
 };
 
 static int __init wm8350_gpio_init(void)
diff --git a/drivers/gpio/gpio-wm8994.c b/drivers/gpio/gpio-wm8994.c
index ae409fd94af..96198f3fab7 100644
--- a/drivers/gpio/gpio-wm8994.c
+++ b/drivers/gpio/gpio-wm8994.c
@@ -19,7 +19,6 @@
 #include <linux/mfd/core.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>
-#include <linux/regmap.h>
 
 #include <linux/mfd/wm8994/core.h>
 #include <linux/mfd/wm8994/pdata.h>
@@ -90,11 +89,8 @@ static int wm8994_gpio_direction_out(struct gpio_chip *chip,
         struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
         struct wm8994 *wm8994 = wm8994_gpio->wm8994;
 
-        if (value)
-                value = WM8994_GPN_LVL;
-
         return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
-                               WM8994_GPN_DIR | WM8994_GPN_LVL, value);
+                               WM8994_GPN_DIR, 0);
 }
 
 static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -113,65 +109,14 @@ static int wm8994_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
         struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
         struct wm8994 *wm8994 = wm8994_gpio->wm8994;
 
-        return regmap_irq_get_virq(wm8994->irq_data, offset);
+        if (!wm8994->irq_base)
+                return -EINVAL;
+
+        return wm8994->irq_base + offset;
 }
 
 
 #ifdef CONFIG_DEBUG_FS
-static const char *wm8994_gpio_fn(u16 fn)
-{
-        switch (fn) {
-        case WM8994_GP_FN_PIN_SPECIFIC:
-                return "pin-specific";
-        case WM8994_GP_FN_GPIO:
-                return "GPIO";
-        case WM8994_GP_FN_SDOUT:
-                return "SDOUT";
-        case WM8994_GP_FN_IRQ:
-                return "IRQ";
-        case WM8994_GP_FN_TEMPERATURE:
-                return "Temperature";
-        case WM8994_GP_FN_MICBIAS1_DET:
-                return "MICBIAS1 detect";
-        case WM8994_GP_FN_MICBIAS1_SHORT:
-                return "MICBIAS1 short";
-        case WM8994_GP_FN_MICBIAS2_DET:
-                return "MICBIAS2 detect";
-        case WM8994_GP_FN_MICBIAS2_SHORT:
-                return "MICBIAS2 short";
-        case WM8994_GP_FN_FLL1_LOCK:
-                return "FLL1 lock";
-        case WM8994_GP_FN_FLL2_LOCK:
-                return "FLL2 lock";
-        case WM8994_GP_FN_SRC1_LOCK:
-                return "SRC1 lock";
-        case WM8994_GP_FN_SRC2_LOCK:
-                return "SRC2 lock";
-        case WM8994_GP_FN_DRC1_ACT:
-                return "DRC1 activity";
-        case WM8994_GP_FN_DRC2_ACT:
-                return "DRC2 activity";
-        case WM8994_GP_FN_DRC3_ACT:
-                return "DRC3 activity";
-        case WM8994_GP_FN_WSEQ_STATUS:
-                return "Write sequencer";
-        case WM8994_GP_FN_FIFO_ERROR:
-                return "FIFO error";
-        case WM8994_GP_FN_OPCLK:
-                return "OPCLK";
-        case WM8994_GP_FN_THW:
-                return "Thermal warning";
-        case WM8994_GP_FN_DCS_DONE:
-                return "DC servo";
-        case WM8994_GP_FN_FLL1_OUT:
-                return "FLL1 output";
-        case WM8994_GP_FN_FLL2_OUT:
-                return "FLL1 output";
-        default:
-                return "Unknown";
-        }
-}
-
 static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
         struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
@@ -203,29 +148,8 @@ static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                         continue;
                 }
 
-                if (reg & WM8994_GPN_DIR)
-                        seq_printf(s, "in ");
-                else
-                        seq_printf(s, "out ");
-
-                if (reg & WM8994_GPN_PU)
-                        seq_printf(s, "pull up ");
-
-                if (reg & WM8994_GPN_PD)
-                        seq_printf(s, "pull down ");
-
-                if (reg & WM8994_GPN_POL)
-                        seq_printf(s, "inverted ");
-                else
-                        seq_printf(s, "noninverted ");
-
-                if (reg & WM8994_GPN_OP_CFG)
-                        seq_printf(s, "open drain ");
-                else
-                        seq_printf(s, "CMOS ");
-
-                seq_printf(s, "%s (%x)\n",
-                           wm8994_gpio_fn(reg & WM8994_GPN_FN_MASK), reg);
+                /* No decode yet; note that GPIO2 is special */
+                seq_printf(s, "(%x)\n", reg);
         }
 }
 #else
@@ -245,15 +169,14 @@ static struct gpio_chip template_chip = {
         .can_sleep              = 1,
 };
 
-static int wm8994_gpio_probe(struct platform_device *pdev)
+static int __devinit wm8994_gpio_probe(struct platform_device *pdev)
 {
         struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent);
         struct wm8994_pdata *pdata = wm8994->dev->platform_data;
         struct wm8994_gpio *wm8994_gpio;
         int ret;
 
-        wm8994_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm8994_gpio),
-                                   GFP_KERNEL);
+        wm8994_gpio = kzalloc(sizeof(*wm8994_gpio), GFP_KERNEL);
         if (wm8994_gpio == NULL)
                 return -ENOMEM;
 
@@ -278,21 +201,27 @@ static int wm8994_gpio_probe(struct platform_device *pdev)
         return ret;
 
 err:
+        kfree(wm8994_gpio);
         return ret;
 }
 
-static int wm8994_gpio_remove(struct platform_device *pdev)
+static int __devexit wm8994_gpio_remove(struct platform_device *pdev)
 {
         struct wm8994_gpio *wm8994_gpio = platform_get_drvdata(pdev);
+        int ret;
 
-        return gpiochip_remove(&wm8994_gpio->gpio_chip);
+        ret = gpiochip_remove(&wm8994_gpio->gpio_chip);
+        if (ret == 0)
+                kfree(wm8994_gpio);
+
+        return ret;
 }
 
 static struct platform_driver wm8994_gpio_driver = {
         .driver.name    = "wm8994-gpio",
         .driver.owner   = THIS_MODULE,
         .probe          = wm8994_gpio_probe,
-        .remove         = wm8994_gpio_remove,
+        .remove         = __devexit_p(wm8994_gpio_remove),
 };
 
 static int __init wm8994_gpio_init(void)
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 9ae7aa8ca48..846fbd5e31b 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -14,7 +14,6 @@
 
 #include <linux/init.h>
 #include <linux/errno.h>
-#include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
@@ -159,7 +158,7 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
  * driver data structure. It returns 0, if the driver is bound to the GPIO
  * device, or a negative value if there is an error.
  */
-static int xgpio_of_probe(struct device_node *np)
+static int __devinit xgpio_of_probe(struct device_node *np)
 {
         struct xgpio_instance *chip;
         int status = 0;
@@ -206,10 +205,11 @@ static int xgpio_of_probe(struct device_node *np)
                        np->full_name, status);
                 return status;
         }
+        pr_info("XGpio: %s: registered\n", np->full_name);
         return 0;
 }
 
-static struct of_device_id xgpio_of_match[] = {
+static struct of_device_id xgpio_of_match[] __devinitdata = {
         { .compatible = "xlnx,xps-gpio-1.00.a", },
         { /* end of list */ },
 };
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
deleted file mode 100644
index cbad6e908d3..00000000000
--- a/drivers/gpio/gpiolib-acpi.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * ACPI helpers for GPIO API
- *
- * Copyright (C) 2012, Intel Corporation
- * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
- *          Mika Westerberg <mika.westerberg@linux.intel.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/errno.h>
-#include <linux/gpio.h>
-#include <linux/export.h>
-#include <linux/acpi_gpio.h>
-#include <linux/acpi.h>
-
-static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
-{
-        if (!gc->dev)
-                return false;
-
-        return ACPI_HANDLE(gc->dev) == data;
-}
-
-/**
- * acpi_get_gpio() - Translate ACPI GPIO pin to GPIO number usable with GPIO API
- * @path:       ACPI GPIO controller full path name, (e.g. "\\_SB.GPO1")
- * @pin:        ACPI GPIO pin number (0-based, controller-relative)
- *
- * Returns GPIO number to use with Linux generic GPIO API, or errno error value
- */
-
-int acpi_get_gpio(char *path, int pin)
-{
-        struct gpio_chip *chip;
-        acpi_handle handle;
-        acpi_status status;
-
-        status = acpi_get_handle(NULL, path, &handle);
-        if (ACPI_FAILURE(status))
-                return -ENODEV;
-
-        chip = gpiochip_find(handle, acpi_gpiochip_find);
-        if (!chip)
-                return -ENODEV;
-
-        if (!gpio_is_valid(chip->base + pin))
-                return -EINVAL;
-
-        return chip->base + pin;
-}
-EXPORT_SYMBOL_GPL(acpi_get_gpio);
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
deleted file mode 100644
index d542a141811..00000000000
--- a/drivers/gpio/gpiolib-of.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * OF helpers for the GPIO API
- *
- * Copyright (c) 2007-2008  MontaVista Software, Inc.
- *
- * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_gpio.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/slab.h>
-
-/* Private data structure for of_gpiochip_find_and_xlate */
-struct gg_data {
-        enum of_gpio_flags *flags;
-        struct of_phandle_args gpiospec;
-
-        int out_gpio;
-};
-
-/* Private function for resolving node pointer to gpio_chip */
-static int of_gpiochip_find_and_xlate(struct gpio_chip *gc, void *data)
-{
-        struct gg_data *gg_data = data;
-        int ret;
-
-        if ((gc->of_node != gg_data->gpiospec.np) ||
-            (gc->of_gpio_n_cells != gg_data->gpiospec.args_count) ||
-            (!gc->of_xlate))
-                return false;
-
-        ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags);
-        if (ret < 0)
-                return false;
-
-        gg_data->out_gpio = ret + gc->base;
-        return true;
-}
-
-/**
- * of_get_named_gpio_flags() - Get a GPIO number and flags to use with GPIO API
- * @np:         device node to get GPIO from
- * @propname:   property name containing gpio specifier(s)
- * @index:      index of the GPIO
- * @flags:      a flags pointer to fill in
- *
- * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
- * value on the error condition. If @flags is not NULL the function also fills
- * in flags for the GPIO.
- */
-int of_get_named_gpio_flags(struct device_node *np, const char *propname,
-                           int index, enum of_gpio_flags *flags)
-{
-        /* Return -EPROBE_DEFER to support probe() functions to be called
-         * later when the GPIO actually becomes available
-         */
-        struct gg_data gg_data = { .flags = flags, .out_gpio = -EPROBE_DEFER };
-        int ret;
-
-        /* .of_xlate might decide to not fill in the flags, so clear it. */
-        if (flags)
-                *flags = 0;
-
-        ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index,
-                                         &gg_data.gpiospec);
-        if (ret) {
-                pr_debug("%s: can't parse gpios property\n", __func__);
-                return ret;
-        }
-
-        gpiochip_find(&gg_data, of_gpiochip_find_and_xlate);
-
-        of_node_put(gg_data.gpiospec.np);
-        pr_debug("%s exited with status %d\n", __func__, gg_data.out_gpio);
-        return gg_data.out_gpio;
-}
-EXPORT_SYMBOL(of_get_named_gpio_flags);
-
-/**
- * of_gpio_named_count - Count GPIOs for a device
- * @np:         device node to count GPIOs for
- * @propname:   property name containing gpio specifier(s)
- *
- * The function returns the count of GPIOs specified for a node.
- *
- * Note that the empty GPIO specifiers counts too. For example,
- *
- * gpios = <0
- *          &pio1 1 2
- *          0
- *          &pio2 3 4>;
- *
- * defines four GPIOs (so this function will return 4), two of which
- * are not specified.
- */
-unsigned int of_gpio_named_count(struct device_node *np, const char* propname)
-{
-        unsigned int cnt = 0;
-
-        do {
-                int ret;
-
-                ret = of_parse_phandle_with_args(np, propname, "#gpio-cells",
-                                                 cnt, NULL);
-                /* A hole in the gpios = <> counts anyway. */
-                if (ret < 0 && ret != -EEXIST)
-                        break;
-        } while (++cnt);
-
-        return cnt;
-}
-EXPORT_SYMBOL(of_gpio_named_count);
-
-/**
- * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
- * @gc:         pointer to the gpio_chip structure
- * @np:         device node of the GPIO chip
- * @gpio_spec:  gpio specifier as found in the device tree
- * @flags:      a flags pointer to fill in
- *
- * This is simple translation function, suitable for the most 1:1 mapped
- * gpio chips. This function performs only one sanity check: whether gpio
- * is less than ngpios (that is specified in the gpio_chip).
- */
-int of_gpio_simple_xlate(struct gpio_chip *gc,
-                         const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        /*
-         * We're discouraging gpio_cells < 2, since that way you'll have to
-         * write your own xlate function (that will have to retrive the GPIO
-         * number and the flags from a single gpio cell -- this is possible,
-         * but not recommended).
-         */
-        if (gc->of_gpio_n_cells < 2) {
-                WARN_ON(1);
-                return -EINVAL;
-        }
-
-        if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
-                return -EINVAL;
-
-        if (gpiospec->args[0] >= gc->ngpio)
-                return -EINVAL;
-
-        if (flags)
-                *flags = gpiospec->args[1];
-
-        return gpiospec->args[0];
-}
-EXPORT_SYMBOL(of_gpio_simple_xlate);
-
-/**
- * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank)
- * @np:         device node of the GPIO chip
- * @mm_gc:      pointer to the of_mm_gpio_chip allocated structure
- *
- * To use this function you should allocate and fill mm_gc with:
- *
- * 1) In the gpio_chip structure:
- *    - all the callbacks
- *    - of_gpio_n_cells
- *    - of_xlate callback (optional)
- *
- * 3) In the of_mm_gpio_chip structure:
- *    - save_regs callback (optional)
- *
- * If succeeded, this function will map bank's memory and will
- * do all necessary work for you. Then you'll able to use .regs
- * to manage GPIOs from the callbacks.
- */
-int of_mm_gpiochip_add(struct device_node *np,
-                       struct of_mm_gpio_chip *mm_gc)
-{
-        int ret = -ENOMEM;
-        struct gpio_chip *gc = &mm_gc->gc;
-
-        gc->label = kstrdup(np->full_name, GFP_KERNEL);
-        if (!gc->label)
-                goto err0;
-
-        mm_gc->regs = of_iomap(np, 0);
-        if (!mm_gc->regs)
-                goto err1;
-
-        gc->base = -1;
-
-        if (mm_gc->save_regs)
-                mm_gc->save_regs(mm_gc);
-
-        mm_gc->gc.of_node = np;
-
-        ret = gpiochip_add(gc);
-        if (ret)
-                goto err2;
-
-        return 0;
-err2:
-        iounmap(mm_gc->regs);
-err1:
-        kfree(gc->label);
-err0:
-        pr_err("%s: GPIO chip registration failed with status %d\n",
-               np->full_name, ret);
-        return ret;
-}
-EXPORT_SYMBOL(of_mm_gpiochip_add);
-
-#ifdef CONFIG_PINCTRL
-static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
-{
-        struct device_node *np = chip->of_node;
-        struct of_phandle_args pinspec;
-        struct pinctrl_dev *pctldev;
-        int index = 0, ret;
-
-        if (!np)
-                return;
-
-        do {
-                ret = of_parse_phandle_with_args(np, "gpio-ranges",
-                                "#gpio-range-cells", index, &pinspec);
-                if (ret)
-                        break;
-
-                pctldev = of_pinctrl_get(pinspec.np);
-                if (!pctldev)
-                        break;
-
-                /*
-                 * This assumes that the n GPIO pins are consecutive in the
-                 * GPIO number space, and that the pins are also consecutive
-                 * in their local number space. Currently it is not possible
-                 * to add different ranges for one and the same GPIO chip,
-                 * as the code assumes that we have one consecutive range
-                 * on both, mapping 1-to-1.
-                 *
-                 * TODO: make the OF bindings handle multiple sparse ranges
-                 * on the same GPIO chip.
-                 */
-                ret = gpiochip_add_pin_range(chip,
-                                             pinctrl_dev_get_name(pctldev),
-                                             0, /* offset in gpiochip */
-                                             pinspec.args[0],
-                                             pinspec.args[1]);
-
-                if (ret)
-                        break;
-
-        } while (index++);
-}
-
-#else
-static void of_gpiochip_add_pin_range(struct gpio_chip *chip) {}
-#endif
-
-void of_gpiochip_add(struct gpio_chip *chip)
-{
-        if ((!chip->of_node) && (chip->dev))
-                chip->of_node = chip->dev->of_node;
-
-        if (!chip->of_node)
-                return;
-
-        if (!chip->of_xlate) {
-                chip->of_gpio_n_cells = 2;
-                chip->of_xlate = of_gpio_simple_xlate;
-        }
-
-        of_gpiochip_add_pin_range(chip);
-        of_node_get(chip->of_node);
-}
-
-void of_gpiochip_remove(struct gpio_chip *chip)
-{
-        gpiochip_remove_pin_ranges(chip);
-
-        if (chip->of_node)
-                of_node_put(chip->of_node);
-}
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 199fca15f27..a0fa0b25d21 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -116,7 +116,7 @@ static int gpio_ensure_requested(struct gpio_desc *desc, unsigned offset)
 }
 
 /* caller holds gpio_lock *OR* gpio is marked as requested */
-struct gpio_chip *gpio_to_chip(unsigned gpio)
+static inline struct gpio_chip *gpio_to_chip(unsigned gpio)
 {
         return gpio_desc[gpio].chip;
 }
@@ -191,32 +191,6 @@ err:
         return ret;
 }
 
-/* caller ensures gpio is valid and requested, chip->get_direction may sleep  */
-static int gpio_get_direction(unsigned gpio)
-{
-        struct gpio_chip        *chip;
-        struct gpio_desc        *desc = &gpio_desc[gpio];
-        int                     status = -EINVAL;
-
-        chip = gpio_to_chip(gpio);
-        gpio -= chip->base;
-
-        if (!chip->get_direction)
-                return status;
-
-        status = chip->get_direction(chip, gpio);
-        if (status > 0) {
-                /* GPIOF_DIR_IN, or other positive */
-                status = 1;
-                clear_bit(FLAG_IS_OUT, &desc->flags);
-        }
-        if (status == 0) {
-                /* GPIOF_DIR_OUT */
-                set_bit(FLAG_IS_OUT, &desc->flags);
-        }
-        return status;
-}
-
 #ifdef CONFIG_GPIO_SYSFS
 
 /* lock protects against unexport_gpio() being called while
@@ -249,7 +223,6 @@ static ssize_t gpio_direction_show(struct device *dev,
                 struct device_attribute *attr, char *buf)
 {
         const struct gpio_desc  *desc = dev_get_drvdata(dev);
-        unsigned                gpio = desc - gpio_desc;
         ssize_t                 status;
 
         mutex_lock(&sysfs_lock);
@@ -257,7 +230,6 @@ static ssize_t gpio_direction_show(struct device *dev,
         if (!test_bit(FLAG_EXPORT, &desc->flags))
                 status = -EIO;
         else
-                gpio_get_direction(gpio);
                 status = sprintf(buf, "%s\n",
                         test_bit(FLAG_IS_OUT, &desc->flags)
                                 ? "out" : "in");
@@ -651,11 +623,9 @@ static ssize_t export_store(struct class *class,
          */
 
         status = gpio_request(gpio, "sysfs");
-        if (status < 0) {
-                if (status == -EPROBE_DEFER)
-                        status = -ENODEV;
+        if (status < 0)
                 goto done;
-        }
+
         status = gpio_export(gpio, true);
         if (status < 0)
                 gpio_free(gpio);
@@ -732,9 +702,8 @@ int gpio_export(unsigned gpio, bool direction_may_change)
 {
         unsigned long           flags;
         struct gpio_desc        *desc;
-        int                     status;
+        int                     status = -EINVAL;
         const char              *ioname = NULL;
-        struct device           *dev;
 
         /* can't export until sysfs is available ... */
         if (!gpio_class.p) {
@@ -742,66 +711,59 @@ int gpio_export(unsigned gpio, bool direction_may_change)
                 return -ENOENT;
         }
 
-        if (!gpio_is_valid(gpio)) {
-                pr_debug("%s: gpio %d is not valid\n", __func__, gpio);
-                return -EINVAL;
-        }
+        if (!gpio_is_valid(gpio))
+                goto done;
 
         mutex_lock(&sysfs_lock);
 
         spin_lock_irqsave(&gpio_lock, flags);
         desc = &gpio_desc[gpio];
-        if (!test_bit(FLAG_REQUESTED, &desc->flags) ||
-             test_bit(FLAG_EXPORT, &desc->flags)) {
-                spin_unlock_irqrestore(&gpio_lock, flags);
-                pr_debug("%s: gpio %d unavailable (requested=%d, exported=%d)\n",
-                                __func__, gpio,
-                                test_bit(FLAG_REQUESTED, &desc->flags),
-                                test_bit(FLAG_EXPORT, &desc->flags));
-                status = -EPERM;
-                goto fail_unlock;
+        if (test_bit(FLAG_REQUESTED, &desc->flags)
+                        && !test_bit(FLAG_EXPORT, &desc->flags)) {
+                status = 0;
+                if (!desc->chip->direction_input
+                                || !desc->chip->direction_output)
+                        direction_may_change = false;
         }
-
-        if (!desc->chip->direction_input || !desc->chip->direction_output)
-                direction_may_change = false;
         spin_unlock_irqrestore(&gpio_lock, flags);
 
         if (desc->chip->names && desc->chip->names[gpio - desc->chip->base])
                 ioname = desc->chip->names[gpio - desc->chip->base];
 
-        dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0),
-                            desc, ioname ? ioname : "gpio%u", gpio);
-        if (IS_ERR(dev)) {
-                status = PTR_ERR(dev);
-                goto fail_unlock;
-        }
-
-        status = sysfs_create_group(&dev->kobj, &gpio_attr_group);
-        if (status)
-                goto fail_unregister_device;
-
-        if (direction_may_change) {
-                status = device_create_file(dev, &dev_attr_direction);
-                if (status)
-                        goto fail_unregister_device;
-        }
-
-        if (gpio_to_irq(gpio) >= 0 && (direction_may_change ||
-                                       !test_bit(FLAG_IS_OUT, &desc->flags))) {
-                status = device_create_file(dev, &dev_attr_edge);
-                if (status)
-                        goto fail_unregister_device;
+        if (status == 0) {
+                struct device   *dev;
+
+                dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0),
+                                desc, ioname ? ioname : "gpio%u", gpio);
+                if (!IS_ERR(dev)) {
+                        status = sysfs_create_group(&dev->kobj,
+                                                &gpio_attr_group);
+
+                        if (!status && direction_may_change)
+                                status = device_create_file(dev,
+                                                &dev_attr_direction);
+
+                        if (!status && gpio_to_irq(gpio) >= 0
+                                        && (direction_may_change
+                                                || !test_bit(FLAG_IS_OUT,
+                                                        &desc->flags)))
+                                status = device_create_file(dev,
+                                                &dev_attr_edge);
+
+                        if (status != 0)
+                                device_unregister(dev);
+                } else
+                        status = PTR_ERR(dev);
+                if (status == 0)
+                        set_bit(FLAG_EXPORT, &desc->flags);
         }
 
-        set_bit(FLAG_EXPORT, &desc->flags);
         mutex_unlock(&sysfs_lock);
-        return 0;
 
-fail_unregister_device:
-        device_unregister(dev);
-fail_unlock:
-        mutex_unlock(&sysfs_lock);
-        pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
+done:
+        if (status)
+                pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
+
         return status;
 }
 EXPORT_SYMBOL_GPL(gpio_export);
@@ -913,7 +875,6 @@ void gpio_unexport(unsigned gpio)
 {
         struct gpio_desc        *desc;
         int                     status = 0;
-        struct device           *dev = NULL;
 
         if (!gpio_is_valid(gpio)) {
                 status = -EINVAL;
@@ -925,20 +886,19 @@ void gpio_unexport(unsigned gpio)
         desc = &gpio_desc[gpio];
 
         if (test_bit(FLAG_EXPORT, &desc->flags)) {
+                struct device   *dev = NULL;
 
                 dev = class_find_device(&gpio_class, NULL, desc, match_export);
                 if (dev) {
                         gpio_setup_irq(desc, dev, 0);
                         clear_bit(FLAG_EXPORT, &desc->flags);
+                        put_device(dev);
+                        device_unregister(dev);
                 } else
                         status = -ENODEV;
         }
 
         mutex_unlock(&sysfs_lock);
-        if (dev) {
-                device_unregister(dev);
-                put_device(dev);
-        }
 done:
         if (status)
                 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
@@ -1111,7 +1071,6 @@ int gpiochip_add(struct gpio_chip *chip)
                          * inputs (often with pullups enabled) so power
                          * usage is minimized.  Linux code should set the
                          * gpio direction first thing; but until it does,
-                         * and in case chip->get_direction is not set,
                          * we may expose the wrong direction in sysfs.
                          */
                         gpio_desc[id].flags = !chip->direction_input
@@ -1120,10 +1079,6 @@ int gpiochip_add(struct gpio_chip *chip)
                 }
         }
 
-#ifdef CONFIG_PINCTRL
-        INIT_LIST_HEAD(&chip->pin_ranges);
-#endif
-
         of_gpiochip_add(chip);
 
 unlock:
@@ -1136,10 +1091,6 @@ unlock:
         if (status)
                 goto fail;
 
-        pr_debug("gpiochip_add: registered GPIOs %d to %d on device: %s\n",
-                chip->base, chip->base + chip->ngpio - 1,
-                chip->label ? : "generic");
-
         return 0;
 fail:
         /* failures here can mean systems won't boot... */
@@ -1164,7 +1115,6 @@ int gpiochip_remove(struct gpio_chip *chip)
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        gpiochip_remove_pin_ranges(chip);
         of_gpiochip_remove(chip);
 
         for (id = chip->base; id < chip->base + chip->ngpio; id++) {
@@ -1199,8 +1149,7 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
  * more gpio_chips.
  */
 struct gpio_chip *gpiochip_find(void *data,
-                                int (*match)(struct gpio_chip *chip,
-                                             void *data))
+                                int (*match)(struct gpio_chip *chip, void *data))
 {
         struct gpio_chip *chip = NULL;
         unsigned long flags;
@@ -1222,77 +1171,6 @@ struct gpio_chip *gpiochip_find(void *data,
 }
 EXPORT_SYMBOL_GPL(gpiochip_find);
 
-#ifdef CONFIG_PINCTRL
-
-/**
- * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping
- * @chip: the gpiochip to add the range for
- * @pinctrl_name: the dev_name() of the pin controller to map to
- * @gpio_offset: the start offset in the current gpio_chip number space
- * @pin_offset: the start offset in the pin controller number space
- * @npins: the number of pins from the offset of each pin space (GPIO and
- *      pin controller) to accumulate in this range
- */
-int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
-                           unsigned int gpio_offset, unsigned int pin_offset,
-                           unsigned int npins)
-{
-        struct gpio_pin_range *pin_range;
-        int ret;
-
-        pin_range = kzalloc(sizeof(*pin_range), GFP_KERNEL);
-        if (!pin_range) {
-                pr_err("%s: GPIO chip: failed to allocate pin ranges\n",
-                                chip->label);
-                return -ENOMEM;
-        }
-
-        /* Use local offset as range ID */
-        pin_range->range.id = gpio_offset;
-        pin_range->range.gc = chip;
-        pin_range->range.name = chip->label;
-        pin_range->range.base = chip->base + gpio_offset;
-        pin_range->range.pin_base = pin_offset;
-        pin_range->range.npins = npins;
-        pin_range->pctldev = pinctrl_find_and_add_gpio_range(pinctl_name,
-                        &pin_range->range);
-        if (IS_ERR(pin_range->pctldev)) {
-                ret = PTR_ERR(pin_range->pctldev);
-                pr_err("%s: GPIO chip: could not create pin range\n",
-                       chip->label);
-                kfree(pin_range);
-                return ret;
-        }
-        pr_debug("GPIO chip %s: created GPIO range %d->%d ==> %s PIN %d->%d\n",
-                 chip->label, gpio_offset, gpio_offset + npins - 1,
-                 pinctl_name,
-                 pin_offset, pin_offset + npins - 1);
-
-        list_add_tail(&pin_range->node, &chip->pin_ranges);
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(gpiochip_add_pin_range);
-
-/**
- * gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings
- * @chip: the chip to remove all the mappings for
- */
-void gpiochip_remove_pin_ranges(struct gpio_chip *chip)
-{
-        struct gpio_pin_range *pin_range, *tmp;
-
-        list_for_each_entry_safe(pin_range, tmp, &chip->pin_ranges, node) {
-                list_del(&pin_range->node);
-                pinctrl_remove_gpio_range(pin_range->pctldev,
-                                &pin_range->range);
-                kfree(pin_range);
-        }
-}
-EXPORT_SYMBOL_GPL(gpiochip_remove_pin_ranges);
-
-#endif /* CONFIG_PINCTRL */
-
 /* These "optional" allocation calls help prevent drivers from stomping
  * on each other, and help provide better diagnostics in debugfs.
  * They're called even less than the "set direction" calls.
@@ -1301,15 +1179,13 @@ int gpio_request(unsigned gpio, const char *label)
 {
         struct gpio_desc        *desc;
         struct gpio_chip        *chip;
-        int                     status = -EPROBE_DEFER;
+        int                     status = -EINVAL;
         unsigned long           flags;
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        if (!gpio_is_valid(gpio)) {
-                status = -EINVAL;
+        if (!gpio_is_valid(gpio))
                 goto done;
-        }
         desc = &gpio_desc[gpio];
         chip = desc->chip;
         if (chip == NULL)
@@ -1341,15 +1217,9 @@ int gpio_request(unsigned gpio, const char *label)
                         desc_set_label(desc, NULL);
                         module_put(chip->owner);
                         clear_bit(FLAG_REQUESTED, &desc->flags);
-                        goto done;
                 }
         }
-        if (chip->get_direction) {
-                /* chip->get_direction may sleep */
-                spin_unlock_irqrestore(&gpio_lock, flags);
-                gpio_get_direction(gpio);
-                spin_lock_irqsave(&gpio_lock, flags);
-        }
+
 done:
         if (status)
                 pr_debug("gpio_request: gpio-%d (%s) status %d\n",
@@ -1425,18 +1295,8 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
                                 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
 
         if (err)
-                goto free_gpio;
-
-        if (flags & GPIOF_EXPORT) {
-                err = gpio_export(gpio, flags & GPIOF_EXPORT_CHANGEABLE);
-                if (err)
-                        goto free_gpio;
-        }
-
-        return 0;
+                gpio_free(gpio);
 
- free_gpio:
-        gpio_free(gpio);
         return err;
 }
 EXPORT_SYMBOL_GPL(gpio_request_one);
@@ -1714,7 +1574,6 @@ int __gpio_get_value(unsigned gpio)
         int value;
 
         chip = gpio_to_chip(gpio);
-        /* Should be using gpio_get_value_cansleep() */
         WARN_ON(chip->can_sleep);
         value = chip->get ? chip->get(chip, gpio - chip->base) : 0;
         trace_gpio_value(gpio, 1, value);
@@ -1787,7 +1646,6 @@ void __gpio_set_value(unsigned gpio, int value)
         struct gpio_chip        *chip;
 
         chip = gpio_to_chip(gpio);
-        /* Should be using gpio_set_value_cansleep() */
         WARN_ON(chip->can_sleep);
         trace_gpio_value(gpio, 0, value);
         if (test_bit(FLAG_OPEN_DRAIN,  &gpio_desc[gpio].flags))
@@ -1885,7 +1743,6 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                 if (!test_bit(FLAG_REQUESTED, &gdesc->flags))
                         continue;
 
-                gpio_get_direction(gpio);
                 is_out = test_bit(FLAG_IS_OUT, &gdesc->flags);
                 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s",
                         gpio, gdesc->label,
@@ -1897,102 +1754,56 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
         }
 }
 
-static void *gpiolib_seq_start(struct seq_file *s, loff_t *pos)
+static int gpiolib_show(struct seq_file *s, void *unused)
 {
-        struct gpio_chip *chip = NULL;
-        unsigned int gpio;
-        void *ret = NULL;
-        loff_t index = 0;
+        struct gpio_chip        *chip = NULL;
+        unsigned                gpio;
+        int                     started = 0;
 
         /* REVISIT this isn't locked against gpio_chip removal ... */
 
         for (gpio = 0; gpio_is_valid(gpio); gpio++) {
-                if (gpio_desc[gpio].chip == chip)
-                        continue;
+                struct device *dev;
 
+                if (chip == gpio_desc[gpio].chip)
+                        continue;
                 chip = gpio_desc[gpio].chip;
                 if (!chip)
                         continue;
 
-                if (index++ >= *pos) {
-                        ret = chip;
-                        break;
-                }
+                seq_printf(s, "%sGPIOs %d-%d",
+                                started ? "\n" : "",
+                                chip->base, chip->base + chip->ngpio - 1);
+                dev = chip->dev;
+                if (dev)
+                        seq_printf(s, ", %s/%s",
+                                dev->bus ? dev->bus->name : "no-bus",
+                                dev_name(dev));
+                if (chip->label)
+                        seq_printf(s, ", %s", chip->label);
+                if (chip->can_sleep)
+                        seq_printf(s, ", can sleep");
+                seq_printf(s, ":\n");
+
+                started = 1;
+                if (chip->dbg_show)
+                        chip->dbg_show(s, chip);
+                else
+                        gpiolib_dbg_show(s, chip);
         }
-
-        s->private = "";
-
-        return ret;
-}
-
-static void *gpiolib_seq_next(struct seq_file *s, void *v, loff_t *pos)
-{
-        struct gpio_chip *chip = v;
-        unsigned int gpio;
-        void *ret = NULL;
-
-        /* skip GPIOs provided by the current chip */
-        for (gpio = chip->base + chip->ngpio; gpio_is_valid(gpio); gpio++) {
-                chip = gpio_desc[gpio].chip;
-                if (chip) {
-                        ret = chip;
-                        break;
-                }
-        }
-
-        s->private = "\n";
-        ++*pos;
-
-        return ret;
-}
-
-static void gpiolib_seq_stop(struct seq_file *s, void *v)
-{
-}
-
-static int gpiolib_seq_show(struct seq_file *s, void *v)
-{
-        struct gpio_chip *chip = v;
-        struct device *dev;
-
-        seq_printf(s, "%sGPIOs %d-%d", (char *)s->private,
-                        chip->base, chip->base + chip->ngpio - 1);
-        dev = chip->dev;
-        if (dev)
-                seq_printf(s, ", %s/%s", dev->bus ? dev->bus->name : "no-bus",
-                        dev_name(dev));
-        if (chip->label)
-                seq_printf(s, ", %s", chip->label);
-        if (chip->can_sleep)
-                seq_printf(s, ", can sleep");
-        seq_printf(s, ":\n");
-
-        if (chip->dbg_show)
-                chip->dbg_show(s, chip);
-        else
-                gpiolib_dbg_show(s, chip);
-
         return 0;
 }
 
-static const struct seq_operations gpiolib_seq_ops = {
-        .start = gpiolib_seq_start,
-        .next = gpiolib_seq_next,
-        .stop = gpiolib_seq_stop,
-        .show = gpiolib_seq_show,
-};
-
 static int gpiolib_open(struct inode *inode, struct file *file)
 {
-        return seq_open(file, &gpiolib_seq_ops);
+        return single_open(file, gpiolib_show, NULL);
 }
 
 static const struct file_operations gpiolib_operations = {
-        .owner          = THIS_MODULE,
         .open           = gpiolib_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
 static int __init gpiolib_debugfs_init(void)