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authorBorislav Petkov <borislav.petkov@amd.com>2010-09-22 11:42:27 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2011-01-07 05:54:22 -0500
commitfa7ae8cc8c88c0679eab24c5a1b5d3b134a5f542 (patch)
treec6325ce19c35d8fb5b1e85358973c517866584aa /drivers/edac
parent6245288232516aadf293f575d1812dafb4696aee (diff)
EDAC, MCE: Shorten error report formatting
Shorten up MCi_STATUS flags and add BD's new deferred and poison types. Also, simplify formatting. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/mce_amd.c54
1 files changed, 32 insertions, 22 deletions
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 53d4dc0de34..0a19d262668 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -723,19 +723,22 @@ wrong_fp_mce:
723 723
724static inline void amd_decode_err_code(u16 ec) 724static inline void amd_decode_err_code(u16 ec)
725{ 725{
726 if (TLB_ERROR(ec)) { 726
727 pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n", 727 pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
728 TT_MSG(ec), LL_MSG(ec)); 728
729 } else if (MEM_ERROR(ec)) { 729 if (BUS_ERROR(ec))
730 pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n", 730 pr_cont(", mem/io: %s", II_MSG(ec));
731 R4_MSG(ec), TT_MSG(ec), LL_MSG(ec)); 731 else
732 } else if (BUS_ERROR(ec)) { 732 pr_cont(", tx: %s", TT_MSG(ec));
733 pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, " 733
734 "Participating Processor: %s\n", 734 if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
735 R4_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), 735 pr_cont(", mem-tx: %s", R4_MSG(ec));
736 PP_MSG(ec)); 736
737 } else 737 if (BUS_ERROR(ec))
738 pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec); 738 pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
739 }
740
741 pr_cont("\n");
739} 742}
740 743
741/* 744/*
@@ -757,25 +760,32 @@ static bool amd_filter_mce(struct mce *m)
757int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) 760int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
758{ 761{
759 struct mce *m = (struct mce *)data; 762 struct mce *m = (struct mce *)data;
763 struct cpuinfo_x86 *c = &boot_cpu_data;
760 int node, ecc; 764 int node, ecc;
761 765
762 if (amd_filter_mce(m)) 766 if (amd_filter_mce(m))
763 return NOTIFY_STOP; 767 return NOTIFY_STOP;
764 768
765 pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank); 769 pr_emerg(HW_ERR "MC%d_STATUS[%s|%s|%s|%s|%s",
770 m->bank,
771 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
772 ((m->status & MCI_STATUS_UC) ? "UE" : "CE"),
773 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
774 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
775 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
766 776
767 pr_cont("%sorrected error, other errors lost: %s, " 777 if (c->x86 == 0x15)
768 "CPU context corrupt: %s", 778 pr_cont("|%s|%s",
769 ((m->status & MCI_STATUS_UC) ? "Unc" : "C"), 779 ((m->status & BIT(44)) ? "Deferred" : "-"),
770 ((m->status & MCI_STATUS_OVER) ? "yes" : "no"), 780 ((m->status & BIT(43)) ? "Poison" : "-"));
771 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
772 781
773 /* do the two bits[14:13] together */ 782 /* do the two bits[14:13] together */
774 ecc = (m->status >> 45) & 0x3; 783 ecc = (m->status >> 45) & 0x3;
775 if (ecc) 784 if (ecc)
776 pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U")); 785 pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
786
787 pr_cont("]: 0x%016llx\n", m->status);
777 788
778 pr_cont("\n");
779 789
780 switch (m->bank) { 790 switch (m->bank) {
781 case 0: 791 case 0:
@@ -787,7 +797,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
787 break; 797 break;
788 798
789 case 2: 799 case 2:
790 if (boot_cpu_data.x86 == 0x15) 800 if (c->x86 == 0x15)
791 amd_decode_cu_mce(m); 801 amd_decode_cu_mce(m);
792 else 802 else
793 amd_decode_bu_mce(m); 803 amd_decode_bu_mce(m);