diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2009-07-28 04:56:15 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-09-14 13:01:20 -0400 |
commit | d93cc222adf3532ddb442648f8db00c15d1dc4c1 (patch) | |
tree | 57e0ac9280bff2b824a066621a3009ea7f9835ea /drivers/edac | |
parent | b69b29de65fe4078b125acc9dea34be82f7c362c (diff) |
EDAC, AMD: carve out decoding of MCi_STATUS ErrorCode
This is the MCE error code from the MCi_STATUS banks, bits [15:0] which
describe what type of error was encountered: GART TLB, Memory or Bus
error. The semantics of those bits are identical across all MCE banks so
decode those separately, irrespectively of MCE type.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/amd64_edac.c | 4 | ||||
-rw-r--r-- | drivers/edac/edac_mce_amd.c | 37 |
2 files changed, 22 insertions, 19 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index c81ca2cf8dc..173dc4a8416 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -2289,10 +2289,6 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, | |||
2289 | u32 xec = EXT_ERROR_CODE(info->nbsl); | 2289 | u32 xec = EXT_ERROR_CODE(info->nbsl); |
2290 | int ecc_type = info->nbsh & (0x3 << 13); | 2290 | int ecc_type = info->nbsh & (0x3 << 13); |
2291 | 2291 | ||
2292 | pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, %s\n", | ||
2293 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), PP_MSG(ec)); | ||
2294 | |||
2295 | |||
2296 | /* Bail early out if this was an 'observed' error */ | 2292 | /* Bail early out if this was an 'observed' error */ |
2297 | if (PP(ec) == K8_NBSL_PP_OBS) | 2293 | if (PP(ec) == K8_NBSL_PP_OBS) |
2298 | return; | 2294 | return; |
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c index 0ba92d65db4..81f812eb3ae 100644 --- a/drivers/edac/edac_mce_amd.c +++ b/drivers/edac/edac_mce_amd.c | |||
@@ -150,6 +150,16 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) | |||
150 | pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf))); | 150 | pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf))); |
151 | } | 151 | } |
152 | 152 | ||
153 | |||
154 | pr_emerg("%s.\n", EXT_ERR_MSG(xec)); | ||
155 | |||
156 | if (BUS_ERROR(ec) && nb_bus_decoder) | ||
157 | nb_bus_decoder(node_id, regs); | ||
158 | } | ||
159 | EXPORT_SYMBOL_GPL(amd_decode_nb_mce); | ||
160 | |||
161 | static inline void amd_decode_err_code(unsigned int ec) | ||
162 | { | ||
153 | if (TLB_ERROR(ec)) { | 163 | if (TLB_ERROR(ec)) { |
154 | /* | 164 | /* |
155 | * GART errors are intended to help graphics driver developers | 165 | * GART errors are intended to help graphics driver developers |
@@ -166,33 +176,28 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) | |||
166 | if (!report_gart_errors) | 176 | if (!report_gart_errors) |
167 | return; | 177 | return; |
168 | 178 | ||
169 | pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n", | 179 | pr_emerg(" Transaction: %s, Cache Level %s\n", |
170 | TT_MSG(ec), LL_MSG(ec)); | 180 | TT_MSG(ec), LL_MSG(ec)); |
171 | } else if (MEM_ERROR(ec)) { | 181 | } else if (MEM_ERROR(ec)) { |
172 | pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s," | 182 | pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s", |
173 | " Cache Level: %s", | ||
174 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); | 183 | RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); |
175 | } else if (BUS_ERROR(ec)) { | 184 | } else if (BUS_ERROR(ec)) { |
176 | pr_emerg(" Bus (Link/DRAM) error\n"); | 185 | pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, " |
177 | if (nb_bus_decoder) | 186 | "Participating Processor: %s\n", |
178 | nb_bus_decoder(node_id, regs); | 187 | RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), |
179 | } else { | 188 | PP_MSG(ec)); |
180 | /* shouldn't reach here! */ | 189 | } else |
181 | pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec); | 190 | pr_warning("Huh? Unknown MCE error 0x%x\n", ec); |
182 | } | ||
183 | |||
184 | pr_emerg("%s.\n", EXT_ERR_MSG(xec)); | ||
185 | } | 191 | } |
186 | EXPORT_SYMBOL_GPL(amd_decode_nb_mce); | ||
187 | 192 | ||
188 | void decode_mce(struct mce *m) | 193 | void decode_mce(struct mce *m) |
189 | { | 194 | { |
190 | struct err_regs regs; | 195 | struct err_regs regs; |
191 | int node, ecc; | 196 | int node, ecc; |
192 | 197 | ||
193 | pr_emerg("MC%d_STATUS:\n", m->bank); | 198 | pr_emerg("MC%d_STATUS: ", m->bank); |
194 | 199 | ||
195 | pr_emerg(" Error: %sorrected, Report: %s, MiscV: %svalid, " | 200 | pr_cont("%sorrected error, report: %s, MiscV: %svalid, " |
196 | "CPU context corrupt: %s", | 201 | "CPU context corrupt: %s", |
197 | ((m->status & MCI_STATUS_UC) ? "Unc" : "C"), | 202 | ((m->status & MCI_STATUS_UC) ? "Unc" : "C"), |
198 | ((m->status & MCI_STATUS_EN) ? "yes" : "no"), | 203 | ((m->status & MCI_STATUS_EN) ? "yes" : "no"), |
@@ -206,6 +211,8 @@ void decode_mce(struct mce *m) | |||
206 | 211 | ||
207 | pr_cont("\n"); | 212 | pr_cont("\n"); |
208 | 213 | ||
214 | amd_decode_err_code(m->status & 0xffff); | ||
215 | |||
209 | if (m->bank == 4) { | 216 | if (m->bank == 4) { |
210 | regs.nbsl = (u32) m->status; | 217 | regs.nbsl = (u32) m->status; |
211 | regs.nbsh = (u32)(m->status >> 32); | 218 | regs.nbsh = (u32)(m->status >> 32); |