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authorBorislav Petkov <borislav.petkov@amd.com>2009-07-23 10:05:53 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2009-09-14 12:58:29 -0400
commitb7225e4fc19ce27a594cb2b868ef151bf82f8f93 (patch)
tree8b102ce7756a69a624a51ca1a2d2af6c21df4755 /drivers/edac
parent5110dbdeab546268dda2e4c6a83448639b2fc5ae (diff)
amd64_edac: remove memory and GART TLB error decoders
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c36
1 files changed, 7 insertions, 29 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 5af87d44c80..75842f08db8 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2209,28 +2209,6 @@ static int amd64_get_error_info(struct mem_ctl_info *mci,
2209 return 1; 2209 return 1;
2210} 2210}
2211 2211
2212static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci,
2213 struct err_regs *info)
2214{
2215 u32 ec = ERROR_CODE(info->nbsl);
2216
2217 amd64_mc_printk(mci, KERN_ERR,
2218 "GART TLB event: transaction type(%s), "
2219 "cache level(%s)\n", TT_MSG(ec), LL_MSG(ec));
2220}
2221
2222static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci,
2223 struct err_regs *info)
2224{
2225 u32 ec = ERROR_CODE(info->nbsl);
2226
2227 amd64_mc_printk(mci, KERN_ERR,
2228 "cache hierarchy error: memory transaction type(%s), "
2229 "transaction type(%s), cache level(%s)\n",
2230 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
2231}
2232
2233
2234/* 2212/*
2235 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR 2213 * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
2236 * ADDRESS and process. 2214 * ADDRESS and process.
@@ -2411,19 +2389,19 @@ void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs,
2411 if (!report_gart_errors) 2389 if (!report_gart_errors)
2412 return; 2390 return;
2413 2391
2414 pr_emerg("GART TLB error\n"); 2392 pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
2415 amd64_decode_gart_tlb_error(mci, regs); 2393 TT_MSG(ec), LL_MSG(ec));
2416 } else if (MEM_ERROR(ec)) { 2394 } else if (MEM_ERROR(ec)) {
2417 pr_emerg("Memory/Cache error\n"); 2395 pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
2418 amd64_decode_mem_cache_error(mci, regs); 2396 " Cache Level: %s",
2397 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
2419 } else if (BUS_ERROR(ec)) { 2398 } else if (BUS_ERROR(ec)) {
2420 pr_emerg("Bus (Link/DRAM) error\n"); 2399 pr_emerg(" Bus (Link/DRAM) error\n");
2421 amd64_decode_bus_error(mci, regs); 2400 amd64_decode_bus_error(mci, regs);
2422 } else { 2401 } else {
2423 /* shouldn't reach here! */ 2402 /* shouldn't reach here! */
2424 amd64_mc_printk(mci, KERN_WARNING, 2403 amd64_mc_printk(mci, KERN_WARNING,
2425 "%s(): unknown MCE error 0x%x\n", __func__, 2404 "%s(): unknown MCE error 0x%x\n", __func__, ec);
2426 ec);
2427 } 2405 }
2428 2406
2429 pr_emerg("%s.\n", EXT_ERR_MSG(xec)); 2407 pr_emerg("%s.\n", EXT_ERR_MSG(xec));