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authorChristoph Egger <siccegge@cs.fau.de>2010-05-17 11:25:54 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-05-21 12:34:31 -0400
commit0dbb5671921b6dad2396090ef81a3efee1ae7da1 (patch)
treef4cc6f2e8a0868bdb81b685a24654db5457ccae9 /drivers/char/serial167.c
parent26e1e8d1d1cfa914b95b5dab001a6ed898872755 (diff)
serial: Tidy REMOTE_DEBUG
REMOTE_DEBUG does already appear in 2.2 kernel sources but didn't appear as a config Option in the initial git import 2.6.12-rc. It's currently just used in one single place of the linux kernel and should probably be dropped totally Signed-off-by: Christoph Egger <siccegge@cs.fau.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/char/serial167.c')
-rw-r--r--drivers/char/serial167.c223
1 files changed, 1 insertions, 222 deletions
diff --git a/drivers/char/serial167.c b/drivers/char/serial167.c
index 78a62ebe75c..ecbe479c7d6 100644
--- a/drivers/char/serial167.c
+++ b/drivers/char/serial167.c
@@ -176,23 +176,6 @@ static void config_setup(struct cyclades_port *);
176static void show_status(int); 176static void show_status(int);
177#endif 177#endif
178 178
179#ifdef CONFIG_REMOTE_DEBUG
180static void debug_setup(void);
181void queueDebugChar(int c);
182int getDebugChar(void);
183
184#define DEBUG_PORT 1
185#define DEBUG_LEN 256
186
187typedef struct {
188 int in;
189 int out;
190 unsigned char buf[DEBUG_LEN];
191} debugq;
192
193debugq debugiq;
194#endif
195
196/* 179/*
197 * I have my own version of udelay(), as it is needed when initialising 180 * I have my own version of udelay(), as it is needed when initialising
198 * the chip, before the delay loop has been calibrated. Should probably 181 * the chip, before the delay loop has been calibrated. Should probably
@@ -515,11 +498,6 @@ static irqreturn_t cd2401_tx_interrupt(int irq, void *dev_id)
515 /* determine the channel and change to that context */ 498 /* determine the channel and change to that context */
516 channel = (u_short) (base_addr[CyLICR] >> 2); 499 channel = (u_short) (base_addr[CyLICR] >> 2);
517 500
518#ifdef CONFIG_REMOTE_DEBUG
519 if (channel == DEBUG_PORT) {
520 panic("TxInt on debug port!!!");
521 }
522#endif
523 /* validate the port number (as configured and open) */ 501 /* validate the port number (as configured and open) */
524 if ((channel < 0) || (NR_PORTS <= channel)) { 502 if ((channel < 0) || (NR_PORTS <= channel)) {
525 base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); 503 base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy);
@@ -634,14 +612,6 @@ static irqreturn_t cd2401_rx_interrupt(int irq, void *dev_id)
634 info->last_active = jiffies; 612 info->last_active = jiffies;
635 save_cnt = char_count = base_addr[CyRFOC]; 613 save_cnt = char_count = base_addr[CyRFOC];
636 614
637#ifdef CONFIG_REMOTE_DEBUG
638 if (channel == DEBUG_PORT) {
639 while (char_count--) {
640 data = base_addr[CyRDR];
641 queueDebugChar(data);
642 }
643 } else
644#endif
645 /* if there is nowhere to put the data, discard it */ 615 /* if there is nowhere to put the data, discard it */
646 if (info->tty == 0) { 616 if (info->tty == 0) {
647 while (char_count--) { 617 while (char_count--) {
@@ -2195,9 +2165,7 @@ static int __init serial167_init(void)
2195 port_num++; 2165 port_num++;
2196 info++; 2166 info++;
2197 } 2167 }
2198#ifdef CONFIG_REMOTE_DEBUG 2168
2199 debug_setup();
2200#endif
2201 ret = request_irq(MVME167_IRQ_SER_ERR, cd2401_rxerr_interrupt, 0, 2169 ret = request_irq(MVME167_IRQ_SER_ERR, cd2401_rxerr_interrupt, 0,
2202 "cd2401_errors", cd2401_rxerr_interrupt); 2170 "cd2401_errors", cd2401_rxerr_interrupt);
2203 if (ret) { 2171 if (ret) {
@@ -2518,193 +2486,4 @@ static int __init serial167_console_init(void)
2518 2486
2519console_initcall(serial167_console_init); 2487console_initcall(serial167_console_init);
2520 2488
2521#ifdef CONFIG_REMOTE_DEBUG
2522void putDebugChar(int c)
2523{
2524 volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
2525 unsigned long flags;
2526 volatile u_char sink;
2527 u_char ier;
2528 int port;
2529
2530 local_irq_save(flags);
2531
2532 /* Ensure transmitter is enabled! */
2533
2534 port = DEBUG_PORT;
2535 base_addr[CyCAR] = (u_char) port;
2536 while (base_addr[CyCCR])
2537 ;
2538 base_addr[CyCCR] = CyENB_XMTR;
2539
2540 ier = base_addr[CyIER];
2541 base_addr[CyIER] = CyTxMpty;
2542
2543 while (1) {
2544 if (pcc2chip[PccSCCTICR] & 0x20) {
2545 /* We have a Tx int. Acknowledge it */
2546 sink = pcc2chip[PccTPIACKR];
2547 if ((base_addr[CyLICR] >> 2) == port) {
2548 base_addr[CyTDR] = c;
2549 base_addr[CyTEOIR] = 0;
2550 break;
2551 } else
2552 base_addr[CyTEOIR] = CyNOTRANS;
2553 }
2554 }
2555
2556 base_addr[CyIER] = ier;
2557
2558 local_irq_restore(flags);
2559}
2560
2561int getDebugChar()
2562{
2563 volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
2564 unsigned long flags;
2565 volatile u_char sink;
2566 u_char ier;
2567 int port;
2568 int i, c;
2569
2570 i = debugiq.out;
2571 if (i != debugiq.in) {
2572 c = debugiq.buf[i];
2573 if (++i == DEBUG_LEN)
2574 i = 0;
2575 debugiq.out = i;
2576 return c;
2577 }
2578 /* OK, nothing in queue, wait in poll loop */
2579
2580 local_irq_save(flags);
2581
2582 /* Ensure receiver is enabled! */
2583
2584 port = DEBUG_PORT;
2585 base_addr[CyCAR] = (u_char) port;
2586#if 0
2587 while (base_addr[CyCCR])
2588 ;
2589 base_addr[CyCCR] = CyENB_RCVR;
2590#endif
2591 ier = base_addr[CyIER];
2592 base_addr[CyIER] = CyRxData;
2593
2594 while (1) {
2595 if (pcc2chip[PccSCCRICR] & 0x20) {
2596 /* We have a Rx int. Acknowledge it */
2597 sink = pcc2chip[PccRPIACKR];
2598 if ((base_addr[CyLICR] >> 2) == port) {
2599 int cnt = base_addr[CyRFOC];
2600 while (cnt-- > 0) {
2601 c = base_addr[CyRDR];
2602 if (c == 0)
2603 printk
2604 ("!! debug char is null (cnt=%d) !!",
2605 cnt);
2606 else
2607 queueDebugChar(c);
2608 }
2609 base_addr[CyREOIR] = 0;
2610 i = debugiq.out;
2611 if (i == debugiq.in)
2612 panic("Debug input queue empty!");
2613 c = debugiq.buf[i];
2614 if (++i == DEBUG_LEN)
2615 i = 0;
2616 debugiq.out = i;
2617 break;
2618 } else
2619 base_addr[CyREOIR] = CyNOTRANS;
2620 }
2621 }
2622
2623 base_addr[CyIER] = ier;
2624
2625 local_irq_restore(flags);
2626
2627 return (c);
2628}
2629
2630void queueDebugChar(int c)
2631{
2632 int i;
2633
2634 i = debugiq.in;
2635 debugiq.buf[i] = c;
2636 if (++i == DEBUG_LEN)
2637 i = 0;
2638 if (i != debugiq.out)
2639 debugiq.in = i;
2640}
2641
2642static void debug_setup()
2643{
2644 unsigned long flags;
2645 volatile unsigned char *base_addr = (u_char *) BASE_ADDR;
2646 int i, cflag;
2647
2648 cflag = B19200;
2649
2650 local_irq_save(flags);
2651
2652 for (i = 0; i < 4; i++) {
2653 base_addr[CyCAR] = i;
2654 base_addr[CyLICR] = i << 2;
2655 }
2656
2657 debugiq.in = debugiq.out = 0;
2658
2659 base_addr[CyCAR] = DEBUG_PORT;
2660
2661 /* baud rate */
2662 i = cflag & CBAUD;
2663
2664 base_addr[CyIER] = 0;
2665
2666 base_addr[CyCMR] = CyASYNC;
2667 base_addr[CyLICR] = DEBUG_PORT << 2;
2668 base_addr[CyLIVR] = 0x5c;
2669
2670 /* tx and rx baud rate */
2671
2672 base_addr[CyTCOR] = baud_co[i];
2673 base_addr[CyTBPR] = baud_bpr[i];
2674 base_addr[CyRCOR] = baud_co[i] >> 5;
2675 base_addr[CyRBPR] = baud_bpr[i];
2676
2677 /* set line characteristics according configuration */
2678
2679 base_addr[CySCHR1] = 0;
2680 base_addr[CySCHR2] = 0;
2681 base_addr[CySCRL] = 0;
2682 base_addr[CySCRH] = 0;
2683 base_addr[CyCOR1] = Cy_8_BITS | CyPARITY_NONE;
2684 base_addr[CyCOR2] = 0;
2685 base_addr[CyCOR3] = Cy_1_STOP;
2686 base_addr[CyCOR4] = baud_cor4[i];
2687 base_addr[CyCOR5] = 0;
2688 base_addr[CyCOR6] = 0;
2689 base_addr[CyCOR7] = 0;
2690
2691 write_cy_cmd(base_addr, CyINIT_CHAN);
2692 write_cy_cmd(base_addr, CyENB_RCVR);
2693
2694 base_addr[CyCAR] = DEBUG_PORT; /* !!! Is this needed? */
2695
2696 base_addr[CyRTPRL] = 2;
2697 base_addr[CyRTPRH] = 0;
2698
2699 base_addr[CyMSVR1] = CyRTS;
2700 base_addr[CyMSVR2] = CyDTR;
2701
2702 base_addr[CyIER] = CyRxData;
2703
2704 local_irq_restore(flags);
2705
2706} /* debug_setup */
2707
2708#endif
2709
2710MODULE_LICENSE("GPL"); 2489MODULE_LICENSE("GPL");