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authorChris Wilson <chris@chris-wilson.co.uk>2010-10-22 09:59:29 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-22 10:04:09 -0400
commit85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181 (patch)
treee0fdb8cf1c837c9f9365e385346d353ca0cc80d5 /drivers/char/agp/intel-gtt.c
parent878a3c37d36142a192bdf5b6bfcf920832f431d7 (diff)
agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
-rw-r--r--drivers/char/agp/intel-gtt.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0c8ff6d8824..6b6760ea243 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1211,13 +1211,13 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1211 u32 pte_flags; 1211 u32 pte_flags;
1212 1212
1213 if (type_mask == AGP_USER_UNCACHED_MEMORY) 1213 if (type_mask == AGP_USER_UNCACHED_MEMORY)
1214 pte_flags = GEN6_PTE_UNCACHED; 1214 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1215 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1215 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1216 pte_flags = GEN6_PTE_LLC; 1216 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1217 if (gfdt) 1217 if (gfdt)
1218 pte_flags |= GEN6_PTE_GFDT; 1218 pte_flags |= GEN6_PTE_GFDT;
1219 } else { /* set 'normal'/'cached' to LLC by default */ 1219 } else { /* set 'normal'/'cached' to LLC by default */
1220 pte_flags = GEN6_PTE_LLC_MLC; 1220 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1221 if (gfdt) 1221 if (gfdt)
1222 pte_flags |= GEN6_PTE_GFDT; 1222 pte_flags |= GEN6_PTE_GFDT;
1223 } 1223 }