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authorThomas Gleixner <tglx@linutronix.de>2010-04-13 08:12:17 -0400
committerThomas Gleixner <tglx@linutronix.de>2010-04-13 08:12:17 -0400
commit7c7145f6acc68100dbdc5d3c5c64fe3af1c99c89 (patch)
tree5e93e3eb4787229032f1df222fa490112f4b0c32 /drivers/char/agp/intel-agp.c
parent92d6b71ab906be706f3679353b30a8d2c3831144 (diff)
parent0d0fb0f9c5fddef4a10242fe3337f00f528a3099 (diff)
Merge branch 'linus' into irq/core
Reason: Get the upstream IRQF_DISABLED related changes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/char/agp/intel-agp.c')
-rw-r--r--drivers/char/agp/intel-agp.c35
1 files changed, 32 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a3e10dc7cc2..d41331bc2aa 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -4,6 +4,7 @@
4 4
5#include <linux/module.h> 5#include <linux/module.h>
6#include <linux/pci.h> 6#include <linux/pci.h>
7#include <linux/slab.h>
7#include <linux/init.h> 8#include <linux/init.h>
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9#include <linux/pagemap.h> 10#include <linux/pagemap.h>
@@ -97,6 +98,9 @@ EXPORT_SYMBOL(intel_agp_enabled);
97#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ 98#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) 99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
99 100
101#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
103
100#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ 104#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
101 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 105 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
102 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 106 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
@@ -107,8 +111,7 @@ EXPORT_SYMBOL(intel_agp_enabled);
107 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ 111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
108 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ 112 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
109 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ 113 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
110 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ 114 IS_SNB)
111 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
112 115
113extern int agp_memory_reserved; 116extern int agp_memory_reserved;
114 117
@@ -175,6 +178,10 @@ extern int agp_memory_reserved;
175#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 178#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
176#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 179#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
177#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 180#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
181#define SNB_GTT_SIZE_0M (0 << 8)
182#define SNB_GTT_SIZE_1M (1 << 8)
183#define SNB_GTT_SIZE_2M (2 << 8)
184#define SNB_GTT_SIZE_MASK (3 << 8)
178 185
179static const struct aper_size_info_fixed intel_i810_sizes[] = 186static const struct aper_size_info_fixed intel_i810_sizes[] =
180{ 187{
@@ -1200,6 +1207,9 @@ static void intel_i9xx_setup_flush(void)
1200 if (intel_private.ifp_resource.start) 1207 if (intel_private.ifp_resource.start)
1201 return; 1208 return;
1202 1209
1210 if (IS_SNB)
1211 return;
1212
1203 /* setup a resource for this object */ 1213 /* setup a resource for this object */
1204 intel_private.ifp_resource.name = "Intel Flush Page"; 1214 intel_private.ifp_resource.name = "Intel Flush Page";
1205 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1215 intel_private.ifp_resource.flags = IORESOURCE_MEM;
@@ -1438,6 +1448,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1438 1448
1439static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1449static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1440{ 1450{
1451 u16 snb_gmch_ctl;
1452
1441 switch (agp_bridge->dev->device) { 1453 switch (agp_bridge->dev->device) {
1442 case PCI_DEVICE_ID_INTEL_GM45_HB: 1454 case PCI_DEVICE_ID_INTEL_GM45_HB:
1443 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: 1455 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
@@ -1449,9 +1461,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1449 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: 1461 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1450 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: 1462 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1451 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: 1463 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1464 *gtt_offset = *gtt_size = MB(2);
1465 break;
1452 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: 1466 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1453 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: 1467 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1454 *gtt_offset = *gtt_size = MB(2); 1468 *gtt_offset = MB(2);
1469
1470 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1471 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1472 default:
1473 case SNB_GTT_SIZE_0M:
1474 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1475 *gtt_size = MB(0);
1476 break;
1477 case SNB_GTT_SIZE_1M:
1478 *gtt_size = MB(1);
1479 break;
1480 case SNB_GTT_SIZE_2M:
1481 *gtt_size = MB(2);
1482 break;
1483 }
1455 break; 1484 break;
1456 default: 1485 default:
1457 *gtt_offset = *gtt_size = KB(512); 1486 *gtt_offset = *gtt_size = KB(512);