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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2012-09-14 05:20:34 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-19 10:53:26 -0400
commit0ee7261c9212dbaf72d510e37f6c5b849d1847f0 (patch)
treecd9902a94a286aab6e337c31f8ec2768250e5b17 /drivers/bus
parent46ca6811534e66e7b3967512efe8259021cd5488 (diff)
drivers: bus: Move the OMAP interconnect driver to drivers/bus/
OMAP interconnect drivers are used for the interconnect error handling. Since they are bus driver, lets move it to newly created drivers/bus. Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/Kconfig6
-rw-r--r--drivers/bus/Makefile3
-rw-r--r--drivers/bus/omap_l3_noc.c266
-rw-r--r--drivers/bus/omap_l3_noc.h176
-rw-r--r--drivers/bus/omap_l3_smx.c297
-rw-r--r--drivers/bus/omap_l3_smx.h338
6 files changed, 1086 insertions, 0 deletions
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 6270415107d..bbec35d21fe 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -12,4 +12,10 @@ config OMAP_OCP2SCP
12 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via 12 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
13 OCP2SCP. 13 OCP2SCP.
14 14
15config OMAP_INTERCONNECT
16 tristate "OMAP INTERCONNECT DRIVER"
17 depends on ARCH_OMAP2PLUS
18
19 help
20 Driver to enable OMAP interconnect error handling driver.
15endmenu 21endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 0ec50bc43d7..45d997c8545 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -3,3 +3,6 @@
3# 3#
4 4
5obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o 5obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
6
7# Interconnect bus driver for OMAP SoCs.
8obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
new file mode 100644
index 00000000000..d15225ff5c4
--- /dev/null
+++ b/drivers/bus/omap_l3_noc.c
@@ -0,0 +1,266 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/platform_device.h>
27#include <linux/interrupt.h>
28#include <linux/kernel.h>
29#include <linux/slab.h>
30
31#include "omap_l3_noc.h"
32
33/*
34 * Interrupt Handler for L3 error detection.
35 * 1) Identify the L3 clockdomain partition to which the error belongs to.
36 * 2) Identify the slave where the error information is logged
37 * 3) Print the logged information.
38 * 4) Add dump stack to provide kernel trace.
39 *
40 * Two Types of errors :
41 * 1) Custom errors in L3 :
42 * Target like DMM/FW/EMIF generates SRESP=ERR error
43 * 2) Standard L3 error:
44 * - Unsupported CMD.
45 * L3 tries to access target while it is idle
46 * - OCP disconnect.
47 * - Address hole error:
48 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
49 * do not have connectivity, the error is logged in
50 * their default target which is DMM2.
51 *
52 * On High Secure devices, firewall errors are possible and those
53 * can be trapped as well. But the trapping is implemented as part
54 * secure software and hence need not be implemented here.
55 */
56static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
57{
58
59 struct omap4_l3 *l3 = _l3;
60 int inttype, i, k;
61 int err_src = 0;
62 u32 std_err_main, err_reg, clear, masterid;
63 void __iomem *base, *l3_targ_base;
64 char *target_name, *master_name = "UN IDENTIFIED";
65
66 /* Get the Type of interrupt */
67 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
68
69 for (i = 0; i < L3_MODULES; i++) {
70 /*
71 * Read the regerr register of the clock domain
72 * to determine the source
73 */
74 base = l3->l3_base[i];
75 err_reg = __raw_readl(base + l3_flagmux[i] +
76 + L3_FLAGMUX_REGERR0 + (inttype << 3));
77
78 /* Get the corresponding error and analyse */
79 if (err_reg) {
80 /* Identify the source from control status register */
81 err_src = __ffs(err_reg);
82
83 /* Read the stderrlog_main_source from clk domain */
84 l3_targ_base = base + *(l3_targ[i] + err_src);
85 std_err_main = __raw_readl(l3_targ_base +
86 L3_TARG_STDERRLOG_MAIN);
87 masterid = __raw_readl(l3_targ_base +
88 L3_TARG_STDERRLOG_MSTADDR);
89
90 switch (std_err_main & CUSTOM_ERROR) {
91 case STANDARD_ERROR:
92 target_name =
93 l3_targ_inst_name[i][err_src];
94 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
95 target_name,
96 __raw_readl(l3_targ_base +
97 L3_TARG_STDERRLOG_SLVOFSLSB));
98 /* clear the std error log*/
99 clear = std_err_main | CLEAR_STDERR_LOG;
100 writel(clear, l3_targ_base +
101 L3_TARG_STDERRLOG_MAIN);
102 break;
103
104 case CUSTOM_ERROR:
105 target_name =
106 l3_targ_inst_name[i][err_src];
107 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
108 if (masterid == l3_masters[k].id)
109 master_name =
110 l3_masters[k].name;
111 }
112 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
113 master_name, target_name);
114 /* clear the std error log*/
115 clear = std_err_main | CLEAR_STDERR_LOG;
116 writel(clear, l3_targ_base +
117 L3_TARG_STDERRLOG_MAIN);
118 break;
119
120 default:
121 /* Nothing to be handled here as of now */
122 break;
123 }
124 /* Error found so break the for loop */
125 break;
126 }
127 }
128 return IRQ_HANDLED;
129}
130
131static int __devinit omap4_l3_probe(struct platform_device *pdev)
132{
133 static struct omap4_l3 *l3;
134 struct resource *res;
135 int ret;
136
137 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
138 if (!l3)
139 return -ENOMEM;
140
141 platform_set_drvdata(pdev, l3);
142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
143 if (!res) {
144 dev_err(&pdev->dev, "couldn't find resource 0\n");
145 ret = -ENODEV;
146 goto err0;
147 }
148
149 l3->l3_base[0] = ioremap(res->start, resource_size(res));
150 if (!l3->l3_base[0]) {
151 dev_err(&pdev->dev, "ioremap failed\n");
152 ret = -ENOMEM;
153 goto err0;
154 }
155
156 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
157 if (!res) {
158 dev_err(&pdev->dev, "couldn't find resource 1\n");
159 ret = -ENODEV;
160 goto err1;
161 }
162
163 l3->l3_base[1] = ioremap(res->start, resource_size(res));
164 if (!l3->l3_base[1]) {
165 dev_err(&pdev->dev, "ioremap failed\n");
166 ret = -ENOMEM;
167 goto err1;
168 }
169
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
171 if (!res) {
172 dev_err(&pdev->dev, "couldn't find resource 2\n");
173 ret = -ENODEV;
174 goto err2;
175 }
176
177 l3->l3_base[2] = ioremap(res->start, resource_size(res));
178 if (!l3->l3_base[2]) {
179 dev_err(&pdev->dev, "ioremap failed\n");
180 ret = -ENOMEM;
181 goto err2;
182 }
183
184 /*
185 * Setup interrupt Handlers
186 */
187 l3->debug_irq = platform_get_irq(pdev, 0);
188 ret = request_irq(l3->debug_irq,
189 l3_interrupt_handler,
190 IRQF_DISABLED, "l3-dbg-irq", l3);
191 if (ret) {
192 pr_crit("L3: request_irq failed to register for 0x%x\n",
193 OMAP44XX_IRQ_L3_DBG);
194 goto err3;
195 }
196
197 l3->app_irq = platform_get_irq(pdev, 1);
198 ret = request_irq(l3->app_irq,
199 l3_interrupt_handler,
200 IRQF_DISABLED, "l3-app-irq", l3);
201 if (ret) {
202 pr_crit("L3: request_irq failed to register for 0x%x\n",
203 OMAP44XX_IRQ_L3_APP);
204 goto err4;
205 }
206
207 return 0;
208
209err4:
210 free_irq(l3->debug_irq, l3);
211err3:
212 iounmap(l3->l3_base[2]);
213err2:
214 iounmap(l3->l3_base[1]);
215err1:
216 iounmap(l3->l3_base[0]);
217err0:
218 kfree(l3);
219 return ret;
220}
221
222static int __devexit omap4_l3_remove(struct platform_device *pdev)
223{
224 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
225
226 free_irq(l3->app_irq, l3);
227 free_irq(l3->debug_irq, l3);
228 iounmap(l3->l3_base[0]);
229 iounmap(l3->l3_base[1]);
230 iounmap(l3->l3_base[2]);
231 kfree(l3);
232
233 return 0;
234}
235
236#if defined(CONFIG_OF)
237static const struct of_device_id l3_noc_match[] = {
238 {.compatible = "ti,omap4-l3-noc", },
239 {},
240};
241MODULE_DEVICE_TABLE(of, l3_noc_match);
242#else
243#define l3_noc_match NULL
244#endif
245
246static struct platform_driver omap4_l3_driver = {
247 .probe = omap4_l3_probe,
248 .remove = __devexit_p(omap4_l3_remove),
249 .driver = {
250 .name = "omap_l3_noc",
251 .owner = THIS_MODULE,
252 .of_match_table = l3_noc_match,
253 },
254};
255
256static int __init omap4_l3_init(void)
257{
258 return platform_driver_register(&omap4_l3_driver);
259}
260postcore_initcall_sync(omap4_l3_init);
261
262static void __exit omap4_l3_exit(void)
263{
264 platform_driver_unregister(&omap4_l3_driver);
265}
266module_exit(omap4_l3_exit);
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
new file mode 100644
index 00000000000..a6ce34dc481
--- /dev/null
+++ b/drivers/bus/omap_l3_noc.h
@@ -0,0 +1,176 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26#define L3_MODULES 3
27#define CLEAR_STDERR_LOG (1 << 31)
28#define CUSTOM_ERROR 0x2
29#define STANDARD_ERROR 0x0
30#define INBAND_ERROR 0x0
31#define L3_APPLICATION_ERROR 0x0
32#define L3_DEBUG_ERROR 0x1
33
34/* L3 TARG register offsets */
35#define L3_TARG_STDERRLOG_MAIN 0x48
36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
37#define L3_TARG_STDERRLOG_MSTADDR 0x68
38#define L3_FLAGMUX_REGERR0 0xc
39
40#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
41
42static u32 l3_flagmux[L3_MODULES] = {
43 0x500,
44 0x1000,
45 0X0200
46};
47
48/* L3 Target standard Error register offsets */
49static u32 l3_targ_inst_clk1[] = {
50 0x100, /* DMM1 */
51 0x200, /* DMM2 */
52 0x300, /* ABE */
53 0x400, /* L4CFG */
54 0x600, /* CLK2 PWR DISC */
55 0x0, /* Host CLK1 */
56 0x900 /* L4 Wakeup */
57};
58
59static u32 l3_targ_inst_clk2[] = {
60 0x500, /* CORTEX M3 */
61 0x300, /* DSS */
62 0x100, /* GPMC */
63 0x400, /* ISS */
64 0x700, /* IVAHD */
65 0xD00, /* missing in TRM corresponds to AES1*/
66 0x900, /* L4 PER0*/
67 0x200, /* OCMRAM */
68 0x100, /* missing in TRM corresponds to GPMC sERROR*/
69 0x600, /* SGX */
70 0x800, /* SL2 */
71 0x1600, /* C2C */
72 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
73 0xF00, /* missing in TRM corrsponds to SHA1*/
74 0xE00, /* missing in TRM corresponds to AES2*/
75 0xC00, /* L4 PER3 */
76 0xA00, /* L4 PER1*/
77 0xB00, /* L4 PER2*/
78 0x0, /* HOST CLK2 */
79 0x1800, /* CAL */
80 0x1700 /* LLI */
81};
82
83static u32 l3_targ_inst_clk3[] = {
84 0x0100 /* EMUSS */,
85 0x0300, /* DEBUGSS_CT_TBR */
86 0x0 /* HOST CLK3 */
87};
88
89static struct l3_masters_data {
90 u32 id;
91 char name[10];
92} l3_masters[] = {
93 { 0x0 , "MPU"},
94 { 0x10, "CS_ADP"},
95 { 0x14, "xxx"},
96 { 0x20, "DSP"},
97 { 0x30, "IVAHD"},
98 { 0x40, "ISS"},
99 { 0x44, "DucatiM3"},
100 { 0x48, "FaceDetect"},
101 { 0x50, "SDMA_Rd"},
102 { 0x54, "SDMA_Wr"},
103 { 0x58, "xxx"},
104 { 0x5C, "xxx"},
105 { 0x60, "SGX"},
106 { 0x70, "DSS"},
107 { 0x80, "C2C"},
108 { 0x88, "xxx"},
109 { 0x8C, "xxx"},
110 { 0x90, "HSI"},
111 { 0xA0, "MMC1"},
112 { 0xA4, "MMC2"},
113 { 0xA8, "MMC6"},
114 { 0xB0, "UNIPRO1"},
115 { 0xC0, "USBHOSTHS"},
116 { 0xC4, "USBOTGHS"},
117 { 0xC8, "USBHOSTFS"}
118};
119
120static char *l3_targ_inst_name[L3_MODULES][21] = {
121 {
122 "DMM1",
123 "DMM2",
124 "ABE",
125 "L4CFG",
126 "CLK2 PWR DISC",
127 "HOST CLK1",
128 "L4 WAKEUP"
129 },
130 {
131 "CORTEX M3" ,
132 "DSS ",
133 "GPMC ",
134 "ISS ",
135 "IVAHD ",
136 "AES1",
137 "L4 PER0",
138 "OCMRAM ",
139 "GPMC sERROR",
140 "SGX ",
141 "SL2 ",
142 "C2C ",
143 "PWR DISC CLK1",
144 "SHA1",
145 "AES2",
146 "L4 PER3",
147 "L4 PER1",
148 "L4 PER2",
149 "HOST CLK2",
150 "CAL",
151 "LLI"
152 },
153 {
154 "EMUSS",
155 "DEBUG SOURCE",
156 "HOST CLK3"
157 },
158};
159
160static u32 *l3_targ[L3_MODULES] = {
161 l3_targ_inst_clk1,
162 l3_targ_inst_clk2,
163 l3_targ_inst_clk3,
164};
165
166struct omap4_l3 {
167 struct device *dev;
168 struct clk *ick;
169
170 /* memory base */
171 void __iomem *l3_base[L3_MODULES];
172
173 int debug_irq;
174 int app_irq;
175};
176#endif
diff --git a/drivers/bus/omap_l3_smx.c b/drivers/bus/omap_l3_smx.c
new file mode 100644
index 00000000000..acc216491b8
--- /dev/null
+++ b/drivers/bus/omap_l3_smx.c
@@ -0,0 +1,297 @@
1/*
2 * OMAP3XXX L3 Interconnect Driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include "omap_l3_smx.h"
31
32static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
33{
34 return __raw_readll(base + reg);
35}
36
37static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
38{
39 __raw_writell(value, base + reg);
40}
41
42static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
43{
44 return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
45}
46
47static inline u32 omap3_l3_decode_addr(u64 error_addr)
48{
49 return error_addr & 0xffffffff;
50}
51
52static inline unsigned omap3_l3_decode_cmd(u64 error)
53{
54 return (error & 0x07) >> L3_ERROR_LOG_CMD;
55}
56
57static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
58{
59 return (error & 0xff00) >> L3_ERROR_LOG_INITID;
60}
61
62static inline unsigned omap3_l3_decode_req_info(u64 error)
63{
64 return (error >> 32) & 0xffff;
65}
66
67static char *omap3_l3_code_string(u8 code)
68{
69 switch (code) {
70 case OMAP_L3_CODE_NOERROR:
71 return "No Error";
72 case OMAP_L3_CODE_UNSUP_CMD:
73 return "Unsupported Command";
74 case OMAP_L3_CODE_ADDR_HOLE:
75 return "Address Hole";
76 case OMAP_L3_CODE_PROTECT_VIOLATION:
77 return "Protection Violation";
78 case OMAP_L3_CODE_IN_BAND_ERR:
79 return "In-band Error";
80 case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
81 return "Request Timeout Not Accepted";
82 case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
83 return "Request Timeout, no response";
84 default:
85 return "UNKNOWN error";
86 }
87}
88
89static char *omap3_l3_initiator_string(u8 initid)
90{
91 switch (initid) {
92 case OMAP_L3_LCD:
93 return "LCD";
94 case OMAP_L3_SAD2D:
95 return "SAD2D";
96 case OMAP_L3_IA_MPU_SS_1:
97 case OMAP_L3_IA_MPU_SS_2:
98 case OMAP_L3_IA_MPU_SS_3:
99 case OMAP_L3_IA_MPU_SS_4:
100 case OMAP_L3_IA_MPU_SS_5:
101 return "MPU";
102 case OMAP_L3_IA_IVA_SS_1:
103 case OMAP_L3_IA_IVA_SS_2:
104 case OMAP_L3_IA_IVA_SS_3:
105 return "IVA_SS";
106 case OMAP_L3_IA_IVA_SS_DMA_1:
107 case OMAP_L3_IA_IVA_SS_DMA_2:
108 case OMAP_L3_IA_IVA_SS_DMA_3:
109 case OMAP_L3_IA_IVA_SS_DMA_4:
110 case OMAP_L3_IA_IVA_SS_DMA_5:
111 case OMAP_L3_IA_IVA_SS_DMA_6:
112 return "IVA_SS_DMA";
113 case OMAP_L3_IA_SGX:
114 return "SGX";
115 case OMAP_L3_IA_CAM_1:
116 case OMAP_L3_IA_CAM_2:
117 case OMAP_L3_IA_CAM_3:
118 return "CAM";
119 case OMAP_L3_IA_DAP:
120 return "DAP";
121 case OMAP_L3_SDMA_WR_1:
122 case OMAP_L3_SDMA_WR_2:
123 return "SDMA_WR";
124 case OMAP_L3_SDMA_RD_1:
125 case OMAP_L3_SDMA_RD_2:
126 case OMAP_L3_SDMA_RD_3:
127 case OMAP_L3_SDMA_RD_4:
128 return "SDMA_RD";
129 case OMAP_L3_USBOTG:
130 return "USB_OTG";
131 case OMAP_L3_USBHOST:
132 return "USB_HOST";
133 default:
134 return "UNKNOWN Initiator";
135 }
136}
137
138/*
139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 *
141 * @base: register block base address
142 * @error: L3_ERROR_LOG register of our block
143 *
144 * Called in hard-irq context. Caller should take care of locking
145 *
146 * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
147 * Analysis Sequence, we are following that sequence here, please
148 * refer to that Figure for more information on the subject.
149 */
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr)
152{
153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr);
157
158 pr_err("%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "", address);
162 WARN_ON(1);
163
164 return IRQ_HANDLED;
165}
166
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{
169 struct omap3_l3 *l3 = _l3;
170 u64 status, clear;
171 u64 error;
172 u64 error_addr;
173 u64 err_source = 0;
174 void __iomem *base;
175 int int_type;
176 irqreturn_t ret = IRQ_NONE;
177
178 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
179 if (!int_type) {
180 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
181 /*
182 * if we have a timeout error, there's nothing we can
183 * do besides rebooting the board. So let's BUG on any
184 * of such errors and handle the others. timeout error
185 * is severe and not expected to occur.
186 */
187 BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
188 } else {
189 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
190 /* No timeout error for debug sources */
191 }
192
193 /* identify the error source */
194 err_source = __ffs(status);
195
196 base = l3->rt + omap3_l3_bases[int_type][err_source];
197 error = omap3_l3_readll(base, L3_ERROR_LOG);
198 if (error) {
199 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
200 ret |= omap3_l3_block_irq(l3, error, error_addr);
201 }
202
203 /* Clear the status register */
204 clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
205 L3_AGENT_STATUS_CLEAR_TA;
206 omap3_l3_writell(base, L3_AGENT_STATUS, clear);
207
208 /* clear the error log register */
209 omap3_l3_writell(base, L3_ERROR_LOG, error);
210
211 return ret;
212}
213
214static int __init omap3_l3_probe(struct platform_device *pdev)
215{
216 struct omap3_l3 *l3;
217 struct resource *res;
218 int ret;
219
220 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
221 if (!l3)
222 return -ENOMEM;
223
224 platform_set_drvdata(pdev, l3);
225
226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227 if (!res) {
228 dev_err(&pdev->dev, "couldn't find resource\n");
229 ret = -ENODEV;
230 goto err0;
231 }
232 l3->rt = ioremap(res->start, resource_size(res));
233 if (!l3->rt) {
234 dev_err(&pdev->dev, "ioremap failed\n");
235 ret = -ENOMEM;
236 goto err0;
237 }
238
239 l3->debug_irq = platform_get_irq(pdev, 0);
240 ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
241 IRQF_DISABLED | IRQF_TRIGGER_RISING,
242 "l3-debug-irq", l3);
243 if (ret) {
244 dev_err(&pdev->dev, "couldn't request debug irq\n");
245 goto err1;
246 }
247
248 l3->app_irq = platform_get_irq(pdev, 1);
249 ret = request_irq(l3->app_irq, omap3_l3_app_irq,
250 IRQF_DISABLED | IRQF_TRIGGER_RISING,
251 "l3-app-irq", l3);
252 if (ret) {
253 dev_err(&pdev->dev, "couldn't request app irq\n");
254 goto err2;
255 }
256
257 return 0;
258
259err2:
260 free_irq(l3->debug_irq, l3);
261err1:
262 iounmap(l3->rt);
263err0:
264 kfree(l3);
265 return ret;
266}
267
268static int __exit omap3_l3_remove(struct platform_device *pdev)
269{
270 struct omap3_l3 *l3 = platform_get_drvdata(pdev);
271
272 free_irq(l3->app_irq, l3);
273 free_irq(l3->debug_irq, l3);
274 iounmap(l3->rt);
275 kfree(l3);
276
277 return 0;
278}
279
280static struct platform_driver omap3_l3_driver = {
281 .remove = __exit_p(omap3_l3_remove),
282 .driver = {
283 .name = "omap_l3_smx",
284 },
285};
286
287static int __init omap3_l3_init(void)
288{
289 return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
290}
291postcore_initcall_sync(omap3_l3_init);
292
293static void __exit omap3_l3_exit(void)
294{
295 platform_driver_unregister(&omap3_l3_driver);
296}
297module_exit(omap3_l3_exit);
diff --git a/drivers/bus/omap_l3_smx.h b/drivers/bus/omap_l3_smx.h
new file mode 100644
index 00000000000..4f3cebca417
--- /dev/null
+++ b/drivers/bus/omap_l3_smx.h
@@ -0,0 +1,338 @@
1/*
2 * OMAP3XXX L3 Interconnect Driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26
27/* Register definitions. All 64-bit wide */
28#define L3_COMPONENT 0x000
29#define L3_CORE 0x018
30#define L3_AGENT_CONTROL 0x020
31#define L3_AGENT_STATUS 0x028
32#define L3_ERROR_LOG 0x058
33
34#define L3_ERROR_LOG_MULTI (1 << 31)
35#define L3_ERROR_LOG_SECONDARY (1 << 30)
36
37#define L3_ERROR_LOG_ADDR 0x060
38
39/* Register definitions for Sideband Interconnect */
40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510
42
43static const u64 shift = 1;
44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
47#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48#define L3_STATUS_0_IVAIA_BRST (shift << 6)
49#define L3_STATUS_0_IVAIA_RSP (shift << 7)
50#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51#define L3_STATUS_0_SGXIA_BRST (shift << 9)
52#define L3_STATUS_0_SGXIA_RSP (shift << 10)
53#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
54#define L3_STATUS_0_CAMIA_BRST (shift << 12)
55#define L3_STATUS_0_CAMIA_RSP (shift << 13)
56#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
57#define L3_STATUS_0_DISPIA_BRST (shift << 15)
58#define L3_STATUS_0_DISPIA_RSP (shift << 16)
59#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
60#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
61#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
62#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
63#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
64#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
65#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
66#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
67#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
68#define L3_STATUS_0_SMSTA_REQ (shift << 48)
69#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
70#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
71#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
72#define L3_STATUS_0_IVATA_REQ (shift << 54)
73#define L3_STATUS_0_SGXTA_REQ (shift << 55)
74#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
75#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
76#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
77#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ)
108
109#define L3_SI_FLAG_STATUS_1 0x530
110
111#define L3_STATUS_1_MPU_DATAIA (1 << 0)
112#define L3_STATUS_1_DAPIA0 (1 << 3)
113#define L3_STATUS_1_DAPIA1 (1 << 4)
114#define L3_STATUS_1_IVAIA (1 << 6)
115
116#define L3_PM_ERROR_LOG 0x020
117#define L3_PM_CONTROL 0x028
118#define L3_PM_ERROR_CLEAR_SINGLE 0x030
119#define L3_PM_ERROR_CLEAR_MULTI 0x038
120#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
121#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
122#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
123#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
124
125/* L3 error log bit fields. Common for IA and TA */
126#define L3_ERROR_LOG_CODE 24
127#define L3_ERROR_LOG_INITID 8
128#define L3_ERROR_LOG_CMD 0
129
130/* L3 agent status bit fields. */
131#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
132#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
133
134#define OMAP34xx_IRQ_L3_APP 10
135#define L3_APPLICATION_ERROR 0x0
136#define L3_DEBUG_ERROR 0x1
137
138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
156 OMAP_L3_IA_IVA_SS_DMA_3 = 17,
157 OMAP_L3_IA_IVA_SS_DMA_4 = 16,
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1,
180};
181
182enum omap3_l3_code {
183 OMAP_L3_CODE_NOERROR = 0,
184 OMAP_L3_CODE_UNSUP_CMD = 1,
185 OMAP_L3_CODE_ADDR_HOLE = 2,
186 OMAP_L3_CODE_PROTECT_VIOLATION = 3,
187 OMAP_L3_CODE_IN_BAND_ERR = 4,
188 /* codes 5 and 6 are reserved */
189 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
190 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
191 /* codes 9 - 15 are also reserved */
192};
193
194struct omap3_l3 {
195 struct device *dev;
196 struct clk *ick;
197
198 /* memory base*/
199 void __iomem *rt;
200
201 int debug_irq;
202 int app_irq;
203
204 /* true when and inband functional error occurs */
205 unsigned inband:1;
206};
207
208/* offsets for l3 agents in order with the Flag status register */
209static unsigned int omap3_l3_app_bases[] = {
210 /* MPU IA */
211 0x1400,
212 0x1400,
213 0x1400,
214 /* RESERVED */
215 0,
216 0,
217 0,
218 /* IVA 2.2 IA */
219 0x1800,
220 0x1800,
221 0x1800,
222 /* SGX IA */
223 0x1c00,
224 0x1c00,
225 /* RESERVED */
226 0,
227 /* CAMERA IA */
228 0x5800,
229 0x5800,
230 0x5800,
231 /* DISPLAY IA */
232 0x5400,
233 0x5400,
234 /* RESERVED */
235 0,
236 /*SDMA RD IA */
237 0x4c00,
238 0x4c00,
239 /* RESERVED */
240 0,
241 /* SDMA WR IA */
242 0x5000,
243 0x5000,
244 /* RESERVED */
245 0,
246 /* USB OTG IA */
247 0x4400,
248 0x4400,
249 0x4400,
250 /* USB HOST IA */
251 0x4000,
252 0x4000,
253 /* RESERVED */
254 0,
255 0,
256 0,
257 0,
258 /* SAD2D IA */
259 0x3000,
260 0x3000,
261 0x3000,
262 /* RESERVED */
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 /* SMA TA */
276 0x2000,
277 /* GPMC TA */
278 0x2400,
279 /* OCM RAM TA */
280 0x2800,
281 /* OCM ROM TA */
282 0x2C00,
283 /* L4 CORE TA */
284 0x6800,
285 /* L4 PER TA */
286 0x6c00,
287 /* IVA 2.2 TA */
288 0x6000,
289 /* SGX TA */
290 0x6400,
291 /* L4 EMU TA */
292 0x7000,
293 /* GPMC TA */
294 0x2400,
295 /* L4 CORE TA */
296 0x6800,
297 /* L4 PER TA */
298 0x6c00,
299 /* L4 EMU TA */
300 0x7000,
301 /* MAD2D TA */
302 0x3400,
303 /* RESERVED */
304 0,
305 0,
306};
307
308static unsigned int omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */
310 0x1400,
311 /* RESERVED */
312 0,
313 0,
314 /* DAP IA */
315 0x5c00,
316 0x5c00,
317 /* RESERVED */
318 0,
319 /* IVA 2.2 IA */
320 0x1800,
321 /* REST RESERVED */
322};
323
324static u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases,
326 omap3_l3_debug_bases,
327};
328
329/*
330 * REVISIT define __raw_readll/__raw_writell here, but move them to
331 * <asm/io.h> at some point
332 */
333#define __raw_writell(v, a) (__chk_io_ptr(a), \
334 *(volatile u64 __force *)(a) = (v))
335#define __raw_readll(a) (__chk_io_ptr(a), \
336 *(volatile u64 __force *)(a))
337
338#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-24 14:00:22 -0400