[POWERPC] Fix the UCC rx/tx clock of QE

MPC8323EMDS board ethernet interface with RMII uses the CLK16 divisor
for the rx and tx clock, but the ucc_set_qe_mux_rxtx() function doesn't
handle the CLK16 setting of the CMXUCR3 and CMXUCR4 registers.  This
fixes it.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index 916c9e5df57..ac12a44d516 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -207,6 +207,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
                 case QE_CLK18:  source = 8; break;
                 case QE_CLK7:   source = 9; break;
                 case QE_CLK8:   source = 10; break;
+                case QE_CLK16:  source = 11; break;
                 default:        source = -1; break;
                 }
                 break;
@@ -222,6 +223,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
                 case QE_CLK22:  source = 8; break;
                 case QE_CLK7:   source = 9; break;
                 case QE_CLK8:   source = 10; break;
+                case QE_CLK16:  source = 11; break;
                 default:        source = -1; break;
                 }
                 break;