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authorArnd Bergmann <arnd@arndb.de>2012-03-15 17:07:57 -0400
committerArnd Bergmann <arnd@arndb.de>2012-03-15 17:07:57 -0400
commite7051e9dab77ddeaddbe12364939ae239d92ca73 (patch)
treeb1855cb663f64a374277df1a909cbac1ecf15fbf /arch
parent38abdcd0d0689aaca94e740ac67a952c7918caef (diff)
parent5da30bb6d902a36265e74f7141a904b19ec25bd4 (diff)
Merge branch 'samsung/exynos5' into next/soc2
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts26
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi413
-rw-r--r--arch/arm/mach-exynos/Kconfig32
-rw-r--r--arch/arm/mach-exynos/Makefile8
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1576
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.h30
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c48
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c32
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1247
-rw-r--r--arch/arm/mach-exynos/clock.c1564
-rw-r--r--arch/arm/mach-exynos/common.c449
-rw-r--r--arch/arm/mach-exynos/common.h40
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c4
-rw-r--r--arch/arm/mach-exynos/dev-audio.c4
-rw-r--r--arch/arm/mach-exynos/dev-uart.c78
-rw-r--r--arch/arm/mach-exynos/dma.c125
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S9
-rw-r--r--arch/arm/mach-exynos/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h595
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h44
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h478
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h17
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c78
-rw-r--r--arch/arm/mach-exynos/mach-origen.c2
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c2
-rw-r--r--arch/arm/mach-exynos/mct.c23
-rw-r--r--arch/arm/mach-exynos/platsmp.c9
-rw-r--r--arch/arm/mach-exynos/pm.c40
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c9
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-lpc32xx/irq.c25
-rw-r--r--arch/arm/mach-lpc32xx/serial.c20
-rw-r--r--arch/arm/mach-mmp/aspenite.c1
-rw-r--r--arch/arm/mach-mmp/pxa168.c1
-rw-r--r--arch/arm/mach-mmp/tavorevb.c1
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap2/Kconfig4
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c2
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c5
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c52
-rw-r--r--arch/arm/mach-omap2/hsmmc.c6
-rw-r--r--arch/arm/mach-omap2/io.c1
-rw-r--r--arch/arm/mach-omap2/mailbox.c13
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap4-common.c25
-rw-r--r--arch/arm/mach-omap2/pm.c3
-rw-r--r--arch/arm/mach-omap2/usb-host.c6
-rw-r--r--arch/arm/mach-pxa/hx4700.c25
-rw-r--r--arch/arm/mach-pxa/pxa25x.c1
-rw-r--r--arch/arm/mach-pxa/pxa27x.c1
-rw-r--r--arch/arm/mach-pxa/saarb.c1
-rw-r--r--arch/arm/mach-pxa/sharpsl_pm.c3
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c5
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c12
-rw-r--r--arch/arm/mach-s3c2416/clock.c6
-rw-r--r--arch/arm/mach-s3c2416/mach-smdk2416.c8
-rw-r--r--arch/arm/mach-s3c2440/mach-gta02.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c12
-rw-r--r--arch/arm/mach-s3c64xx/common.h2
-rw-r--r--arch/arm/mach-s3c64xx/irq-pm.c2
-rw-r--r--arch/arm/mach-s5p64x0/clock.c11
-rw-r--r--arch/arm/mach-s5p64x0/dma.c12
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h7
-rw-r--r--arch/arm/mach-s5pc100/clock.c28
-rw-r--r--arch/arm/mach-s5pc100/dma.c16
-rw-r--r--arch/arm/mach-s5pv210/dma.c16
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c2
-rw-r--r--arch/arm/plat-omap/common.c1
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h6
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c2
-rw-r--r--arch/arm/plat-s5p/Kconfig8
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/clock.c36
-rw-r--r--arch/arm/plat-s5p/irq-eint.c2
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c2
-rw-r--r--arch/arm/plat-s5p/irq-pm.c25
-rw-r--r--arch/arm/plat-samsung/devs.c13
-rw-r--r--arch/arm/plat-samsung/dma-ops.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c16
-rw-r--r--arch/openrisc/include/asm/ptrace.h8
-rw-r--r--arch/openrisc/kernel/init_task.c1
-rw-r--r--arch/openrisc/kernel/irq.c1
-rw-r--r--arch/openrisc/kernel/ptrace.c12
-rw-r--r--arch/parisc/Makefile4
-rw-r--r--arch/s390/Kconfig3
-rw-r--r--arch/s390/include/asm/compat.h7
-rw-r--r--arch/s390/kernel/crash_dump.c1
-rw-r--r--arch/s390/kernel/process.c1
-rw-r--r--arch/s390/kernel/ptrace.c2
-rw-r--r--arch/s390/kernel/setup.c2
-rw-r--r--arch/s390/kernel/signal.c1
-rw-r--r--arch/s390/mm/fault.c1
-rw-r--r--arch/s390/mm/init.c30
-rw-r--r--arch/s390/mm/mmap.c2
-rw-r--r--arch/x86/include/asm/perf_event.h8
-rw-r--r--arch/x86/kernel/cpu/intel_cacheinfo.c44
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd.c2
-rw-r--r--arch/x86/kernel/cpu/perf_event.h8
-rw-r--r--arch/x86/kernel/cpu/perf_event_amd.c37
-rw-r--r--arch/x86/kernel/entry_64.S9
-rw-r--r--arch/x86/kernel/microcode_amd.c1
-rw-r--r--arch/x86/kvm/svm.c5
-rw-r--r--arch/x86/xen/enlighten.c6
-rw-r--r--arch/x86/xen/mmu.c8
116 files changed, 5387 insertions, 2378 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb9166..a826ffca791 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
180machine-$(CONFIG_ARCH_S5PC100) := s5pc100 180machine-$(CONFIG_ARCH_S5PC100) := s5pc100
181machine-$(CONFIG_ARCH_S5PV210) := s5pv210 181machine-$(CONFIG_ARCH_S5PV210) := s5pv210
182machine-$(CONFIG_ARCH_EXYNOS4) := exynos 182machine-$(CONFIG_ARCH_EXYNOS4) := exynos
183machine-$(CONFIG_ARCH_EXYNOS5) := exynos
183machine-$(CONFIG_ARCH_SA1100) := sa1100 184machine-$(CONFIG_ARCH_SA1100) := sa1100
184machine-$(CONFIG_ARCH_SHARK) := shark 185machine-$(CONFIG_ARCH_SHARK) := shark
185machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 186machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 00000000000..399d17b231d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
1/*
2 * SAMSUNG SMDK5250 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5250.dtsi"
14
15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18
19 memory {
20 reg = <0x40000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
25 };
26};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 00000000000..dfc43359943
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "skeleton.dtsi"
21
22/ {
23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>;
25
26 gic:interrupt-controller@10490000 {
27 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>;
29 interrupt-controller;
30 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
31 };
32
33 watchdog {
34 compatible = "samsung,s3c2410-wdt";
35 reg = <0x101D0000 0x100>;
36 interrupts = <0 42 0>;
37 };
38
39 rtc {
40 compatible = "samsung,s3c6410-rtc";
41 reg = <0x101E0000 0x100>;
42 interrupts = <0 43 0>, <0 44 0>;
43 };
44
45 sdhci@12200000 {
46 compatible = "samsung,exynos4210-sdhci";
47 reg = <0x12200000 0x100>;
48 interrupts = <0 75 0>;
49 };
50
51 sdhci@12210000 {
52 compatible = "samsung,exynos4210-sdhci";
53 reg = <0x12210000 0x100>;
54 interrupts = <0 76 0>;
55 };
56
57 sdhci@12220000 {
58 compatible = "samsung,exynos4210-sdhci";
59 reg = <0x12220000 0x100>;
60 interrupts = <0 77 0>;
61 };
62
63 sdhci@12230000 {
64 compatible = "samsung,exynos4210-sdhci";
65 reg = <0x12230000 0x100>;
66 interrupts = <0 78 0>;
67 };
68
69 serial@12C00000 {
70 compatible = "samsung,exynos4210-uart";
71 reg = <0x12C00000 0x100>;
72 interrupts = <0 51 0>;
73 };
74
75 serial@12C10000 {
76 compatible = "samsung,exynos4210-uart";
77 reg = <0x12C10000 0x100>;
78 interrupts = <0 52 0>;
79 };
80
81 serial@12C20000 {
82 compatible = "samsung,exynos4210-uart";
83 reg = <0x12C20000 0x100>;
84 interrupts = <0 53 0>;
85 };
86
87 serial@12C30000 {
88 compatible = "samsung,exynos4210-uart";
89 reg = <0x12C30000 0x100>;
90 interrupts = <0 54 0>;
91 };
92
93 i2c@12C60000 {
94 compatible = "samsung,s3c2440-i2c";
95 reg = <0x12C60000 0x100>;
96 interrupts = <0 56 0>;
97 };
98
99 i2c@12C70000 {
100 compatible = "samsung,s3c2440-i2c";
101 reg = <0x12C70000 0x100>;
102 interrupts = <0 57 0>;
103 };
104
105 i2c@12C80000 {
106 compatible = "samsung,s3c2440-i2c";
107 reg = <0x12C80000 0x100>;
108 interrupts = <0 58 0>;
109 };
110
111 i2c@12C90000 {
112 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C90000 0x100>;
114 interrupts = <0 59 0>;
115 };
116
117 i2c@12CA0000 {
118 compatible = "samsung,s3c2440-i2c";
119 reg = <0x12CA0000 0x100>;
120 interrupts = <0 60 0>;
121 };
122
123 i2c@12CB0000 {
124 compatible = "samsung,s3c2440-i2c";
125 reg = <0x12CB0000 0x100>;
126 interrupts = <0 61 0>;
127 };
128
129 i2c@12CC0000 {
130 compatible = "samsung,s3c2440-i2c";
131 reg = <0x12CC0000 0x100>;
132 interrupts = <0 62 0>;
133 };
134
135 i2c@12CD0000 {
136 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CD0000 0x100>;
138 interrupts = <0 63 0>;
139 };
140
141 amba {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "arm,amba-bus";
145 interrupt-parent = <&gic>;
146 ranges;
147
148 pdma0: pdma@121A0000 {
149 compatible = "arm,pl330", "arm,primecell";
150 reg = <0x121A0000 0x1000>;
151 interrupts = <0 34 0>;
152 };
153
154 pdma1: pdma@121B0000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0x121B0000 0x1000>;
157 interrupts = <0 35 0>;
158 };
159
160 mdma0: pdma@10800000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x10800000 0x1000>;
163 interrupts = <0 33 0>;
164 };
165
166 mdma1: pdma@11C10000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0x11C10000 0x1000>;
169 interrupts = <0 124 0>;
170 };
171 };
172
173 gpio-controllers {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 gpio-controller;
177 ranges;
178
179 gpa0: gpio-controller@11400000 {
180 compatible = "samsung,exynos4-gpio";
181 reg = <0x11400000 0x20>;
182 #gpio-cells = <4>;
183 };
184
185 gpa1: gpio-controller@11400020 {
186 compatible = "samsung,exynos4-gpio";
187 reg = <0x11400020 0x20>;
188 #gpio-cells = <4>;
189 };
190
191 gpa2: gpio-controller@11400040 {
192 compatible = "samsung,exynos4-gpio";
193 reg = <0x11400040 0x20>;
194 #gpio-cells = <4>;
195 };
196
197 gpb0: gpio-controller@11400060 {
198 compatible = "samsung,exynos4-gpio";
199 reg = <0x11400060 0x20>;
200 #gpio-cells = <4>;
201 };
202
203 gpb1: gpio-controller@11400080 {
204 compatible = "samsung,exynos4-gpio";
205 reg = <0x11400080 0x20>;
206 #gpio-cells = <4>;
207 };
208
209 gpb2: gpio-controller@114000A0 {
210 compatible = "samsung,exynos4-gpio";
211 reg = <0x114000A0 0x20>;
212 #gpio-cells = <4>;
213 };
214
215 gpb3: gpio-controller@114000C0 {
216 compatible = "samsung,exynos4-gpio";
217 reg = <0x114000C0 0x20>;
218 #gpio-cells = <4>;
219 };
220
221 gpc0: gpio-controller@114000E0 {
222 compatible = "samsung,exynos4-gpio";
223 reg = <0x114000E0 0x20>;
224 #gpio-cells = <4>;
225 };
226
227 gpc1: gpio-controller@11400100 {
228 compatible = "samsung,exynos4-gpio";
229 reg = <0x11400100 0x20>;
230 #gpio-cells = <4>;
231 };
232
233 gpc2: gpio-controller@11400120 {
234 compatible = "samsung,exynos4-gpio";
235 reg = <0x11400120 0x20>;
236 #gpio-cells = <4>;
237 };
238
239 gpc3: gpio-controller@11400140 {
240 compatible = "samsung,exynos4-gpio";
241 reg = <0x11400140 0x20>;
242 #gpio-cells = <4>;
243 };
244
245 gpd0: gpio-controller@11400160 {
246 compatible = "samsung,exynos4-gpio";
247 reg = <0x11400160 0x20>;
248 #gpio-cells = <4>;
249 };
250
251 gpd1: gpio-controller@11400180 {
252 compatible = "samsung,exynos4-gpio";
253 reg = <0x11400180 0x20>;
254 #gpio-cells = <4>;
255 };
256
257 gpy0: gpio-controller@114001A0 {
258 compatible = "samsung,exynos4-gpio";
259 reg = <0x114001A0 0x20>;
260 #gpio-cells = <4>;
261 };
262
263 gpy1: gpio-controller@114001C0 {
264 compatible = "samsung,exynos4-gpio";
265 reg = <0x114001C0 0x20>;
266 #gpio-cells = <4>;
267 };
268
269 gpy2: gpio-controller@114001E0 {
270 compatible = "samsung,exynos4-gpio";
271 reg = <0x114001E0 0x20>;
272 #gpio-cells = <4>;
273 };
274
275 gpy3: gpio-controller@11400200 {
276 compatible = "samsung,exynos4-gpio";
277 reg = <0x11400200 0x20>;
278 #gpio-cells = <4>;
279 };
280
281 gpy4: gpio-controller@11400220 {
282 compatible = "samsung,exynos4-gpio";
283 reg = <0x11400220 0x20>;
284 #gpio-cells = <4>;
285 };
286
287 gpy5: gpio-controller@11400240 {
288 compatible = "samsung,exynos4-gpio";
289 reg = <0x11400240 0x20>;
290 #gpio-cells = <4>;
291 };
292
293 gpy6: gpio-controller@11400260 {
294 compatible = "samsung,exynos4-gpio";
295 reg = <0x11400260 0x20>;
296 #gpio-cells = <4>;
297 };
298
299 gpx0: gpio-controller@11400C00 {
300 compatible = "samsung,exynos4-gpio";
301 reg = <0x11400C00 0x20>;
302 #gpio-cells = <4>;
303 };
304
305 gpx1: gpio-controller@11400C20 {
306 compatible = "samsung,exynos4-gpio";
307 reg = <0x11400C20 0x20>;
308 #gpio-cells = <4>;
309 };
310
311 gpx2: gpio-controller@11400C40 {
312 compatible = "samsung,exynos4-gpio";
313 reg = <0x11400C40 0x20>;
314 #gpio-cells = <4>;
315 };
316
317 gpx3: gpio-controller@11400C60 {
318 compatible = "samsung,exynos4-gpio";
319 reg = <0x11400C60 0x20>;
320 #gpio-cells = <4>;
321 };
322
323 gpe0: gpio-controller@13400000 {
324 compatible = "samsung,exynos4-gpio";
325 reg = <0x13400000 0x20>;
326 #gpio-cells = <4>;
327 };
328
329 gpe1: gpio-controller@13400020 {
330 compatible = "samsung,exynos4-gpio";
331 reg = <0x13400020 0x20>;
332 #gpio-cells = <4>;
333 };
334
335 gpf0: gpio-controller@13400040 {
336 compatible = "samsung,exynos4-gpio";
337 reg = <0x13400040 0x20>;
338 #gpio-cells = <4>;
339 };
340
341 gpf1: gpio-controller@13400060 {
342 compatible = "samsung,exynos4-gpio";
343 reg = <0x13400060 0x20>;
344 #gpio-cells = <4>;
345 };
346
347 gpg0: gpio-controller@13400080 {
348 compatible = "samsung,exynos4-gpio";
349 reg = <0x13400080 0x20>;
350 #gpio-cells = <4>;
351 };
352
353 gpg1: gpio-controller@134000A0 {
354 compatible = "samsung,exynos4-gpio";
355 reg = <0x134000A0 0x20>;
356 #gpio-cells = <4>;
357 };
358
359 gpg2: gpio-controller@134000C0 {
360 compatible = "samsung,exynos4-gpio";
361 reg = <0x134000C0 0x20>;
362 #gpio-cells = <4>;
363 };
364
365 gph0: gpio-controller@134000E0 {
366 compatible = "samsung,exynos4-gpio";
367 reg = <0x134000E0 0x20>;
368 #gpio-cells = <4>;
369 };
370
371 gph1: gpio-controller@13400100 {
372 compatible = "samsung,exynos4-gpio";
373 reg = <0x13400100 0x20>;
374 #gpio-cells = <4>;
375 };
376
377 gpv0: gpio-controller@10D10000 {
378 compatible = "samsung,exynos4-gpio";
379 reg = <0x10D10000 0x20>;
380 #gpio-cells = <4>;
381 };
382
383 gpv1: gpio-controller@10D10020 {
384 compatible = "samsung,exynos4-gpio";
385 reg = <0x10D10020 0x20>;
386 #gpio-cells = <4>;
387 };
388
389 gpv2: gpio-controller@10D10040 {
390 compatible = "samsung,exynos4-gpio";
391 reg = <0x10D10040 0x20>;
392 #gpio-cells = <4>;
393 };
394
395 gpv3: gpio-controller@10D10060 {
396 compatible = "samsung,exynos4-gpio";
397 reg = <0x10D10060 0x20>;
398 #gpio-cells = <4>;
399 };
400
401 gpv4: gpio-controller@10D10080 {
402 compatible = "samsung,exynos4-gpio";
403 reg = <0x10D10080 0x20>;
404 #gpio-cells = <4>;
405 };
406
407 gpz: gpio-controller@03860000 {
408 compatible = "samsung,exynos4-gpio";
409 reg = <0x03860000 0x20>;
410 #gpio-cells = <4>;
411 };
412 };
413};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f68a0e..42f072db114 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
11 11
12menu "SAMSUNG EXYNOS SoCs Support" 12menu "SAMSUNG EXYNOS SoCs Support"
13 13
14choice
15 prompt "EXYNOS System Type"
16 default ARCH_EXYNOS4
17
18config ARCH_EXYNOS4 14config ARCH_EXYNOS4
19 bool "SAMSUNG EXYNOS4" 15 bool "SAMSUNG EXYNOS4"
16 default y
20 select HAVE_SMP 17 select HAVE_SMP
21 select MIGHT_HAVE_CACHE_L2X0 18 select MIGHT_HAVE_CACHE_L2X0
22 help 19 help
23 Samsung EXYNOS4 SoCs based systems 20 Samsung EXYNOS4 SoCs based systems
24 21
25endchoice 22config ARCH_EXYNOS5
23 bool "SAMSUNG EXYNOS5"
24 select HAVE_SMP
25 help
26 Samsung EXYNOS5 (Cortex-A15) SoC based systems
26 27
27comment "EXYNOS SoCs" 28comment "EXYNOS SoCs"
28 29
@@ -41,6 +42,7 @@ config SOC_EXYNOS4212
41 bool "SAMSUNG EXYNOS4212" 42 bool "SAMSUNG EXYNOS4212"
42 default y 43 default y
43 depends on ARCH_EXYNOS4 44 depends on ARCH_EXYNOS4
45 select SAMSUNG_DMADEV
44 select S5P_PM if PM 46 select S5P_PM if PM
45 select S5P_SLEEP if PM 47 select S5P_SLEEP if PM
46 help 48 help
@@ -50,9 +52,17 @@ config SOC_EXYNOS4412
50 bool "SAMSUNG EXYNOS4412" 52 bool "SAMSUNG EXYNOS4412"
51 default y 53 default y
52 depends on ARCH_EXYNOS4 54 depends on ARCH_EXYNOS4
55 select SAMSUNG_DMADEV
53 help 56 help
54 Enable EXYNOS4412 SoC support 57 Enable EXYNOS4412 SoC support
55 58
59config SOC_EXYNOS5250
60 bool "SAMSUNG EXYNOS5250"
61 default y
62 depends on ARCH_EXYNOS5
63 help
64 Enable EXYNOS5250 SoC support
65
56config EXYNOS4_MCT 66config EXYNOS4_MCT
57 bool 67 bool
58 default y 68 default y
@@ -333,6 +343,7 @@ config MACH_SMDK4212
333 select SAMSUNG_DEV_BACKLIGHT 343 select SAMSUNG_DEV_BACKLIGHT
334 select SAMSUNG_DEV_KEYPAD 344 select SAMSUNG_DEV_KEYPAD
335 select SAMSUNG_DEV_PWM 345 select SAMSUNG_DEV_PWM
346 select EXYNOS4_DEV_DMA
336 select EXYNOS4_SETUP_I2C1 347 select EXYNOS4_SETUP_I2C1
337 select EXYNOS4_SETUP_I2C3 348 select EXYNOS4_SETUP_I2C3
338 select EXYNOS4_SETUP_I2C7 349 select EXYNOS4_SETUP_I2C7
@@ -351,7 +362,7 @@ config MACH_SMDK4412
351 Machine support for Samsung SMDK4412 362 Machine support for Samsung SMDK4412
352endif 363endif
353 364
354comment "Flattened Device Tree based board for Exynos4 based SoC" 365comment "Flattened Device Tree based board for EXYNOS SoCs"
355 366
356config MACH_EXYNOS4_DT 367config MACH_EXYNOS4_DT
357 bool "Samsung Exynos4 Machine using device tree" 368 bool "Samsung Exynos4 Machine using device tree"
@@ -365,6 +376,15 @@ config MACH_EXYNOS4_DT
365 Note: This is under development and not all peripherals can be supported 376 Note: This is under development and not all peripherals can be supported
366 with this machine file. 377 with this machine file.
367 378
379config MACH_EXYNOS5_DT
380 bool "SAMSUNG EXYNOS5 Machine using device tree"
381 select SOC_EXYNOS5250
382 select USE_OF
383 select ARM_AMBA
384 help
385 Machine support for Samsung Exynos4 machine with device tree enabled.
386 Select this if a fdt blob is available for the EXYNOS4 SoC based board.
387
368if ARCH_EXYNOS4 388if ARCH_EXYNOS4
369 389
370comment "Configuration for HSMMC 8-bit bus width" 390comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb..29967efd262 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,9 @@ obj- :=
12 12
13# Core 13# Core
14 14
15obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
16obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 18obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
17obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 19obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
18 20
@@ -40,9 +42,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
40obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o 42obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
41 43
42obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o 44obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
45obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
43 46
44# device support 47# device support
45 48
49obj-y += dev-uart.o
46obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 50obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
47obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 51obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
48obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 52obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
@@ -51,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
52obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
53 57
54obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o 58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
55obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
56obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
57obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 61obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 00000000000..6504d8b1f8e
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1576 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30#include "clock-exynos4.h"
31
32#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95};
96#endif
97
98static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m",
100 .rate = 27000000,
101};
102
103static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy",
105};
106
107static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0",
109 .rate = 27000000,
110};
111
112static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1",
114};
115
116static struct clk dummy_apb_pclk = {
117 .name = "apb_pclk",
118 .id = -1,
119};
120
121static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122{
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124}
125
126static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127{
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129}
130
131static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132{
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134}
135
136int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137{
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139}
140
141static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142{
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144}
145
146static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147{
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149}
150
151static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152{
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154}
155
156static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157{
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159}
160
161static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162{
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164}
165
166static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167{
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169}
170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174}
175
176static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177{
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179}
180
181int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182{
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184}
185
186int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187{
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189}
190
191static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192{
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194}
195
196static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197{
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199}
200
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202{
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
204}
205
206static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
207{
208 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
209}
210
211/* Core list of CMU_CPU side */
212
213static struct clksrc_clk exynos4_clk_mout_apll = {
214 .clk = {
215 .name = "mout_apll",
216 },
217 .sources = &clk_src_apll,
218 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219};
220
221static struct clksrc_clk exynos4_clk_sclk_apll = {
222 .clk = {
223 .name = "sclk_apll",
224 .parent = &exynos4_clk_mout_apll.clk,
225 },
226 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227};
228
229static struct clksrc_clk exynos4_clk_mout_epll = {
230 .clk = {
231 .name = "mout_epll",
232 },
233 .sources = &clk_src_epll,
234 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235};
236
237struct clksrc_clk exynos4_clk_mout_mpll = {
238 .clk = {
239 .name = "mout_mpll",
240 },
241 .sources = &clk_src_mpll,
242
243 /* reg_src will be added in each SoCs' clock */
244};
245
246static struct clk *exynos4_clkset_moutcore_list[] = {
247 [0] = &exynos4_clk_mout_apll.clk,
248 [1] = &exynos4_clk_mout_mpll.clk,
249};
250
251static struct clksrc_sources exynos4_clkset_moutcore = {
252 .sources = exynos4_clkset_moutcore_list,
253 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
254};
255
256static struct clksrc_clk exynos4_clk_moutcore = {
257 .clk = {
258 .name = "moutcore",
259 },
260 .sources = &exynos4_clkset_moutcore,
261 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262};
263
264static struct clksrc_clk exynos4_clk_coreclk = {
265 .clk = {
266 .name = "core_clk",
267 .parent = &exynos4_clk_moutcore.clk,
268 },
269 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270};
271
272static struct clksrc_clk exynos4_clk_armclk = {
273 .clk = {
274 .name = "armclk",
275 .parent = &exynos4_clk_coreclk.clk,
276 },
277};
278
279static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280 .clk = {
281 .name = "aclk_corem0",
282 .parent = &exynos4_clk_coreclk.clk,
283 },
284 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285};
286
287static struct clksrc_clk exynos4_clk_aclk_cores = {
288 .clk = {
289 .name = "aclk_cores",
290 .parent = &exynos4_clk_coreclk.clk,
291 },
292 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293};
294
295static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296 .clk = {
297 .name = "aclk_corem1",
298 .parent = &exynos4_clk_coreclk.clk,
299 },
300 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301};
302
303static struct clksrc_clk exynos4_clk_periphclk = {
304 .clk = {
305 .name = "periphclk",
306 .parent = &exynos4_clk_coreclk.clk,
307 },
308 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309};
310
311/* Core list of CMU_CORE side */
312
313static struct clk *exynos4_clkset_corebus_list[] = {
314 [0] = &exynos4_clk_mout_mpll.clk,
315 [1] = &exynos4_clk_sclk_apll.clk,
316};
317
318struct clksrc_sources exynos4_clkset_mout_corebus = {
319 .sources = exynos4_clkset_corebus_list,
320 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
321};
322
323static struct clksrc_clk exynos4_clk_mout_corebus = {
324 .clk = {
325 .name = "mout_corebus",
326 },
327 .sources = &exynos4_clkset_mout_corebus,
328 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329};
330
331static struct clksrc_clk exynos4_clk_sclk_dmc = {
332 .clk = {
333 .name = "sclk_dmc",
334 .parent = &exynos4_clk_mout_corebus.clk,
335 },
336 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337};
338
339static struct clksrc_clk exynos4_clk_aclk_cored = {
340 .clk = {
341 .name = "aclk_cored",
342 .parent = &exynos4_clk_sclk_dmc.clk,
343 },
344 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos4_clk_aclk_corep = {
348 .clk = {
349 .name = "aclk_corep",
350 .parent = &exynos4_clk_aclk_cored.clk,
351 },
352 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353};
354
355static struct clksrc_clk exynos4_clk_aclk_acp = {
356 .clk = {
357 .name = "aclk_acp",
358 .parent = &exynos4_clk_mout_corebus.clk,
359 },
360 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361};
362
363static struct clksrc_clk exynos4_clk_pclk_acp = {
364 .clk = {
365 .name = "pclk_acp",
366 .parent = &exynos4_clk_aclk_acp.clk,
367 },
368 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369};
370
371/* Core list of CMU_TOP side */
372
373struct clk *exynos4_clkset_aclk_top_list[] = {
374 [0] = &exynos4_clk_mout_mpll.clk,
375 [1] = &exynos4_clk_sclk_apll.clk,
376};
377
378static struct clksrc_sources exynos4_clkset_aclk = {
379 .sources = exynos4_clkset_aclk_top_list,
380 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381};
382
383static struct clksrc_clk exynos4_clk_aclk_200 = {
384 .clk = {
385 .name = "aclk_200",
386 },
387 .sources = &exynos4_clkset_aclk,
388 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
389 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390};
391
392static struct clksrc_clk exynos4_clk_aclk_100 = {
393 .clk = {
394 .name = "aclk_100",
395 },
396 .sources = &exynos4_clkset_aclk,
397 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
398 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399};
400
401static struct clksrc_clk exynos4_clk_aclk_160 = {
402 .clk = {
403 .name = "aclk_160",
404 },
405 .sources = &exynos4_clkset_aclk,
406 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
407 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408};
409
410struct clksrc_clk exynos4_clk_aclk_133 = {
411 .clk = {
412 .name = "aclk_133",
413 },
414 .sources = &exynos4_clkset_aclk,
415 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
416 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417};
418
419static struct clk *exynos4_clkset_vpllsrc_list[] = {
420 [0] = &clk_fin_vpll,
421 [1] = &exynos4_clk_sclk_hdmi27m,
422};
423
424static struct clksrc_sources exynos4_clkset_vpllsrc = {
425 .sources = exynos4_clkset_vpllsrc_list,
426 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427};
428
429static struct clksrc_clk exynos4_clk_vpllsrc = {
430 .clk = {
431 .name = "vpll_src",
432 .enable = exynos4_clksrc_mask_top_ctrl,
433 .ctrlbit = (1 << 0),
434 },
435 .sources = &exynos4_clkset_vpllsrc,
436 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437};
438
439static struct clk *exynos4_clkset_sclk_vpll_list[] = {
440 [0] = &exynos4_clk_vpllsrc.clk,
441 [1] = &clk_fout_vpll,
442};
443
444static struct clksrc_sources exynos4_clkset_sclk_vpll = {
445 .sources = exynos4_clkset_sclk_vpll_list,
446 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447};
448
449static struct clksrc_clk exynos4_clk_sclk_vpll = {
450 .clk = {
451 .name = "sclk_vpll",
452 },
453 .sources = &exynos4_clkset_sclk_vpll,
454 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455};
456
457static struct clk exynos4_init_clocks_off[] = {
458 {
459 .name = "timers",
460 .parent = &exynos4_clk_aclk_100.clk,
461 .enable = exynos4_clk_ip_peril_ctrl,
462 .ctrlbit = (1<<24),
463 }, {
464 .name = "csis",
465 .devname = "s5p-mipi-csis.0",
466 .enable = exynos4_clk_ip_cam_ctrl,
467 .ctrlbit = (1 << 4),
468 }, {
469 .name = "csis",
470 .devname = "s5p-mipi-csis.1",
471 .enable = exynos4_clk_ip_cam_ctrl,
472 .ctrlbit = (1 << 5),
473 }, {
474 .name = "fimc",
475 .devname = "exynos4-fimc.0",
476 .enable = exynos4_clk_ip_cam_ctrl,
477 .ctrlbit = (1 << 0),
478 }, {
479 .name = "fimc",
480 .devname = "exynos4-fimc.1",
481 .enable = exynos4_clk_ip_cam_ctrl,
482 .ctrlbit = (1 << 1),
483 }, {
484 .name = "fimc",
485 .devname = "exynos4-fimc.2",
486 .enable = exynos4_clk_ip_cam_ctrl,
487 .ctrlbit = (1 << 2),
488 }, {
489 .name = "fimc",
490 .devname = "exynos4-fimc.3",
491 .enable = exynos4_clk_ip_cam_ctrl,
492 .ctrlbit = (1 << 3),
493 }, {
494 .name = "hsmmc",
495 .devname = "s3c-sdhci.0",
496 .parent = &exynos4_clk_aclk_133.clk,
497 .enable = exynos4_clk_ip_fsys_ctrl,
498 .ctrlbit = (1 << 5),
499 }, {
500 .name = "hsmmc",
501 .devname = "s3c-sdhci.1",
502 .parent = &exynos4_clk_aclk_133.clk,
503 .enable = exynos4_clk_ip_fsys_ctrl,
504 .ctrlbit = (1 << 6),
505 }, {
506 .name = "hsmmc",
507 .devname = "s3c-sdhci.2",
508 .parent = &exynos4_clk_aclk_133.clk,
509 .enable = exynos4_clk_ip_fsys_ctrl,
510 .ctrlbit = (1 << 7),
511 }, {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.3",
514 .parent = &exynos4_clk_aclk_133.clk,
515 .enable = exynos4_clk_ip_fsys_ctrl,
516 .ctrlbit = (1 << 8),
517 }, {
518 .name = "dwmmc",
519 .parent = &exynos4_clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl,
521 .ctrlbit = (1 << 9),
522 }, {
523 .name = "dac",
524 .devname = "s5p-sdo",
525 .enable = exynos4_clk_ip_tv_ctrl,
526 .ctrlbit = (1 << 2),
527 }, {
528 .name = "mixer",
529 .devname = "s5p-mixer",
530 .enable = exynos4_clk_ip_tv_ctrl,
531 .ctrlbit = (1 << 1),
532 }, {
533 .name = "vp",
534 .devname = "s5p-mixer",
535 .enable = exynos4_clk_ip_tv_ctrl,
536 .ctrlbit = (1 << 0),
537 }, {
538 .name = "hdmi",
539 .devname = "exynos4-hdmi",
540 .enable = exynos4_clk_ip_tv_ctrl,
541 .ctrlbit = (1 << 3),
542 }, {
543 .name = "hdmiphy",
544 .devname = "exynos4-hdmi",
545 .enable = exynos4_clk_hdmiphy_ctrl,
546 .ctrlbit = (1 << 0),
547 }, {
548 .name = "dacphy",
549 .devname = "s5p-sdo",
550 .enable = exynos4_clk_dac_ctrl,
551 .ctrlbit = (1 << 0),
552 }, {
553 .name = "adc",
554 .enable = exynos4_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 15),
556 }, {
557 .name = "keypad",
558 .enable = exynos4_clk_ip_perir_ctrl,
559 .ctrlbit = (1 << 16),
560 }, {
561 .name = "rtc",
562 .enable = exynos4_clk_ip_perir_ctrl,
563 .ctrlbit = (1 << 15),
564 }, {
565 .name = "watchdog",
566 .parent = &exynos4_clk_aclk_100.clk,
567 .enable = exynos4_clk_ip_perir_ctrl,
568 .ctrlbit = (1 << 14),
569 }, {
570 .name = "usbhost",
571 .enable = exynos4_clk_ip_fsys_ctrl ,
572 .ctrlbit = (1 << 12),
573 }, {
574 .name = "otg",
575 .enable = exynos4_clk_ip_fsys_ctrl,
576 .ctrlbit = (1 << 13),
577 }, {
578 .name = "spi",
579 .devname = "s3c64xx-spi.0",
580 .enable = exynos4_clk_ip_peril_ctrl,
581 .ctrlbit = (1 << 16),
582 }, {
583 .name = "spi",
584 .devname = "s3c64xx-spi.1",
585 .enable = exynos4_clk_ip_peril_ctrl,
586 .ctrlbit = (1 << 17),
587 }, {
588 .name = "spi",
589 .devname = "s3c64xx-spi.2",
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 18),
592 }, {
593 .name = "iis",
594 .devname = "samsung-i2s.0",
595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 19),
597 }, {
598 .name = "iis",
599 .devname = "samsung-i2s.1",
600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 20),
602 }, {
603 .name = "iis",
604 .devname = "samsung-i2s.2",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 21),
607 }, {
608 .name = "ac97",
609 .devname = "samsung-ac97",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 27),
612 }, {
613 .name = "fimg2d",
614 .enable = exynos4_clk_ip_image_ctrl,
615 .ctrlbit = (1 << 0),
616 }, {
617 .name = "mfc",
618 .devname = "s5p-mfc",
619 .enable = exynos4_clk_ip_mfc_ctrl,
620 .ctrlbit = (1 << 0),
621 }, {
622 .name = "i2c",
623 .devname = "s3c2440-i2c.0",
624 .parent = &exynos4_clk_aclk_100.clk,
625 .enable = exynos4_clk_ip_peril_ctrl,
626 .ctrlbit = (1 << 6),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-i2c.1",
630 .parent = &exynos4_clk_aclk_100.clk,
631 .enable = exynos4_clk_ip_peril_ctrl,
632 .ctrlbit = (1 << 7),
633 }, {
634 .name = "i2c",
635 .devname = "s3c2440-i2c.2",
636 .parent = &exynos4_clk_aclk_100.clk,
637 .enable = exynos4_clk_ip_peril_ctrl,
638 .ctrlbit = (1 << 8),
639 }, {
640 .name = "i2c",
641 .devname = "s3c2440-i2c.3",
642 .parent = &exynos4_clk_aclk_100.clk,
643 .enable = exynos4_clk_ip_peril_ctrl,
644 .ctrlbit = (1 << 9),
645 }, {
646 .name = "i2c",
647 .devname = "s3c2440-i2c.4",
648 .parent = &exynos4_clk_aclk_100.clk,
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 10),
651 }, {
652 .name = "i2c",
653 .devname = "s3c2440-i2c.5",
654 .parent = &exynos4_clk_aclk_100.clk,
655 .enable = exynos4_clk_ip_peril_ctrl,
656 .ctrlbit = (1 << 11),
657 }, {
658 .name = "i2c",
659 .devname = "s3c2440-i2c.6",
660 .parent = &exynos4_clk_aclk_100.clk,
661 .enable = exynos4_clk_ip_peril_ctrl,
662 .ctrlbit = (1 << 12),
663 }, {
664 .name = "i2c",
665 .devname = "s3c2440-i2c.7",
666 .parent = &exynos4_clk_aclk_100.clk,
667 .enable = exynos4_clk_ip_peril_ctrl,
668 .ctrlbit = (1 << 13),
669 }, {
670 .name = "i2c",
671 .devname = "s3c2440-hdmiphy-i2c",
672 .parent = &exynos4_clk_aclk_100.clk,
673 .enable = exynos4_clk_ip_peril_ctrl,
674 .ctrlbit = (1 << 14),
675 }, {
676 .name = "SYSMMU_MDMA",
677 .enable = exynos4_clk_ip_image_ctrl,
678 .ctrlbit = (1 << 5),
679 }, {
680 .name = "SYSMMU_FIMC0",
681 .enable = exynos4_clk_ip_cam_ctrl,
682 .ctrlbit = (1 << 7),
683 }, {
684 .name = "SYSMMU_FIMC1",
685 .enable = exynos4_clk_ip_cam_ctrl,
686 .ctrlbit = (1 << 8),
687 }, {
688 .name = "SYSMMU_FIMC2",
689 .enable = exynos4_clk_ip_cam_ctrl,
690 .ctrlbit = (1 << 9),
691 }, {
692 .name = "SYSMMU_FIMC3",
693 .enable = exynos4_clk_ip_cam_ctrl,
694 .ctrlbit = (1 << 10),
695 }, {
696 .name = "SYSMMU_JPEG",
697 .enable = exynos4_clk_ip_cam_ctrl,
698 .ctrlbit = (1 << 11),
699 }, {
700 .name = "SYSMMU_FIMD0",
701 .enable = exynos4_clk_ip_lcd0_ctrl,
702 .ctrlbit = (1 << 4),
703 }, {
704 .name = "SYSMMU_FIMD1",
705 .enable = exynos4_clk_ip_lcd1_ctrl,
706 .ctrlbit = (1 << 4),
707 }, {
708 .name = "SYSMMU_PCIe",
709 .enable = exynos4_clk_ip_fsys_ctrl,
710 .ctrlbit = (1 << 18),
711 }, {
712 .name = "SYSMMU_G2D",
713 .enable = exynos4_clk_ip_image_ctrl,
714 .ctrlbit = (1 << 3),
715 }, {
716 .name = "SYSMMU_ROTATOR",
717 .enable = exynos4_clk_ip_image_ctrl,
718 .ctrlbit = (1 << 4),
719 }, {
720 .name = "SYSMMU_TV",
721 .enable = exynos4_clk_ip_tv_ctrl,
722 .ctrlbit = (1 << 4),
723 }, {
724 .name = "SYSMMU_MFC_L",
725 .enable = exynos4_clk_ip_mfc_ctrl,
726 .ctrlbit = (1 << 1),
727 }, {
728 .name = "SYSMMU_MFC_R",
729 .enable = exynos4_clk_ip_mfc_ctrl,
730 .ctrlbit = (1 << 2),
731 }
732};
733
734static struct clk exynos4_init_clocks_on[] = {
735 {
736 .name = "uart",
737 .devname = "s5pv210-uart.0",
738 .enable = exynos4_clk_ip_peril_ctrl,
739 .ctrlbit = (1 << 0),
740 }, {
741 .name = "uart",
742 .devname = "s5pv210-uart.1",
743 .enable = exynos4_clk_ip_peril_ctrl,
744 .ctrlbit = (1 << 1),
745 }, {
746 .name = "uart",
747 .devname = "s5pv210-uart.2",
748 .enable = exynos4_clk_ip_peril_ctrl,
749 .ctrlbit = (1 << 2),
750 }, {
751 .name = "uart",
752 .devname = "s5pv210-uart.3",
753 .enable = exynos4_clk_ip_peril_ctrl,
754 .ctrlbit = (1 << 3),
755 }, {
756 .name = "uart",
757 .devname = "s5pv210-uart.4",
758 .enable = exynos4_clk_ip_peril_ctrl,
759 .ctrlbit = (1 << 4),
760 }, {
761 .name = "uart",
762 .devname = "s5pv210-uart.5",
763 .enable = exynos4_clk_ip_peril_ctrl,
764 .ctrlbit = (1 << 5),
765 }
766};
767
768static struct clk exynos4_clk_pdma0 = {
769 .name = "dma",
770 .devname = "dma-pl330.0",
771 .enable = exynos4_clk_ip_fsys_ctrl,
772 .ctrlbit = (1 << 0),
773};
774
775static struct clk exynos4_clk_pdma1 = {
776 .name = "dma",
777 .devname = "dma-pl330.1",
778 .enable = exynos4_clk_ip_fsys_ctrl,
779 .ctrlbit = (1 << 1),
780};
781
782static struct clk exynos4_clk_mdma1 = {
783 .name = "dma",
784 .devname = "dma-pl330.2",
785 .enable = exynos4_clk_ip_image_ctrl,
786 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
787};
788
789static struct clk exynos4_clk_fimd0 = {
790 .name = "fimd",
791 .devname = "exynos4-fb.0",
792 .enable = exynos4_clk_ip_lcd0_ctrl,
793 .ctrlbit = (1 << 0),
794};
795
796struct clk *exynos4_clkset_group_list[] = {
797 [0] = &clk_ext_xtal_mux,
798 [1] = &clk_xusbxti,
799 [2] = &exynos4_clk_sclk_hdmi27m,
800 [3] = &exynos4_clk_sclk_usbphy0,
801 [4] = &exynos4_clk_sclk_usbphy1,
802 [5] = &exynos4_clk_sclk_hdmiphy,
803 [6] = &exynos4_clk_mout_mpll.clk,
804 [7] = &exynos4_clk_mout_epll.clk,
805 [8] = &exynos4_clk_sclk_vpll.clk,
806};
807
808struct clksrc_sources exynos4_clkset_group = {
809 .sources = exynos4_clkset_group_list,
810 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
811};
812
813static struct clk *exynos4_clkset_mout_g2d0_list[] = {
814 [0] = &exynos4_clk_mout_mpll.clk,
815 [1] = &exynos4_clk_sclk_apll.clk,
816};
817
818static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
819 .sources = exynos4_clkset_mout_g2d0_list,
820 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
821};
822
823static struct clksrc_clk exynos4_clk_mout_g2d0 = {
824 .clk = {
825 .name = "mout_g2d0",
826 },
827 .sources = &exynos4_clkset_mout_g2d0,
828 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
829};
830
831static struct clk *exynos4_clkset_mout_g2d1_list[] = {
832 [0] = &exynos4_clk_mout_epll.clk,
833 [1] = &exynos4_clk_sclk_vpll.clk,
834};
835
836static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
837 .sources = exynos4_clkset_mout_g2d1_list,
838 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
839};
840
841static struct clksrc_clk exynos4_clk_mout_g2d1 = {
842 .clk = {
843 .name = "mout_g2d1",
844 },
845 .sources = &exynos4_clkset_mout_g2d1,
846 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
847};
848
849static struct clk *exynos4_clkset_mout_g2d_list[] = {
850 [0] = &exynos4_clk_mout_g2d0.clk,
851 [1] = &exynos4_clk_mout_g2d1.clk,
852};
853
854static struct clksrc_sources exynos4_clkset_mout_g2d = {
855 .sources = exynos4_clkset_mout_g2d_list,
856 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
857};
858
859static struct clk *exynos4_clkset_mout_mfc0_list[] = {
860 [0] = &exynos4_clk_mout_mpll.clk,
861 [1] = &exynos4_clk_sclk_apll.clk,
862};
863
864static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
865 .sources = exynos4_clkset_mout_mfc0_list,
866 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
867};
868
869static struct clksrc_clk exynos4_clk_mout_mfc0 = {
870 .clk = {
871 .name = "mout_mfc0",
872 },
873 .sources = &exynos4_clkset_mout_mfc0,
874 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
875};
876
877static struct clk *exynos4_clkset_mout_mfc1_list[] = {
878 [0] = &exynos4_clk_mout_epll.clk,
879 [1] = &exynos4_clk_sclk_vpll.clk,
880};
881
882static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
883 .sources = exynos4_clkset_mout_mfc1_list,
884 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
885};
886
887static struct clksrc_clk exynos4_clk_mout_mfc1 = {
888 .clk = {
889 .name = "mout_mfc1",
890 },
891 .sources = &exynos4_clkset_mout_mfc1,
892 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
893};
894
895static struct clk *exynos4_clkset_mout_mfc_list[] = {
896 [0] = &exynos4_clk_mout_mfc0.clk,
897 [1] = &exynos4_clk_mout_mfc1.clk,
898};
899
900static struct clksrc_sources exynos4_clkset_mout_mfc = {
901 .sources = exynos4_clkset_mout_mfc_list,
902 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
903};
904
905static struct clk *exynos4_clkset_sclk_dac_list[] = {
906 [0] = &exynos4_clk_sclk_vpll.clk,
907 [1] = &exynos4_clk_sclk_hdmiphy,
908};
909
910static struct clksrc_sources exynos4_clkset_sclk_dac = {
911 .sources = exynos4_clkset_sclk_dac_list,
912 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
913};
914
915static struct clksrc_clk exynos4_clk_sclk_dac = {
916 .clk = {
917 .name = "sclk_dac",
918 .enable = exynos4_clksrc_mask_tv_ctrl,
919 .ctrlbit = (1 << 8),
920 },
921 .sources = &exynos4_clkset_sclk_dac,
922 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
923};
924
925static struct clksrc_clk exynos4_clk_sclk_pixel = {
926 .clk = {
927 .name = "sclk_pixel",
928 .parent = &exynos4_clk_sclk_vpll.clk,
929 },
930 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
931};
932
933static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
934 [0] = &exynos4_clk_sclk_pixel.clk,
935 [1] = &exynos4_clk_sclk_hdmiphy,
936};
937
938static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
939 .sources = exynos4_clkset_sclk_hdmi_list,
940 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
941};
942
943static struct clksrc_clk exynos4_clk_sclk_hdmi = {
944 .clk = {
945 .name = "sclk_hdmi",
946 .enable = exynos4_clksrc_mask_tv_ctrl,
947 .ctrlbit = (1 << 0),
948 },
949 .sources = &exynos4_clkset_sclk_hdmi,
950 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
951};
952
953static struct clk *exynos4_clkset_sclk_mixer_list[] = {
954 [0] = &exynos4_clk_sclk_dac.clk,
955 [1] = &exynos4_clk_sclk_hdmi.clk,
956};
957
958static struct clksrc_sources exynos4_clkset_sclk_mixer = {
959 .sources = exynos4_clkset_sclk_mixer_list,
960 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
961};
962
963static struct clksrc_clk exynos4_clk_sclk_mixer = {
964 .clk = {
965 .name = "sclk_mixer",
966 .enable = exynos4_clksrc_mask_tv_ctrl,
967 .ctrlbit = (1 << 4),
968 },
969 .sources = &exynos4_clkset_sclk_mixer,
970 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
971};
972
973static struct clksrc_clk *exynos4_sclk_tv[] = {
974 &exynos4_clk_sclk_dac,
975 &exynos4_clk_sclk_pixel,
976 &exynos4_clk_sclk_hdmi,
977 &exynos4_clk_sclk_mixer,
978};
979
980static struct clksrc_clk exynos4_clk_dout_mmc0 = {
981 .clk = {
982 .name = "dout_mmc0",
983 },
984 .sources = &exynos4_clkset_group,
985 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
986 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
987};
988
989static struct clksrc_clk exynos4_clk_dout_mmc1 = {
990 .clk = {
991 .name = "dout_mmc1",
992 },
993 .sources = &exynos4_clkset_group,
994 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
995 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
996};
997
998static struct clksrc_clk exynos4_clk_dout_mmc2 = {
999 .clk = {
1000 .name = "dout_mmc2",
1001 },
1002 .sources = &exynos4_clkset_group,
1003 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1004 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1005};
1006
1007static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1008 .clk = {
1009 .name = "dout_mmc3",
1010 },
1011 .sources = &exynos4_clkset_group,
1012 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1013 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1014};
1015
1016static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1017 .clk = {
1018 .name = "dout_mmc4",
1019 },
1020 .sources = &exynos4_clkset_group,
1021 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1022 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1023};
1024
1025static struct clksrc_clk exynos4_clksrcs[] = {
1026 {
1027 .clk = {
1028 .name = "sclk_pwm",
1029 .enable = exynos4_clksrc_mask_peril0_ctrl,
1030 .ctrlbit = (1 << 24),
1031 },
1032 .sources = &exynos4_clkset_group,
1033 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1034 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1035 }, {
1036 .clk = {
1037 .name = "sclk_csis",
1038 .devname = "s5p-mipi-csis.0",
1039 .enable = exynos4_clksrc_mask_cam_ctrl,
1040 .ctrlbit = (1 << 24),
1041 },
1042 .sources = &exynos4_clkset_group,
1043 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1044 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1045 }, {
1046 .clk = {
1047 .name = "sclk_csis",
1048 .devname = "s5p-mipi-csis.1",
1049 .enable = exynos4_clksrc_mask_cam_ctrl,
1050 .ctrlbit = (1 << 28),
1051 },
1052 .sources = &exynos4_clkset_group,
1053 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1054 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1055 }, {
1056 .clk = {
1057 .name = "sclk_cam0",
1058 .enable = exynos4_clksrc_mask_cam_ctrl,
1059 .ctrlbit = (1 << 16),
1060 },
1061 .sources = &exynos4_clkset_group,
1062 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1063 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1064 }, {
1065 .clk = {
1066 .name = "sclk_cam1",
1067 .enable = exynos4_clksrc_mask_cam_ctrl,
1068 .ctrlbit = (1 << 20),
1069 },
1070 .sources = &exynos4_clkset_group,
1071 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1072 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1073 }, {
1074 .clk = {
1075 .name = "sclk_fimc",
1076 .devname = "exynos4-fimc.0",
1077 .enable = exynos4_clksrc_mask_cam_ctrl,
1078 .ctrlbit = (1 << 0),
1079 },
1080 .sources = &exynos4_clkset_group,
1081 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1082 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1083 }, {
1084 .clk = {
1085 .name = "sclk_fimc",
1086 .devname = "exynos4-fimc.1",
1087 .enable = exynos4_clksrc_mask_cam_ctrl,
1088 .ctrlbit = (1 << 4),
1089 },
1090 .sources = &exynos4_clkset_group,
1091 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1092 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1093 }, {
1094 .clk = {
1095 .name = "sclk_fimc",
1096 .devname = "exynos4-fimc.2",
1097 .enable = exynos4_clksrc_mask_cam_ctrl,
1098 .ctrlbit = (1 << 8),
1099 },
1100 .sources = &exynos4_clkset_group,
1101 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1102 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1103 }, {
1104 .clk = {
1105 .name = "sclk_fimc",
1106 .devname = "exynos4-fimc.3",
1107 .enable = exynos4_clksrc_mask_cam_ctrl,
1108 .ctrlbit = (1 << 12),
1109 },
1110 .sources = &exynos4_clkset_group,
1111 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1112 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1113 }, {
1114 .clk = {
1115 .name = "sclk_fimd",
1116 .devname = "exynos4-fb.0",
1117 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1118 .ctrlbit = (1 << 0),
1119 },
1120 .sources = &exynos4_clkset_group,
1121 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1122 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1123 }, {
1124 .clk = {
1125 .name = "sclk_fimg2d",
1126 },
1127 .sources = &exynos4_clkset_mout_g2d,
1128 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1129 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1130 }, {
1131 .clk = {
1132 .name = "sclk_mfc",
1133 .devname = "s5p-mfc",
1134 },
1135 .sources = &exynos4_clkset_mout_mfc,
1136 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1137 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1138 }, {
1139 .clk = {
1140 .name = "sclk_dwmmc",
1141 .parent = &exynos4_clk_dout_mmc4.clk,
1142 .enable = exynos4_clksrc_mask_fsys_ctrl,
1143 .ctrlbit = (1 << 16),
1144 },
1145 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1146 }
1147};
1148
1149static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1150 .clk = {
1151 .name = "uclk1",
1152 .devname = "exynos4210-uart.0",
1153 .enable = exynos4_clksrc_mask_peril0_ctrl,
1154 .ctrlbit = (1 << 0),
1155 },
1156 .sources = &exynos4_clkset_group,
1157 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1158 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1159};
1160
1161static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1162 .clk = {
1163 .name = "uclk1",
1164 .devname = "exynos4210-uart.1",
1165 .enable = exynos4_clksrc_mask_peril0_ctrl,
1166 .ctrlbit = (1 << 4),
1167 },
1168 .sources = &exynos4_clkset_group,
1169 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1170 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1171};
1172
1173static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1174 .clk = {
1175 .name = "uclk1",
1176 .devname = "exynos4210-uart.2",
1177 .enable = exynos4_clksrc_mask_peril0_ctrl,
1178 .ctrlbit = (1 << 8),
1179 },
1180 .sources = &exynos4_clkset_group,
1181 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1182 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1183};
1184
1185static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1186 .clk = {
1187 .name = "uclk1",
1188 .devname = "exynos4210-uart.3",
1189 .enable = exynos4_clksrc_mask_peril0_ctrl,
1190 .ctrlbit = (1 << 12),
1191 },
1192 .sources = &exynos4_clkset_group,
1193 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1194 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1195};
1196
1197static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1198 .clk = {
1199 .name = "sclk_mmc",
1200 .devname = "s3c-sdhci.0",
1201 .parent = &exynos4_clk_dout_mmc0.clk,
1202 .enable = exynos4_clksrc_mask_fsys_ctrl,
1203 .ctrlbit = (1 << 0),
1204 },
1205 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1206};
1207
1208static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1209 .clk = {
1210 .name = "sclk_mmc",
1211 .devname = "s3c-sdhci.1",
1212 .parent = &exynos4_clk_dout_mmc1.clk,
1213 .enable = exynos4_clksrc_mask_fsys_ctrl,
1214 .ctrlbit = (1 << 4),
1215 },
1216 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1217};
1218
1219static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1220 .clk = {
1221 .name = "sclk_mmc",
1222 .devname = "s3c-sdhci.2",
1223 .parent = &exynos4_clk_dout_mmc2.clk,
1224 .enable = exynos4_clksrc_mask_fsys_ctrl,
1225 .ctrlbit = (1 << 8),
1226 },
1227 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1228};
1229
1230static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1231 .clk = {
1232 .name = "sclk_mmc",
1233 .devname = "s3c-sdhci.3",
1234 .parent = &exynos4_clk_dout_mmc3.clk,
1235 .enable = exynos4_clksrc_mask_fsys_ctrl,
1236 .ctrlbit = (1 << 12),
1237 },
1238 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1239};
1240
1241static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1242 .clk = {
1243 .name = "sclk_spi",
1244 .devname = "s3c64xx-spi.0",
1245 .enable = exynos4_clksrc_mask_peril1_ctrl,
1246 .ctrlbit = (1 << 16),
1247 },
1248 .sources = &exynos4_clkset_group,
1249 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1250 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1251};
1252
1253static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1254 .clk = {
1255 .name = "sclk_spi",
1256 .devname = "s3c64xx-spi.1",
1257 .enable = exynos4_clksrc_mask_peril1_ctrl,
1258 .ctrlbit = (1 << 20),
1259 },
1260 .sources = &exynos4_clkset_group,
1261 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1262 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1263};
1264
1265static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1266 .clk = {
1267 .name = "sclk_spi",
1268 .devname = "s3c64xx-spi.2",
1269 .enable = exynos4_clksrc_mask_peril1_ctrl,
1270 .ctrlbit = (1 << 24),
1271 },
1272 .sources = &exynos4_clkset_group,
1273 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1274 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1275};
1276
1277/* Clock initialization code */
1278static struct clksrc_clk *exynos4_sysclks[] = {
1279 &exynos4_clk_mout_apll,
1280 &exynos4_clk_sclk_apll,
1281 &exynos4_clk_mout_epll,
1282 &exynos4_clk_mout_mpll,
1283 &exynos4_clk_moutcore,
1284 &exynos4_clk_coreclk,
1285 &exynos4_clk_armclk,
1286 &exynos4_clk_aclk_corem0,
1287 &exynos4_clk_aclk_cores,
1288 &exynos4_clk_aclk_corem1,
1289 &exynos4_clk_periphclk,
1290 &exynos4_clk_mout_corebus,
1291 &exynos4_clk_sclk_dmc,
1292 &exynos4_clk_aclk_cored,
1293 &exynos4_clk_aclk_corep,
1294 &exynos4_clk_aclk_acp,
1295 &exynos4_clk_pclk_acp,
1296 &exynos4_clk_vpllsrc,
1297 &exynos4_clk_sclk_vpll,
1298 &exynos4_clk_aclk_200,
1299 &exynos4_clk_aclk_100,
1300 &exynos4_clk_aclk_160,
1301 &exynos4_clk_aclk_133,
1302 &exynos4_clk_dout_mmc0,
1303 &exynos4_clk_dout_mmc1,
1304 &exynos4_clk_dout_mmc2,
1305 &exynos4_clk_dout_mmc3,
1306 &exynos4_clk_dout_mmc4,
1307 &exynos4_clk_mout_mfc0,
1308 &exynos4_clk_mout_mfc1,
1309};
1310
1311static struct clk *exynos4_clk_cdev[] = {
1312 &exynos4_clk_pdma0,
1313 &exynos4_clk_pdma1,
1314 &exynos4_clk_mdma1,
1315 &exynos4_clk_fimd0,
1316};
1317
1318static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1319 &exynos4_clk_sclk_uart0,
1320 &exynos4_clk_sclk_uart1,
1321 &exynos4_clk_sclk_uart2,
1322 &exynos4_clk_sclk_uart3,
1323 &exynos4_clk_sclk_mmc0,
1324 &exynos4_clk_sclk_mmc1,
1325 &exynos4_clk_sclk_mmc2,
1326 &exynos4_clk_sclk_mmc3,
1327 &exynos4_clk_sclk_spi0,
1328 &exynos4_clk_sclk_spi1,
1329 &exynos4_clk_sclk_spi2,
1330
1331};
1332
1333static struct clk_lookup exynos4_clk_lookup[] = {
1334 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1335 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1336 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1337 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1338 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1339 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1340 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1341 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1342 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1343 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1344 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1345 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1346 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1347 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1348 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1349};
1350
1351static int xtal_rate;
1352
1353static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1354{
1355 if (soc_is_exynos4210())
1356 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1357 pll_4508);
1358 else if (soc_is_exynos4212() || soc_is_exynos4412())
1359 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1360 else
1361 return 0;
1362}
1363
1364static struct clk_ops exynos4_fout_apll_ops = {
1365 .get_rate = exynos4_fout_apll_get_rate,
1366};
1367
1368static u32 exynos4_vpll_div[][8] = {
1369 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1370 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1371};
1372
1373static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1374{
1375 return clk->rate;
1376}
1377
1378static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1379{
1380 unsigned int vpll_con0, vpll_con1 = 0;
1381 unsigned int i;
1382
1383 /* Return if nothing changed */
1384 if (clk->rate == rate)
1385 return 0;
1386
1387 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1388 vpll_con0 &= ~(0x1 << 27 | \
1389 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1390 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1391 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1392
1393 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1394 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1395 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1396 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1397
1398 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1399 if (exynos4_vpll_div[i][0] == rate) {
1400 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1401 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1402 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1403 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1404 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1405 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1406 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1407 break;
1408 }
1409 }
1410
1411 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1412 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1413 __func__);
1414 return -EINVAL;
1415 }
1416
1417 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1418 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1419
1420 /* Wait for VPLL lock */
1421 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1422 continue;
1423
1424 clk->rate = rate;
1425 return 0;
1426}
1427
1428static struct clk_ops exynos4_vpll_ops = {
1429 .get_rate = exynos4_vpll_get_rate,
1430 .set_rate = exynos4_vpll_set_rate,
1431};
1432
1433void __init_or_cpufreq exynos4_setup_clocks(void)
1434{
1435 struct clk *xtal_clk;
1436 unsigned long apll = 0;
1437 unsigned long mpll = 0;
1438 unsigned long epll = 0;
1439 unsigned long vpll = 0;
1440 unsigned long vpllsrc;
1441 unsigned long xtal;
1442 unsigned long armclk;
1443 unsigned long sclk_dmc;
1444 unsigned long aclk_200;
1445 unsigned long aclk_100;
1446 unsigned long aclk_160;
1447 unsigned long aclk_133;
1448 unsigned int ptr;
1449
1450 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1451
1452 xtal_clk = clk_get(NULL, "xtal");
1453 BUG_ON(IS_ERR(xtal_clk));
1454
1455 xtal = clk_get_rate(xtal_clk);
1456
1457 xtal_rate = xtal;
1458
1459 clk_put(xtal_clk);
1460
1461 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1462
1463 if (soc_is_exynos4210()) {
1464 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1465 pll_4508);
1466 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1467 pll_4508);
1468 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1469 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1470
1471 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1472 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1473 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1474 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1475 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1476 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1477 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1478 __raw_readl(EXYNOS4_EPLL_CON1));
1479
1480 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1481 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1482 __raw_readl(EXYNOS4_VPLL_CON1));
1483 } else {
1484 /* nothing */
1485 }
1486
1487 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1488 clk_fout_mpll.rate = mpll;
1489 clk_fout_epll.rate = epll;
1490 clk_fout_vpll.ops = &exynos4_vpll_ops;
1491 clk_fout_vpll.rate = vpll;
1492
1493 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1494 apll, mpll, epll, vpll);
1495
1496 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1497 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1498
1499 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1500 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1501 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1502 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1503
1504 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1505 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1506 armclk, sclk_dmc, aclk_200,
1507 aclk_100, aclk_160, aclk_133);
1508
1509 clk_f.rate = armclk;
1510 clk_h.rate = sclk_dmc;
1511 clk_p.rate = aclk_100;
1512
1513 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1514 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1515}
1516
1517static struct clk *exynos4_clks[] __initdata = {
1518 &exynos4_clk_sclk_hdmi27m,
1519 &exynos4_clk_sclk_hdmiphy,
1520 &exynos4_clk_sclk_usbphy0,
1521 &exynos4_clk_sclk_usbphy1,
1522};
1523
1524#ifdef CONFIG_PM_SLEEP
1525static int exynos4_clock_suspend(void)
1526{
1527 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1528 return 0;
1529}
1530
1531static void exynos4_clock_resume(void)
1532{
1533 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1534}
1535
1536#else
1537#define exynos4_clock_suspend NULL
1538#define exynos4_clock_resume NULL
1539#endif
1540
1541static struct syscore_ops exynos4_clock_syscore_ops = {
1542 .suspend = exynos4_clock_suspend,
1543 .resume = exynos4_clock_resume,
1544};
1545
1546void __init exynos4_register_clocks(void)
1547{
1548 int ptr;
1549
1550 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1551
1552 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1553 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1554
1555 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1556 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1557
1558 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1559 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1560
1561 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1562 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1563
1564 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1565 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1566 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1567
1568 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1569 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1570 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1571
1572 register_syscore_ops(&exynos4_clock_syscore_ops);
1573 s3c24xx_register_clock(&dummy_apb_pclk);
1574
1575 s3c_pwmclk_init();
1576}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 00000000000..cb71c29c14d
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for exynos4 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_CLOCK_H
13#define __ASM_ARCH_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk exynos4_clk_aclk_133;
18extern struct clksrc_clk exynos4_clk_mout_mpll;
19
20extern struct clksrc_sources exynos4_clkset_mout_corebus;
21extern struct clksrc_sources exynos4_clkset_group;
22
23extern struct clk *exynos4_clkset_aclk_top_list[];
24extern struct clk *exynos4_clkset_group_list[];
25
26extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
27extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
28extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
29
30#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 13312ccb2d9..3b131e4b6ef 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4210.c 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 3 * http://www.samsung.com
6 * 4 *
7 * EXYNOS4210 - Clock support 5 * EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@
28#include <mach/hardware.h> 26#include <mach/hardware.h>
29#include <mach/map.h> 27#include <mach/map.h>
30#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 29
33#include "common.h" 30#include "common.h"
31#include "clock-exynos4.h"
34 32
35#ifdef CONFIG_PM_SLEEP 33#ifdef CONFIG_PM_SLEEP
36static struct sleep_save exynos4210_clock_save[] = { 34static struct sleep_save exynos4210_clock_save[] = {
37 SAVE_ITEM(S5P_CLKSRC_IMAGE), 35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
38 SAVE_ITEM(S5P_CLKSRC_LCD1), 36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
39 SAVE_ITEM(S5P_CLKDIV_IMAGE), 37 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
40 SAVE_ITEM(S5P_CLKDIV_LCD1), 38 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
41 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), 39 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
42 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), 40 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
43 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
44 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
45}; 43};
46#endif 44#endif
47 45
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
51 49
52static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 50static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
53{ 51{
54 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); 52 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
55} 53}
56 54
57static struct clksrc_clk clksrcs[] = { 55static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
62 .enable = exynos4_clksrc_mask_fsys_ctrl, 60 .enable = exynos4_clksrc_mask_fsys_ctrl,
63 .ctrlbit = (1 << 24), 61 .ctrlbit = (1 << 24),
64 }, 62 },
65 .sources = &clkset_mout_corebus, 63 .sources = &exynos4_clkset_mout_corebus,
66 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, 64 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
67 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, 65 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
68 }, { 66 }, {
69 .clk = { 67 .clk = {
70 .name = "sclk_fimd", 68 .name = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
72 .enable = exynos4_clksrc_mask_lcd1_ctrl, 70 .enable = exynos4_clksrc_mask_lcd1_ctrl,
73 .ctrlbit = (1 << 0), 71 .ctrlbit = (1 << 0),
74 }, 72 },
75 .sources = &clkset_group, 73 .sources = &exynos4_clkset_group,
76 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, 74 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
77 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, 75 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
78 }, 76 },
79}; 77};
80 78
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
82 { 80 {
83 .name = "sataphy", 81 .name = "sataphy",
84 .id = -1, 82 .id = -1,
85 .parent = &clk_aclk_133.clk, 83 .parent = &exynos4_clk_aclk_133.clk,
86 .enable = exynos4_clk_ip_fsys_ctrl, 84 .enable = exynos4_clk_ip_fsys_ctrl,
87 .ctrlbit = (1 << 3), 85 .ctrlbit = (1 << 3),
88 }, { 86 }, {
89 .name = "sata", 87 .name = "sata",
90 .id = -1, 88 .id = -1,
91 .parent = &clk_aclk_133.clk, 89 .parent = &exynos4_clk_aclk_133.clk,
92 .enable = exynos4_clk_ip_fsys_ctrl, 90 .enable = exynos4_clk_ip_fsys_ctrl,
93 .ctrlbit = (1 << 10), 91 .ctrlbit = (1 << 10),
94 }, { 92 }, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
117#define exynos4210_clock_resume NULL 115#define exynos4210_clock_resume NULL
118#endif 116#endif
119 117
120struct syscore_ops exynos4210_clock_syscore_ops = { 118static struct syscore_ops exynos4210_clock_syscore_ops = {
121 .suspend = exynos4210_clock_suspend, 119 .suspend = exynos4210_clock_suspend,
122 .resume = exynos4210_clock_resume, 120 .resume = exynos4210_clock_resume,
123}; 121};
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
126{ 124{
127 int ptr; 125 int ptr;
128 126
129 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; 127 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
130 clk_mout_mpll.reg_src.shift = 8; 128 exynos4_clk_mout_mpll.reg_src.shift = 8;
131 clk_mout_mpll.reg_src.size = 1; 129 exynos4_clk_mout_mpll.reg_src.size = 1;
132 130
133 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 131 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
134 s3c_register_clksrc(sysclks[ptr], 1); 132 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 48af28566fa..3ecc01e06f7 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 3 * http://www.samsung.com
6 * 4 *
7 * EXYNOS4212 - Clock support 5 * EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@
28#include <mach/hardware.h> 26#include <mach/hardware.h>
29#include <mach/map.h> 27#include <mach/map.h>
30#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
31#include <mach/exynos4-clock.h>
32 29
33#include "common.h" 30#include "common.h"
31#include "clock-exynos4.h"
34 32
35#ifdef CONFIG_PM_SLEEP 33#ifdef CONFIG_PM_SLEEP
36static struct sleep_save exynos4212_clock_save[] = { 34static struct sleep_save exynos4212_clock_save[] = {
37 SAVE_ITEM(S5P_CLKSRC_IMAGE), 35 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_IMAGE), 36 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 37 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
41}; 39};
42#endif 40#endif
43 41
44static struct clk *clk_src_mpll_user_list[] = { 42static struct clk *clk_src_mpll_user_list[] = {
45 [0] = &clk_fin_mpll, 43 [0] = &clk_fin_mpll,
46 [1] = &clk_mout_mpll.clk, 44 [1] = &exynos4_clk_mout_mpll.clk,
47}; 45};
48 46
49static struct clksrc_sources clk_src_mpll_user = { 47static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
56 .name = "mout_mpll_user", 54 .name = "mout_mpll_user",
57 }, 55 },
58 .sources = &clk_src_mpll_user, 56 .sources = &clk_src_mpll_user,
59 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, 57 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
60}; 58};
61 59
62static struct clksrc_clk *sysclks[] = { 60static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
89#define exynos4212_clock_resume NULL 87#define exynos4212_clock_resume NULL
90#endif 88#endif
91 89
92struct syscore_ops exynos4212_clock_syscore_ops = { 90static struct syscore_ops exynos4212_clock_syscore_ops = {
93 .suspend = exynos4212_clock_suspend, 91 .suspend = exynos4212_clock_suspend,
94 .resume = exynos4212_clock_resume, 92 .resume = exynos4212_clock_resume,
95}; 93};
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
99 int ptr; 97 int ptr;
100 98
101 /* usbphy1 is removed */ 99 /* usbphy1 is removed */
102 clkset_group_list[4] = NULL; 100 exynos4_clkset_group_list[4] = NULL;
103 101
104 /* mout_mpll_user is used */ 102 /* mout_mpll_user is used */
105 clkset_group_list[6] = &clk_mout_mpll_user.clk; 103 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
106 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; 104 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
107 105
108 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; 106 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
109 clk_mout_mpll.reg_src.shift = 12; 107 exynos4_clk_mout_mpll.reg_src.shift = 12;
110 clk_mout_mpll.reg_src.size = 1; 108 exynos4_clk_mout_mpll.reg_src.size = 1;
111 109
112 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 110 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
113 s3c_register_clksrc(sysclks[ptr], 1); 111 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 00000000000..d013982d0f8
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30
31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos5_clock_save[] = {
33 /* will be implemented */
34};
35#endif
36
37static struct clk exynos5_clk_sclk_dptxphy = {
38 .name = "sclk_dptx",
39};
40
41static struct clk exynos5_clk_sclk_hdmi24m = {
42 .name = "sclk_hdmi24m",
43 .rate = 24000000,
44};
45
46static struct clk exynos5_clk_sclk_hdmi27m = {
47 .name = "sclk_hdmi27m",
48 .rate = 27000000,
49};
50
51static struct clk exynos5_clk_sclk_hdmiphy = {
52 .name = "sclk_hdmiphy",
53};
54
55static struct clk exynos5_clk_sclk_usbphy = {
56 .name = "sclk_usbphy",
57 .rate = 48000000,
58};
59
60static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
61{
62 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
63}
64
65static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
66{
67 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
68}
69
70static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
71{
72 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
73}
74
75static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
76{
77 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
78}
79
80static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
81{
82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
83}
84
85static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
86{
87 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
88}
89
90static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
91{
92 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
93}
94
95static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
96{
97 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
98}
99
100static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
101{
102 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
103}
104
105static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
106{
107 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
108}
109
110static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
113}
114
115static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
118}
119
120static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
123}
124
125static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
128}
129
130/* Core list of CMU_CPU side */
131
132static struct clksrc_clk exynos5_clk_mout_apll = {
133 .clk = {
134 .name = "mout_apll",
135 },
136 .sources = &clk_src_apll,
137 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
138};
139
140static struct clksrc_clk exynos5_clk_sclk_apll = {
141 .clk = {
142 .name = "sclk_apll",
143 .parent = &exynos5_clk_mout_apll.clk,
144 },
145 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
146};
147
148static struct clksrc_clk exynos5_clk_mout_bpll = {
149 .clk = {
150 .name = "mout_bpll",
151 },
152 .sources = &clk_src_bpll,
153 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
154};
155
156static struct clk *exynos5_clk_src_bpll_user_list[] = {
157 [0] = &clk_fin_mpll,
158 [1] = &exynos5_clk_mout_bpll.clk,
159};
160
161static struct clksrc_sources exynos5_clk_src_bpll_user = {
162 .sources = exynos5_clk_src_bpll_user_list,
163 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
164};
165
166static struct clksrc_clk exynos5_clk_mout_bpll_user = {
167 .clk = {
168 .name = "mout_bpll_user",
169 },
170 .sources = &exynos5_clk_src_bpll_user,
171 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
172};
173
174static struct clksrc_clk exynos5_clk_mout_cpll = {
175 .clk = {
176 .name = "mout_cpll",
177 },
178 .sources = &clk_src_cpll,
179 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
180};
181
182static struct clksrc_clk exynos5_clk_mout_epll = {
183 .clk = {
184 .name = "mout_epll",
185 },
186 .sources = &clk_src_epll,
187 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
188};
189
190struct clksrc_clk exynos5_clk_mout_mpll = {
191 .clk = {
192 .name = "mout_mpll",
193 },
194 .sources = &clk_src_mpll,
195 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
196};
197
198static struct clk *exynos_clkset_vpllsrc_list[] = {
199 [0] = &clk_fin_vpll,
200 [1] = &exynos5_clk_sclk_hdmi27m,
201};
202
203static struct clksrc_sources exynos5_clkset_vpllsrc = {
204 .sources = exynos_clkset_vpllsrc_list,
205 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
206};
207
208static struct clksrc_clk exynos5_clk_vpllsrc = {
209 .clk = {
210 .name = "vpll_src",
211 .enable = exynos5_clksrc_mask_top_ctrl,
212 .ctrlbit = (1 << 0),
213 },
214 .sources = &exynos5_clkset_vpllsrc,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
216};
217
218static struct clk *exynos5_clkset_sclk_vpll_list[] = {
219 [0] = &exynos5_clk_vpllsrc.clk,
220 [1] = &clk_fout_vpll,
221};
222
223static struct clksrc_sources exynos5_clkset_sclk_vpll = {
224 .sources = exynos5_clkset_sclk_vpll_list,
225 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
226};
227
228static struct clksrc_clk exynos5_clk_sclk_vpll = {
229 .clk = {
230 .name = "sclk_vpll",
231 },
232 .sources = &exynos5_clkset_sclk_vpll,
233 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
234};
235
236static struct clksrc_clk exynos5_clk_sclk_pixel = {
237 .clk = {
238 .name = "sclk_pixel",
239 .parent = &exynos5_clk_sclk_vpll.clk,
240 },
241 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
242};
243
244static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
245 [0] = &exynos5_clk_sclk_pixel.clk,
246 [1] = &exynos5_clk_sclk_hdmiphy,
247};
248
249static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
250 .sources = exynos5_clkset_sclk_hdmi_list,
251 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
252};
253
254static struct clksrc_clk exynos5_clk_sclk_hdmi = {
255 .clk = {
256 .name = "sclk_hdmi",
257 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
258 .ctrlbit = (1 << 20),
259 },
260 .sources = &exynos5_clkset_sclk_hdmi,
261 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
262};
263
264static struct clksrc_clk *exynos5_sclk_tv[] = {
265 &exynos5_clk_sclk_pixel,
266 &exynos5_clk_sclk_hdmi,
267};
268
269static struct clk *exynos5_clk_src_mpll_user_list[] = {
270 [0] = &clk_fin_mpll,
271 [1] = &exynos5_clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources exynos5_clk_src_mpll_user = {
275 .sources = exynos5_clk_src_mpll_user_list,
276 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
277};
278
279static struct clksrc_clk exynos5_clk_mout_mpll_user = {
280 .clk = {
281 .name = "mout_mpll_user",
282 },
283 .sources = &exynos5_clk_src_mpll_user,
284 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
285};
286
287static struct clk *exynos5_clkset_mout_cpu_list[] = {
288 [0] = &exynos5_clk_mout_apll.clk,
289 [1] = &exynos5_clk_mout_mpll.clk,
290};
291
292static struct clksrc_sources exynos5_clkset_mout_cpu = {
293 .sources = exynos5_clkset_mout_cpu_list,
294 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
295};
296
297static struct clksrc_clk exynos5_clk_mout_cpu = {
298 .clk = {
299 .name = "mout_cpu",
300 },
301 .sources = &exynos5_clkset_mout_cpu,
302 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
303};
304
305static struct clksrc_clk exynos5_clk_dout_armclk = {
306 .clk = {
307 .name = "dout_armclk",
308 .parent = &exynos5_clk_mout_cpu.clk,
309 },
310 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
311};
312
313static struct clksrc_clk exynos5_clk_dout_arm2clk = {
314 .clk = {
315 .name = "dout_arm2clk",
316 .parent = &exynos5_clk_dout_armclk.clk,
317 },
318 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
319};
320
321static struct clk exynos5_clk_armclk = {
322 .name = "armclk",
323 .parent = &exynos5_clk_dout_arm2clk.clk,
324};
325
326/* Core list of CMU_CDREX side */
327
328static struct clk *exynos5_clkset_cdrex_list[] = {
329 [0] = &exynos5_clk_mout_mpll.clk,
330 [1] = &exynos5_clk_mout_bpll.clk,
331};
332
333static struct clksrc_sources exynos5_clkset_cdrex = {
334 .sources = exynos5_clkset_cdrex_list,
335 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
336};
337
338static struct clksrc_clk exynos5_clk_cdrex = {
339 .clk = {
340 .name = "clk_cdrex",
341 },
342 .sources = &exynos5_clkset_cdrex,
343 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
344 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos5_clk_aclk_acp = {
348 .clk = {
349 .name = "aclk_acp",
350 .parent = &exynos5_clk_mout_mpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
353};
354
355static struct clksrc_clk exynos5_clk_pclk_acp = {
356 .clk = {
357 .name = "pclk_acp",
358 .parent = &exynos5_clk_aclk_acp.clk,
359 },
360 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
361};
362
363/* Core list of CMU_TOP side */
364
365struct clk *exynos5_clkset_aclk_top_list[] = {
366 [0] = &exynos5_clk_mout_mpll_user.clk,
367 [1] = &exynos5_clk_mout_bpll_user.clk,
368};
369
370struct clksrc_sources exynos5_clkset_aclk = {
371 .sources = exynos5_clkset_aclk_top_list,
372 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
373};
374
375static struct clksrc_clk exynos5_clk_aclk_400 = {
376 .clk = {
377 .name = "aclk_400",
378 },
379 .sources = &exynos5_clkset_aclk,
380 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
381 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
382};
383
384struct clk *exynos5_clkset_aclk_333_166_list[] = {
385 [0] = &exynos5_clk_mout_cpll.clk,
386 [1] = &exynos5_clk_mout_mpll_user.clk,
387};
388
389struct clksrc_sources exynos5_clkset_aclk_333_166 = {
390 .sources = exynos5_clkset_aclk_333_166_list,
391 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
392};
393
394static struct clksrc_clk exynos5_clk_aclk_333 = {
395 .clk = {
396 .name = "aclk_333",
397 },
398 .sources = &exynos5_clkset_aclk_333_166,
399 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
400 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
401};
402
403static struct clksrc_clk exynos5_clk_aclk_166 = {
404 .clk = {
405 .name = "aclk_166",
406 },
407 .sources = &exynos5_clkset_aclk_333_166,
408 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
409 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
410};
411
412static struct clksrc_clk exynos5_clk_aclk_266 = {
413 .clk = {
414 .name = "aclk_266",
415 .parent = &exynos5_clk_mout_mpll_user.clk,
416 },
417 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
418};
419
420static struct clksrc_clk exynos5_clk_aclk_200 = {
421 .clk = {
422 .name = "aclk_200",
423 },
424 .sources = &exynos5_clkset_aclk,
425 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
426 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
427};
428
429static struct clksrc_clk exynos5_clk_aclk_66_pre = {
430 .clk = {
431 .name = "aclk_66_pre",
432 .parent = &exynos5_clk_mout_mpll_user.clk,
433 },
434 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
435};
436
437static struct clksrc_clk exynos5_clk_aclk_66 = {
438 .clk = {
439 .name = "aclk_66",
440 .parent = &exynos5_clk_aclk_66_pre.clk,
441 },
442 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
443};
444
445static struct clk exynos5_init_clocks_off[] = {
446 {
447 .name = "timers",
448 .parent = &exynos5_clk_aclk_66.clk,
449 .enable = exynos5_clk_ip_peric_ctrl,
450 .ctrlbit = (1 << 24),
451 }, {
452 .name = "rtc",
453 .parent = &exynos5_clk_aclk_66.clk,
454 .enable = exynos5_clk_ip_peris_ctrl,
455 .ctrlbit = (1 << 20),
456 }, {
457 .name = "hsmmc",
458 .devname = "s3c-sdhci.0",
459 .parent = &exynos5_clk_aclk_200.clk,
460 .enable = exynos5_clk_ip_fsys_ctrl,
461 .ctrlbit = (1 << 12),
462 }, {
463 .name = "hsmmc",
464 .devname = "s3c-sdhci.1",
465 .parent = &exynos5_clk_aclk_200.clk,
466 .enable = exynos5_clk_ip_fsys_ctrl,
467 .ctrlbit = (1 << 13),
468 }, {
469 .name = "hsmmc",
470 .devname = "s3c-sdhci.2",
471 .parent = &exynos5_clk_aclk_200.clk,
472 .enable = exynos5_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 14),
474 }, {
475 .name = "hsmmc",
476 .devname = "s3c-sdhci.3",
477 .parent = &exynos5_clk_aclk_200.clk,
478 .enable = exynos5_clk_ip_fsys_ctrl,
479 .ctrlbit = (1 << 15),
480 }, {
481 .name = "dwmci",
482 .parent = &exynos5_clk_aclk_200.clk,
483 .enable = exynos5_clk_ip_fsys_ctrl,
484 .ctrlbit = (1 << 16),
485 }, {
486 .name = "sata",
487 .devname = "ahci",
488 .enable = exynos5_clk_ip_fsys_ctrl,
489 .ctrlbit = (1 << 6),
490 }, {
491 .name = "sata_phy",
492 .enable = exynos5_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 24),
494 }, {
495 .name = "sata_phy_i2c",
496 .enable = exynos5_clk_ip_fsys_ctrl,
497 .ctrlbit = (1 << 25),
498 }, {
499 .name = "mfc",
500 .devname = "s5p-mfc",
501 .enable = exynos5_clk_ip_mfc_ctrl,
502 .ctrlbit = (1 << 0),
503 }, {
504 .name = "hdmi",
505 .devname = "exynos4-hdmi",
506 .enable = exynos5_clk_ip_disp1_ctrl,
507 .ctrlbit = (1 << 6),
508 }, {
509 .name = "mixer",
510 .devname = "s5p-mixer",
511 .enable = exynos5_clk_ip_disp1_ctrl,
512 .ctrlbit = (1 << 5),
513 }, {
514 .name = "jpeg",
515 .enable = exynos5_clk_ip_gen_ctrl,
516 .ctrlbit = (1 << 2),
517 }, {
518 .name = "dsim0",
519 .enable = exynos5_clk_ip_disp1_ctrl,
520 .ctrlbit = (1 << 3),
521 }, {
522 .name = "iis",
523 .devname = "samsung-i2s.1",
524 .enable = exynos5_clk_ip_peric_ctrl,
525 .ctrlbit = (1 << 20),
526 }, {
527 .name = "iis",
528 .devname = "samsung-i2s.2",
529 .enable = exynos5_clk_ip_peric_ctrl,
530 .ctrlbit = (1 << 21),
531 }, {
532 .name = "pcm",
533 .devname = "samsung-pcm.1",
534 .enable = exynos5_clk_ip_peric_ctrl,
535 .ctrlbit = (1 << 22),
536 }, {
537 .name = "pcm",
538 .devname = "samsung-pcm.2",
539 .enable = exynos5_clk_ip_peric_ctrl,
540 .ctrlbit = (1 << 23),
541 }, {
542 .name = "spdif",
543 .devname = "samsung-spdif",
544 .enable = exynos5_clk_ip_peric_ctrl,
545 .ctrlbit = (1 << 26),
546 }, {
547 .name = "ac97",
548 .devname = "samsung-ac97",
549 .enable = exynos5_clk_ip_peric_ctrl,
550 .ctrlbit = (1 << 27),
551 }, {
552 .name = "usbhost",
553 .enable = exynos5_clk_ip_fsys_ctrl ,
554 .ctrlbit = (1 << 18),
555 }, {
556 .name = "usbotg",
557 .enable = exynos5_clk_ip_fsys_ctrl,
558 .ctrlbit = (1 << 7),
559 }, {
560 .name = "gps",
561 .enable = exynos5_clk_ip_gps_ctrl,
562 .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
563 }, {
564 .name = "nfcon",
565 .enable = exynos5_clk_ip_fsys_ctrl,
566 .ctrlbit = (1 << 22),
567 }, {
568 .name = "iop",
569 .enable = exynos5_clk_ip_fsys_ctrl,
570 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
571 }, {
572 .name = "core_iop",
573 .enable = exynos5_clk_ip_core_ctrl,
574 .ctrlbit = ((1 << 21) | (1 << 3)),
575 }, {
576 .name = "mcu_iop",
577 .enable = exynos5_clk_ip_fsys_ctrl,
578 .ctrlbit = (1 << 0),
579 }, {
580 .name = "i2c",
581 .devname = "s3c2440-i2c.0",
582 .parent = &exynos5_clk_aclk_66.clk,
583 .enable = exynos5_clk_ip_peric_ctrl,
584 .ctrlbit = (1 << 6),
585 }, {
586 .name = "i2c",
587 .devname = "s3c2440-i2c.1",
588 .parent = &exynos5_clk_aclk_66.clk,
589 .enable = exynos5_clk_ip_peric_ctrl,
590 .ctrlbit = (1 << 7),
591 }, {
592 .name = "i2c",
593 .devname = "s3c2440-i2c.2",
594 .parent = &exynos5_clk_aclk_66.clk,
595 .enable = exynos5_clk_ip_peric_ctrl,
596 .ctrlbit = (1 << 8),
597 }, {
598 .name = "i2c",
599 .devname = "s3c2440-i2c.3",
600 .parent = &exynos5_clk_aclk_66.clk,
601 .enable = exynos5_clk_ip_peric_ctrl,
602 .ctrlbit = (1 << 9),
603 }, {
604 .name = "i2c",
605 .devname = "s3c2440-i2c.4",
606 .parent = &exynos5_clk_aclk_66.clk,
607 .enable = exynos5_clk_ip_peric_ctrl,
608 .ctrlbit = (1 << 10),
609 }, {
610 .name = "i2c",
611 .devname = "s3c2440-i2c.5",
612 .parent = &exynos5_clk_aclk_66.clk,
613 .enable = exynos5_clk_ip_peric_ctrl,
614 .ctrlbit = (1 << 11),
615 }, {
616 .name = "i2c",
617 .devname = "s3c2440-i2c.6",
618 .parent = &exynos5_clk_aclk_66.clk,
619 .enable = exynos5_clk_ip_peric_ctrl,
620 .ctrlbit = (1 << 12),
621 }, {
622 .name = "i2c",
623 .devname = "s3c2440-i2c.7",
624 .parent = &exynos5_clk_aclk_66.clk,
625 .enable = exynos5_clk_ip_peric_ctrl,
626 .ctrlbit = (1 << 13),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-hdmiphy-i2c",
630 .parent = &exynos5_clk_aclk_66.clk,
631 .enable = exynos5_clk_ip_peric_ctrl,
632 .ctrlbit = (1 << 14),
633 }
634};
635
636static struct clk exynos5_init_clocks_on[] = {
637 {
638 .name = "uart",
639 .devname = "s5pv210-uart.0",
640 .enable = exynos5_clk_ip_peric_ctrl,
641 .ctrlbit = (1 << 0),
642 }, {
643 .name = "uart",
644 .devname = "s5pv210-uart.1",
645 .enable = exynos5_clk_ip_peric_ctrl,
646 .ctrlbit = (1 << 1),
647 }, {
648 .name = "uart",
649 .devname = "s5pv210-uart.2",
650 .enable = exynos5_clk_ip_peric_ctrl,
651 .ctrlbit = (1 << 2),
652 }, {
653 .name = "uart",
654 .devname = "s5pv210-uart.3",
655 .enable = exynos5_clk_ip_peric_ctrl,
656 .ctrlbit = (1 << 3),
657 }, {
658 .name = "uart",
659 .devname = "s5pv210-uart.4",
660 .enable = exynos5_clk_ip_peric_ctrl,
661 .ctrlbit = (1 << 4),
662 }, {
663 .name = "uart",
664 .devname = "s5pv210-uart.5",
665 .enable = exynos5_clk_ip_peric_ctrl,
666 .ctrlbit = (1 << 5),
667 }
668};
669
670static struct clk exynos5_clk_pdma0 = {
671 .name = "dma",
672 .devname = "dma-pl330.0",
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 1),
675};
676
677static struct clk exynos5_clk_pdma1 = {
678 .name = "dma",
679 .devname = "dma-pl330.1",
680 .enable = exynos5_clk_ip_fsys_ctrl,
681 .ctrlbit = (1 << 1),
682};
683
684static struct clk exynos5_clk_mdma1 = {
685 .name = "dma",
686 .devname = "dma-pl330.2",
687 .enable = exynos5_clk_ip_gen_ctrl,
688 .ctrlbit = (1 << 4),
689};
690
691struct clk *exynos5_clkset_group_list[] = {
692 [0] = &clk_ext_xtal_mux,
693 [1] = NULL,
694 [2] = &exynos5_clk_sclk_hdmi24m,
695 [3] = &exynos5_clk_sclk_dptxphy,
696 [4] = &exynos5_clk_sclk_usbphy,
697 [5] = &exynos5_clk_sclk_hdmiphy,
698 [6] = &exynos5_clk_mout_mpll_user.clk,
699 [7] = &exynos5_clk_mout_epll.clk,
700 [8] = &exynos5_clk_sclk_vpll.clk,
701 [9] = &exynos5_clk_mout_cpll.clk,
702};
703
704struct clksrc_sources exynos5_clkset_group = {
705 .sources = exynos5_clkset_group_list,
706 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
707};
708
709/* Possible clock sources for aclk_266_gscl_sub Mux */
710static struct clk *clk_src_gscl_266_list[] = {
711 [0] = &clk_ext_xtal_mux,
712 [1] = &exynos5_clk_aclk_266.clk,
713};
714
715static struct clksrc_sources clk_src_gscl_266 = {
716 .sources = clk_src_gscl_266_list,
717 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
718};
719
720static struct clksrc_clk exynos5_clk_dout_mmc0 = {
721 .clk = {
722 .name = "dout_mmc0",
723 },
724 .sources = &exynos5_clkset_group,
725 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
726 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
727};
728
729static struct clksrc_clk exynos5_clk_dout_mmc1 = {
730 .clk = {
731 .name = "dout_mmc1",
732 },
733 .sources = &exynos5_clkset_group,
734 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
735 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
736};
737
738static struct clksrc_clk exynos5_clk_dout_mmc2 = {
739 .clk = {
740 .name = "dout_mmc2",
741 },
742 .sources = &exynos5_clkset_group,
743 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
744 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
745};
746
747static struct clksrc_clk exynos5_clk_dout_mmc3 = {
748 .clk = {
749 .name = "dout_mmc3",
750 },
751 .sources = &exynos5_clkset_group,
752 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
753 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
754};
755
756static struct clksrc_clk exynos5_clk_dout_mmc4 = {
757 .clk = {
758 .name = "dout_mmc4",
759 },
760 .sources = &exynos5_clkset_group,
761 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
762 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
763};
764
765static struct clksrc_clk exynos5_clk_sclk_uart0 = {
766 .clk = {
767 .name = "uclk1",
768 .devname = "exynos4210-uart.0",
769 .enable = exynos5_clksrc_mask_peric0_ctrl,
770 .ctrlbit = (1 << 0),
771 },
772 .sources = &exynos5_clkset_group,
773 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
774 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
775};
776
777static struct clksrc_clk exynos5_clk_sclk_uart1 = {
778 .clk = {
779 .name = "uclk1",
780 .devname = "exynos4210-uart.1",
781 .enable = exynos5_clksrc_mask_peric0_ctrl,
782 .ctrlbit = (1 << 4),
783 },
784 .sources = &exynos5_clkset_group,
785 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
786 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
787};
788
789static struct clksrc_clk exynos5_clk_sclk_uart2 = {
790 .clk = {
791 .name = "uclk1",
792 .devname = "exynos4210-uart.2",
793 .enable = exynos5_clksrc_mask_peric0_ctrl,
794 .ctrlbit = (1 << 8),
795 },
796 .sources = &exynos5_clkset_group,
797 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
798 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
799};
800
801static struct clksrc_clk exynos5_clk_sclk_uart3 = {
802 .clk = {
803 .name = "uclk1",
804 .devname = "exynos4210-uart.3",
805 .enable = exynos5_clksrc_mask_peric0_ctrl,
806 .ctrlbit = (1 << 12),
807 },
808 .sources = &exynos5_clkset_group,
809 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
810 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
811};
812
813static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
814 .clk = {
815 .name = "sclk_mmc",
816 .devname = "s3c-sdhci.0",
817 .parent = &exynos5_clk_dout_mmc0.clk,
818 .enable = exynos5_clksrc_mask_fsys_ctrl,
819 .ctrlbit = (1 << 0),
820 },
821 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
822};
823
824static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
825 .clk = {
826 .name = "sclk_mmc",
827 .devname = "s3c-sdhci.1",
828 .parent = &exynos5_clk_dout_mmc1.clk,
829 .enable = exynos5_clksrc_mask_fsys_ctrl,
830 .ctrlbit = (1 << 4),
831 },
832 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
833};
834
835static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
836 .clk = {
837 .name = "sclk_mmc",
838 .devname = "s3c-sdhci.2",
839 .parent = &exynos5_clk_dout_mmc2.clk,
840 .enable = exynos5_clksrc_mask_fsys_ctrl,
841 .ctrlbit = (1 << 8),
842 },
843 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
844};
845
846static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
847 .clk = {
848 .name = "sclk_mmc",
849 .devname = "s3c-sdhci.3",
850 .parent = &exynos5_clk_dout_mmc3.clk,
851 .enable = exynos5_clksrc_mask_fsys_ctrl,
852 .ctrlbit = (1 << 12),
853 },
854 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
855};
856
857static struct clksrc_clk exynos5_clksrcs[] = {
858 {
859 .clk = {
860 .name = "sclk_dwmci",
861 .parent = &exynos5_clk_dout_mmc4.clk,
862 .enable = exynos5_clksrc_mask_fsys_ctrl,
863 .ctrlbit = (1 << 16),
864 },
865 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
866 }, {
867 .clk = {
868 .name = "sclk_fimd",
869 .devname = "s3cfb.1",
870 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
871 .ctrlbit = (1 << 0),
872 },
873 .sources = &exynos5_clkset_group,
874 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
875 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
876 }, {
877 .clk = {
878 .name = "aclk_266_gscl",
879 },
880 .sources = &clk_src_gscl_266,
881 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
882 }, {
883 .clk = {
884 .name = "sclk_g3d",
885 .devname = "mali-t604.0",
886 .enable = exynos5_clk_block_ctrl,
887 .ctrlbit = (1 << 1),
888 },
889 .sources = &exynos5_clkset_aclk,
890 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
891 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
892 }, {
893 .clk = {
894 .name = "sclk_gscl_wrap",
895 .devname = "s5p-mipi-csis.0",
896 .enable = exynos5_clksrc_mask_gscl_ctrl,
897 .ctrlbit = (1 << 24),
898 },
899 .sources = &exynos5_clkset_group,
900 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
901 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
902 }, {
903 .clk = {
904 .name = "sclk_gscl_wrap",
905 .devname = "s5p-mipi-csis.1",
906 .enable = exynos5_clksrc_mask_gscl_ctrl,
907 .ctrlbit = (1 << 28),
908 },
909 .sources = &exynos5_clkset_group,
910 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
911 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
912 }, {
913 .clk = {
914 .name = "sclk_cam0",
915 .enable = exynos5_clksrc_mask_gscl_ctrl,
916 .ctrlbit = (1 << 16),
917 },
918 .sources = &exynos5_clkset_group,
919 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
920 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
921 }, {
922 .clk = {
923 .name = "sclk_cam1",
924 .enable = exynos5_clksrc_mask_gscl_ctrl,
925 .ctrlbit = (1 << 20),
926 },
927 .sources = &exynos5_clkset_group,
928 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
929 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
930 }, {
931 .clk = {
932 .name = "sclk_jpeg",
933 .parent = &exynos5_clk_mout_cpll.clk,
934 },
935 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
936 },
937};
938
939/* Clock initialization code */
940static struct clksrc_clk *exynos5_sysclks[] = {
941 &exynos5_clk_mout_apll,
942 &exynos5_clk_sclk_apll,
943 &exynos5_clk_mout_bpll,
944 &exynos5_clk_mout_bpll_user,
945 &exynos5_clk_mout_cpll,
946 &exynos5_clk_mout_epll,
947 &exynos5_clk_mout_mpll,
948 &exynos5_clk_mout_mpll_user,
949 &exynos5_clk_vpllsrc,
950 &exynos5_clk_sclk_vpll,
951 &exynos5_clk_mout_cpu,
952 &exynos5_clk_dout_armclk,
953 &exynos5_clk_dout_arm2clk,
954 &exynos5_clk_cdrex,
955 &exynos5_clk_aclk_400,
956 &exynos5_clk_aclk_333,
957 &exynos5_clk_aclk_266,
958 &exynos5_clk_aclk_200,
959 &exynos5_clk_aclk_166,
960 &exynos5_clk_aclk_66_pre,
961 &exynos5_clk_aclk_66,
962 &exynos5_clk_dout_mmc0,
963 &exynos5_clk_dout_mmc1,
964 &exynos5_clk_dout_mmc2,
965 &exynos5_clk_dout_mmc3,
966 &exynos5_clk_dout_mmc4,
967 &exynos5_clk_aclk_acp,
968 &exynos5_clk_pclk_acp,
969};
970
971static struct clk *exynos5_clk_cdev[] = {
972 &exynos5_clk_pdma0,
973 &exynos5_clk_pdma1,
974 &exynos5_clk_mdma1,
975};
976
977static struct clksrc_clk *exynos5_clksrc_cdev[] = {
978 &exynos5_clk_sclk_uart0,
979 &exynos5_clk_sclk_uart1,
980 &exynos5_clk_sclk_uart2,
981 &exynos5_clk_sclk_uart3,
982 &exynos5_clk_sclk_mmc0,
983 &exynos5_clk_sclk_mmc1,
984 &exynos5_clk_sclk_mmc2,
985 &exynos5_clk_sclk_mmc3,
986};
987
988static struct clk_lookup exynos5_clk_lookup[] = {
989 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
990 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
991 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
992 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
993 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
997 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
998 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
999 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1000};
1001
1002static unsigned long exynos5_epll_get_rate(struct clk *clk)
1003{
1004 return clk->rate;
1005}
1006
1007static struct clk *exynos5_clks[] __initdata = {
1008 &exynos5_clk_sclk_hdmi27m,
1009 &exynos5_clk_sclk_hdmiphy,
1010 &clk_fout_bpll,
1011 &clk_fout_cpll,
1012 &exynos5_clk_armclk,
1013};
1014
1015static u32 epll_div[][6] = {
1016 { 192000000, 0, 48, 3, 1, 0 },
1017 { 180000000, 0, 45, 3, 1, 0 },
1018 { 73728000, 1, 73, 3, 3, 47710 },
1019 { 67737600, 1, 90, 4, 3, 20762 },
1020 { 49152000, 0, 49, 3, 3, 9961 },
1021 { 45158400, 0, 45, 3, 3, 10381 },
1022 { 180633600, 0, 45, 3, 1, 10381 },
1023};
1024
1025static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1026{
1027 unsigned int epll_con, epll_con_k;
1028 unsigned int i;
1029 unsigned int tmp;
1030 unsigned int epll_rate;
1031 unsigned int locktime;
1032 unsigned int lockcnt;
1033
1034 /* Return if nothing changed */
1035 if (clk->rate == rate)
1036 return 0;
1037
1038 if (clk->parent)
1039 epll_rate = clk_get_rate(clk->parent);
1040 else
1041 epll_rate = clk_ext_xtal_mux.rate;
1042
1043 if (epll_rate != 24000000) {
1044 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1045 return -EINVAL;
1046 }
1047
1048 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1049 epll_con &= ~(0x1 << 27 | \
1050 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1051 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1052 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1053
1054 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1055 if (epll_div[i][0] == rate) {
1056 epll_con_k = epll_div[i][5] << 0;
1057 epll_con |= epll_div[i][1] << 27;
1058 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1059 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1060 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1061 break;
1062 }
1063 }
1064
1065 if (i == ARRAY_SIZE(epll_div)) {
1066 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1067 __func__);
1068 return -EINVAL;
1069 }
1070
1071 epll_rate /= 1000000;
1072
1073 /* 3000 max_cycls : specification data */
1074 locktime = 3000 / epll_rate * epll_div[i][3];
1075 lockcnt = locktime * 10000 / (10000 / epll_rate);
1076
1077 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1078
1079 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1080 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1081
1082 do {
1083 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1084 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1085
1086 clk->rate = rate;
1087
1088 return 0;
1089}
1090
1091static struct clk_ops exynos5_epll_ops = {
1092 .get_rate = exynos5_epll_get_rate,
1093 .set_rate = exynos5_epll_set_rate,
1094};
1095
1096static int xtal_rate;
1097
1098static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1099{
1100 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1101}
1102
1103static struct clk_ops exynos5_fout_apll_ops = {
1104 .get_rate = exynos5_fout_apll_get_rate,
1105};
1106
1107#ifdef CONFIG_PM
1108static int exynos5_clock_suspend(void)
1109{
1110 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1111
1112 return 0;
1113}
1114
1115static void exynos5_clock_resume(void)
1116{
1117 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1118}
1119#else
1120#define exynos5_clock_suspend NULL
1121#define exynos5_clock_resume NULL
1122#endif
1123
1124struct syscore_ops exynos5_clock_syscore_ops = {
1125 .suspend = exynos5_clock_suspend,
1126 .resume = exynos5_clock_resume,
1127};
1128
1129void __init_or_cpufreq exynos5_setup_clocks(void)
1130{
1131 struct clk *xtal_clk;
1132 unsigned long apll;
1133 unsigned long bpll;
1134 unsigned long cpll;
1135 unsigned long mpll;
1136 unsigned long epll;
1137 unsigned long vpll;
1138 unsigned long vpllsrc;
1139 unsigned long xtal;
1140 unsigned long armclk;
1141 unsigned long mout_cdrex;
1142 unsigned long aclk_400;
1143 unsigned long aclk_333;
1144 unsigned long aclk_266;
1145 unsigned long aclk_200;
1146 unsigned long aclk_166;
1147 unsigned long aclk_66;
1148 unsigned int ptr;
1149
1150 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1151
1152 xtal_clk = clk_get(NULL, "xtal");
1153 BUG_ON(IS_ERR(xtal_clk));
1154
1155 xtal = clk_get_rate(xtal_clk);
1156
1157 xtal_rate = xtal;
1158
1159 clk_put(xtal_clk);
1160
1161 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1162
1163 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1164 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1165 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1166 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1167 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1168 __raw_readl(EXYNOS5_EPLL_CON1));
1169
1170 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1171 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1172 __raw_readl(EXYNOS5_VPLL_CON1));
1173
1174 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1175 clk_fout_bpll.rate = bpll;
1176 clk_fout_cpll.rate = cpll;
1177 clk_fout_mpll.rate = mpll;
1178 clk_fout_epll.rate = epll;
1179 clk_fout_vpll.rate = vpll;
1180
1181 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1182 "M=%ld, E=%ld V=%ld",
1183 apll, bpll, cpll, mpll, epll, vpll);
1184
1185 armclk = clk_get_rate(&exynos5_clk_armclk);
1186 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1187
1188 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1189 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1190 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1191 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1192 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1193 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1194
1195 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1196 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1197 "ACLK166=%ld, ACLK66=%ld\n",
1198 armclk, mout_cdrex, aclk_400,
1199 aclk_333, aclk_266, aclk_200,
1200 aclk_166, aclk_66);
1201
1202
1203 clk_fout_epll.ops = &exynos5_epll_ops;
1204
1205 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1206 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1207 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1208
1209 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1210 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1211
1212 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1213 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1214
1215 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1216 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1217}
1218
1219void __init exynos5_register_clocks(void)
1220{
1221 int ptr;
1222
1223 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1224
1225 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1226 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1227
1228 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1229 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1230
1231 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1232 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1233
1234 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1235 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1236
1237 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1238 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1239 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1240
1241 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1242 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1243 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1244
1245 register_syscore_ops(&exynos5_clock_syscore_ops);
1246 s3c_pwmclk_init();
1247}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 187287aa57a..00000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1564 +0,0 @@
1/* linux/arch/arm/mach-exynos4/clock.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/pm.h>
25
26#include <mach/map.h>
27#include <mach/regs-clock.h>
28#include <mach/sysmmu.h>
29#include <mach/exynos4-clock.h>
30
31#include "common.h"
32
33#ifdef CONFIG_PM_SLEEP
34static struct sleep_save exynos4_clock_save[] = {
35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
37 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
39 SAVE_ITEM(S5P_CLKSRC_TOP0),
40 SAVE_ITEM(S5P_CLKSRC_TOP1),
41 SAVE_ITEM(S5P_CLKSRC_CAM),
42 SAVE_ITEM(S5P_CLKSRC_TV),
43 SAVE_ITEM(S5P_CLKSRC_MFC),
44 SAVE_ITEM(S5P_CLKSRC_G3D),
45 SAVE_ITEM(S5P_CLKSRC_LCD0),
46 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
47 SAVE_ITEM(S5P_CLKSRC_FSYS),
48 SAVE_ITEM(S5P_CLKSRC_PERIL0),
49 SAVE_ITEM(S5P_CLKSRC_PERIL1),
50 SAVE_ITEM(S5P_CLKDIV_CAM),
51 SAVE_ITEM(S5P_CLKDIV_TV),
52 SAVE_ITEM(S5P_CLKDIV_MFC),
53 SAVE_ITEM(S5P_CLKDIV_G3D),
54 SAVE_ITEM(S5P_CLKDIV_LCD0),
55 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
56 SAVE_ITEM(S5P_CLKDIV_FSYS0),
57 SAVE_ITEM(S5P_CLKDIV_FSYS1),
58 SAVE_ITEM(S5P_CLKDIV_FSYS2),
59 SAVE_ITEM(S5P_CLKDIV_FSYS3),
60 SAVE_ITEM(S5P_CLKDIV_PERIL0),
61 SAVE_ITEM(S5P_CLKDIV_PERIL1),
62 SAVE_ITEM(S5P_CLKDIV_PERIL2),
63 SAVE_ITEM(S5P_CLKDIV_PERIL3),
64 SAVE_ITEM(S5P_CLKDIV_PERIL4),
65 SAVE_ITEM(S5P_CLKDIV_PERIL5),
66 SAVE_ITEM(S5P_CLKDIV_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
68 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
69 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
70 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
71 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
72 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
74 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
75 SAVE_ITEM(S5P_CLKDIV2_RATIO),
76 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
78 SAVE_ITEM(S5P_CLKGATE_IP_TV),
79 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
80 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
81 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
82 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
83 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
84 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
85 SAVE_ITEM(S5P_CLKGATE_BLOCK),
86 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
87 SAVE_ITEM(S5P_CLKSRC_DMC),
88 SAVE_ITEM(S5P_CLKDIV_DMC0),
89 SAVE_ITEM(S5P_CLKDIV_DMC1),
90 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
91 SAVE_ITEM(S5P_CLKSRC_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU),
93 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96};
97#endif
98
99struct clk clk_sclk_hdmi27m = {
100 .name = "sclk_hdmi27m",
101 .rate = 27000000,
102};
103
104struct clk clk_sclk_hdmiphy = {
105 .name = "sclk_hdmiphy",
106};
107
108struct clk clk_sclk_usbphy0 = {
109 .name = "sclk_usbphy0",
110 .rate = 27000000,
111};
112
113struct clk clk_sclk_usbphy1 = {
114 .name = "sclk_usbphy1",
115};
116
117static struct clk dummy_apb_pclk = {
118 .name = "apb_pclk",
119 .id = -1,
120};
121
122static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
123{
124 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
125}
126
127static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
128{
129 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
130}
131
132static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
133{
134 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
135}
136
137int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
138{
139 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
140}
141
142static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
143{
144 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
145}
146
147static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
148{
149 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
150}
151
152static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
153{
154 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
155}
156
157static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
158{
159 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
160}
161
162static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
163{
164 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
165}
166
167static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
168{
169 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
170}
171
172static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
173{
174 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
175}
176
177static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
178{
179 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
180}
181
182int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
183{
184 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
185}
186
187int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
188{
189 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
190}
191
192static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
193{
194 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
195}
196
197static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
198{
199 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
200}
201
202static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
203{
204 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
205}
206
207static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
208{
209 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
210}
211
212/* Core list of CMU_CPU side */
213
214static struct clksrc_clk clk_mout_apll = {
215 .clk = {
216 .name = "mout_apll",
217 },
218 .sources = &clk_src_apll,
219 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
220};
221
222struct clksrc_clk clk_sclk_apll = {
223 .clk = {
224 .name = "sclk_apll",
225 .parent = &clk_mout_apll.clk,
226 },
227 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
228};
229
230struct clksrc_clk clk_mout_epll = {
231 .clk = {
232 .name = "mout_epll",
233 },
234 .sources = &clk_src_epll,
235 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
236};
237
238struct clksrc_clk clk_mout_mpll = {
239 .clk = {
240 .name = "mout_mpll",
241 },
242 .sources = &clk_src_mpll,
243
244 /* reg_src will be added in each SoCs' clock */
245};
246
247static struct clk *clkset_moutcore_list[] = {
248 [0] = &clk_mout_apll.clk,
249 [1] = &clk_mout_mpll.clk,
250};
251
252static struct clksrc_sources clkset_moutcore = {
253 .sources = clkset_moutcore_list,
254 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
255};
256
257static struct clksrc_clk clk_moutcore = {
258 .clk = {
259 .name = "moutcore",
260 },
261 .sources = &clkset_moutcore,
262 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
263};
264
265static struct clksrc_clk clk_coreclk = {
266 .clk = {
267 .name = "core_clk",
268 .parent = &clk_moutcore.clk,
269 },
270 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
271};
272
273static struct clksrc_clk clk_armclk = {
274 .clk = {
275 .name = "armclk",
276 .parent = &clk_coreclk.clk,
277 },
278};
279
280static struct clksrc_clk clk_aclk_corem0 = {
281 .clk = {
282 .name = "aclk_corem0",
283 .parent = &clk_coreclk.clk,
284 },
285 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
286};
287
288static struct clksrc_clk clk_aclk_cores = {
289 .clk = {
290 .name = "aclk_cores",
291 .parent = &clk_coreclk.clk,
292 },
293 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
294};
295
296static struct clksrc_clk clk_aclk_corem1 = {
297 .clk = {
298 .name = "aclk_corem1",
299 .parent = &clk_coreclk.clk,
300 },
301 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
302};
303
304static struct clksrc_clk clk_periphclk = {
305 .clk = {
306 .name = "periphclk",
307 .parent = &clk_coreclk.clk,
308 },
309 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
310};
311
312/* Core list of CMU_CORE side */
313
314struct clk *clkset_corebus_list[] = {
315 [0] = &clk_mout_mpll.clk,
316 [1] = &clk_sclk_apll.clk,
317};
318
319struct clksrc_sources clkset_mout_corebus = {
320 .sources = clkset_corebus_list,
321 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
322};
323
324static struct clksrc_clk clk_mout_corebus = {
325 .clk = {
326 .name = "mout_corebus",
327 },
328 .sources = &clkset_mout_corebus,
329 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
330};
331
332static struct clksrc_clk clk_sclk_dmc = {
333 .clk = {
334 .name = "sclk_dmc",
335 .parent = &clk_mout_corebus.clk,
336 },
337 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
338};
339
340static struct clksrc_clk clk_aclk_cored = {
341 .clk = {
342 .name = "aclk_cored",
343 .parent = &clk_sclk_dmc.clk,
344 },
345 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
346};
347
348static struct clksrc_clk clk_aclk_corep = {
349 .clk = {
350 .name = "aclk_corep",
351 .parent = &clk_aclk_cored.clk,
352 },
353 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
354};
355
356static struct clksrc_clk clk_aclk_acp = {
357 .clk = {
358 .name = "aclk_acp",
359 .parent = &clk_mout_corebus.clk,
360 },
361 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
362};
363
364static struct clksrc_clk clk_pclk_acp = {
365 .clk = {
366 .name = "pclk_acp",
367 .parent = &clk_aclk_acp.clk,
368 },
369 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
370};
371
372/* Core list of CMU_TOP side */
373
374struct clk *clkset_aclk_top_list[] = {
375 [0] = &clk_mout_mpll.clk,
376 [1] = &clk_sclk_apll.clk,
377};
378
379struct clksrc_sources clkset_aclk = {
380 .sources = clkset_aclk_top_list,
381 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
382};
383
384static struct clksrc_clk clk_aclk_200 = {
385 .clk = {
386 .name = "aclk_200",
387 },
388 .sources = &clkset_aclk,
389 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
390 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
391};
392
393static struct clksrc_clk clk_aclk_100 = {
394 .clk = {
395 .name = "aclk_100",
396 },
397 .sources = &clkset_aclk,
398 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
399 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
400};
401
402static struct clksrc_clk clk_aclk_160 = {
403 .clk = {
404 .name = "aclk_160",
405 },
406 .sources = &clkset_aclk,
407 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
408 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
409};
410
411struct clksrc_clk clk_aclk_133 = {
412 .clk = {
413 .name = "aclk_133",
414 },
415 .sources = &clkset_aclk,
416 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
417 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
418};
419
420static struct clk *clkset_vpllsrc_list[] = {
421 [0] = &clk_fin_vpll,
422 [1] = &clk_sclk_hdmi27m,
423};
424
425static struct clksrc_sources clkset_vpllsrc = {
426 .sources = clkset_vpllsrc_list,
427 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
428};
429
430static struct clksrc_clk clk_vpllsrc = {
431 .clk = {
432 .name = "vpll_src",
433 .enable = exynos4_clksrc_mask_top_ctrl,
434 .ctrlbit = (1 << 0),
435 },
436 .sources = &clkset_vpllsrc,
437 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
438};
439
440static struct clk *clkset_sclk_vpll_list[] = {
441 [0] = &clk_vpllsrc.clk,
442 [1] = &clk_fout_vpll,
443};
444
445static struct clksrc_sources clkset_sclk_vpll = {
446 .sources = clkset_sclk_vpll_list,
447 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
448};
449
450struct clksrc_clk clk_sclk_vpll = {
451 .clk = {
452 .name = "sclk_vpll",
453 },
454 .sources = &clkset_sclk_vpll,
455 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
456};
457
458static struct clk init_clocks_off[] = {
459 {
460 .name = "timers",
461 .parent = &clk_aclk_100.clk,
462 .enable = exynos4_clk_ip_peril_ctrl,
463 .ctrlbit = (1<<24),
464 }, {
465 .name = "csis",
466 .devname = "s5p-mipi-csis.0",
467 .enable = exynos4_clk_ip_cam_ctrl,
468 .ctrlbit = (1 << 4),
469 }, {
470 .name = "csis",
471 .devname = "s5p-mipi-csis.1",
472 .enable = exynos4_clk_ip_cam_ctrl,
473 .ctrlbit = (1 << 5),
474 }, {
475 .name = "fimc",
476 .devname = "exynos4-fimc.0",
477 .enable = exynos4_clk_ip_cam_ctrl,
478 .ctrlbit = (1 << 0),
479 }, {
480 .name = "fimc",
481 .devname = "exynos4-fimc.1",
482 .enable = exynos4_clk_ip_cam_ctrl,
483 .ctrlbit = (1 << 1),
484 }, {
485 .name = "fimc",
486 .devname = "exynos4-fimc.2",
487 .enable = exynos4_clk_ip_cam_ctrl,
488 .ctrlbit = (1 << 2),
489 }, {
490 .name = "fimc",
491 .devname = "exynos4-fimc.3",
492 .enable = exynos4_clk_ip_cam_ctrl,
493 .ctrlbit = (1 << 3),
494 }, {
495 .name = "fimd",
496 .devname = "exynos4-fb.0",
497 .enable = exynos4_clk_ip_lcd0_ctrl,
498 .ctrlbit = (1 << 0),
499 }, {
500 .name = "hsmmc",
501 .devname = "s3c-sdhci.0",
502 .parent = &clk_aclk_133.clk,
503 .enable = exynos4_clk_ip_fsys_ctrl,
504 .ctrlbit = (1 << 5),
505 }, {
506 .name = "hsmmc",
507 .devname = "s3c-sdhci.1",
508 .parent = &clk_aclk_133.clk,
509 .enable = exynos4_clk_ip_fsys_ctrl,
510 .ctrlbit = (1 << 6),
511 }, {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.2",
514 .parent = &clk_aclk_133.clk,
515 .enable = exynos4_clk_ip_fsys_ctrl,
516 .ctrlbit = (1 << 7),
517 }, {
518 .name = "hsmmc",
519 .devname = "s3c-sdhci.3",
520 .parent = &clk_aclk_133.clk,
521 .enable = exynos4_clk_ip_fsys_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "dwmmc",
525 .parent = &clk_aclk_133.clk,
526 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 9),
528 }, {
529 .name = "dac",
530 .devname = "s5p-sdo",
531 .enable = exynos4_clk_ip_tv_ctrl,
532 .ctrlbit = (1 << 2),
533 }, {
534 .name = "mixer",
535 .devname = "s5p-mixer",
536 .enable = exynos4_clk_ip_tv_ctrl,
537 .ctrlbit = (1 << 1),
538 }, {
539 .name = "vp",
540 .devname = "s5p-mixer",
541 .enable = exynos4_clk_ip_tv_ctrl,
542 .ctrlbit = (1 << 0),
543 }, {
544 .name = "hdmi",
545 .devname = "exynos4-hdmi",
546 .enable = exynos4_clk_ip_tv_ctrl,
547 .ctrlbit = (1 << 3),
548 }, {
549 .name = "hdmiphy",
550 .devname = "exynos4-hdmi",
551 .enable = exynos4_clk_hdmiphy_ctrl,
552 .ctrlbit = (1 << 0),
553 }, {
554 .name = "dacphy",
555 .devname = "s5p-sdo",
556 .enable = exynos4_clk_dac_ctrl,
557 .ctrlbit = (1 << 0),
558 }, {
559 .name = "adc",
560 .enable = exynos4_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 15),
562 }, {
563 .name = "keypad",
564 .enable = exynos4_clk_ip_perir_ctrl,
565 .ctrlbit = (1 << 16),
566 }, {
567 .name = "rtc",
568 .enable = exynos4_clk_ip_perir_ctrl,
569 .ctrlbit = (1 << 15),
570 }, {
571 .name = "watchdog",
572 .parent = &clk_aclk_100.clk,
573 .enable = exynos4_clk_ip_perir_ctrl,
574 .ctrlbit = (1 << 14),
575 }, {
576 .name = "usbhost",
577 .enable = exynos4_clk_ip_fsys_ctrl ,
578 .ctrlbit = (1 << 12),
579 }, {
580 .name = "otg",
581 .enable = exynos4_clk_ip_fsys_ctrl,
582 .ctrlbit = (1 << 13),
583 }, {
584 .name = "spi",
585 .devname = "s3c64xx-spi.0",
586 .enable = exynos4_clk_ip_peril_ctrl,
587 .ctrlbit = (1 << 16),
588 }, {
589 .name = "spi",
590 .devname = "s3c64xx-spi.1",
591 .enable = exynos4_clk_ip_peril_ctrl,
592 .ctrlbit = (1 << 17),
593 }, {
594 .name = "spi",
595 .devname = "s3c64xx-spi.2",
596 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 18),
598 }, {
599 .name = "iis",
600 .devname = "samsung-i2s.0",
601 .enable = exynos4_clk_ip_peril_ctrl,
602 .ctrlbit = (1 << 19),
603 }, {
604 .name = "iis",
605 .devname = "samsung-i2s.1",
606 .enable = exynos4_clk_ip_peril_ctrl,
607 .ctrlbit = (1 << 20),
608 }, {
609 .name = "iis",
610 .devname = "samsung-i2s.2",
611 .enable = exynos4_clk_ip_peril_ctrl,
612 .ctrlbit = (1 << 21),
613 }, {
614 .name = "ac97",
615 .devname = "samsung-ac97",
616 .enable = exynos4_clk_ip_peril_ctrl,
617 .ctrlbit = (1 << 27),
618 }, {
619 .name = "fimg2d",
620 .enable = exynos4_clk_ip_image_ctrl,
621 .ctrlbit = (1 << 0),
622 }, {
623 .name = "mfc",
624 .devname = "s5p-mfc",
625 .enable = exynos4_clk_ip_mfc_ctrl,
626 .ctrlbit = (1 << 0),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-i2c.0",
630 .parent = &clk_aclk_100.clk,
631 .enable = exynos4_clk_ip_peril_ctrl,
632 .ctrlbit = (1 << 6),
633 }, {
634 .name = "i2c",
635 .devname = "s3c2440-i2c.1",
636 .parent = &clk_aclk_100.clk,
637 .enable = exynos4_clk_ip_peril_ctrl,
638 .ctrlbit = (1 << 7),
639 }, {
640 .name = "i2c",
641 .devname = "s3c2440-i2c.2",
642 .parent = &clk_aclk_100.clk,
643 .enable = exynos4_clk_ip_peril_ctrl,
644 .ctrlbit = (1 << 8),
645 }, {
646 .name = "i2c",
647 .devname = "s3c2440-i2c.3",
648 .parent = &clk_aclk_100.clk,
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 9),
651 }, {
652 .name = "i2c",
653 .devname = "s3c2440-i2c.4",
654 .parent = &clk_aclk_100.clk,
655 .enable = exynos4_clk_ip_peril_ctrl,
656 .ctrlbit = (1 << 10),
657 }, {
658 .name = "i2c",
659 .devname = "s3c2440-i2c.5",
660 .parent = &clk_aclk_100.clk,
661 .enable = exynos4_clk_ip_peril_ctrl,
662 .ctrlbit = (1 << 11),
663 }, {
664 .name = "i2c",
665 .devname = "s3c2440-i2c.6",
666 .parent = &clk_aclk_100.clk,
667 .enable = exynos4_clk_ip_peril_ctrl,
668 .ctrlbit = (1 << 12),
669 }, {
670 .name = "i2c",
671 .devname = "s3c2440-i2c.7",
672 .parent = &clk_aclk_100.clk,
673 .enable = exynos4_clk_ip_peril_ctrl,
674 .ctrlbit = (1 << 13),
675 }, {
676 .name = "i2c",
677 .devname = "s3c2440-hdmiphy-i2c",
678 .parent = &clk_aclk_100.clk,
679 .enable = exynos4_clk_ip_peril_ctrl,
680 .ctrlbit = (1 << 14),
681 }, {
682 .name = "SYSMMU_MDMA",
683 .enable = exynos4_clk_ip_image_ctrl,
684 .ctrlbit = (1 << 5),
685 }, {
686 .name = "SYSMMU_FIMC0",
687 .enable = exynos4_clk_ip_cam_ctrl,
688 .ctrlbit = (1 << 7),
689 }, {
690 .name = "SYSMMU_FIMC1",
691 .enable = exynos4_clk_ip_cam_ctrl,
692 .ctrlbit = (1 << 8),
693 }, {
694 .name = "SYSMMU_FIMC2",
695 .enable = exynos4_clk_ip_cam_ctrl,
696 .ctrlbit = (1 << 9),
697 }, {
698 .name = "SYSMMU_FIMC3",
699 .enable = exynos4_clk_ip_cam_ctrl,
700 .ctrlbit = (1 << 10),
701 }, {
702 .name = "SYSMMU_JPEG",
703 .enable = exynos4_clk_ip_cam_ctrl,
704 .ctrlbit = (1 << 11),
705 }, {
706 .name = "SYSMMU_FIMD0",
707 .enable = exynos4_clk_ip_lcd0_ctrl,
708 .ctrlbit = (1 << 4),
709 }, {
710 .name = "SYSMMU_FIMD1",
711 .enable = exynos4_clk_ip_lcd1_ctrl,
712 .ctrlbit = (1 << 4),
713 }, {
714 .name = "SYSMMU_PCIe",
715 .enable = exynos4_clk_ip_fsys_ctrl,
716 .ctrlbit = (1 << 18),
717 }, {
718 .name = "SYSMMU_G2D",
719 .enable = exynos4_clk_ip_image_ctrl,
720 .ctrlbit = (1 << 3),
721 }, {
722 .name = "SYSMMU_ROTATOR",
723 .enable = exynos4_clk_ip_image_ctrl,
724 .ctrlbit = (1 << 4),
725 }, {
726 .name = "SYSMMU_TV",
727 .enable = exynos4_clk_ip_tv_ctrl,
728 .ctrlbit = (1 << 4),
729 }, {
730 .name = "SYSMMU_MFC_L",
731 .enable = exynos4_clk_ip_mfc_ctrl,
732 .ctrlbit = (1 << 1),
733 }, {
734 .name = "SYSMMU_MFC_R",
735 .enable = exynos4_clk_ip_mfc_ctrl,
736 .ctrlbit = (1 << 2),
737 }
738};
739
740static struct clk init_clocks[] = {
741 {
742 .name = "uart",
743 .devname = "s5pv210-uart.0",
744 .enable = exynos4_clk_ip_peril_ctrl,
745 .ctrlbit = (1 << 0),
746 }, {
747 .name = "uart",
748 .devname = "s5pv210-uart.1",
749 .enable = exynos4_clk_ip_peril_ctrl,
750 .ctrlbit = (1 << 1),
751 }, {
752 .name = "uart",
753 .devname = "s5pv210-uart.2",
754 .enable = exynos4_clk_ip_peril_ctrl,
755 .ctrlbit = (1 << 2),
756 }, {
757 .name = "uart",
758 .devname = "s5pv210-uart.3",
759 .enable = exynos4_clk_ip_peril_ctrl,
760 .ctrlbit = (1 << 3),
761 }, {
762 .name = "uart",
763 .devname = "s5pv210-uart.4",
764 .enable = exynos4_clk_ip_peril_ctrl,
765 .ctrlbit = (1 << 4),
766 }, {
767 .name = "uart",
768 .devname = "s5pv210-uart.5",
769 .enable = exynos4_clk_ip_peril_ctrl,
770 .ctrlbit = (1 << 5),
771 }
772};
773
774static struct clk clk_pdma0 = {
775 .name = "dma",
776 .devname = "dma-pl330.0",
777 .enable = exynos4_clk_ip_fsys_ctrl,
778 .ctrlbit = (1 << 0),
779};
780
781static struct clk clk_pdma1 = {
782 .name = "dma",
783 .devname = "dma-pl330.1",
784 .enable = exynos4_clk_ip_fsys_ctrl,
785 .ctrlbit = (1 << 1),
786};
787
788struct clk *clkset_group_list[] = {
789 [0] = &clk_ext_xtal_mux,
790 [1] = &clk_xusbxti,
791 [2] = &clk_sclk_hdmi27m,
792 [3] = &clk_sclk_usbphy0,
793 [4] = &clk_sclk_usbphy1,
794 [5] = &clk_sclk_hdmiphy,
795 [6] = &clk_mout_mpll.clk,
796 [7] = &clk_mout_epll.clk,
797 [8] = &clk_sclk_vpll.clk,
798};
799
800struct clksrc_sources clkset_group = {
801 .sources = clkset_group_list,
802 .nr_sources = ARRAY_SIZE(clkset_group_list),
803};
804
805static struct clk *clkset_mout_g2d0_list[] = {
806 [0] = &clk_mout_mpll.clk,
807 [1] = &clk_sclk_apll.clk,
808};
809
810static struct clksrc_sources clkset_mout_g2d0 = {
811 .sources = clkset_mout_g2d0_list,
812 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
813};
814
815static struct clksrc_clk clk_mout_g2d0 = {
816 .clk = {
817 .name = "mout_g2d0",
818 },
819 .sources = &clkset_mout_g2d0,
820 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
821};
822
823static struct clk *clkset_mout_g2d1_list[] = {
824 [0] = &clk_mout_epll.clk,
825 [1] = &clk_sclk_vpll.clk,
826};
827
828static struct clksrc_sources clkset_mout_g2d1 = {
829 .sources = clkset_mout_g2d1_list,
830 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
831};
832
833static struct clksrc_clk clk_mout_g2d1 = {
834 .clk = {
835 .name = "mout_g2d1",
836 },
837 .sources = &clkset_mout_g2d1,
838 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
839};
840
841static struct clk *clkset_mout_g2d_list[] = {
842 [0] = &clk_mout_g2d0.clk,
843 [1] = &clk_mout_g2d1.clk,
844};
845
846static struct clksrc_sources clkset_mout_g2d = {
847 .sources = clkset_mout_g2d_list,
848 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
849};
850
851static struct clk *clkset_mout_mfc0_list[] = {
852 [0] = &clk_mout_mpll.clk,
853 [1] = &clk_sclk_apll.clk,
854};
855
856static struct clksrc_sources clkset_mout_mfc0 = {
857 .sources = clkset_mout_mfc0_list,
858 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
859};
860
861static struct clksrc_clk clk_mout_mfc0 = {
862 .clk = {
863 .name = "mout_mfc0",
864 },
865 .sources = &clkset_mout_mfc0,
866 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
867};
868
869static struct clk *clkset_mout_mfc1_list[] = {
870 [0] = &clk_mout_epll.clk,
871 [1] = &clk_sclk_vpll.clk,
872};
873
874static struct clksrc_sources clkset_mout_mfc1 = {
875 .sources = clkset_mout_mfc1_list,
876 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
877};
878
879static struct clksrc_clk clk_mout_mfc1 = {
880 .clk = {
881 .name = "mout_mfc1",
882 },
883 .sources = &clkset_mout_mfc1,
884 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
885};
886
887static struct clk *clkset_mout_mfc_list[] = {
888 [0] = &clk_mout_mfc0.clk,
889 [1] = &clk_mout_mfc1.clk,
890};
891
892static struct clksrc_sources clkset_mout_mfc = {
893 .sources = clkset_mout_mfc_list,
894 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
895};
896
897static struct clk *clkset_sclk_dac_list[] = {
898 [0] = &clk_sclk_vpll.clk,
899 [1] = &clk_sclk_hdmiphy,
900};
901
902static struct clksrc_sources clkset_sclk_dac = {
903 .sources = clkset_sclk_dac_list,
904 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
905};
906
907static struct clksrc_clk clk_sclk_dac = {
908 .clk = {
909 .name = "sclk_dac",
910 .enable = exynos4_clksrc_mask_tv_ctrl,
911 .ctrlbit = (1 << 8),
912 },
913 .sources = &clkset_sclk_dac,
914 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
915};
916
917static struct clksrc_clk clk_sclk_pixel = {
918 .clk = {
919 .name = "sclk_pixel",
920 .parent = &clk_sclk_vpll.clk,
921 },
922 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
923};
924
925static struct clk *clkset_sclk_hdmi_list[] = {
926 [0] = &clk_sclk_pixel.clk,
927 [1] = &clk_sclk_hdmiphy,
928};
929
930static struct clksrc_sources clkset_sclk_hdmi = {
931 .sources = clkset_sclk_hdmi_list,
932 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
933};
934
935static struct clksrc_clk clk_sclk_hdmi = {
936 .clk = {
937 .name = "sclk_hdmi",
938 .enable = exynos4_clksrc_mask_tv_ctrl,
939 .ctrlbit = (1 << 0),
940 },
941 .sources = &clkset_sclk_hdmi,
942 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
943};
944
945static struct clk *clkset_sclk_mixer_list[] = {
946 [0] = &clk_sclk_dac.clk,
947 [1] = &clk_sclk_hdmi.clk,
948};
949
950static struct clksrc_sources clkset_sclk_mixer = {
951 .sources = clkset_sclk_mixer_list,
952 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
953};
954
955static struct clksrc_clk clk_sclk_mixer = {
956 .clk = {
957 .name = "sclk_mixer",
958 .enable = exynos4_clksrc_mask_tv_ctrl,
959 .ctrlbit = (1 << 4),
960 },
961 .sources = &clkset_sclk_mixer,
962 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
963};
964
965static struct clksrc_clk *sclk_tv[] = {
966 &clk_sclk_dac,
967 &clk_sclk_pixel,
968 &clk_sclk_hdmi,
969 &clk_sclk_mixer,
970};
971
972static struct clksrc_clk clk_dout_mmc0 = {
973 .clk = {
974 .name = "dout_mmc0",
975 },
976 .sources = &clkset_group,
977 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
979};
980
981static struct clksrc_clk clk_dout_mmc1 = {
982 .clk = {
983 .name = "dout_mmc1",
984 },
985 .sources = &clkset_group,
986 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
988};
989
990static struct clksrc_clk clk_dout_mmc2 = {
991 .clk = {
992 .name = "dout_mmc2",
993 },
994 .sources = &clkset_group,
995 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
996 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
997};
998
999static struct clksrc_clk clk_dout_mmc3 = {
1000 .clk = {
1001 .name = "dout_mmc3",
1002 },
1003 .sources = &clkset_group,
1004 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1005 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1006};
1007
1008static struct clksrc_clk clk_dout_mmc4 = {
1009 .clk = {
1010 .name = "dout_mmc4",
1011 },
1012 .sources = &clkset_group,
1013 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1014 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1015};
1016
1017static struct clksrc_clk clksrcs[] = {
1018 {
1019 .clk = {
1020 .name = "sclk_pwm",
1021 .enable = exynos4_clksrc_mask_peril0_ctrl,
1022 .ctrlbit = (1 << 24),
1023 },
1024 .sources = &clkset_group,
1025 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1026 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1027 }, {
1028 .clk = {
1029 .name = "sclk_csis",
1030 .devname = "s5p-mipi-csis.0",
1031 .enable = exynos4_clksrc_mask_cam_ctrl,
1032 .ctrlbit = (1 << 24),
1033 },
1034 .sources = &clkset_group,
1035 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1036 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_csis",
1040 .devname = "s5p-mipi-csis.1",
1041 .enable = exynos4_clksrc_mask_cam_ctrl,
1042 .ctrlbit = (1 << 28),
1043 },
1044 .sources = &clkset_group,
1045 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1046 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1047 }, {
1048 .clk = {
1049 .name = "sclk_cam0",
1050 .enable = exynos4_clksrc_mask_cam_ctrl,
1051 .ctrlbit = (1 << 16),
1052 },
1053 .sources = &clkset_group,
1054 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1055 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1056 }, {
1057 .clk = {
1058 .name = "sclk_cam1",
1059 .enable = exynos4_clksrc_mask_cam_ctrl,
1060 .ctrlbit = (1 << 20),
1061 },
1062 .sources = &clkset_group,
1063 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1064 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1065 }, {
1066 .clk = {
1067 .name = "sclk_fimc",
1068 .devname = "exynos4-fimc.0",
1069 .enable = exynos4_clksrc_mask_cam_ctrl,
1070 .ctrlbit = (1 << 0),
1071 },
1072 .sources = &clkset_group,
1073 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1074 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1075 }, {
1076 .clk = {
1077 .name = "sclk_fimc",
1078 .devname = "exynos4-fimc.1",
1079 .enable = exynos4_clksrc_mask_cam_ctrl,
1080 .ctrlbit = (1 << 4),
1081 },
1082 .sources = &clkset_group,
1083 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1084 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1085 }, {
1086 .clk = {
1087 .name = "sclk_fimc",
1088 .devname = "exynos4-fimc.2",
1089 .enable = exynos4_clksrc_mask_cam_ctrl,
1090 .ctrlbit = (1 << 8),
1091 },
1092 .sources = &clkset_group,
1093 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1094 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1095 }, {
1096 .clk = {
1097 .name = "sclk_fimc",
1098 .devname = "exynos4-fimc.3",
1099 .enable = exynos4_clksrc_mask_cam_ctrl,
1100 .ctrlbit = (1 << 12),
1101 },
1102 .sources = &clkset_group,
1103 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1104 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1105 }, {
1106 .clk = {
1107 .name = "sclk_fimd",
1108 .devname = "exynos4-fb.0",
1109 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1110 .ctrlbit = (1 << 0),
1111 },
1112 .sources = &clkset_group,
1113 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1114 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1115 }, {
1116 .clk = {
1117 .name = "sclk_fimg2d",
1118 },
1119 .sources = &clkset_mout_g2d,
1120 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1121 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1122 }, {
1123 .clk = {
1124 .name = "sclk_mfc",
1125 .devname = "s5p-mfc",
1126 },
1127 .sources = &clkset_mout_mfc,
1128 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1129 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1130 }, {
1131 .clk = {
1132 .name = "sclk_dwmmc",
1133 .parent = &clk_dout_mmc4.clk,
1134 .enable = exynos4_clksrc_mask_fsys_ctrl,
1135 .ctrlbit = (1 << 16),
1136 },
1137 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1138 }
1139};
1140
1141static struct clksrc_clk clk_sclk_uart0 = {
1142 .clk = {
1143 .name = "uclk1",
1144 .devname = "exynos4210-uart.0",
1145 .enable = exynos4_clksrc_mask_peril0_ctrl,
1146 .ctrlbit = (1 << 0),
1147 },
1148 .sources = &clkset_group,
1149 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1150 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1151};
1152
1153static struct clksrc_clk clk_sclk_uart1 = {
1154 .clk = {
1155 .name = "uclk1",
1156 .devname = "exynos4210-uart.1",
1157 .enable = exynos4_clksrc_mask_peril0_ctrl,
1158 .ctrlbit = (1 << 4),
1159 },
1160 .sources = &clkset_group,
1161 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1162 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1163};
1164
1165static struct clksrc_clk clk_sclk_uart2 = {
1166 .clk = {
1167 .name = "uclk1",
1168 .devname = "exynos4210-uart.2",
1169 .enable = exynos4_clksrc_mask_peril0_ctrl,
1170 .ctrlbit = (1 << 8),
1171 },
1172 .sources = &clkset_group,
1173 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1174 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1175};
1176
1177static struct clksrc_clk clk_sclk_uart3 = {
1178 .clk = {
1179 .name = "uclk1",
1180 .devname = "exynos4210-uart.3",
1181 .enable = exynos4_clksrc_mask_peril0_ctrl,
1182 .ctrlbit = (1 << 12),
1183 },
1184 .sources = &clkset_group,
1185 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1186 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1187};
1188
1189static struct clksrc_clk clk_sclk_mmc0 = {
1190 .clk = {
1191 .name = "sclk_mmc",
1192 .devname = "s3c-sdhci.0",
1193 .parent = &clk_dout_mmc0.clk,
1194 .enable = exynos4_clksrc_mask_fsys_ctrl,
1195 .ctrlbit = (1 << 0),
1196 },
1197 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1198};
1199
1200static struct clksrc_clk clk_sclk_mmc1 = {
1201 .clk = {
1202 .name = "sclk_mmc",
1203 .devname = "s3c-sdhci.1",
1204 .parent = &clk_dout_mmc1.clk,
1205 .enable = exynos4_clksrc_mask_fsys_ctrl,
1206 .ctrlbit = (1 << 4),
1207 },
1208 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1209};
1210
1211static struct clksrc_clk clk_sclk_mmc2 = {
1212 .clk = {
1213 .name = "sclk_mmc",
1214 .devname = "s3c-sdhci.2",
1215 .parent = &clk_dout_mmc2.clk,
1216 .enable = exynos4_clksrc_mask_fsys_ctrl,
1217 .ctrlbit = (1 << 8),
1218 },
1219 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1220};
1221
1222static struct clksrc_clk clk_sclk_mmc3 = {
1223 .clk = {
1224 .name = "sclk_mmc",
1225 .devname = "s3c-sdhci.3",
1226 .parent = &clk_dout_mmc3.clk,
1227 .enable = exynos4_clksrc_mask_fsys_ctrl,
1228 .ctrlbit = (1 << 12),
1229 },
1230 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1231};
1232
1233static struct clksrc_clk clk_sclk_spi0 = {
1234 .clk = {
1235 .name = "sclk_spi",
1236 .devname = "s3c64xx-spi.0",
1237 .enable = exynos4_clksrc_mask_peril1_ctrl,
1238 .ctrlbit = (1 << 16),
1239 },
1240 .sources = &clkset_group,
1241 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1242 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1243};
1244
1245static struct clksrc_clk clk_sclk_spi1 = {
1246 .clk = {
1247 .name = "sclk_spi",
1248 .devname = "s3c64xx-spi.1",
1249 .enable = exynos4_clksrc_mask_peril1_ctrl,
1250 .ctrlbit = (1 << 20),
1251 },
1252 .sources = &clkset_group,
1253 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255};
1256
1257static struct clksrc_clk clk_sclk_spi2 = {
1258 .clk = {
1259 .name = "sclk_spi",
1260 .devname = "s3c64xx-spi.2",
1261 .enable = exynos4_clksrc_mask_peril1_ctrl,
1262 .ctrlbit = (1 << 24),
1263 },
1264 .sources = &clkset_group,
1265 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1266 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1267};
1268
1269/* Clock initialization code */
1270static struct clksrc_clk *sysclks[] = {
1271 &clk_mout_apll,
1272 &clk_sclk_apll,
1273 &clk_mout_epll,
1274 &clk_mout_mpll,
1275 &clk_moutcore,
1276 &clk_coreclk,
1277 &clk_armclk,
1278 &clk_aclk_corem0,
1279 &clk_aclk_cores,
1280 &clk_aclk_corem1,
1281 &clk_periphclk,
1282 &clk_mout_corebus,
1283 &clk_sclk_dmc,
1284 &clk_aclk_cored,
1285 &clk_aclk_corep,
1286 &clk_aclk_acp,
1287 &clk_pclk_acp,
1288 &clk_vpllsrc,
1289 &clk_sclk_vpll,
1290 &clk_aclk_200,
1291 &clk_aclk_100,
1292 &clk_aclk_160,
1293 &clk_aclk_133,
1294 &clk_dout_mmc0,
1295 &clk_dout_mmc1,
1296 &clk_dout_mmc2,
1297 &clk_dout_mmc3,
1298 &clk_dout_mmc4,
1299 &clk_mout_mfc0,
1300 &clk_mout_mfc1,
1301};
1302
1303static struct clk *clk_cdev[] = {
1304 &clk_pdma0,
1305 &clk_pdma1,
1306};
1307
1308static struct clksrc_clk *clksrc_cdev[] = {
1309 &clk_sclk_uart0,
1310 &clk_sclk_uart1,
1311 &clk_sclk_uart2,
1312 &clk_sclk_uart3,
1313 &clk_sclk_mmc0,
1314 &clk_sclk_mmc1,
1315 &clk_sclk_mmc2,
1316 &clk_sclk_mmc3,
1317 &clk_sclk_spi0,
1318 &clk_sclk_spi1,
1319 &clk_sclk_spi2,
1320
1321};
1322
1323static struct clk_lookup exynos4_clk_lookup[] = {
1324 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1325 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1326 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1327 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1328 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1329 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1330 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1331 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1332 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1333 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1334 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1335 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1336 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1337};
1338
1339static int xtal_rate;
1340
1341static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1342{
1343 if (soc_is_exynos4210())
1344 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1345 pll_4508);
1346 else if (soc_is_exynos4212() || soc_is_exynos4412())
1347 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1348 else
1349 return 0;
1350}
1351
1352static struct clk_ops exynos4_fout_apll_ops = {
1353 .get_rate = exynos4_fout_apll_get_rate,
1354};
1355
1356static u32 vpll_div[][8] = {
1357 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1358 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1359};
1360
1361static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1362{
1363 return clk->rate;
1364}
1365
1366static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1367{
1368 unsigned int vpll_con0, vpll_con1 = 0;
1369 unsigned int i;
1370
1371 /* Return if nothing changed */
1372 if (clk->rate == rate)
1373 return 0;
1374
1375 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1376 vpll_con0 &= ~(0x1 << 27 | \
1377 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1378 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1379 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1380
1381 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1382 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1383 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1384 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1385
1386 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1387 if (vpll_div[i][0] == rate) {
1388 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1389 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1390 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1391 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1392 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1393 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1394 vpll_con0 |= vpll_div[i][7] << 27;
1395 break;
1396 }
1397 }
1398
1399 if (i == ARRAY_SIZE(vpll_div)) {
1400 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1401 __func__);
1402 return -EINVAL;
1403 }
1404
1405 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1406 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1407
1408 /* Wait for VPLL lock */
1409 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1410 continue;
1411
1412 clk->rate = rate;
1413 return 0;
1414}
1415
1416static struct clk_ops exynos4_vpll_ops = {
1417 .get_rate = exynos4_vpll_get_rate,
1418 .set_rate = exynos4_vpll_set_rate,
1419};
1420
1421void __init_or_cpufreq exynos4_setup_clocks(void)
1422{
1423 struct clk *xtal_clk;
1424 unsigned long apll = 0;
1425 unsigned long mpll = 0;
1426 unsigned long epll = 0;
1427 unsigned long vpll = 0;
1428 unsigned long vpllsrc;
1429 unsigned long xtal;
1430 unsigned long armclk;
1431 unsigned long sclk_dmc;
1432 unsigned long aclk_200;
1433 unsigned long aclk_100;
1434 unsigned long aclk_160;
1435 unsigned long aclk_133;
1436 unsigned int ptr;
1437
1438 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1439
1440 xtal_clk = clk_get(NULL, "xtal");
1441 BUG_ON(IS_ERR(xtal_clk));
1442
1443 xtal = clk_get_rate(xtal_clk);
1444
1445 xtal_rate = xtal;
1446
1447 clk_put(xtal_clk);
1448
1449 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1450
1451 if (soc_is_exynos4210()) {
1452 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1453 pll_4508);
1454 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1455 pll_4508);
1456 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1457 __raw_readl(S5P_EPLL_CON1), pll_4600);
1458
1459 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1460 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1461 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1462 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1463 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1464 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1465 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1466 __raw_readl(S5P_EPLL_CON1));
1467
1468 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1469 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1470 __raw_readl(S5P_VPLL_CON1));
1471 } else {
1472 /* nothing */
1473 }
1474
1475 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1476 clk_fout_mpll.rate = mpll;
1477 clk_fout_epll.rate = epll;
1478 clk_fout_vpll.ops = &exynos4_vpll_ops;
1479 clk_fout_vpll.rate = vpll;
1480
1481 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1482 apll, mpll, epll, vpll);
1483
1484 armclk = clk_get_rate(&clk_armclk.clk);
1485 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1486
1487 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1488 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1489 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1490 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1491
1492 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1493 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1494 armclk, sclk_dmc, aclk_200,
1495 aclk_100, aclk_160, aclk_133);
1496
1497 clk_f.rate = armclk;
1498 clk_h.rate = sclk_dmc;
1499 clk_p.rate = aclk_100;
1500
1501 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1502 s3c_set_clksrc(&clksrcs[ptr], true);
1503}
1504
1505static struct clk *clks[] __initdata = {
1506 &clk_sclk_hdmi27m,
1507 &clk_sclk_hdmiphy,
1508 &clk_sclk_usbphy0,
1509 &clk_sclk_usbphy1,
1510};
1511
1512#ifdef CONFIG_PM_SLEEP
1513static int exynos4_clock_suspend(void)
1514{
1515 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1516 return 0;
1517}
1518
1519static void exynos4_clock_resume(void)
1520{
1521 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1522}
1523
1524#else
1525#define exynos4_clock_suspend NULL
1526#define exynos4_clock_resume NULL
1527#endif
1528
1529struct syscore_ops exynos4_clock_syscore_ops = {
1530 .suspend = exynos4_clock_suspend,
1531 .resume = exynos4_clock_resume,
1532};
1533
1534void __init exynos4_register_clocks(void)
1535{
1536 int ptr;
1537
1538 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1539
1540 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1541 s3c_register_clksrc(sysclks[ptr], 1);
1542
1543 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1544 s3c_register_clksrc(sclk_tv[ptr], 1);
1545
1546 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1547 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1548
1549 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1550 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1551
1552 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1553 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1554 s3c_disable_clocks(clk_cdev[ptr], 1);
1555
1556 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1557 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1558 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1559
1560 register_syscore_ops(&exynos4_clock_syscore_ops);
1561 s3c24xx_register_clock(&dummy_apb_pclk);
1562
1563 s3c_pwmclk_init();
1564}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 031c1e5b3df..cbbaca54966 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -49,6 +49,14 @@
49static const char name_exynos4210[] = "EXYNOS4210"; 49static const char name_exynos4210[] = "EXYNOS4210";
50static const char name_exynos4212[] = "EXYNOS4212"; 50static const char name_exynos4212[] = "EXYNOS4212";
51static const char name_exynos4412[] = "EXYNOS4412"; 51static const char name_exynos4412[] = "EXYNOS4412";
52static const char name_exynos5250[] = "EXYNOS5250";
53
54static void exynos4_map_io(void);
55static void exynos5_map_io(void);
56static void exynos4_init_clocks(int xtal);
57static void exynos5_init_clocks(int xtal);
58static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59static int exynos_init(void);
52 60
53static struct cpu_table cpu_ids[] __initdata = { 61static struct cpu_table cpu_ids[] __initdata = {
54 { 62 {
@@ -56,7 +64,7 @@ static struct cpu_table cpu_ids[] __initdata = {
56 .idmask = EXYNOS4_CPU_MASK, 64 .idmask = EXYNOS4_CPU_MASK,
57 .map_io = exynos4_map_io, 65 .map_io = exynos4_map_io,
58 .init_clocks = exynos4_init_clocks, 66 .init_clocks = exynos4_init_clocks,
59 .init_uarts = exynos4_init_uarts, 67 .init_uarts = exynos_init_uarts,
60 .init = exynos_init, 68 .init = exynos_init,
61 .name = name_exynos4210, 69 .name = name_exynos4210,
62 }, { 70 }, {
@@ -64,7 +72,7 @@ static struct cpu_table cpu_ids[] __initdata = {
64 .idmask = EXYNOS4_CPU_MASK, 72 .idmask = EXYNOS4_CPU_MASK,
65 .map_io = exynos4_map_io, 73 .map_io = exynos4_map_io,
66 .init_clocks = exynos4_init_clocks, 74 .init_clocks = exynos4_init_clocks,
67 .init_uarts = exynos4_init_uarts, 75 .init_uarts = exynos_init_uarts,
68 .init = exynos_init, 76 .init = exynos_init,
69 .name = name_exynos4212, 77 .name = name_exynos4212,
70 }, { 78 }, {
@@ -72,9 +80,17 @@ static struct cpu_table cpu_ids[] __initdata = {
72 .idmask = EXYNOS4_CPU_MASK, 80 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io, 81 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks, 82 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts, 83 .init_uarts = exynos_init_uarts,
76 .init = exynos_init, 84 .init = exynos_init,
77 .name = name_exynos4412, 85 .name = name_exynos4412,
86 }, {
87 .idcode = EXYNOS5250_SOC_ID,
88 .idmask = EXYNOS5_SOC_MASK,
89 .map_io = exynos5_map_io,
90 .init_clocks = exynos5_init_clocks,
91 .init_uarts = exynos_init_uarts,
92 .init = exynos_init,
93 .name = name_exynos5250,
78 }, 94 },
79}; 95};
80 96
@@ -83,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
83static struct map_desc exynos_iodesc[] __initdata = { 99static struct map_desc exynos_iodesc[] __initdata = {
84 { 100 {
85 .virtual = (unsigned long)S5P_VA_CHIPID, 101 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID), 102 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
87 .length = SZ_4K, 103 .length = SZ_4K,
88 .type = MT_DEVICE, 104 .type = MT_DEVICE,
89 }, { 105 },
106};
107
108static struct map_desc exynos4_iodesc[] __initdata = {
109 {
90 .virtual = (unsigned long)S3C_VA_SYS, 110 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), 111 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
92 .length = SZ_64K, 112 .length = SZ_64K,
@@ -136,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
136 .pfn = __phys_to_pfn(EXYNOS4_PA_UART), 156 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
137 .length = SZ_512K, 157 .length = SZ_512K,
138 .type = MT_DEVICE, 158 .type = MT_DEVICE,
139 }, 159 }, {
140};
141
142static struct map_desc exynos4_iodesc[] __initdata = {
143 {
144 .virtual = (unsigned long)S5P_VA_CMU, 160 .virtual = (unsigned long)S5P_VA_CMU,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 161 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
146 .length = SZ_128K, 162 .length = SZ_128K,
@@ -201,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
201 }, 217 },
202}; 218};
203 219
220static struct map_desc exynos5_iodesc[] __initdata = {
221 {
222 .virtual = (unsigned long)S3C_VA_SYS,
223 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
224 .length = SZ_64K,
225 .type = MT_DEVICE,
226 }, {
227 .virtual = (unsigned long)S3C_VA_TIMER,
228 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
229 .length = SZ_16K,
230 .type = MT_DEVICE,
231 }, {
232 .virtual = (unsigned long)S3C_VA_WATCHDOG,
233 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
234 .length = SZ_4K,
235 .type = MT_DEVICE,
236 }, {
237 .virtual = (unsigned long)S5P_VA_SROMC,
238 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
239 .length = SZ_4K,
240 .type = MT_DEVICE,
241 }, {
242 .virtual = (unsigned long)S5P_VA_SYSTIMER,
243 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
244 .length = SZ_4K,
245 .type = MT_DEVICE,
246 }, {
247 .virtual = (unsigned long)S5P_VA_SYSRAM,
248 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
249 .length = SZ_4K,
250 .type = MT_DEVICE,
251 }, {
252 .virtual = (unsigned long)S5P_VA_CMU,
253 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
254 .length = 144 * SZ_1K,
255 .type = MT_DEVICE,
256 }, {
257 .virtual = (unsigned long)S5P_VA_PMU,
258 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
259 .length = SZ_64K,
260 .type = MT_DEVICE,
261 }, {
262 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
263 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
264 .length = SZ_4K,
265 .type = MT_DEVICE,
266 }, {
267 .virtual = (unsigned long)S3C_VA_UART,
268 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
269 .length = SZ_512K,
270 .type = MT_DEVICE,
271 }, {
272 .virtual = (unsigned long)S5P_VA_GIC_CPU,
273 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
274 .length = SZ_64K,
275 .type = MT_DEVICE,
276 }, {
277 .virtual = (unsigned long)S5P_VA_GIC_DIST,
278 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
279 .length = SZ_64K,
280 .type = MT_DEVICE,
281 },
282};
283
204void exynos4_restart(char mode, const char *cmd) 284void exynos4_restart(char mode, const char *cmd)
205{ 285{
206 __raw_writel(0x1, S5P_SWRESET); 286 __raw_writel(0x1, S5P_SWRESET);
207} 287}
208 288
289void exynos5_restart(char mode, const char *cmd)
290{
291 __raw_writel(0x1, EXYNOS_SWRESET);
292}
293
209/* 294/*
210 * exynos_map_io 295 * exynos_map_io
211 * 296 *
@@ -225,7 +310,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
225 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 310 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
226} 311}
227 312
228void __init exynos4_map_io(void) 313static void __init exynos4_map_io(void)
229{ 314{
230 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 315 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
231 316
@@ -256,7 +341,22 @@ void __init exynos4_map_io(void)
256 s5p_hdmi_setname("exynos4-hdmi"); 341 s5p_hdmi_setname("exynos4-hdmi");
257} 342}
258 343
259void __init exynos4_init_clocks(int xtal) 344static void __init exynos5_map_io(void)
345{
346 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
347
348 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
349 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
350 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
351 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
352
353 /* The I2C bus controllers are directly compatible with s3c2440 */
354 s3c_i2c0_setname("s3c2440-i2c");
355 s3c_i2c1_setname("s3c2440-i2c");
356 s3c_i2c2_setname("s3c2440-i2c");
357}
358
359static void __init exynos4_init_clocks(int xtal)
260{ 360{
261 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 361 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
262 362
@@ -272,6 +372,17 @@ void __init exynos4_init_clocks(int xtal)
272 exynos4_setup_clocks(); 372 exynos4_setup_clocks();
273} 373}
274 374
375static void __init exynos5_init_clocks(int xtal)
376{
377 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
378
379 s3c24xx_register_baseclocks(xtal);
380 s5p_register_clocks(xtal);
381
382 exynos5_register_clocks();
383 exynos5_setup_clocks();
384}
385
275#define COMBINER_ENABLE_SET 0x0 386#define COMBINER_ENABLE_SET 0x0
276#define COMBINER_ENABLE_CLEAR 0x4 387#define COMBINER_ENABLE_CLEAR 0x4
277#define COMBINER_INT_STATUS 0xC 388#define COMBINER_INT_STATUS 0xC
@@ -345,7 +456,14 @@ static struct irq_chip combiner_chip = {
345 456
346static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 457static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
347{ 458{
348 if (combiner_nr >= MAX_COMBINER_NR) 459 unsigned int max_nr;
460
461 if (soc_is_exynos5250())
462 max_nr = EXYNOS5_MAX_COMBINER_NR;
463 else
464 max_nr = EXYNOS4_MAX_COMBINER_NR;
465
466 if (combiner_nr >= max_nr)
349 BUG(); 467 BUG();
350 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) 468 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
351 BUG(); 469 BUG();
@@ -356,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
356 unsigned int irq_start) 474 unsigned int irq_start)
357{ 475{
358 unsigned int i; 476 unsigned int i;
477 unsigned int max_nr;
478
479 if (soc_is_exynos5250())
480 max_nr = EXYNOS5_MAX_COMBINER_NR;
481 else
482 max_nr = EXYNOS4_MAX_COMBINER_NR;
359 483
360 if (combiner_nr >= MAX_COMBINER_NR) 484 if (combiner_nr >= max_nr)
361 BUG(); 485 BUG();
362 486
363 combiner_data[combiner_nr].base = base; 487 combiner_data[combiner_nr].base = base;
@@ -400,8 +524,28 @@ void __init exynos4_init_irq(void)
400 of_irq_init(exynos4_dt_irq_match); 524 of_irq_init(exynos4_dt_irq_match);
401#endif 525#endif
402 526
403 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 527 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
528
529 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
530 COMBINER_IRQ(irq, 0));
531 combiner_cascade_irq(irq, IRQ_SPI(irq));
532 }
533
534 /*
535 * The parameters of s5p_init_irq() are for VIC init.
536 * Theses parameters should be NULL and 0 because EXYNOS4
537 * uses GIC instead of VIC.
538 */
539 s5p_init_irq(NULL, 0);
540}
541
542void __init exynos5_init_irq(void)
543{
544 int irq;
545
546 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
404 547
548 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
405 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 549 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
406 COMBINER_IRQ(irq, 0)); 550 COMBINER_IRQ(irq, 0));
407 combiner_cascade_irq(irq, IRQ_SPI(irq)); 551 combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -420,19 +564,34 @@ struct bus_type exynos4_subsys = {
420 .dev_name = "exynos4-core", 564 .dev_name = "exynos4-core",
421}; 565};
422 566
567struct bus_type exynos5_subsys = {
568 .name = "exynos5-core",
569 .dev_name = "exynos5-core",
570};
571
423static struct device exynos4_dev = { 572static struct device exynos4_dev = {
424 .bus = &exynos4_subsys, 573 .bus = &exynos4_subsys,
425}; 574};
426 575
427static int __init exynos4_core_init(void) 576static struct device exynos5_dev = {
577 .bus = &exynos5_subsys,
578};
579
580static int __init exynos_core_init(void)
428{ 581{
429 return subsys_system_register(&exynos4_subsys, NULL); 582 if (soc_is_exynos5250())
583 return subsys_system_register(&exynos5_subsys, NULL);
584 else
585 return subsys_system_register(&exynos4_subsys, NULL);
430} 586}
431core_initcall(exynos4_core_init); 587core_initcall(exynos_core_init);
432 588
433#ifdef CONFIG_CACHE_L2X0 589#ifdef CONFIG_CACHE_L2X0
434static int __init exynos4_l2x0_cache_init(void) 590static int __init exynos4_l2x0_cache_init(void)
435{ 591{
592 if (soc_is_exynos5250())
593 return 0;
594
436 /* TAG, Data Latency Control: 2cycle */ 595 /* TAG, Data Latency Control: 2cycle */
437 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 596 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
438 597
@@ -452,19 +611,47 @@ static int __init exynos4_l2x0_cache_init(void)
452 611
453 return 0; 612 return 0;
454} 613}
455
456early_initcall(exynos4_l2x0_cache_init); 614early_initcall(exynos4_l2x0_cache_init);
457#endif 615#endif
458 616
459int __init exynos_init(void) 617static int __init exynos5_l2_cache_init(void)
618{
619 unsigned int val;
620
621 if (!soc_is_exynos5250())
622 return 0;
623
624 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
625 "bic %0, %0, #(1 << 2)\n" /* cache disable */
626 "mcr p15, 0, %0, c1, c0, 0\n"
627 "mrc p15, 1, %0, c9, c0, 2\n"
628 : "=r"(val));
629
630 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
631
632 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
633 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
634 "orr %0, %0, #(1 << 2)\n" /* cache enable */
635 "mcr p15, 0, %0, c1, c0, 0\n"
636 : : "r"(val));
637
638 return 0;
639}
640early_initcall(exynos5_l2_cache_init);
641
642static int __init exynos_init(void)
460{ 643{
461 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 644 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
462 return device_register(&exynos4_dev); 645
646 if (soc_is_exynos5250())
647 return device_register(&exynos5_dev);
648 else
649 return device_register(&exynos4_dev);
463} 650}
464 651
465/* uart registration process */ 652/* uart registration process */
466 653
467void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) 654static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
468{ 655{
469 struct s3c2410_uartcfg *tcfg = cfg; 656 struct s3c2410_uartcfg *tcfg = cfg;
470 u32 ucnt; 657 u32 ucnt;
@@ -472,69 +659,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
472 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) 659 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
473 tcfg->has_fracval = 1; 660 tcfg->has_fracval = 1;
474 661
475 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); 662 if (soc_is_exynos5250())
663 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
664 else
665 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
476} 666}
477 667
668static void __iomem *exynos_eint_base;
669
478static DEFINE_SPINLOCK(eint_lock); 670static DEFINE_SPINLOCK(eint_lock);
479 671
480static unsigned int eint0_15_data[16]; 672static unsigned int eint0_15_data[16];
481 673
482static unsigned int exynos4_get_irq_nr(unsigned int number) 674static inline int exynos4_irq_to_gpio(unsigned int irq)
483{ 675{
484 u32 ret = 0; 676 if (irq < IRQ_EINT(0))
677 return -EINVAL;
485 678
486 switch (number) { 679 irq -= IRQ_EINT(0);
487 case 0 ... 3: 680 if (irq < 8)
488 ret = (number + IRQ_EINT0); 681 return EXYNOS4_GPX0(irq);
489 break; 682
490 case 4 ... 7: 683 irq -= 8;
491 ret = (number + (IRQ_EINT4 - 4)); 684 if (irq < 8)
492 break; 685 return EXYNOS4_GPX1(irq);
493 case 8 ... 15: 686
494 ret = (number + (IRQ_EINT8 - 8)); 687 irq -= 8;
495 break; 688 if (irq < 8)
496 default: 689 return EXYNOS4_GPX2(irq);
497 printk(KERN_ERR "number available : %d\n", number);
498 }
499 690
500 return ret; 691 irq -= 8;
692 if (irq < 8)
693 return EXYNOS4_GPX3(irq);
694
695 return -EINVAL;
501} 696}
502 697
503static inline void exynos4_irq_eint_mask(struct irq_data *data) 698static inline int exynos5_irq_to_gpio(unsigned int irq)
699{
700 if (irq < IRQ_EINT(0))
701 return -EINVAL;
702
703 irq -= IRQ_EINT(0);
704 if (irq < 8)
705 return EXYNOS5_GPX0(irq);
706
707 irq -= 8;
708 if (irq < 8)
709 return EXYNOS5_GPX1(irq);
710
711 irq -= 8;
712 if (irq < 8)
713 return EXYNOS5_GPX2(irq);
714
715 irq -= 8;
716 if (irq < 8)
717 return EXYNOS5_GPX3(irq);
718
719 return -EINVAL;
720}
721
722static unsigned int exynos4_eint0_15_src_int[16] = {
723 EXYNOS4_IRQ_EINT0,
724 EXYNOS4_IRQ_EINT1,
725 EXYNOS4_IRQ_EINT2,
726 EXYNOS4_IRQ_EINT3,
727 EXYNOS4_IRQ_EINT4,
728 EXYNOS4_IRQ_EINT5,
729 EXYNOS4_IRQ_EINT6,
730 EXYNOS4_IRQ_EINT7,
731 EXYNOS4_IRQ_EINT8,
732 EXYNOS4_IRQ_EINT9,
733 EXYNOS4_IRQ_EINT10,
734 EXYNOS4_IRQ_EINT11,
735 EXYNOS4_IRQ_EINT12,
736 EXYNOS4_IRQ_EINT13,
737 EXYNOS4_IRQ_EINT14,
738 EXYNOS4_IRQ_EINT15,
739};
740
741static unsigned int exynos5_eint0_15_src_int[16] = {
742 EXYNOS5_IRQ_EINT0,
743 EXYNOS5_IRQ_EINT1,
744 EXYNOS5_IRQ_EINT2,
745 EXYNOS5_IRQ_EINT3,
746 EXYNOS5_IRQ_EINT4,
747 EXYNOS5_IRQ_EINT5,
748 EXYNOS5_IRQ_EINT6,
749 EXYNOS5_IRQ_EINT7,
750 EXYNOS5_IRQ_EINT8,
751 EXYNOS5_IRQ_EINT9,
752 EXYNOS5_IRQ_EINT10,
753 EXYNOS5_IRQ_EINT11,
754 EXYNOS5_IRQ_EINT12,
755 EXYNOS5_IRQ_EINT13,
756 EXYNOS5_IRQ_EINT14,
757 EXYNOS5_IRQ_EINT15,
758};
759static inline void exynos_irq_eint_mask(struct irq_data *data)
504{ 760{
505 u32 mask; 761 u32 mask;
506 762
507 spin_lock(&eint_lock); 763 spin_lock(&eint_lock);
508 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 764 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
509 mask |= eint_irq_to_bit(data->irq); 765 mask |= EINT_OFFSET_BIT(data->irq);
510 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 766 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
511 spin_unlock(&eint_lock); 767 spin_unlock(&eint_lock);
512} 768}
513 769
514static void exynos4_irq_eint_unmask(struct irq_data *data) 770static void exynos_irq_eint_unmask(struct irq_data *data)
515{ 771{
516 u32 mask; 772 u32 mask;
517 773
518 spin_lock(&eint_lock); 774 spin_lock(&eint_lock);
519 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 775 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
520 mask &= ~(eint_irq_to_bit(data->irq)); 776 mask &= ~(EINT_OFFSET_BIT(data->irq));
521 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 777 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
522 spin_unlock(&eint_lock); 778 spin_unlock(&eint_lock);
523} 779}
524 780
525static inline void exynos4_irq_eint_ack(struct irq_data *data) 781static inline void exynos_irq_eint_ack(struct irq_data *data)
526{ 782{
527 __raw_writel(eint_irq_to_bit(data->irq), 783 __raw_writel(EINT_OFFSET_BIT(data->irq),
528 S5P_EINT_PEND(EINT_REG_NR(data->irq))); 784 EINT_PEND(exynos_eint_base, data->irq));
529} 785}
530 786
531static void exynos4_irq_eint_maskack(struct irq_data *data) 787static void exynos_irq_eint_maskack(struct irq_data *data)
532{ 788{
533 exynos4_irq_eint_mask(data); 789 exynos_irq_eint_mask(data);
534 exynos4_irq_eint_ack(data); 790 exynos_irq_eint_ack(data);
535} 791}
536 792
537static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type) 793static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
538{ 794{
539 int offs = EINT_OFFSET(data->irq); 795 int offs = EINT_OFFSET(data->irq);
540 int shift; 796 int shift;
@@ -571,39 +827,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
571 mask = 0x7 << shift; 827 mask = 0x7 << shift;
572 828
573 spin_lock(&eint_lock); 829 spin_lock(&eint_lock);
574 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); 830 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
575 ctrl &= ~mask; 831 ctrl &= ~mask;
576 ctrl |= newvalue << shift; 832 ctrl |= newvalue << shift;
577 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); 833 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
578 spin_unlock(&eint_lock); 834 spin_unlock(&eint_lock);
579 835
580 switch (offs) { 836 if (soc_is_exynos5250())
581 case 0 ... 7: 837 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
582 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); 838 else
583 break; 839 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
584 case 8 ... 15:
585 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
586 break;
587 case 16 ... 23:
588 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
589 break;
590 case 24 ... 31:
591 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
592 break;
593 default:
594 printk(KERN_ERR "No such irq number %d", offs);
595 }
596 840
597 return 0; 841 return 0;
598} 842}
599 843
600static struct irq_chip exynos4_irq_eint = { 844static struct irq_chip exynos_irq_eint = {
601 .name = "exynos4-eint", 845 .name = "exynos-eint",
602 .irq_mask = exynos4_irq_eint_mask, 846 .irq_mask = exynos_irq_eint_mask,
603 .irq_unmask = exynos4_irq_eint_unmask, 847 .irq_unmask = exynos_irq_eint_unmask,
604 .irq_mask_ack = exynos4_irq_eint_maskack, 848 .irq_mask_ack = exynos_irq_eint_maskack,
605 .irq_ack = exynos4_irq_eint_ack, 849 .irq_ack = exynos_irq_eint_ack,
606 .irq_set_type = exynos4_irq_eint_set_type, 850 .irq_set_type = exynos_irq_eint_set_type,
607#ifdef CONFIG_PM 851#ifdef CONFIG_PM
608 .irq_set_wake = s3c_irqext_wake, 852 .irq_set_wake = s3c_irqext_wake,
609#endif 853#endif
@@ -618,12 +862,12 @@ static struct irq_chip exynos4_irq_eint = {
618 * 862 *
619 * Each EINT pend/mask registers handle eight of them. 863 * Each EINT pend/mask registers handle eight of them.
620 */ 864 */
621static inline void exynos4_irq_demux_eint(unsigned int start) 865static inline void exynos_irq_demux_eint(unsigned int start)
622{ 866{
623 unsigned int irq; 867 unsigned int irq;
624 868
625 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); 869 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
626 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); 870 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
627 871
628 status &= ~mask; 872 status &= ~mask;
629 status &= 0xff; 873 status &= 0xff;
@@ -635,16 +879,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
635 } 879 }
636} 880}
637 881
638static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 882static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
639{ 883{
640 struct irq_chip *chip = irq_get_chip(irq); 884 struct irq_chip *chip = irq_get_chip(irq);
641 chained_irq_enter(chip, desc); 885 chained_irq_enter(chip, desc);
642 exynos4_irq_demux_eint(IRQ_EINT(16)); 886 exynos_irq_demux_eint(IRQ_EINT(16));
643 exynos4_irq_demux_eint(IRQ_EINT(24)); 887 exynos_irq_demux_eint(IRQ_EINT(24));
644 chained_irq_exit(chip, desc); 888 chained_irq_exit(chip, desc);
645} 889}
646 890
647static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 891static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
648{ 892{
649 u32 *irq_data = irq_get_handler_data(irq); 893 u32 *irq_data = irq_get_handler_data(irq);
650 struct irq_chip *chip = irq_get_chip(irq); 894 struct irq_chip *chip = irq_get_chip(irq);
@@ -661,27 +905,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
661 chained_irq_exit(chip, desc); 905 chained_irq_exit(chip, desc);
662} 906}
663 907
664int __init exynos4_init_irq_eint(void) 908static int __init exynos_init_irq_eint(void)
665{ 909{
666 int irq; 910 int irq;
667 911
912 if (soc_is_exynos5250())
913 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
914 else
915 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
916
917 if (exynos_eint_base == NULL) {
918 pr_err("unable to ioremap for EINT base address\n");
919 return -ENOMEM;
920 }
921
668 for (irq = 0 ; irq <= 31 ; irq++) { 922 for (irq = 0 ; irq <= 31 ; irq++) {
669 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, 923 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
670 handle_level_irq); 924 handle_level_irq);
671 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 925 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
672 } 926 }
673 927
674 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); 928 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
675 929
676 for (irq = 0 ; irq <= 15 ; irq++) { 930 for (irq = 0 ; irq <= 15 ; irq++) {
677 eint0_15_data[irq] = IRQ_EINT(irq); 931 eint0_15_data[irq] = IRQ_EINT(irq);
678 932
679 irq_set_handler_data(exynos4_get_irq_nr(irq), 933 if (soc_is_exynos5250()) {
680 &eint0_15_data[irq]); 934 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
681 irq_set_chained_handler(exynos4_get_irq_nr(irq), 935 &eint0_15_data[irq]);
682 exynos4_irq_eint0_15); 936 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
937 exynos_irq_eint0_15);
938 } else {
939 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
940 &eint0_15_data[irq]);
941 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
942 exynos_irq_eint0_15);
943 }
683 } 944 }
684 945
685 return 0; 946 return 0;
686} 947}
687arch_initcall(exynos4_init_irq_eint); 948arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f39..677b5467df1 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,30 +12,44 @@
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H 12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H 13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14 14
15extern struct sys_timer exynos4_timer;
16
15void exynos_init_io(struct map_desc *mach_desc, int size); 17void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void); 18void exynos4_init_irq(void);
19void exynos5_init_irq(void);
20void exynos4_restart(char mode, const char *cmd);
21void exynos5_restart(char mode, const char *cmd);
17 22
23#ifdef CONFIG_ARCH_EXYNOS4
18void exynos4_register_clocks(void); 24void exynos4_register_clocks(void);
19void exynos4_setup_clocks(void); 25void exynos4_setup_clocks(void);
20 26
21void exynos4210_register_clocks(void); 27#else
22void exynos4212_register_clocks(void); 28#define exynos4_register_clocks()
29#define exynos4_setup_clocks()
30#endif
23 31
24void exynos4_restart(char mode, const char *cmd); 32#ifdef CONFIG_ARCH_EXYNOS5
33void exynos5_register_clocks(void);
34void exynos5_setup_clocks(void);
25 35
26extern struct sys_timer exynos4_timer; 36#else
37#define exynos5_register_clocks()
38#define exynos5_setup_clocks()
39#endif
40
41#ifdef CONFIG_CPU_EXYNOS4210
42void exynos4210_register_clocks(void);
27 43
28#ifdef CONFIG_ARCH_EXYNOS 44#else
29extern int exynos_init(void); 45#define exynos4210_register_clocks()
30extern void exynos4_map_io(void); 46#endif
31extern void exynos4_init_clocks(int xtal); 47
32extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); 48#ifdef CONFIG_SOC_EXYNOS4212
49void exynos4212_register_clocks(void);
33 50
34#else 51#else
35#define exynos4_init_clocks NULL 52#define exynos4212_register_clocks()
36#define exynos4_init_uarts NULL
37#define exynos4_map_io NULL
38#define exynos_init NULL
39#endif 53#endif
40 54
41#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 55#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de8e1d..50ce5b0adcf 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
242 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
243 }, 243 },
244 [1] = { 244 [1] = {
245 .start = IRQ_SATA, 245 .start = EXYNOS4_IRQ_SATA,
246 .end = IRQ_SATA, 246 .end = EXYNOS4_IRQ_SATA,
247 .flags = IORESOURCE_IRQ, 247 .flags = IORESOURCE_IRQ,
248 }, 248 },
249}; 249};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e53b..7199e1ae79b 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
304 .flags = IORESOURCE_DMA, 304 .flags = IORESOURCE_DMA,
305 }, 305 },
306 [4] = { 306 [4] = {
307 .start = IRQ_AC97, 307 .start = EXYNOS4_IRQ_AC97,
308 .end = IRQ_AC97, 308 .end = EXYNOS4_IRQ_AC97,
309 .flags = IORESOURCE_IRQ, 309 .flags = IORESOURCE_IRQ,
310 }, 310 },
311}; 311};
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 00000000000..2e85c022fd1
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Base EXYNOS UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/devs.h>
25
26#define EXYNOS_UART_RESOURCE(_series, _nr) \
27static struct resource exynos##_series##_uart##_nr##_resource[] = { \
28 [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
29 [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
30};
31
32EXYNOS_UART_RESOURCE(4, 0)
33EXYNOS_UART_RESOURCE(4, 1)
34EXYNOS_UART_RESOURCE(4, 2)
35EXYNOS_UART_RESOURCE(4, 3)
36
37struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
38 [0] = {
39 .resources = exynos4_uart0_resource,
40 .nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
41 },
42 [1] = {
43 .resources = exynos4_uart1_resource,
44 .nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
45 },
46 [2] = {
47 .resources = exynos4_uart2_resource,
48 .nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
49 },
50 [3] = {
51 .resources = exynos4_uart3_resource,
52 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
53 },
54};
55
56EXYNOS_UART_RESOURCE(5, 0)
57EXYNOS_UART_RESOURCE(5, 1)
58EXYNOS_UART_RESOURCE(5, 2)
59EXYNOS_UART_RESOURCE(5, 3)
60
61struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
62 [0] = {
63 .resources = exynos5_uart0_resource,
64 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
65 },
66 [1] = {
67 .resources = exynos5_uart1_resource,
68 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
69 },
70 [2] = {
71 .resources = exynos5_uart2_resource,
72 .nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
73 },
74 [3] = {
75 .resources = exynos5_uart3_resource,
76 .nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
77 },
78};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 91370def4a7..3983abee426 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <plat/devs.h> 30#include <plat/devs.h>
31#include <plat/irqs.h> 31#include <plat/irqs.h>
32#include <plat/cpu.h>
32 33
33#include <mach/map.h> 34#include <mach/map.h>
34#include <mach/irqs.h> 35#include <mach/irqs.h>
@@ -36,7 +37,7 @@
36 37
37static u64 dma_dmamask = DMA_BIT_MASK(32); 38static u64 dma_dmamask = DMA_BIT_MASK(32);
38 39
39u8 pdma0_peri[] = { 40static u8 exynos4210_pdma0_peri[] = {
40 DMACH_PCM0_RX, 41 DMACH_PCM0_RX,
41 DMACH_PCM0_TX, 42 DMACH_PCM0_TX,
42 DMACH_PCM2_RX, 43 DMACH_PCM2_RX,
@@ -69,15 +70,47 @@ u8 pdma0_peri[] = {
69 DMACH_AC97_PCMOUT, 70 DMACH_AC97_PCMOUT,
70}; 71};
71 72
72struct dma_pl330_platdata exynos4_pdma0_pdata = { 73static u8 exynos4212_pdma0_peri[] = {
73 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 74 DMACH_PCM0_RX,
74 .peri_id = pdma0_peri, 75 DMACH_PCM0_TX,
76 DMACH_PCM2_RX,
77 DMACH_PCM2_TX,
78 DMACH_MIPI_HSI0,
79 DMACH_MIPI_HSI1,
80 DMACH_SPI0_RX,
81 DMACH_SPI0_TX,
82 DMACH_SPI2_RX,
83 DMACH_SPI2_TX,
84 DMACH_I2S0S_TX,
85 DMACH_I2S0_RX,
86 DMACH_I2S0_TX,
87 DMACH_I2S2_RX,
88 DMACH_I2S2_TX,
89 DMACH_UART0_RX,
90 DMACH_UART0_TX,
91 DMACH_UART2_RX,
92 DMACH_UART2_TX,
93 DMACH_UART4_RX,
94 DMACH_UART4_TX,
95 DMACH_SLIMBUS0_RX,
96 DMACH_SLIMBUS0_TX,
97 DMACH_SLIMBUS2_RX,
98 DMACH_SLIMBUS2_TX,
99 DMACH_SLIMBUS4_RX,
100 DMACH_SLIMBUS4_TX,
101 DMACH_AC97_MICIN,
102 DMACH_AC97_PCMIN,
103 DMACH_AC97_PCMOUT,
104 DMACH_MIPI_HSI4,
105 DMACH_MIPI_HSI5,
75}; 106};
76 107
77AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0, 108struct dma_pl330_platdata exynos4_pdma0_pdata;
78 {IRQ_PDMA0}, &exynos4_pdma0_pdata); 109
110static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
111 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
79 112
80u8 pdma1_peri[] = { 113static u8 exynos4210_pdma1_peri[] = {
81 DMACH_PCM0_RX, 114 DMACH_PCM0_RX,
82 DMACH_PCM0_TX, 115 DMACH_PCM0_TX,
83 DMACH_PCM1_RX, 116 DMACH_PCM1_RX,
@@ -105,19 +138,84 @@ u8 pdma1_peri[] = {
105 DMACH_SLIMBUS5_TX, 138 DMACH_SLIMBUS5_TX,
106}; 139};
107 140
108struct dma_pl330_platdata exynos4_pdma1_pdata = { 141static u8 exynos4212_pdma1_peri[] = {
109 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 142 DMACH_PCM0_RX,
110 .peri_id = pdma1_peri, 143 DMACH_PCM0_TX,
144 DMACH_PCM1_RX,
145 DMACH_PCM1_TX,
146 DMACH_MIPI_HSI2,
147 DMACH_MIPI_HSI3,
148 DMACH_SPI1_RX,
149 DMACH_SPI1_TX,
150 DMACH_I2S0S_TX,
151 DMACH_I2S0_RX,
152 DMACH_I2S0_TX,
153 DMACH_I2S1_RX,
154 DMACH_I2S1_TX,
155 DMACH_UART0_RX,
156 DMACH_UART0_TX,
157 DMACH_UART1_RX,
158 DMACH_UART1_TX,
159 DMACH_UART3_RX,
160 DMACH_UART3_TX,
161 DMACH_SLIMBUS1_RX,
162 DMACH_SLIMBUS1_TX,
163 DMACH_SLIMBUS3_RX,
164 DMACH_SLIMBUS3_TX,
165 DMACH_SLIMBUS5_RX,
166 DMACH_SLIMBUS5_TX,
167 DMACH_SLIMBUS0AUX_RX,
168 DMACH_SLIMBUS0AUX_TX,
169 DMACH_SPDIF,
170 DMACH_MIPI_HSI6,
171 DMACH_MIPI_HSI7,
172};
173
174static struct dma_pl330_platdata exynos4_pdma1_pdata;
175
176static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
177 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
178
179static u8 mdma_peri[] = {
180 DMACH_MTOM_0,
181 DMACH_MTOM_1,
182 DMACH_MTOM_2,
183 DMACH_MTOM_3,
184 DMACH_MTOM_4,
185 DMACH_MTOM_5,
186 DMACH_MTOM_6,
187 DMACH_MTOM_7,
111}; 188};
112 189
113AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1, 190static struct dma_pl330_platdata exynos4_mdma1_pdata = {
114 {IRQ_PDMA1}, &exynos4_pdma1_pdata); 191 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
192 .peri_id = mdma_peri,
193};
194
195static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
196 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
115 197
116static int __init exynos4_dma_init(void) 198static int __init exynos4_dma_init(void)
117{ 199{
118 if (of_have_populated_dt()) 200 if (of_have_populated_dt())
119 return 0; 201 return 0;
120 202
203 if (soc_is_exynos4210()) {
204 exynos4_pdma0_pdata.nr_valid_peri =
205 ARRAY_SIZE(exynos4210_pdma0_peri);
206 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
207 exynos4_pdma1_pdata.nr_valid_peri =
208 ARRAY_SIZE(exynos4210_pdma1_peri);
209 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
210 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
211 exynos4_pdma0_pdata.nr_valid_peri =
212 ARRAY_SIZE(exynos4212_pdma0_peri);
213 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
214 exynos4_pdma1_pdata.nr_valid_peri =
215 ARRAY_SIZE(exynos4212_pdma1_peri);
216 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
217 }
218
121 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); 219 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
122 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); 220 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
123 amba_device_register(&exynos4_pdma0_device, &iomem_resource); 221 amba_device_register(&exynos4_pdma0_device, &iomem_resource);
@@ -126,6 +224,9 @@ static int __init exynos4_dma_init(void)
126 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); 224 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
127 amba_device_register(&exynos4_pdma1_device, &iomem_resource); 225 amba_device_register(&exynos4_pdma1_device, &iomem_resource);
128 226
227 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
228 amba_device_register(&exynos4_mdma1_device, &iomem_resource);
229
129 return 0; 230 return 0;
130} 231}
131arch_initcall(exynos4_dma_init); 232arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a..6c857ff0b5d 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
21 */ 21 */
22 22
23 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART 24 mov \rp, #0x10000000
25 ldr \rv, = S3C_VA_UART 25 ldr \rp, [\rp, #0x0]
26 and \rp, \rp, #0xf00000
27 teq \rp, #0x500000 @@ EXYNOS5
28 ldreq \rp, =EXYNOS5_PA_UART
29 movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
30 ldr \rv, =S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0 31#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 32 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) 33 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf5525..00000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Header file for exynos4 clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_CLOCK_H
15#define __ASM_ARCH_CLOCK_H __FILE__
16
17#include <linux/clk.h>
18
19extern struct clk clk_sclk_hdmi27m;
20extern struct clk clk_sclk_usbphy0;
21extern struct clk clk_sclk_usbphy1;
22extern struct clk clk_sclk_hdmiphy;
23
24extern struct clksrc_clk clk_sclk_apll;
25extern struct clksrc_clk clk_mout_mpll;
26extern struct clksrc_clk clk_aclk_133;
27extern struct clksrc_clk clk_mout_epll;
28extern struct clksrc_clk clk_sclk_vpll;
29
30extern struct clk *clkset_corebus_list[];
31extern struct clksrc_sources clkset_mout_corebus;
32
33extern struct clk *clkset_aclk_top_list[];
34extern struct clksrc_sources clkset_aclk;
35
36extern struct clk *clkset_group_list[];
37extern struct clksrc_sources clkset_group;
38
39extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
40extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
41extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
42
43#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce04789..9bee8535d9e 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - IRQ definitions 5 * EXYNOS - IRQ definitions
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -17,158 +16,450 @@
17 16
18/* PPI: Private Peripheral Interrupt */ 17/* PPI: Private Peripheral Interrupt */
19 18
20#define IRQ_PPI(x) (x+16) 19#define IRQ_PPI(x) (x + 16)
21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23 20
24/* SPI: Shared Peripheral Interrupt */ 21/* SPI: Shared Peripheral Interrupt */
25 22
26#define IRQ_SPI(x) (x+32) 23#define IRQ_SPI(x) (x + 32)
27 24
28#define IRQ_EINT0 IRQ_SPI(16) 25/* COMBINER */
29#define IRQ_EINT1 IRQ_SPI(17) 26
30#define IRQ_EINT2 IRQ_SPI(18) 27#define MAX_IRQ_IN_COMBINER 8
31#define IRQ_EINT3 IRQ_SPI(19) 28#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
32#define IRQ_EINT4 IRQ_SPI(20) 29#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
33#define IRQ_EINT5 IRQ_SPI(21) 30
34#define IRQ_EINT6 IRQ_SPI(22) 31/* For EXYNOS4 and EXYNOS5 */
35#define IRQ_EINT7 IRQ_SPI(23) 32
36#define IRQ_EINT8 IRQ_SPI(24) 33#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
37#define IRQ_EINT9 IRQ_SPI(25) 34
38#define IRQ_EINT10 IRQ_SPI(26) 35#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
39#define IRQ_EINT11 IRQ_SPI(27) 36
40#define IRQ_EINT12 IRQ_SPI(28) 37/* For EXYNOS4 SoCs */
41#define IRQ_EINT13 IRQ_SPI(29) 38
42#define IRQ_EINT14 IRQ_SPI(30) 39#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
43#define IRQ_EINT15 IRQ_SPI(31) 40#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
44#define IRQ_EINT16_31 IRQ_SPI(32) 41#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
45 42#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
46#define IRQ_PDMA0 IRQ_SPI(35) 43#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
47#define IRQ_PDMA1 IRQ_SPI(36) 44#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
48#define IRQ_TIMER0_VIC IRQ_SPI(37) 45#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
49#define IRQ_TIMER1_VIC IRQ_SPI(38) 46#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
50#define IRQ_TIMER2_VIC IRQ_SPI(39) 47#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
51#define IRQ_TIMER3_VIC IRQ_SPI(40) 48#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
52#define IRQ_TIMER4_VIC IRQ_SPI(41) 49#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
53#define IRQ_MCT_L0 IRQ_SPI(42) 50#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
54#define IRQ_WDT IRQ_SPI(43) 51#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
55#define IRQ_RTC_ALARM IRQ_SPI(44) 52#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
56#define IRQ_RTC_TIC IRQ_SPI(45) 53#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
57#define IRQ_GPIO_XB IRQ_SPI(46) 54#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
58#define IRQ_GPIO_XA IRQ_SPI(47) 55
59#define IRQ_MCT_L1 IRQ_SPI(48) 56#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
60 57#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
61#define IRQ_UART0 IRQ_SPI(52) 58#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
62#define IRQ_UART1 IRQ_SPI(53) 59#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
63#define IRQ_UART2 IRQ_SPI(54) 60#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
64#define IRQ_UART3 IRQ_SPI(55) 61#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
65#define IRQ_UART4 IRQ_SPI(56) 62#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
66#define IRQ_MCT_G0 IRQ_SPI(57) 63#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
67#define IRQ_IIC IRQ_SPI(58) 64#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
68#define IRQ_IIC1 IRQ_SPI(59) 65#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
69#define IRQ_IIC2 IRQ_SPI(60) 66#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
70#define IRQ_IIC3 IRQ_SPI(61) 67#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
71#define IRQ_IIC4 IRQ_SPI(62) 68#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
72#define IRQ_IIC5 IRQ_SPI(63) 69#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
73#define IRQ_IIC6 IRQ_SPI(64) 70#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
74#define IRQ_IIC7 IRQ_SPI(65) 71#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
75#define IRQ_SPI0 IRQ_SPI(66) 72
76#define IRQ_SPI1 IRQ_SPI(67) 73#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
77#define IRQ_SPI2 IRQ_SPI(68) 74#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
78 75#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
79#define IRQ_USB_HOST IRQ_SPI(70) 76#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
80#define IRQ_USB_HSOTG IRQ_SPI(71) 77#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
81#define IRQ_MODEM_IF IRQ_SPI(72) 78#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
82#define IRQ_HSMMC0 IRQ_SPI(73) 79#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
83#define IRQ_HSMMC1 IRQ_SPI(74) 80#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
84#define IRQ_HSMMC2 IRQ_SPI(75) 81#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
85#define IRQ_HSMMC3 IRQ_SPI(76) 82#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
86#define IRQ_DWMCI IRQ_SPI(77) 83#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
87 84#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
88#define IRQ_MIPI_CSIS0 IRQ_SPI(78) 85#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
89#define IRQ_MIPI_CSIS1 IRQ_SPI(80) 86#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
90 87#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
91#define IRQ_ONENAND_AUDI IRQ_SPI(82) 88#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
92#define IRQ_ROTATOR IRQ_SPI(83) 89#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
93#define IRQ_FIMC0 IRQ_SPI(84) 90
94#define IRQ_FIMC1 IRQ_SPI(85) 91#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
95#define IRQ_FIMC2 IRQ_SPI(86) 92#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
96#define IRQ_FIMC3 IRQ_SPI(87) 93#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
97#define IRQ_JPEG IRQ_SPI(88) 94#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
98#define IRQ_2D IRQ_SPI(89) 95#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
99#define IRQ_PCIE IRQ_SPI(90) 96#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
100 97#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
101#define IRQ_MIXER IRQ_SPI(91) 98#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
102#define IRQ_HDMI IRQ_SPI(92) 99
103#define IRQ_IIC_HDMIPHY IRQ_SPI(93) 100#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
104#define IRQ_MFC IRQ_SPI(94) 101#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
105#define IRQ_SDO IRQ_SPI(95) 102
106 103#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
107#define IRQ_AUDIO_SS IRQ_SPI(96) 104#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
108#define IRQ_I2S0 IRQ_SPI(97) 105#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
109#define IRQ_I2S1 IRQ_SPI(98) 106#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
110#define IRQ_I2S2 IRQ_SPI(99) 107#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
111#define IRQ_AC97 IRQ_SPI(100) 108#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
112 109#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
113#define IRQ_SPDIF IRQ_SPI(104) 110#define EXYNOS4_IRQ_2D IRQ_SPI(89)
114#define IRQ_ADC0 IRQ_SPI(105) 111#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
115#define IRQ_PEN0 IRQ_SPI(106) 112
116#define IRQ_ADC1 IRQ_SPI(107) 113#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
117#define IRQ_PEN1 IRQ_SPI(108) 114#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
118#define IRQ_KEYPAD IRQ_SPI(109) 115#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
119#define IRQ_PMU IRQ_SPI(110) 116#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
120#define IRQ_GPS IRQ_SPI(111) 117#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
121#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) 118
122#define IRQ_SLIMBUS IRQ_SPI(113) 119#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
123 120#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
124#define IRQ_TSI IRQ_SPI(115) 121#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
125#define IRQ_SATA IRQ_SPI(116) 122#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
126 123#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
127#define MAX_IRQ_IN_COMBINER 8 124
128#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) 125#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
129#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 126#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
130 127#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
131#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 128#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
132#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) 129#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
133#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) 130#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
134#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) 131#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
135#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) 132#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
136#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) 133#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
137#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) 134#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
138#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) 135
139 136#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
140#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) 137#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
141#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) 138
142#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) 139#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
143#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) 140#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
144#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) 141#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
145#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) 142#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
146#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 143#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
147#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 144#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
148 145#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
149#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) 146#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
150#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) 147
151#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) 148#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
152 149#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
153#define MAX_COMBINER_NR 16 150#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
154 151#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
155#define IRQ_ADC IRQ_ADC0 152#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
156#define IRQ_TC IRQ_PEN0 153#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
157 154#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
158#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 155#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
159 156
160#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) 157#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
161#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) 158#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
162 159#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
163/* optional GPIO interrupts */ 160
164#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32) 161#define EXYNOS4_MAX_COMBINER_NR 16
165#define IRQ_GPIO1_NR_GROUPS 16 162
166#define IRQ_GPIO2_NR_GROUPS 9 163#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
167#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 164#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
168 165
169#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) 166/*
167 * For Compatibility:
168 * the default is for EXYNOS4, and
169 * for exynos5, should be re-mapped at function
170 */
171
172#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
173#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
174#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
175#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
176#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
177
178#define IRQ_WDT EXYNOS4_IRQ_WDT
179#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
180#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
181#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
182#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
183
184#define IRQ_IIC EXYNOS4_IRQ_IIC
185#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
186#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
187#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
188#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
189#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
190
191#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
192
193#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
194#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
195#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
196#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
197
198#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
199
200#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
201
202#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
203#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
204#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
205#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
206#define IRQ_JPEG EXYNOS4_IRQ_JPEG
207#define IRQ_2D EXYNOS4_IRQ_2D
208
209#define IRQ_MIXER EXYNOS4_IRQ_MIXER
210#define IRQ_HDMI EXYNOS4_IRQ_HDMI
211#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
212#define IRQ_MFC EXYNOS4_IRQ_MFC
213#define IRQ_SDO EXYNOS4_IRQ_SDO
214
215#define IRQ_ADC EXYNOS4_IRQ_ADC0
216#define IRQ_TC EXYNOS4_IRQ_PEN0
217
218#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
219#define IRQ_PMU EXYNOS4_IRQ_PMU
220
221#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
222#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
223#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
224#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
225#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
226#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
227#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
228#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
229
230#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
231#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
232#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
233#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
234#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
235#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
236#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
237#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
238
239#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
240#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
241#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
242
243#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
244#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
245
246/* For EXYNOS5 SoCs */
247
248#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
249#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
250#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
251#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
252#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
253#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
254#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
255#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
256#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
257#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
258#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
259#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
260#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
261#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
262#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
263#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
264#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
265#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
266#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
267#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
268#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
269#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
270#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
271#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
272#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
273#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
274#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
275#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
276#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
277#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
278#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
279#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
280#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
281#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
282#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
283#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
284#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
285#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
286#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
287#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
288#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
289#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
290#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
291#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
292#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
293#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
294#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
295#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
296#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
297#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
298#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
299#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
300#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
301#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
302#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
303#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
304#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
305#define EXYNOS5_IRQ_2D IRQ_SPI(91)
306#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
307#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
308#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
309#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
310#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
311#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
312#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
313#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
314#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
315#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
316#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
317#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
318#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
319#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
320#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
321
322#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
323#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
324#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
325#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
326#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
327#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
328#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
329#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
330#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
331
332#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
333#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
334#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
335#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
336#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
337
338#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
339#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
340
341#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
342#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
343#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
344#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
345#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
346#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
347#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
348#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
349
350#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
351#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
352#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
353#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
354#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
355#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
356
357#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
358#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
359#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
360#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
361
362#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
363#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
364#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
365#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
366#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
367#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
368#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
369#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
370
371#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
372#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
373#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
374#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
375#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
376#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
377#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
378#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
379
380#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
381#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
382#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
383#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
384#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
385#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
386#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
387#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
388
389#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
390#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
391
392#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
393#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
394
395#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
396#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
397#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
398#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
399#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
400
401#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
402#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
403#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
404#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
405
406#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
407#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
408#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
409
410#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
411#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
412#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
413#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
414#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
415#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
416#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
417
418#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
419#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
420#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
421#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
422#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
423
424#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
425#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
426
427#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
428#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
429
430#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
431#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
432
433#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
434#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
435
436#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
437#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
438
439#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
440#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
441
442#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
443#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
444
445#define EXYNOS5_MAX_COMBINER_NR 32
446
447#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
448#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
449#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
450#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
451
452#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
453 EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
454
455#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
456#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
457#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
458#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
459#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
170 460
171/* Set the default NR_IRQS */ 461/* Set the default NR_IRQS */
172#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) 462
463#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
173 464
174#endif /* __ASM_ARCH_IRQS_H */ 465#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22a2bb..bf90bb0ab2b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
25 25
26#define EXYNOS4_PA_SYSRAM0 0x02025000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000 27#define EXYNOS4_PA_SYSRAM1 0x02020000
28#define EXYNOS5_PA_SYSRAM 0x02020000
28 29
29#define EXYNOS4_PA_FIMC0 0x11800000 30#define EXYNOS4_PA_FIMC0 0x11800000
30#define EXYNOS4_PA_FIMC1 0x11810000 31#define EXYNOS4_PA_FIMC1 0x11810000
@@ -44,14 +45,23 @@
44#define EXYNOS4_PA_ONENAND 0x0C000000 45#define EXYNOS4_PA_ONENAND 0x0C000000
45#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 46#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
46 47
47#define EXYNOS4_PA_CHIPID 0x10000000 48#define EXYNOS_PA_CHIPID 0x10000000
48 49
49#define EXYNOS4_PA_SYSCON 0x10010000 50#define EXYNOS4_PA_SYSCON 0x10010000
51#define EXYNOS5_PA_SYSCON 0x10050100
52
50#define EXYNOS4_PA_PMU 0x10020000 53#define EXYNOS4_PA_PMU 0x10020000
54#define EXYNOS5_PA_PMU 0x10040000
55
51#define EXYNOS4_PA_CMU 0x10030000 56#define EXYNOS4_PA_CMU 0x10030000
57#define EXYNOS5_PA_CMU 0x10010000
52 58
53#define EXYNOS4_PA_SYSTIMER 0x10050000 59#define EXYNOS4_PA_SYSTIMER 0x10050000
60#define EXYNOS5_PA_SYSTIMER 0x101C0000
61
54#define EXYNOS4_PA_WATCHDOG 0x10060000 62#define EXYNOS4_PA_WATCHDOG 0x10060000
63#define EXYNOS5_PA_WATCHDOG 0x101D0000
64
55#define EXYNOS4_PA_RTC 0x10070000 65#define EXYNOS4_PA_RTC 0x10070000
56 66
57#define EXYNOS4_PA_KEYPAD 0x100A0000 67#define EXYNOS4_PA_KEYPAD 0x100A0000
@@ -59,15 +69,19 @@
59#define EXYNOS4_PA_DMC0 0x10400000 69#define EXYNOS4_PA_DMC0 0x10400000
60 70
61#define EXYNOS4_PA_COMBINER 0x10440000 71#define EXYNOS4_PA_COMBINER 0x10440000
72#define EXYNOS5_PA_COMBINER 0x10440000
62 73
63#define EXYNOS4_PA_GIC_CPU 0x10480000 74#define EXYNOS4_PA_GIC_CPU 0x10480000
64#define EXYNOS4_PA_GIC_DIST 0x10490000 75#define EXYNOS4_PA_GIC_DIST 0x10490000
76#define EXYNOS5_PA_GIC_CPU 0x10480000
77#define EXYNOS5_PA_GIC_DIST 0x10490000
65 78
66#define EXYNOS4_PA_COREPERI 0x10500000 79#define EXYNOS4_PA_COREPERI 0x10500000
67#define EXYNOS4_PA_TWD 0x10500600 80#define EXYNOS4_PA_TWD 0x10500600
68#define EXYNOS4_PA_L2CC 0x10502000 81#define EXYNOS4_PA_L2CC 0x10502000
69 82
70#define EXYNOS4_PA_MDMA 0x10810000 83#define EXYNOS4_PA_MDMA0 0x10810000
84#define EXYNOS4_PA_MDMA1 0x12840000
71#define EXYNOS4_PA_PDMA0 0x12680000 85#define EXYNOS4_PA_PDMA0 0x12680000
72#define EXYNOS4_PA_PDMA1 0x12690000 86#define EXYNOS4_PA_PDMA1 0x12690000
73 87
@@ -91,7 +105,6 @@
91#define EXYNOS4_PA_SPI1 0x13930000 105#define EXYNOS4_PA_SPI1 0x13930000
92#define EXYNOS4_PA_SPI2 0x13940000 106#define EXYNOS4_PA_SPI2 0x13940000
93 107
94
95#define EXYNOS4_PA_GPIO1 0x11400000 108#define EXYNOS4_PA_GPIO1 0x11400000
96#define EXYNOS4_PA_GPIO2 0x11000000 109#define EXYNOS4_PA_GPIO2 0x11000000
97#define EXYNOS4_PA_GPIO3 0x03860000 110#define EXYNOS4_PA_GPIO3 0x03860000
@@ -109,6 +122,7 @@
109#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 122#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
110 123
111#define EXYNOS4_PA_SROMC 0x12570000 124#define EXYNOS4_PA_SROMC 0x12570000
125#define EXYNOS5_PA_SROMC 0x12250000
112 126
113#define EXYNOS4_PA_EHCI 0x12580000 127#define EXYNOS4_PA_EHCI 0x12580000
114#define EXYNOS4_PA_OHCI 0x12590000 128#define EXYNOS4_PA_OHCI 0x12590000
@@ -116,6 +130,7 @@
116#define EXYNOS4_PA_MFC 0x13400000 130#define EXYNOS4_PA_MFC 0x13400000
117 131
118#define EXYNOS4_PA_UART 0x13800000 132#define EXYNOS4_PA_UART 0x13800000
133#define EXYNOS5_PA_UART 0x12C00000
119 134
120#define EXYNOS4_PA_VP 0x12C00000 135#define EXYNOS4_PA_VP 0x12C00000
121#define EXYNOS4_PA_MIXER 0x12C10000 136#define EXYNOS4_PA_MIXER 0x12C10000
@@ -124,6 +139,7 @@
124#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 139#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
125 140
126#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 141#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
142#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
127 143
128#define EXYNOS4_PA_ADC 0x13910000 144#define EXYNOS4_PA_ADC 0x13910000
129#define EXYNOS4_PA_ADC1 0x13911000 145#define EXYNOS4_PA_ADC1 0x13911000
@@ -133,8 +149,10 @@
133#define EXYNOS4_PA_SPDIF 0x139B0000 149#define EXYNOS4_PA_SPDIF 0x139B0000
134 150
135#define EXYNOS4_PA_TIMER 0x139D0000 151#define EXYNOS4_PA_TIMER 0x139D0000
152#define EXYNOS5_PA_TIMER 0x12DD0000
136 153
137#define EXYNOS4_PA_SDRAM 0x40000000 154#define EXYNOS4_PA_SDRAM 0x40000000
155#define EXYNOS5_PA_SDRAM 0x40000000
138 156
139/* Compatibiltiy Defines */ 157/* Compatibiltiy Defines */
140 158
@@ -152,7 +170,6 @@
152#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 170#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
153#define S3C_PA_RTC EXYNOS4_PA_RTC 171#define S3C_PA_RTC EXYNOS4_PA_RTC
154#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 172#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
155#define S3C_PA_UART EXYNOS4_PA_UART
156#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 173#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
157#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 174#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
158#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 175#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
@@ -181,15 +198,18 @@
181 198
182/* Compatibility UART */ 199/* Compatibility UART */
183 200
184#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 201#define EXYNOS4_PA_UART0 0x13800000
202#define EXYNOS4_PA_UART1 0x13810000
203#define EXYNOS4_PA_UART2 0x13820000
204#define EXYNOS4_PA_UART3 0x13830000
205#define EXYNOS4_SZ_UART SZ_256
185 206
186#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) 207#define EXYNOS5_PA_UART0 0x12C00000
187#define S5P_PA_UART0 S5P_PA_UART(0) 208#define EXYNOS5_PA_UART1 0x12C10000
188#define S5P_PA_UART1 S5P_PA_UART(1) 209#define EXYNOS5_PA_UART2 0x12C20000
189#define S5P_PA_UART2 S5P_PA_UART(2) 210#define EXYNOS5_PA_UART3 0x12C30000
190#define S5P_PA_UART3 S5P_PA_UART(3) 211#define EXYNOS5_SZ_UART SZ_256
191#define S5P_PA_UART4 S5P_PA_UART(4)
192 212
193#define S5P_SZ_UART SZ_256 213#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
194 214
195#endif /* __ASM_ARCH_MAP_H */ 215#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe9482..e141c1fd68d 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,309 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <mach/map.h> 17#include <mach/map.h>
18 18
19#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 19#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
20 20
21#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) 21#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
22#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) 22#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
23#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) 23#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
24 24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) 25#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 26#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
27#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) 27#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
28 28
29#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) 29#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
30#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) 30#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
31 31
32#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 32#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
33#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 33#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
34#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 34#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
35#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) 35#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
36 36
37#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 37#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
38#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 38#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
39#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 39#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
40#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) 40#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
41#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) 41#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
42#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) 42#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
43#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 43#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
44#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 44#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) 45#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 46#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 47#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 48#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
49 49
50#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 50#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
51#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 51#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
52#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) 52#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
53#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) 53#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
54#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) 54#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
55#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) 55#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
56#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 56#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
57#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 57#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
58 58
59#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 59#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
60#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 60#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
61#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) 61#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
62#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) 62#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
63#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) 63#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
64#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 64#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
65#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 65#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
66#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) 66#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
67#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 67#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
68#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 68#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
69#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) 69#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
70#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) 70#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
71#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) 71#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
72#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) 72#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
73#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) 73#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
74#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) 74#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
75#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 75#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
76#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 76#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
77#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) 77#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
78 78
79#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 79#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
80 80#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
81#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) 81
82#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 82#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
83#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) 83#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
84#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) 84#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
85#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) 85#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
86#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ 86#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
87 S5P_CLKREG(0x0C930) : \ 87#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
88 S5P_CLKREG(0x04930)) 88 EXYNOS_CLKREG(0x0C930) : \
89#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) 89 EXYNOS_CLKREG(0x04930))
90#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) 90#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
91#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 91#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
92#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 92#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
93#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) 93#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
94#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 94#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
95#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ 95#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
96 S5P_CLKREG(0x0C960) : \ 96#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
97 S5P_CLKREG(0x08960)) 97 EXYNOS_CLKREG(0x0C960) : \
98#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) 98 EXYNOS_CLKREG(0x08960))
99#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) 99#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
100#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) 100#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
101 101#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
102#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) 102
103#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) 103#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
104#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) 104#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
105#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) 105#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
106#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) 106#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
107#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) 107#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
108 108#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
109#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 109#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
110#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ 110
111 S5P_CLKREG(0x14004) : \ 111#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
112 S5P_CLKREG(0x10008)) 112#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
113#define S5P_APLL_CON0 S5P_CLKREG(0x14100) 113
114#define S5P_APLL_CON1 S5P_CLKREG(0x14104) 114#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
115#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ 115#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
116 S5P_CLKREG(0x14108) : \ 116 EXYNOS_CLKREG(0x14004) : \
117 S5P_CLKREG(0x10108)) 117 EXYNOS_CLKREG(0x10008))
118#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ 118#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
119 S5P_CLKREG(0x1410C) : \ 119#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
120 S5P_CLKREG(0x1010C)) 120#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
121 121 EXYNOS_CLKREG(0x14108) : \
122#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) 122 EXYNOS_CLKREG(0x10108))
123#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 123#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
124 124 EXYNOS_CLKREG(0x1410C) : \
125#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) 125 EXYNOS_CLKREG(0x1010C))
126#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) 126
127#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) 127#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
128#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) 128#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
129 129
130#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 130#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
131#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) 131#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
132 132#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
133#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ 133#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
134 134
135#define S5P_APLLCON0_ENABLE_SHIFT (31) 135#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
136#define S5P_APLLCON0_LOCKED_SHIFT (29) 136#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
137#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 137
138#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 138#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
139 139
140#define S5P_EPLLCON0_ENABLE_SHIFT (31) 140#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
141#define S5P_EPLLCON0_LOCKED_SHIFT (29) 141#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
142 142#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
143#define S5P_VPLLCON0_ENABLE_SHIFT (31) 143#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
144#define S5P_VPLLCON0_LOCKED_SHIFT (29) 144
145 145#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
146#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 146#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
147#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 147
148 148#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
149#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) 149#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
150#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) 150
151#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) 151#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
152#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) 152#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
153#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) 153
154#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) 154#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
155#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) 155#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
156#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) 156#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
157#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) 157#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
158#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) 158#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
159#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) 159#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
160#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) 160#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
161#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) 161#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
162#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) 162#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
163 163#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
164#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) 164#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
165#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) 165#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
166#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) 166#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
167#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) 167#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
168#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) 168#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
169#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) 169#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
170#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) 170
171#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) 171#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
172#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) 172#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
173#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) 173#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
174#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) 174#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
175#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) 175#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
176#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) 176#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
177#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) 177
178#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) 178#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
179#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) 179#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
180 180#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
181#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) 181#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
182#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) 182#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
183#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) 183#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
184#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) 184#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
185#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) 185#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
186#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) 186#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
187#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) 187#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
188#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) 188#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
189#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) 189#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
190#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) 190#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
191 191#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
192#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) 192#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
193#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) 193#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
194#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 194
195#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 195#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
196#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
197#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
198#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
199#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
200#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
201#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
202#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
203#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
204#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
205#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
206#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
207
208#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
209#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
210
211#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
212#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
213#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
214#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
215#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
216#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
217#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
218#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
219#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
220#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
221#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
222#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
223#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
224#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
225
226#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
227#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
228#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
229#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
230
231#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
232#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
233#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
234#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
235#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
236#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
237#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
238#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
196 239
197/* Only for EXYNOS4210 */ 240/* Only for EXYNOS4210 */
198 241
199#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 242#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
200#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) 243#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
201#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) 244#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
202#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) 245#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
246
247/* Only for EXYNOS4212 */
248
249#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
250
251#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
252
253#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
254#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
255
256/* For EXYNOS5250 */
257
258#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
259#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
260#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
261#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
262#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
263
264#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
265
266#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
267
268#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
269#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
270#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
271#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
272#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
273#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
274
275#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
276#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
277#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
278#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
279#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
280#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
281
282#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
283#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
284#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
285#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
286#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
287
288#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
289#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
290#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
291#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
292#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
293#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
294#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
295#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
296#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
297#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
298
299#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
300#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
301#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
302#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
303#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
304#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
305#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
306#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
307#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
308#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
309
310#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
311#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
312#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
313
314#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
315
316#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
203 317
204/* Compatibility defines and inclusion */ 318/* Compatibility defines and inclusion */
205 319
206#include <mach/regs-pmu.h> 320#include <mach/regs-pmu.h>
207 321
208#define S5P_EPLL_CON S5P_EPLL_CON0 322#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
209 323
210#endif /* __ASM_ARCH_REGS_CLOCK_H */ 324#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a..e4b5b60dcb8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
20#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
21#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
22#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
23#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
24
25#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
26
27/* compatibility for plat-s5p/irq-pm.c */
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) 28#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) 29#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21 30
@@ -28,15 +37,4 @@
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) 37#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) 38#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30 39
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */ 40#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fe..4c53f38b5a9 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) 31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
32 32
33#define S5P_SWRESET S5P_PMUREG(0x0400) 33#define S5P_SWRESET S5P_PMUREG(0x0400)
34#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
34 35
35#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 36#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 37#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9ac..493f4f365dd 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - uncompress code 5 * EXYNOS - uncompress code
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 12#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__ 13#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15 14
15#include <asm/mach-types.h>
16
16#include <mach/map.h> 17#include <mach/map.h>
18
19volatile u8 *uart_base;
20
17#include <plat/uncompress.h> 21#include <plat/uncompress.h>
18 22
19static void arch_detect_cpu(void) 23static void arch_detect_cpu(void)
20{ 24{
21 /* we do not need to do any cpu detection here at the moment. */ 25 if (machine_is_smdk5250())
26 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
27 else
28 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
22 29
23 /* 30 /*
24 * For preventing FIFO overrun or infinite loop of UART console, 31 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e6b02fdf1b0..8245f1c761d 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -37,13 +37,13 @@
37 * data from the device tree. 37 * data from the device tree.
38 */ 38 */
39static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { 39static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, 40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
41 "exynos4210-uart.0", NULL), 41 "exynos4210-uart.0", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, 42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
43 "exynos4210-uart.1", NULL), 43 "exynos4210-uart.1", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, 44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
45 "exynos4210-uart.2", NULL), 45 "exynos4210-uart.2", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, 46 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
47 "exynos4210-uart.3", NULL), 47 "exynos4210-uart.3", NULL),
48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), 48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
49 "exynos4-sdhci.0", NULL), 49 "exynos4-sdhci.0", NULL),
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 00000000000..0d26f50081a
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
1/*
2 * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/of_platform.h>
13#include <linux/serial_core.h>
14
15#include <asm/mach/arch.h>
16#include <asm/hardware/gic.h>
17#include <mach/map.h>
18
19#include <plat/cpu.h>
20#include <plat/regs-serial.h>
21
22#include "common.h"
23
24/*
25 * The following lookup table is used to override device names when devices
26 * are registered from device tree. This is temporarily added to enable
27 * device tree support addition for the EXYNOS5 architecture.
28 *
29 * For drivers that require platform data to be provided from the machine
30 * file, a platform data pointer can also be supplied along with the
31 * devices names. Usually, the platform data elements that cannot be parsed
32 * from the device tree by the drivers (example: function pointers) are
33 * supplied. But it should be noted that this is a temporary mechanism and
34 * at some point, the drivers should be capable of parsing all the platform
35 * data from the device tree.
36 */
37static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
39 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
41 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
47 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
48 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
49 {},
50};
51
52static void __init exynos5250_dt_map_io(void)
53{
54 exynos_init_io(NULL, 0);
55 s3c24xx_init_clocks(24000000);
56}
57
58static void __init exynos5250_dt_machine_init(void)
59{
60 of_platform_populate(NULL, of_default_bus_match_table,
61 exynos5250_auxdata_lookup, NULL);
62}
63
64static char const *exynos5250_dt_compat[] __initdata = {
65 "samsung,exynos5250",
66 NULL
67};
68
69DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
70 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
71 .init_irq = exynos5_init_irq,
72 .map_io = exynos5250_dt_map_io,
73 .handle_irq = gic_handle_irq,
74 .init_machine = exynos5250_dt_machine_init,
75 .timer = &exynos4_timer,
76 .dt_compat = exynos5250_dt_compat,
77 .restart = exynos5_restart,
78MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 0679b8ad2d1..3ec3ccf9f35 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -412,7 +412,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
412 { MAX8997_BUCK7, &max8997_buck7_data }, 412 { MAX8997_BUCK7, &max8997_buck7_data },
413}; 413};
414 414
415struct max8997_platform_data __initdata origen_max8997_pdata = { 415static struct max8997_platform_data __initdata origen_max8997_pdata = {
416 .num_regulators = ARRAY_SIZE(origen_max8997_regulators), 416 .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
417 .regulators = origen_max8997_regulators, 417 .regulators = origen_max8997_regulators,
418 418
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 0fc65ffde8f..e00d8e26d52 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -997,7 +997,7 @@ static void __init universal_map_io(void)
997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 997 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
998} 998}
999 999
1000void s5p_tv_setup(void) 1000static void s5p_tv_setup(void)
1001{ 1001{
1002 /* direct HPD to HDMI chip */ 1002 /* direct HPD to HDMI chip */
1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); 1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527d091..1016515dc9a 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -258,7 +258,10 @@ static void exynos4_clockevent_init(void)
258 mct_comp_device.cpumask = cpumask_of(0); 258 mct_comp_device.cpumask = cpumask_of(0);
259 clockevents_register_device(&mct_comp_device); 259 clockevents_register_device(&mct_comp_device);
260 260
261 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq); 261 if (soc_is_exynos5250())
262 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
263 else
264 setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
262} 265}
263 266
264#ifdef CONFIG_LOCAL_TIMERS 267#ifdef CONFIG_LOCAL_TIMERS
@@ -406,16 +409,16 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
406 if (mct_int_type == MCT_INT_SPI) { 409 if (mct_int_type == MCT_INT_SPI) {
407 if (cpu == 0) { 410 if (cpu == 0) {
408 mct_tick0_event_irq.dev_id = mevt; 411 mct_tick0_event_irq.dev_id = mevt;
409 evt->irq = IRQ_MCT_L0; 412 evt->irq = EXYNOS4_IRQ_MCT_L0;
410 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 413 setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
411 } else { 414 } else {
412 mct_tick1_event_irq.dev_id = mevt; 415 mct_tick1_event_irq.dev_id = mevt;
413 evt->irq = IRQ_MCT_L1; 416 evt->irq = EXYNOS4_IRQ_MCT_L1;
414 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 417 setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
415 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); 418 irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
416 } 419 }
417 } else { 420 } else {
418 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0); 421 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
419 } 422 }
420} 423}
421 424
@@ -437,7 +440,7 @@ void local_timer_stop(struct clock_event_device *evt)
437 else 440 else
438 remove_irq(evt->irq, &mct_tick1_event_irq); 441 remove_irq(evt->irq, &mct_tick1_event_irq);
439 else 442 else
440 disable_percpu_irq(IRQ_MCT_LOCALTIMER); 443 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
441} 444}
442#endif /* CONFIG_LOCAL_TIMERS */ 445#endif /* CONFIG_LOCAL_TIMERS */
443 446
@@ -452,11 +455,11 @@ static void __init exynos4_timer_resources(void)
452 if (mct_int_type == MCT_INT_PPI) { 455 if (mct_int_type == MCT_INT_PPI) {
453 int err; 456 int err;
454 457
455 err = request_percpu_irq(IRQ_MCT_LOCALTIMER, 458 err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
456 exynos4_mct_tick_isr, "MCT", 459 exynos4_mct_tick_isr, "MCT",
457 &percpu_mct_tick); 460 &percpu_mct_tick);
458 WARN(err, "MCT: can't request IRQ %d (%d)\n", 461 WARN(err, "MCT: can't request IRQ %d (%d)\n",
459 IRQ_MCT_LOCALTIMER, err); 462 EXYNOS_IRQ_MCT_LOCALTIMER, err);
460 } 463 }
461#endif /* CONFIG_LOCAL_TIMERS */ 464#endif /* CONFIG_LOCAL_TIMERS */
462} 465}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a1eb6..36c3984aaa4 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
166 void __iomem *scu_base = scu_base_addr(); 166 void __iomem *scu_base = scu_base_addr();
167 unsigned int i, ncores; 167 unsigned int i, ncores;
168 168
169 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 169 if (soc_is_exynos5250())
170 ncores = 2;
171 else
172 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
170 173
171 /* sanity check */ 174 /* sanity check */
172 if (ncores > nr_cpu_ids) { 175 if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
183 186
184void __init platform_smp_prepare_cpus(unsigned int max_cpus) 187void __init platform_smp_prepare_cpus(unsigned int max_cpus)
185{ 188{
186 189 if (!soc_is_exynos5250())
187 scu_enable(scu_base_addr()); 190 scu_enable(scu_base_addr());
188 191
189 /* 192 /*
190 * Write the address of secondary startup into the 193 * Write the address of secondary startup into the
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e1901305177..f105bd2b676 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
38#include <mach/pmu.h> 38#include <mach/pmu.h>
39 39
40static struct sleep_save exynos4_set_clksrc[] = { 40static struct sleep_save exynos4_set_clksrc[] = {
41 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, 41 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
42 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, 42 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
43 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, 43 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
44 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 44 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
45 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 45 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
46 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 46 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
47 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
48 { .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, 48 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 49 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
50}; 50};
51 51
52static struct sleep_save exynos4210_set_clksrc[] = { 52static struct sleep_save exynos4210_set_clksrc[] = {
53 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, 53 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
54}; 54};
55 55
56static struct sleep_save exynos4_epll_save[] = { 56static struct sleep_save exynos4_epll_save[] = {
57 SAVE_ITEM(S5P_EPLL_CON0), 57 SAVE_ITEM(EXYNOS4_EPLL_CON0),
58 SAVE_ITEM(S5P_EPLL_CON1), 58 SAVE_ITEM(EXYNOS4_EPLL_CON1),
59}; 59};
60 60
61static struct sleep_save exynos4_vpll_save[] = { 61static struct sleep_save exynos4_vpll_save[] = {
62 SAVE_ITEM(S5P_VPLL_CON0), 62 SAVE_ITEM(EXYNOS4_VPLL_CON0),
63 SAVE_ITEM(S5P_VPLL_CON1), 63 SAVE_ITEM(EXYNOS4_VPLL_CON1),
64}; 64};
65 65
66static struct sleep_save exynos4_core_save[] = { 66static struct sleep_save exynos4_core_save[] = {
@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void)
239 locktime = (3000 / pll_in_rate) * p_div; 239 locktime = (3000 / pll_in_rate) * p_div;
240 lockcnt = locktime * 10000 / (10000 / pll_in_rate); 240 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
241 241
242 __raw_writel(lockcnt, S5P_EPLL_LOCK); 242 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
243 243
244 s3c_pm_do_restore_core(exynos4_epll_save, 244 s3c_pm_do_restore_core(exynos4_epll_save,
245 ARRAY_SIZE(exynos4_epll_save)); 245 ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void)
257 locktime = 750; 257 locktime = 750;
258 lockcnt = locktime * 10000 / (10000 / pll_in_rate); 258 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
259 259
260 __raw_writel(lockcnt, S5P_VPLL_LOCK); 260 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
261 261
262 s3c_pm_do_restore_core(exynos4_vpll_save, 262 s3c_pm_do_restore_core(exynos4_vpll_save,
263 ARRAY_SIZE(exynos4_vpll_save)); 263 ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void)
268 268
269 do { 269 do {
270 if (epll_wait) { 270 if (epll_wait) {
271 pll_con = __raw_readl(S5P_EPLL_CON0); 271 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
272 if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) 272 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
273 epll_wait = 0; 273 epll_wait = 0;
274 } 274 }
275 275
276 if (vpll_wait) { 276 if (vpll_wait) {
277 pll_con = __raw_readl(S5P_VPLL_CON0); 277 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
278 if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) 278 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
279 vpll_wait = 0; 279 vpll_wait = 0;
280 } 280 }
281 } while (epll_wait || vpll_wait); 281 } while (epll_wait || vpll_wait);
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd17c38..b90d94c17f7 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c0.c 2 * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 3 * http://www.samsung.com/
6 * 4 *
7 * I2C0 GPIO configuration. 5 * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
18#include <linux/gpio.h> 16#include <linux/gpio.h>
19#include <plat/iic.h> 17#include <plat/iic.h>
20#include <plat/gpio-cfg.h> 18#include <plat/gpio-cfg.h>
19#include <plat/cpu.h>
21 20
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 22{
23 if (soc_is_exynos5250())
24 /* will be implemented with gpio function */
25 return;
26
24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, 27 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 29}
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 2667f52e3b0..9e3b90df32e 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -61,7 +61,7 @@
61 */ 61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) 62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) 63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) 64#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) 65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) 66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) 67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 4eae566dfdc..c74de01ab5b 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
118 .event_group = &lpc32xx_event_pin_regs, 118 .event_group = &lpc32xx_event_pin_regs,
119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, 119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
120 }, 120 },
121 [IRQ_LPC32XX_GPI_28] = {
122 .event_group = &lpc32xx_event_pin_regs,
123 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
124 },
121 [IRQ_LPC32XX_GPIO_00] = { 125 [IRQ_LPC32XX_GPIO_00] = {
122 .event_group = &lpc32xx_event_int_regs, 126 .event_group = &lpc32xx_event_int_regs,
123 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, 127 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
@@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
305 309
306 if (state) 310 if (state)
307 eventreg |= lpc32xx_events[d->irq].mask; 311 eventreg |= lpc32xx_events[d->irq].mask;
308 else 312 else {
309 eventreg &= ~lpc32xx_events[d->irq].mask; 313 eventreg &= ~lpc32xx_events[d->irq].mask;
310 314
315 /*
316 * When disabling the wakeup, clear the latched
317 * event
318 */
319 __raw_writel(lpc32xx_events[d->irq].mask,
320 lpc32xx_events[d->irq].
321 event_group->rawstat_reg);
322 }
323
311 __raw_writel(eventreg, 324 __raw_writel(eventreg,
312 lpc32xx_events[d->irq].event_group->enab_reg); 325 lpc32xx_events[d->irq].event_group->enab_reg);
313 326
@@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
380 393
381 /* Setup SIC1 */ 394 /* Setup SIC1 */
382 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); 395 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
383 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); 396 __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
384 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); 397 __raw_writel(SIC1_ATR_DEFAULT,
398 LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
385 399
386 /* Setup SIC2 */ 400 /* Setup SIC2 */
387 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); 401 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
388 __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); 402 __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
389 __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); 403 __raw_writel(SIC2_ATR_DEFAULT,
404 LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
390 405
391 /* Configure supported IRQ's */ 406 /* Configure supported IRQ's */
392 for (i = 0; i < NR_IRQS; i++) { 407 for (i = 0; i < NR_IRQS; i++) {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 429cfdbb2b3..f2735281616 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -88,6 +88,7 @@ struct uartinit {
88 char *uart_ck_name; 88 char *uart_ck_name;
89 u32 ck_mode_mask; 89 u32 ck_mode_mask;
90 void __iomem *pdiv_clk_reg; 90 void __iomem *pdiv_clk_reg;
91 resource_size_t mapbase;
91}; 92};
92 93
93static struct uartinit uartinit_data[] __initdata = { 94static struct uartinit uartinit_data[] __initdata = {
@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
97 .ck_mode_mask = 98 .ck_mode_mask =
98 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), 99 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
99 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, 100 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
101 .mapbase = LPC32XX_UART5_BASE,
100 }, 102 },
101#endif 103#endif
102#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT 104#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
105 .ck_mode_mask = 107 .ck_mode_mask =
106 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), 108 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
107 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, 109 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
110 .mapbase = LPC32XX_UART3_BASE,
108 }, 111 },
109#endif 112#endif
110#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT 113#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
113 .ck_mode_mask = 116 .ck_mode_mask =
114 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), 117 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
115 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, 118 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
119 .mapbase = LPC32XX_UART4_BASE,
116 }, 120 },
117#endif 121#endif
118#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT 122#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
121 .ck_mode_mask = 125 .ck_mode_mask =
122 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), 126 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
123 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, 127 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
128 .mapbase = LPC32XX_UART6_BASE,
124 }, 129 },
125#endif 130#endif
126}; 131};
@@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
165 170
166 /* pre-UART clock divider set to 1 */ 171 /* pre-UART clock divider set to 1 */
167 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); 172 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
173
174 /*
175 * Force a flush of the RX FIFOs to work around a
176 * HW bug
177 */
178 puart = uartinit_data[i].mapbase;
179 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
180 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
181 j = LPC32XX_SUART_FIFO_SIZE;
182 while (j--)
183 tmp = __raw_readl(
184 LPC32XX_UART_DLL_FIFO(puart));
185 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
168 } 186 }
169 187
170 /* This needs to be done after all UART clocks are setup */ 188 /* This needs to be done after all UART clocks are setup */
171 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); 189 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
172 for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { 190 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
173 /* Force a flush of the RX FIFOs to work around a HW bug */ 191 /* Force a flush of the RX FIFOs to work around a HW bug */
174 puart = serial_std_platform_data[i].mapbase; 192 puart = serial_std_platform_data[i].mapbase;
175 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); 193 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 17cb7606012..3588a558415 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -17,7 +17,6 @@
17#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/gpio.h>
21 20
22#include <asm/mach-types.h> 21#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 7bc17eaa12e..ada1213982b 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -24,7 +24,6 @@
24#include <mach/dma.h> 24#include <mach/dma.h>
25#include <mach/devices.h> 25#include <mach/devices.h>
26#include <mach/mfp.h> 26#include <mach/mfp.h>
27#include <linux/platform_device.h>
28#include <linux/dma-mapping.h> 27#include <linux/dma-mapping.h>
29#include <mach/pxa168.h> 28#include <mach/pxa168.h>
30 29
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 8e3b5af04a5..bc97170125b 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -12,7 +12,6 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/smc91x.h> 14#include <linux/smc91x.h>
15#include <linux/gpio.h>
16 15
17#include <asm/mach-types.h> 16#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 309369ea697..be2002f42de 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -416,13 +416,13 @@ static void __init innovator_init(void)
416#ifdef CONFIG_ARCH_OMAP15XX 416#ifdef CONFIG_ARCH_OMAP15XX
417 if (cpu_is_omap1510()) { 417 if (cpu_is_omap1510()) {
418 omap1_usb_init(&innovator1510_usb_config); 418 omap1_usb_init(&innovator1510_usb_config);
419 innovator_config[1].data = &innovator1510_lcd_config; 419 innovator_config[0].data = &innovator1510_lcd_config;
420 } 420 }
421#endif 421#endif
422#ifdef CONFIG_ARCH_OMAP16XX 422#ifdef CONFIG_ARCH_OMAP16XX
423 if (cpu_is_omap1610()) { 423 if (cpu_is_omap1610()) {
424 omap1_usb_init(&h2_usb_config); 424 omap1_usb_init(&h2_usb_config);
425 innovator_config[1].data = &innovator1610_lcd_config; 425 innovator_config[0].data = &innovator1610_lcd_config;
426 } 426 }
427#endif 427#endif
428 omap_board_config = innovator_config; 428 omap_board_config = innovator_config;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d965da45160..e20c8ab80b0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -364,8 +364,8 @@ config OMAP3_SDRC_AC_TIMING
364 going on could result in system crashes; 364 going on could result in system crashes;
365 365
366config OMAP4_ERRATA_I688 366config OMAP4_ERRATA_I688
367 bool "OMAP4 errata: Async Bridge Corruption (BROKEN)" 367 bool "OMAP4 errata: Async Bridge Corruption"
368 depends on ARCH_OMAP4 && BROKEN 368 depends on ARCH_OMAP4
369 select ARCH_HAS_BARRIERS 369 select ARCH_HAS_BARRIERS
370 help 370 help
371 If a data is stalled inside asynchronous bridge because of back 371 If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 42a4d11fad2..67226271760 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -371,7 +371,11 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
371 else 371 else
372 *openp = 0; 372 *openp = 0;
373 373
374#ifdef CONFIG_MMC_OMAP
374 omap_mmc_notify_cover_event(mmc_device, index, *openp); 375 omap_mmc_notify_cover_event(mmc_device, index, *openp);
376#else
377 pr_warn("MMC: notify cover event not available\n");
378#endif
375} 379}
376 380
377static int n8x0_mmc_late_init(struct device *dev) 381static int n8x0_mmc_late_init(struct device *dev)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c775bead149..c877236a844 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -381,7 +381,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
381 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI"); 381 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
382 382
383 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ 383 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
384 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; 384 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
385 385
386 platform_device_register(&leds_gpio); 386 platform_device_register(&leds_gpio);
387 387
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index febffde2ff1..7e9338e8d68 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -132,6 +132,7 @@ void omap3_map_io(void);
132void am33xx_map_io(void); 132void am33xx_map_io(void);
133void omap4_map_io(void); 133void omap4_map_io(void);
134void ti81xx_map_io(void); 134void ti81xx_map_io(void);
135void omap_barriers_init(void);
135 136
136/** 137/**
137 * omap_test_timeout - busy-loop, testing a condition 138 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cfdbb86bc84..72e018b9b26 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -65,7 +65,6 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
65 struct timespec ts_preidle, ts_postidle, ts_idle; 65 struct timespec ts_preidle, ts_postidle, ts_idle;
66 u32 cpu1_state; 66 u32 cpu1_state;
67 int idle_time; 67 int idle_time;
68 int new_state_idx;
69 int cpu_id = smp_processor_id(); 68 int cpu_id = smp_processor_id();
70 69
71 /* Used to keep track of the total time in idle */ 70 /* Used to keep track of the total time in idle */
@@ -84,8 +83,8 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
84 */ 83 */
85 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 84 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
86 if (cpu1_state != PWRDM_POWER_OFF) { 85 if (cpu1_state != PWRDM_POWER_OFF) {
87 new_state_idx = drv->safe_state_index; 86 index = drv->safe_state_index;
88 cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]); 87 cx = cpuidle_get_statedata(&dev->states_usage[index]);
89 } 88 }
90 89
91 if (index > 0) 90 if (index > 0)
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 997033129d2..bbb870c04a5 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -19,6 +19,8 @@
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/smsc911x.h> 21#include <linux/smsc911x.h>
22#include <linux/regulator/fixed.h>
23#include <linux/regulator/machine.h>
22 24
23#include <plat/board.h> 25#include <plat/board.h>
24#include <plat/gpmc.h> 26#include <plat/gpmc.h>
@@ -42,6 +44,50 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
42 .flags = SMSC911X_USE_16BIT, 44 .flags = SMSC911X_USE_16BIT,
43}; 45};
44 46
47static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
48 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
49 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
50};
51
52/* Generic regulator definition to satisfy smsc911x */
53static struct regulator_init_data gpmc_smsc911x_reg_init_data = {
54 .constraints = {
55 .min_uV = 3300000,
56 .max_uV = 3300000,
57 .valid_modes_mask = REGULATOR_MODE_NORMAL
58 | REGULATOR_MODE_STANDBY,
59 .valid_ops_mask = REGULATOR_CHANGE_MODE
60 | REGULATOR_CHANGE_STATUS,
61 },
62 .num_consumer_supplies = ARRAY_SIZE(gpmc_smsc911x_supply),
63 .consumer_supplies = gpmc_smsc911x_supply,
64};
65
66static struct fixed_voltage_config gpmc_smsc911x_fixed_reg_data = {
67 .supply_name = "gpmc_smsc911x",
68 .microvolts = 3300000,
69 .gpio = -EINVAL,
70 .startup_delay = 0,
71 .enable_high = 0,
72 .enabled_at_boot = 1,
73 .init_data = &gpmc_smsc911x_reg_init_data,
74};
75
76/*
77 * Platform device id of 42 is a temporary fix to avoid conflicts
78 * with other reg-fixed-voltage devices. The real fix should
79 * involve the driver core providing a way of dynamically
80 * assigning a unique id on registration for platform devices
81 * in the same name space.
82 */
83static struct platform_device gpmc_smsc911x_regulator = {
84 .name = "reg-fixed-voltage",
85 .id = 42,
86 .dev = {
87 .platform_data = &gpmc_smsc911x_fixed_reg_data,
88 },
89};
90
45/* 91/*
46 * Initialize smsc911x device connected to the GPMC. Note that we 92 * Initialize smsc911x device connected to the GPMC. Note that we
47 * assume that pin multiplexing is done in the board-*.c file, 93 * assume that pin multiplexing is done in the board-*.c file,
@@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
55 101
56 gpmc_cfg = board_data; 102 gpmc_cfg = board_data;
57 103
104 ret = platform_device_register(&gpmc_smsc911x_regulator);
105 if (ret < 0) {
106 pr_err("Unable to register smsc911x regulators: %d\n", ret);
107 return;
108 }
109
58 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { 110 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
59 pr_err("Failed to request GPMC mem region\n"); 111 pr_err("Failed to request GPMC mem region\n");
60 return; 112 return;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index b40c2889529..19dd1657245 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -428,6 +428,7 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
428 return 0; 428 return 0;
429} 429}
430 430
431static int omap_hsmmc_done;
431#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 432#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
432 433
433void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) 434void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
@@ -491,6 +492,11 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
491{ 492{
492 u32 reg; 493 u32 reg;
493 494
495 if (omap_hsmmc_done)
496 return;
497
498 omap_hsmmc_done = 1;
499
494 if (!cpu_is_omap44xx()) { 500 if (!cpu_is_omap44xx()) {
495 if (cpu_is_omap2430()) { 501 if (cpu_is_omap2430()) {
496 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 502 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index eb50c29fb64..fb11b44fbde 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -307,6 +307,7 @@ void __init omapam33xx_map_common_io(void)
307void __init omap44xx_map_common_io(void) 307void __init omap44xx_map_common_io(void)
308{ 308{
309 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 309 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
310 omap_barriers_init();
310} 311}
311#endif 312#endif
312 313
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 609ea2ded7e..2cc1aa004b9 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -281,8 +281,16 @@ static struct omap_mbox mbox_iva_info = {
281 .ops = &omap2_mbox_ops, 281 .ops = &omap2_mbox_ops,
282 .priv = &omap2_mbox_iva_priv, 282 .priv = &omap2_mbox_iva_priv,
283}; 283};
284#endif
284 285
285struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL }; 286#ifdef CONFIG_ARCH_OMAP2
287struct omap_mbox *omap2_mboxes[] = {
288 &mbox_dsp_info,
289#ifdef CONFIG_SOC_OMAP2420
290 &mbox_iva_info,
291#endif
292 NULL
293};
286#endif 294#endif
287 295
288#if defined(CONFIG_ARCH_OMAP4) 296#if defined(CONFIG_ARCH_OMAP4)
@@ -412,7 +420,8 @@ static void __exit omap2_mbox_exit(void)
412 platform_driver_unregister(&omap2_mbox_driver); 420 platform_driver_unregister(&omap2_mbox_driver);
413} 421}
414 422
415module_init(omap2_mbox_init); 423/* must be ready before omap3isp is probed */
424subsys_initcall(omap2_mbox_init);
416module_exit(omap2_mbox_exit); 425module_exit(omap2_mbox_exit);
417 426
418MODULE_LICENSE("GPL v2"); 427MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index fb8bc9fa43b..611a0e3d54c 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -218,7 +218,7 @@ static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
218 return -ENODEV; 218 return -ENODEV;
219} 219}
220 220
221static int __init 221static int
222omap_mux_get_by_name(const char *muxname, 222omap_mux_get_by_name(const char *muxname,
223 struct omap_mux_partition **found_partition, 223 struct omap_mux_partition **found_partition,
224 struct omap_mux **found_mux) 224 struct omap_mux **found_mux)
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 40a8fbc07e4..ebc59509131 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -24,6 +24,7 @@
24 24
25#include <plat/irqs.h> 25#include <plat/irqs.h>
26#include <plat/sram.h> 26#include <plat/sram.h>
27#include <plat/omap-secure.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <mach/omap-wakeupgen.h> 30#include <mach/omap-wakeupgen.h>
@@ -43,6 +44,9 @@ static void __iomem *sar_ram_base;
43 44
44void __iomem *dram_sync, *sram_sync; 45void __iomem *dram_sync, *sram_sync;
45 46
47static phys_addr_t paddr;
48static u32 size;
49
46void omap_bus_sync(void) 50void omap_bus_sync(void)
47{ 51{
48 if (dram_sync && sram_sync) { 52 if (dram_sync && sram_sync) {
@@ -52,18 +56,20 @@ void omap_bus_sync(void)
52 } 56 }
53} 57}
54 58
55static int __init omap_barriers_init(void) 59/* Steal one page physical memory for barrier implementation */
60int __init omap_barrier_reserve_memblock(void)
56{ 61{
57 struct map_desc dram_io_desc[1];
58 phys_addr_t paddr;
59 u32 size;
60
61 if (!cpu_is_omap44xx())
62 return -ENODEV;
63 62
64 size = ALIGN(PAGE_SIZE, SZ_1M); 63 size = ALIGN(PAGE_SIZE, SZ_1M);
65 paddr = arm_memblock_steal(size, SZ_1M); 64 paddr = arm_memblock_steal(size, SZ_1M);
66 65
66 return 0;
67}
68
69void __init omap_barriers_init(void)
70{
71 struct map_desc dram_io_desc[1];
72
67 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; 73 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
68 dram_io_desc[0].pfn = __phys_to_pfn(paddr); 74 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
69 dram_io_desc[0].length = size; 75 dram_io_desc[0].length = size;
@@ -75,9 +81,10 @@ static int __init omap_barriers_init(void)
75 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", 81 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
76 (long long) paddr, dram_io_desc[0].virtual); 82 (long long) paddr, dram_io_desc[0].virtual);
77 83
78 return 0;
79} 84}
80core_initcall(omap_barriers_init); 85#else
86void __init omap_barriers_init(void)
87{}
81#endif 88#endif
82 89
83void __init gic_init_irq(void) 90void __init gic_init_irq(void)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 1881fe91514..5a65dd04aa3 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -174,14 +174,17 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
174 freq = clk->rate; 174 freq = clk->rate;
175 clk_put(clk); 175 clk_put(clk);
176 176
177 rcu_read_lock();
177 opp = opp_find_freq_ceil(dev, &freq); 178 opp = opp_find_freq_ceil(dev, &freq);
178 if (IS_ERR(opp)) { 179 if (IS_ERR(opp)) {
180 rcu_read_unlock();
179 pr_err("%s: unable to find boot up OPP for vdd_%s\n", 181 pr_err("%s: unable to find boot up OPP for vdd_%s\n",
180 __func__, vdd_name); 182 __func__, vdd_name);
181 goto exit; 183 goto exit;
182 } 184 }
183 185
184 bootup_volt = opp_get_voltage(opp); 186 bootup_volt = opp_get_voltage(opp);
187 rcu_read_unlock();
185 if (!bootup_volt) { 188 if (!bootup_volt) {
186 pr_err("%s: unable to find voltage corresponding " 189 pr_err("%s: unable to find voltage corresponding "
187 "to the bootup OPP for vdd_%s\n", __func__, vdd_name); 190 "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 771dc781b74..f51348dafaf 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -486,7 +486,7 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
486void __init usbhs_init(const struct usbhs_omap_board_data *pdata) 486void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
487{ 487{
488 struct omap_hwmod *oh[2]; 488 struct omap_hwmod *oh[2];
489 struct omap_device *od; 489 struct platform_device *pdev;
490 int bus_id = -1; 490 int bus_id = -1;
491 int i; 491 int i;
492 492
@@ -522,11 +522,11 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
522 return; 522 return;
523 } 523 }
524 524
525 od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2, 525 pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
526 (void *)&usbhs_data, sizeof(usbhs_data), 526 (void *)&usbhs_data, sizeof(usbhs_data),
527 omap_uhhtll_latency, 527 omap_uhhtll_latency,
528 ARRAY_SIZE(omap_uhhtll_latency), false); 528 ARRAY_SIZE(omap_uhhtll_latency), false);
529 if (IS_ERR(od)) { 529 if (IS_ERR(pdev)) {
530 pr_err("Could not build hwmod devices %s,%s\n", 530 pr_err("Could not build hwmod devices %s,%s\n",
531 USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME); 531 USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
532 return; 532 return;
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index fb9b62dcf4c..208eef1c048 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -45,6 +45,7 @@
45#include <mach/hx4700.h> 45#include <mach/hx4700.h>
46#include <mach/irda.h> 46#include <mach/irda.h>
47 47
48#include <sound/ak4641.h>
48#include <video/platform_lcd.h> 49#include <video/platform_lcd.h>
49#include <video/w100fb.h> 50#include <video/w100fb.h>
50 51
@@ -765,6 +766,28 @@ static struct i2c_board_info __initdata pi2c_board_info[] = {
765}; 766};
766 767
767/* 768/*
769 * Asahi Kasei AK4641 on I2C
770 */
771
772static struct ak4641_platform_data ak4641_info = {
773 .gpio_power = GPIO27_HX4700_CODEC_ON,
774 .gpio_npdn = GPIO109_HX4700_CODEC_nPDN,
775};
776
777static struct i2c_board_info i2c_board_info[] __initdata = {
778 {
779 I2C_BOARD_INFO("ak4641", 0x12),
780 .platform_data = &ak4641_info,
781 },
782};
783
784static struct platform_device audio = {
785 .name = "hx4700-audio",
786 .id = -1,
787};
788
789
790/*
768 * PCMCIA 791 * PCMCIA
769 */ 792 */
770 793
@@ -790,6 +813,7 @@ static struct platform_device *devices[] __initdata = {
790 &gpio_vbus, 813 &gpio_vbus,
791 &power_supply, 814 &power_supply,
792 &strataflash, 815 &strataflash,
816 &audio,
793 &pcmcia, 817 &pcmcia,
794}; 818};
795 819
@@ -827,6 +851,7 @@ static void __init hx4700_init(void)
827 pxa_set_ficp_info(&ficp_info); 851 pxa_set_ficp_info(&ficp_info);
828 pxa27x_set_i2c_power_info(NULL); 852 pxa27x_set_i2c_power_info(NULL);
829 pxa_set_i2c_info(NULL); 853 pxa_set_i2c_info(NULL);
854 i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
830 i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info)); 855 i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
831 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); 856 pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
832 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); 857 spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 91e4f6c0376..00d6eacab8e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -25,7 +25,6 @@
25#include <linux/suspend.h> 25#include <linux/suspend.h>
26#include <linux/syscore_ops.h> 26#include <linux/syscore_ops.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/gpio.h>
29 28
30#include <asm/mach/map.h> 29#include <asm/mach/map.h>
31#include <asm/suspend.h> 30#include <asm/suspend.h>
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index aed6cbcf386..c1673b3441d 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -22,7 +22,6 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/i2c/pxa-i2c.h> 24#include <linux/i2c/pxa-i2c.h>
25#include <linux/gpio.h>
26 25
27#include <asm/mach/map.h> 26#include <asm/mach/map.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index febc809ed5a..5aded5e6148 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -15,7 +15,6 @@
15#include <linux/i2c.h> 15#include <linux/i2c.h>
16#include <linux/i2c/pxa-i2c.h> 16#include <linux/i2c/pxa-i2c.h>
17#include <linux/mfd/88pm860x.h> 17#include <linux/mfd/88pm860x.h>
18#include <linux/gpio.h>
19 18
20#include <asm/mach-types.h> 19#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8d5168d253a..30989baf7f2 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -168,6 +168,7 @@ struct battery_thresh sharpsl_battery_levels_noac[] = {
168#define MAXCTRL_SEL_SH 4 168#define MAXCTRL_SEL_SH 4
169#define MAXCTRL_STR (1u << 7) 169#define MAXCTRL_STR (1u << 7)
170 170
171extern int max1111_read_channel(int);
171/* 172/*
172 * Read MAX1111 ADC 173 * Read MAX1111 ADC
173 */ 174 */
@@ -177,8 +178,6 @@ int sharpsl_pm_pxa_read_max1111(int channel)
177 if (machine_is_tosa()) 178 if (machine_is_tosa())
178 return 0; 179 return 0;
179 180
180 extern int max1111_read_channel(int);
181
182 /* max1111 accepts channels from 0-3, however, 181 /* max1111 accepts channels from 0-3, however,
183 * it is encoded from 0-7 here in the code. 182 * it is encoded from 0-7 here in the code.
184 */ 183 */
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 34cbdac5152..438f02fe122 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -172,10 +172,9 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
172static unsigned long spitz_charger_wakeup(void) 172static unsigned long spitz_charger_wakeup(void)
173{ 173{
174 unsigned long ret; 174 unsigned long ret;
175 ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT) 175 ret = ((!gpio_get_value(SPITZ_GPIO_KEY_INT)
176 << GPIO_bit(SPITZ_GPIO_KEY_INT)) 176 << GPIO_bit(SPITZ_GPIO_KEY_INT))
177 | (!gpio_get_value(SPITZ_GPIO_SYNC) 177 | gpio_get_value(SPITZ_GPIO_SYNC));
178 << GPIO_bit(SPITZ_GPIO_SYNC));
179 return ret; 178 return ret;
180} 179}
181 180
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 41245a60398..6b21ba107ea 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
162 return (latch_state >> (offset + 16)) & 1; 162 return (latch_state >> (offset + 16)) & 1;
163} 163}
164 164
165struct gpio_chip h1940_latch_gpiochip = { 165static struct gpio_chip h1940_latch_gpiochip = {
166 .base = H1940_LATCH_GPIO(0), 166 .base = H1940_LATCH_GPIO(0),
167 .owner = THIS_MODULE, 167 .owner = THIS_MODULE,
168 .label = "H1940_LATCH", 168 .label = "H1940_LATCH",
@@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
304 { .volt = 3841, .cur = 0, .level = 0}, 304 { .volt = 3841, .cur = 0, .level = 0},
305}; 305};
306 306
307int h1940_bat_init(void) 307static int h1940_bat_init(void)
308{ 308{
309 int ret; 309 int ret;
310 310
@@ -317,17 +317,17 @@ int h1940_bat_init(void)
317 317
318} 318}
319 319
320void h1940_bat_exit(void) 320static void h1940_bat_exit(void)
321{ 321{
322 gpio_free(H1940_LATCH_SM803_ENABLE); 322 gpio_free(H1940_LATCH_SM803_ENABLE);
323} 323}
324 324
325void h1940_enable_charger(void) 325static void h1940_enable_charger(void)
326{ 326{
327 gpio_set_value(H1940_LATCH_SM803_ENABLE, 1); 327 gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
328} 328}
329 329
330void h1940_disable_charger(void) 330static void h1940_disable_charger(void)
331{ 331{
332 gpio_set_value(H1940_LATCH_SM803_ENABLE, 0); 332 gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
333} 333}
@@ -364,7 +364,7 @@ static struct platform_device h1940_battery = {
364 }, 364 },
365}; 365};
366 366
367DEFINE_SPINLOCK(h1940_blink_spin); 367static DEFINE_SPINLOCK(h1940_blink_spin);
368 368
369int h1940_led_blink_set(unsigned gpio, int state, 369int h1940_led_blink_set(unsigned gpio, int state,
370 unsigned long *delay_on, unsigned long *delay_off) 370 unsigned long *delay_on, unsigned long *delay_off)
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 59f54d1d7f8..e01490db099 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -132,12 +132,6 @@ static struct clk hsmmc0_clk = {
132 .ctrlbit = S3C2416_HCLKCON_HSMMC0, 132 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
133}; 133};
134 134
135void __init_or_cpufreq s3c2416_setup_clocks(void)
136{
137 s3c2443_common_setup_clocks(s3c2416_get_pll);
138}
139
140
141static struct clksrc_clk *clksrcs[] __initdata = { 135static struct clksrc_clk *clksrcs[] __initdata = {
142 &hsspi_eplldiv, 136 &hsspi_eplldiv,
143 &hsspi_mux, 137 &hsspi_mux,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index eebe1e72b93..30a44f806e0 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
125 } 125 }
126}; 126};
127 127
128void smdk2416_hsudc_gpio_init(void) 128static void smdk2416_hsudc_gpio_init(void)
129{ 129{
130 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP); 130 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
131 s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE); 131 s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
@@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void)
133 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0); 133 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
134} 134}
135 135
136void smdk2416_hsudc_gpio_uninit(void) 136static void smdk2416_hsudc_gpio_uninit(void)
137{ 137{
138 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1); 138 s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
139 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE); 139 s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
140 s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0)); 140 s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
141} 141}
142 142
143struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = { 143static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
144 .epnum = 9, 144 .epnum = 9,
145 .gpio_init = smdk2416_hsudc_gpio_init, 145 .gpio_init = smdk2416_hsudc_gpio_init,
146 .gpio_uninit = smdk2416_hsudc_gpio_uninit, 146 .gpio_uninit = smdk2416_hsudc_gpio_uninit,
147}; 147};
148 148
149struct s3c_fb_pd_win smdk2416_fb_win[] = { 149static struct s3c_fb_pd_win smdk2416_fb_win[] = {
150 [0] = { 150 [0] = {
151 /* think this is the same as the smdk6410 */ 151 /* think this is the same as the smdk6410 */
152 .win_mode = { 152 .win_mode = {
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 5859e609d28..7365a441cc5 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = {
258 .ramp_time = 5, 258 .ramp_time = 5,
259}; 259};
260 260
261struct pcf50633_platform_data gta02_pcf_pdata = { 261static struct pcf50633_platform_data gta02_pcf_pdata = {
262 .resumers = { 262 .resumers = {
263 [0] = PCF50633_INT1_USBINS | 263 [0] = PCF50633_INT1_USBINS |
264 PCF50633_INT1_USBREM | 264 PCF50633_INT1_USBREM |
@@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = {
404}; 404};
405 405
406 406
407struct platform_device s3c24xx_pwm_device = { 407static struct platform_device s3c24xx_pwm_device = {
408 .name = "s3c24xx_pwm", 408 .name = "s3c24xx_pwm",
409 .num_resources = 0, 409 .num_resources = 0,
410}; 410};
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 80077f6472e..4a8e2d34994 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
217 { .volt = 3820, .cur = 0, .level = 0}, 217 { .volt = 3820, .cur = 0, .level = 0},
218}; 218};
219 219
220int rx1950_bat_init(void) 220static int rx1950_bat_init(void)
221{ 221{
222 int ret; 222 int ret;
223 223
@@ -236,25 +236,25 @@ err_gpio1:
236 return ret; 236 return ret;
237} 237}
238 238
239void rx1950_bat_exit(void) 239static void rx1950_bat_exit(void)
240{ 240{
241 gpio_free(S3C2410_GPJ(2)); 241 gpio_free(S3C2410_GPJ(2));
242 gpio_free(S3C2410_GPJ(3)); 242 gpio_free(S3C2410_GPJ(3));
243} 243}
244 244
245void rx1950_enable_charger(void) 245static void rx1950_enable_charger(void)
246{ 246{
247 gpio_direction_output(S3C2410_GPJ(2), 1); 247 gpio_direction_output(S3C2410_GPJ(2), 1);
248 gpio_direction_output(S3C2410_GPJ(3), 1); 248 gpio_direction_output(S3C2410_GPJ(3), 1);
249} 249}
250 250
251void rx1950_disable_charger(void) 251static void rx1950_disable_charger(void)
252{ 252{
253 gpio_direction_output(S3C2410_GPJ(2), 0); 253 gpio_direction_output(S3C2410_GPJ(2), 0);
254 gpio_direction_output(S3C2410_GPJ(3), 0); 254 gpio_direction_output(S3C2410_GPJ(3), 0);
255} 255}
256 256
257DEFINE_SPINLOCK(rx1950_blink_spin); 257static DEFINE_SPINLOCK(rx1950_blink_spin);
258 258
259static int rx1950_led_blink_set(unsigned gpio, int state, 259static int rx1950_led_blink_set(unsigned gpio, int state,
260 unsigned long *delay_on, unsigned long *delay_off) 260 unsigned long *delay_on, unsigned long *delay_off)
@@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
382 382
383static struct pwm_device *lcd_pwm; 383static struct pwm_device *lcd_pwm;
384 384
385void rx1950_lcd_power(int enable) 385static void rx1950_lcd_power(int enable)
386{ 386{
387 int i; 387 int i;
388 static int enabled; 388 static int enabled;
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 5eb9c9a7d73..7a10be629ab 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void);
25 25
26void s3c64xx_restart(char mode, const char *cmd); 26void s3c64xx_restart(char mode, const char *cmd);
27 27
28extern struct syscore_ops s3c64xx_irq_syscore_ops;
29
30#ifdef CONFIG_CPU_S3C6400 28#ifdef CONFIG_CPU_S3C6400
31 29
32extern int s3c6400_init(void); 30extern int s3c6400_init(void);
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 8bec61e242c..0c7e1d960ca 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void)
96 S3C_PMDBG("%s: IRQ configuration restored\n", __func__); 96 S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
97} 97}
98 98
99struct syscore_ops s3c64xx_irq_syscore_ops = { 99static struct syscore_ops s3c64xx_irq_syscore_ops = {
100 .suspend = s3c64xx_irq_pm_suspend, 100 .suspend = s3c64xx_irq_pm_suspend,
101 .resume = s3c64xx_irq_pm_resume, 101 .resume = s3c64xx_irq_pm_resume,
102}; 102};
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 241d0e645c8..57e718957ef 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, 73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74}; 74};
75 75
76unsigned long s5p64x0_armclk_get_rate(struct clk *clk) 76static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
77{ 77{
78 unsigned long rate = clk_get_rate(clk->parent); 78 unsigned long rate = clk_get_rate(clk->parent);
79 u32 clkdiv; 79 u32 clkdiv;
@@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
84 return rate / (clkdiv + 1); 84 return rate / (clkdiv + 1);
85} 85}
86 86
87unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate) 87static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
88 unsigned long rate)
88{ 89{
89 u32 iter; 90 u32 iter;
90 91
@@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
96 return clock_table[ARRAY_SIZE(clock_table) - 1][0]; 97 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
97} 98}
98 99
99int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) 100static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
100{ 101{
101 u32 round_tmp; 102 u32 round_tmp;
102 u32 iter; 103 u32 iter;
@@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
148 return 0; 149 return 0;
149} 150}
150 151
151struct clk_ops s5p64x0_clkarm_ops = { 152static struct clk_ops s5p64x0_clkarm_ops = {
152 .get_rate = s5p64x0_armclk_get_rate, 153 .get_rate = s5p64x0_armclk_get_rate,
153 .set_rate = s5p64x0_armclk_set_rate, 154 .set_rate = s5p64x0_armclk_set_rate,
154 .round_rate = s5p64x0_armclk_round_rate, 155 .round_rate = s5p64x0_armclk_round_rate,
@@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
173 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, 174 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
174}; 175};
175 176
176struct clk *clkset_hclk_low_list[] = { 177static struct clk *clkset_hclk_low_list[] = {
177 &clk_mout_apll.clk, 178 &clk_mout_apll.clk,
178 &clk_mout_mpll.clk, 179 &clk_mout_mpll.clk,
179}; 180};
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index f7f68ad7791..2ee5dc069b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,7 +38,7 @@
38 38
39static u64 dma_dmamask = DMA_BIT_MASK(32); 39static u64 dma_dmamask = DMA_BIT_MASK(32);
40 40
41u8 s5p6440_pdma_peri[] = { 41static u8 s5p6440_pdma_peri[] = {
42 DMACH_UART0_RX, 42 DMACH_UART0_RX,
43 DMACH_UART0_TX, 43 DMACH_UART0_TX,
44 DMACH_UART1_RX, 44 DMACH_UART1_RX,
@@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = {
63 DMACH_SPI1_RX, 63 DMACH_SPI1_RX,
64}; 64};
65 65
66struct dma_pl330_platdata s5p6440_pdma_pdata = { 66static struct dma_pl330_platdata s5p6440_pdma_pdata = {
67 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), 67 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
68 .peri_id = s5p6440_pdma_peri, 68 .peri_id = s5p6440_pdma_peri,
69}; 69};
70 70
71u8 s5p6450_pdma_peri[] = { 71static u8 s5p6450_pdma_peri[] = {
72 DMACH_UART0_RX, 72 DMACH_UART0_RX,
73 DMACH_UART0_TX, 73 DMACH_UART0_TX,
74 DMACH_UART1_RX, 74 DMACH_UART1_RX,
@@ -103,13 +103,13 @@ u8 s5p6450_pdma_peri[] = {
103 DMACH_UART5_TX, 103 DMACH_UART5_TX,
104}; 104};
105 105
106struct dma_pl330_platdata s5p6450_pdma_pdata = { 106static struct dma_pl330_platdata s5p6450_pdma_pdata = {
107 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), 107 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
108 .peri_id = s5p6450_pdma_peri, 108 .peri_id = s5p6450_pdma_peri,
109}; 109};
110 110
111AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA, 111static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
112 {IRQ_DMA0}, NULL); 112 S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
113 113
114static int __init s5p64x0_dma_init(void) 114static int __init s5p64x0_dma_init(void)
115{ 115{
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
index ff85b4b6e8d..0ef47d1b767 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll;
22extern int s5p64x0_epll_enable(struct clk *clk, int enable); 22extern int s5p64x0_epll_enable(struct clk *clk, int enable);
23extern unsigned long s5p64x0_epll_get_rate(struct clk *clk); 23extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
24 24
25extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
26extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
27extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
28
29extern struct clk_ops s5p64x0_clkarm_ops;
30
31extern struct clksrc_clk clk_armclk; 25extern struct clksrc_clk clk_armclk;
32extern struct clksrc_clk clk_dout_mpll; 26extern struct clksrc_clk clk_dout_mpll;
33 27
34extern struct clk *clkset_hclk_low_list[];
35extern struct clksrc_sources clkset_hclk_low; 28extern struct clksrc_sources clkset_hclk_low;
36 29
37extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable); 30extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 247194dd366..16eca4ea201 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = {
170 [1] = &clk_div_apll2.clk, 170 [1] = &clk_div_apll2.clk,
171}; 171};
172 172
173struct clksrc_sources clk_src_mout_am = { 173static struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list, 174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), 175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
176}; 176};
@@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = {
212 [1] = &clk_div_d1_bus.clk, 212 [1] = &clk_div_d1_bus.clk,
213}; 213};
214 214
215struct clksrc_sources clk_src_mout_onenand = { 215static struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list, 216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), 217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
218}; 218};
@@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = {
756 [3] = &clk_mout_hpll.clk, 756 [3] = &clk_mout_hpll.clk,
757}; 757};
758 758
759struct clksrc_sources clk_src_group1 = { 759static struct clksrc_sources clk_src_group1 = {
760 .sources = clk_src_group1_list, 760 .sources = clk_src_group1_list,
761 .nr_sources = ARRAY_SIZE(clk_src_group1_list), 761 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
762}; 762};
@@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = {
766 [1] = &clk_div_mpll.clk, 766 [1] = &clk_div_mpll.clk,
767}; 767};
768 768
769struct clksrc_sources clk_src_group2 = { 769static struct clksrc_sources clk_src_group2 = {
770 .sources = clk_src_group2_list, 770 .sources = clk_src_group2_list,
771 .nr_sources = ARRAY_SIZE(clk_src_group2_list), 771 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
772}; 772};
@@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = {
780 [5] = &clk_mout_hpll.clk, 780 [5] = &clk_mout_hpll.clk,
781}; 781};
782 782
783struct clksrc_sources clk_src_group3 = { 783static struct clksrc_sources clk_src_group3 = {
784 .sources = clk_src_group3_list, 784 .sources = clk_src_group3_list,
785 .nr_sources = ARRAY_SIZE(clk_src_group3_list), 785 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
786}; 786};
@@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = {
806 [5] = &clk_mout_hpll.clk, 806 [5] = &clk_mout_hpll.clk,
807}; 807};
808 808
809struct clksrc_sources clk_src_group4 = { 809static struct clksrc_sources clk_src_group4 = {
810 .sources = clk_src_group4_list, 810 .sources = clk_src_group4_list,
811 .nr_sources = ARRAY_SIZE(clk_src_group4_list), 811 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
812}; 812};
@@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = {
831 [4] = &clk_mout_hpll.clk, 831 [4] = &clk_mout_hpll.clk,
832}; 832};
833 833
834struct clksrc_sources clk_src_group5 = { 834static struct clksrc_sources clk_src_group5 = {
835 .sources = clk_src_group5_list, 835 .sources = clk_src_group5_list,
836 .nr_sources = ARRAY_SIZE(clk_src_group5_list), 836 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
837}; 837};
@@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = {
854 [2] = &clk_div_hdmi.clk, 854 [2] = &clk_div_hdmi.clk,
855}; 855};
856 856
857struct clksrc_sources clk_src_group6 = { 857static struct clksrc_sources clk_src_group6 = {
858 .sources = clk_src_group6_list, 858 .sources = clk_src_group6_list,
859 .nr_sources = ARRAY_SIZE(clk_src_group6_list), 859 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
860}; 860};
@@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = {
866 [3] = &clk_vclk54m, 866 [3] = &clk_vclk54m,
867}; 867};
868 868
869struct clksrc_sources clk_src_group7 = { 869static struct clksrc_sources clk_src_group7 = {
870 .sources = clk_src_group7_list, 870 .sources = clk_src_group7_list,
871 .nr_sources = ARRAY_SIZE(clk_src_group7_list), 871 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
872}; 872};
@@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = {
877 [2] = &clk_fin_epll, 877 [2] = &clk_fin_epll,
878}; 878};
879 879
880struct clksrc_sources clk_src_mmc0 = { 880static struct clksrc_sources clk_src_mmc0 = {
881 .sources = clk_src_mmc0_list, 881 .sources = clk_src_mmc0_list,
882 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), 882 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
883}; 883};
@@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = {
889 [3] = &clk_mout_hpll.clk, 889 [3] = &clk_mout_hpll.clk,
890}; 890};
891 891
892struct clksrc_sources clk_src_mmc12 = { 892static struct clksrc_sources clk_src_mmc12 = {
893 .sources = clk_src_mmc12_list, 893 .sources = clk_src_mmc12_list,
894 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), 894 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
895}; 895};
@@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = {
901 [3] = &clk_mout_hpll.clk, 901 [3] = &clk_mout_hpll.clk,
902}; 902};
903 903
904struct clksrc_sources clk_src_irda_usb = { 904static struct clksrc_sources clk_src_irda_usb = {
905 .sources = clk_src_irda_usb_list, 905 .sources = clk_src_irda_usb_list,
906 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), 906 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
907}; 907};
@@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = {
912 [2] = &clk_div_mpll.clk, 912 [2] = &clk_div_mpll.clk,
913}; 913};
914 914
915struct clksrc_sources clk_src_pwi = { 915static struct clksrc_sources clk_src_pwi = {
916 .sources = clk_src_pwi_list, 916 .sources = clk_src_pwi_list,
917 .nr_sources = ARRAY_SIZE(clk_src_pwi_list), 917 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
918}; 918};
@@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = {
923 [2] = &clk_sclk_audio2.clk, 923 [2] = &clk_sclk_audio2.clk,
924}; 924};
925 925
926struct clksrc_sources clk_src_sclk_spdif = { 926static struct clksrc_sources clk_src_sclk_spdif = {
927 .sources = clk_sclk_spdif_list, 927 .sources = clk_sclk_spdif_list,
928 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), 928 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
929}; 929};
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 96b1ab3dcd4..afd8db2d599 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,7 +35,7 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38u8 pdma0_peri[] = { 38static u8 pdma0_peri[] = {
39 DMACH_UART0_RX, 39 DMACH_UART0_RX,
40 DMACH_UART0_TX, 40 DMACH_UART0_TX,
41 DMACH_UART1_RX, 41 DMACH_UART1_RX,
@@ -68,15 +68,15 @@ u8 pdma0_peri[] = {
68 DMACH_HSI_TX, 68 DMACH_HSI_TX,
69}; 69};
70 70
71struct dma_pl330_platdata s5pc100_pdma0_pdata = { 71static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
72 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 72 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
73 .peri_id = pdma0_peri, 73 .peri_id = pdma0_peri,
74}; 74};
75 75
76AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0, 76static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330,
77 {IRQ_PDMA0}, &s5pc100_pdma0_pdata); 77 S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
78 78
79u8 pdma1_peri[] = { 79static u8 pdma1_peri[] = {
80 DMACH_UART0_RX, 80 DMACH_UART0_RX,
81 DMACH_UART0_TX, 81 DMACH_UART0_TX,
82 DMACH_UART1_RX, 82 DMACH_UART1_RX,
@@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
109 DMACH_MSM_REQ3, 109 DMACH_MSM_REQ3,
110}; 110};
111 111
112struct dma_pl330_platdata s5pc100_pdma1_pdata = { 112static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
113 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 113 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
114 .peri_id = pdma1_peri, 114 .peri_id = pdma1_peri,
115}; 115};
116 116
117AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1, 117static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
118 {IRQ_PDMA1}, &s5pc100_pdma1_pdata); 118 S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
119 119
120static int __init s5pc100_dma_init(void) 120static int __init s5pc100_dma_init(void)
121{ 121{
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index f6885d247d1..86ce62f6619 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,7 +35,7 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38u8 pdma0_peri[] = { 38static u8 pdma0_peri[] = {
39 DMACH_UART0_RX, 39 DMACH_UART0_RX,
40 DMACH_UART0_TX, 40 DMACH_UART0_TX,
41 DMACH_UART1_RX, 41 DMACH_UART1_RX,
@@ -66,15 +66,15 @@ u8 pdma0_peri[] = {
66 DMACH_SPDIF, 66 DMACH_SPDIF,
67}; 67};
68 68
69struct dma_pl330_platdata s5pv210_pdma0_pdata = { 69static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
71 .peri_id = pdma0_peri, 71 .peri_id = pdma0_peri,
72}; 72};
73 73
74AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0, 74static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
75 {IRQ_PDMA0}, &s5pv210_pdma0_pdata); 75 S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
76 76
77u8 pdma1_peri[] = { 77static u8 pdma1_peri[] = {
78 DMACH_UART0_RX, 78 DMACH_UART0_RX,
79 DMACH_UART0_TX, 79 DMACH_UART0_TX,
80 DMACH_UART1_RX, 80 DMACH_UART1_RX,
@@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
109 DMACH_PCM2_TX, 109 DMACH_PCM2_TX,
110}; 110};
111 111
112struct dma_pl330_platdata s5pv210_pdma1_pdata = { 112static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
113 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 113 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
114 .peri_id = pdma1_peri, 114 .peri_id = pdma1_peri,
115}; 115};
116 116
117AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1, 117static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
118 {IRQ_PDMA1}, &s5pv210_pdma1_pdata); 118 S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
119 119
120static int __init s5pv210_dma_init(void) 120static int __init s5pv210_dma_init(void)
121{ 121{
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index ff915261043..2cf5ed75f39 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
844 }, 844 },
845}; 845};
846 846
847struct s5p_platform_fimc goni_fimc_md_platdata __initdata = { 847static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
848 .isp_info = goni_camera_sensors, 848 .isp_info = goni_camera_sensors,
849 .num_clients = ARRAY_SIZE(goni_camera_sensors), 849 .num_clients = ARRAY_SIZE(goni_camera_sensors),
850}; 850};
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index dff9ea7b5bb..0933c8e1eb7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -140,7 +140,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = {
140 .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 }, 140 .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
141}; 141};
142 142
143struct platform_device smdkv210_dm9000 = { 143static struct platform_device smdkv210_dm9000 = {
144 .name = "dm9000", 144 .name = "dm9000",
145 .id = -1, 145 .id = -1,
146 .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources), 146 .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 06383b51e65..4de7d1e79e7 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -69,6 +69,7 @@ void __init omap_reserve(void)
69 omap_vram_reserve_sdram_memblock(); 69 omap_vram_reserve_sdram_memblock();
70 omap_dsp_reserve_sdram_memblock(); 70 omap_dsp_reserve_sdram_memblock();
71 omap_secure_ram_reserve_memblock(); 71 omap_secure_ram_reserve_memblock();
72 omap_barrier_reserve_memblock();
72} 73}
73 74
74void __init omap_init_consistent_dma_size(void) 75void __init omap_init_consistent_dma_size(void)
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 3047ff923a6..8c7994ce986 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -10,4 +10,10 @@ static inline void omap_secure_ram_reserve_memblock(void)
10{ } 10{ }
11#endif 11#endif
12 12
13#ifdef CONFIG_OMAP4_ERRATA_I688
14extern int omap_barrier_reserve_memblock(void);
15#else
16static inline void omap_barrier_reserve_memblock(void)
17{ }
18#endif
13#endif /* __OMAP_SECURE_H__ */ 19#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 95e68190d59..037b448992a 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -53,7 +53,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as 53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible. 54 * such directly equating the two source clocks is impossible.
55 */ 55 */
56struct clk clk_mpllref = { 56static struct clk clk_mpllref = {
57 .name = "mpllref", 57 .name = "mpllref",
58 .parent = &clk_xtal, 58 .parent = &clk_xtal,
59}; 59};
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce66188..88795ea2eca 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
11 default y 11 default y
12 select ARM_VIC if !ARCH_EXYNOS4 12 select ARM_VIC if !ARCH_EXYNOS
13 select ARM_GIC if ARCH_EXYNOS4 13 select ARM_GIC if ARCH_EXYNOS
14 select GIC_NON_BANKED if ARCH_EXYNOS4 14 select GIC_NON_BANKED if ARCH_EXYNOS4
15 select NO_IOPORT 15 select NO_IOPORT
16 select ARCH_REQUIRE_GPIOLIB 16 select ARCH_REQUIRE_GPIOLIB
@@ -40,6 +40,10 @@ config S5P_HRT
40 help 40 help
41 Use the High Resolution timer support 41 Use the High Resolution timer support
42 42
43config S5P_DEV_UART
44 def_bool y
45 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
46
43config S5P_PM 47config S5P_PM
44 bool 48 bool
45 help 49 help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c3016e6..4bd82413665 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj- :=
12 12
13# Core files 13# Core files
14 14
15obj-y += dev-uart.o
16obj-y += clock.o 15obj-y += clock.o
17obj-y += irq.o 16obj-y += irq.o
18obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 17obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP) += sleep.o
23obj-$(CONFIG_S5P_HRT) += s5p-time.o 22obj-$(CONFIG_S5P_HRT) += s5p-time.o
24 23
25# devices 24# devices
25
26obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o
26obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o 27obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
27obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o 28obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea7f7e..f68a9bb1194 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
61 .id = -1, 61 .id = -1,
62}; 62};
63 63
64/* BPLL clock output */
65
66struct clk clk_fout_bpll = {
67 .name = "fout_bpll",
68 .id = -1,
69};
70
71/* CPLL clock output */
72
73struct clk clk_fout_cpll = {
74 .name = "fout_cpll",
75 .id = -1,
76};
77
64/* MPLL clock output 78/* MPLL clock output
65 * No need .ctrlbit, this is always on 79 * No need .ctrlbit, this is always on
66*/ 80*/
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
101 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 115 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
102}; 116};
103 117
118/* Possible clock sources for BPLL Mux */
119static struct clk *clk_src_bpll_list[] = {
120 [0] = &clk_fin_bpll,
121 [1] = &clk_fout_bpll,
122};
123
124struct clksrc_sources clk_src_bpll = {
125 .sources = clk_src_bpll_list,
126 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
127};
128
129/* Possible clock sources for CPLL Mux */
130static struct clk *clk_src_cpll_list[] = {
131 [0] = &clk_fin_cpll,
132 [1] = &clk_fout_cpll,
133};
134
135struct clksrc_sources clk_src_cpll = {
136 .sources = clk_src_cpll_list,
137 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
138};
139
104/* Possible clock sources for MPLL Mux */ 140/* Possible clock sources for MPLL Mux */
105static struct clk *clk_src_mpll_list[] = { 141static struct clk *clk_src_mpll_list[] = {
106 [0] = &clk_fin_mpll, 142 [0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index c496b359c37..139c050918c 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = {
200#endif 200#endif
201}; 201};
202 202
203int __init s5p_init_irq_eint(void) 203static int __init s5p_init_irq_eint(void)
204{ 204{
205 int irq; 205 int irq;
206 206
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 1fdfaa4599c..82c7311017a 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,7 +41,7 @@ struct s5p_gpioint_bank {
41 void (*handler)(unsigned int, struct irq_desc *); 41 void (*handler)(unsigned int, struct irq_desc *);
42}; 42};
43 43
44LIST_HEAD(banks); 44static LIST_HEAD(banks);
45 45
46static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type) 46static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
47{ 47{
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index 327acb3a446..d1bfecae6c9 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow = 0xffffffffL;
39int s3c_irq_wake(struct irq_data *data, unsigned int state) 39int s3c_irq_wake(struct irq_data *data, unsigned int state)
40{ 40{
41 unsigned long irqbit; 41 unsigned long irqbit;
42 unsigned int irq_rtc_tic, irq_rtc_alarm;
43
44#ifdef CONFIG_ARCH_EXYNOS
45 if (soc_is_exynos5250()) {
46 irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
47 irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
48 } else {
49 irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
50 irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
51 }
52#else
53 irq_rtc_tic = IRQ_RTC_TIC;
54 irq_rtc_alarm = IRQ_RTC_ALARM;
55#endif
56
57 if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
58 irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
42 59
43 switch (data->irq) {
44 case IRQ_RTC_TIC:
45 case IRQ_RTC_ALARM:
46 irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
47 if (!state) 60 if (!state)
48 s3c_irqwake_intmask |= irqbit; 61 s3c_irqwake_intmask |= irqbit;
49 else 62 else
50 s3c_irqwake_intmask &= ~irqbit; 63 s3c_irqwake_intmask &= ~irqbit;
51 break; 64 } else {
52 default:
53 return -ENOENT; 65 return -ENOENT;
54 } 66 }
67
55 return 0; 68 return 0;
56} 69}
57 70
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index f10768e988d..98b864777a3 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -744,17 +744,6 @@ struct platform_device s3c_device_iis = {
744}; 744};
745#endif /* CONFIG_PLAT_S3C24XX */ 745#endif /* CONFIG_PLAT_S3C24XX */
746 746
747#ifdef CONFIG_CPU_S3C2440
748struct platform_device s3c2412_device_iis = {
749 .name = "s3c2412-iis",
750 .id = -1,
751 .dev = {
752 .dma_mask = &samsung_device_dma_mask,
753 .coherent_dma_mask = DMA_BIT_MASK(32),
754 }
755};
756#endif /* CONFIG_CPU_S3C2440 */
757
758/* IDE CFCON */ 747/* IDE CFCON */
759 748
760#ifdef CONFIG_SAMSUNG_DEV_IDE 749#ifdef CONFIG_SAMSUNG_DEV_IDE
@@ -1078,7 +1067,7 @@ static struct resource s5p_pmu_resource[] = {
1078 DEFINE_RES_IRQ(IRQ_PMU) 1067 DEFINE_RES_IRQ(IRQ_PMU)
1079}; 1068};
1080 1069
1081struct platform_device s5p_device_pmu = { 1070static struct platform_device s5p_device_pmu = {
1082 .name = "arm-pmu", 1071 .name = "arm-pmu",
1083 .id = ARM_PMU_DEVICE_CPU, 1072 .id = ARM_PMU_DEVICE_CPU,
1084 .num_resources = ARRAY_SIZE(s5p_pmu_resource), 1073 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 0747c77a2fd..301d9c319d0 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
116 return dmaengine_terminate_all((struct dma_chan *)ch); 116 return dmaengine_terminate_all((struct dma_chan *)ch);
117} 117}
118 118
119struct samsung_dma_ops dmadev_ops = { 119static struct samsung_dma_ops dmadev_ops = {
120 .request = samsung_dmadev_request, 120 .request = samsung_dmadev_request,
121 .release = samsung_dmadev_release, 121 .release = samsung_dmadev_release,
122 .prepare = samsung_dmadev_prepare, 122 .prepare = samsung_dmadev_prepare,
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cfd068..787ceaca0be 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
42#define EXYNOS4412_CPU_ID 0xE4412200 42#define EXYNOS4412_CPU_ID 0xE4412200
43#define EXYNOS4_CPU_MASK 0xFFFE0000 43#define EXYNOS4_CPU_MASK 0xFFFE0000
44 44
45#define EXYNOS5250_SOC_ID 0x43520000
46#define EXYNOS5_SOC_MASK 0xFFFFF000
47
45#define IS_SAMSUNG_CPU(name, id, mask) \ 48#define IS_SAMSUNG_CPU(name, id, mask) \
46static inline int is_samsung_##name(void) \ 49static inline int is_samsung_##name(void) \
47{ \ 50{ \
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
58IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) 61IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
59IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 62IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
60IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) 63IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
64IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
61 65
62#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 66#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
63 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ 67 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
120#define EXYNOS4210_REV_1_0 (0x10) 124#define EXYNOS4210_REV_1_0 (0x10)
121#define EXYNOS4210_REV_1_1 (0x11) 125#define EXYNOS4210_REV_1_1 (0x11)
122 126
127#if defined(CONFIG_SOC_EXYNOS5250)
128# define soc_is_exynos5250() is_samsung_exynos5250()
129#else
130# define soc_is_exynos5250() 0
131#endif
132
123#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 133#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
124 134
125#ifndef MHZ 135#ifndef MHZ
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0ff8f..32cc67e6be1 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
26extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; 26extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; 27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
28extern struct s3c24xx_uart_resources s5p_uart_resources[]; 28extern struct s3c24xx_uart_resources s5p_uart_resources[];
29extern struct s3c24xx_uart_resources exynos4_uart_resources[];
30extern struct s3c24xx_uart_resources exynos5_uart_resources[];
29 31
30extern struct platform_device *s3c24xx_uart_devs[]; 32extern struct platform_device *s3c24xx_uart_devs[];
31extern struct platform_device *s3c24xx_uart_src[]; 33extern struct platform_device *s3c24xx_uart_src[];
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index c5eaad529de..0670f37aaae 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -82,6 +82,22 @@ enum dma_ch {
82 DMACH_SLIMBUS4_TX, 82 DMACH_SLIMBUS4_TX,
83 DMACH_SLIMBUS5_RX, 83 DMACH_SLIMBUS5_RX,
84 DMACH_SLIMBUS5_TX, 84 DMACH_SLIMBUS5_TX,
85 DMACH_MIPI_HSI0,
86 DMACH_MIPI_HSI1,
87 DMACH_MIPI_HSI2,
88 DMACH_MIPI_HSI3,
89 DMACH_MIPI_HSI4,
90 DMACH_MIPI_HSI5,
91 DMACH_MIPI_HSI6,
92 DMACH_MIPI_HSI7,
93 DMACH_MTOM_0,
94 DMACH_MTOM_1,
95 DMACH_MTOM_2,
96 DMACH_MTOM_3,
97 DMACH_MTOM_4,
98 DMACH_MTOM_5,
99 DMACH_MTOM_6,
100 DMACH_MTOM_7,
85 /* END Marker, also used to denote a reserved channel */ 101 /* END Marker, also used to denote a reserved channel */
86 DMACH_MAX, 102 DMACH_MAX,
87}; 103};
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e7bc8..1de4b32f98e 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19 19
20#define clk_fin_apll clk_ext_xtal_mux 20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_bpll clk_ext_xtal_mux
22#define clk_fin_cpll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux 23#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux 24#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux 25#define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
29extern struct clk clk_48m; 31extern struct clk clk_48m;
30extern struct clk s5p_clk_27m; 32extern struct clk s5p_clk_27m;
31extern struct clk clk_fout_apll; 33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_cpll;
32extern struct clk clk_fout_mpll; 36extern struct clk clk_fout_mpll;
33extern struct clk clk_fout_epll; 37extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll; 38extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
37extern struct clk clk_vpll; 41extern struct clk clk_vpll;
38 42
39extern struct clksrc_sources clk_src_apll; 43extern struct clksrc_sources clk_src_apll;
44extern struct clksrc_sources clk_src_bpll;
45extern struct clksrc_sources clk_src_cpll;
40extern struct clksrc_sources clk_src_mpll; 46extern struct clksrc_sources clk_src_mpll;
41extern struct clksrc_sources clk_src_epll; 47extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll; 48extern struct clksrc_sources clk_src_dpll;
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12a1e7..7e068d182c3 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
37/* how many bytes we allow into the FIFO at a time in FIFO mode */ 37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14) 38#define FIFO_MAX (14)
39 39
40#ifdef S3C_PA_UART
40#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) 41#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
42#endif
41 43
42static __inline__ void 44static __inline__ void
43uart_wr(unsigned int reg, unsigned int val) 45uart_wr(unsigned int reg, unsigned int val)
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 51583cd3016..f980cf3d2ba 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <mach/map.h> 21#include <mach/map.h>
22#include <plat/cpu.h>
22#include <plat/irq-vic-timer.h> 23#include <plat/irq-vic-timer.h>
23#include <plat/regs-timer.h> 24#include <plat/regs-timer.h>
24 25
@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
57 struct irq_chip_type *ct; 58 struct irq_chip_type *ct;
58 unsigned int i; 59 unsigned int i;
59 60
61#ifdef CONFIG_ARCH_EXYNOS
62 if (soc_is_exynos5250()) {
63 pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
64 pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
65 pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
66 pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
67 pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
68 } else {
69 pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
70 pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
71 pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
72 pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
73 pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
74 }
75#endif
60 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, 76 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
61 S3C64XX_TINT_CSTAT, handle_level_irq); 77 S3C64XX_TINT_CSTAT, handle_level_irq);
62 78
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
index 054537c5f9c..e612ce4512c 100644
--- a/arch/openrisc/include/asm/ptrace.h
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -77,7 +77,6 @@ struct pt_regs {
77 long syscallno; /* Syscall number (used by strace) */ 77 long syscallno; /* Syscall number (used by strace) */
78 long dummy; /* Cheap alignment fix */ 78 long dummy; /* Cheap alignment fix */
79}; 79};
80#endif /* __ASSEMBLY__ */
81 80
82/* TODO: Rename this to REDZONE because that's what it is */ 81/* TODO: Rename this to REDZONE because that's what it is */
83#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */ 82#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
@@ -87,6 +86,13 @@ struct pt_regs {
87#define user_stack_pointer(regs) ((unsigned long)(regs)->sp) 86#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
88#define profile_pc(regs) instruction_pointer(regs) 87#define profile_pc(regs) instruction_pointer(regs)
89 88
89static inline long regs_return_value(struct pt_regs *regs)
90{
91 return regs->gpr[11];
92}
93
94#endif /* __ASSEMBLY__ */
95
90/* 96/*
91 * Offsets used by 'ptrace' system call interface. 97 * Offsets used by 'ptrace' system call interface.
92 */ 98 */
diff --git a/arch/openrisc/kernel/init_task.c b/arch/openrisc/kernel/init_task.c
index 45744a38492..ca534082d5f 100644
--- a/arch/openrisc/kernel/init_task.c
+++ b/arch/openrisc/kernel/init_task.c
@@ -17,6 +17,7 @@
17 17
18#include <linux/init_task.h> 18#include <linux/init_task.h>
19#include <linux/mqueue.h> 19#include <linux/mqueue.h>
20#include <linux/export.h>
20 21
21static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 22static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
22static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 23static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index 59b30233833..4bfead22095 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -23,6 +23,7 @@
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/seq_file.h> 24#include <linux/seq_file.h>
25#include <linux/kernel_stat.h> 25#include <linux/kernel_stat.h>
26#include <linux/export.h>
26 27
27#include <linux/irqflags.h> 28#include <linux/irqflags.h>
28 29
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index 656b94beab8..7259047d5f9 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -188,11 +188,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
188 */ 188 */
189 ret = -1L; 189 ret = -1L;
190 190
191 /* Are these regs right??? */ 191 audit_syscall_entry(audit_arch(), regs->syscallno,
192 if (unlikely(current->audit_context)) 192 regs->gpr[3], regs->gpr[4],
193 audit_syscall_entry(audit_arch(), regs->syscallno, 193 regs->gpr[5], regs->gpr[6]);
194 regs->gpr[3], regs->gpr[4],
195 regs->gpr[5], regs->gpr[6]);
196 194
197 return ret ? : regs->syscallno; 195 return ret ? : regs->syscallno;
198} 196}
@@ -201,9 +199,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
201{ 199{
202 int step; 200 int step;
203 201
204 if (unlikely(current->audit_context)) 202 audit_syscall_exit(regs);
205 audit_syscall_exit(AUDITSC_RESULT(regs->gpr[11]),
206 regs->gpr[11]);
207 203
208 step = test_thread_flag(TIF_SINGLESTEP); 204 step = test_thread_flag(TIF_SINGLESTEP);
209 if (step || test_thread_flag(TIF_SYSCALL_TRACE)) 205 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 55cca1dac43..19ab7b2ea1c 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -31,7 +31,11 @@ ifdef CONFIG_64BIT
31UTS_MACHINE := parisc64 31UTS_MACHINE := parisc64
32CHECKFLAGS += -D__LP64__=1 -m64 32CHECKFLAGS += -D__LP64__=1 -m64
33WIDTH := 64 33WIDTH := 64
34
35# FIXME: if no default set, should really try to locate dynamically
36ifeq ($(CROSS_COMPILE),)
34CROSS_COMPILE := hppa64-linux-gnu- 37CROSS_COMPILE := hppa64-linux-gnu-
38endif
35else # 32-bit 39else # 32-bit
36WIDTH := 40WIDTH :=
37endif 41endif
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index d1727584230..6d99a5fcc09 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -227,6 +227,9 @@ config COMPAT
227config SYSVIPC_COMPAT 227config SYSVIPC_COMPAT
228 def_bool y if COMPAT && SYSVIPC 228 def_bool y if COMPAT && SYSVIPC
229 229
230config KEYS_COMPAT
231 def_bool y if COMPAT && KEYS
232
230config AUDIT_ARCH 233config AUDIT_ARCH
231 def_bool y 234 def_bool y
232 235
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index 2e49748b27d..234f1d859ce 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -172,13 +172,6 @@ static inline int is_compat_task(void)
172 return is_32bit_task(); 172 return is_32bit_task();
173} 173}
174 174
175#else
176
177static inline int is_compat_task(void)
178{
179 return 0;
180}
181
182#endif 175#endif
183 176
184static inline void __user *arch_compat_alloc_user_space(long len) 177static inline void __user *arch_compat_alloc_user_space(long len)
diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index 39f8fd4438f..c383ce440d9 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -11,7 +11,6 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/gfp.h> 12#include <linux/gfp.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/crash_dump.h>
15#include <linux/bootmem.h> 14#include <linux/bootmem.h>
16#include <linux/elf.h> 15#include <linux/elf.h>
17#include <asm/ipl.h> 16#include <asm/ipl.h>
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 4261aa79977..e795933eb2c 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -29,7 +29,6 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/timer.h> 30#include <asm/timer.h>
31#include <asm/nmi.h> 31#include <asm/nmi.h>
32#include <asm/compat.h>
33#include <asm/smp.h> 32#include <asm/smp.h>
34#include "entry.h" 33#include "entry.h"
35 34
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 9d82ed4bcb2..61f95489d70 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -20,8 +20,8 @@
20#include <linux/regset.h> 20#include <linux/regset.h>
21#include <linux/tracehook.h> 21#include <linux/tracehook.h>
22#include <linux/seccomp.h> 22#include <linux/seccomp.h>
23#include <linux/compat.h>
23#include <trace/syscall.h> 24#include <trace/syscall.h>
24#include <asm/compat.h>
25#include <asm/segment.h> 25#include <asm/segment.h>
26#include <asm/page.h> 26#include <asm/page.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 354de0763ef..3b2efc81f34 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -46,6 +46,7 @@
46#include <linux/kexec.h> 46#include <linux/kexec.h>
47#include <linux/crash_dump.h> 47#include <linux/crash_dump.h>
48#include <linux/memory.h> 48#include <linux/memory.h>
49#include <linux/compat.h>
49 50
50#include <asm/ipl.h> 51#include <asm/ipl.h>
51#include <asm/uaccess.h> 52#include <asm/uaccess.h>
@@ -59,7 +60,6 @@
59#include <asm/ptrace.h> 60#include <asm/ptrace.h>
60#include <asm/sections.h> 61#include <asm/sections.h>
61#include <asm/ebcdic.h> 62#include <asm/ebcdic.h>
62#include <asm/compat.h>
63#include <asm/kvm_virtio.h> 63#include <asm/kvm_virtio.h>
64#include <asm/diag.h> 64#include <asm/diag.h>
65 65
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index a8ba840294f..2d421d90fad 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -30,7 +30,6 @@
30#include <asm/ucontext.h> 30#include <asm/ucontext.h>
31#include <asm/uaccess.h> 31#include <asm/uaccess.h>
32#include <asm/lowcore.h> 32#include <asm/lowcore.h>
33#include <asm/compat.h>
34#include "entry.h" 33#include "entry.h"
35 34
36#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 35#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 354dd39073e..e8fcd928dc7 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -36,7 +36,6 @@
36#include <asm/pgtable.h> 36#include <asm/pgtable.h>
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/mmu_context.h> 38#include <asm/mmu_context.h>
39#include <asm/compat.h>
40#include "../kernel/entry.h" 39#include "../kernel/entry.h"
41 40
42#ifndef CONFIG_64BIT 41#ifndef CONFIG_64BIT
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 5d633019d8f..50236610de8 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -223,16 +223,38 @@ void free_initrd_mem(unsigned long start, unsigned long end)
223#ifdef CONFIG_MEMORY_HOTPLUG 223#ifdef CONFIG_MEMORY_HOTPLUG
224int arch_add_memory(int nid, u64 start, u64 size) 224int arch_add_memory(int nid, u64 start, u64 size)
225{ 225{
226 struct pglist_data *pgdat; 226 unsigned long zone_start_pfn, zone_end_pfn, nr_pages;
227 unsigned long start_pfn = PFN_DOWN(start);
228 unsigned long size_pages = PFN_DOWN(size);
227 struct zone *zone; 229 struct zone *zone;
228 int rc; 230 int rc;
229 231
230 pgdat = NODE_DATA(nid);
231 zone = pgdat->node_zones + ZONE_MOVABLE;
232 rc = vmem_add_mapping(start, size); 232 rc = vmem_add_mapping(start, size);
233 if (rc) 233 if (rc)
234 return rc; 234 return rc;
235 rc = __add_pages(nid, zone, PFN_DOWN(start), PFN_DOWN(size)); 235 for_each_zone(zone) {
236 if (zone_idx(zone) != ZONE_MOVABLE) {
237 /* Add range within existing zone limits */
238 zone_start_pfn = zone->zone_start_pfn;
239 zone_end_pfn = zone->zone_start_pfn +
240 zone->spanned_pages;
241 } else {
242 /* Add remaining range to ZONE_MOVABLE */
243 zone_start_pfn = start_pfn;
244 zone_end_pfn = start_pfn + size_pages;
245 }
246 if (start_pfn < zone_start_pfn || start_pfn >= zone_end_pfn)
247 continue;
248 nr_pages = (start_pfn + size_pages > zone_end_pfn) ?
249 zone_end_pfn - start_pfn : size_pages;
250 rc = __add_pages(nid, zone, start_pfn, nr_pages);
251 if (rc)
252 break;
253 start_pfn += nr_pages;
254 size_pages -= nr_pages;
255 if (!size_pages)
256 break;
257 }
236 if (rc) 258 if (rc)
237 vmem_remove_mapping(start, size); 259 vmem_remove_mapping(start, size);
238 return rc; 260 return rc;
diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
index f09c74881b7..a0155c02e32 100644
--- a/arch/s390/mm/mmap.c
+++ b/arch/s390/mm/mmap.c
@@ -29,8 +29,8 @@
29#include <linux/mman.h> 29#include <linux/mman.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/random.h> 31#include <linux/random.h>
32#include <linux/compat.h>
32#include <asm/pgalloc.h> 33#include <asm/pgalloc.h>
33#include <asm/compat.h>
34 34
35static unsigned long stack_maxrandom_size(void) 35static unsigned long stack_maxrandom_size(void)
36{ 36{
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 096c975e099..461ce432b1c 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -242,4 +242,12 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
242static inline void perf_events_lapic_init(void) { } 242static inline void perf_events_lapic_init(void) { }
243#endif 243#endif
244 244
245#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
246 extern void amd_pmu_enable_virt(void);
247 extern void amd_pmu_disable_virt(void);
248#else
249 static inline void amd_pmu_enable_virt(void) { }
250 static inline void amd_pmu_disable_virt(void) { }
251#endif
252
245#endif /* _ASM_X86_PERF_EVENT_H */ 253#endif /* _ASM_X86_PERF_EVENT_H */
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6b45e5e7a90..73d08ed98a6 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -326,8 +326,7 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb)
326 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; 326 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
327} 327}
328 328
329static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, 329static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
330 int index)
331{ 330{
332 int node; 331 int node;
333 332
@@ -725,14 +724,16 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
725#define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y])) 724#define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
726 725
727#ifdef CONFIG_SMP 726#ifdef CONFIG_SMP
728static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) 727
728static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
729{ 729{
730 struct _cpuid4_info *this_leaf, *sibling_leaf; 730 struct _cpuid4_info *this_leaf;
731 unsigned long num_threads_sharing; 731 int ret, i, sibling;
732 int index_msb, i, sibling;
733 struct cpuinfo_x86 *c = &cpu_data(cpu); 732 struct cpuinfo_x86 *c = &cpu_data(cpu);
734 733
735 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) { 734 ret = 0;
735 if (index == 3) {
736 ret = 1;
736 for_each_cpu(i, cpu_llc_shared_mask(cpu)) { 737 for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
737 if (!per_cpu(ici_cpuid4_info, i)) 738 if (!per_cpu(ici_cpuid4_info, i))
738 continue; 739 continue;
@@ -743,8 +744,35 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
743 set_bit(sibling, this_leaf->shared_cpu_map); 744 set_bit(sibling, this_leaf->shared_cpu_map);
744 } 745 }
745 } 746 }
746 return; 747 } else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
748 ret = 1;
749 for_each_cpu(i, cpu_sibling_mask(cpu)) {
750 if (!per_cpu(ici_cpuid4_info, i))
751 continue;
752 this_leaf = CPUID4_INFO_IDX(i, index);
753 for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
754 if (!cpu_online(sibling))
755 continue;
756 set_bit(sibling, this_leaf->shared_cpu_map);
757 }
758 }
747 } 759 }
760
761 return ret;
762}
763
764static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
765{
766 struct _cpuid4_info *this_leaf, *sibling_leaf;
767 unsigned long num_threads_sharing;
768 int index_msb, i;
769 struct cpuinfo_x86 *c = &cpu_data(cpu);
770
771 if (c->x86_vendor == X86_VENDOR_AMD) {
772 if (cache_shared_amd_cpu_map_setup(cpu, index))
773 return;
774 }
775
748 this_leaf = CPUID4_INFO_IDX(cpu, index); 776 this_leaf = CPUID4_INFO_IDX(cpu, index);
749 num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing; 777 num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing;
750 778
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 786e76a8632..e4eeaaf58a4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -528,6 +528,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
528 528
529 sprintf(name, "threshold_bank%i", bank); 529 sprintf(name, "threshold_bank%i", bank);
530 530
531#ifdef CONFIG_SMP
531 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */ 532 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
532 i = cpumask_first(cpu_llc_shared_mask(cpu)); 533 i = cpumask_first(cpu_llc_shared_mask(cpu));
533 534
@@ -553,6 +554,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
553 554
554 goto out; 555 goto out;
555 } 556 }
557#endif
556 558
557 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 559 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
558 if (!b) { 560 if (!b) {
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 8944062f46e..c30c807ddc7 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -147,7 +147,9 @@ struct cpu_hw_events {
147 /* 147 /*
148 * AMD specific bits 148 * AMD specific bits
149 */ 149 */
150 struct amd_nb *amd_nb; 150 struct amd_nb *amd_nb;
151 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
152 u64 perf_ctr_virt_mask;
151 153
152 void *kfree_on_online; 154 void *kfree_on_online;
153}; 155};
@@ -417,9 +419,11 @@ void x86_pmu_disable_all(void);
417static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 419static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
418 u64 enable_mask) 420 u64 enable_mask)
419{ 421{
422 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
423
420 if (hwc->extra_reg.reg) 424 if (hwc->extra_reg.reg)
421 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 425 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
422 wrmsrl(hwc->config_base, hwc->config | enable_mask); 426 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
423} 427}
424 428
425void x86_pmu_enable_all(int added); 429void x86_pmu_enable_all(int added);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 0397b23be8e..67250a52430 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -1,4 +1,5 @@
1#include <linux/perf_event.h> 1#include <linux/perf_event.h>
2#include <linux/export.h>
2#include <linux/types.h> 3#include <linux/types.h>
3#include <linux/init.h> 4#include <linux/init.h>
4#include <linux/slab.h> 5#include <linux/slab.h>
@@ -357,7 +358,9 @@ static void amd_pmu_cpu_starting(int cpu)
357 struct amd_nb *nb; 358 struct amd_nb *nb;
358 int i, nb_id; 359 int i, nb_id;
359 360
360 if (boot_cpu_data.x86_max_cores < 2) 361 cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
362
363 if (boot_cpu_data.x86_max_cores < 2 || boot_cpu_data.x86 == 0x15)
361 return; 364 return;
362 365
363 nb_id = amd_get_nb_id(cpu); 366 nb_id = amd_get_nb_id(cpu);
@@ -587,9 +590,9 @@ static __initconst const struct x86_pmu amd_pmu_f15h = {
587 .put_event_constraints = amd_put_event_constraints, 590 .put_event_constraints = amd_put_event_constraints,
588 591
589 .cpu_prepare = amd_pmu_cpu_prepare, 592 .cpu_prepare = amd_pmu_cpu_prepare,
590 .cpu_starting = amd_pmu_cpu_starting,
591 .cpu_dead = amd_pmu_cpu_dead, 593 .cpu_dead = amd_pmu_cpu_dead,
592#endif 594#endif
595 .cpu_starting = amd_pmu_cpu_starting,
593}; 596};
594 597
595__init int amd_pmu_init(void) 598__init int amd_pmu_init(void)
@@ -621,3 +624,33 @@ __init int amd_pmu_init(void)
621 624
622 return 0; 625 return 0;
623} 626}
627
628void amd_pmu_enable_virt(void)
629{
630 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
631
632 cpuc->perf_ctr_virt_mask = 0;
633
634 /* Reload all events */
635 x86_pmu_disable_all();
636 x86_pmu_enable_all(0);
637}
638EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
639
640void amd_pmu_disable_virt(void)
641{
642 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
643
644 /*
645 * We only mask out the Host-only bit so that host-only counting works
646 * when SVM is disabled. If someone sets up a guest-only counter when
647 * SVM is disabled the Guest-only bits still gets set and the counter
648 * will not count anything.
649 */
650 cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
651
652 /* Reload all events */
653 x86_pmu_disable_all();
654 x86_pmu_enable_all(0);
655}
656EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 3fe8239fd8f..1333d985177 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1532,10 +1532,17 @@ ENTRY(nmi)
1532 pushq_cfi %rdx 1532 pushq_cfi %rdx
1533 1533
1534 /* 1534 /*
1535 * If %cs was not the kernel segment, then the NMI triggered in user
1536 * space, which means it is definitely not nested.
1537 */
1538 cmpl $__KERNEL_CS, 16(%rsp)
1539 jne first_nmi
1540
1541 /*
1535 * Check the special variable on the stack to see if NMIs are 1542 * Check the special variable on the stack to see if NMIs are
1536 * executing. 1543 * executing.
1537 */ 1544 */
1538 cmp $1, -8(%rsp) 1545 cmpl $1, -8(%rsp)
1539 je nested_nmi 1546 je nested_nmi
1540 1547
1541 /* 1548 /*
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index ac0417be913..73465aab28f 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -360,7 +360,6 @@ out:
360static enum ucode_state 360static enum ucode_state
361request_microcode_user(int cpu, const void __user *buf, size_t size) 361request_microcode_user(int cpu, const void __user *buf, size_t size)
362{ 362{
363 pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
364 return UCODE_ERROR; 363 return UCODE_ERROR;
365} 364}
366 365
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5fa553babe5..e385214711c 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -29,6 +29,7 @@
29#include <linux/ftrace_event.h> 29#include <linux/ftrace_event.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31 31
32#include <asm/perf_event.h>
32#include <asm/tlbflush.h> 33#include <asm/tlbflush.h>
33#include <asm/desc.h> 34#include <asm/desc.h>
34#include <asm/kvm_para.h> 35#include <asm/kvm_para.h>
@@ -575,6 +576,8 @@ static void svm_hardware_disable(void *garbage)
575 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); 576 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
576 577
577 cpu_svm_disable(); 578 cpu_svm_disable();
579
580 amd_pmu_disable_virt();
578} 581}
579 582
580static int svm_hardware_enable(void *garbage) 583static int svm_hardware_enable(void *garbage)
@@ -622,6 +625,8 @@ static int svm_hardware_enable(void *garbage)
622 625
623 svm_init_erratum_383(); 626 svm_init_erratum_383();
624 627
628 amd_pmu_enable_virt();
629
625 return 0; 630 return 0;
626} 631}
627 632
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 12eb07bfb26..4172af8ceeb 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1141,7 +1141,9 @@ asmlinkage void __init xen_start_kernel(void)
1141 1141
1142 /* Prevent unwanted bits from being set in PTEs. */ 1142 /* Prevent unwanted bits from being set in PTEs. */
1143 __supported_pte_mask &= ~_PAGE_GLOBAL; 1143 __supported_pte_mask &= ~_PAGE_GLOBAL;
1144#if 0
1144 if (!xen_initial_domain()) 1145 if (!xen_initial_domain())
1146#endif
1145 __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD); 1147 __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
1146 1148
1147 __supported_pte_mask |= _PAGE_IOMAP; 1149 __supported_pte_mask |= _PAGE_IOMAP;
@@ -1204,10 +1206,6 @@ asmlinkage void __init xen_start_kernel(void)
1204 1206
1205 pgd = (pgd_t *)xen_start_info->pt_base; 1207 pgd = (pgd_t *)xen_start_info->pt_base;
1206 1208
1207 if (!xen_initial_domain())
1208 __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
1209
1210 __supported_pte_mask |= _PAGE_IOMAP;
1211 /* Don't do the full vcpu_info placement stuff until we have a 1209 /* Don't do the full vcpu_info placement stuff until we have a
1212 possible map and a non-dummy shared_info. */ 1210 possible map and a non-dummy shared_info. */
1213 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; 1211 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 58a0e46c404..95c1cf60c66 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -415,13 +415,13 @@ static pteval_t iomap_pte(pteval_t val)
415static pteval_t xen_pte_val(pte_t pte) 415static pteval_t xen_pte_val(pte_t pte)
416{ 416{
417 pteval_t pteval = pte.pte; 417 pteval_t pteval = pte.pte;
418 418#if 0
419 /* If this is a WC pte, convert back from Xen WC to Linux WC */ 419 /* If this is a WC pte, convert back from Xen WC to Linux WC */
420 if ((pteval & (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)) == _PAGE_PAT) { 420 if ((pteval & (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)) == _PAGE_PAT) {
421 WARN_ON(!pat_enabled); 421 WARN_ON(!pat_enabled);
422 pteval = (pteval & ~_PAGE_PAT) | _PAGE_PWT; 422 pteval = (pteval & ~_PAGE_PAT) | _PAGE_PWT;
423 } 423 }
424 424#endif
425 if (xen_initial_domain() && (pteval & _PAGE_IOMAP)) 425 if (xen_initial_domain() && (pteval & _PAGE_IOMAP))
426 return pteval; 426 return pteval;
427 427
@@ -463,7 +463,7 @@ void xen_set_pat(u64 pat)
463static pte_t xen_make_pte(pteval_t pte) 463static pte_t xen_make_pte(pteval_t pte)
464{ 464{
465 phys_addr_t addr = (pte & PTE_PFN_MASK); 465 phys_addr_t addr = (pte & PTE_PFN_MASK);
466 466#if 0
467 /* If Linux is trying to set a WC pte, then map to the Xen WC. 467 /* If Linux is trying to set a WC pte, then map to the Xen WC.
468 * If _PAGE_PAT is set, then it probably means it is really 468 * If _PAGE_PAT is set, then it probably means it is really
469 * _PAGE_PSE, so avoid fiddling with the PAT mapping and hope 469 * _PAGE_PSE, so avoid fiddling with the PAT mapping and hope
@@ -476,7 +476,7 @@ static pte_t xen_make_pte(pteval_t pte)
476 if ((pte & (_PAGE_PCD | _PAGE_PWT)) == _PAGE_PWT) 476 if ((pte & (_PAGE_PCD | _PAGE_PWT)) == _PAGE_PWT)
477 pte = (pte & ~(_PAGE_PCD | _PAGE_PWT)) | _PAGE_PAT; 477 pte = (pte & ~(_PAGE_PCD | _PAGE_PWT)) | _PAGE_PAT;
478 } 478 }
479 479#endif
480 /* 480 /*
481 * Unprivileged domains are allowed to do IOMAPpings for 481 * Unprivileged domains are allowed to do IOMAPpings for
482 * PCI passthrough, but not map ISA space. The ISA 482 * PCI passthrough, but not map ISA space. The ISA
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 16:00:58 -0400