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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-04-19 12:17:29 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-19 12:17:29 -0400
commitadf6d34e460387ee3e8f1e1875d52bff51212c7d (patch)
tree88ef100143e6184103a608f82dfd232bf6376eaf /arch
parentd1964dab60ce7c104dd21590e987a8787db18051 (diff)
parent3760d31f11bfbd0ead9eaeb8573e0602437a9d7c (diff)
Merge branch 'omap2-upstream' into devel
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/kernel/pci_iommu.c8
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/common/it8152.c5
-rw-r--r--arch/arm/kernel/calls.S2
-rw-r--r--arch/arm/kernel/sys_oabi-compat.c24
-rw-r--r--arch/arm/mach-omap1/Makefile3
-rw-r--r--arch/arm/mach-omap1/board-osk.c138
-rw-r--r--arch/arm/mach-omap1/leds-osk.c80
-rw-r--r--arch/arm/mach-omap1/mux.c146
-rw-r--r--arch/arm/mach-omap1/time.c49
-rw-r--r--arch/arm/mach-omap1/timer32k.c (renamed from arch/arm/plat-omap/timer32k.c)76
-rw-r--r--arch/arm/mach-omap2/Makefile12
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c23
-rw-r--r--arch/arm/mach-omap2/board-apollon.c60
-rw-r--r--arch/arm/mach-omap2/board-h4.c111
-rw-r--r--arch/arm/mach-omap2/clock.c1362
-rw-r--r--arch/arm/mach-omap2/clock.h2129
-rw-r--r--arch/arm/mach-omap2/clock24xx.c539
-rw-r--r--arch/arm/mach-omap2/clock24xx.h2643
-rw-r--r--arch/arm/mach-omap2/clock34xx.c235
-rw-r--r--arch/arm/mach-omap2/clock34xx.h3009
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h401
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h673
-rw-r--r--arch/arm/mach-omap2/cm.h124
-rw-r--r--arch/arm/mach-omap2/control.c74
-rw-r--r--arch/arm/mach-omap2/gpmc.c12
-rw-r--r--arch/arm/mach-omap2/memory.c74
-rw-r--r--arch/arm/mach-omap2/memory.h2
-rw-r--r--arch/arm/mach-omap2/mux.c121
-rw-r--r--arch/arm/mach-omap2/pm-domain.c299
-rw-r--r--arch/arm/mach-omap2/pm.c270
-rw-r--r--arch/arm/mach-omap2/prcm-common.h317
-rw-r--r--arch/arm/mach-omap2/prcm-regs.h483
-rw-r--r--arch/arm/mach-omap2/prcm.c14
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h279
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h582
-rw-r--r--arch/arm/mach-omap2/prm.h316
-rw-r--r--arch/arm/mach-omap2/sdrc.h58
-rw-r--r--arch/arm/mach-omap2/sleep.S23
-rw-r--r--arch/arm/mach-omap2/sram-fn.S42
-rw-r--r--arch/arm/mach-omap2/timer-gp.c152
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c42
-rw-r--r--arch/arm/plat-omap/common.c64
-rw-r--r--arch/arm/plat-omap/gpio.c176
-rw-r--r--arch/arm/plat-omap/mux.c174
-rw-r--r--arch/arm/plat-omap/usb.c67
-rw-r--r--arch/avr32/kernel/setup.c1
-rw-r--r--arch/avr32/kernel/traps.c4
-rw-r--r--arch/frv/kernel/entry-table.S8
-rw-r--r--arch/frv/kernel/entry.S20
-rw-r--r--arch/frv/kernel/head.inc2
-rw-r--r--arch/frv/kernel/switch_to.S7
-rw-r--r--arch/frv/kernel/traps.c227
-rw-r--r--arch/m68k/Makefile2
-rw-r--r--arch/m68k/configs/amiga_defconfig1005
-rw-r--r--arch/m68k/configs/apollo_defconfig863
-rw-r--r--arch/m68k/configs/atari_defconfig949
-rw-r--r--arch/m68k/configs/bvme6000_defconfig827
-rw-r--r--arch/m68k/configs/hp300_defconfig875
-rw-r--r--arch/m68k/configs/mac_defconfig964
-rw-r--r--arch/m68k/configs/mvme147_defconfig852
-rw-r--r--arch/m68k/configs/mvme16x_defconfig853
-rw-r--r--arch/m68k/configs/q40_defconfig991
-rw-r--r--arch/m68k/configs/sun3_defconfig864
-rw-r--r--arch/m68k/configs/sun3x_defconfig864
-rw-r--r--arch/m68k/defconfig657
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/au1000/common/cputable.c36
-rw-r--r--arch/mips/au1000/common/setup.c13
-rw-r--r--arch/mips/au1000/common/time.c24
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c3
-rw-r--r--arch/mips/au1000/xxs1500/irqmap.c2
-rw-r--r--arch/mips/configs/bigsur_defconfig939
-rw-r--r--arch/mips/kernel/gdb-stub.c3
-rw-r--r--arch/mips/kernel/i8253.c1
-rw-r--r--arch/mips/kernel/time.c2
-rw-r--r--arch/mips/kernel/vpe.c21
-rw-r--r--arch/mips/mm/c-r4k.c14
-rw-r--r--arch/mips/mm/c-tx39.c15
-rw-r--r--arch/mips/mm/cache.c3
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/mips/pci/pci-bcm1480.c6
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c21
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts37
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts15
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts63
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts3
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts42
-rw-r--r--arch/powerpc/configs/mpc832x_mds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc834x_mds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc836x_mds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc837x_rdb_defconfig24
-rw-r--r--arch/powerpc/configs/mpc83xx_defconfig24
-rw-r--r--arch/powerpc/configs/mpc8544_ds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc8568mds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc8572_ds_defconfig11
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig11
-rw-r--r--arch/powerpc/configs/mpc8641_hpcn_defconfig11
-rw-r--r--arch/powerpc/configs/pasemi_defconfig142
-rw-r--r--arch/powerpc/configs/prpmc2800_defconfig11
-rw-r--r--arch/powerpc/configs/storcenter_defconfig11
-rw-r--r--arch/powerpc/kernel/head_64.S13
-rw-r--r--arch/powerpc/kernel/irq.c1
-rw-r--r--arch/powerpc/kernel/process.c10
-rw-r--r--arch/powerpc/kernel/rtas_flash.c2
-rw-r--r--arch/powerpc/mm/hash_low_32.S8
-rw-r--r--arch/powerpc/oprofile/cell/vma_map.c37
-rw-r--r--arch/powerpc/platforms/pseries/xics.c2
-rw-r--r--arch/powerpc/sysdev/cpm2.c1
-rw-r--r--arch/sh/Kconfig3
-rw-r--r--arch/sh/boot/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh2a/fpu.c1
-rw-r--r--arch/sh/kernel/cpu/sh4/fpu.c1
-rw-r--r--arch/sh/kernel/cpu/sh5/fpu.c1
-rw-r--r--arch/sh/kernel/dump_task.c1
-rw-r--r--arch/sh/kernel/process_32.c1
-rw-r--r--arch/sh/kernel/signal_32.c1
-rw-r--r--arch/sparc/kernel/ptrace.c2
-rw-r--r--arch/sparc64/defconfig12
-rw-r--r--arch/sparc64/kernel/cpu.c10
-rw-r--r--arch/sparc64/kernel/entry.S30
-rw-r--r--arch/sparc64/kernel/entry.h196
-rw-r--r--arch/sparc64/kernel/iommu.c20
-rw-r--r--arch/sparc64/kernel/iommu_common.h18
-rw-r--r--arch/sparc64/kernel/irq.c21
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c12
-rw-r--r--arch/sparc64/kernel/ptrace.c222
-rw-r--r--arch/sparc64/kernel/setup.c5
-rw-r--r--arch/sparc64/kernel/signal.c5
-rw-r--r--arch/sparc64/kernel/smp.c3
-rw-r--r--arch/sparc64/kernel/stacktrace.c4
-rw-r--r--arch/sparc64/kernel/sys_sparc.c14
-rw-r--r--arch/sparc64/kernel/systbls.h53
-rw-r--r--arch/sparc64/kernel/time.c66
-rw-r--r--arch/sparc64/kernel/traps.c49
-rw-r--r--arch/sparc64/mm/init.c5
-rw-r--r--arch/sparc64/mm/tlb.c6
-rw-r--r--arch/um/drivers/net_kern.c6
-rw-r--r--arch/x86/kernel/alternative.c12
-rw-r--r--arch/x86/kernel/cpu/bugs.c8
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-smi.c39
-rw-r--r--arch/x86/kernel/cpu/mtrr/generic.c42
-rw-r--r--arch/x86/kernel/cpu/perfctr-watchdog.c7
-rw-r--r--arch/x86/kernel/hpet.c9
-rw-r--r--arch/x86/kernel/io_delay.c8
-rw-r--r--arch/x86/kernel/machine_kexec_64.c1
-rw-r--r--arch/x86/kernel/mfgpt_32.c1
-rw-r--r--arch/x86/kernel/pci-gart_64.c10
-rw-r--r--arch/x86/kernel/process_32.c47
-rw-r--r--arch/x86/kernel/process_64.c47
-rw-r--r--arch/x86/kernel/ptrace.c169
-rw-r--r--arch/x86/kernel/setup_32.c9
-rw-r--r--arch/x86/kernel/setup_64.c2
-rw-r--r--arch/x86/kernel/step.c11
-rw-r--r--arch/x86/kernel/tls.c4
-rw-r--r--arch/x86/kernel/tsc_32.c4
-rw-r--r--arch/x86/kernel/tsc_64.c4
-rw-r--r--arch/x86/lguest/boot.c108
-rw-r--r--arch/x86/lguest/i386_head.S15
-rw-r--r--arch/x86/mach-rdc321x/gpio.c199
-rw-r--r--arch/x86/mach-rdc321x/platform.c2
-rw-r--r--arch/x86/mm/discontig_32.c1
-rw-r--r--arch/x86/mm/fault.c10
-rw-r--r--arch/x86/mm/highmem_32.c6
-rw-r--r--arch/x86/mm/hugetlbpage.c2
-rw-r--r--arch/x86/mm/ioremap.c6
-rw-r--r--arch/x86/mm/pageattr.c2
-rw-r--r--arch/x86/xen/enlighten.c74
-rw-r--r--arch/x86/xen/mmu.c7
-rw-r--r--arch/x86/xen/mmu.h7
-rw-r--r--arch/x86/xen/xen-asm.S9
176 files changed, 18960 insertions, 10686 deletions
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index 4e1c08636ed..dd6e334ab9e 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -424,11 +424,13 @@ EXPORT_SYMBOL(pci_unmap_page);
424 else DMA_ADDRP is undefined. */ 424 else DMA_ADDRP is undefined. */
425 425
426void * 426void *
427pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp) 427__pci_alloc_consistent(struct pci_dev *pdev, size_t size,
428 dma_addr_t *dma_addrp, gfp_t gfp)
428{ 429{
429 void *cpu_addr; 430 void *cpu_addr;
430 long order = get_order(size); 431 long order = get_order(size);
431 gfp_t gfp = GFP_ATOMIC; 432
433 gfp &= ~GFP_DMA;
432 434
433try_again: 435try_again:
434 cpu_addr = (void *)__get_free_pages(gfp, order); 436 cpu_addr = (void *)__get_free_pages(gfp, order);
@@ -458,7 +460,7 @@ try_again:
458 460
459 return cpu_addr; 461 return cpu_addr;
460} 462}
461EXPORT_SYMBOL(pci_alloc_consistent); 463EXPORT_SYMBOL(__pci_alloc_consistent);
462 464
463/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must 465/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
464 be values that were returned from pci_alloc_consistent. SIZE must 466 be values that were returned from pci_alloc_consistent. SIZE must
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ac1bef1797e..a34cc03e727 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -476,6 +476,7 @@ config ARCH_DAVINCI
476config ARCH_OMAP 476config ARCH_OMAP
477 bool "TI OMAP" 477 bool "TI OMAP"
478 select GENERIC_GPIO 478 select GENERIC_GPIO
479 select HAVE_GPIO_LIB
479 select GENERIC_TIME 480 select GENERIC_TIME
480 select GENERIC_CLOCKEVENTS 481 select GENERIC_CLOCKEVENTS
481 help 482 help
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 53826224148..5fe9588db07 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -120,6 +120,7 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
120 time, when they all three were 0. */ 120 time, when they all three were 0. */
121 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); 121 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
122 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); 122 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
123 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
123 if (!(bits_ld | bits_lp | bits_pd)) 124 if (!(bits_ld | bits_lp | bits_pd))
124 return; 125 return;
125 } 126 }
@@ -133,14 +134,14 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
133 134
134 bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); 135 bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
135 while (bits_lp) { 136 while (bits_lp) {
136 i = __ffs(bits_pd); 137 i = __ffs(bits_lp);
137 it8152_irq(IT8152_LP_IRQ(i)); 138 it8152_irq(IT8152_LP_IRQ(i));
138 bits_lp &= ~(1 << i); 139 bits_lp &= ~(1 << i);
139 } 140 }
140 141
141 bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); 142 bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
142 while (bits_ld) { 143 while (bits_ld) {
143 i = __ffs(bits_pd); 144 i = __ffs(bits_ld);
144 it8152_irq(IT8152_LD_IRQ(i)); 145 it8152_irq(IT8152_LD_IRQ(i));
145 bits_ld &= ~(1 << i); 146 bits_ld &= ~(1 << i);
146 } 147 }
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 95f1c121cb3..30a67a5a40a 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -336,7 +336,7 @@
336 CALL(sys_mknodat) 336 CALL(sys_mknodat)
337/* 325 */ CALL(sys_fchownat) 337/* 325 */ CALL(sys_fchownat)
338 CALL(sys_futimesat) 338 CALL(sys_futimesat)
339 CALL(sys_fstatat64) 339 CALL(ABI(sys_fstatat64, sys_oabi_fstatat64))
340 CALL(sys_unlinkat) 340 CALL(sys_unlinkat)
341 CALL(sys_renameat) 341 CALL(sys_renameat)
342/* 330 */ CALL(sys_linkat) 342/* 330 */ CALL(sys_linkat)
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index e8b98046895..96ab5f52949 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -25,6 +25,7 @@
25 * sys_stat64: 25 * sys_stat64:
26 * sys_lstat64: 26 * sys_lstat64:
27 * sys_fstat64: 27 * sys_fstat64:
28 * sys_fstatat64:
28 * 29 *
29 * struct stat64 has different sizes and some members are shifted 30 * struct stat64 has different sizes and some members are shifted
30 * Compatibility wrappers are needed for them and provided below. 31 * Compatibility wrappers are needed for them and provided below.
@@ -169,6 +170,29 @@ asmlinkage long sys_oabi_fstat64(unsigned long fd,
169 return error; 170 return error;
170} 171}
171 172
173asmlinkage long sys_oabi_fstatat64(int dfd,
174 char __user *filename,
175 struct oldabi_stat64 __user *statbuf,
176 int flag)
177{
178 struct kstat stat;
179 int error = -EINVAL;
180
181 if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0)
182 goto out;
183
184 if (flag & AT_SYMLINK_NOFOLLOW)
185 error = vfs_lstat_fd(dfd, filename, &stat);
186 else
187 error = vfs_stat_fd(dfd, filename, &stat);
188
189 if (!error)
190 error = cp_oldabi_stat64(&stat, statbuf);
191
192out:
193 return error;
194}
195
172struct oabi_flock64 { 196struct oabi_flock64 {
173 short l_type; 197 short l_type;
174 short l_whence; 198 short l_whence;
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 015a66b3ca8..c06f5254c0f 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -5,7 +5,8 @@
5# Common support 5# Common support
6obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o 6obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
7 7
8obj-$(CONFIG_OMAP_MPU_TIMER) += time.o 8obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
9obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
9 10
10# Power Management 11# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o 12obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 5279e35a8ae..4f9baba7d89 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -32,6 +32,7 @@
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/leds.h>
35 36
36#include <linux/mtd/mtd.h> 37#include <linux/mtd/mtd.h>
37#include <linux/mtd/partitions.h> 38#include <linux/mtd/partitions.h>
@@ -183,11 +184,80 @@ static struct platform_device *osk5912_devices[] __initdata = {
183 &osk5912_mcbsp1_device, 184 &osk5912_mcbsp1_device,
184}; 185};
185 186
187static struct gpio_led tps_leds[] = {
188 /* NOTE: D9 and D2 have hardware blink support.
189 * Also, D9 requires non-battery power.
190 */
191 { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", },
192 { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", },
193 { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1,
194 .default_trigger = "heartbeat", },
195};
196
197static struct gpio_led_platform_data tps_leds_data = {
198 .num_leds = 3,
199 .leds = tps_leds,
200};
201
202static struct platform_device osk5912_tps_leds = {
203 .name = "leds-gpio",
204 .id = 0,
205 .dev.platform_data = &tps_leds_data,
206};
207
208static int osk_tps_setup(struct i2c_client *client, void *context)
209{
210 /* Set GPIO 1 HIGH to disable VBUS power supply;
211 * OHCI driver powers it up/down as needed.
212 */
213 gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en");
214 gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1);
215
216 /* Set GPIO 2 high so LED D3 is off by default */
217 tps65010_set_gpio_out_value(GPIO2, HIGH);
218
219 /* Set GPIO 3 low to take ethernet out of reset */
220 gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset");
221 gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0);
222
223 /* GPIO4 is VDD_DSP */
224 gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power");
225 gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1);
226 /* REVISIT if DSP support isn't configured, power it off ... */
227
228 /* Let LED1 (D9) blink; leds-gpio may override it */
229 tps65010_set_led(LED1, BLINK);
230
231 /* Set LED2 off by default */
232 tps65010_set_led(LED2, OFF);
233
234 /* Enable LOW_PWR handshake */
235 tps65010_set_low_pwr(ON);
236
237 /* Switch VLDO2 to 3.0V for AIC23 */
238 tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
239 | TPS_LDO1_ENABLE);
240
241 /* register these three LEDs */
242 osk5912_tps_leds.dev.parent = &client->dev;
243 platform_device_register(&osk5912_tps_leds);
244
245 return 0;
246}
247
248static struct tps65010_board tps_board = {
249 .base = OSK_TPS_GPIO_BASE,
250 .outmask = 0x0f,
251 .setup = osk_tps_setup,
252};
253
186static struct i2c_board_info __initdata osk_i2c_board_info[] = { 254static struct i2c_board_info __initdata osk_i2c_board_info[] = {
187 { 255 {
188 I2C_BOARD_INFO("tps65010", 0x48), 256 I2C_BOARD_INFO("tps65010", 0x48),
189 .type = "tps65010", 257 .type = "tps65010",
190 .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)), 258 .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
259 .platform_data = &tps_board,
260
191 }, 261 },
192 /* TODO when driver support is ready: 262 /* TODO when driver support is ready:
193 * - aic23 audio chip at 0x1a 263 * - aic23 audio chip at 0x1a
@@ -198,7 +268,7 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
198 268
199static void __init osk_init_smc91x(void) 269static void __init osk_init_smc91x(void)
200{ 270{
201 if ((omap_request_gpio(0)) < 0) { 271 if ((gpio_request(0, "smc_irq")) < 0) {
202 printk("Error requesting gpio 0 for smc91x irq\n"); 272 printk("Error requesting gpio 0 for smc91x irq\n");
203 return; 273 return;
204 } 274 }
@@ -210,7 +280,7 @@ static void __init osk_init_smc91x(void)
210static void __init osk_init_cf(void) 280static void __init osk_init_cf(void)
211{ 281{
212 omap_cfg_reg(M7_1610_GPIO62); 282 omap_cfg_reg(M7_1610_GPIO62);
213 if ((omap_request_gpio(62)) < 0) { 283 if ((gpio_request(62, "cf_irq")) < 0) {
214 printk("Error requesting gpio 62 for CF irq\n"); 284 printk("Error requesting gpio 62 for CF irq\n");
215 return; 285 return;
216 } 286 }
@@ -334,7 +404,7 @@ static struct platform_device *mistral_devices[] __initdata = {
334 404
335static int mistral_get_pendown_state(void) 405static int mistral_get_pendown_state(void)
336{ 406{
337 return !omap_get_gpio_datain(4); 407 return !gpio_get_value(4);
338} 408}
339 409
340static const struct ads7846_platform_data mistral_ts_info = { 410static const struct ads7846_platform_data mistral_ts_info = {
@@ -396,25 +466,31 @@ static void __init osk_mistral_init(void)
396 omap_cfg_reg(W14_1610_CCP_DATAP); 466 omap_cfg_reg(W14_1610_CCP_DATAP);
397 467
398 /* CAM_PWDN */ 468 /* CAM_PWDN */
399 if (omap_request_gpio(11) == 0) { 469 if (gpio_request(11, "cam_pwdn") == 0) {
400 omap_cfg_reg(N20_1610_GPIO11); 470 omap_cfg_reg(N20_1610_GPIO11);
401 omap_set_gpio_direction(11, 0 /* out */); 471 gpio_direction_output(11, 0);
402 omap_set_gpio_dataout(11, 0 /* off */);
403 } else 472 } else
404 pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); 473 pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
405 474
406 475
407 /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */ 476 /* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */
477 gpio_request(6, "ts_busy");
478 gpio_direction_input(6);
479
408 omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ 480 omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
481 gpio_request(4, "ts_int");
482 gpio_direction_input(4);
409 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); 483 set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
484
410 spi_register_board_info(mistral_boardinfo, 485 spi_register_board_info(mistral_boardinfo,
411 ARRAY_SIZE(mistral_boardinfo)); 486 ARRAY_SIZE(mistral_boardinfo));
412 487
413 /* the sideways button (SW1) is for use as a "wakeup" button */ 488 /* the sideways button (SW1) is for use as a "wakeup" button */
414 omap_cfg_reg(N15_1610_MPUIO2); 489 omap_cfg_reg(N15_1610_MPUIO2);
415 if (omap_request_gpio(OMAP_MPUIO(2)) == 0) { 490 if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) {
416 int ret = 0; 491 int ret = 0;
417 omap_set_gpio_direction(OMAP_MPUIO(2), 1); 492
493 gpio_direction_input(OMAP_MPUIO(2));
418 set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING); 494 set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
419#ifdef CONFIG_PM 495#ifdef CONFIG_PM
420 /* share the IRQ in case someone wants to use the 496 /* share the IRQ in case someone wants to use the
@@ -425,7 +501,7 @@ static void __init osk_mistral_init(void)
425 IRQF_SHARED, "mistral_wakeup", 501 IRQF_SHARED, "mistral_wakeup",
426 &osk_mistral_wake_interrupt); 502 &osk_mistral_wake_interrupt);
427 if (ret != 0) { 503 if (ret != 0) {
428 omap_free_gpio(OMAP_MPUIO(2)); 504 gpio_free(OMAP_MPUIO(2));
429 printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", 505 printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n",
430 ret); 506 ret);
431 } else 507 } else
@@ -438,10 +514,8 @@ static void __init osk_mistral_init(void)
438 * board, like the touchscreen, EEPROM, and wakeup (!) switch. 514 * board, like the touchscreen, EEPROM, and wakeup (!) switch.
439 */ 515 */
440 omap_cfg_reg(PWL); 516 omap_cfg_reg(PWL);
441 if (omap_request_gpio(2) == 0) { 517 if (gpio_request(2, "lcd_pwr") == 0)
442 omap_set_gpio_direction(2, 0 /* out */); 518 gpio_direction_output(2, 1);
443 omap_set_gpio_dataout(2, 1 /* on */);
444 }
445 519
446 platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); 520 platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
447} 521}
@@ -484,44 +558,6 @@ static void __init osk_map_io(void)
484 omap1_map_common_io(); 558 omap1_map_common_io();
485} 559}
486 560
487#ifdef CONFIG_TPS65010
488static int __init osk_tps_init(void)
489{
490 if (!machine_is_omap_osk())
491 return 0;
492
493 /* Let LED1 (D9) blink */
494 tps65010_set_led(LED1, BLINK);
495
496 /* Disable LED 2 (D2) */
497 tps65010_set_led(LED2, OFF);
498
499 /* Set GPIO 1 HIGH to disable VBUS power supply;
500 * OHCI driver powers it up/down as needed.
501 */
502 tps65010_set_gpio_out_value(GPIO1, HIGH);
503
504 /* Set GPIO 2 low to turn on LED D3 */
505 tps65010_set_gpio_out_value(GPIO2, HIGH);
506
507 /* Set GPIO 3 low to take ethernet out of reset */
508 tps65010_set_gpio_out_value(GPIO3, LOW);
509
510 /* gpio4 for VDD_DSP */
511 /* FIXME send power to DSP iff it's configured */
512
513 /* Enable LOW_PWR */
514 tps65010_set_low_pwr(ON);
515
516 /* Switch VLDO2 to 3.0V for AIC23 */
517 tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
518 | TPS_LDO1_ENABLE);
519
520 return 0;
521}
522fs_initcall(osk_tps_init);
523#endif
524
525MACHINE_START(OMAP_OSK, "TI-OSK") 561MACHINE_START(OMAP_OSK, "TI-OSK")
526 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ 562 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
527 .phys_io = 0xfff00000, 563 .phys_io = 0xfff00000,
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index 026685ed461..754383dde80 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -1,11 +1,9 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/leds-osk.c 2 * linux/arch/arm/mach-omap1/leds-osk.c
3 * 3 *
4 * LED driver for OSK, and optionally Mistral QVGA, boards 4 * LED driver for OSK with optional Mistral QVGA board
5 */ 5 */
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/workqueue.h>
8#include <linux/i2c/tps65010.h>
9 7
10#include <asm/hardware.h> 8#include <asm/hardware.h>
11#include <asm/leds.h> 9#include <asm/leds.h>
@@ -20,49 +18,11 @@
20#define LED_STATE_CLAIMED (1 << 1) 18#define LED_STATE_CLAIMED (1 << 1)
21static u8 led_state; 19static u8 led_state;
22 20
23#define GREEN_LED (1 << 0) /* TPS65010 LED1 */
24#define AMBER_LED (1 << 1) /* TPS65010 LED2 */
25#define RED_LED (1 << 2) /* TPS65010 GPIO2 */
26#define TIMER_LED (1 << 3) /* Mistral board */ 21#define TIMER_LED (1 << 3) /* Mistral board */
27#define IDLE_LED (1 << 4) /* Mistral board */ 22#define IDLE_LED (1 << 4) /* Mistral board */
28static u8 hw_led_state; 23static u8 hw_led_state;
29 24
30 25
31/* TPS65010 leds are changed using i2c -- from a task context.
32 * Using one of these for the "idle" LED would be impractical...
33 */
34#define TPS_LEDS (GREEN_LED | RED_LED | AMBER_LED)
35
36static u8 tps_leds_change;
37
38static void tps_work(struct work_struct *unused)
39{
40 for (;;) {
41 u8 leds;
42
43 local_irq_disable();
44 leds = tps_leds_change;
45 tps_leds_change = 0;
46 local_irq_enable();
47
48 if (!leds)
49 break;
50
51 /* careful: the set_led() value is on/off/blink */
52 if (leds & GREEN_LED)
53 tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
54 if (leds & AMBER_LED)
55 tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
56
57 /* the gpio led doesn't have that issue */
58 if (leds & RED_LED)
59 tps65010_set_gpio_out_value(GPIO2,
60 !(hw_led_state & RED_LED));
61 }
62}
63
64static DECLARE_WORK(work, tps_work);
65
66#ifdef CONFIG_OMAP_OSK_MISTRAL 26#ifdef CONFIG_OMAP_OSK_MISTRAL
67 27
68/* For now, all system indicators require the Mistral board, since that 28/* For now, all system indicators require the Mistral board, since that
@@ -112,7 +72,6 @@ void osk_leds_event(led_event_t evt)
112 case led_stop: 72 case led_stop:
113 led_state &= ~LED_STATE_ENABLED; 73 led_state &= ~LED_STATE_ENABLED;
114 hw_led_state = 0; 74 hw_led_state = 0;
115 /* NOTE: work may still be pending!! */
116 break; 75 break;
117 76
118 case led_claim: 77 case led_claim:
@@ -145,48 +104,11 @@ void osk_leds_event(led_event_t evt)
145 104
146#endif /* CONFIG_OMAP_OSK_MISTRAL */ 105#endif /* CONFIG_OMAP_OSK_MISTRAL */
147 106
148 /* "green" == tps LED1 (leftmost, normally power-good)
149 * works only with DC adapter, not on battery power!
150 */
151 case led_green_on:
152 if (led_state & LED_STATE_CLAIMED)
153 hw_led_state |= GREEN_LED;
154 break;
155 case led_green_off:
156 if (led_state & LED_STATE_CLAIMED)
157 hw_led_state &= ~GREEN_LED;
158 break;
159
160 /* "amber" == tps LED2 (middle) */
161 case led_amber_on:
162 if (led_state & LED_STATE_CLAIMED)
163 hw_led_state |= AMBER_LED;
164 break;
165 case led_amber_off:
166 if (led_state & LED_STATE_CLAIMED)
167 hw_led_state &= ~AMBER_LED;
168 break;
169
170 /* "red" == LED on tps gpio3 (rightmost) */
171 case led_red_on:
172 if (led_state & LED_STATE_CLAIMED)
173 hw_led_state |= RED_LED;
174 break;
175 case led_red_off:
176 if (led_state & LED_STATE_CLAIMED)
177 hw_led_state &= ~RED_LED;
178 break;
179
180 default: 107 default:
181 break; 108 break;
182 } 109 }
183 110
184 leds ^= hw_led_state; 111 leds ^= hw_led_state;
185 leds &= TPS_LEDS;
186 if (leds && (led_state & LED_STATE_CLAIMED)) {
187 tps_leds_change |= leds;
188 schedule_work(&work);
189 }
190 112
191done: 113done:
192 local_irq_restore(flags); 114 local_irq_restore(flags);
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 52c70e5fcf6..e207bf7cb85 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -3,9 +3,9 @@
3 * 3 *
4 * OMAP1 pin multiplexing configurations 4 * OMAP1 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2003 - 2005 Nokia Corporation 6 * Copyright (C) 2003 - 2008 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
@@ -32,8 +32,10 @@
32 32
33#ifdef CONFIG_OMAP_MUX 33#ifdef CONFIG_OMAP_MUX
34 34
35static struct omap_mux_cfg arch_mux_cfg;
36
35#ifdef CONFIG_ARCH_OMAP730 37#ifdef CONFIG_ARCH_OMAP730
36struct pin_config __initdata_or_module omap730_pins[] = { 38static struct pin_config __initdata_or_module omap730_pins[] = {
37MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) 39MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
38MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) 40MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0)
39MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) 41MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0)
@@ -49,10 +51,14 @@ MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0)
49MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) 51MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0)
50MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) 52MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0)
51}; 53};
52#endif 54#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins)
55#else
56#define omap730_pins NULL
57#define OMAP730_PINS_SZ 0
58#endif /* CONFIG_ARCH_OMAP730 */
53 59
54#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) 60#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
55struct pin_config __initdata_or_module omap1xxx_pins[] = { 61static struct pin_config __initdata_or_module omap1xxx_pins[] = {
56/* 62/*
57 * description mux mode mux pull pull pull pu_pd pu dbg 63 * description mux mode mux pull pull pull pu_pd pu dbg
58 * reg offset mode reg bit ena reg 64 * reg offset mode reg bit ena reg
@@ -306,22 +312,136 @@ MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
306MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) 312MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
307MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) 313MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
308MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) 314MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
309
310}; 315};
316#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
317#else
318#define omap1xxx_pins NULL
319#define OMAP1XXX_PINS_SZ 0
311#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ 320#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
312 321
313int __init omap1_mux_init(void) 322int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
314{ 323{
315 324 static DEFINE_SPINLOCK(mux_spin_lock);
316#ifdef CONFIG_ARCH_OMAP730 325 unsigned long flags;
317 omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins)); 326 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
327 pull_orig = 0, pull = 0;
328 unsigned int mask, warn = 0;
329
330 /* Check the mux register in question */
331 if (cfg->mux_reg) {
332 unsigned tmp1, tmp2;
333
334 spin_lock_irqsave(&mux_spin_lock, flags);
335 reg_orig = omap_readl(cfg->mux_reg);
336
337 /* The mux registers always seem to be 3 bits long */
338 mask = (0x7 << cfg->mask_offset);
339 tmp1 = reg_orig & mask;
340 reg = reg_orig & ~mask;
341
342 tmp2 = (cfg->mask << cfg->mask_offset);
343 reg |= tmp2;
344
345 if (tmp1 != tmp2)
346 warn = 1;
347
348 omap_writel(reg, cfg->mux_reg);
349 spin_unlock_irqrestore(&mux_spin_lock, flags);
350 }
351
352 /* Check for pull up or pull down selection on 1610 */
353 if (!cpu_is_omap15xx()) {
354 if (cfg->pu_pd_reg && cfg->pull_val) {
355 spin_lock_irqsave(&mux_spin_lock, flags);
356 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
357 mask = 1 << cfg->pull_bit;
358
359 if (cfg->pu_pd_val) {
360 if (!(pu_pd_orig & mask))
361 warn = 1;
362 /* Use pull up */
363 pu_pd = pu_pd_orig | mask;
364 } else {
365 if (pu_pd_orig & mask)
366 warn = 1;
367 /* Use pull down */
368 pu_pd = pu_pd_orig & ~mask;
369 }
370 omap_writel(pu_pd, cfg->pu_pd_reg);
371 spin_unlock_irqrestore(&mux_spin_lock, flags);
372 }
373 }
374
375 /* Check for an associated pull down register */
376 if (cfg->pull_reg) {
377 spin_lock_irqsave(&mux_spin_lock, flags);
378 pull_orig = omap_readl(cfg->pull_reg);
379 mask = 1 << cfg->pull_bit;
380
381 if (cfg->pull_val) {
382 if (pull_orig & mask)
383 warn = 1;
384 /* Low bit = pull enabled */
385 pull = pull_orig & ~mask;
386 } else {
387 if (!(pull_orig & mask))
388 warn = 1;
389 /* High bit = pull disabled */
390 pull = pull_orig | mask;
391 }
392
393 omap_writel(pull, cfg->pull_reg);
394 spin_unlock_irqrestore(&mux_spin_lock, flags);
395 }
396
397 if (warn) {
398#ifdef CONFIG_OMAP_MUX_WARNINGS
399 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
318#endif 400#endif
319 401 }
320#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) 402
321 omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins)); 403#ifdef CONFIG_OMAP_MUX_DEBUG
404 if (cfg->debug || warn) {
405 printk("MUX: Setting register %s\n", cfg->name);
406 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
407 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
408
409 if (!cpu_is_omap15xx()) {
410 if (cfg->pu_pd_reg && cfg->pull_val) {
411 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
412 cfg->pu_pd_name, cfg->pu_pd_reg,
413 pu_pd_orig, pu_pd);
414 }
415 }
416
417 if (cfg->pull_reg)
418 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
419 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
420 }
322#endif 421#endif
323 422
423#ifdef CONFIG_OMAP_MUX_ERRORS
424 return warn ? -ETXTBSY : 0;
425#else
324 return 0; 426 return 0;
427#endif
428}
429
430int __init omap1_mux_init(void)
431{
432 if (cpu_is_omap730()) {
433 arch_mux_cfg.pins = omap730_pins;
434 arch_mux_cfg.size = OMAP730_PINS_SZ;
435 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
436 }
437
438 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
439 arch_mux_cfg.pins = omap1xxx_pins;
440 arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
441 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
442 }
443
444 return omap_mux_register(&arch_mux_cfg);
325} 445}
326 446
327#endif 447#endif
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a4f8b205543..5d2b270935a 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -56,37 +56,6 @@
56#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE 56#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
57#define OMAP_MPU_TIMER_OFFSET 0x100 57#define OMAP_MPU_TIMER_OFFSET 0x100
58 58
59/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
60 * converted to use kHz by Kevin Hilman */
61/* convert from cycles(64bits) => nanoseconds (64bits)
62 * basic equation:
63 * ns = cycles / (freq / ns_per_sec)
64 * ns = cycles * (ns_per_sec / freq)
65 * ns = cycles * (10^9 / (cpu_khz * 10^3))
66 * ns = cycles * (10^6 / cpu_khz)
67 *
68 * Then we use scaling math (suggested by george at mvista.com) to get:
69 * ns = cycles * (10^6 * SC / cpu_khz / SC
70 * ns = cycles * cyc2ns_scale / SC
71 *
72 * And since SC is a constant power of two, we can convert the div
73 * into a shift.
74 * -johnstul at us.ibm.com "math is hard, lets go shopping!"
75 */
76static unsigned long cyc2ns_scale;
77#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
78
79static inline void set_cyc2ns_scale(unsigned long cpu_khz)
80{
81 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
82}
83
84static inline unsigned long long cycles_2_ns(unsigned long long cyc)
85{
86 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
87}
88
89
90typedef struct { 59typedef struct {
91 u32 cntl; /* CNTL_TIMER, R/W */ 60 u32 cntl; /* CNTL_TIMER, R/W */
92 u32 load_tim; /* LOAD_TIM, W */ 61 u32 load_tim; /* LOAD_TIM, W */
@@ -194,8 +163,6 @@ static struct irqaction omap_mpu_timer1_irq = {
194 163
195static __init void omap_init_mpu_timer(unsigned long rate) 164static __init void omap_init_mpu_timer(unsigned long rate)
196{ 165{
197 set_cyc2ns_scale(rate / 1000);
198
199 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); 166 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
200 omap_mpu_timer_start(0, (rate / HZ) - 1, 1); 167 omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
201 168
@@ -260,22 +227,6 @@ static void __init omap_init_clocksource(unsigned long rate)
260 printk(err, clocksource_mpu.name); 227 printk(err, clocksource_mpu.name);
261} 228}
262 229
263
264/*
265 * Scheduler clock - returns current time in nanosec units.
266 */
267unsigned long long sched_clock(void)
268{
269 unsigned long ticks = 0 - omap_mpu_timer_read(1);
270 unsigned long long ticks64;
271
272 ticks64 = omap_mpu_timer2_overflows;
273 ticks64 <<= 32;
274 ticks64 |= ticks;
275
276 return cycles_2_ns(ticks64);
277}
278
279/* 230/*
280 * --------------------------------------------------------------------------- 231 * ---------------------------------------------------------------------------
281 * Timer initialization 232 * Timer initialization
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index ea76f1979a3..fbbdb806c95 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/timer32k.c 2 * linux/arch/arm/mach-omap1/timer32k.c
3 * 3 *
4 * OMAP 32K Timer 4 * OMAP 32K Timer
5 * 5 *
@@ -70,8 +70,6 @@ struct sys_timer omap_timer;
70 70
71#if defined(CONFIG_ARCH_OMAP16XX) 71#if defined(CONFIG_ARCH_OMAP16XX)
72#define TIMER_32K_SYNCHRONIZED 0xfffbc410 72#define TIMER_32K_SYNCHRONIZED 0xfffbc410
73#elif defined(CONFIG_ARCH_OMAP24XX)
74#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10)
75#else 73#else
76#error OMAP 32KHz timer does not currently work on 15XX! 74#error OMAP 32KHz timer does not currently work on 15XX!
77#endif 75#endif
@@ -93,8 +91,6 @@ struct sys_timer omap_timer;
93#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 91#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
94 (((nr_jiffies) * (clock_rate)) / HZ) 92 (((nr_jiffies) * (clock_rate)) / HZ)
95 93
96#if defined(CONFIG_ARCH_OMAP1)
97
98static inline void omap_32k_timer_write(int val, int reg) 94static inline void omap_32k_timer_write(int val, int reg)
99{ 95{
100 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 96 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +116,14 @@ static inline void omap_32k_timer_stop(void)
120 116
121#define omap_32k_timer_ack_irq() 117#define omap_32k_timer_ack_irq()
122 118
123#elif defined(CONFIG_ARCH_OMAP2) 119static int omap_32k_timer_set_next_event(unsigned long delta,
124 120 struct clock_event_device *dev)
125static struct omap_dm_timer *gptimer;
126
127static inline void omap_32k_timer_start(unsigned long load_val)
128{
129 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
130 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
131 omap_dm_timer_start(gptimer);
132}
133
134static inline void omap_32k_timer_stop(void)
135{ 121{
136 omap_dm_timer_stop(gptimer); 122 omap_32k_timer_start(delta);
137}
138 123
139static inline void omap_32k_timer_ack_irq(void) 124 return 0;
140{
141 u32 status = omap_dm_timer_read_status(gptimer);
142 omap_dm_timer_write_status(gptimer, status);
143} 125}
144 126
145#endif
146
147static void omap_32k_timer_set_mode(enum clock_event_mode mode, 127static void omap_32k_timer_set_mode(enum clock_event_mode mode,
148 struct clock_event_device *evt) 128 struct clock_event_device *evt)
149{ 129{
@@ -164,8 +144,9 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
164 144
165static struct clock_event_device clockevent_32k_timer = { 145static struct clock_event_device clockevent_32k_timer = {
166 .name = "32k-timer", 146 .name = "32k-timer",
167 .features = CLOCK_EVT_FEAT_PERIODIC, 147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
168 .shift = 32, 148 .shift = 32,
149 .set_next_event = omap_32k_timer_set_next_event,
169 .set_mode = omap_32k_timer_set_mode, 150 .set_mode = omap_32k_timer_set_mode,
170}; 151};
171 152
@@ -178,32 +159,6 @@ static inline unsigned long omap_32k_sync_timer_read(void)
178 return omap_readl(TIMER_32K_SYNCHRONIZED); 159 return omap_readl(TIMER_32K_SYNCHRONIZED);
179} 160}
180 161
181/*
182 * Rounds down to nearest usec. Note that this will overflow for larger values.
183 */
184static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
185{
186 return (ticks_32k * 5*5*5*5*5*5) >> 9;
187}
188
189/*
190 * Rounds down to nearest nsec.
191 */
192static inline unsigned long long
193omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
194{
195 return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
196}
197
198/*
199 * Returns current time from boot in nsecs. It's OK for this to wrap
200 * around for now, as it's just a relative time stamp.
201 */
202unsigned long long sched_clock(void)
203{
204 return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
205}
206
207static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 162static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
208{ 163{
209 struct clock_event_device *evt = &clockevent_32k_timer; 164 struct clock_event_device *evt = &clockevent_32k_timer;
@@ -222,22 +177,7 @@ static struct irqaction omap_32k_timer_irq = {
222 177
223static __init void omap_init_32k_timer(void) 178static __init void omap_init_32k_timer(void)
224{ 179{
225 if (cpu_class_is_omap1()) 180 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
226 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
227
228#ifdef CONFIG_ARCH_OMAP2
229 /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
230 if (cpu_is_omap24xx()) {
231 gptimer = omap_dm_timer_request_specific(1);
232 BUG_ON(gptimer == NULL);
233
234 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
235 setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
236 omap_dm_timer_set_int_enable(gptimer,
237 OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
238 OMAP_TIMER_INT_MATCH);
239 }
240#endif
241 181
242 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, 182 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
243 NSEC_PER_SEC, 183 NSEC_PER_SEC,
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b05b738d31e..2feb6870b73 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,13 +3,15 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ 6obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
7 serial.o gpmc.o 7 devices.o serial.o gpmc.o timer-gp.o
8
9obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
10 8
11# Power Management 9# Power Management
12obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o 10obj-$(CONFIG_PM) += pm.o sleep.o
11
12# Clock framework
13obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
14obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
13 15
14# Specific board support 16# Specific board support
15obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 17obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 64235dee561..1c12d7c6c7f 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
33#include <asm/arch/board.h> 33#include <asm/arch/board.h>
34#include <asm/arch/common.h> 34#include <asm/arch/common.h>
35#include <asm/arch/gpmc.h> 35#include <asm/arch/gpmc.h>
36#include "prcm-regs.h"
37 36
38#include <asm/io.h> 37#include <asm/io.h>
39 38
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void)
125 int eth_cs; 124 int eth_cs;
126 unsigned long cs_mem_base; 125 unsigned long cs_mem_base;
127 unsigned int rate; 126 unsigned int rate;
128 struct clk *l3ck; 127 struct clk *gpmc_fck;
129 128
130 eth_cs = SDP2430_SMC91X_CS; 129 eth_cs = SDP2430_SMC91X_CS;
131 130
132 l3ck = clk_get(NULL, "core_l3_ck"); 131 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
133 if (IS_ERR(l3ck)) 132 if (IS_ERR(gpmc_fck)) {
134 rate = 100000000; 133 WARN_ON(1);
135 else 134 return;
136 rate = clk_get_rate(l3ck); 135 }
136
137 clk_enable(gpmc_fck);
138 rate = clk_get_rate(gpmc_fck);
137 139
138 /* Make sure CS1 timings are correct, for 2430 always muxed */ 140 /* Make sure CS1 timings are correct, for 2430 always muxed */
139 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); 141 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void)
160 162
161 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { 163 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
162 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); 164 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
163 return; 165 goto out;
164 } 166 }
165 167
166 sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; 168 sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void)
171 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 173 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
172 OMAP24XX_ETHR_GPIO_IRQ); 174 OMAP24XX_ETHR_GPIO_IRQ);
173 gpmc_cs_free(eth_cs); 175 gpmc_cs_free(eth_cs);
174 return; 176 goto out;
175 } 177 }
176 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); 178 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
177 179
180out:
181 clk_disable(gpmc_fck);
182 clk_put(gpmc_fck);
178} 183}
179 184
180static void __init omap_2430sdp_init_irq(void) 185static void __init omap_2430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7846551f057..a1e1e6765b5 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,8 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/leds.h> 28#include <linux/leds.h>
29#include <linux/err.h>
30#include <linux/clk.h>
29 31
30#include <asm/hardware.h> 32#include <asm/hardware.h>
31#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -39,7 +41,7 @@
39#include <asm/arch/board.h> 41#include <asm/arch/board.h>
40#include <asm/arch/common.h> 42#include <asm/arch/common.h>
41#include <asm/arch/gpmc.h> 43#include <asm/arch/gpmc.h>
42#include "prcm-regs.h" 44#include <asm/arch/control.h>
43 45
44/* LED & Switch macros */ 46/* LED & Switch macros */
45#define LED0_GPIO13 13 47#define LED0_GPIO13 13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void)
187{ 189{
188 unsigned long base; 190 unsigned long base;
189 191
192 unsigned int rate;
193 struct clk *gpmc_fck;
194 int eth_cs;
195
196 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
197 if (IS_ERR(gpmc_fck)) {
198 WARN_ON(1);
199 return;
200 }
201
202 clk_enable(gpmc_fck);
203 rate = clk_get_rate(gpmc_fck);
204
205 eth_cs = APOLLON_ETH_CS;
206
190 /* Make sure CS1 timings are correct */ 207 /* Make sure CS1 timings are correct */
191 GPMC_CONFIG1_1 = 0x00011203; 208 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
192 GPMC_CONFIG2_1 = 0x001f1f01; 209
193 GPMC_CONFIG3_1 = 0x00080803; 210 if (rate >= 160000000) {
194 GPMC_CONFIG4_1 = 0x1c091c09; 211 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
195 GPMC_CONFIG5_1 = 0x041f1f1f; 212 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
196 GPMC_CONFIG6_1 = 0x000004c4; 213 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
214 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
215 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
216 } else if (rate >= 130000000) {
217 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
218 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
219 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
220 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
221 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
222 } else {/* rate = 100000000 */
223 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
224 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
225 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
226 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
227 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
228 }
197 229
198 if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { 230 if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
199 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); 231 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
200 return; 232 goto out;
201 } 233 }
202 apollon_smc91x_resources[0].start = base + 0x300; 234 apollon_smc91x_resources[0].start = base + 0x300;
203 apollon_smc91x_resources[0].end = base + 0x30f; 235 apollon_smc91x_resources[0].end = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void)
208 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
209 APOLLON_ETHR_GPIO_IRQ); 241 APOLLON_ETHR_GPIO_IRQ);
210 gpmc_cs_free(APOLLON_ETH_CS); 242 gpmc_cs_free(APOLLON_ETH_CS);
211 return; 243 goto out;
212 } 244 }
213 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); 245 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
246
247out:
248 clk_disable(gpmc_fck);
249 clk_put(gpmc_fck);
214} 250}
215 251
216static void __init omap_apollon_init_irq(void) 252static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void)
330 366
331static void __init omap_apollon_init(void) 367static void __init omap_apollon_init(void)
332{ 368{
369 u32 v;
370
333 apollon_led_init(); 371 apollon_led_init();
334 apollon_sw_init(); 372 apollon_sw_init();
335 apollon_flash_init(); 373 apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void)
339 omap_cfg_reg(W19_24XX_SYS_NIRQ); 377 omap_cfg_reg(W19_24XX_SYS_NIRQ);
340 378
341 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ 379 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
342 CONTROL_DEVCONF |= (1 << 24); 380 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
381 v |= (1 << 24);
382 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
343 383
344 /* 384 /*
345 * Make sure the serial ports are muxed on at this point. 385 * Make sure the serial ports are muxed on at this point.
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f125f432cc3..d1915f99a5f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/workqueue.h> 20#include <linux/workqueue.h>
21#include <linux/input.h> 21#include <linux/input.h>
22#include <linux/err.h>
23#include <linux/clk.h>
22 24
23#include <asm/hardware.h> 25#include <asm/hardware.h>
24#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -26,6 +28,7 @@
26#include <asm/mach/map.h> 28#include <asm/mach/map.h>
27#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
28 30
31#include <asm/arch/control.h>
29#include <asm/arch/gpio.h> 32#include <asm/arch/gpio.h>
30#include <asm/arch/gpioexpander.h> 33#include <asm/arch/gpioexpander.h>
31#include <asm/arch/mux.h> 34#include <asm/arch/mux.h>
@@ -36,10 +39,13 @@
36#include <asm/arch/keypad.h> 39#include <asm/arch/keypad.h>
37#include <asm/arch/menelaus.h> 40#include <asm/arch/menelaus.h>
38#include <asm/arch/dma.h> 41#include <asm/arch/dma.h>
39#include "prcm-regs.h" 42#include <asm/arch/gpmc.h>
40 43
41#include <asm/io.h> 44#include <asm/io.h>
42 45
46#define H4_FLASH_CS 0
47#define H4_SMC91X_CS 1
48
43static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; 49static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
44static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; 50static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
45 51
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = {
116}; 122};
117 123
118static struct resource h4_flash_resource = { 124static struct resource h4_flash_resource = {
119 .start = H4_CS0_BASE,
120 .end = H4_CS0_BASE + SZ_64M - 1,
121 .flags = IORESOURCE_MEM, 125 .flags = IORESOURCE_MEM,
122}; 126};
123 127
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = {
253 &h4_lcd_device, 257 &h4_lcd_device,
254}; 258};
255 259
260/* 2420 Sysboot setup (2430 is different) */
261static u32 get_sysboot_value(void)
262{
263 return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
264 (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
265 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
266 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
267}
268
269/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
270 *
271 * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
272 * correctly. The macro needs to look at production_id not just hawkeye.
273 */
274static u32 is_gpmc_muxed(void)
275{
276 u32 mux;
277 mux = get_sysboot_value();
278 if ((mux & 0xF) == 0xd)
279 return 1; /* NAND config (could be either) */
280 if (mux & 0x2) /* if mux'ed */
281 return 1;
282 else
283 return 0;
284}
285
256static inline void __init h4_init_debug(void) 286static inline void __init h4_init_debug(void)
257{ 287{
288 int eth_cs;
289 unsigned long cs_mem_base;
290 unsigned int muxed, rate;
291 struct clk *gpmc_fck;
292
293 eth_cs = H4_SMC91X_CS;
294
295 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
296 if (IS_ERR(gpmc_fck)) {
297 WARN_ON(1);
298 return;
299 }
300
301 clk_enable(gpmc_fck);
302 rate = clk_get_rate(gpmc_fck);
303 clk_disable(gpmc_fck);
304 clk_put(gpmc_fck);
305
306 if (is_gpmc_muxed())
307 muxed = 0x200;
308 else
309 muxed = 0;
310
258 /* Make sure CS1 timings are correct */ 311 /* Make sure CS1 timings are correct */
259 GPMC_CONFIG1_1 = 0x00011200; 312 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
260 GPMC_CONFIG2_1 = 0x001f1f01; 313 0x00011000 | muxed);
261 GPMC_CONFIG3_1 = 0x00080803; 314
262 GPMC_CONFIG4_1 = 0x1c091c09; 315 if (rate >= 160000000) {
263 GPMC_CONFIG5_1 = 0x041f1f1f; 316 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
264 GPMC_CONFIG6_1 = 0x000004c4; 317 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
265 GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24); 318 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
319 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
320 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
321 } else if (rate >= 130000000) {
322 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
323 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
324 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
325 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
326 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
327 } else {/* rate = 100000000 */
328 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
329 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
330 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
331 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
332 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
333 }
334
335 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
336 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
337 goto out;
338 }
339
266 udelay(100); 340 udelay(100);
267 341
268 omap_cfg_reg(M15_24XX_GPIO92); 342 omap_cfg_reg(M15_24XX_GPIO92);
269 if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) 343 if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
270 gpmc_cs_free(eth_cs); 344 gpmc_cs_free(eth_cs);
345
346out:
347 clk_disable(gpmc_fck);
348 clk_put(gpmc_fck);
349}
350
351static void __init h4_init_flash(void)
352{
353 unsigned long base;
354
355 if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
356 printk("Can't request GPMC CS for flash\n");
357 return;
358 }
359 h4_flash_resource.start = base;
360 h4_flash_resource.end = base + SZ_64M - 1;
271} 361}
272 362
273static void __init omap_h4_init_irq(void) 363static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void)
275 omap2_init_common_hw(); 365 omap2_init_common_hw();
276 omap_init_irq(); 366 omap_init_irq();
277 omap_gpio_init(); 367 omap_gpio_init();
368 h4_init_flash();
278} 369}
279 370
280static struct omap_uart_config h4_uart_config __initdata = { 371static struct omap_uart_config h4_uart_config __initdata = {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e6e85b7b097..b57ffb5a22a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1,20 +1,19 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock.c 2 * linux/arch/arm/mach-omap2/clock.c
3 * 3 *
4 * Copyright (C) 2005 Texas Instruments Inc. 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Richard Woodruff <r-woodruff2@ti.com> 5 * Copyright (C) 2004-2008 Nokia Corporation
6 * Created for OMAP2.
7 *
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
10 * 6 *
11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation 7 * Contacts:
12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
13 * 10 *
14 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
17 */ 14 */
15#undef DEBUG
16
18#include <linux/module.h> 17#include <linux/module.h>
19#include <linux/kernel.h> 18#include <linux/kernel.h>
20#include <linux/device.h> 19#include <linux/device.h>
@@ -22,176 +21,227 @@
22#include <linux/errno.h> 21#include <linux/errno.h>
23#include <linux/delay.h> 22#include <linux/delay.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
24#include <asm/bitops.h>
25 25
26#include <asm/io.h> 26#include <asm/io.h>
27 27
28#include <asm/arch/clock.h> 28#include <asm/arch/clock.h>
29#include <asm/arch/sram.h> 29#include <asm/arch/sram.h>
30#include <asm/arch/cpu.h>
30#include <asm/div64.h> 31#include <asm/div64.h>
31 32
32#include "prcm-regs.h"
33#include "memory.h" 33#include "memory.h"
34#include "sdrc.h"
34#include "clock.h" 35#include "clock.h"
36#include "prm.h"
37#include "prm-regbits-24xx.h"
38#include "cm.h"
39#include "cm-regbits-24xx.h"
40#include "cm-regbits-34xx.h"
35 41
36#undef DEBUG 42#define MAX_CLOCK_ENABLE_WAIT 100000
37
38//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
39 43
40static struct prcm_config *curr_prcm_set; 44u8 cpu_mask;
41static u32 curr_perf_level = PRCM_FULL_SPEED;
42static struct clk *vclk;
43static struct clk *sclk;
44 45
45/*------------------------------------------------------------------------- 46/*-------------------------------------------------------------------------
46 * Omap2 specific clock functions 47 * Omap2 specific clock functions
47 *-------------------------------------------------------------------------*/ 48 *-------------------------------------------------------------------------*/
48 49
49/* Recalculate SYST_CLK */ 50/**
50static void omap2_sys_clk_recalc(struct clk * clk) 51 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
52 * @clk: OMAP clock struct ptr to use
53 *
54 * Given a pointer to a source-selectable struct clk, read the hardware
55 * register and determine what its parent is currently set to. Update the
56 * clk->parent field with the appropriate clk ptr.
57 */
58void omap2_init_clksel_parent(struct clk *clk)
51{ 59{
52 u32 div = PRCM_CLKSRC_CTRL; 60 const struct clksel *clks;
53 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ 61 const struct clksel_rate *clkr;
54 div >>= clk->rate_offset; 62 u32 r, found = 0;
55 clk->rate = (clk->parent->rate / div); 63
56 propagate_rate(clk); 64 if (!clk->clksel)
65 return;
66
67 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
68 r >>= __ffs(clk->clksel_mask);
69
70 for (clks = clk->clksel; clks->parent && !found; clks++) {
71 for (clkr = clks->rates; clkr->div && !found; clkr++) {
72 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
73 if (clk->parent != clks->parent) {
74 pr_debug("clock: inited %s parent "
75 "to %s (was %s)\n",
76 clk->name, clks->parent->name,
77 ((clk->parent) ?
78 clk->parent->name : "NULL"));
79 clk->parent = clks->parent;
80 };
81 found = 1;
82 }
83 }
84 }
85
86 if (!found)
87 printk(KERN_ERR "clock: init parent: could not find "
88 "regval %0x for clock %s\n", r, clk->name);
89
90 return;
57} 91}
58 92
59static u32 omap2_get_dpll_rate(struct clk * tclk) 93/* Returns the DPLL rate */
94u32 omap2_get_dpll_rate(struct clk *clk)
60{ 95{
61 long long dpll_clk; 96 long long dpll_clk;
62 int dpll_mult, dpll_div, amult; 97 u32 dpll_mult, dpll_div, dpll;
98 const struct dpll_data *dd;
99
100 dd = clk->dpll_data;
101 /* REVISIT: What do we return on error? */
102 if (!dd)
103 return 0;
104
105 dpll = __raw_readl(dd->mult_div1_reg);
106 dpll_mult = dpll & dd->mult_mask;
107 dpll_mult >>= __ffs(dd->mult_mask);
108 dpll_div = dpll & dd->div1_mask;
109 dpll_div >>= __ffs(dd->div1_mask);
63 110
64 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ 111 dpll_clk = (long long)clk->parent->rate * dpll_mult;
65 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
66 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
67 do_div(dpll_clk, dpll_div + 1); 112 do_div(dpll_clk, dpll_div + 1);
68 amult = CM_CLKSEL2_PLL & 0x3;
69 dpll_clk *= amult;
70 113
71 return dpll_clk; 114 return dpll_clk;
72} 115}
73 116
74static void omap2_followparent_recalc(struct clk *clk) 117/*
75{ 118 * Used for clocks that have the same value as the parent clock,
76 followparent_recalc(clk); 119 * divided by some factor
77} 120 */
78 121void omap2_fixed_divisor_recalc(struct clk *clk)
79static void omap2_propagate_rate(struct clk * clk)
80{ 122{
81 if (!(clk->flags & RATE_FIXED)) 123 WARN_ON(!clk->fixed_div);
82 clk->rate = clk->parent->rate;
83 124
84 propagate_rate(clk); 125 clk->rate = clk->parent->rate / clk->fixed_div;
85}
86 126
87static void omap2_set_osc_ck(int enable) 127 if (clk->flags & RATE_PROPAGATES)
88{ 128 propagate_rate(clk);
89 if (enable)
90 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
91 else
92 PRCM_CLKSRC_CTRL |= 0x3 << 3;
93} 129}
94 130
95/* Enable an APLL if off */ 131/**
96static void omap2_clk_fixed_enable(struct clk *clk) 132 * omap2_wait_clock_ready - wait for clock to enable
133 * @reg: physical address of clock IDLEST register
134 * @mask: value to mask against to determine if the clock is active
135 * @name: name of the clock (for printk)
136 *
137 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
138 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
139 */
140int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
97{ 141{
98 u32 cval, i=0; 142 int i = 0;
143 int ena = 0;
99 144
100 if (clk->enable_bit == 0xff) /* Parent will do it */ 145 /*
101 return; 146 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
147 * 34xx reverses this, just to keep us on our toes
148 */
149 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
150 ena = mask;
151 } else if (cpu_mask & RATE_IN_343X) {
152 ena = 0;
153 }
102 154
103 cval = CM_CLKEN_PLL; 155 /* Wait for lock */
156 while (((__raw_readl(reg) & mask) != ena) &&
157 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
158 udelay(1);
159 }
104 160
105 if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) 161 if (i < MAX_CLOCK_ENABLE_WAIT)
106 return; 162 pr_debug("Clock %s stable after %d loops\n", name, i);
163 else
164 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
165 name, MAX_CLOCK_ENABLE_WAIT);
107 166
108 cval &= ~(0x3 << clk->enable_bit);
109 cval |= (0x3 << clk->enable_bit);
110 CM_CLKEN_PLL = cval;
111 167
112 if (clk == &apll96_ck) 168 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
113 cval = (1 << 8); 169};
114 else if (clk == &apll54_ck)
115 cval = (1 << 6);
116 170
117 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
118 ++i;
119 udelay(1);
120 if (i == 100000) {
121 printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
122 break;
123 }
124 }
125}
126 171
172/*
173 * Note: We don't need special code here for INVERT_ENABLE
174 * for the time being since INVERT_ENABLE only applies to clocks enabled by
175 * CM_CLKEN_PLL
176 */
127static void omap2_clk_wait_ready(struct clk *clk) 177static void omap2_clk_wait_ready(struct clk *clk)
128{ 178{
129 unsigned long reg, other_reg, st_reg; 179 void __iomem *reg, *other_reg, *st_reg;
130 u32 bit; 180 u32 bit;
131 int i; 181
132 182 /*
133 reg = (unsigned long) clk->enable_reg; 183 * REVISIT: This code is pretty ugly. It would be nice to generalize
134 if (reg == (unsigned long) &CM_FCLKEN1_CORE || 184 * it and pull it into struct clk itself somehow.
135 reg == (unsigned long) &CM_FCLKEN2_CORE) 185 */
136 other_reg = (reg & ~0xf0) | 0x10; 186 reg = clk->enable_reg;
137 else if (reg == (unsigned long) &CM_ICLKEN1_CORE || 187 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
138 reg == (unsigned long) &CM_ICLKEN2_CORE) 188 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
139 other_reg = (reg & ~0xf0) | 0x00; 189 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
190 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
191 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
192 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
140 else 193 else
141 return; 194 return;
142 195
196 /* REVISIT: What are the appropriate exclusions for 34XX? */
143 /* No check for DSS or cam clocks */ 197 /* No check for DSS or cam clocks */
144 if ((reg & 0x0f) == 0) { 198 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
145 if (clk->enable_bit <= 1 || clk->enable_bit == 31) 199 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
200 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
201 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
146 return; 202 return;
147 } 203 }
148 204
205 /* REVISIT: What are the appropriate exclusions for 34XX? */
206 /* OMAP3: ignore DSS-mod clocks */
207 if (cpu_is_omap34xx() &&
208 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
209 return;
210
149 /* Check if both functional and interface clocks 211 /* Check if both functional and interface clocks
150 * are running. */ 212 * are running. */
151 bit = 1 << clk->enable_bit; 213 bit = 1 << clk->enable_bit;
152 if (!(__raw_readl(other_reg) & bit)) 214 if (!(__raw_readl(other_reg) & bit))
153 return; 215 return;
154 st_reg = (other_reg & ~0xf0) | 0x20; 216 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
155 i = 0; 217
156 while (!(__raw_readl(st_reg) & bit)) { 218 omap2_wait_clock_ready(st_reg, bit, clk->name);
157 i++;
158 if (i == 100000) {
159 printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
160 break;
161 }
162 }
163 if (i)
164 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
165} 219}
166 220
167/* Enables clock without considering parent dependencies or use count 221/* Enables clock without considering parent dependencies or use count
168 * REVISIT: Maybe change this to use clk->enable like on omap1? 222 * REVISIT: Maybe change this to use clk->enable like on omap1?
169 */ 223 */
170static int _omap2_clk_enable(struct clk * clk) 224int _omap2_clk_enable(struct clk *clk)
171{ 225{
172 u32 regval32; 226 u32 regval32;
173 227
174 if (clk->flags & ALWAYS_ENABLED) 228 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
175 return 0; 229 return 0;
176 230
177 if (unlikely(clk == &osc_ck)) { 231 if (clk->enable)
178 omap2_set_osc_ck(1); 232 return clk->enable(clk);
179 return 0;
180 }
181 233
182 if (unlikely(clk->enable_reg == 0)) { 234 if (unlikely(clk->enable_reg == 0)) {
183 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 235 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
184 clk->name); 236 clk->name);
185 return 0; 237 return 0; /* REVISIT: -EINVAL */
186 }
187
188 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
189 omap2_clk_fixed_enable(clk);
190 return 0;
191 } 238 }
192 239
193 regval32 = __raw_readl(clk->enable_reg); 240 regval32 = __raw_readl(clk->enable_reg);
194 regval32 |= (1 << clk->enable_bit); 241 if (clk->flags & INVERT_ENABLE)
242 regval32 &= ~(1 << clk->enable_bit);
243 else
244 regval32 |= (1 << clk->enable_bit);
195 __raw_writel(regval32, clk->enable_reg); 245 __raw_writel(regval32, clk->enable_reg);
196 wmb(); 246 wmb();
197 247
@@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk)
200 return 0; 250 return 0;
201} 251}
202 252
203/* Stop APLL */
204static void omap2_clk_fixed_disable(struct clk *clk)
205{
206 u32 cval;
207
208 if(clk->enable_bit == 0xff) /* let parent off do it */
209 return;
210
211 cval = CM_CLKEN_PLL;
212 cval &= ~(0x3 << clk->enable_bit);
213 CM_CLKEN_PLL = cval;
214}
215
216/* Disables clock without considering parent dependencies or use count */ 253/* Disables clock without considering parent dependencies or use count */
217static void _omap2_clk_disable(struct clk *clk) 254void _omap2_clk_disable(struct clk *clk)
218{ 255{
219 u32 regval32; 256 u32 regval32;
220 257
221 if (unlikely(clk == &osc_ck)) { 258 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
222 omap2_set_osc_ck(0);
223 return; 259 return;
224 }
225 260
226 if (clk->enable_reg == 0) 261 if (clk->disable) {
262 clk->disable(clk);
227 return; 263 return;
264 }
228 265
229 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { 266 if (clk->enable_reg == 0) {
230 omap2_clk_fixed_disable(clk); 267 /*
268 * 'Independent' here refers to a clock which is not
269 * controlled by its parent.
270 */
271 printk(KERN_ERR "clock: clk_disable called on independent "
272 "clock %s which has no enable_reg\n", clk->name);
231 return; 273 return;
232 } 274 }
233 275
234 regval32 = __raw_readl(clk->enable_reg); 276 regval32 = __raw_readl(clk->enable_reg);
235 regval32 &= ~(1 << clk->enable_bit); 277 if (clk->flags & INVERT_ENABLE)
278 regval32 |= (1 << clk->enable_bit);
279 else
280 regval32 &= ~(1 << clk->enable_bit);
236 __raw_writel(regval32, clk->enable_reg); 281 __raw_writel(regval32, clk->enable_reg);
237 wmb(); 282 wmb();
238} 283}
239 284
240static int omap2_clk_enable(struct clk *clk) 285void omap2_clk_disable(struct clk *clk)
286{
287 if (clk->usecount > 0 && !(--clk->usecount)) {
288 _omap2_clk_disable(clk);
289 if (likely((u32)clk->parent))
290 omap2_clk_disable(clk->parent);
291 }
292}
293
294int omap2_clk_enable(struct clk *clk)
241{ 295{
242 int ret = 0; 296 int ret = 0;
243 297
@@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk)
261 return ret; 315 return ret;
262} 316}
263 317
264static void omap2_clk_disable(struct clk *clk)
265{
266 if (clk->usecount > 0 && !(--clk->usecount)) {
267 _omap2_clk_disable(clk);
268 if (likely((u32)clk->parent))
269 omap2_clk_disable(clk->parent);
270 }
271}
272
273/*
274 * Uses the current prcm set to tell if a rate is valid.
275 * You can go slower, but not faster within a given rate set.
276 */
277static u32 omap2_dpll_round_rate(unsigned long target_rate)
278{
279 u32 high, low;
280
281 if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
282 high = curr_prcm_set->dpll_speed * 2;
283 low = curr_prcm_set->dpll_speed;
284 } else { /* DPLL clockout x 2 */
285 high = curr_prcm_set->dpll_speed;
286 low = curr_prcm_set->dpll_speed / 2;
287 }
288
289#ifdef DOWN_VARIABLE_DPLL
290 if (target_rate > high)
291 return high;
292 else
293 return target_rate;
294#else
295 if (target_rate > low)
296 return high;
297 else
298 return low;
299#endif
300
301}
302
303/* 318/*
304 * Used for clocks that are part of CLKSEL_xyz governed clocks. 319 * Used for clocks that are part of CLKSEL_xyz governed clocks.
305 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 320 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
306 */ 321 */
307static void omap2_clksel_recalc(struct clk * clk) 322void omap2_clksel_recalc(struct clk *clk)
308{ 323{
309 u32 fixed = 0, div = 0; 324 u32 div = 0;
310 325
311 if (clk == &dpll_ck) { 326 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
312 clk->rate = omap2_get_dpll_rate(clk);
313 fixed = 1;
314 div = 0;
315 }
316 327
317 if (clk == &iva1_mpu_int_ifck) { 328 div = omap2_clksel_get_divisor(clk);
318 div = 2; 329 if (div == 0)
319 fixed = 1;
320 }
321
322 if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
323 clk->rate = sys_ck.rate;
324 return; 330 return;
325 }
326 331
327 if (!fixed) { 332 if (unlikely(clk->rate == clk->parent->rate / div))
328 div = omap2_clksel_get_divisor(clk); 333 return;
329 if (div == 0) 334 clk->rate = clk->parent->rate / div;
330 return;
331 }
332 335
333 if (div != 0) { 336 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
334 if (unlikely(clk->rate == clk->parent->rate / div))
335 return;
336 clk->rate = clk->parent->rate / div;
337 }
338 337
339 if (unlikely(clk->flags & RATE_PROPAGATES)) 338 if (unlikely(clk->flags & RATE_PROPAGATES))
340 propagate_rate(clk); 339 propagate_rate(clk);
341} 340}
342 341
343/* 342/**
344 * Finds best divider value in an array based on the source and target 343 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
345 * rates. The divider array must be sorted with smallest divider first. 344 * @clk: OMAP struct clk ptr to inspect
345 * @src_clk: OMAP struct clk ptr of the parent clk to search for
346 *
347 * Scan the struct clksel array associated with the clock to find
348 * the element associated with the supplied parent clock address.
349 * Returns a pointer to the struct clksel on success or NULL on error.
346 */ 350 */
347static inline u32 omap2_divider_from_table(u32 size, u32 *div_array, 351const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
348 u32 src_rate, u32 tgt_rate) 352 struct clk *src_clk)
349{ 353{
350 int i, test_rate; 354 const struct clksel *clks;
351 355
352 if (div_array == NULL) 356 if (!clk->clksel)
353 return ~1; 357 return NULL;
354 358
355 for (i=0; i < size; i++) { 359 for (clks = clk->clksel; clks->parent; clks++) {
356 test_rate = src_rate / *div_array; 360 if (clks->parent == src_clk)
357 if (test_rate <= tgt_rate) 361 break; /* Found the requested parent */
358 return *div_array;
359 ++div_array;
360 } 362 }
361 363
362 return ~0; /* No acceptable divider */ 364 if (!clks->parent) {
365 printk(KERN_ERR "clock: Could not find parent clock %s in "
366 "clksel array of clock %s\n", src_clk->name,
367 clk->name);
368 return NULL;
369 }
370
371 return clks;
363} 372}
364 373
365/* 374/**
366 * Find divisor for the given clock and target rate. 375 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
376 * @clk: OMAP struct clk to use
377 * @target_rate: desired clock rate
378 * @new_div: ptr to where we should store the divisor
367 * 379 *
380 * Finds 'best' divider value in an array based on the source and target
381 * rates. The divider array must be sorted with smallest divider first.
368 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 382 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
369 * they are only settable as part of virtual_prcm set. 383 * they are only settable as part of virtual_prcm set.
384 *
385 * Returns the rounded clock rate or returns 0xffffffff on error.
370 */ 386 */
371static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate, 387u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
372 u32 *new_div) 388 u32 *new_div)
373{ 389{
374 u32 gfx_div[] = {2, 3, 4}; 390 unsigned long test_rate;
375 u32 sysclkout_div[] = {1, 2, 4, 8, 16}; 391 const struct clksel *clks;
376 u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16}; 392 const struct clksel_rate *clkr;
377 u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18}; 393 u32 last_div = 0;
378 u32 best_div = ~0, asize = 0; 394
379 u32 *div_array = NULL; 395 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
380 396 clk->name, target_rate);
381 switch (tclk->flags & SRC_RATE_SEL_MASK) { 397
382 case CM_GFX_SEL1: 398 *new_div = 1;
383 asize = 3; 399
384 div_array = gfx_div; 400 clks = omap2_get_clksel_by_parent(clk, clk->parent);
385 break; 401 if (clks == NULL)
386 case CM_PLL_SEL1: 402 return ~0;
387 return omap2_dpll_round_rate(target_rate); 403
388 case CM_SYSCLKOUT_SEL1: 404 for (clkr = clks->rates; clkr->div; clkr++) {
389 asize = 5; 405 if (!(clkr->flags & cpu_mask))
390 div_array = sysclkout_div; 406 continue;
391 break; 407
392 case CM_CORE_SEL1: 408 /* Sanity check */
393 if(tclk == &dss1_fck){ 409 if (clkr->div <= last_div)
394 if(tclk->parent == &core_ck){ 410 printk(KERN_ERR "clock: clksel_rate table not sorted "
395 asize = 10; 411 "for clock %s", clk->name);
396 div_array = dss1_div; 412
397 } else { 413 last_div = clkr->div;
398 *new_div = 0; /* fixed clk */ 414
399 return(tclk->parent->rate); 415 test_rate = clk->parent->rate / clkr->div;
400 } 416
401 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){ 417 if (test_rate <= target_rate)
402 if(tclk->parent == &core_ck){ 418 break; /* found it */
403 asize = 10;
404 div_array = vylnq_div;
405 } else {
406 *new_div = 0; /* fixed clk */
407 return(tclk->parent->rate);
408 }
409 }
410 break;
411 } 419 }
412 420
413 best_div = omap2_divider_from_table(asize, div_array, 421 if (!clkr->div) {
414 tclk->parent->rate, target_rate); 422 printk(KERN_ERR "clock: Could not find divisor for target "
415 if (best_div == ~0){ 423 "rate %ld for clock %s parent %s\n", target_rate,
416 *new_div = 1; 424 clk->name, clk->parent->name);
417 return best_div; /* signal error */ 425 return ~0;
418 } 426 }
419 427
420 *new_div = best_div; 428 *new_div = clkr->div;
421 return (tclk->parent->rate / best_div); 429
430 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
431 (clk->parent->rate / clkr->div));
432
433 return (clk->parent->rate / clkr->div);
422} 434}
423 435
424/* Given a clock and a rate apply a clock specific rounding function */ 436/**
425static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 437 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
438 * @clk: OMAP struct clk to use
439 * @target_rate: desired clock rate
440 *
441 * Compatibility wrapper for OMAP clock framework
442 * Finds best target rate based on the source clock and possible dividers.
443 * rates. The divider array must be sorted with smallest divider first.
444 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
445 * they are only settable as part of virtual_prcm set.
446 *
447 * Returns the rounded clock rate or returns 0xffffffff on error.
448 */
449long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
426{ 450{
427 u32 new_div = 0; 451 u32 new_div;
428 int valid_rate;
429 452
430 if (clk->flags & RATE_FIXED) 453 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
431 return clk->rate; 454}
432 455
433 if (clk->flags & RATE_CKCTL) {
434 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
435 return valid_rate;
436 }
437 456
457/* Given a clock and a rate apply a clock specific rounding function */
458long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
459{
438 if (clk->round_rate != 0) 460 if (clk->round_rate != 0)
439 return clk->round_rate(clk, rate); 461 return clk->round_rate(clk, rate);
440 462
463 if (clk->flags & RATE_FIXED)
464 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
465 "on fixed-rate clock %s\n", clk->name);
466
441 return clk->rate; 467 return clk->rate;
442} 468}
443 469
444/* 470/**
445 * Check the DLL lock state, and return tue if running in unlock mode. 471 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
446 * This is needed to compensate for the shifted DLL value in unlock mode. 472 * @clk: OMAP struct clk to use
473 * @field_val: register field value to find
474 *
475 * Given a struct clk of a rate-selectable clksel clock, and a register field
476 * value to search for, find the corresponding clock divisor. The register
477 * field value should be pre-masked and shifted down so the LSB is at bit 0
478 * before calling. Returns 0 on error
447 */ 479 */
448static u32 omap2_dll_force_needed(void) 480u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
449{ 481{
450 u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */ 482 const struct clksel *clks;
483 const struct clksel_rate *clkr;
451 484
452 if ((dll_state & (1 << 2)) == (1 << 2)) 485 clks = omap2_get_clksel_by_parent(clk, clk->parent);
453 return 1; 486 if (clks == NULL)
454 else
455 return 0; 487 return 0;
456}
457 488
458static u32 omap2_reprogram_sdrc(u32 level, u32 force) 489 for (clkr = clks->rates; clkr->div; clkr++) {
459{ 490 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
460 u32 slow_dll_ctrl, fast_dll_ctrl, m_type; 491 break;
461 u32 prev = curr_perf_level, flags;
462
463 if ((curr_perf_level == level) && !force)
464 return prev;
465
466 m_type = omap2_memory_get_type();
467 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
468 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
469
470 if (level == PRCM_HALF_SPEED) {
471 local_irq_save(flags);
472 PRCM_VOLTSETUP = 0xffff;
473 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
474 slow_dll_ctrl, m_type);
475 curr_perf_level = PRCM_HALF_SPEED;
476 local_irq_restore(flags);
477 } 492 }
478 if (level == PRCM_FULL_SPEED) { 493
479 local_irq_save(flags); 494 if (!clkr->div) {
480 PRCM_VOLTSETUP = 0xffff; 495 printk(KERN_ERR "clock: Could not find fieldval %d for "
481 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, 496 "clock %s parent %s\n", field_val, clk->name,
482 fast_dll_ctrl, m_type); 497 clk->parent->name);
483 curr_perf_level = PRCM_FULL_SPEED; 498 return 0;
484 local_irq_restore(flags);
485 } 499 }
486 500
487 return prev; 501 return clkr->div;
488} 502}
489 503
490static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) 504/**
505 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
506 * @clk: OMAP struct clk to use
507 * @div: integer divisor to search for
508 *
509 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
510 * find the corresponding register field value. The return register value is
511 * the value before left-shifting. Returns 0xffffffff on error
512 */
513u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
491{ 514{
492 u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; 515 const struct clksel *clks;
493 u32 bypass = 0; 516 const struct clksel_rate *clkr;
494 struct prcm_config tmpset;
495 int ret = -EINVAL;
496 517
497 local_irq_save(flags); 518 /* should never happen */
498 cur_rate = omap2_get_dpll_rate(&dpll_ck); 519 WARN_ON(div == 0);
499 mult = CM_CLKSEL2_PLL & 0x3;
500
501 if ((rate == (cur_rate / 2)) && (mult == 2)) {
502 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
503 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
504 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
505 } else if (rate != cur_rate) {
506 valid_rate = omap2_dpll_round_rate(rate);
507 if (valid_rate != rate)
508 goto dpll_exit;
509
510 if ((CM_CLKSEL2_PLL & 0x3) == 1)
511 low = curr_prcm_set->dpll_speed;
512 else
513 low = curr_prcm_set->dpll_speed / 2;
514
515 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
516 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
517 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
518 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
519 tmpset.cm_clksel2_pll &= ~0x3;
520 if (rate > low) {
521 tmpset.cm_clksel2_pll |= 0x2;
522 mult = ((rate / 2) / 1000000);
523 done_rate = PRCM_FULL_SPEED;
524 } else {
525 tmpset.cm_clksel2_pll |= 0x1;
526 mult = (rate / 1000000);
527 done_rate = PRCM_HALF_SPEED;
528 }
529 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
530
531 /* Worst case */
532 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
533
534 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
535 bypass = 1;
536 520
537 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ 521 clks = omap2_get_clksel_by_parent(clk, clk->parent);
538 522 if (clks == NULL)
539 /* Force dll lock mode */ 523 return 0;
540 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
541 bypass);
542 524
543 /* Errata: ret dll entry state */ 525 for (clkr = clks->rates; clkr->div; clkr++) {
544 omap2_init_memory_params(omap2_dll_force_needed()); 526 if ((clkr->flags & cpu_mask) && (clkr->div == div))
545 omap2_reprogram_sdrc(done_rate, 0); 527 break;
546 } 528 }
547 omap2_clksel_recalc(&dpll_ck);
548 ret = 0;
549 529
550dpll_exit: 530 if (!clkr->div) {
551 local_irq_restore(flags); 531 printk(KERN_ERR "clock: Could not find divisor %d for "
552 return(ret); 532 "clock %s parent %s\n", div, clk->name,
553} 533 clk->parent->name);
534 return 0;
535 }
554 536
555/* Just return the MPU speed */ 537 return clkr->val;
556static void omap2_mpu_recalc(struct clk * clk)
557{
558 clk->rate = curr_prcm_set->mpu_speed;
559} 538}
560 539
561/* 540/**
562 * Look for a rate equal or less than the target rate given a configuration set. 541 * omap2_get_clksel - find clksel register addr & field mask for a clk
542 * @clk: struct clk to use
543 * @field_mask: ptr to u32 to store the register field mask
563 * 544 *
564 * What's not entirely clear is "which" field represents the key field. 545 * Returns the address of the clksel register upon success or NULL on error.
565 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
566 * just uses the ARM rates.
567 */ 546 */
568static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) 547void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
569{ 548{
570 struct prcm_config * ptr; 549 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
571 long highest_rate; 550 return NULL;
572
573 if (clk != &virt_prcm_set)
574 return -EINVAL;
575
576 highest_rate = -EINVAL;
577
578 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
579 if (ptr->xtal_speed != sys_ck.rate)
580 continue;
581 551
582 highest_rate = ptr->mpu_speed; 552 *field_mask = clk->clksel_mask;
583 553
584 /* Can check only after xtal frequency check */ 554 return clk->clksel_reg;
585 if (ptr->mpu_speed <= rate)
586 break;
587 }
588 return highest_rate;
589} 555}
590 556
591/* 557/**
592 * omap2_convert_field_to_div() - turn field value into integer divider 558 * omap2_clksel_get_divisor - get current divider applied to parent clock.
559 * @clk: OMAP struct clk to use.
560 *
561 * Returns the integer divisor upon success or 0 on error.
593 */ 562 */
594static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val) 563u32 omap2_clksel_get_divisor(struct clk *clk)
595{ 564{
596 u32 i; 565 u32 field_mask, field_val;
597 u32 clkout_array[] = {1, 2, 4, 8, 16}; 566 void __iomem *div_addr;
598 567
599 if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) { 568 div_addr = omap2_get_clksel(clk, &field_mask);
600 for (i = 0; i < 5; i++) { 569 if (div_addr == 0)
601 if (field_val == i) 570 return 0;
602 return clkout_array[i]; 571
603 } 572 field_val = __raw_readl(div_addr) & field_mask;
604 return ~0; 573 field_val >>= __ffs(field_mask);
605 } else 574
606 return field_val; 575 return omap2_clksel_to_divisor(clk, field_val);
607} 576}
608 577
609/* 578int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
610 * Returns the CLKSEL divider register value
611 * REVISIT: This should be cleaned up to work nicely with void __iomem *
612 */
613static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
614 struct clk *clk)
615{ 579{
616 int ret = ~0; 580 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
617 u32 reg_val, div_off; 581 void __iomem *div_addr;
618 u32 div_addr = 0;
619 u32 mask = ~0;
620
621 div_off = clk->rate_offset;
622
623 switch ((*div_sel & SRC_RATE_SEL_MASK)) {
624 case CM_MPU_SEL1:
625 div_addr = (u32)&CM_CLKSEL_MPU;
626 mask = 0x1f;
627 break;
628 case CM_DSP_SEL1:
629 div_addr = (u32)&CM_CLKSEL_DSP;
630 if (cpu_is_omap2420()) {
631 if ((div_off == 0) || (div_off == 8))
632 mask = 0x1f;
633 else if (div_off == 5)
634 mask = 0x3;
635 } else if (cpu_is_omap2430()) {
636 if (div_off == 0)
637 mask = 0x1f;
638 else if (div_off == 5)
639 mask = 0x3;
640 }
641 break;
642 case CM_GFX_SEL1:
643 div_addr = (u32)&CM_CLKSEL_GFX;
644 if (div_off == 0)
645 mask = 0x7;
646 break;
647 case CM_MODEM_SEL1:
648 div_addr = (u32)&CM_CLKSEL_MDM;
649 if (div_off == 0)
650 mask = 0xf;
651 break;
652 case CM_SYSCLKOUT_SEL1:
653 div_addr = (u32)&PRCM_CLKOUT_CTRL;
654 if ((div_off == 3) || (div_off == 11))
655 mask= 0x3;
656 break;
657 case CM_CORE_SEL1:
658 div_addr = (u32)&CM_CLKSEL1_CORE;
659 switch (div_off) {
660 case 0: /* l3 */
661 case 8: /* dss1 */
662 case 15: /* vylnc-2420 */
663 case 20: /* ssi */
664 mask = 0x1f; break;
665 case 5: /* l4 */
666 mask = 0x3; break;
667 case 13: /* dss2 */
668 mask = 0x1; break;
669 case 25: /* usb */
670 mask = 0x7; break;
671 }
672 }
673 582
674 *field_mask = mask; 583 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
584 if (validrate != rate)
585 return -EINVAL;
675 586
676 if (unlikely(mask == ~0)) 587 div_addr = omap2_get_clksel(clk, &field_mask);
677 div_addr = 0; 588 if (div_addr == 0)
589 return -EINVAL;
678 590
679 *div_sel = div_addr; 591 field_val = omap2_divisor_to_clksel(clk, new_div);
592 if (field_val == ~0)
593 return -EINVAL;
680 594
681 if (unlikely(div_addr == 0)) 595 reg_val = __raw_readl(div_addr);
682 return ret; 596 reg_val &= ~field_mask;
597 reg_val |= (field_val << __ffs(field_mask));
598 __raw_writel(reg_val, div_addr);
599 wmb();
683 600
684 /* Isolate field */ 601 clk->rate = clk->parent->rate / new_div;
685 reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
686 602
687 /* Normalize back to divider value */ 603 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
688 reg_val >>= div_off; 604 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
605 wmb();
606 }
689 607
690 return reg_val; 608 return 0;
691} 609}
692 610
693/*
694 * Return divider to be applied to parent clock.
695 * Return 0 on error.
696 */
697static u32 omap2_clksel_get_divisor(struct clk *clk)
698{
699 int ret = 0;
700 u32 div, div_sel, div_off, field_mask, field_val;
701
702 /* isolate control register */
703 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
704
705 div_off = clk->rate_offset;
706 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
707 if (div_sel == 0)
708 return ret;
709
710 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
711 div = omap2_clksel_to_divisor(div_sel, field_val);
712
713 return div;
714}
715 611
716/* Set the clock rate for a clock source */ 612/* Set the clock rate for a clock source */
717static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 613int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
718
719{ 614{
720 int ret = -EINVAL; 615 int ret = -EINVAL;
721 void __iomem * reg;
722 u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
723 u32 new_div = 0;
724
725 if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
726 if (clk == &dpll_ck)
727 return omap2_reprogram_dpll(clk, rate);
728
729 /* Isolate control register */
730 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
731 div_off = clk->rate_offset;
732
733 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
734 if (validrate != rate)
735 return(ret);
736 616
737 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 617 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
738 if (div_sel == 0)
739 return ret;
740
741 if (clk->flags & CM_SYSCLKOUT_SEL1) {
742 switch (new_div) {
743 case 16:
744 field_val = 4;
745 break;
746 case 8:
747 field_val = 3;
748 break;
749 case 4:
750 field_val = 2;
751 break;
752 case 2:
753 field_val = 1;
754 break;
755 case 1:
756 field_val = 0;
757 break;
758 }
759 } else
760 field_val = new_div;
761 618
762 reg = (void __iomem *)div_sel; 619 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
763 620 rate table mechanism, driven by mpu_speed */
764 reg_val = __raw_readl(reg); 621 if (clk->flags & CONFIG_PARTICIPANT)
765 reg_val &= ~(field_mask << div_off); 622 return -EINVAL;
766 reg_val |= (field_val << div_off);
767 __raw_writel(reg_val, reg);
768 wmb();
769 clk->rate = clk->parent->rate / field_val;
770 623
771 if (clk->flags & DELAYED_APP) { 624 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
772 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 625 if (clk->set_rate != 0)
773 wmb();
774 }
775 ret = 0;
776 } else if (clk->set_rate != 0)
777 ret = clk->set_rate(clk, rate); 626 ret = clk->set_rate(clk, rate);
778 627
779 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 628 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
782 return ret; 631 return ret;
783} 632}
784 633
785/* Converts encoded control register address into a full address */ 634/*
786static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, 635 * Converts encoded control register address into a full address
787 struct clk *src_clk, u32 *field_mask) 636 * On error, *src_addr will be returned as 0.
788{ 637 */
789 u32 val = ~0, src_reg_addr = 0, mask = 0; 638static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
790 639 struct clk *src_clk, u32 *field_mask,
791 /* Find target control register.*/ 640 struct clk *clk, u32 *parent_div)
792 switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
793 case CM_CORE_SEL1:
794 src_reg_addr = (u32)&CM_CLKSEL1_CORE;
795 if (reg_offset == 13) { /* DSS2_fclk */
796 mask = 0x1;
797 if (src_clk == &sys_ck)
798 val = 0;
799 if (src_clk == &func_48m_ck)
800 val = 1;
801 } else if (reg_offset == 8) { /* DSS1_fclk */
802 mask = 0x1f;
803 if (src_clk == &sys_ck)
804 val = 0;
805 else if (src_clk == &core_ck) /* divided clock */
806 val = 0x10; /* rate needs fixing */
807 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
808 mask = 0x1F;
809 if(src_clk == &func_96m_ck)
810 val = 0;
811 else if (src_clk == &core_ck)
812 val = 0x10;
813 }
814 break;
815 case CM_CORE_SEL2:
816 src_reg_addr = (u32)&CM_CLKSEL2_CORE;
817 mask = 0x3;
818 if (src_clk == &func_32k_ck)
819 val = 0x0;
820 if (src_clk == &sys_ck)
821 val = 0x1;
822 if (src_clk == &alt_ck)
823 val = 0x2;
824 break;
825 case CM_WKUP_SEL1:
826 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
827 mask = 0x3;
828 if (src_clk == &func_32k_ck)
829 val = 0x0;
830 if (src_clk == &sys_ck)
831 val = 0x1;
832 if (src_clk == &alt_ck)
833 val = 0x2;
834 break;
835 case CM_PLL_SEL1:
836 src_reg_addr = (u32)&CM_CLKSEL1_PLL;
837 mask = 0x1;
838 if (reg_offset == 0x3) {
839 if (src_clk == &apll96_ck)
840 val = 0;
841 if (src_clk == &alt_ck)
842 val = 1;
843 }
844 else if (reg_offset == 0x5) {
845 if (src_clk == &apll54_ck)
846 val = 0;
847 if (src_clk == &alt_ck)
848 val = 1;
849 }
850 break;
851 case CM_PLL_SEL2:
852 src_reg_addr = (u32)&CM_CLKSEL2_PLL;
853 mask = 0x3;
854 if (src_clk == &func_32k_ck)
855 val = 0x0;
856 if (src_clk == &dpll_ck)
857 val = 0x2;
858 break;
859 case CM_SYSCLKOUT_SEL1:
860 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
861 mask = 0x3;
862 if (src_clk == &dpll_ck)
863 val = 0;
864 if (src_clk == &sys_ck)
865 val = 1;
866 if (src_clk == &func_96m_ck)
867 val = 2;
868 if (src_clk == &func_54m_ck)
869 val = 3;
870 break;
871 }
872
873 if (val == ~0) /* Catch errors in offset */
874 *type_to_addr = 0;
875 else
876 *type_to_addr = src_reg_addr;
877 *field_mask = mask;
878
879 return val;
880}
881
882static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
883{ 641{
884 void __iomem * reg; 642 const struct clksel *clks;
885 u32 src_sel, src_off, field_val, field_mask, reg_val, rate; 643 const struct clksel_rate *clkr;
886 int ret = -EINVAL;
887
888 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
889 return ret;
890
891 if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
892 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
893 src_off = clk->src_offset;
894
895 if (src_sel == 0)
896 goto set_parent_error;
897
898 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
899 &field_mask);
900
901 reg = (void __iomem *)src_sel;
902
903 if (clk->usecount > 0)
904 _omap2_clk_disable(clk);
905
906 /* Set new source value (previous dividers if any in effect) */
907 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
908 reg_val |= (field_val << src_off);
909 __raw_writel(reg_val, reg);
910 wmb();
911 644
912 if (clk->flags & DELAYED_APP) { 645 *parent_div = 0;
913 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 646 *src_addr = 0;
914 wmb();
915 }
916 if (clk->usecount > 0)
917 _omap2_clk_enable(clk);
918
919 clk->parent = new_parent;
920 647
921 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/ 648 clks = omap2_get_clksel_by_parent(clk, src_clk);
922 if ((new_parent == &core_ck) && (clk == &dss1_fck)) 649 if (clks == NULL)
923 clk->rate = new_parent->rate / 0x10; 650 return 0;
924 else
925 clk->rate = new_parent->rate;
926 651
927 if (unlikely(clk->flags & RATE_PROPAGATES)) 652 for (clkr = clks->rates; clkr->div; clkr++) {
928 propagate_rate(clk); 653 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
654 break; /* Found the default rate for this platform */
655 }
929 656
657 if (!clkr->div) {
658 printk(KERN_ERR "clock: Could not find default rate for "
659 "clock %s parent %s\n", clk->name,
660 src_clk->parent->name);
930 return 0; 661 return 0;
931 } else {
932 clk->parent = new_parent;
933 rate = new_parent->rate;
934 omap2_clk_set_rate(clk, rate);
935 ret = 0;
936 } 662 }
937 663
938 set_parent_error: 664 /* Should never happen. Add a clksel mask to the struct clk. */
939 return ret; 665 WARN_ON(clk->clksel_mask == 0);
666
667 *field_mask = clk->clksel_mask;
668 *src_addr = clk->clksel_reg;
669 *parent_div = clkr->div;
670
671 return clkr->val;
940} 672}
941 673
942/* Sets basic clocks based on the specified rate */ 674int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
943static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
944{ 675{
945 u32 flags, cur_rate, done_rate, bypass = 0; 676 void __iomem *src_addr;
946 u8 cpu_mask = 0; 677 u32 field_val, field_mask, reg_val, parent_div;
947 struct prcm_config *prcm;
948 unsigned long found_speed = 0;
949 678
950 if (clk != &virt_prcm_set) 679 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
951 return -EINVAL; 680 return -EINVAL;
952 681
953 /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ 682 if (!clk->clksel)
954 if (cpu_is_omap2420())
955 cpu_mask = RATE_IN_242X;
956 else if (cpu_is_omap2430())
957 cpu_mask = RATE_IN_243X;
958
959 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
960 if (!(prcm->flags & cpu_mask))
961 continue;
962
963 if (prcm->xtal_speed != sys_ck.rate)
964 continue;
965
966 if (prcm->mpu_speed <= rate) {
967 found_speed = prcm->mpu_speed;
968 break;
969 }
970 }
971
972 if (!found_speed) {
973 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
974 rate / 1000000);
975 return -EINVAL; 683 return -EINVAL;
976 }
977
978 curr_prcm_set = prcm;
979 cur_rate = omap2_get_dpll_rate(&dpll_ck);
980
981 if (prcm->dpll_speed == cur_rate / 2) {
982 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
983 } else if (prcm->dpll_speed == cur_rate * 2) {
984 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
985 } else if (prcm->dpll_speed != cur_rate) {
986 local_irq_save(flags);
987 684
988 if (prcm->dpll_speed == prcm->xtal_speed) 685 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
989 bypass = 1; 686 &field_mask, clk, &parent_div);
687 if (src_addr == 0)
688 return -EINVAL;
990 689
991 if ((prcm->cm_clksel2_pll & 0x3) == 2) 690 if (clk->usecount > 0)
992 done_rate = PRCM_FULL_SPEED; 691 _omap2_clk_disable(clk);
993 else
994 done_rate = PRCM_HALF_SPEED;
995 692
996 /* MPU divider */ 693 /* Set new source value (previous dividers if any in effect) */
997 CM_CLKSEL_MPU = prcm->cm_clksel_mpu; 694 reg_val = __raw_readl(src_addr) & ~field_mask;
695 reg_val |= (field_val << __ffs(field_mask));
696 __raw_writel(reg_val, src_addr);
697 wmb();
998 698
999 /* dsp + iva1 div(2420), iva2.1(2430) */ 699 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
1000 CM_CLKSEL_DSP = prcm->cm_clksel_dsp; 700 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
701 wmb();
702 }
1001 703
1002 CM_CLKSEL_GFX = prcm->cm_clksel_gfx; 704 if (clk->usecount > 0)
705 _omap2_clk_enable(clk);
1003 706
1004 /* Major subsystem dividers */ 707 clk->parent = new_parent;
1005 CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
1006 if (cpu_is_omap2430())
1007 CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
1008 708
1009 /* x2 to enter init_mem */ 709 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
1010 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); 710 clk->rate = new_parent->rate;
1011 711
1012 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, 712 if (parent_div > 0)
1013 bypass); 713 clk->rate /= parent_div;
1014 714
1015 omap2_init_memory_params(omap2_dll_force_needed()); 715 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
1016 omap2_reprogram_sdrc(done_rate, 0); 716 clk->name, clk->parent->name, clk->rate);
1017 717
1018 local_irq_restore(flags); 718 if (unlikely(clk->flags & RATE_PROPAGATES))
1019 } 719 propagate_rate(clk);
1020 omap2_clksel_recalc(&dpll_ck);
1021 720
1022 return 0; 721 return 0;
1023} 722}
@@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
1027 *-------------------------------------------------------------------------*/ 726 *-------------------------------------------------------------------------*/
1028 727
1029#ifdef CONFIG_OMAP_RESET_CLOCKS 728#ifdef CONFIG_OMAP_RESET_CLOCKS
1030static void __init omap2_clk_disable_unused(struct clk *clk) 729void omap2_clk_disable_unused(struct clk *clk)
1031{ 730{
1032 u32 regval32; 731 u32 regval32, v;
732
733 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1033 734
1034 regval32 = __raw_readl(clk->enable_reg); 735 regval32 = __raw_readl(clk->enable_reg);
1035 if ((regval32 & (1 << clk->enable_bit)) == 0) 736 if ((regval32 & (1 << clk->enable_bit)) == v)
1036 return; 737 return;
1037 738
1038 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 739 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1039 _omap2_clk_disable(clk); 740 _omap2_clk_disable(clk);
1040} 741}
1041#else
1042#define omap2_clk_disable_unused NULL
1043#endif 742#endif
1044
1045static struct clk_functions omap2_clk_functions = {
1046 .clk_enable = omap2_clk_enable,
1047 .clk_disable = omap2_clk_disable,
1048 .clk_round_rate = omap2_clk_round_rate,
1049 .clk_set_rate = omap2_clk_set_rate,
1050 .clk_set_parent = omap2_clk_set_parent,
1051 .clk_disable_unused = omap2_clk_disable_unused,
1052};
1053
1054static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1055{
1056 u32 div, aplls, sclk = 13000000;
1057
1058 aplls = CM_CLKSEL1_PLL;
1059 aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
1060 aplls >>= 23; /* Isolate field, 0,2,3 */
1061
1062 if (aplls == 0)
1063 sclk = 19200000;
1064 else if (aplls == 2)
1065 sclk = 13000000;
1066 else if (aplls == 3)
1067 sclk = 12000000;
1068
1069 div = PRCM_CLKSRC_CTRL;
1070 div &= ((1 << 7) | (1 << 6));
1071 div >>= sys->rate_offset;
1072
1073 osc->rate = sclk * div;
1074 sys->rate = sclk;
1075}
1076
1077/*
1078 * Set clocks for bypass mode for reboot to work.
1079 */
1080void omap2_clk_prepare_for_reboot(void)
1081{
1082 u32 rate;
1083
1084 if (vclk == NULL || sclk == NULL)
1085 return;
1086
1087 rate = clk_get_rate(sclk);
1088 clk_set_rate(vclk, rate);
1089}
1090
1091/*
1092 * Switch the MPU rate if specified on cmdline.
1093 * We cannot do this early until cmdline is parsed.
1094 */
1095static int __init omap2_clk_arch_init(void)
1096{
1097 if (!mpurate)
1098 return -EINVAL;
1099
1100 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1101 printk(KERN_ERR "Could not find matching MPU rate\n");
1102
1103 propagate_rate(&osc_ck); /* update main root fast */
1104 propagate_rate(&func_32k_ck); /* update main root slow */
1105
1106 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1107 "%ld.%01ld/%ld/%ld MHz\n",
1108 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1109 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1110
1111 return 0;
1112}
1113arch_initcall(omap2_clk_arch_init);
1114
1115int __init omap2_clk_init(void)
1116{
1117 struct prcm_config *prcm;
1118 struct clk ** clkp;
1119 u32 clkrate;
1120
1121 clk_init(&omap2_clk_functions);
1122 omap2_get_crystal_rate(&osc_ck, &sys_ck);
1123
1124 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1125 clkp++) {
1126
1127 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1128 clk_register(*clkp);
1129 continue;
1130 }
1131
1132 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1133 clk_register(*clkp);
1134 continue;
1135 }
1136 }
1137
1138 /* Check the MPU rate set by bootloader */
1139 clkrate = omap2_get_dpll_rate(&dpll_ck);
1140 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1141 if (prcm->xtal_speed != sys_ck.rate)
1142 continue;
1143 if (prcm->dpll_speed <= clkrate)
1144 break;
1145 }
1146 curr_prcm_set = prcm;
1147
1148 propagate_rate(&osc_ck); /* update main root fast */
1149 propagate_rate(&func_32k_ck); /* update main root slow */
1150
1151 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1152 "%ld.%01ld/%ld/%ld MHz\n",
1153 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1154 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1155
1156 /*
1157 * Only enable those clocks we will need, let the drivers
1158 * enable other clocks as necessary
1159 */
1160 clk_enable(&sync_32k_ick);
1161 clk_enable(&omapctrl_ick);
1162
1163 /* Force the APLLs always active. The clocks are idled
1164 * automatically by hardware. */
1165 clk_enable(&apll96_ck);
1166 clk_enable(&apll54_ck);
1167
1168 if (cpu_is_omap2430())
1169 clk_enable(&sdrc_ick);
1170
1171 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1172 vclk = clk_get(NULL, "virt_prcm_set");
1173 sclk = clk_get(NULL, "sys_ck");
1174
1175 return 0;
1176}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4f791866b91..d5980a9e09a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,13 +1,12 @@
1/* 1/*
2 * linux/arch/arm/mach-omap24xx/clock.h 2 * linux/arch/arm/mach-omap2/clock.h
3 * 3 *
4 * Copyright (C) 2005 Texas Instruments Inc. 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Richard Woodruff <r-woodruff2@ti.com> 5 * Copyright (C) 2004-2008 Nokia Corporation
6 * Created for OMAP2.
7 * 6 *
8 * Copyright (C) 2004 Nokia corporation 7 * Contacts:
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 9 * Paul Walmsley
11 * 10 *
12 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -17,2095 +16,53 @@
17#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
18#define __ARCH_ARM_MACH_OMAP2_CLOCK_H 17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 18
20static void omap2_sys_clk_recalc(struct clk * clk); 19#include <asm/arch/clock.h>
21static void omap2_clksel_recalc(struct clk * clk);
22static void omap2_followparent_recalc(struct clk * clk);
23static void omap2_propagate_rate(struct clk * clk);
24static void omap2_mpu_recalc(struct clk * clk);
25static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
26static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
27static void omap2_clk_disable(struct clk *clk);
28static void omap2_sys_clk_recalc(struct clk * clk);
29static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
30static u32 omap2_clksel_get_divisor(struct clk *clk);
31
32
33#define RATE_IN_242X (1 << 0)
34#define RATE_IN_243X (1 << 1)
35
36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
39 */
40struct prcm_config {
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
52 unsigned char flags;
53};
54
55/* Mask for clksel which support parent settign in set_rate */
56#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
57 CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
58
59/* Mask for clksel regs which support rate operations */
60#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
61 CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
62 CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
63 CM_SYSCLKOUT_SEL1)
64
65/*
66 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
67 * These configurations are characterized by voltage and speed for clocks.
68 * The device is only validated for certain combinations. One way to express
69 * these combinations is via the 'ratio's' which the clocks operate with
70 * respect to each other. These ratio sets are for a given voltage/DPLL
71 * setting. All configurations can be described by a DPLL setting and a ratio
72 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
73 *
74 * 2430 differs from 2420 in that there are no more phase synchronizers used.
75 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
76 * 2430 (iva2.1, NOdsp, mdm)
77 */
78
79/* Core fields for cm_clksel, not ratio governed */
80#define RX_CLKSEL_DSS1 (0x10 << 8)
81#define RX_CLKSEL_DSS2 (0x0 << 13)
82#define RX_CLKSEL_SSI (0x5 << 20)
83
84/*-------------------------------------------------------------------------
85 * Voltage/DPLL ratios
86 *-------------------------------------------------------------------------*/
87
88/* 2430 Ratio's, 2430-Ratio Config 1 */
89#define R1_CLKSEL_L3 (4 << 0)
90#define R1_CLKSEL_L4 (2 << 5)
91#define R1_CLKSEL_USB (4 << 25)
92#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
93 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
94 R1_CLKSEL_L4 | R1_CLKSEL_L3
95#define R1_CLKSEL_MPU (2 << 0)
96#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
97#define R1_CLKSEL_DSP (2 << 0)
98#define R1_CLKSEL_DSP_IF (2 << 5)
99#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
100#define R1_CLKSEL_GFX (2 << 0)
101#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
102#define R1_CLKSEL_MDM (4 << 0)
103#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
104
105/* 2430-Ratio Config 2 */
106#define R2_CLKSEL_L3 (6 << 0)
107#define R2_CLKSEL_L4 (2 << 5)
108#define R2_CLKSEL_USB (2 << 25)
109#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
110 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
111 R2_CLKSEL_L4 | R2_CLKSEL_L3
112#define R2_CLKSEL_MPU (2 << 0)
113#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
114#define R2_CLKSEL_DSP (2 << 0)
115#define R2_CLKSEL_DSP_IF (3 << 5)
116#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
117#define R2_CLKSEL_GFX (2 << 0)
118#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
119#define R2_CLKSEL_MDM (6 << 0)
120#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
121
122/* 2430-Ratio Bootm (BYPASS) */
123#define RB_CLKSEL_L3 (1 << 0)
124#define RB_CLKSEL_L4 (1 << 5)
125#define RB_CLKSEL_USB (1 << 25)
126#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
127 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
128 RB_CLKSEL_L4 | RB_CLKSEL_L3
129#define RB_CLKSEL_MPU (1 << 0)
130#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
131#define RB_CLKSEL_DSP (1 << 0)
132#define RB_CLKSEL_DSP_IF (1 << 5)
133#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
134#define RB_CLKSEL_GFX (1 << 0)
135#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
136#define RB_CLKSEL_MDM (1 << 0)
137#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
138
139/* 2420 Ratio Equivalents */
140#define RXX_CLKSEL_VLYNQ (0x12 << 15)
141#define RXX_CLKSEL_SSI (0x8 << 20)
142
143/* 2420-PRCM III 532MHz core */
144#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
145#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
146#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
147#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
148 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
149 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
150 RIII_CLKSEL_L3
151#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
152#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
153#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
154#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
155#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
156#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
157#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
158#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
159 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
160 RIII_CLKSEL_DSP
161#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
162#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
163
164/* 2420-PRCM II 600MHz core */
165#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
166#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
167#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
168#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
169 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
170 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
171 RII_CLKSEL_L4 | RII_CLKSEL_L3
172#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
173#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
174#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
175#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
176#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
177#define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
178#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
179#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
180 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
181 RII_CLKSEL_DSP
182#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
183#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
184
185/* 2420-PRCM VII (boot) */
186#define RVII_CLKSEL_L3 (1 << 0)
187#define RVII_CLKSEL_L4 (1 << 5)
188#define RVII_CLKSEL_DSS1 (1 << 8)
189#define RVII_CLKSEL_DSS2 (0 << 13)
190#define RVII_CLKSEL_VLYNQ (1 << 15)
191#define RVII_CLKSEL_SSI (1 << 20)
192#define RVII_CLKSEL_USB (1 << 25)
193
194#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
195 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
196 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
197
198#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
199#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
200 20
201#define RVII_CLKSEL_DSP (1 << 0) 21int omap2_clk_enable(struct clk *clk);
202#define RVII_CLKSEL_DSP_IF (1 << 5) 22void omap2_clk_disable(struct clk *clk);
203#define RVII_SYNC_DSP (0 << 7) 23long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
204#define RVII_CLKSEL_IVA (1 << 8) 24int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
205#define RVII_SYNC_IVA (0 << 13) 25int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
206#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
207 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
208
209#define RVII_CLKSEL_GFX (1 << 0)
210#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
211
212/*-------------------------------------------------------------------------
213 * 2430 Target modes: Along with each configuration the CPU has several
214 * modes which goes along with them. Modes mainly are the addition of
215 * describe DPLL combinations to go along with a ratio.
216 *-------------------------------------------------------------------------*/
217
218/* Hardware governed */
219#define MX_48M_SRC (0 << 3)
220#define MX_54M_SRC (0 << 5)
221#define MX_APLLS_CLIKIN_12 (3 << 23)
222#define MX_APLLS_CLIKIN_13 (2 << 23)
223#define MX_APLLS_CLIKIN_19_2 (0 << 23)
224
225/*
226 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
227 * #2 (ratio1) baseport-target
228 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
229 */
230#define M5A_DPLL_MULT_12 (133 << 12)
231#define M5A_DPLL_DIV_12 (5 << 8)
232#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
233 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
234 MX_APLLS_CLIKIN_12
235#define M5A_DPLL_MULT_13 (266 << 12)
236#define M5A_DPLL_DIV_13 (12 << 8)
237#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
238 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
239 MX_APLLS_CLIKIN_13
240#define M5A_DPLL_MULT_19 (180 << 12)
241#define M5A_DPLL_DIV_19 (12 << 8)
242#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
244 MX_APLLS_CLIKIN_19_2
245/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
246#define M5B_DPLL_MULT_12 (50 << 12)
247#define M5B_DPLL_DIV_12 (2 << 8)
248#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
249 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
250 MX_APLLS_CLIKIN_12
251#define M5B_DPLL_MULT_13 (200 << 12)
252#define M5B_DPLL_DIV_13 (12 << 8)
253
254#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
255 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
256 MX_APLLS_CLIKIN_13
257#define M5B_DPLL_MULT_19 (125 << 12)
258#define M5B_DPLL_DIV_19 (31 << 8)
259#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
260 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
261 MX_APLLS_CLIKIN_19_2
262/*
263 * #4 (ratio2)
264 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
265 */
266#define M3_DPLL_MULT_12 (55 << 12)
267#define M3_DPLL_DIV_12 (1 << 8)
268#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
269 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
270 MX_APLLS_CLIKIN_12
271#define M3_DPLL_MULT_13 (330 << 12)
272#define M3_DPLL_DIV_13 (12 << 8)
273#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
274 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
275 MX_APLLS_CLIKIN_13
276#define M3_DPLL_MULT_19 (275 << 12)
277#define M3_DPLL_DIV_19 (15 << 8)
278#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
279 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
280 MX_APLLS_CLIKIN_19_2
281/* boot (boot) */
282#define MB_DPLL_MULT (1 << 12)
283#define MB_DPLL_DIV (0 << 8)
284#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
285 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
286
287#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
288 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
289
290#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
291 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
292
293/*
294 * 2430 - chassis (sedna)
295 * 165 (ratio1) same as above #2
296 * 150 (ratio1)
297 * 133 (ratio2) same as above #4
298 * 110 (ratio2) same as above #3
299 * 104 (ratio2)
300 * boot (boot)
301 */
302
303/*
304 * 2420 Equivalent - mode registers
305 * PRCM II , target DPLL = 2*300MHz = 600MHz
306 */
307#define MII_DPLL_MULT_12 (50 << 12)
308#define MII_DPLL_DIV_12 (1 << 8)
309#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
310 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
311 MX_APLLS_CLIKIN_12
312#define MII_DPLL_MULT_13 (300 << 12)
313#define MII_DPLL_DIV_13 (12 << 8)
314#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
315 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
316 MX_APLLS_CLIKIN_13
317
318/* PRCM III target DPLL = 2*266 = 532MHz*/
319#define MIII_DPLL_MULT_12 (133 << 12)
320#define MIII_DPLL_DIV_12 (5 << 8)
321#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324#define MIII_DPLL_MULT_13 (266 << 12)
325#define MIII_DPLL_DIV_13 (12 << 8)
326#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
328 MX_APLLS_CLIKIN_13
329
330/* PRCM VII (boot bypass) */
331#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
332#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
333
334/* High and low operation value */
335#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
336#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
337
338/*
339 * These represent optimal values for common parts, it won't work for all.
340 * As long as you scale down, most parameters are still work, they just
341 * become sub-optimal. The RFR value goes in the opposite direction. If you
342 * don't adjust it down as your clock period increases the refresh interval
343 * will not be met. Setting all parameters for complete worst case may work,
344 * but may cut memory performance by 2x. Due to errata the DLLs need to be
345 * unlocked and their value needs run time calibration. A dynamic call is
346 * need for that as no single right value exists acorss production samples.
347 *
348 * Only the FULL speed values are given. Current code is such that rate
349 * changes must be made at DPLLoutx2. The actual value adjustment for low
350 * frequency operation will be handled by omap_set_performance()
351 *
352 * By having the boot loader boot up in the fastest L4 speed available likely
353 * will result in something which you can switch between.
354 */
355#define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
356#define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
357#define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
358#define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
359
360/* MPU speed defines */
361#define S12M 12000000
362#define S13M 13000000
363#define S19M 19200000
364#define S26M 26000000
365#define S100M 100000000
366#define S133M 133000000
367#define S150M 150000000
368#define S165M 165000000
369#define S200M 200000000
370#define S266M 266000000
371#define S300M 300000000
372#define S330M 330000000
373#define S400M 400000000
374#define S532M 532000000
375#define S600M 600000000
376#define S660M 660000000
377
378/*-------------------------------------------------------------------------
379 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
380 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
381 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
382 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
383 *
384 * Filling in table based on H4 boards and 2430-SDPs variants available.
385 * There are quite a few more rates combinations which could be defined.
386 *
387 * When multiple values are defined the start up will try and choose the
388 * fastest one. If a 'fast' value is defined, then automatically, the /2
389 * one should be included as it can be used. Generally having more that
390 * one fast set does not make sense, as static timings need to be changed
391 * to change the set. The exception is the bypass setting which is
392 * availble for low power bypass.
393 *
394 * Note: This table needs to be sorted, fastest to slowest.
395 *-------------------------------------------------------------------------*/
396static struct prcm_config rate_table[] = {
397 /* PRCM II - FAST */
398 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
399 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
400 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
401 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
402 RATE_IN_242X},
403
404 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
405 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
406 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
407 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
408 RATE_IN_242X},
409
410 /* PRCM III - FAST */
411 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
412 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
413 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
414 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
415 RATE_IN_242X},
416
417 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
418 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
419 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
420 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
421 RATE_IN_242X},
422
423 /* PRCM II - SLOW */
424 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
425 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
426 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
427 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
428 RATE_IN_242X},
429
430 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
431 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
432 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
433 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
434 RATE_IN_242X},
435
436 /* PRCM III - SLOW */
437 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
438 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
439 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
440 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
441 RATE_IN_242X},
442
443 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
444 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
445 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
446 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
447 RATE_IN_242X},
448
449 /* PRCM-VII (boot-bypass) */
450 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
451 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
452 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
453 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
454 RATE_IN_242X},
455
456 /* PRCM-VII (boot-bypass) */
457 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
458 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
459 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
461 RATE_IN_242X},
462
463 /* PRCM #3 - ratio2 (ES2) - FAST */
464 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
465 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
466 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
468 V24XX_SDRC_RFR_CTRL_110MHz,
469 RATE_IN_243X},
470
471 /* PRCM #5a - ratio1 - FAST */
472 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
473 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
474 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
475 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
476 V24XX_SDRC_RFR_CTRL_133MHz,
477 RATE_IN_243X},
478
479 /* PRCM #5b - ratio1 - FAST */
480 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
481 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
482 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
483 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
484 V24XX_SDRC_RFR_CTRL_100MHz,
485 RATE_IN_243X},
486
487 /* PRCM #3 - ratio2 (ES2) - SLOW */
488 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
489 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
490 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
491 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
492 V24XX_SDRC_RFR_CTRL_110MHz,
493 RATE_IN_243X},
494
495 /* PRCM #5a - ratio1 - SLOW */
496 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
498 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
500 V24XX_SDRC_RFR_CTRL_133MHz,
501 RATE_IN_243X},
502
503 /* PRCM #5b - ratio1 - SLOW*/
504 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
505 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
506 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
507 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
508 V24XX_SDRC_RFR_CTRL_100MHz,
509 RATE_IN_243X},
510
511 /* PRCM-boot/bypass */
512 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
513 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
514 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
515 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
516 V24XX_SDRC_RFR_CTRL_BYPASS,
517 RATE_IN_243X},
518
519 /* PRCM-boot/bypass */
520 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
521 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
522 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
523 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
524 V24XX_SDRC_RFR_CTRL_BYPASS,
525 RATE_IN_243X},
526
527 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
528};
529
530/*-------------------------------------------------------------------------
531 * 24xx clock tree.
532 *
533 * NOTE:In many cases here we are assigning a 'default' parent. In many
534 * cases the parent is selectable. The get/set parent calls will also
535 * switch sources.
536 *
537 * Many some clocks say always_enabled, but they can be auto idled for
538 * power savings. They will always be available upon clock request.
539 *
540 * Several sources are given initial rates which may be wrong, this will
541 * be fixed up in the init func.
542 *
543 * Things are broadly separated below by clock domains. It is
544 * noteworthy that most periferals have dependencies on multiple clock
545 * domains. Many get their interface clocks from the L4 domain, but get
546 * functional clocks from fixed sources or other core domain derived
547 * clocks.
548 *-------------------------------------------------------------------------*/
549
550/* Base external input clocks */
551static struct clk func_32k_ck = {
552 .name = "func_32k_ck",
553 .rate = 32000,
554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
555 RATE_FIXED | ALWAYS_ENABLED,
556};
557
558/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
559static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
560 .name = "osc_ck",
561 .rate = 26000000, /* fixed up in clock init */
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
563 RATE_FIXED | RATE_PROPAGATES,
564};
565
566/* With out modem likely 12MHz, with modem likely 13MHz */
567static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
568 .name = "sys_ck", /* ~ ref_clk also */
569 .parent = &osc_ck,
570 .rate = 13000000,
571 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
572 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
573 .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */
574 .recalc = &omap2_sys_clk_recalc,
575};
576
577static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
578 .name = "alt_ck",
579 .rate = 54000000,
580 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
581 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
582 .recalc = &omap2_propagate_rate,
583};
584
585/*
586 * Analog domain root source clocks
587 */
588
589/* dpll_ck, is broken out in to special cases through clksel */
590static struct clk dpll_ck = {
591 .name = "dpll_ck",
592 .parent = &sys_ck, /* Can be func_32k also */
593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
594 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
595 .recalc = &omap2_clksel_recalc,
596};
597
598static struct clk apll96_ck = {
599 .name = "apll96_ck",
600 .parent = &sys_ck,
601 .rate = 96000000,
602 .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
603 RATE_FIXED | RATE_PROPAGATES,
604 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
605 .enable_bit = 0x2,
606 .recalc = &omap2_propagate_rate,
607};
608
609static struct clk apll54_ck = {
610 .name = "apll54_ck",
611 .parent = &sys_ck,
612 .rate = 54000000,
613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
614 RATE_FIXED | RATE_PROPAGATES,
615 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
616 .enable_bit = 0x6,
617 .recalc = &omap2_propagate_rate,
618};
619 26
620/* 27#ifdef CONFIG_OMAP_RESET_CLOCKS
621 * PRCM digital base sources 28void omap2_clk_disable_unused(struct clk *clk);
622 */ 29#else
623static struct clk func_54m_ck = { 30#define omap2_clk_disable_unused NULL
624 .name = "func_54m_ck", 31#endif
625 .parent = &apll54_ck, /* can also be alt_clk */
626 .rate = 54000000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
629 .src_offset = 5,
630 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
631 .enable_bit = 0xff,
632 .recalc = &omap2_propagate_rate,
633};
634
635static struct clk core_ck = {
636 .name = "core_ck",
637 .parent = &dpll_ck, /* can also be 32k */
638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
639 ALWAYS_ENABLED | RATE_PROPAGATES,
640 .recalc = &omap2_propagate_rate,
641};
642
643static struct clk sleep_ck = { /* sys_clk or 32k */
644 .name = "sleep_ck",
645 .parent = &func_32k_ck,
646 .rate = 32000,
647 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
648 .recalc = &omap2_propagate_rate,
649};
650
651static struct clk func_96m_ck = {
652 .name = "func_96m_ck",
653 .parent = &apll96_ck,
654 .rate = 96000000,
655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
656 RATE_FIXED | RATE_PROPAGATES,
657 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
658 .enable_bit = 0xff,
659 .recalc = &omap2_propagate_rate,
660};
661
662static struct clk func_48m_ck = {
663 .name = "func_48m_ck",
664 .parent = &apll96_ck, /* 96M or Alt */
665 .rate = 48000000,
666 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
667 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
668 .src_offset = 3,
669 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
670 .enable_bit = 0xff,
671 .recalc = &omap2_propagate_rate,
672};
673
674static struct clk func_12m_ck = {
675 .name = "func_12m_ck",
676 .parent = &func_48m_ck,
677 .rate = 12000000,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_FIXED | RATE_PROPAGATES,
680 .recalc = &omap2_propagate_rate,
681 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
682 .enable_bit = 0xff,
683};
684
685/* Secure timer, only available in secure mode */
686static struct clk wdt1_osc_ck = {
687 .name = "ck_wdt1_osc",
688 .parent = &osc_ck,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
690 .recalc = &omap2_followparent_recalc,
691};
692
693static struct clk sys_clkout = {
694 .name = "sys_clkout",
695 .parent = &func_54m_ck,
696 .rate = 54000000,
697 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
698 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
699 .src_offset = 0,
700 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
701 .enable_bit = 7,
702 .rate_offset = 3,
703 .recalc = &omap2_clksel_recalc,
704};
705
706/* In 2430, new in 2420 ES2 */
707static struct clk sys_clkout2 = {
708 .name = "sys_clkout2",
709 .parent = &func_54m_ck,
710 .rate = 54000000,
711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
712 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
713 .src_offset = 8,
714 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
715 .enable_bit = 15,
716 .rate_offset = 11,
717 .recalc = &omap2_clksel_recalc,
718};
719
720static struct clk emul_ck = {
721 .name = "emul_ck",
722 .parent = &func_54m_ck,
723 .flags = CLOCK_IN_OMAP242X,
724 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
725 .enable_bit = 0,
726 .recalc = &omap2_propagate_rate,
727
728};
729
730/*
731 * MPU clock domain
732 * Clocks:
733 * MPU_FCLK, MPU_ICLK
734 * INT_M_FCLK, INT_M_I_CLK
735 *
736 * - Individual clocks are hardware managed.
737 * - Base divider comes from: CM_CLKSEL_MPU
738 *
739 */
740static struct clk mpu_ck = { /* Control cpu */
741 .name = "mpu_ck",
742 .parent = &core_ck,
743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
744 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
745 CONFIG_PARTICIPANT | RATE_PROPAGATES,
746 .rate_offset = 0, /* bits 0-4 */
747 .recalc = &omap2_clksel_recalc,
748};
749
750/*
751 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
752 * Clocks:
753 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
754 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
755 */
756static struct clk iva2_1_fck = {
757 .name = "iva2_1_fck",
758 .parent = &core_ck,
759 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
760 DELAYED_APP | RATE_PROPAGATES |
761 CONFIG_PARTICIPANT,
762 .rate_offset = 0,
763 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
764 .enable_bit = 0,
765 .recalc = &omap2_clksel_recalc,
766};
767
768static struct clk iva2_1_ick = {
769 .name = "iva2_1_ick",
770 .parent = &iva2_1_fck,
771 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
772 DELAYED_APP | CONFIG_PARTICIPANT,
773 .rate_offset = 5,
774 .recalc = &omap2_clksel_recalc,
775};
776
777/*
778 * Won't be too specific here. The core clock comes into this block
779 * it is divided then tee'ed. One branch goes directly to xyz enable
780 * controls. The other branch gets further divided by 2 then possibly
781 * routed into a synchronizer and out of clocks abc.
782 */
783static struct clk dsp_fck = {
784 .name = "dsp_fck",
785 .parent = &core_ck,
786 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
787 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
788 .rate_offset = 0,
789 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
790 .enable_bit = 0,
791 .recalc = &omap2_clksel_recalc,
792};
793
794static struct clk dsp_ick = {
795 .name = "dsp_ick", /* apparently ipi and isp */
796 .parent = &dsp_fck,
797 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
798 DELAYED_APP | CONFIG_PARTICIPANT,
799 .rate_offset = 5,
800 .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
801 .enable_bit = 1, /* for ipi */
802 .recalc = &omap2_clksel_recalc,
803};
804
805static struct clk iva1_ifck = {
806 .name = "iva1_ifck",
807 .parent = &core_ck,
808 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
809 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
810 .rate_offset= 8,
811 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
812 .enable_bit = 10,
813 .recalc = &omap2_clksel_recalc,
814};
815
816/* IVA1 mpu/int/i/f clocks are /2 of parent */
817static struct clk iva1_mpu_int_ifck = {
818 .name = "iva1_mpu_int_ifck",
819 .parent = &iva1_ifck,
820 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
821 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
822 .enable_bit = 8,
823 .recalc = &omap2_clksel_recalc,
824};
825
826/*
827 * L3 clock domain
828 * L3 clocks are used for both interface and functional clocks to
829 * multiple entities. Some of these clocks are completely managed
830 * by hardware, and some others allow software control. Hardware
831 * managed ones general are based on directly CLK_REQ signals and
832 * various auto idle settings. The functional spec sets many of these
833 * as 'tie-high' for their enables.
834 *
835 * I-CLOCKS:
836 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
837 * CAM, HS-USB.
838 * F-CLOCK
839 * SSI.
840 *
841 * GPMC memories and SDRC have timing and clock sensitive registers which
842 * may very well need notification when the clock changes. Currently for low
843 * operating points, these are taken care of in sleep.S.
844 */
845static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
846 .name = "core_l3_ck",
847 .parent = &core_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
849 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
850 DELAYED_APP | CONFIG_PARTICIPANT |
851 RATE_PROPAGATES,
852 .rate_offset = 0,
853 .recalc = &omap2_clksel_recalc,
854};
855
856static struct clk usb_l4_ick = { /* FS-USB interface clock */
857 .name = "usb_l4_ick",
858 .parent = &core_l3_ck,
859 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
860 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
861 CONFIG_PARTICIPANT,
862 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
863 .enable_bit = 0,
864 .rate_offset = 25,
865 .recalc = &omap2_clksel_recalc,
866};
867
868/*
869 * SSI is in L3 management domain, its direct parent is core not l3,
870 * many core power domain entities are grouped into the L3 clock
871 * domain.
872 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
873 *
874 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
875 */
876static struct clk ssi_ssr_sst_fck = {
877 .name = "ssi_fck",
878 .parent = &core_ck,
879 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
880 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
881 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
882 .enable_bit = 1,
883 .rate_offset = 20,
884 .recalc = &omap2_clksel_recalc,
885};
886
887/*
888 * GFX clock domain
889 * Clocks:
890 * GFX_FCLK, GFX_ICLK
891 * GFX_CG1(2d), GFX_CG2(3d)
892 *
893 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
894 * The 2d and 3d clocks run at a hardware determined
895 * divided value of fclk.
896 *
897 */
898static struct clk gfx_3d_fck = {
899 .name = "gfx_3d_fck",
900 .parent = &core_l3_ck,
901 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
902 RATE_CKCTL | CM_GFX_SEL1,
903 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
904 .enable_bit = 2,
905 .rate_offset= 0,
906 .recalc = &omap2_clksel_recalc,
907};
908
909static struct clk gfx_2d_fck = {
910 .name = "gfx_2d_fck",
911 .parent = &core_l3_ck,
912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
913 RATE_CKCTL | CM_GFX_SEL1,
914 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
915 .enable_bit = 1,
916 .rate_offset= 0,
917 .recalc = &omap2_clksel_recalc,
918};
919
920static struct clk gfx_ick = {
921 .name = "gfx_ick", /* From l3 */
922 .parent = &core_l3_ck,
923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
924 RATE_CKCTL,
925 .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
926 .enable_bit = 0,
927 .recalc = &omap2_followparent_recalc,
928};
929
930/*
931 * Modem clock domain (2430)
932 * CLOCKS:
933 * MDM_OSC_CLK
934 * MDM_ICLK
935 */
936static struct clk mdm_ick = { /* used both as a ick and fck */
937 .name = "mdm_ick",
938 .parent = &core_ck,
939 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
940 DELAYED_APP | CONFIG_PARTICIPANT,
941 .rate_offset = 0,
942 .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
943 .enable_bit = 0,
944 .recalc = &omap2_clksel_recalc,
945};
946
947static struct clk mdm_osc_ck = {
948 .name = "mdm_osc_ck",
949 .rate = 26000000,
950 .parent = &osc_ck,
951 .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
952 .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
953 .enable_bit = 1,
954 .recalc = &omap2_followparent_recalc,
955};
956
957/*
958 * L4 clock management domain
959 *
960 * This domain contains lots of interface clocks from the L4 interface, some
961 * functional clocks. Fixed APLL functional source clocks are managed in
962 * this domain.
963 */
964static struct clk l4_ck = { /* used both as an ick and fck */
965 .name = "l4_ck",
966 .parent = &core_l3_ck,
967 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
968 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
969 DELAYED_APP | RATE_PROPAGATES,
970 .rate_offset = 5,
971 .recalc = &omap2_clksel_recalc,
972};
973
974static struct clk ssi_l4_ick = {
975 .name = "ssi_l4_ick",
976 .parent = &l4_ck,
977 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
978 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
979 .enable_bit = 1,
980 .recalc = &omap2_followparent_recalc,
981};
982
983/*
984 * DSS clock domain
985 * CLOCKs:
986 * DSS_L4_ICLK, DSS_L3_ICLK,
987 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
988 *
989 * DSS is both initiator and target.
990 */
991static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
992 .name = "dss_ick",
993 .parent = &l4_ck, /* really both l3 and l4 */
994 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
995 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
996 .enable_bit = 0,
997 .recalc = &omap2_followparent_recalc,
998};
999
1000static struct clk dss1_fck = {
1001 .name = "dss1_fck",
1002 .parent = &core_ck, /* Core or sys */
1003 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1004 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1005 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1006 .enable_bit = 0,
1007 .rate_offset = 8,
1008 .src_offset = 8,
1009 .recalc = &omap2_clksel_recalc,
1010};
1011
1012static struct clk dss2_fck = { /* Alt clk used in power management */
1013 .name = "dss2_fck",
1014 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1017 DELAYED_APP,
1018 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1019 .enable_bit = 1,
1020 .src_offset = 13,
1021 .recalc = &omap2_followparent_recalc,
1022};
1023
1024static struct clk dss_54m_fck = { /* Alt clk used in power management */
1025 .name = "dss_54m_fck", /* 54m tv clk */
1026 .parent = &func_54m_ck,
1027 .rate = 54000000,
1028 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1029 RATE_FIXED | RATE_PROPAGATES,
1030 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1031 .enable_bit = 2,
1032 .recalc = &omap2_propagate_rate,
1033};
1034
1035/*
1036 * CORE power domain ICLK & FCLK defines.
1037 * Many of the these can have more than one possible parent. Entries
1038 * here will likely have an L4 interface parent, and may have multiple
1039 * functional clock parents.
1040 */
1041static struct clk gpt1_ick = {
1042 .name = "gpt1_ick",
1043 .parent = &l4_ck,
1044 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1045 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
1046 .enable_bit = 0,
1047 .recalc = &omap2_followparent_recalc,
1048};
1049
1050static struct clk gpt1_fck = {
1051 .name = "gpt1_fck",
1052 .parent = &func_32k_ck,
1053 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1054 CM_WKUP_SEL1,
1055 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
1056 .enable_bit = 0,
1057 .src_offset = 0,
1058 .recalc = &omap2_followparent_recalc,
1059};
1060
1061static struct clk gpt2_ick = {
1062 .name = "gpt2_ick",
1063 .parent = &l4_ck,
1064 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1065 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1066 .enable_bit = 4,
1067 .recalc = &omap2_followparent_recalc,
1068};
1069
1070static struct clk gpt2_fck = {
1071 .name = "gpt2_fck",
1072 .parent = &func_32k_ck,
1073 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1074 CM_CORE_SEL2,
1075 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1076 .enable_bit = 4,
1077 .src_offset = 2,
1078 .recalc = &omap2_followparent_recalc,
1079};
1080
1081static struct clk gpt3_ick = {
1082 .name = "gpt3_ick",
1083 .parent = &l4_ck,
1084 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1085 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
1086 .enable_bit = 5,
1087 .recalc = &omap2_followparent_recalc,
1088};
1089
1090static struct clk gpt3_fck = {
1091 .name = "gpt3_fck",
1092 .parent = &func_32k_ck,
1093 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1094 CM_CORE_SEL2,
1095 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1096 .enable_bit = 5,
1097 .src_offset = 4,
1098 .recalc = &omap2_followparent_recalc,
1099};
1100
1101static struct clk gpt4_ick = {
1102 .name = "gpt4_ick",
1103 .parent = &l4_ck,
1104 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1105 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
1106 .enable_bit = 6,
1107 .recalc = &omap2_followparent_recalc,
1108};
1109
1110static struct clk gpt4_fck = {
1111 .name = "gpt4_fck",
1112 .parent = &func_32k_ck,
1113 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1114 CM_CORE_SEL2,
1115 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1116 .enable_bit = 6,
1117 .src_offset = 6,
1118 .recalc = &omap2_followparent_recalc,
1119};
1120
1121static struct clk gpt5_ick = {
1122 .name = "gpt5_ick",
1123 .parent = &l4_ck,
1124 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1125 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
1126 .enable_bit = 7,
1127 .recalc = &omap2_followparent_recalc,
1128};
1129
1130static struct clk gpt5_fck = {
1131 .name = "gpt5_fck",
1132 .parent = &func_32k_ck,
1133 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1134 CM_CORE_SEL2,
1135 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1136 .enable_bit = 7,
1137 .src_offset = 8,
1138 .recalc = &omap2_followparent_recalc,
1139};
1140
1141static struct clk gpt6_ick = {
1142 .name = "gpt6_ick",
1143 .parent = &l4_ck,
1144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1145 .enable_bit = 8,
1146 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
1147 .recalc = &omap2_followparent_recalc,
1148};
1149
1150static struct clk gpt6_fck = {
1151 .name = "gpt6_fck",
1152 .parent = &func_32k_ck,
1153 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1154 CM_CORE_SEL2,
1155 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1156 .enable_bit = 8,
1157 .src_offset = 10,
1158 .recalc = &omap2_followparent_recalc,
1159};
1160
1161static struct clk gpt7_ick = {
1162 .name = "gpt7_ick",
1163 .parent = &l4_ck,
1164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1165 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
1166 .enable_bit = 9,
1167 .recalc = &omap2_followparent_recalc,
1168};
1169
1170static struct clk gpt7_fck = {
1171 .name = "gpt7_fck",
1172 .parent = &func_32k_ck,
1173 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1174 CM_CORE_SEL2,
1175 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1176 .enable_bit = 9,
1177 .src_offset = 12,
1178 .recalc = &omap2_followparent_recalc,
1179};
1180
1181static struct clk gpt8_ick = {
1182 .name = "gpt8_ick",
1183 .parent = &l4_ck,
1184 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1185 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
1186 .enable_bit = 10,
1187 .recalc = &omap2_followparent_recalc,
1188};
1189
1190static struct clk gpt8_fck = {
1191 .name = "gpt8_fck",
1192 .parent = &func_32k_ck,
1193 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1194 CM_CORE_SEL2,
1195 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1196 .enable_bit = 10,
1197 .src_offset = 14,
1198 .recalc = &omap2_followparent_recalc,
1199};
1200
1201static struct clk gpt9_ick = {
1202 .name = "gpt9_ick",
1203 .parent = &l4_ck,
1204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1205 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1206 .enable_bit = 11,
1207 .recalc = &omap2_followparent_recalc,
1208};
1209
1210static struct clk gpt9_fck = {
1211 .name = "gpt9_fck",
1212 .parent = &func_32k_ck,
1213 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1214 CM_CORE_SEL2,
1215 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1216 .enable_bit = 11,
1217 .src_offset = 16,
1218 .recalc = &omap2_followparent_recalc,
1219};
1220
1221static struct clk gpt10_ick = {
1222 .name = "gpt10_ick",
1223 .parent = &l4_ck,
1224 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1225 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1226 .enable_bit = 12,
1227 .recalc = &omap2_followparent_recalc,
1228};
1229
1230static struct clk gpt10_fck = {
1231 .name = "gpt10_fck",
1232 .parent = &func_32k_ck,
1233 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1234 CM_CORE_SEL2,
1235 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1236 .enable_bit = 12,
1237 .src_offset = 18,
1238 .recalc = &omap2_followparent_recalc,
1239};
1240
1241static struct clk gpt11_ick = {
1242 .name = "gpt11_ick",
1243 .parent = &l4_ck,
1244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1245 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1246 .enable_bit = 13,
1247 .recalc = &omap2_followparent_recalc,
1248};
1249
1250static struct clk gpt11_fck = {
1251 .name = "gpt11_fck",
1252 .parent = &func_32k_ck,
1253 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1254 CM_CORE_SEL2,
1255 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1256 .enable_bit = 13,
1257 .src_offset = 20,
1258 .recalc = &omap2_followparent_recalc,
1259};
1260
1261static struct clk gpt12_ick = {
1262 .name = "gpt12_ick",
1263 .parent = &l4_ck,
1264 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1265 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
1266 .enable_bit = 14,
1267 .recalc = &omap2_followparent_recalc,
1268};
1269
1270static struct clk gpt12_fck = {
1271 .name = "gpt12_fck",
1272 .parent = &func_32k_ck,
1273 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1274 CM_CORE_SEL2,
1275 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1276 .enable_bit = 14,
1277 .src_offset = 22,
1278 .recalc = &omap2_followparent_recalc,
1279};
1280
1281static struct clk mcbsp1_ick = {
1282 .name = "mcbsp1_ick",
1283 .parent = &l4_ck,
1284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1285 .enable_bit = 15,
1286 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
1287 .recalc = &omap2_followparent_recalc,
1288};
1289
1290static struct clk mcbsp1_fck = {
1291 .name = "mcbsp1_fck",
1292 .parent = &func_96m_ck,
1293 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1294 .enable_bit = 15,
1295 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1296 .recalc = &omap2_followparent_recalc,
1297};
1298
1299static struct clk mcbsp2_ick = {
1300 .name = "mcbsp2_ick",
1301 .parent = &l4_ck,
1302 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1303 .enable_bit = 16,
1304 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1305 .recalc = &omap2_followparent_recalc,
1306};
1307
1308static struct clk mcbsp2_fck = {
1309 .name = "mcbsp2_fck",
1310 .parent = &func_96m_ck,
1311 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1312 .enable_bit = 16,
1313 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1314 .recalc = &omap2_followparent_recalc,
1315};
1316
1317static struct clk mcbsp3_ick = {
1318 .name = "mcbsp3_ick",
1319 .parent = &l4_ck,
1320 .flags = CLOCK_IN_OMAP243X,
1321 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1322 .enable_bit = 3,
1323 .recalc = &omap2_followparent_recalc,
1324};
1325
1326static struct clk mcbsp3_fck = {
1327 .name = "mcbsp3_fck",
1328 .parent = &func_96m_ck,
1329 .flags = CLOCK_IN_OMAP243X,
1330 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1331 .enable_bit = 3,
1332 .recalc = &omap2_followparent_recalc,
1333};
1334
1335static struct clk mcbsp4_ick = {
1336 .name = "mcbsp4_ick",
1337 .parent = &l4_ck,
1338 .flags = CLOCK_IN_OMAP243X,
1339 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1340 .enable_bit = 4,
1341 .recalc = &omap2_followparent_recalc,
1342};
1343
1344static struct clk mcbsp4_fck = {
1345 .name = "mcbsp4_fck",
1346 .parent = &func_96m_ck,
1347 .flags = CLOCK_IN_OMAP243X,
1348 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1349 .enable_bit = 4,
1350 .recalc = &omap2_followparent_recalc,
1351};
1352
1353static struct clk mcbsp5_ick = {
1354 .name = "mcbsp5_ick",
1355 .parent = &l4_ck,
1356 .flags = CLOCK_IN_OMAP243X,
1357 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1358 .enable_bit = 5,
1359 .recalc = &omap2_followparent_recalc,
1360};
1361
1362static struct clk mcbsp5_fck = {
1363 .name = "mcbsp5_fck",
1364 .parent = &func_96m_ck,
1365 .flags = CLOCK_IN_OMAP243X,
1366 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1367 .enable_bit = 5,
1368 .recalc = &omap2_followparent_recalc,
1369};
1370
1371static struct clk mcspi1_ick = {
1372 .name = "mcspi_ick",
1373 .id = 1,
1374 .parent = &l4_ck,
1375 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1376 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1377 .enable_bit = 17,
1378 .recalc = &omap2_followparent_recalc,
1379};
1380
1381static struct clk mcspi1_fck = {
1382 .name = "mcspi_fck",
1383 .id = 1,
1384 .parent = &func_48m_ck,
1385 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1386 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1387 .enable_bit = 17,
1388 .recalc = &omap2_followparent_recalc,
1389};
1390
1391static struct clk mcspi2_ick = {
1392 .name = "mcspi_ick",
1393 .id = 2,
1394 .parent = &l4_ck,
1395 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1396 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1397 .enable_bit = 18,
1398 .recalc = &omap2_followparent_recalc,
1399};
1400
1401static struct clk mcspi2_fck = {
1402 .name = "mcspi_fck",
1403 .id = 2,
1404 .parent = &func_48m_ck,
1405 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1406 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1407 .enable_bit = 18,
1408 .recalc = &omap2_followparent_recalc,
1409};
1410
1411static struct clk mcspi3_ick = {
1412 .name = "mcspi_ick",
1413 .id = 3,
1414 .parent = &l4_ck,
1415 .flags = CLOCK_IN_OMAP243X,
1416 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1417 .enable_bit = 9,
1418 .recalc = &omap2_followparent_recalc,
1419};
1420
1421static struct clk mcspi3_fck = {
1422 .name = "mcspi_fck",
1423 .id = 3,
1424 .parent = &func_48m_ck,
1425 .flags = CLOCK_IN_OMAP243X,
1426 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1427 .enable_bit = 9,
1428 .recalc = &omap2_followparent_recalc,
1429};
1430
1431static struct clk uart1_ick = {
1432 .name = "uart1_ick",
1433 .parent = &l4_ck,
1434 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1435 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1436 .enable_bit = 21,
1437 .recalc = &omap2_followparent_recalc,
1438};
1439
1440static struct clk uart1_fck = {
1441 .name = "uart1_fck",
1442 .parent = &func_48m_ck,
1443 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1444 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1445 .enable_bit = 21,
1446 .recalc = &omap2_followparent_recalc,
1447};
1448
1449static struct clk uart2_ick = {
1450 .name = "uart2_ick",
1451 .parent = &l4_ck,
1452 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1453 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1454 .enable_bit = 22,
1455 .recalc = &omap2_followparent_recalc,
1456};
1457
1458static struct clk uart2_fck = {
1459 .name = "uart2_fck",
1460 .parent = &func_48m_ck,
1461 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1462 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1463 .enable_bit = 22,
1464 .recalc = &omap2_followparent_recalc,
1465};
1466
1467static struct clk uart3_ick = {
1468 .name = "uart3_ick",
1469 .parent = &l4_ck,
1470 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1472 .enable_bit = 2,
1473 .recalc = &omap2_followparent_recalc,
1474};
1475
1476static struct clk uart3_fck = {
1477 .name = "uart3_fck",
1478 .parent = &func_48m_ck,
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1480 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1481 .enable_bit = 2,
1482 .recalc = &omap2_followparent_recalc,
1483};
1484
1485static struct clk gpios_ick = {
1486 .name = "gpios_ick",
1487 .parent = &l4_ck,
1488 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1489 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1490 .enable_bit = 2,
1491 .recalc = &omap2_followparent_recalc,
1492};
1493
1494static struct clk gpios_fck = {
1495 .name = "gpios_fck",
1496 .parent = &func_32k_ck,
1497 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1498 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1499 .enable_bit = 2,
1500 .recalc = &omap2_followparent_recalc,
1501};
1502
1503static struct clk mpu_wdt_ick = {
1504 .name = "mpu_wdt_ick",
1505 .parent = &l4_ck,
1506 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1507 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1508 .enable_bit = 3,
1509 .recalc = &omap2_followparent_recalc,
1510};
1511
1512static struct clk mpu_wdt_fck = {
1513 .name = "mpu_wdt_fck",
1514 .parent = &func_32k_ck,
1515 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1516 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1517 .enable_bit = 3,
1518 .recalc = &omap2_followparent_recalc,
1519};
1520
1521static struct clk sync_32k_ick = {
1522 .name = "sync_32k_ick",
1523 .parent = &l4_ck,
1524 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1525 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1526 .enable_bit = 1,
1527 .recalc = &omap2_followparent_recalc,
1528};
1529static struct clk wdt1_ick = {
1530 .name = "wdt1_ick",
1531 .parent = &l4_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1534 .enable_bit = 4,
1535 .recalc = &omap2_followparent_recalc,
1536};
1537static struct clk omapctrl_ick = {
1538 .name = "omapctrl_ick",
1539 .parent = &l4_ck,
1540 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1541 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1542 .enable_bit = 5,
1543 .recalc = &omap2_followparent_recalc,
1544};
1545static struct clk icr_ick = {
1546 .name = "icr_ick",
1547 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP243X,
1549 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1550 .enable_bit = 6,
1551 .recalc = &omap2_followparent_recalc,
1552};
1553
1554static struct clk cam_ick = {
1555 .name = "cam_ick",
1556 .parent = &l4_ck,
1557 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1559 .enable_bit = 31,
1560 .recalc = &omap2_followparent_recalc,
1561};
1562
1563static struct clk cam_fck = {
1564 .name = "cam_fck",
1565 .parent = &func_96m_ck,
1566 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1568 .enable_bit = 31,
1569 .recalc = &omap2_followparent_recalc,
1570};
1571
1572static struct clk mailboxes_ick = {
1573 .name = "mailboxes_ick",
1574 .parent = &l4_ck,
1575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1576 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1577 .enable_bit = 30,
1578 .recalc = &omap2_followparent_recalc,
1579};
1580
1581static struct clk wdt4_ick = {
1582 .name = "wdt4_ick",
1583 .parent = &l4_ck,
1584 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1585 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1586 .enable_bit = 29,
1587 .recalc = &omap2_followparent_recalc,
1588};
1589
1590static struct clk wdt4_fck = {
1591 .name = "wdt4_fck",
1592 .parent = &func_32k_ck,
1593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1594 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1595 .enable_bit = 29,
1596 .recalc = &omap2_followparent_recalc,
1597};
1598
1599static struct clk wdt3_ick = {
1600 .name = "wdt3_ick",
1601 .parent = &l4_ck,
1602 .flags = CLOCK_IN_OMAP242X,
1603 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1604 .enable_bit = 28,
1605 .recalc = &omap2_followparent_recalc,
1606};
1607
1608static struct clk wdt3_fck = {
1609 .name = "wdt3_fck",
1610 .parent = &func_32k_ck,
1611 .flags = CLOCK_IN_OMAP242X,
1612 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1613 .enable_bit = 28,
1614 .recalc = &omap2_followparent_recalc,
1615};
1616
1617static struct clk mspro_ick = {
1618 .name = "mspro_ick",
1619 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1622 .enable_bit = 27,
1623 .recalc = &omap2_followparent_recalc,
1624};
1625
1626static struct clk mspro_fck = {
1627 .name = "mspro_fck",
1628 .parent = &func_96m_ck,
1629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1631 .enable_bit = 27,
1632 .recalc = &omap2_followparent_recalc,
1633};
1634
1635static struct clk mmc_ick = {
1636 .name = "mmc_ick",
1637 .parent = &l4_ck,
1638 .flags = CLOCK_IN_OMAP242X,
1639 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1640 .enable_bit = 26,
1641 .recalc = &omap2_followparent_recalc,
1642};
1643
1644static struct clk mmc_fck = {
1645 .name = "mmc_fck",
1646 .parent = &func_96m_ck,
1647 .flags = CLOCK_IN_OMAP242X,
1648 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1649 .enable_bit = 26,
1650 .recalc = &omap2_followparent_recalc,
1651};
1652
1653static struct clk fac_ick = {
1654 .name = "fac_ick",
1655 .parent = &l4_ck,
1656 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1657 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1658 .enable_bit = 25,
1659 .recalc = &omap2_followparent_recalc,
1660};
1661
1662static struct clk fac_fck = {
1663 .name = "fac_fck",
1664 .parent = &func_12m_ck,
1665 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1667 .enable_bit = 25,
1668 .recalc = &omap2_followparent_recalc,
1669};
1670
1671static struct clk eac_ick = {
1672 .name = "eac_ick",
1673 .parent = &l4_ck,
1674 .flags = CLOCK_IN_OMAP242X,
1675 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1676 .enable_bit = 24,
1677 .recalc = &omap2_followparent_recalc,
1678};
1679
1680static struct clk eac_fck = {
1681 .name = "eac_fck",
1682 .parent = &func_96m_ck,
1683 .flags = CLOCK_IN_OMAP242X,
1684 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1685 .enable_bit = 24,
1686 .recalc = &omap2_followparent_recalc,
1687};
1688
1689static struct clk hdq_ick = {
1690 .name = "hdq_ick",
1691 .parent = &l4_ck,
1692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1693 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1694 .enable_bit = 23,
1695 .recalc = &omap2_followparent_recalc,
1696};
1697
1698static struct clk hdq_fck = {
1699 .name = "hdq_fck",
1700 .parent = &func_12m_ck,
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1703 .enable_bit = 23,
1704 .recalc = &omap2_followparent_recalc,
1705};
1706
1707static struct clk i2c2_ick = {
1708 .name = "i2c_ick",
1709 .id = 2,
1710 .parent = &l4_ck,
1711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1712 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1713 .enable_bit = 20,
1714 .recalc = &omap2_followparent_recalc,
1715};
1716
1717static struct clk i2c2_fck = {
1718 .name = "i2c_fck",
1719 .id = 2,
1720 .parent = &func_12m_ck,
1721 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1722 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1723 .enable_bit = 20,
1724 .recalc = &omap2_followparent_recalc,
1725};
1726
1727static struct clk i2chs2_fck = {
1728 .name = "i2chs2_fck",
1729 .parent = &func_96m_ck,
1730 .flags = CLOCK_IN_OMAP243X,
1731 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1732 .enable_bit = 20,
1733 .recalc = &omap2_followparent_recalc,
1734};
1735
1736static struct clk i2c1_ick = {
1737 .name = "i2c_ick",
1738 .id = 1,
1739 .parent = &l4_ck,
1740 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1742 .enable_bit = 19,
1743 .recalc = &omap2_followparent_recalc,
1744};
1745
1746static struct clk i2c1_fck = {
1747 .name = "i2c_fck",
1748 .id = 1,
1749 .parent = &func_12m_ck,
1750 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1751 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1752 .enable_bit = 19,
1753 .recalc = &omap2_followparent_recalc,
1754};
1755
1756static struct clk i2chs1_fck = {
1757 .name = "i2chs1_fck",
1758 .parent = &func_96m_ck,
1759 .flags = CLOCK_IN_OMAP243X,
1760 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1761 .enable_bit = 19,
1762 .recalc = &omap2_followparent_recalc,
1763};
1764
1765static struct clk vlynq_ick = {
1766 .name = "vlynq_ick",
1767 .parent = &core_l3_ck,
1768 .flags = CLOCK_IN_OMAP242X,
1769 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1770 .enable_bit = 3,
1771 .recalc = &omap2_followparent_recalc,
1772};
1773
1774static struct clk vlynq_fck = {
1775 .name = "vlynq_fck",
1776 .parent = &func_96m_ck,
1777 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1778 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1779 .enable_bit = 3,
1780 .src_offset = 15,
1781 .recalc = &omap2_followparent_recalc,
1782};
1783
1784static struct clk sdrc_ick = {
1785 .name = "sdrc_ick",
1786 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP243X,
1788 .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
1789 .enable_bit = 2,
1790 .recalc = &omap2_followparent_recalc,
1791};
1792
1793static struct clk des_ick = {
1794 .name = "des_ick",
1795 .parent = &l4_ck,
1796 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1797 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1798 .enable_bit = 0,
1799 .recalc = &omap2_followparent_recalc,
1800};
1801
1802static struct clk sha_ick = {
1803 .name = "sha_ick",
1804 .parent = &l4_ck,
1805 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1806 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1807 .enable_bit = 1,
1808 .recalc = &omap2_followparent_recalc,
1809};
1810
1811static struct clk rng_ick = {
1812 .name = "rng_ick",
1813 .parent = &l4_ck,
1814 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1815 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1816 .enable_bit = 2,
1817 .recalc = &omap2_followparent_recalc,
1818};
1819
1820static struct clk aes_ick = {
1821 .name = "aes_ick",
1822 .parent = &l4_ck,
1823 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1824 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1825 .enable_bit = 3,
1826 .recalc = &omap2_followparent_recalc,
1827};
1828
1829static struct clk pka_ick = {
1830 .name = "pka_ick",
1831 .parent = &l4_ck,
1832 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1833 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1834 .enable_bit = 4,
1835 .recalc = &omap2_followparent_recalc,
1836};
1837
1838static struct clk usb_fck = {
1839 .name = "usb_fck",
1840 .parent = &func_48m_ck,
1841 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1842 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1843 .enable_bit = 0,
1844 .recalc = &omap2_followparent_recalc,
1845};
1846
1847static struct clk usbhs_ick = {
1848 .name = "usbhs_ick",
1849 .parent = &core_l3_ck,
1850 .flags = CLOCK_IN_OMAP243X,
1851 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1852 .enable_bit = 6,
1853 .recalc = &omap2_followparent_recalc,
1854};
1855
1856static struct clk mmchs1_ick = {
1857 .name = "mmchs1_ick",
1858 .parent = &l4_ck,
1859 .flags = CLOCK_IN_OMAP243X,
1860 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1861 .enable_bit = 7,
1862 .recalc = &omap2_followparent_recalc,
1863};
1864
1865static struct clk mmchs1_fck = {
1866 .name = "mmchs1_fck",
1867 .parent = &func_96m_ck,
1868 .flags = CLOCK_IN_OMAP243X,
1869 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1870 .enable_bit = 7,
1871 .recalc = &omap2_followparent_recalc,
1872};
1873
1874static struct clk mmchs2_ick = {
1875 .name = "mmchs2_ick",
1876 .parent = &l4_ck,
1877 .flags = CLOCK_IN_OMAP243X,
1878 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1879 .enable_bit = 8,
1880 .recalc = &omap2_followparent_recalc,
1881};
1882
1883static struct clk mmchs2_fck = {
1884 .name = "mmchs2_fck",
1885 .parent = &func_96m_ck,
1886 .flags = CLOCK_IN_OMAP243X,
1887 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1888 .enable_bit = 8,
1889 .recalc = &omap2_followparent_recalc,
1890};
1891 32
1892static struct clk gpio5_ick = { 33void omap2_clksel_recalc(struct clk *clk);
1893 .name = "gpio5_ick", 34void omap2_init_clksel_parent(struct clk *clk);
1894 .parent = &l4_ck, 35u32 omap2_clksel_get_divisor(struct clk *clk);
1895 .flags = CLOCK_IN_OMAP243X, 36u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
1896 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 37 u32 *new_div);
1897 .enable_bit = 10, 38u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
1898 .recalc = &omap2_followparent_recalc, 39u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
1899}; 40void omap2_fixed_divisor_recalc(struct clk *clk);
41long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
42int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
43u32 omap2_get_dpll_rate(struct clk *clk);
44int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
1900 45
1901static struct clk gpio5_fck = { 46extern u8 cpu_mask;
1902 .name = "gpio5_fck",
1903 .parent = &func_32k_ck,
1904 .flags = CLOCK_IN_OMAP243X,
1905 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1906 .enable_bit = 10,
1907 .recalc = &omap2_followparent_recalc,
1908};
1909 47
1910static struct clk mdm_intc_ick = { 48/* clksel_rate data common to 24xx/343x */
1911 .name = "mdm_intc_ick", 49static const struct clksel_rate gpt_32k_rates[] = {
1912 .parent = &l4_ck, 50 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
1913 .flags = CLOCK_IN_OMAP243X, 51 { .div = 0 }
1914 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1915 .enable_bit = 11,
1916 .recalc = &omap2_followparent_recalc,
1917}; 52};
1918 53
1919static struct clk mmchsdb1_fck = { 54static const struct clksel_rate gpt_sys_rates[] = {
1920 .name = "mmchsdb1_fck", 55 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
1921 .parent = &func_32k_ck, 56 { .div = 0 }
1922 .flags = CLOCK_IN_OMAP243X,
1923 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1924 .enable_bit = 16,
1925 .recalc = &omap2_followparent_recalc,
1926}; 57};
1927 58
1928static struct clk mmchsdb2_fck = { 59static const struct clksel_rate gfx_l3_rates[] = {
1929 .name = "mmchsdb2_fck", 60 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
1930 .parent = &func_32k_ck, 61 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
1931 .flags = CLOCK_IN_OMAP243X, 62 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
1932 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 63 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
1933 .enable_bit = 17, 64 { .div = 0 }
1934 .recalc = &omap2_followparent_recalc,
1935}; 65};
1936 66
1937/*
1938 * This clock is a composite clock which does entire set changes then
1939 * forces a rebalance. It keys on the MPU speed, but it really could
1940 * be any key speed part of a set in the rate table.
1941 *
1942 * to really change a set, you need memory table sets which get changed
1943 * in sram, pre-notifiers & post notifiers, changing the top set, without
1944 * having low level display recalc's won't work... this is why dpm notifiers
1945 * work, isr's off, walk a list of clocks already _off_ and not messing with
1946 * the bus.
1947 *
1948 * This clock should have no parent. It embodies the entire upper level
1949 * active set. A parent will mess up some of the init also.
1950 */
1951static struct clk virt_prcm_set = {
1952 .name = "virt_prcm_set",
1953 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1954 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1955 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1956 .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
1957 .set_rate = &omap2_select_table_rate,
1958 .round_rate = &omap2_round_to_table_rate,
1959};
1960
1961static struct clk *onchip_clks[] = {
1962 /* external root sources */
1963 &func_32k_ck,
1964 &osc_ck,
1965 &sys_ck,
1966 &alt_ck,
1967 /* internal analog sources */
1968 &dpll_ck,
1969 &apll96_ck,
1970 &apll54_ck,
1971 /* internal prcm root sources */
1972 &func_54m_ck,
1973 &core_ck,
1974 &sleep_ck,
1975 &func_96m_ck,
1976 &func_48m_ck,
1977 &func_12m_ck,
1978 &wdt1_osc_ck,
1979 &sys_clkout,
1980 &sys_clkout2,
1981 &emul_ck,
1982 /* mpu domain clocks */
1983 &mpu_ck,
1984 /* dsp domain clocks */
1985 &iva2_1_fck, /* 2430 */
1986 &iva2_1_ick,
1987 &dsp_ick, /* 2420 */
1988 &dsp_fck,
1989 &iva1_ifck,
1990 &iva1_mpu_int_ifck,
1991 /* GFX domain clocks */
1992 &gfx_3d_fck,
1993 &gfx_2d_fck,
1994 &gfx_ick,
1995 /* Modem domain clocks */
1996 &mdm_ick,
1997 &mdm_osc_ck,
1998 /* DSS domain clocks */
1999 &dss_ick,
2000 &dss1_fck,
2001 &dss2_fck,
2002 &dss_54m_fck,
2003 /* L3 domain clocks */
2004 &core_l3_ck,
2005 &ssi_ssr_sst_fck,
2006 &usb_l4_ick,
2007 /* L4 domain clocks */
2008 &l4_ck, /* used as both core_l4 and wu_l4 */
2009 &ssi_l4_ick,
2010 /* virtual meta-group clock */
2011 &virt_prcm_set,
2012 /* general l4 interface ck, multi-parent functional clk */
2013 &gpt1_ick,
2014 &gpt1_fck,
2015 &gpt2_ick,
2016 &gpt2_fck,
2017 &gpt3_ick,
2018 &gpt3_fck,
2019 &gpt4_ick,
2020 &gpt4_fck,
2021 &gpt5_ick,
2022 &gpt5_fck,
2023 &gpt6_ick,
2024 &gpt6_fck,
2025 &gpt7_ick,
2026 &gpt7_fck,
2027 &gpt8_ick,
2028 &gpt8_fck,
2029 &gpt9_ick,
2030 &gpt9_fck,
2031 &gpt10_ick,
2032 &gpt10_fck,
2033 &gpt11_ick,
2034 &gpt11_fck,
2035 &gpt12_ick,
2036 &gpt12_fck,
2037 &mcbsp1_ick,
2038 &mcbsp1_fck,
2039 &mcbsp2_ick,
2040 &mcbsp2_fck,
2041 &mcbsp3_ick,
2042 &mcbsp3_fck,
2043 &mcbsp4_ick,
2044 &mcbsp4_fck,
2045 &mcbsp5_ick,
2046 &mcbsp5_fck,
2047 &mcspi1_ick,
2048 &mcspi1_fck,
2049 &mcspi2_ick,
2050 &mcspi2_fck,
2051 &mcspi3_ick,
2052 &mcspi3_fck,
2053 &uart1_ick,
2054 &uart1_fck,
2055 &uart2_ick,
2056 &uart2_fck,
2057 &uart3_ick,
2058 &uart3_fck,
2059 &gpios_ick,
2060 &gpios_fck,
2061 &mpu_wdt_ick,
2062 &mpu_wdt_fck,
2063 &sync_32k_ick,
2064 &wdt1_ick,
2065 &omapctrl_ick,
2066 &icr_ick,
2067 &cam_fck,
2068 &cam_ick,
2069 &mailboxes_ick,
2070 &wdt4_ick,
2071 &wdt4_fck,
2072 &wdt3_ick,
2073 &wdt3_fck,
2074 &mspro_ick,
2075 &mspro_fck,
2076 &mmc_ick,
2077 &mmc_fck,
2078 &fac_ick,
2079 &fac_fck,
2080 &eac_ick,
2081 &eac_fck,
2082 &hdq_ick,
2083 &hdq_fck,
2084 &i2c1_ick,
2085 &i2c1_fck,
2086 &i2chs1_fck,
2087 &i2c2_ick,
2088 &i2c2_fck,
2089 &i2chs2_fck,
2090 &vlynq_ick,
2091 &vlynq_fck,
2092 &sdrc_ick,
2093 &des_ick,
2094 &sha_ick,
2095 &rng_ick,
2096 &aes_ick,
2097 &pka_ick,
2098 &usb_fck,
2099 &usbhs_ick,
2100 &mmchs1_ick,
2101 &mmchs1_fck,
2102 &mmchs2_ick,
2103 &mmchs2_fck,
2104 &gpio5_ick,
2105 &gpio5_fck,
2106 &mdm_intc_ick,
2107 &mmchsdb1_fck,
2108 &mmchsdb2_fck,
2109};
2110 67
2111#endif 68#endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
new file mode 100644
index 00000000000..ece32d8acba
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -0,0 +1,539 @@
1/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/device.h>
23#include <linux/list.h>
24#include <linux/errno.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27
28#include <linux/io.h>
29#include <linux/cpufreq.h>
30
31#include <asm/arch/clock.h>
32#include <asm/arch/sram.h>
33#include <asm/div64.h>
34#include <asm/bitops.h>
35
36#include "memory.h"
37#include "clock.h"
38#include "clock24xx.h"
39#include "prm.h"
40#include "prm-regbits-24xx.h"
41#include "cm.h"
42#include "cm-regbits-24xx.h"
43
44/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
45#define EN_APLL_STOPPED 0
46#define EN_APLL_LOCKED 3
47
48/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
49#define APLLS_CLKIN_19_2MHZ 0
50#define APLLS_CLKIN_13MHZ 2
51#define APLLS_CLKIN_12MHZ 3
52
53/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
54
55static struct prcm_config *curr_prcm_set;
56static struct clk *vclk;
57static struct clk *sclk;
58
59/*-------------------------------------------------------------------------
60 * Omap24xx specific clock functions
61 *-------------------------------------------------------------------------*/
62
63/* This actually returns the rate of core_ck, not dpll_ck. */
64static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
65{
66 long long dpll_clk;
67 u8 amult;
68
69 dpll_clk = omap2_get_dpll_rate(tclk);
70
71 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
72 amult &= OMAP24XX_CORE_CLK_SRC_MASK;
73 dpll_clk *= amult;
74
75 return dpll_clk;
76}
77
78static int omap2_enable_osc_ck(struct clk *clk)
79{
80 u32 pcc;
81
82 pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
83
84 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
85 OMAP24XX_PRCM_CLKSRC_CTRL);
86
87 return 0;
88}
89
90static void omap2_disable_osc_ck(struct clk *clk)
91{
92 u32 pcc;
93
94 pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
95
96 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
97 OMAP24XX_PRCM_CLKSRC_CTRL);
98}
99
100#ifdef OLD_CK
101/* Recalculate SYST_CLK */
102static void omap2_sys_clk_recalc(struct clk * clk)
103{
104 u32 div = PRCM_CLKSRC_CTRL;
105 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
106 div >>= clk->rate_offset;
107 clk->rate = (clk->parent->rate / div);
108 propagate_rate(clk);
109}
110#endif /* OLD_CK */
111
112/* Enable an APLL if off */
113static int omap2_clk_fixed_enable(struct clk *clk)
114{
115 u32 cval, apll_mask;
116
117 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
118
119 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
120
121 if ((cval & apll_mask) == apll_mask)
122 return 0; /* apll already enabled */
123
124 cval &= ~apll_mask;
125 cval |= apll_mask;
126 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
127
128 if (clk == &apll96_ck)
129 cval = OMAP24XX_ST_96M_APLL;
130 else if (clk == &apll54_ck)
131 cval = OMAP24XX_ST_54M_APLL;
132
133 omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
134 clk->name);
135
136 /*
137 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
138 * fails?
139 */
140 return 0;
141}
142
143/* Stop APLL */
144static void omap2_clk_fixed_disable(struct clk *clk)
145{
146 u32 cval;
147
148 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
149 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
150 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
151}
152
153/*
154 * Uses the current prcm set to tell if a rate is valid.
155 * You can go slower, but not faster within a given rate set.
156 */
157static u32 omap2_dpll_round_rate(unsigned long target_rate)
158{
159 u32 high, low, core_clk_src;
160
161 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
162 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
163
164 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
165 high = curr_prcm_set->dpll_speed * 2;
166 low = curr_prcm_set->dpll_speed;
167 } else { /* DPLL clockout x 2 */
168 high = curr_prcm_set->dpll_speed;
169 low = curr_prcm_set->dpll_speed / 2;
170 }
171
172#ifdef DOWN_VARIABLE_DPLL
173 if (target_rate > high)
174 return high;
175 else
176 return target_rate;
177#else
178 if (target_rate > low)
179 return high;
180 else
181 return low;
182#endif
183
184}
185
186static void omap2_dpll_recalc(struct clk *clk)
187{
188 clk->rate = omap2_get_dpll_rate_24xx(clk);
189
190 propagate_rate(clk);
191}
192
193static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
194{
195 u32 cur_rate, low, mult, div, valid_rate, done_rate;
196 u32 bypass = 0;
197 struct prcm_config tmpset;
198 const struct dpll_data *dd;
199 unsigned long flags;
200 int ret = -EINVAL;
201
202 local_irq_save(flags);
203 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
204 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
205 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
206
207 if ((rate == (cur_rate / 2)) && (mult == 2)) {
208 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
209 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
210 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
211 } else if (rate != cur_rate) {
212 valid_rate = omap2_dpll_round_rate(rate);
213 if (valid_rate != rate)
214 goto dpll_exit;
215
216 if (mult == 1)
217 low = curr_prcm_set->dpll_speed;
218 else
219 low = curr_prcm_set->dpll_speed / 2;
220
221 dd = clk->dpll_data;
222 if (!dd)
223 goto dpll_exit;
224
225 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
226 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
227 dd->div1_mask);
228 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
229 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
230 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
231 if (rate > low) {
232 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
233 mult = ((rate / 2) / 1000000);
234 done_rate = CORE_CLK_SRC_DPLL_X2;
235 } else {
236 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
237 mult = (rate / 1000000);
238 done_rate = CORE_CLK_SRC_DPLL;
239 }
240 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
241 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
242
243 /* Worst case */
244 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
245
246 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
247 bypass = 1;
248
249 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
250
251 /* Force dll lock mode */
252 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
253 bypass);
254
255 /* Errata: ret dll entry state */
256 omap2_init_memory_params(omap2_dll_force_needed());
257 omap2_reprogram_sdrc(done_rate, 0);
258 }
259 omap2_dpll_recalc(&dpll_ck);
260 ret = 0;
261
262dpll_exit:
263 local_irq_restore(flags);
264 return(ret);
265}
266
267/**
268 * omap2_table_mpu_recalc - just return the MPU speed
269 * @clk: virt_prcm_set struct clk
270 *
271 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
272 */
273static void omap2_table_mpu_recalc(struct clk *clk)
274{
275 clk->rate = curr_prcm_set->mpu_speed;
276}
277
278/*
279 * Look for a rate equal or less than the target rate given a configuration set.
280 *
281 * What's not entirely clear is "which" field represents the key field.
282 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
283 * just uses the ARM rates.
284 */
285static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
286{
287 struct prcm_config *ptr;
288 long highest_rate;
289
290 if (clk != &virt_prcm_set)
291 return -EINVAL;
292
293 highest_rate = -EINVAL;
294
295 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
296 if (!(ptr->flags & cpu_mask))
297 continue;
298 if (ptr->xtal_speed != sys_ck.rate)
299 continue;
300
301 highest_rate = ptr->mpu_speed;
302
303 /* Can check only after xtal frequency check */
304 if (ptr->mpu_speed <= rate)
305 break;
306 }
307 return highest_rate;
308}
309
310/* Sets basic clocks based on the specified rate */
311static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
312{
313 u32 cur_rate, done_rate, bypass = 0, tmp;
314 struct prcm_config *prcm;
315 unsigned long found_speed = 0;
316 unsigned long flags;
317
318 if (clk != &virt_prcm_set)
319 return -EINVAL;
320
321 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
322 if (!(prcm->flags & cpu_mask))
323 continue;
324
325 if (prcm->xtal_speed != sys_ck.rate)
326 continue;
327
328 if (prcm->mpu_speed <= rate) {
329 found_speed = prcm->mpu_speed;
330 break;
331 }
332 }
333
334 if (!found_speed) {
335 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
336 rate / 1000000);
337 return -EINVAL;
338 }
339
340 curr_prcm_set = prcm;
341 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
342
343 if (prcm->dpll_speed == cur_rate / 2) {
344 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
345 } else if (prcm->dpll_speed == cur_rate * 2) {
346 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
347 } else if (prcm->dpll_speed != cur_rate) {
348 local_irq_save(flags);
349
350 if (prcm->dpll_speed == prcm->xtal_speed)
351 bypass = 1;
352
353 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
354 CORE_CLK_SRC_DPLL_X2)
355 done_rate = CORE_CLK_SRC_DPLL_X2;
356 else
357 done_rate = CORE_CLK_SRC_DPLL;
358
359 /* MPU divider */
360 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
361
362 /* dsp + iva1 div(2420), iva2.1(2430) */
363 cm_write_mod_reg(prcm->cm_clksel_dsp,
364 OMAP24XX_DSP_MOD, CM_CLKSEL);
365
366 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
367
368 /* Major subsystem dividers */
369 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
370 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
371 if (cpu_is_omap2430())
372 cm_write_mod_reg(prcm->cm_clksel_mdm,
373 OMAP2430_MDM_MOD, CM_CLKSEL);
374
375 /* x2 to enter init_mem */
376 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
377
378 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
379 bypass);
380
381 omap2_init_memory_params(omap2_dll_force_needed());
382 omap2_reprogram_sdrc(done_rate, 0);
383
384 local_irq_restore(flags);
385 }
386 omap2_dpll_recalc(&dpll_ck);
387
388 return 0;
389}
390
391static struct clk_functions omap2_clk_functions = {
392 .clk_enable = omap2_clk_enable,
393 .clk_disable = omap2_clk_disable,
394 .clk_round_rate = omap2_clk_round_rate,
395 .clk_set_rate = omap2_clk_set_rate,
396 .clk_set_parent = omap2_clk_set_parent,
397 .clk_disable_unused = omap2_clk_disable_unused,
398};
399
400static u32 omap2_get_apll_clkin(void)
401{
402 u32 aplls, sclk = 0;
403
404 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
405 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
406 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
407
408 if (aplls == APLLS_CLKIN_19_2MHZ)
409 sclk = 19200000;
410 else if (aplls == APLLS_CLKIN_13MHZ)
411 sclk = 13000000;
412 else if (aplls == APLLS_CLKIN_12MHZ)
413 sclk = 12000000;
414
415 return sclk;
416}
417
418static u32 omap2_get_sysclkdiv(void)
419{
420 u32 div;
421
422 div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
423 div &= OMAP_SYSCLKDIV_MASK;
424 div >>= OMAP_SYSCLKDIV_SHIFT;
425
426 return div;
427}
428
429static void omap2_osc_clk_recalc(struct clk *clk)
430{
431 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
432 propagate_rate(clk);
433}
434
435static void omap2_sys_clk_recalc(struct clk *clk)
436{
437 clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
438 propagate_rate(clk);
439}
440
441/*
442 * Set clocks for bypass mode for reboot to work.
443 */
444void omap2_clk_prepare_for_reboot(void)
445{
446 u32 rate;
447
448 if (vclk == NULL || sclk == NULL)
449 return;
450
451 rate = clk_get_rate(sclk);
452 clk_set_rate(vclk, rate);
453}
454
455/*
456 * Switch the MPU rate if specified on cmdline.
457 * We cannot do this early until cmdline is parsed.
458 */
459static int __init omap2_clk_arch_init(void)
460{
461 if (!mpurate)
462 return -EINVAL;
463
464 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
465 printk(KERN_ERR "Could not find matching MPU rate\n");
466
467 recalculate_root_clocks();
468
469 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
470 "%ld.%01ld/%ld/%ld MHz\n",
471 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
472 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
473
474 return 0;
475}
476arch_initcall(omap2_clk_arch_init);
477
478int __init omap2_clk_init(void)
479{
480 struct prcm_config *prcm;
481 struct clk **clkp;
482 u32 clkrate;
483
484 if (cpu_is_omap242x())
485 cpu_mask = RATE_IN_242X;
486 else if (cpu_is_omap2430())
487 cpu_mask = RATE_IN_243X;
488
489 clk_init(&omap2_clk_functions);
490
491 omap2_osc_clk_recalc(&osc_ck);
492 omap2_sys_clk_recalc(&sys_ck);
493
494 for (clkp = onchip_24xx_clks;
495 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
496 clkp++) {
497
498 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
499 clk_register(*clkp);
500 continue;
501 }
502
503 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
504 clk_register(*clkp);
505 continue;
506 }
507 }
508
509 /* Check the MPU rate set by bootloader */
510 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
511 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
512 if (!(prcm->flags & cpu_mask))
513 continue;
514 if (prcm->xtal_speed != sys_ck.rate)
515 continue;
516 if (prcm->dpll_speed <= clkrate)
517 break;
518 }
519 curr_prcm_set = prcm;
520
521 recalculate_root_clocks();
522
523 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
524 "%ld.%01ld/%ld/%ld MHz\n",
525 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
526 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
527
528 /*
529 * Only enable those clocks we will need, let the drivers
530 * enable other clocks as necessary
531 */
532 clk_enable_init_clocks();
533
534 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
535 vclk = clk_get(NULL, "virt_prcm_set");
536 sclk = clk_get(NULL, "sys_ck");
537
538 return 0;
539}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
new file mode 100644
index 00000000000..88081ed13f9
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -0,0 +1,2643 @@
1/*
2 * linux/arch/arm/mach-omap2/clock24xx.h
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
18
19#include "clock.h"
20
21#include "prm.h"
22#include "cm.h"
23#include "prm-regbits-24xx.h"
24#include "cm-regbits-24xx.h"
25#include "sdrc.h"
26
27static void omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpll_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
39
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
42 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
43 */
44struct prcm_config {
45 unsigned long xtal_speed; /* crystal rate */
46 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
47 unsigned long mpu_speed; /* speed of MPU */
48 unsigned long cm_clksel_mpu; /* mpu divider */
49 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
50 unsigned long cm_clksel_gfx; /* gfx dividers */
51 unsigned long cm_clksel1_core; /* major subsystem dividers */
52 unsigned long cm_clksel1_pll; /* m,n */
53 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
54 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
55 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 unsigned char flags;
57};
58
59/*
60 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
61 * These configurations are characterized by voltage and speed for clocks.
62 * The device is only validated for certain combinations. One way to express
63 * these combinations is via the 'ratio's' which the clocks operate with
64 * respect to each other. These ratio sets are for a given voltage/DPLL
65 * setting. All configurations can be described by a DPLL setting and a ratio
66 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
67 *
68 * 2430 differs from 2420 in that there are no more phase synchronizers used.
69 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
70 * 2430 (iva2.1, NOdsp, mdm)
71 */
72
73/* Core fields for cm_clksel, not ratio governed */
74#define RX_CLKSEL_DSS1 (0x10 << 8)
75#define RX_CLKSEL_DSS2 (0x0 << 13)
76#define RX_CLKSEL_SSI (0x5 << 20)
77
78/*-------------------------------------------------------------------------
79 * Voltage/DPLL ratios
80 *-------------------------------------------------------------------------*/
81
82/* 2430 Ratio's, 2430-Ratio Config 1 */
83#define R1_CLKSEL_L3 (4 << 0)
84#define R1_CLKSEL_L4 (2 << 5)
85#define R1_CLKSEL_USB (4 << 25)
86#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
87 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
88 R1_CLKSEL_L4 | R1_CLKSEL_L3
89#define R1_CLKSEL_MPU (2 << 0)
90#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
91#define R1_CLKSEL_DSP (2 << 0)
92#define R1_CLKSEL_DSP_IF (2 << 5)
93#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
94#define R1_CLKSEL_GFX (2 << 0)
95#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
96#define R1_CLKSEL_MDM (4 << 0)
97#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
98
99/* 2430-Ratio Config 2 */
100#define R2_CLKSEL_L3 (6 << 0)
101#define R2_CLKSEL_L4 (2 << 5)
102#define R2_CLKSEL_USB (2 << 25)
103#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
104 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
105 R2_CLKSEL_L4 | R2_CLKSEL_L3
106#define R2_CLKSEL_MPU (2 << 0)
107#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
108#define R2_CLKSEL_DSP (2 << 0)
109#define R2_CLKSEL_DSP_IF (3 << 5)
110#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
111#define R2_CLKSEL_GFX (2 << 0)
112#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
113#define R2_CLKSEL_MDM (6 << 0)
114#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
115
116/* 2430-Ratio Bootm (BYPASS) */
117#define RB_CLKSEL_L3 (1 << 0)
118#define RB_CLKSEL_L4 (1 << 5)
119#define RB_CLKSEL_USB (1 << 25)
120#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
121 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
122 RB_CLKSEL_L4 | RB_CLKSEL_L3
123#define RB_CLKSEL_MPU (1 << 0)
124#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
125#define RB_CLKSEL_DSP (1 << 0)
126#define RB_CLKSEL_DSP_IF (1 << 5)
127#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
128#define RB_CLKSEL_GFX (1 << 0)
129#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
130#define RB_CLKSEL_MDM (1 << 0)
131#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
132
133/* 2420 Ratio Equivalents */
134#define RXX_CLKSEL_VLYNQ (0x12 << 15)
135#define RXX_CLKSEL_SSI (0x8 << 20)
136
137/* 2420-PRCM III 532MHz core */
138#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
139#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
140#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
141#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
142 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
143 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
144 RIII_CLKSEL_L3
145#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
146#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
147#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
148#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
149#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
150#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
151#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
152#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
153 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
154 RIII_CLKSEL_DSP
155#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
156#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
157
158/* 2420-PRCM II 600MHz core */
159#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
160#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
161#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
162#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
163 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
164 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
165 RII_CLKSEL_L4 | RII_CLKSEL_L3
166#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
167#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
168#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
169#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
170#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
171#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
172#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
173#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
174 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
175 RII_CLKSEL_DSP
176#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
177#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
178
179/* 2420-PRCM I 660MHz core */
180#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
181#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
182#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
183#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
184 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
185 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
186 RI_CLKSEL_L4 | RI_CLKSEL_L3
187#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
188#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
189#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
190#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
191#define RI_SYNC_DSP (1 << 7) /* Activate sync */
192#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
193#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
194#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
195 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
196 RI_CLKSEL_DSP
197#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
198#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
199
200/* 2420-PRCM VII (boot) */
201#define RVII_CLKSEL_L3 (1 << 0)
202#define RVII_CLKSEL_L4 (1 << 5)
203#define RVII_CLKSEL_DSS1 (1 << 8)
204#define RVII_CLKSEL_DSS2 (0 << 13)
205#define RVII_CLKSEL_VLYNQ (1 << 15)
206#define RVII_CLKSEL_SSI (1 << 20)
207#define RVII_CLKSEL_USB (1 << 25)
208
209#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
210 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
211 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
212
213#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
214#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
215
216#define RVII_CLKSEL_DSP (1 << 0)
217#define RVII_CLKSEL_DSP_IF (1 << 5)
218#define RVII_SYNC_DSP (0 << 7)
219#define RVII_CLKSEL_IVA (1 << 8)
220#define RVII_SYNC_IVA (0 << 13)
221#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
222 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
223
224#define RVII_CLKSEL_GFX (1 << 0)
225#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
226
227/*-------------------------------------------------------------------------
228 * 2430 Target modes: Along with each configuration the CPU has several
229 * modes which goes along with them. Modes mainly are the addition of
230 * describe DPLL combinations to go along with a ratio.
231 *-------------------------------------------------------------------------*/
232
233/* Hardware governed */
234#define MX_48M_SRC (0 << 3)
235#define MX_54M_SRC (0 << 5)
236#define MX_APLLS_CLIKIN_12 (3 << 23)
237#define MX_APLLS_CLIKIN_13 (2 << 23)
238#define MX_APLLS_CLIKIN_19_2 (0 << 23)
239
240/*
241 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
243 */
244#define M5A_DPLL_MULT_12 (133 << 12)
245#define M5A_DPLL_DIV_12 (5 << 8)
246#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
248 MX_APLLS_CLIKIN_12
249#define M5A_DPLL_MULT_13 (61 << 12)
250#define M5A_DPLL_DIV_13 (2 << 8)
251#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
253 MX_APLLS_CLIKIN_13
254#define M5A_DPLL_MULT_19 (55 << 12)
255#define M5A_DPLL_DIV_19 (3 << 8)
256#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
258 MX_APLLS_CLIKIN_19_2
259/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
260#define M5B_DPLL_MULT_12 (50 << 12)
261#define M5B_DPLL_DIV_12 (2 << 8)
262#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
264 MX_APLLS_CLIKIN_12
265#define M5B_DPLL_MULT_13 (200 << 12)
266#define M5B_DPLL_DIV_13 (12 << 8)
267
268#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
270 MX_APLLS_CLIKIN_13
271#define M5B_DPLL_MULT_19 (125 << 12)
272#define M5B_DPLL_DIV_19 (31 << 8)
273#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
275 MX_APLLS_CLIKIN_19_2
276/*
277 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
278 */
279#define M4_DPLL_MULT_12 (133 << 12)
280#define M4_DPLL_DIV_12 (3 << 8)
281#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
282 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
283 MX_APLLS_CLIKIN_12
284
285#define M4_DPLL_MULT_13 (399 << 12)
286#define M4_DPLL_DIV_13 (12 << 8)
287#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
288 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
289 MX_APLLS_CLIKIN_13
290
291#define M4_DPLL_MULT_19 (145 << 12)
292#define M4_DPLL_DIV_19 (6 << 8)
293#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
294 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
295 MX_APLLS_CLIKIN_19_2
296
297/*
298 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
299 */
300#define M3_DPLL_MULT_12 (55 << 12)
301#define M3_DPLL_DIV_12 (1 << 8)
302#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
303 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
304 MX_APLLS_CLIKIN_12
305#define M3_DPLL_MULT_13 (76 << 12)
306#define M3_DPLL_DIV_13 (2 << 8)
307#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
308 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
309 MX_APLLS_CLIKIN_13
310#define M3_DPLL_MULT_19 (17 << 12)
311#define M3_DPLL_DIV_19 (0 << 8)
312#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
313 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
314 MX_APLLS_CLIKIN_19_2
315
316/*
317 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
318 */
319#define M2_DPLL_MULT_12 (55 << 12)
320#define M2_DPLL_DIV_12 (1 << 8)
321#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324
325/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
326 * relock time issue */
327/* Core frequency changed from 330/165 to 329/164 MHz*/
328#define M2_DPLL_MULT_13 (76 << 12)
329#define M2_DPLL_DIV_13 (2 << 8)
330#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
331 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
332 MX_APLLS_CLIKIN_13
333
334#define M2_DPLL_MULT_19 (17 << 12)
335#define M2_DPLL_DIV_19 (0 << 8)
336#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
337 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
338 MX_APLLS_CLIKIN_19_2
339
340/* boot (boot) */
341#define MB_DPLL_MULT (1 << 12)
342#define MB_DPLL_DIV (0 << 8)
343#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
344 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
345
346#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
347 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
348
349#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
350 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
351
352/*
353 * 2430 - chassis (sedna)
354 * 165 (ratio1) same as above #2
355 * 150 (ratio1)
356 * 133 (ratio2) same as above #4
357 * 110 (ratio2) same as above #3
358 * 104 (ratio2)
359 * boot (boot)
360 */
361
362/* PRCM I target DPLL = 2*330MHz = 660MHz */
363#define MI_DPLL_MULT_12 (55 << 12)
364#define MI_DPLL_DIV_12 (1 << 8)
365#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
366 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
367 MX_APLLS_CLIKIN_12
368
369/*
370 * 2420 Equivalent - mode registers
371 * PRCM II , target DPLL = 2*300MHz = 600MHz
372 */
373#define MII_DPLL_MULT_12 (50 << 12)
374#define MII_DPLL_DIV_12 (1 << 8)
375#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
376 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
377 MX_APLLS_CLIKIN_12
378#define MII_DPLL_MULT_13 (300 << 12)
379#define MII_DPLL_DIV_13 (12 << 8)
380#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
381 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
382 MX_APLLS_CLIKIN_13
383
384/* PRCM III target DPLL = 2*266 = 532MHz*/
385#define MIII_DPLL_MULT_12 (133 << 12)
386#define MIII_DPLL_DIV_12 (5 << 8)
387#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
388 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
389 MX_APLLS_CLIKIN_12
390#define MIII_DPLL_MULT_13 (266 << 12)
391#define MIII_DPLL_DIV_13 (12 << 8)
392#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
393 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
394 MX_APLLS_CLIKIN_13
395
396/* PRCM VII (boot bypass) */
397#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
398#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
399
400/* High and low operation value */
401#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
402#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
403
404/* MPU speed defines */
405#define S12M 12000000
406#define S13M 13000000
407#define S19M 19200000
408#define S26M 26000000
409#define S100M 100000000
410#define S133M 133000000
411#define S150M 150000000
412#define S164M 164000000
413#define S165M 165000000
414#define S199M 199000000
415#define S200M 200000000
416#define S266M 266000000
417#define S300M 300000000
418#define S329M 329000000
419#define S330M 330000000
420#define S399M 399000000
421#define S400M 400000000
422#define S532M 532000000
423#define S600M 600000000
424#define S658M 658000000
425#define S660M 660000000
426#define S798M 798000000
427
428/*-------------------------------------------------------------------------
429 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
430 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
431 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
432 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
433 *
434 * Filling in table based on H4 boards and 2430-SDPs variants available.
435 * There are quite a few more rates combinations which could be defined.
436 *
437 * When multiple values are defined the start up will try and choose the
438 * fastest one. If a 'fast' value is defined, then automatically, the /2
439 * one should be included as it can be used. Generally having more that
440 * one fast set does not make sense, as static timings need to be changed
441 * to change the set. The exception is the bypass setting which is
442 * availble for low power bypass.
443 *
444 * Note: This table needs to be sorted, fastest to slowest.
445 *-------------------------------------------------------------------------*/
446static struct prcm_config rate_table[] = {
447 /* PRCM I - FAST */
448 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
449 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
450 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
451 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
452 RATE_IN_242X},
453
454 /* PRCM II - FAST */
455 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
456 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
457 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
459 RATE_IN_242X},
460
461 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
462 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
463 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
464 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
465 RATE_IN_242X},
466
467 /* PRCM III - FAST */
468 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
469 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
470 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
472 RATE_IN_242X},
473
474 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
475 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
476 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
477 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
478 RATE_IN_242X},
479
480 /* PRCM II - SLOW */
481 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
482 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
483 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
485 RATE_IN_242X},
486
487 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
488 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
489 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
490 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
491 RATE_IN_242X},
492
493 /* PRCM III - SLOW */
494 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
495 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
496 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
498 RATE_IN_242X},
499
500 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
501 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
502 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
503 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
504 RATE_IN_242X},
505
506 /* PRCM-VII (boot-bypass) */
507 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
508 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
509 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
511 RATE_IN_242X},
512
513 /* PRCM-VII (boot-bypass) */
514 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
518 RATE_IN_242X},
519
520 /* PRCM #4 - ratio2 (ES2.1) - FAST */
521 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
522 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
523 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
524 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
525 SDRC_RFR_CTRL_133MHz,
526 RATE_IN_243X},
527
528 /* PRCM #2 - ratio1 (ES2) - FAST */
529 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
530 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
531 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
532 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
533 SDRC_RFR_CTRL_165MHz,
534 RATE_IN_243X},
535
536 /* PRCM #5a - ratio1 - FAST */
537 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
538 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
539 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
540 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
541 SDRC_RFR_CTRL_133MHz,
542 RATE_IN_243X},
543
544 /* PRCM #5b - ratio1 - FAST */
545 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
546 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
547 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
548 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
549 SDRC_RFR_CTRL_100MHz,
550 RATE_IN_243X},
551
552 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
553 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
554 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
555 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
556 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
557 SDRC_RFR_CTRL_133MHz,
558 RATE_IN_243X},
559
560 /* PRCM #2 - ratio1 (ES2) - SLOW */
561 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
562 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
563 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
564 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
565 SDRC_RFR_CTRL_165MHz,
566 RATE_IN_243X},
567
568 /* PRCM #5a - ratio1 - SLOW */
569 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
570 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
571 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
572 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
573 SDRC_RFR_CTRL_133MHz,
574 RATE_IN_243X},
575
576 /* PRCM #5b - ratio1 - SLOW*/
577 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
578 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
579 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
580 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
581 SDRC_RFR_CTRL_100MHz,
582 RATE_IN_243X},
583
584 /* PRCM-boot/bypass */
585 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
586 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
587 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
588 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
589 SDRC_RFR_CTRL_BYPASS,
590 RATE_IN_243X},
591
592 /* PRCM-boot/bypass */
593 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
594 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
595 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
596 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
597 SDRC_RFR_CTRL_BYPASS,
598 RATE_IN_243X},
599
600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
601};
602
603/*-------------------------------------------------------------------------
604 * 24xx clock tree.
605 *
606 * NOTE:In many cases here we are assigning a 'default' parent. In many
607 * cases the parent is selectable. The get/set parent calls will also
608 * switch sources.
609 *
610 * Many some clocks say always_enabled, but they can be auto idled for
611 * power savings. They will always be available upon clock request.
612 *
613 * Several sources are given initial rates which may be wrong, this will
614 * be fixed up in the init func.
615 *
616 * Things are broadly separated below by clock domains. It is
617 * noteworthy that most periferals have dependencies on multiple clock
618 * domains. Many get their interface clocks from the L4 domain, but get
619 * functional clocks from fixed sources or other core domain derived
620 * clocks.
621 *-------------------------------------------------------------------------*/
622
623/* Base external input clocks */
624static struct clk func_32k_ck = {
625 .name = "func_32k_ck",
626 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .recalc = &propagate_rate,
630};
631
632/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
633static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
634 .name = "osc_ck",
635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
636 RATE_PROPAGATES,
637 .enable = &omap2_enable_osc_ck,
638 .disable = &omap2_disable_osc_ck,
639 .recalc = &omap2_osc_clk_recalc,
640};
641
642/* With out modem likely 12MHz, with modem likely 13MHz */
643static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
644 .name = "sys_ck", /* ~ ref_clk also */
645 .parent = &osc_ck,
646 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
647 ALWAYS_ENABLED | RATE_PROPAGATES,
648 .recalc = &omap2_sys_clk_recalc,
649};
650
651static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
652 .name = "alt_ck",
653 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
656 .recalc = &propagate_rate,
657};
658
659/*
660 * Analog domain root source clocks
661 */
662
663/* dpll_ck, is broken out in to special cases through clksel */
664/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
665 * deal with this
666 */
667
668static const struct dpll_data dpll_dd = {
669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
671 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
672};
673
674static struct clk dpll_ck = {
675 .name = "dpll_ck",
676 .parent = &sys_ck, /* Can be func_32k also */
677 .dpll_data = &dpll_dd,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_PROPAGATES | ALWAYS_ENABLED,
680 .recalc = &omap2_dpll_recalc,
681 .set_rate = &omap2_reprogram_dpll,
682};
683
684static struct clk apll96_ck = {
685 .name = "apll96_ck",
686 .parent = &sys_ck,
687 .rate = 96000000,
688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
689 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
690 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
691 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
692 .enable = &omap2_clk_fixed_enable,
693 .disable = &omap2_clk_fixed_disable,
694 .recalc = &propagate_rate,
695};
696
697static struct clk apll54_ck = {
698 .name = "apll54_ck",
699 .parent = &sys_ck,
700 .rate = 54000000,
701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
702 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
708};
709
710/*
711 * PRCM digital base sources
712 */
713
714/* func_54m_ck */
715
716static const struct clksel_rate func_54m_apll54_rates[] = {
717 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
718 { .div = 0 },
719};
720
721static const struct clksel_rate func_54m_alt_rates[] = {
722 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
723 { .div = 0 },
724};
725
726static const struct clksel func_54m_clksel[] = {
727 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
728 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
729 { .parent = NULL },
730};
731
732static struct clk func_54m_ck = {
733 .name = "func_54m_ck",
734 .parent = &apll54_ck, /* can also be alt_clk */
735 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
736 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
737 .init = &omap2_init_clksel_parent,
738 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
739 .clksel_mask = OMAP24XX_54M_SOURCE,
740 .clksel = func_54m_clksel,
741 .recalc = &omap2_clksel_recalc,
742};
743
744static struct clk core_ck = {
745 .name = "core_ck",
746 .parent = &dpll_ck, /* can also be 32k */
747 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
748 ALWAYS_ENABLED | RATE_PROPAGATES,
749 .recalc = &followparent_recalc,
750};
751
752/* func_96m_ck */
753static const struct clksel_rate func_96m_apll96_rates[] = {
754 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
755 { .div = 0 },
756};
757
758static const struct clksel_rate func_96m_alt_rates[] = {
759 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
760 { .div = 0 },
761};
762
763static const struct clksel func_96m_clksel[] = {
764 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
765 { .parent = &alt_ck, .rates = func_96m_alt_rates },
766 { .parent = NULL }
767};
768
769/* The parent of this clock is not selectable on 2420. */
770static struct clk func_96m_ck = {
771 .name = "func_96m_ck",
772 .parent = &apll96_ck,
773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
774 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP2430_96M_SOURCE,
778 .clksel = func_96m_clksel,
779 .recalc = &omap2_clksel_recalc,
780 .round_rate = &omap2_clksel_round_rate,
781 .set_rate = &omap2_clksel_set_rate
782};
783
784/* func_48m_ck */
785
786static const struct clksel_rate func_48m_apll96_rates[] = {
787 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
788 { .div = 0 },
789};
790
791static const struct clksel_rate func_48m_alt_rates[] = {
792 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
793 { .div = 0 },
794};
795
796static const struct clksel func_48m_clksel[] = {
797 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
798 { .parent = &alt_ck, .rates = func_48m_alt_rates },
799 { .parent = NULL }
800};
801
802static struct clk func_48m_ck = {
803 .name = "func_48m_ck",
804 .parent = &apll96_ck, /* 96M or Alt */
805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
806 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
807 .init = &omap2_init_clksel_parent,
808 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
809 .clksel_mask = OMAP24XX_48M_SOURCE,
810 .clksel = func_48m_clksel,
811 .recalc = &omap2_clksel_recalc,
812 .round_rate = &omap2_clksel_round_rate,
813 .set_rate = &omap2_clksel_set_rate
814};
815
816static struct clk func_12m_ck = {
817 .name = "func_12m_ck",
818 .parent = &func_48m_ck,
819 .fixed_div = 4,
820 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
821 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
822 .recalc = &omap2_fixed_divisor_recalc,
823};
824
825/* Secure timer, only available in secure mode */
826static struct clk wdt1_osc_ck = {
827 .name = "ck_wdt1_osc",
828 .parent = &osc_ck,
829 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
830 .recalc = &followparent_recalc,
831};
832
833/*
834 * The common_clkout* clksel_rate structs are common to
835 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
836 * sys_clkout2_* are 2420-only, so the
837 * clksel_rate flags fields are inaccurate for those clocks. This is
838 * harmless since access to those clocks are gated by the struct clk
839 * flags fields, which mark them as 2420-only.
840 */
841static const struct clksel_rate common_clkout_src_core_rates[] = {
842 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
843 { .div = 0 }
844};
845
846static const struct clksel_rate common_clkout_src_sys_rates[] = {
847 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
848 { .div = 0 }
849};
850
851static const struct clksel_rate common_clkout_src_96m_rates[] = {
852 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
853 { .div = 0 }
854};
855
856static const struct clksel_rate common_clkout_src_54m_rates[] = {
857 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
858 { .div = 0 }
859};
860
861static const struct clksel common_clkout_src_clksel[] = {
862 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
863 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
864 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
865 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
866 { .parent = NULL }
867};
868
869static struct clk sys_clkout_src = {
870 .name = "sys_clkout_src",
871 .parent = &func_54m_ck,
872 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
873 RATE_PROPAGATES,
874 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
875 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
876 .init = &omap2_init_clksel_parent,
877 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
878 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
879 .clksel = common_clkout_src_clksel,
880 .recalc = &omap2_clksel_recalc,
881 .round_rate = &omap2_clksel_round_rate,
882 .set_rate = &omap2_clksel_set_rate
883};
884
885static const struct clksel_rate common_clkout_rates[] = {
886 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
887 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
888 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
889 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
890 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
891 { .div = 0 },
892};
893
894static const struct clksel sys_clkout_clksel[] = {
895 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
896 { .parent = NULL }
897};
898
899static struct clk sys_clkout = {
900 .name = "sys_clkout",
901 .parent = &sys_clkout_src,
902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
903 PARENT_CONTROLS_CLOCK,
904 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
905 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
906 .clksel = sys_clkout_clksel,
907 .recalc = &omap2_clksel_recalc,
908 .round_rate = &omap2_clksel_round_rate,
909 .set_rate = &omap2_clksel_set_rate
910};
911
912/* In 2430, new in 2420 ES2 */
913static struct clk sys_clkout2_src = {
914 .name = "sys_clkout2_src",
915 .parent = &func_54m_ck,
916 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
917 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
918 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
919 .init = &omap2_init_clksel_parent,
920 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
921 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
922 .clksel = common_clkout_src_clksel,
923 .recalc = &omap2_clksel_recalc,
924 .round_rate = &omap2_clksel_round_rate,
925 .set_rate = &omap2_clksel_set_rate
926};
927
928static const struct clksel sys_clkout2_clksel[] = {
929 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
930 { .parent = NULL }
931};
932
933/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2 = {
935 .name = "sys_clkout2",
936 .parent = &sys_clkout2_src,
937 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
938 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
939 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
940 .clksel = sys_clkout2_clksel,
941 .recalc = &omap2_clksel_recalc,
942 .round_rate = &omap2_clksel_round_rate,
943 .set_rate = &omap2_clksel_set_rate
944};
945
946static struct clk emul_ck = {
947 .name = "emul_ck",
948 .parent = &func_54m_ck,
949 .flags = CLOCK_IN_OMAP242X,
950 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
951 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
952 .recalc = &followparent_recalc,
953
954};
955
956/*
957 * MPU clock domain
958 * Clocks:
959 * MPU_FCLK, MPU_ICLK
960 * INT_M_FCLK, INT_M_I_CLK
961 *
962 * - Individual clocks are hardware managed.
963 * - Base divider comes from: CM_CLKSEL_MPU
964 *
965 */
966static const struct clksel_rate mpu_core_rates[] = {
967 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
969 { .div = 4, .val = 4, .flags = RATE_IN_242X },
970 { .div = 6, .val = 6, .flags = RATE_IN_242X },
971 { .div = 8, .val = 8, .flags = RATE_IN_242X },
972 { .div = 0 },
973};
974
975static const struct clksel mpu_clksel[] = {
976 { .parent = &core_ck, .rates = mpu_core_rates },
977 { .parent = NULL }
978};
979
980static struct clk mpu_ck = { /* Control cpu */
981 .name = "mpu_ck",
982 .parent = &core_ck,
983 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
984 ALWAYS_ENABLED | DELAYED_APP |
985 CONFIG_PARTICIPANT | RATE_PROPAGATES,
986 .init = &omap2_init_clksel_parent,
987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
988 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
989 .clksel = mpu_clksel,
990 .recalc = &omap2_clksel_recalc,
991 .round_rate = &omap2_clksel_round_rate,
992 .set_rate = &omap2_clksel_set_rate
993};
994
995/*
996 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
997 * Clocks:
998 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
999 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1000 *
1001 * Won't be too specific here. The core clock comes into this block
1002 * it is divided then tee'ed. One branch goes directly to xyz enable
1003 * controls. The other branch gets further divided by 2 then possibly
1004 * routed into a synchronizer and out of clocks abc.
1005 */
1006static const struct clksel_rate dsp_fck_core_rates[] = {
1007 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1008 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1009 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1010 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1011 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1012 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1013 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1014 { .div = 0 },
1015};
1016
1017static const struct clksel dsp_fck_clksel[] = {
1018 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1019 { .parent = NULL }
1020};
1021
1022static struct clk dsp_fck = {
1023 .name = "dsp_fck",
1024 .parent = &core_ck,
1025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1026 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1027 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1028 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1029 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1030 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1031 .clksel = dsp_fck_clksel,
1032 .recalc = &omap2_clksel_recalc,
1033 .round_rate = &omap2_clksel_round_rate,
1034 .set_rate = &omap2_clksel_set_rate
1035};
1036
1037/* DSP interface clock */
1038static const struct clksel_rate dsp_irate_ick_rates[] = {
1039 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1040 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1041 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1042 { .div = 0 },
1043};
1044
1045static const struct clksel dsp_irate_ick_clksel[] = {
1046 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1047 { .parent = NULL }
1048};
1049
1050/*
1051 * This clock does not exist as such in the TRM, but is added to
1052 * separate source selection from XXX
1053 */
1054static struct clk dsp_irate_ick = {
1055 .name = "dsp_irate_ick",
1056 .parent = &dsp_fck,
1057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1058 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1059 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1060 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1061 .clksel = dsp_irate_ick_clksel,
1062 .recalc = &omap2_clksel_recalc,
1063 .round_rate = &omap2_clksel_round_rate,
1064 .set_rate = &omap2_clksel_set_rate
1065};
1066
1067/* 2420 only */
1068static struct clk dsp_ick = {
1069 .name = "dsp_ick", /* apparently ipi and isp */
1070 .parent = &dsp_irate_ick,
1071 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1072 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1073 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1074};
1075
1076/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1077static struct clk iva2_1_ick = {
1078 .name = "iva2_1_ick",
1079 .parent = &dsp_irate_ick,
1080 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1081 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1082 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1083};
1084
1085static struct clk iva1_ifck = {
1086 .name = "iva1_ifck",
1087 .parent = &core_ck,
1088 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1089 RATE_PROPAGATES | DELAYED_APP,
1090 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1091 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1092 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1093 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1094 .clksel = dsp_fck_clksel,
1095 .recalc = &omap2_clksel_recalc,
1096 .round_rate = &omap2_clksel_round_rate,
1097 .set_rate = &omap2_clksel_set_rate
1098};
1099
1100/* IVA1 mpu/int/i/f clocks are /2 of parent */
1101static struct clk iva1_mpu_int_ifck = {
1102 .name = "iva1_mpu_int_ifck",
1103 .parent = &iva1_ifck,
1104 .flags = CLOCK_IN_OMAP242X,
1105 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1106 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1107 .fixed_div = 2,
1108 .recalc = &omap2_fixed_divisor_recalc,
1109};
1110
1111/*
1112 * L3 clock domain
1113 * L3 clocks are used for both interface and functional clocks to
1114 * multiple entities. Some of these clocks are completely managed
1115 * by hardware, and some others allow software control. Hardware
1116 * managed ones general are based on directly CLK_REQ signals and
1117 * various auto idle settings. The functional spec sets many of these
1118 * as 'tie-high' for their enables.
1119 *
1120 * I-CLOCKS:
1121 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1122 * CAM, HS-USB.
1123 * F-CLOCK
1124 * SSI.
1125 *
1126 * GPMC memories and SDRC have timing and clock sensitive registers which
1127 * may very well need notification when the clock changes. Currently for low
1128 * operating points, these are taken care of in sleep.S.
1129 */
1130static const struct clksel_rate core_l3_core_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1132 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1133 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1134 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1135 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1136 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1137 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1138 { .div = 0 }
1139};
1140
1141static const struct clksel core_l3_clksel[] = {
1142 { .parent = &core_ck, .rates = core_l3_core_rates },
1143 { .parent = NULL }
1144};
1145
1146static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1147 .name = "core_l3_ck",
1148 .parent = &core_ck,
1149 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1150 ALWAYS_ENABLED | DELAYED_APP |
1151 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1153 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1154 .clksel = core_l3_clksel,
1155 .recalc = &omap2_clksel_recalc,
1156 .round_rate = &omap2_clksel_round_rate,
1157 .set_rate = &omap2_clksel_set_rate
1158};
1159
1160/* usb_l4_ick */
1161static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1162 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1163 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1164 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1165 { .div = 0 }
1166};
1167
1168static const struct clksel usb_l4_ick_clksel[] = {
1169 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1170 { .parent = NULL },
1171};
1172
1173static struct clk usb_l4_ick = { /* FS-USB interface clock */
1174 .name = "usb_l4_ick",
1175 .parent = &core_l3_ck,
1176 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1177 DELAYED_APP | CONFIG_PARTICIPANT,
1178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1179 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1180 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1181 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1182 .clksel = usb_l4_ick_clksel,
1183 .recalc = &omap2_clksel_recalc,
1184 .round_rate = &omap2_clksel_round_rate,
1185 .set_rate = &omap2_clksel_set_rate
1186};
1187
1188/*
1189 * SSI is in L3 management domain, its direct parent is core not l3,
1190 * many core power domain entities are grouped into the L3 clock
1191 * domain.
1192 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1193 *
1194 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1195 */
1196static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1197 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1198 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1199 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1200 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1201 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1202 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1203 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1204 { .div = 0 }
1205};
1206
1207static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1208 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1209 { .parent = NULL }
1210};
1211
1212static struct clk ssi_ssr_sst_fck = {
1213 .name = "ssi_fck",
1214 .parent = &core_ck,
1215 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1216 DELAYED_APP,
1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1218 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1219 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1220 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1221 .clksel = ssi_ssr_sst_fck_clksel,
1222 .recalc = &omap2_clksel_recalc,
1223 .round_rate = &omap2_clksel_round_rate,
1224 .set_rate = &omap2_clksel_set_rate
1225};
1226
1227/*
1228 * GFX clock domain
1229 * Clocks:
1230 * GFX_FCLK, GFX_ICLK
1231 * GFX_CG1(2d), GFX_CG2(3d)
1232 *
1233 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1234 * The 2d and 3d clocks run at a hardware determined
1235 * divided value of fclk.
1236 *
1237 */
1238/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1239
1240/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1241static const struct clksel gfx_fck_clksel[] = {
1242 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1243 { .parent = NULL },
1244};
1245
1246static struct clk gfx_3d_fck = {
1247 .name = "gfx_3d_fck",
1248 .parent = &core_l3_ck,
1249 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1250 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1252 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1253 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1254 .clksel = gfx_fck_clksel,
1255 .recalc = &omap2_clksel_recalc,
1256 .round_rate = &omap2_clksel_round_rate,
1257 .set_rate = &omap2_clksel_set_rate
1258};
1259
1260static struct clk gfx_2d_fck = {
1261 .name = "gfx_2d_fck",
1262 .parent = &core_l3_ck,
1263 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1264 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1265 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1268 .clksel = gfx_fck_clksel,
1269 .recalc = &omap2_clksel_recalc,
1270 .round_rate = &omap2_clksel_round_rate,
1271 .set_rate = &omap2_clksel_set_rate
1272};
1273
1274static struct clk gfx_ick = {
1275 .name = "gfx_ick", /* From l3 */
1276 .parent = &core_l3_ck,
1277 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1278 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1279 .enable_bit = OMAP_EN_GFX_SHIFT,
1280 .recalc = &followparent_recalc,
1281};
1282
1283/*
1284 * Modem clock domain (2430)
1285 * CLOCKS:
1286 * MDM_OSC_CLK
1287 * MDM_ICLK
1288 * These clocks are usable in chassis mode only.
1289 */
1290static const struct clksel_rate mdm_ick_core_rates[] = {
1291 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1292 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1293 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1294 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1295 { .div = 0 }
1296};
1297
1298static const struct clksel mdm_ick_clksel[] = {
1299 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1300 { .parent = NULL }
1301};
1302
1303static struct clk mdm_ick = { /* used both as a ick and fck */
1304 .name = "mdm_ick",
1305 .parent = &core_ck,
1306 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1307 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1308 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1309 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1310 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1311 .clksel = mdm_ick_clksel,
1312 .recalc = &omap2_clksel_recalc,
1313 .round_rate = &omap2_clksel_round_rate,
1314 .set_rate = &omap2_clksel_set_rate
1315};
1316
1317static struct clk mdm_osc_ck = {
1318 .name = "mdm_osc_ck",
1319 .parent = &osc_ck,
1320 .flags = CLOCK_IN_OMAP243X,
1321 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1322 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1323 .recalc = &followparent_recalc,
1324};
1325
1326/*
1327 * L4 clock management domain
1328 *
1329 * This domain contains lots of interface clocks from the L4 interface, some
1330 * functional clocks. Fixed APLL functional source clocks are managed in
1331 * this domain.
1332 */
1333static const struct clksel_rate l4_core_l3_rates[] = {
1334 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1335 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1336 { .div = 0 }
1337};
1338
1339static const struct clksel l4_clksel[] = {
1340 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1341 { .parent = NULL }
1342};
1343
1344static struct clk l4_ck = { /* used both as an ick and fck */
1345 .name = "l4_ck",
1346 .parent = &core_l3_ck,
1347 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1348 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1349 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1350 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1351 .clksel = l4_clksel,
1352 .recalc = &omap2_clksel_recalc,
1353 .round_rate = &omap2_clksel_round_rate,
1354 .set_rate = &omap2_clksel_set_rate
1355};
1356
1357static struct clk ssi_l4_ick = {
1358 .name = "ssi_l4_ick",
1359 .parent = &l4_ck,
1360 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1362 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1363 .recalc = &followparent_recalc,
1364};
1365
1366/*
1367 * DSS clock domain
1368 * CLOCKs:
1369 * DSS_L4_ICLK, DSS_L3_ICLK,
1370 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1371 *
1372 * DSS is both initiator and target.
1373 */
1374/* XXX Add RATE_NOT_VALIDATED */
1375
1376static const struct clksel_rate dss1_fck_sys_rates[] = {
1377 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1378 { .div = 0 }
1379};
1380
1381static const struct clksel_rate dss1_fck_core_rates[] = {
1382 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1383 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1384 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1385 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1386 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1387 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1388 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1389 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1390 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1391 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1392 { .div = 0 }
1393};
1394
1395static const struct clksel dss1_fck_clksel[] = {
1396 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1397 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1398 { .parent = NULL },
1399};
1400
1401static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1402 .name = "dss_ick",
1403 .parent = &l4_ck, /* really both l3 and l4 */
1404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1406 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1407 .recalc = &followparent_recalc,
1408};
1409
1410static struct clk dss1_fck = {
1411 .name = "dss1_fck",
1412 .parent = &core_ck, /* Core or sys */
1413 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1414 DELAYED_APP,
1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1417 .init = &omap2_init_clksel_parent,
1418 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1419 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1420 .clksel = dss1_fck_clksel,
1421 .recalc = &omap2_clksel_recalc,
1422 .round_rate = &omap2_clksel_round_rate,
1423 .set_rate = &omap2_clksel_set_rate
1424};
1425
1426static const struct clksel_rate dss2_fck_sys_rates[] = {
1427 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1428 { .div = 0 }
1429};
1430
1431static const struct clksel_rate dss2_fck_48m_rates[] = {
1432 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1433 { .div = 0 }
1434};
1435
1436static const struct clksel dss2_fck_clksel[] = {
1437 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1438 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1439 { .parent = NULL }
1440};
1441
1442static struct clk dss2_fck = { /* Alt clk used in power management */
1443 .name = "dss2_fck",
1444 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1445 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1446 DELAYED_APP,
1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1449 .init = &omap2_init_clksel_parent,
1450 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1451 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1452 .clksel = dss2_fck_clksel,
1453 .recalc = &followparent_recalc,
1454};
1455
1456static struct clk dss_54m_fck = { /* Alt clk used in power management */
1457 .name = "dss_54m_fck", /* 54m tv clk */
1458 .parent = &func_54m_ck,
1459 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1462 .recalc = &followparent_recalc,
1463};
1464
1465/*
1466 * CORE power domain ICLK & FCLK defines.
1467 * Many of the these can have more than one possible parent. Entries
1468 * here will likely have an L4 interface parent, and may have multiple
1469 * functional clock parents.
1470 */
1471static const struct clksel_rate gpt_alt_rates[] = {
1472 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1473 { .div = 0 }
1474};
1475
1476static const struct clksel omap24xx_gpt_clksel[] = {
1477 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1478 { .parent = &sys_ck, .rates = gpt_sys_rates },
1479 { .parent = &alt_ck, .rates = gpt_alt_rates },
1480 { .parent = NULL },
1481};
1482
1483static struct clk gpt1_ick = {
1484 .name = "gpt1_ick",
1485 .parent = &l4_ck,
1486 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1487 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1488 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1489 .recalc = &followparent_recalc,
1490};
1491
1492static struct clk gpt1_fck = {
1493 .name = "gpt1_fck",
1494 .parent = &func_32k_ck,
1495 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1496 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1497 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1498 .init = &omap2_init_clksel_parent,
1499 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1500 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1501 .clksel = omap24xx_gpt_clksel,
1502 .recalc = &omap2_clksel_recalc,
1503 .round_rate = &omap2_clksel_round_rate,
1504 .set_rate = &omap2_clksel_set_rate
1505};
1506
1507static struct clk gpt2_ick = {
1508 .name = "gpt2_ick",
1509 .parent = &l4_ck,
1510 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1512 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1513 .recalc = &followparent_recalc,
1514};
1515
1516static struct clk gpt2_fck = {
1517 .name = "gpt2_fck",
1518 .parent = &func_32k_ck,
1519 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1521 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1522 .init = &omap2_init_clksel_parent,
1523 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1524 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1525 .clksel = omap24xx_gpt_clksel,
1526 .recalc = &omap2_clksel_recalc,
1527};
1528
1529static struct clk gpt3_ick = {
1530 .name = "gpt3_ick",
1531 .parent = &l4_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1534 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1535 .recalc = &followparent_recalc,
1536};
1537
1538static struct clk gpt3_fck = {
1539 .name = "gpt3_fck",
1540 .parent = &func_32k_ck,
1541 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1544 .init = &omap2_init_clksel_parent,
1545 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1546 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1547 .clksel = omap24xx_gpt_clksel,
1548 .recalc = &omap2_clksel_recalc,
1549};
1550
1551static struct clk gpt4_ick = {
1552 .name = "gpt4_ick",
1553 .parent = &l4_ck,
1554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1556 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1557 .recalc = &followparent_recalc,
1558};
1559
1560static struct clk gpt4_fck = {
1561 .name = "gpt4_fck",
1562 .parent = &func_32k_ck,
1563 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1566 .init = &omap2_init_clksel_parent,
1567 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1568 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1569 .clksel = omap24xx_gpt_clksel,
1570 .recalc = &omap2_clksel_recalc,
1571};
1572
1573static struct clk gpt5_ick = {
1574 .name = "gpt5_ick",
1575 .parent = &l4_ck,
1576 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1578 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1579 .recalc = &followparent_recalc,
1580};
1581
1582static struct clk gpt5_fck = {
1583 .name = "gpt5_fck",
1584 .parent = &func_32k_ck,
1585 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1587 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1588 .init = &omap2_init_clksel_parent,
1589 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1590 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1591 .clksel = omap24xx_gpt_clksel,
1592 .recalc = &omap2_clksel_recalc,
1593};
1594
1595static struct clk gpt6_ick = {
1596 .name = "gpt6_ick",
1597 .parent = &l4_ck,
1598 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1600 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1601 .recalc = &followparent_recalc,
1602};
1603
1604static struct clk gpt6_fck = {
1605 .name = "gpt6_fck",
1606 .parent = &func_32k_ck,
1607 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1610 .init = &omap2_init_clksel_parent,
1611 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1612 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1613 .clksel = omap24xx_gpt_clksel,
1614 .recalc = &omap2_clksel_recalc,
1615};
1616
1617static struct clk gpt7_ick = {
1618 .name = "gpt7_ick",
1619 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1622 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1623 .recalc = &followparent_recalc,
1624};
1625
1626static struct clk gpt7_fck = {
1627 .name = "gpt7_fck",
1628 .parent = &func_32k_ck,
1629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1631 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1632 .init = &omap2_init_clksel_parent,
1633 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1634 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1635 .clksel = omap24xx_gpt_clksel,
1636 .recalc = &omap2_clksel_recalc,
1637};
1638
1639static struct clk gpt8_ick = {
1640 .name = "gpt8_ick",
1641 .parent = &l4_ck,
1642 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1644 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1645 .recalc = &followparent_recalc,
1646};
1647
1648static struct clk gpt8_fck = {
1649 .name = "gpt8_fck",
1650 .parent = &func_32k_ck,
1651 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1654 .init = &omap2_init_clksel_parent,
1655 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1656 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1657 .clksel = omap24xx_gpt_clksel,
1658 .recalc = &omap2_clksel_recalc,
1659};
1660
1661static struct clk gpt9_ick = {
1662 .name = "gpt9_ick",
1663 .parent = &l4_ck,
1664 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1667 .recalc = &followparent_recalc,
1668};
1669
1670static struct clk gpt9_fck = {
1671 .name = "gpt9_fck",
1672 .parent = &func_32k_ck,
1673 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1674 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1676 .init = &omap2_init_clksel_parent,
1677 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1678 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1679 .clksel = omap24xx_gpt_clksel,
1680 .recalc = &omap2_clksel_recalc,
1681};
1682
1683static struct clk gpt10_ick = {
1684 .name = "gpt10_ick",
1685 .parent = &l4_ck,
1686 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1688 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1689 .recalc = &followparent_recalc,
1690};
1691
1692static struct clk gpt10_fck = {
1693 .name = "gpt10_fck",
1694 .parent = &func_32k_ck,
1695 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1697 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1698 .init = &omap2_init_clksel_parent,
1699 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1700 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1701 .clksel = omap24xx_gpt_clksel,
1702 .recalc = &omap2_clksel_recalc,
1703};
1704
1705static struct clk gpt11_ick = {
1706 .name = "gpt11_ick",
1707 .parent = &l4_ck,
1708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1711 .recalc = &followparent_recalc,
1712};
1713
1714static struct clk gpt11_fck = {
1715 .name = "gpt11_fck",
1716 .parent = &func_32k_ck,
1717 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1719 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1720 .init = &omap2_init_clksel_parent,
1721 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1722 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1723 .clksel = omap24xx_gpt_clksel,
1724 .recalc = &omap2_clksel_recalc,
1725};
1726
1727static struct clk gpt12_ick = {
1728 .name = "gpt12_ick",
1729 .parent = &l4_ck,
1730 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1733 .recalc = &followparent_recalc,
1734};
1735
1736static struct clk gpt12_fck = {
1737 .name = "gpt12_fck",
1738 .parent = &func_32k_ck,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1741 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1742 .init = &omap2_init_clksel_parent,
1743 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1744 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1745 .clksel = omap24xx_gpt_clksel,
1746 .recalc = &omap2_clksel_recalc,
1747};
1748
1749static struct clk mcbsp1_ick = {
1750 .name = "mcbsp1_ick",
1751 .parent = &l4_ck,
1752 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1754 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1755 .recalc = &followparent_recalc,
1756};
1757
1758static struct clk mcbsp1_fck = {
1759 .name = "mcbsp1_fck",
1760 .parent = &func_96m_ck,
1761 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1763 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1764 .recalc = &followparent_recalc,
1765};
1766
1767static struct clk mcbsp2_ick = {
1768 .name = "mcbsp2_ick",
1769 .parent = &l4_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1772 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1773 .recalc = &followparent_recalc,
1774};
1775
1776static struct clk mcbsp2_fck = {
1777 .name = "mcbsp2_fck",
1778 .parent = &func_96m_ck,
1779 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1781 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1782 .recalc = &followparent_recalc,
1783};
1784
1785static struct clk mcbsp3_ick = {
1786 .name = "mcbsp3_ick",
1787 .parent = &l4_ck,
1788 .flags = CLOCK_IN_OMAP243X,
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1790 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1791 .recalc = &followparent_recalc,
1792};
1793
1794static struct clk mcbsp3_fck = {
1795 .name = "mcbsp3_fck",
1796 .parent = &func_96m_ck,
1797 .flags = CLOCK_IN_OMAP243X,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1799 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1800 .recalc = &followparent_recalc,
1801};
1802
1803static struct clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick",
1805 .parent = &l4_ck,
1806 .flags = CLOCK_IN_OMAP243X,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1808 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1809 .recalc = &followparent_recalc,
1810};
1811
1812static struct clk mcbsp4_fck = {
1813 .name = "mcbsp4_fck",
1814 .parent = &func_96m_ck,
1815 .flags = CLOCK_IN_OMAP243X,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1817 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1818 .recalc = &followparent_recalc,
1819};
1820
1821static struct clk mcbsp5_ick = {
1822 .name = "mcbsp5_ick",
1823 .parent = &l4_ck,
1824 .flags = CLOCK_IN_OMAP243X,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1826 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1827 .recalc = &followparent_recalc,
1828};
1829
1830static struct clk mcbsp5_fck = {
1831 .name = "mcbsp5_fck",
1832 .parent = &func_96m_ck,
1833 .flags = CLOCK_IN_OMAP243X,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1835 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1836 .recalc = &followparent_recalc,
1837};
1838
1839static struct clk mcspi1_ick = {
1840 .name = "mcspi_ick",
1841 .id = 1,
1842 .parent = &l4_ck,
1843 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1844 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1845 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1846 .recalc = &followparent_recalc,
1847};
1848
1849static struct clk mcspi1_fck = {
1850 .name = "mcspi_fck",
1851 .id = 1,
1852 .parent = &func_48m_ck,
1853 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1855 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1856 .recalc = &followparent_recalc,
1857};
1858
1859static struct clk mcspi2_ick = {
1860 .name = "mcspi_ick",
1861 .id = 2,
1862 .parent = &l4_ck,
1863 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1866 .recalc = &followparent_recalc,
1867};
1868
1869static struct clk mcspi2_fck = {
1870 .name = "mcspi_fck",
1871 .id = 2,
1872 .parent = &func_48m_ck,
1873 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1875 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1876 .recalc = &followparent_recalc,
1877};
1878
1879static struct clk mcspi3_ick = {
1880 .name = "mcspi_ick",
1881 .id = 3,
1882 .parent = &l4_ck,
1883 .flags = CLOCK_IN_OMAP243X,
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1885 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1886 .recalc = &followparent_recalc,
1887};
1888
1889static struct clk mcspi3_fck = {
1890 .name = "mcspi_fck",
1891 .id = 3,
1892 .parent = &func_48m_ck,
1893 .flags = CLOCK_IN_OMAP243X,
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1895 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1896 .recalc = &followparent_recalc,
1897};
1898
1899static struct clk uart1_ick = {
1900 .name = "uart1_ick",
1901 .parent = &l4_ck,
1902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1903 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1904 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1905 .recalc = &followparent_recalc,
1906};
1907
1908static struct clk uart1_fck = {
1909 .name = "uart1_fck",
1910 .parent = &func_48m_ck,
1911 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1913 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk uart2_ick = {
1918 .name = "uart2_ick",
1919 .parent = &l4_ck,
1920 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1923 .recalc = &followparent_recalc,
1924};
1925
1926static struct clk uart2_fck = {
1927 .name = "uart2_fck",
1928 .parent = &func_48m_ck,
1929 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1930 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1931 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1932 .recalc = &followparent_recalc,
1933};
1934
1935static struct clk uart3_ick = {
1936 .name = "uart3_ick",
1937 .parent = &l4_ck,
1938 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1940 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1941 .recalc = &followparent_recalc,
1942};
1943
1944static struct clk uart3_fck = {
1945 .name = "uart3_fck",
1946 .parent = &func_48m_ck,
1947 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1949 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1950 .recalc = &followparent_recalc,
1951};
1952
1953static struct clk gpios_ick = {
1954 .name = "gpios_ick",
1955 .parent = &l4_ck,
1956 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1957 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1958 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1959 .recalc = &followparent_recalc,
1960};
1961
1962static struct clk gpios_fck = {
1963 .name = "gpios_fck",
1964 .parent = &func_32k_ck,
1965 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1966 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1967 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1968 .recalc = &followparent_recalc,
1969};
1970
1971static struct clk mpu_wdt_ick = {
1972 .name = "mpu_wdt_ick",
1973 .parent = &l4_ck,
1974 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1975 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1976 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1977 .recalc = &followparent_recalc,
1978};
1979
1980static struct clk mpu_wdt_fck = {
1981 .name = "mpu_wdt_fck",
1982 .parent = &func_32k_ck,
1983 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1984 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1985 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1986 .recalc = &followparent_recalc,
1987};
1988
1989static struct clk sync_32k_ick = {
1990 .name = "sync_32k_ick",
1991 .parent = &l4_ck,
1992 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1993 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1994 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1995 .recalc = &followparent_recalc,
1996};
1997static struct clk wdt1_ick = {
1998 .name = "wdt1_ick",
1999 .parent = &l4_ck,
2000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2001 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2002 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2003 .recalc = &followparent_recalc,
2004};
2005static struct clk omapctrl_ick = {
2006 .name = "omapctrl_ick",
2007 .parent = &l4_ck,
2008 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2009 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2010 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2011 .recalc = &followparent_recalc,
2012};
2013static struct clk icr_ick = {
2014 .name = "icr_ick",
2015 .parent = &l4_ck,
2016 .flags = CLOCK_IN_OMAP243X,
2017 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2018 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2019 .recalc = &followparent_recalc,
2020};
2021
2022static struct clk cam_ick = {
2023 .name = "cam_ick",
2024 .parent = &l4_ck,
2025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2028 .recalc = &followparent_recalc,
2029};
2030
2031static struct clk cam_fck = {
2032 .name = "cam_fck",
2033 .parent = &func_96m_ck,
2034 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2036 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2037 .recalc = &followparent_recalc,
2038};
2039
2040static struct clk mailboxes_ick = {
2041 .name = "mailboxes_ick",
2042 .parent = &l4_ck,
2043 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2044 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2045 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2046 .recalc = &followparent_recalc,
2047};
2048
2049static struct clk wdt4_ick = {
2050 .name = "wdt4_ick",
2051 .parent = &l4_ck,
2052 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2053 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2054 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2055 .recalc = &followparent_recalc,
2056};
2057
2058static struct clk wdt4_fck = {
2059 .name = "wdt4_fck",
2060 .parent = &func_32k_ck,
2061 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2063 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2064 .recalc = &followparent_recalc,
2065};
2066
2067static struct clk wdt3_ick = {
2068 .name = "wdt3_ick",
2069 .parent = &l4_ck,
2070 .flags = CLOCK_IN_OMAP242X,
2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2072 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2073 .recalc = &followparent_recalc,
2074};
2075
2076static struct clk wdt3_fck = {
2077 .name = "wdt3_fck",
2078 .parent = &func_32k_ck,
2079 .flags = CLOCK_IN_OMAP242X,
2080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2081 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2082 .recalc = &followparent_recalc,
2083};
2084
2085static struct clk mspro_ick = {
2086 .name = "mspro_ick",
2087 .parent = &l4_ck,
2088 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2089 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2091 .recalc = &followparent_recalc,
2092};
2093
2094static struct clk mspro_fck = {
2095 .name = "mspro_fck",
2096 .parent = &func_96m_ck,
2097 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2098 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2099 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2100 .recalc = &followparent_recalc,
2101};
2102
2103static struct clk mmc_ick = {
2104 .name = "mmc_ick",
2105 .parent = &l4_ck,
2106 .flags = CLOCK_IN_OMAP242X,
2107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2108 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2109 .recalc = &followparent_recalc,
2110};
2111
2112static struct clk mmc_fck = {
2113 .name = "mmc_fck",
2114 .parent = &func_96m_ck,
2115 .flags = CLOCK_IN_OMAP242X,
2116 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2117 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2118 .recalc = &followparent_recalc,
2119};
2120
2121static struct clk fac_ick = {
2122 .name = "fac_ick",
2123 .parent = &l4_ck,
2124 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2125 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2126 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk fac_fck = {
2131 .name = "fac_fck",
2132 .parent = &func_12m_ck,
2133 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2134 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2135 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2136 .recalc = &followparent_recalc,
2137};
2138
2139static struct clk eac_ick = {
2140 .name = "eac_ick",
2141 .parent = &l4_ck,
2142 .flags = CLOCK_IN_OMAP242X,
2143 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2144 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2145 .recalc = &followparent_recalc,
2146};
2147
2148static struct clk eac_fck = {
2149 .name = "eac_fck",
2150 .parent = &func_96m_ck,
2151 .flags = CLOCK_IN_OMAP242X,
2152 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2153 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2154 .recalc = &followparent_recalc,
2155};
2156
2157static struct clk hdq_ick = {
2158 .name = "hdq_ick",
2159 .parent = &l4_ck,
2160 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2162 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2163 .recalc = &followparent_recalc,
2164};
2165
2166static struct clk hdq_fck = {
2167 .name = "hdq_fck",
2168 .parent = &func_12m_ck,
2169 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2170 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2171 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2172 .recalc = &followparent_recalc,
2173};
2174
2175static struct clk i2c2_ick = {
2176 .name = "i2c_ick",
2177 .id = 2,
2178 .parent = &l4_ck,
2179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2180 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2181 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2182 .recalc = &followparent_recalc,
2183};
2184
2185static struct clk i2c2_fck = {
2186 .name = "i2c_fck",
2187 .id = 2,
2188 .parent = &func_12m_ck,
2189 .flags = CLOCK_IN_OMAP242X,
2190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2191 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2192 .recalc = &followparent_recalc,
2193};
2194
2195static struct clk i2chs2_fck = {
2196 .name = "i2chs_fck",
2197 .id = 2,
2198 .parent = &func_96m_ck,
2199 .flags = CLOCK_IN_OMAP243X,
2200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2201 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2202 .recalc = &followparent_recalc,
2203};
2204
2205static struct clk i2c1_ick = {
2206 .name = "i2c_ick",
2207 .id = 1,
2208 .parent = &l4_ck,
2209 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2211 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2212 .recalc = &followparent_recalc,
2213};
2214
2215static struct clk i2c1_fck = {
2216 .name = "i2c_fck",
2217 .id = 1,
2218 .parent = &func_12m_ck,
2219 .flags = CLOCK_IN_OMAP242X,
2220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2221 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2222 .recalc = &followparent_recalc,
2223};
2224
2225static struct clk i2chs1_fck = {
2226 .name = "i2chs_fck",
2227 .id = 1,
2228 .parent = &func_96m_ck,
2229 .flags = CLOCK_IN_OMAP243X,
2230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2231 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2232 .recalc = &followparent_recalc,
2233};
2234
2235static struct clk gpmc_fck = {
2236 .name = "gpmc_fck",
2237 .parent = &core_l3_ck,
2238 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2239 .recalc = &followparent_recalc,
2240};
2241
2242static struct clk sdma_fck = {
2243 .name = "sdma_fck",
2244 .parent = &core_l3_ck,
2245 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2246 .recalc = &followparent_recalc,
2247};
2248
2249static struct clk sdma_ick = {
2250 .name = "sdma_ick",
2251 .parent = &l4_ck,
2252 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2253 .recalc = &followparent_recalc,
2254};
2255
2256static struct clk vlynq_ick = {
2257 .name = "vlynq_ick",
2258 .parent = &core_l3_ck,
2259 .flags = CLOCK_IN_OMAP242X,
2260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2261 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2262 .recalc = &followparent_recalc,
2263};
2264
2265static const struct clksel_rate vlynq_fck_96m_rates[] = {
2266 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2267 { .div = 0 }
2268};
2269
2270static const struct clksel_rate vlynq_fck_core_rates[] = {
2271 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2272 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2273 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2274 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2275 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2276 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2277 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2278 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2279 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2280 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2281 { .div = 0 }
2282};
2283
2284static const struct clksel vlynq_fck_clksel[] = {
2285 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2286 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2287 { .parent = NULL }
2288};
2289
2290static struct clk vlynq_fck = {
2291 .name = "vlynq_fck",
2292 .parent = &func_96m_ck,
2293 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2294 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2295 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2296 .init = &omap2_init_clksel_parent,
2297 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2298 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2299 .clksel = vlynq_fck_clksel,
2300 .recalc = &omap2_clksel_recalc,
2301 .round_rate = &omap2_clksel_round_rate,
2302 .set_rate = &omap2_clksel_set_rate
2303};
2304
2305static struct clk sdrc_ick = {
2306 .name = "sdrc_ick",
2307 .parent = &l4_ck,
2308 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2310 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2311 .recalc = &followparent_recalc,
2312};
2313
2314static struct clk des_ick = {
2315 .name = "des_ick",
2316 .parent = &l4_ck,
2317 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2319 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2320 .recalc = &followparent_recalc,
2321};
2322
2323static struct clk sha_ick = {
2324 .name = "sha_ick",
2325 .parent = &l4_ck,
2326 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2328 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2329 .recalc = &followparent_recalc,
2330};
2331
2332static struct clk rng_ick = {
2333 .name = "rng_ick",
2334 .parent = &l4_ck,
2335 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2337 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2338 .recalc = &followparent_recalc,
2339};
2340
2341static struct clk aes_ick = {
2342 .name = "aes_ick",
2343 .parent = &l4_ck,
2344 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2345 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2346 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2347 .recalc = &followparent_recalc,
2348};
2349
2350static struct clk pka_ick = {
2351 .name = "pka_ick",
2352 .parent = &l4_ck,
2353 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2354 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2355 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2356 .recalc = &followparent_recalc,
2357};
2358
2359static struct clk usb_fck = {
2360 .name = "usb_fck",
2361 .parent = &func_48m_ck,
2362 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2363 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2364 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2365 .recalc = &followparent_recalc,
2366};
2367
2368static struct clk usbhs_ick = {
2369 .name = "usbhs_ick",
2370 .parent = &core_l3_ck,
2371 .flags = CLOCK_IN_OMAP243X,
2372 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2373 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2374 .recalc = &followparent_recalc,
2375};
2376
2377static struct clk mmchs1_ick = {
2378 .name = "mmchs_ick",
2379 .id = 1,
2380 .parent = &l4_ck,
2381 .flags = CLOCK_IN_OMAP243X,
2382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2383 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2384 .recalc = &followparent_recalc,
2385};
2386
2387static struct clk mmchs1_fck = {
2388 .name = "mmchs_fck",
2389 .id = 1,
2390 .parent = &func_96m_ck,
2391 .flags = CLOCK_IN_OMAP243X,
2392 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2393 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2394 .recalc = &followparent_recalc,
2395};
2396
2397static struct clk mmchs2_ick = {
2398 .name = "mmchs_ick",
2399 .id = 2,
2400 .parent = &l4_ck,
2401 .flags = CLOCK_IN_OMAP243X,
2402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2403 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2404 .recalc = &followparent_recalc,
2405};
2406
2407static struct clk mmchs2_fck = {
2408 .name = "mmchs_fck",
2409 .id = 2,
2410 .parent = &func_96m_ck,
2411 .flags = CLOCK_IN_OMAP243X,
2412 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2413 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2414 .recalc = &followparent_recalc,
2415};
2416
2417static struct clk gpio5_ick = {
2418 .name = "gpio5_ick",
2419 .parent = &l4_ck,
2420 .flags = CLOCK_IN_OMAP243X,
2421 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2422 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2423 .recalc = &followparent_recalc,
2424};
2425
2426static struct clk gpio5_fck = {
2427 .name = "gpio5_fck",
2428 .parent = &func_32k_ck,
2429 .flags = CLOCK_IN_OMAP243X,
2430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2431 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2432 .recalc = &followparent_recalc,
2433};
2434
2435static struct clk mdm_intc_ick = {
2436 .name = "mdm_intc_ick",
2437 .parent = &l4_ck,
2438 .flags = CLOCK_IN_OMAP243X,
2439 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2440 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2441 .recalc = &followparent_recalc,
2442};
2443
2444static struct clk mmchsdb1_fck = {
2445 .name = "mmchsdb_fck",
2446 .id = 1,
2447 .parent = &func_32k_ck,
2448 .flags = CLOCK_IN_OMAP243X,
2449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2450 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2451 .recalc = &followparent_recalc,
2452};
2453
2454static struct clk mmchsdb2_fck = {
2455 .name = "mmchsdb_fck",
2456 .id = 2,
2457 .parent = &func_32k_ck,
2458 .flags = CLOCK_IN_OMAP243X,
2459 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2460 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2461 .recalc = &followparent_recalc,
2462};
2463
2464/*
2465 * This clock is a composite clock which does entire set changes then
2466 * forces a rebalance. It keys on the MPU speed, but it really could
2467 * be any key speed part of a set in the rate table.
2468 *
2469 * to really change a set, you need memory table sets which get changed
2470 * in sram, pre-notifiers & post notifiers, changing the top set, without
2471 * having low level display recalc's won't work... this is why dpm notifiers
2472 * work, isr's off, walk a list of clocks already _off_ and not messing with
2473 * the bus.
2474 *
2475 * This clock should have no parent. It embodies the entire upper level
2476 * active set. A parent will mess up some of the init also.
2477 */
2478static struct clk virt_prcm_set = {
2479 .name = "virt_prcm_set",
2480 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2481 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2482 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2483 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2484 .set_rate = &omap2_select_table_rate,
2485 .round_rate = &omap2_round_to_table_rate,
2486};
2487
2488static struct clk *onchip_24xx_clks[] __initdata = {
2489 /* external root sources */
2490 &func_32k_ck,
2491 &osc_ck,
2492 &sys_ck,
2493 &alt_ck,
2494 /* internal analog sources */
2495 &dpll_ck,
2496 &apll96_ck,
2497 &apll54_ck,
2498 /* internal prcm root sources */
2499 &func_54m_ck,
2500 &core_ck,
2501 &func_96m_ck,
2502 &func_48m_ck,
2503 &func_12m_ck,
2504 &wdt1_osc_ck,
2505 &sys_clkout_src,
2506 &sys_clkout,
2507 &sys_clkout2_src,
2508 &sys_clkout2,
2509 &emul_ck,
2510 /* mpu domain clocks */
2511 &mpu_ck,
2512 /* dsp domain clocks */
2513 &dsp_fck,
2514 &dsp_irate_ick,
2515 &dsp_ick, /* 242x */
2516 &iva2_1_ick, /* 243x */
2517 &iva1_ifck, /* 242x */
2518 &iva1_mpu_int_ifck, /* 242x */
2519 /* GFX domain clocks */
2520 &gfx_3d_fck,
2521 &gfx_2d_fck,
2522 &gfx_ick,
2523 /* Modem domain clocks */
2524 &mdm_ick,
2525 &mdm_osc_ck,
2526 /* DSS domain clocks */
2527 &dss_ick,
2528 &dss1_fck,
2529 &dss2_fck,
2530 &dss_54m_fck,
2531 /* L3 domain clocks */
2532 &core_l3_ck,
2533 &ssi_ssr_sst_fck,
2534 &usb_l4_ick,
2535 /* L4 domain clocks */
2536 &l4_ck, /* used as both core_l4 and wu_l4 */
2537 &ssi_l4_ick,
2538 /* virtual meta-group clock */
2539 &virt_prcm_set,
2540 /* general l4 interface ck, multi-parent functional clk */
2541 &gpt1_ick,
2542 &gpt1_fck,
2543 &gpt2_ick,
2544 &gpt2_fck,
2545 &gpt3_ick,
2546 &gpt3_fck,
2547 &gpt4_ick,
2548 &gpt4_fck,
2549 &gpt5_ick,
2550 &gpt5_fck,
2551 &gpt6_ick,
2552 &gpt6_fck,
2553 &gpt7_ick,
2554 &gpt7_fck,
2555 &gpt8_ick,
2556 &gpt8_fck,
2557 &gpt9_ick,
2558 &gpt9_fck,
2559 &gpt10_ick,
2560 &gpt10_fck,
2561 &gpt11_ick,
2562 &gpt11_fck,
2563 &gpt12_ick,
2564 &gpt12_fck,
2565 &mcbsp1_ick,
2566 &mcbsp1_fck,
2567 &mcbsp2_ick,
2568 &mcbsp2_fck,
2569 &mcbsp3_ick,
2570 &mcbsp3_fck,
2571 &mcbsp4_ick,
2572 &mcbsp4_fck,
2573 &mcbsp5_ick,
2574 &mcbsp5_fck,
2575 &mcspi1_ick,
2576 &mcspi1_fck,
2577 &mcspi2_ick,
2578 &mcspi2_fck,
2579 &mcspi3_ick,
2580 &mcspi3_fck,
2581 &uart1_ick,
2582 &uart1_fck,
2583 &uart2_ick,
2584 &uart2_fck,
2585 &uart3_ick,
2586 &uart3_fck,
2587 &gpios_ick,
2588 &gpios_fck,
2589 &mpu_wdt_ick,
2590 &mpu_wdt_fck,
2591 &sync_32k_ick,
2592 &wdt1_ick,
2593 &omapctrl_ick,
2594 &icr_ick,
2595 &cam_fck,
2596 &cam_ick,
2597 &mailboxes_ick,
2598 &wdt4_ick,
2599 &wdt4_fck,
2600 &wdt3_ick,
2601 &wdt3_fck,
2602 &mspro_ick,
2603 &mspro_fck,
2604 &mmc_ick,
2605 &mmc_fck,
2606 &fac_ick,
2607 &fac_fck,
2608 &eac_ick,
2609 &eac_fck,
2610 &hdq_ick,
2611 &hdq_fck,
2612 &i2c1_ick,
2613 &i2c1_fck,
2614 &i2chs1_fck,
2615 &i2c2_ick,
2616 &i2c2_fck,
2617 &i2chs2_fck,
2618 &gpmc_fck,
2619 &sdma_fck,
2620 &sdma_ick,
2621 &vlynq_ick,
2622 &vlynq_fck,
2623 &sdrc_ick,
2624 &des_ick,
2625 &sha_ick,
2626 &rng_ick,
2627 &aes_ick,
2628 &pka_ick,
2629 &usb_fck,
2630 &usbhs_ick,
2631 &mmchs1_ick,
2632 &mmchs1_fck,
2633 &mmchs2_ick,
2634 &mmchs2_fck,
2635 &gpio5_ick,
2636 &gpio5_fck,
2637 &mdm_intc_ick,
2638 &mmchsdb1_fck,
2639 &mmchsdb2_fck,
2640};
2641
2642#endif
2643
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
new file mode 100644
index 00000000000..b42bdd6079a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -0,0 +1,235 @@
1/*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * Parts of this code are based on code written by
10 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#undef DEBUG
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#include <asm/arch/clock.h>
28#include <asm/arch/sram.h>
29#include <asm/div64.h>
30#include <asm/bitops.h>
31
32#include "memory.h"
33#include "clock.h"
34#include "clock34xx.h"
35#include "prm.h"
36#include "prm-regbits-34xx.h"
37#include "cm.h"
38#include "cm-regbits-34xx.h"
39
40/* CM_CLKEN_PLL*.EN* bit values */
41#define DPLL_LOCKED 0x7
42
43/**
44 * omap3_dpll_recalc - recalculate DPLL rate
45 * @clk: DPLL struct clk
46 *
47 * Recalculate and propagate the DPLL rate.
48 */
49static void omap3_dpll_recalc(struct clk *clk)
50{
51 clk->rate = omap2_get_dpll_rate(clk);
52
53 propagate_rate(clk);
54}
55
56/**
57 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
58 * @clk: DPLL output struct clk
59 *
60 * Using parent clock DPLL data, look up DPLL state. If locked, set our
61 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
62 */
63static void omap3_clkoutx2_recalc(struct clk *clk)
64{
65 const struct dpll_data *dd;
66 u32 v;
67 struct clk *pclk;
68
69 /* Walk up the parents of clk, looking for a DPLL */
70 pclk = clk->parent;
71 while (pclk && !pclk->dpll_data)
72 pclk = pclk->parent;
73
74 /* clk does not have a DPLL as a parent? */
75 WARN_ON(!pclk);
76
77 dd = pclk->dpll_data;
78
79 WARN_ON(!dd->control_reg || !dd->enable_mask);
80
81 v = __raw_readl(dd->control_reg) & dd->enable_mask;
82 v >>= __ffs(dd->enable_mask);
83 if (v != DPLL_LOCKED)
84 clk->rate = clk->parent->rate;
85 else
86 clk->rate = clk->parent->rate * 2;
87
88 if (clk->flags & RATE_PROPAGATES)
89 propagate_rate(clk);
90}
91
92/*
93 * As it is structured now, this will prevent an OMAP2/3 multiboot
94 * kernel from compiling. This will need further attention.
95 */
96#if defined(CONFIG_ARCH_OMAP3)
97
98static struct clk_functions omap2_clk_functions = {
99 .clk_enable = omap2_clk_enable,
100 .clk_disable = omap2_clk_disable,
101 .clk_round_rate = omap2_clk_round_rate,
102 .clk_set_rate = omap2_clk_set_rate,
103 .clk_set_parent = omap2_clk_set_parent,
104 .clk_disable_unused = omap2_clk_disable_unused,
105};
106
107/*
108 * Set clocks for bypass mode for reboot to work.
109 */
110void omap2_clk_prepare_for_reboot(void)
111{
112 /* REVISIT: Not ready for 343x */
113#if 0
114 u32 rate;
115
116 if (vclk == NULL || sclk == NULL)
117 return;
118
119 rate = clk_get_rate(sclk);
120 clk_set_rate(vclk, rate);
121#endif
122}
123
124/* REVISIT: Move this init stuff out into clock.c */
125
126/*
127 * Switch the MPU rate if specified on cmdline.
128 * We cannot do this early until cmdline is parsed.
129 */
130static int __init omap2_clk_arch_init(void)
131{
132 if (!mpurate)
133 return -EINVAL;
134
135 /* REVISIT: not yet ready for 343x */
136#if 0
137 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
138 printk(KERN_ERR "Could not find matching MPU rate\n");
139#endif
140
141 recalculate_root_clocks();
142
143 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
144 "%ld.%01ld/%ld/%ld MHz\n",
145 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
146 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
147
148 return 0;
149}
150arch_initcall(omap2_clk_arch_init);
151
152int __init omap2_clk_init(void)
153{
154 /* struct prcm_config *prcm; */
155 struct clk **clkp;
156 /* u32 clkrate; */
157 u32 cpu_clkflg;
158
159 /* REVISIT: Ultimately this will be used for multiboot */
160#if 0
161 if (cpu_is_omap242x()) {
162 cpu_mask = RATE_IN_242X;
163 cpu_clkflg = CLOCK_IN_OMAP242X;
164 clkp = onchip_24xx_clks;
165 } else if (cpu_is_omap2430()) {
166 cpu_mask = RATE_IN_243X;
167 cpu_clkflg = CLOCK_IN_OMAP243X;
168 clkp = onchip_24xx_clks;
169 }
170#endif
171 if (cpu_is_omap34xx()) {
172 cpu_mask = RATE_IN_343X;
173 cpu_clkflg = CLOCK_IN_OMAP343X;
174 clkp = onchip_34xx_clks;
175
176 /*
177 * Update this if there are further clock changes between ES2
178 * and production parts
179 */
180 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
181 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
182 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
183 } else {
184 cpu_mask |= RATE_IN_3430ES2;
185 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
186 }
187 }
188
189 clk_init(&omap2_clk_functions);
190
191 for (clkp = onchip_34xx_clks;
192 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
193 clkp++) {
194 if ((*clkp)->flags & cpu_clkflg)
195 clk_register(*clkp);
196 }
197
198 /* REVISIT: Not yet ready for OMAP3 */
199#if 0
200 /* Check the MPU rate set by bootloader */
201 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
202 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
203 if (!(prcm->flags & cpu_mask))
204 continue;
205 if (prcm->xtal_speed != sys_ck.rate)
206 continue;
207 if (prcm->dpll_speed <= clkrate)
208 break;
209 }
210 curr_prcm_set = prcm;
211#endif
212
213 recalculate_root_clocks();
214
215 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
216 "%ld.%01ld/%ld/%ld MHz\n",
217 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
218 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
219
220 /*
221 * Only enable those clocks we will need, let the drivers
222 * enable other clocks as necessary
223 */
224 clk_enable_init_clocks();
225
226 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
227 /* REVISIT: not yet ready for 343x */
228#if 0
229 vclk = clk_get(NULL, "virt_prcm_set");
230 sclk = clk_get(NULL, "sys_ck");
231#endif
232 return 0;
233}
234
235#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
new file mode 100644
index 00000000000..cf4644a94b9
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -0,0 +1,3009 @@
1/*
2 * OMAP3 clock framework
3 *
4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
8 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
10 *
11 * Written by Paul Walmsley
12 */
13
14#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
15#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
16
17#include <asm/arch/control.h>
18
19#include "clock.h"
20#include "cm.h"
21#include "cm-regbits-34xx.h"
22#include "prm.h"
23#include "prm-regbits-34xx.h"
24
25static void omap3_dpll_recalc(struct clk *clk);
26static void omap3_clkoutx2_recalc(struct clk *clk);
27
28/*
29 * DPLL1 supplies clock to the MPU.
30 * DPLL2 supplies clock to the IVA2.
31 * DPLL3 supplies CORE domain clocks.
32 * DPLL4 supplies peripheral clocks.
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
34 */
35
36/* PRM CLOCKS */
37
38/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
39static struct clk omap_32k_fck = {
40 .name = "omap_32k_fck",
41 .rate = 32768,
42 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
43 ALWAYS_ENABLED,
44 .recalc = &propagate_rate,
45};
46
47static struct clk secure_32k_fck = {
48 .name = "secure_32k_fck",
49 .rate = 32768,
50 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
51 ALWAYS_ENABLED,
52 .recalc = &propagate_rate,
53};
54
55/* Virtual source clocks for osc_sys_ck */
56static struct clk virt_12m_ck = {
57 .name = "virt_12m_ck",
58 .rate = 12000000,
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
60 ALWAYS_ENABLED,
61 .recalc = &propagate_rate,
62};
63
64static struct clk virt_13m_ck = {
65 .name = "virt_13m_ck",
66 .rate = 13000000,
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
68 ALWAYS_ENABLED,
69 .recalc = &propagate_rate,
70};
71
72static struct clk virt_16_8m_ck = {
73 .name = "virt_16_8m_ck",
74 .rate = 16800000,
75 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
76 ALWAYS_ENABLED,
77 .recalc = &propagate_rate,
78};
79
80static struct clk virt_19_2m_ck = {
81 .name = "virt_19_2m_ck",
82 .rate = 19200000,
83 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
84 ALWAYS_ENABLED,
85 .recalc = &propagate_rate,
86};
87
88static struct clk virt_26m_ck = {
89 .name = "virt_26m_ck",
90 .rate = 26000000,
91 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
92 ALWAYS_ENABLED,
93 .recalc = &propagate_rate,
94};
95
96static struct clk virt_38_4m_ck = {
97 .name = "virt_38_4m_ck",
98 .rate = 38400000,
99 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
100 ALWAYS_ENABLED,
101 .recalc = &propagate_rate,
102};
103
104static const struct clksel_rate osc_sys_12m_rates[] = {
105 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
106 { .div = 0 }
107};
108
109static const struct clksel_rate osc_sys_13m_rates[] = {
110 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
111 { .div = 0 }
112};
113
114static const struct clksel_rate osc_sys_16_8m_rates[] = {
115 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
116 { .div = 0 }
117};
118
119static const struct clksel_rate osc_sys_19_2m_rates[] = {
120 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
121 { .div = 0 }
122};
123
124static const struct clksel_rate osc_sys_26m_rates[] = {
125 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
126 { .div = 0 }
127};
128
129static const struct clksel_rate osc_sys_38_4m_rates[] = {
130 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
131 { .div = 0 }
132};
133
134static const struct clksel osc_sys_clksel[] = {
135 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
136 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
137 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
138 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
139 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
140 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
141 { .parent = NULL },
142};
143
144/* Oscillator clock */
145/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
146static struct clk osc_sys_ck = {
147 .name = "osc_sys_ck",
148 .init = &omap2_init_clksel_parent,
149 .clksel_reg = OMAP3430_PRM_CLKSEL,
150 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
151 .clksel = osc_sys_clksel,
152 /* REVISIT: deal with autoextclkmode? */
153 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
154 ALWAYS_ENABLED,
155 .recalc = &omap2_clksel_recalc,
156};
157
158static const struct clksel_rate div2_rates[] = {
159 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
160 { .div = 2, .val = 2, .flags = RATE_IN_343X },
161 { .div = 0 }
162};
163
164static const struct clksel sys_clksel[] = {
165 { .parent = &osc_sys_ck, .rates = div2_rates },
166 { .parent = NULL }
167};
168
169/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
170/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
171static struct clk sys_ck = {
172 .name = "sys_ck",
173 .parent = &osc_sys_ck,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
176 .clksel_mask = OMAP_SYSCLKDIV_MASK,
177 .clksel = sys_clksel,
178 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
179 .recalc = &omap2_clksel_recalc,
180};
181
182static struct clk sys_altclk = {
183 .name = "sys_altclk",
184 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
185 .recalc = &propagate_rate,
186};
187
188/* Optional external clock input for some McBSPs */
189static struct clk mcbsp_clks = {
190 .name = "mcbsp_clks",
191 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
192 .recalc = &propagate_rate,
193};
194
195/* PRM EXTERNAL CLOCK OUTPUT */
196
197static struct clk sys_clkout1 = {
198 .name = "sys_clkout1",
199 .parent = &osc_sys_ck,
200 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
201 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
202 .flags = CLOCK_IN_OMAP343X,
203 .recalc = &followparent_recalc,
204};
205
206/* DPLLS */
207
208/* CM CLOCKS */
209
210static const struct clksel_rate dpll_bypass_rates[] = {
211 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
212 { .div = 0 }
213};
214
215static const struct clksel_rate dpll_locked_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
217 { .div = 0 }
218};
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
240/* DPLL1 */
241/* MPU clock source */
242/* Type: DPLL */
243static const struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
252};
253
254static struct clk dpll1_ck = {
255 .name = "dpll1_ck",
256 .parent = &sys_ck,
257 .dpll_data = &dpll1_dd,
258 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .recalc = &omap3_dpll_recalc,
260};
261
262/*
263 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
264 * DPLL isn't bypassed.
265 */
266static struct clk dpll1_x2_ck = {
267 .name = "dpll1_x2_ck",
268 .parent = &dpll1_ck,
269 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
270 PARENT_CONTROLS_CLOCK,
271 .recalc = &omap3_clkoutx2_recalc,
272};
273
274/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
275static const struct clksel div16_dpll1_x2m2_clksel[] = {
276 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
277 { .parent = NULL }
278};
279
280/*
281 * Does not exist in the TRM - needed to separate the M2 divider from
282 * bypass selection in mpu_ck
283 */
284static struct clk dpll1_x2m2_ck = {
285 .name = "dpll1_x2m2_ck",
286 .parent = &dpll1_x2_ck,
287 .init = &omap2_init_clksel_parent,
288 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
289 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
290 .clksel = div16_dpll1_x2m2_clksel,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
292 PARENT_CONTROLS_CLOCK,
293 .recalc = &omap2_clksel_recalc,
294};
295
296/* DPLL2 */
297/* IVA2 clock source */
298/* Type: DPLL */
299
300static const struct dpll_data dpll2_dd = {
301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
309};
310
311static struct clk dpll2_ck = {
312 .name = "dpll2_ck",
313 .parent = &sys_ck,
314 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
316 .recalc = &omap3_dpll_recalc,
317};
318
319static const struct clksel div16_dpll2_m2x2_clksel[] = {
320 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
321 { .parent = NULL }
322};
323
324/*
325 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
326 * or CLKOUTX2. CLKOUT seems most plausible.
327 */
328static struct clk dpll2_m2_ck = {
329 .name = "dpll2_m2_ck",
330 .parent = &dpll2_ck,
331 .init = &omap2_init_clksel_parent,
332 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
333 OMAP3430_CM_CLKSEL2_PLL),
334 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
335 .clksel = div16_dpll2_m2x2_clksel,
336 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
337 PARENT_CONTROLS_CLOCK,
338 .recalc = &omap2_clksel_recalc,
339};
340
341/* DPLL3 */
342/* Source clock for all interfaces and for some device fclks */
343/* Type: DPLL */
344static const struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
348 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
349 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
353};
354
355static struct clk dpll3_ck = {
356 .name = "dpll3_ck",
357 .parent = &sys_ck,
358 .dpll_data = &dpll3_dd,
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
360 .recalc = &omap3_dpll_recalc,
361};
362
363/*
364 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
365 * DPLL isn't bypassed
366 */
367static struct clk dpll3_x2_ck = {
368 .name = "dpll3_x2_ck",
369 .parent = &dpll3_ck,
370 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
371 PARENT_CONTROLS_CLOCK,
372 .recalc = &omap3_clkoutx2_recalc,
373};
374
375static const struct clksel_rate div31_dpll3_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
377 { .div = 2, .val = 2, .flags = RATE_IN_343X },
378 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
379 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
380 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
381 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
382 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
383 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
384 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
385 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
386 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
387 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
388 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
389 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
390 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
391 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
392 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
393 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
394 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
395 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
396 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
397 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
398 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
399 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
400 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
401 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
402 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
403 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
404 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
405 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
406 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
407 { .div = 0 },
408};
409
410static const struct clksel div31_dpll3m2_clksel[] = {
411 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
412 { .parent = NULL }
413};
414
415/*
416 * DPLL3 output M2
417 * REVISIT: This DPLL output divider must be changed in SRAM, so until
418 * that code is ready, this should remain a 'read-only' clksel clock.
419 */
420static struct clk dpll3_m2_ck = {
421 .name = "dpll3_m2_ck",
422 .parent = &dpll3_ck,
423 .init = &omap2_init_clksel_parent,
424 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
425 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
426 .clksel = div31_dpll3m2_clksel,
427 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
428 PARENT_CONTROLS_CLOCK,
429 .recalc = &omap2_clksel_recalc,
430};
431
432static const struct clksel core_ck_clksel[] = {
433 { .parent = &sys_ck, .rates = dpll_bypass_rates },
434 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
435 { .parent = NULL }
436};
437
438static struct clk core_ck = {
439 .name = "core_ck",
440 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK,
443 .clksel = core_ck_clksel,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK,
446 .recalc = &omap2_clksel_recalc,
447};
448
449static const struct clksel dpll3_m2x2_ck_clksel[] = {
450 { .parent = &sys_ck, .rates = dpll_bypass_rates },
451 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
452 { .parent = NULL }
453};
454
455static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck",
457 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK,
460 .clksel = dpll3_m2x2_ck_clksel,
461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK,
463 .recalc = &omap2_clksel_recalc,
464};
465
466/* The PWRDN bit is apparently only available on 3430ES2 and above */
467static const struct clksel div16_dpll3_clksel[] = {
468 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
469 { .parent = NULL }
470};
471
472/* This virtual clock is the source for dpll3_m3x2_ck */
473static struct clk dpll3_m3_ck = {
474 .name = "dpll3_m3_ck",
475 .parent = &dpll3_ck,
476 .init = &omap2_init_clksel_parent,
477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
478 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
479 .clksel = div16_dpll3_clksel,
480 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
481 PARENT_CONTROLS_CLOCK,
482 .recalc = &omap2_clksel_recalc,
483};
484
485/* The PWRDN bit is apparently only available on 3430ES2 and above */
486static struct clk dpll3_m3x2_ck = {
487 .name = "dpll3_m3x2_ck",
488 .parent = &dpll3_m3_ck,
489 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
490 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
491 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
492 .recalc = &omap3_clkoutx2_recalc,
493};
494
495static const struct clksel emu_core_alwon_ck_clksel[] = {
496 { .parent = &sys_ck, .rates = dpll_bypass_rates },
497 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
498 { .parent = NULL }
499};
500
501static struct clk emu_core_alwon_ck = {
502 .name = "emu_core_alwon_ck",
503 .parent = &dpll3_m3x2_ck,
504 .init = &omap2_init_clksel_parent,
505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK,
507 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc,
511};
512
513/* DPLL4 */
514/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
515/* Type: DPLL */
516static const struct dpll_data dpll4_dd = {
517 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
518 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
525};
526
527static struct clk dpll4_ck = {
528 .name = "dpll4_ck",
529 .parent = &sys_ck,
530 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
532 .recalc = &omap3_dpll_recalc,
533};
534
535/*
536 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
537 * DPLL isn't bypassed --
538 * XXX does this serve any downstream clocks?
539 */
540static struct clk dpll4_x2_ck = {
541 .name = "dpll4_x2_ck",
542 .parent = &dpll4_ck,
543 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
544 PARENT_CONTROLS_CLOCK,
545 .recalc = &omap3_clkoutx2_recalc,
546};
547
548static const struct clksel div16_dpll4_clksel[] = {
549 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
550 { .parent = NULL }
551};
552
553/* This virtual clock is the source for dpll4_m2x2_ck */
554static struct clk dpll4_m2_ck = {
555 .name = "dpll4_m2_ck",
556 .parent = &dpll4_ck,
557 .init = &omap2_init_clksel_parent,
558 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
559 .clksel_mask = OMAP3430_DIV_96M_MASK,
560 .clksel = div16_dpll4_clksel,
561 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
562 PARENT_CONTROLS_CLOCK,
563 .recalc = &omap2_clksel_recalc,
564};
565
566/* The PWRDN bit is apparently only available on 3430ES2 and above */
567static struct clk dpll4_m2x2_ck = {
568 .name = "dpll4_m2x2_ck",
569 .parent = &dpll4_m2_ck,
570 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
572 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
573 .recalc = &omap3_clkoutx2_recalc,
574};
575
576static const struct clksel omap_96m_alwon_fck_clksel[] = {
577 { .parent = &sys_ck, .rates = dpll_bypass_rates },
578 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
579 { .parent = NULL }
580};
581
582static struct clk omap_96m_alwon_fck = {
583 .name = "omap_96m_alwon_fck",
584 .parent = &dpll4_m2x2_ck,
585 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
588 .clksel = omap_96m_alwon_fck_clksel,
589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK,
591 .recalc = &omap2_clksel_recalc,
592};
593
594static struct clk omap_96m_fck = {
595 .name = "omap_96m_fck",
596 .parent = &omap_96m_alwon_fck,
597 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
598 PARENT_CONTROLS_CLOCK,
599 .recalc = &followparent_recalc,
600};
601
602static const struct clksel cm_96m_fck_clksel[] = {
603 { .parent = &sys_ck, .rates = dpll_bypass_rates },
604 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
605 { .parent = NULL }
606};
607
608static struct clk cm_96m_fck = {
609 .name = "cm_96m_fck",
610 .parent = &dpll4_m2x2_ck,
611 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
614 .clksel = cm_96m_fck_clksel,
615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK,
617 .recalc = &omap2_clksel_recalc,
618};
619
620/* This virtual clock is the source for dpll4_m3x2_ck */
621static struct clk dpll4_m3_ck = {
622 .name = "dpll4_m3_ck",
623 .parent = &dpll4_ck,
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
627 .clksel = div16_dpll4_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
631};
632
633/* The PWRDN bit is apparently only available on 3430ES2 and above */
634static struct clk dpll4_m3x2_ck = {
635 .name = "dpll4_m3x2_ck",
636 .parent = &dpll4_m3_ck,
637 .init = &omap2_init_clksel_parent,
638 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
639 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
640 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
641 .recalc = &omap3_clkoutx2_recalc,
642};
643
644static const struct clksel virt_omap_54m_fck_clksel[] = {
645 { .parent = &sys_ck, .rates = dpll_bypass_rates },
646 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
647 { .parent = NULL }
648};
649
650static struct clk virt_omap_54m_fck = {
651 .name = "virt_omap_54m_fck",
652 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
656 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK,
659 .recalc = &omap2_clksel_recalc,
660};
661
662static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
663 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
664 { .div = 0 }
665};
666
667static const struct clksel_rate omap_54m_alt_rates[] = {
668 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
669 { .div = 0 }
670};
671
672static const struct clksel omap_54m_clksel[] = {
673 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
674 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
675 { .parent = NULL }
676};
677
678static struct clk omap_54m_fck = {
679 .name = "omap_54m_fck",
680 .init = &omap2_init_clksel_parent,
681 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
682 .clksel_mask = OMAP3430_SOURCE_54M,
683 .clksel = omap_54m_clksel,
684 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
685 PARENT_CONTROLS_CLOCK,
686 .recalc = &omap2_clksel_recalc,
687};
688
689static const struct clksel_rate omap_48m_96md2_rates[] = {
690 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
691 { .div = 0 }
692};
693
694static const struct clksel_rate omap_48m_alt_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
696 { .div = 0 }
697};
698
699static const struct clksel omap_48m_clksel[] = {
700 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
701 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
702 { .parent = NULL }
703};
704
705static struct clk omap_48m_fck = {
706 .name = "omap_48m_fck",
707 .init = &omap2_init_clksel_parent,
708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
709 .clksel_mask = OMAP3430_SOURCE_48M,
710 .clksel = omap_48m_clksel,
711 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
712 PARENT_CONTROLS_CLOCK,
713 .recalc = &omap2_clksel_recalc,
714};
715
716static struct clk omap_12m_fck = {
717 .name = "omap_12m_fck",
718 .parent = &omap_48m_fck,
719 .fixed_div = 4,
720 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
721 PARENT_CONTROLS_CLOCK,
722 .recalc = &omap2_fixed_divisor_recalc,
723};
724
725/* This virstual clock is the source for dpll4_m4x2_ck */
726static struct clk dpll4_m4_ck = {
727 .name = "dpll4_m4_ck",
728 .parent = &dpll4_ck,
729 .init = &omap2_init_clksel_parent,
730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
731 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
732 .clksel = div16_dpll4_clksel,
733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
734 PARENT_CONTROLS_CLOCK,
735 .recalc = &omap2_clksel_recalc,
736};
737
738/* The PWRDN bit is apparently only available on 3430ES2 and above */
739static struct clk dpll4_m4x2_ck = {
740 .name = "dpll4_m4x2_ck",
741 .parent = &dpll4_m4_ck,
742 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
743 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
745 .recalc = &omap3_clkoutx2_recalc,
746};
747
748/* This virtual clock is the source for dpll4_m5x2_ck */
749static struct clk dpll4_m5_ck = {
750 .name = "dpll4_m5_ck",
751 .parent = &dpll4_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
755 .clksel = div16_dpll4_clksel,
756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
757 PARENT_CONTROLS_CLOCK,
758 .recalc = &omap2_clksel_recalc,
759};
760
761/* The PWRDN bit is apparently only available on 3430ES2 and above */
762static struct clk dpll4_m5x2_ck = {
763 .name = "dpll4_m5x2_ck",
764 .parent = &dpll4_m5_ck,
765 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
766 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
768 .recalc = &omap3_clkoutx2_recalc,
769};
770
771/* This virtual clock is the source for dpll4_m6x2_ck */
772static struct clk dpll4_m6_ck = {
773 .name = "dpll4_m6_ck",
774 .parent = &dpll4_ck,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
778 .clksel = div16_dpll4_clksel,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
781 .recalc = &omap2_clksel_recalc,
782};
783
784/* The PWRDN bit is apparently only available on 3430ES2 and above */
785static struct clk dpll4_m6x2_ck = {
786 .name = "dpll4_m6x2_ck",
787 .parent = &dpll4_m6_ck,
788 .init = &omap2_init_clksel_parent,
789 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
790 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
791 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
792 .recalc = &omap3_clkoutx2_recalc,
793};
794
795static struct clk emu_per_alwon_ck = {
796 .name = "emu_per_alwon_ck",
797 .parent = &dpll4_m6x2_ck,
798 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
799 PARENT_CONTROLS_CLOCK,
800 .recalc = &followparent_recalc,
801};
802
803/* DPLL5 */
804/* Supplies 120MHz clock, USIM source clock */
805/* Type: DPLL */
806/* 3430ES2 only */
807static const struct dpll_data dpll5_dd = {
808 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
809 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
816};
817
818static struct clk dpll5_ck = {
819 .name = "dpll5_ck",
820 .parent = &sys_ck,
821 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
823 ALWAYS_ENABLED,
824 .recalc = &omap3_dpll_recalc,
825};
826
827static const struct clksel div16_dpll5_clksel[] = {
828 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
829 { .parent = NULL }
830};
831
832static struct clk dpll5_m2_ck = {
833 .name = "dpll5_m2_ck",
834 .parent = &dpll5_ck,
835 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
838 .clksel = div16_dpll5_clksel,
839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
840 .recalc = &omap2_clksel_recalc,
841};
842
843static const struct clksel omap_120m_fck_clksel[] = {
844 { .parent = &sys_ck, .rates = dpll_bypass_rates },
845 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
846 { .parent = NULL }
847};
848
849static struct clk omap_120m_fck = {
850 .name = "omap_120m_fck",
851 .parent = &dpll5_m2_ck,
852 .init = &omap2_init_clksel_parent,
853 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
854 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
855 .clksel = omap_120m_fck_clksel,
856 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
857 PARENT_CONTROLS_CLOCK,
858 .recalc = &omap2_clksel_recalc,
859};
860
861/* CM EXTERNAL CLOCK OUTPUTS */
862
863static const struct clksel_rate clkout2_src_core_rates[] = {
864 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
865 { .div = 0 }
866};
867
868static const struct clksel_rate clkout2_src_sys_rates[] = {
869 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
870 { .div = 0 }
871};
872
873static const struct clksel_rate clkout2_src_96m_rates[] = {
874 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
875 { .div = 0 }
876};
877
878static const struct clksel_rate clkout2_src_54m_rates[] = {
879 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
880 { .div = 0 }
881};
882
883static const struct clksel clkout2_src_clksel[] = {
884 { .parent = &core_ck, .rates = clkout2_src_core_rates },
885 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
886 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
887 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
888 { .parent = NULL }
889};
890
891static struct clk clkout2_src_ck = {
892 .name = "clkout2_src_ck",
893 .init = &omap2_init_clksel_parent,
894 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
895 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
896 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
897 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
898 .clksel = clkout2_src_clksel,
899 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
900 .recalc = &omap2_clksel_recalc,
901};
902
903static const struct clksel_rate sys_clkout2_rates[] = {
904 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
905 { .div = 2, .val = 1, .flags = RATE_IN_343X },
906 { .div = 4, .val = 2, .flags = RATE_IN_343X },
907 { .div = 8, .val = 3, .flags = RATE_IN_343X },
908 { .div = 16, .val = 4, .flags = RATE_IN_343X },
909 { .div = 0 },
910};
911
912static const struct clksel sys_clkout2_clksel[] = {
913 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
914 { .parent = NULL },
915};
916
917static struct clk sys_clkout2 = {
918 .name = "sys_clkout2",
919 .init = &omap2_init_clksel_parent,
920 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
921 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
922 .clksel = sys_clkout2_clksel,
923 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
924 .recalc = &omap2_clksel_recalc,
925};
926
927/* CM OUTPUT CLOCKS */
928
929static struct clk corex2_fck = {
930 .name = "corex2_fck",
931 .parent = &dpll3_m2x2_ck,
932 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
933 PARENT_CONTROLS_CLOCK,
934 .recalc = &followparent_recalc,
935};
936
937/* DPLL power domain clock controls */
938
939static const struct clksel div2_core_clksel[] = {
940 { .parent = &core_ck, .rates = div2_rates },
941 { .parent = NULL }
942};
943
944/*
945 * REVISIT: Are these in DPLL power domain or CM power domain? docs
946 * may be inconsistent here?
947 */
948static struct clk dpll1_fck = {
949 .name = "dpll1_fck",
950 .parent = &core_ck,
951 .init = &omap2_init_clksel_parent,
952 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
953 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
954 .clksel = div2_core_clksel,
955 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
956 PARENT_CONTROLS_CLOCK,
957 .recalc = &omap2_clksel_recalc,
958};
959
960/*
961 * MPU clksel:
962 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
963 * derives from the high-frequency bypass clock originating from DPLL3,
964 * called 'dpll1_fck'
965 */
966static const struct clksel mpu_clksel[] = {
967 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
968 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
969 { .parent = NULL }
970};
971
972static struct clk mpu_ck = {
973 .name = "mpu_ck",
974 .parent = &dpll1_x2m2_ck,
975 .init = &omap2_init_clksel_parent,
976 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
977 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
978 .clksel = mpu_clksel,
979 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
980 PARENT_CONTROLS_CLOCK,
981 .recalc = &omap2_clksel_recalc,
982};
983
984/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
985static const struct clksel_rate arm_fck_rates[] = {
986 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
987 { .div = 2, .val = 1, .flags = RATE_IN_343X },
988 { .div = 0 },
989};
990
991static const struct clksel arm_fck_clksel[] = {
992 { .parent = &mpu_ck, .rates = arm_fck_rates },
993 { .parent = NULL }
994};
995
996static struct clk arm_fck = {
997 .name = "arm_fck",
998 .parent = &mpu_ck,
999 .init = &omap2_init_clksel_parent,
1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1001 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1002 .clksel = arm_fck_clksel,
1003 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1004 PARENT_CONTROLS_CLOCK,
1005 .recalc = &omap2_clksel_recalc,
1006};
1007
1008/*
1009 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1010 * although it is referenced - so this is a guess
1011 */
1012static struct clk emu_mpu_alwon_ck = {
1013 .name = "emu_mpu_alwon_ck",
1014 .parent = &mpu_ck,
1015 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1016 PARENT_CONTROLS_CLOCK,
1017 .recalc = &followparent_recalc,
1018};
1019
1020static struct clk dpll2_fck = {
1021 .name = "dpll2_fck",
1022 .parent = &core_ck,
1023 .init = &omap2_init_clksel_parent,
1024 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1025 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1026 .clksel = div2_core_clksel,
1027 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1028 PARENT_CONTROLS_CLOCK,
1029 .recalc = &omap2_clksel_recalc,
1030};
1031
1032/*
1033 * IVA2 clksel:
1034 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1035 * derives from the high-frequency bypass clock originating from DPLL3,
1036 * called 'dpll2_fck'
1037 */
1038
1039static const struct clksel iva2_clksel[] = {
1040 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1041 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1042 { .parent = NULL }
1043};
1044
1045static struct clk iva2_ck = {
1046 .name = "iva2_ck",
1047 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent,
1049 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1050 OMAP3430_CM_IDLEST_PLL),
1051 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1052 .clksel = iva2_clksel,
1053 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1054 PARENT_CONTROLS_CLOCK,
1055 .recalc = &omap2_clksel_recalc,
1056};
1057
1058/* Common interface clocks */
1059
1060static struct clk l3_ick = {
1061 .name = "l3_ick",
1062 .parent = &core_ck,
1063 .init = &omap2_init_clksel_parent,
1064 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1065 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1066 .clksel = div2_core_clksel,
1067 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1068 PARENT_CONTROLS_CLOCK,
1069 .recalc = &omap2_clksel_recalc,
1070};
1071
1072static const struct clksel div2_l3_clksel[] = {
1073 { .parent = &l3_ick, .rates = div2_rates },
1074 { .parent = NULL }
1075};
1076
1077static struct clk l4_ick = {
1078 .name = "l4_ick",
1079 .parent = &l3_ick,
1080 .init = &omap2_init_clksel_parent,
1081 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1082 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1083 .clksel = div2_l3_clksel,
1084 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1085 PARENT_CONTROLS_CLOCK,
1086 .recalc = &omap2_clksel_recalc,
1087
1088};
1089
1090static const struct clksel div2_l4_clksel[] = {
1091 { .parent = &l4_ick, .rates = div2_rates },
1092 { .parent = NULL }
1093};
1094
1095static struct clk rm_ick = {
1096 .name = "rm_ick",
1097 .parent = &l4_ick,
1098 .init = &omap2_init_clksel_parent,
1099 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1100 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1101 .clksel = div2_l4_clksel,
1102 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1103 .recalc = &omap2_clksel_recalc,
1104};
1105
1106/* GFX power domain */
1107
1108/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1109
1110static const struct clksel gfx_l3_clksel[] = {
1111 { .parent = &l3_ick, .rates = gfx_l3_rates },
1112 { .parent = NULL }
1113};
1114
1115static struct clk gfx_l3_fck = {
1116 .name = "gfx_l3_fck",
1117 .parent = &l3_ick,
1118 .init = &omap2_init_clksel_parent,
1119 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1120 .enable_bit = OMAP_EN_GFX_SHIFT,
1121 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1122 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1123 .clksel = gfx_l3_clksel,
1124 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1125 .recalc = &omap2_clksel_recalc,
1126};
1127
1128static struct clk gfx_l3_ick = {
1129 .name = "gfx_l3_ick",
1130 .parent = &l3_ick,
1131 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1132 .enable_bit = OMAP_EN_GFX_SHIFT,
1133 .flags = CLOCK_IN_OMAP3430ES1,
1134 .recalc = &followparent_recalc,
1135};
1136
1137static struct clk gfx_cg1_ck = {
1138 .name = "gfx_cg1_ck",
1139 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1140 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1141 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1142 .flags = CLOCK_IN_OMAP3430ES1,
1143 .recalc = &followparent_recalc,
1144};
1145
1146static struct clk gfx_cg2_ck = {
1147 .name = "gfx_cg2_ck",
1148 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1149 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1150 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1151 .flags = CLOCK_IN_OMAP3430ES1,
1152 .recalc = &followparent_recalc,
1153};
1154
1155/* SGX power domain - 3430ES2 only */
1156
1157static const struct clksel_rate sgx_core_rates[] = {
1158 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1159 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1160 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1161 { .div = 0 },
1162};
1163
1164static const struct clksel_rate sgx_96m_rates[] = {
1165 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1166 { .div = 0 },
1167};
1168
1169static const struct clksel sgx_clksel[] = {
1170 { .parent = &core_ck, .rates = sgx_core_rates },
1171 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1172 { .parent = NULL },
1173};
1174
1175static struct clk sgx_fck = {
1176 .name = "sgx_fck",
1177 .init = &omap2_init_clksel_parent,
1178 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1179 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1180 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1181 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1182 .clksel = sgx_clksel,
1183 .flags = CLOCK_IN_OMAP3430ES2,
1184 .recalc = &omap2_clksel_recalc,
1185};
1186
1187static struct clk sgx_ick = {
1188 .name = "sgx_ick",
1189 .parent = &l3_ick,
1190 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1191 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1192 .flags = CLOCK_IN_OMAP3430ES2,
1193 .recalc = &followparent_recalc,
1194};
1195
1196/* CORE power domain */
1197
1198static struct clk d2d_26m_fck = {
1199 .name = "d2d_26m_fck",
1200 .parent = &sys_ck,
1201 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1202 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1203 .flags = CLOCK_IN_OMAP3430ES1,
1204 .recalc = &followparent_recalc,
1205};
1206
1207static const struct clksel omap343x_gpt_clksel[] = {
1208 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1209 { .parent = &sys_ck, .rates = gpt_sys_rates },
1210 { .parent = NULL}
1211};
1212
1213static struct clk gpt10_fck = {
1214 .name = "gpt10_fck",
1215 .parent = &sys_ck,
1216 .init = &omap2_init_clksel_parent,
1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1218 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1219 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1220 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1221 .clksel = omap343x_gpt_clksel,
1222 .flags = CLOCK_IN_OMAP343X,
1223 .recalc = &omap2_clksel_recalc,
1224};
1225
1226static struct clk gpt11_fck = {
1227 .name = "gpt11_fck",
1228 .parent = &sys_ck,
1229 .init = &omap2_init_clksel_parent,
1230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1231 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1232 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1233 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1234 .clksel = omap343x_gpt_clksel,
1235 .flags = CLOCK_IN_OMAP343X,
1236 .recalc = &omap2_clksel_recalc,
1237};
1238
1239static struct clk cpefuse_fck = {
1240 .name = "cpefuse_fck",
1241 .parent = &sys_ck,
1242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1243 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1244 .flags = CLOCK_IN_OMAP3430ES2,
1245 .recalc = &followparent_recalc,
1246};
1247
1248static struct clk ts_fck = {
1249 .name = "ts_fck",
1250 .parent = &omap_32k_fck,
1251 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1252 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1253 .flags = CLOCK_IN_OMAP3430ES2,
1254 .recalc = &followparent_recalc,
1255};
1256
1257static struct clk usbtll_fck = {
1258 .name = "usbtll_fck",
1259 .parent = &omap_120m_fck,
1260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1261 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1262 .flags = CLOCK_IN_OMAP3430ES2,
1263 .recalc = &followparent_recalc,
1264};
1265
1266/* CORE 96M FCLK-derived clocks */
1267
1268static struct clk core_96m_fck = {
1269 .name = "core_96m_fck",
1270 .parent = &omap_96m_fck,
1271 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1272 PARENT_CONTROLS_CLOCK,
1273 .recalc = &followparent_recalc,
1274};
1275
1276static struct clk mmchs3_fck = {
1277 .name = "mmchs_fck",
1278 .id = 3,
1279 .parent = &core_96m_fck,
1280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1282 .flags = CLOCK_IN_OMAP3430ES2,
1283 .recalc = &followparent_recalc,
1284};
1285
1286static struct clk mmchs2_fck = {
1287 .name = "mmchs_fck",
1288 .id = 2,
1289 .parent = &core_96m_fck,
1290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1291 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1292 .flags = CLOCK_IN_OMAP343X,
1293 .recalc = &followparent_recalc,
1294};
1295
1296static struct clk mspro_fck = {
1297 .name = "mspro_fck",
1298 .parent = &core_96m_fck,
1299 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1300 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1301 .flags = CLOCK_IN_OMAP343X,
1302 .recalc = &followparent_recalc,
1303};
1304
1305static struct clk mmchs1_fck = {
1306 .name = "mmchs_fck",
1307 .id = 1,
1308 .parent = &core_96m_fck,
1309 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1310 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1311 .flags = CLOCK_IN_OMAP343X,
1312 .recalc = &followparent_recalc,
1313};
1314
1315static struct clk i2c3_fck = {
1316 .name = "i2c_fck",
1317 .id = 3,
1318 .parent = &core_96m_fck,
1319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1320 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1321 .flags = CLOCK_IN_OMAP343X,
1322 .recalc = &followparent_recalc,
1323};
1324
1325static struct clk i2c2_fck = {
1326 .name = "i2c_fck",
1327 .id = 2,
1328 .parent = &core_96m_fck,
1329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1330 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1331 .flags = CLOCK_IN_OMAP343X,
1332 .recalc = &followparent_recalc,
1333};
1334
1335static struct clk i2c1_fck = {
1336 .name = "i2c_fck",
1337 .id = 1,
1338 .parent = &core_96m_fck,
1339 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1340 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1341 .flags = CLOCK_IN_OMAP343X,
1342 .recalc = &followparent_recalc,
1343};
1344
1345/*
1346 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1347 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1348 */
1349static const struct clksel_rate common_mcbsp_96m_rates[] = {
1350 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1351 { .div = 0 }
1352};
1353
1354static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1355 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1356 { .div = 0 }
1357};
1358
1359static const struct clksel mcbsp_15_clksel[] = {
1360 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1361 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1362 { .parent = NULL }
1363};
1364
1365static struct clk mcbsp5_fck = {
1366 .name = "mcbsp5_fck",
1367 .init = &omap2_init_clksel_parent,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1370 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1371 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1372 .clksel = mcbsp_15_clksel,
1373 .flags = CLOCK_IN_OMAP343X,
1374 .recalc = &omap2_clksel_recalc,
1375};
1376
1377static struct clk mcbsp1_fck = {
1378 .name = "mcbsp1_fck",
1379 .init = &omap2_init_clksel_parent,
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1382 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1383 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1384 .clksel = mcbsp_15_clksel,
1385 .flags = CLOCK_IN_OMAP343X,
1386 .recalc = &omap2_clksel_recalc,
1387};
1388
1389/* CORE_48M_FCK-derived clocks */
1390
1391static struct clk core_48m_fck = {
1392 .name = "core_48m_fck",
1393 .parent = &omap_48m_fck,
1394 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1395 PARENT_CONTROLS_CLOCK,
1396 .recalc = &followparent_recalc,
1397};
1398
1399static struct clk mcspi4_fck = {
1400 .name = "mcspi_fck",
1401 .id = 4,
1402 .parent = &core_48m_fck,
1403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1404 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1405 .flags = CLOCK_IN_OMAP343X,
1406 .recalc = &followparent_recalc,
1407};
1408
1409static struct clk mcspi3_fck = {
1410 .name = "mcspi_fck",
1411 .id = 3,
1412 .parent = &core_48m_fck,
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1415 .flags = CLOCK_IN_OMAP343X,
1416 .recalc = &followparent_recalc,
1417};
1418
1419static struct clk mcspi2_fck = {
1420 .name = "mcspi_fck",
1421 .id = 2,
1422 .parent = &core_48m_fck,
1423 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1424 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1425 .flags = CLOCK_IN_OMAP343X,
1426 .recalc = &followparent_recalc,
1427};
1428
1429static struct clk mcspi1_fck = {
1430 .name = "mcspi_fck",
1431 .id = 1,
1432 .parent = &core_48m_fck,
1433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1435 .flags = CLOCK_IN_OMAP343X,
1436 .recalc = &followparent_recalc,
1437};
1438
1439static struct clk uart2_fck = {
1440 .name = "uart2_fck",
1441 .parent = &core_48m_fck,
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1444 .flags = CLOCK_IN_OMAP343X,
1445 .recalc = &followparent_recalc,
1446};
1447
1448static struct clk uart1_fck = {
1449 .name = "uart1_fck",
1450 .parent = &core_48m_fck,
1451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1452 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1453 .flags = CLOCK_IN_OMAP343X,
1454 .recalc = &followparent_recalc,
1455};
1456
1457static struct clk fshostusb_fck = {
1458 .name = "fshostusb_fck",
1459 .parent = &core_48m_fck,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1462 .flags = CLOCK_IN_OMAP3430ES1,
1463 .recalc = &followparent_recalc,
1464};
1465
1466/* CORE_12M_FCK based clocks */
1467
1468static struct clk core_12m_fck = {
1469 .name = "core_12m_fck",
1470 .parent = &omap_12m_fck,
1471 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1472 PARENT_CONTROLS_CLOCK,
1473 .recalc = &followparent_recalc,
1474};
1475
1476static struct clk hdq_fck = {
1477 .name = "hdq_fck",
1478 .parent = &core_12m_fck,
1479 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1481 .flags = CLOCK_IN_OMAP343X,
1482 .recalc = &followparent_recalc,
1483};
1484
1485/* DPLL3-derived clock */
1486
1487static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1488 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1489 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1490 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1491 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1492 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1493 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1494 { .div = 0 }
1495};
1496
1497static const struct clksel ssi_ssr_clksel[] = {
1498 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1499 { .parent = NULL }
1500};
1501
1502static struct clk ssi_ssr_fck = {
1503 .name = "ssi_ssr_fck",
1504 .init = &omap2_init_clksel_parent,
1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1507 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1508 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1509 .clksel = ssi_ssr_clksel,
1510 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1511 .recalc = &omap2_clksel_recalc,
1512};
1513
1514static struct clk ssi_sst_fck = {
1515 .name = "ssi_sst_fck",
1516 .parent = &ssi_ssr_fck,
1517 .fixed_div = 2,
1518 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1519 .recalc = &omap2_fixed_divisor_recalc,
1520};
1521
1522
1523
1524/* CORE_L3_ICK based clocks */
1525
1526static struct clk core_l3_ick = {
1527 .name = "core_l3_ick",
1528 .parent = &l3_ick,
1529 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1530 PARENT_CONTROLS_CLOCK,
1531 .recalc = &followparent_recalc,
1532};
1533
1534static struct clk hsotgusb_ick = {
1535 .name = "hsotgusb_ick",
1536 .parent = &core_l3_ick,
1537 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1538 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1539 .flags = CLOCK_IN_OMAP343X,
1540 .recalc = &followparent_recalc,
1541};
1542
1543static struct clk sdrc_ick = {
1544 .name = "sdrc_ick",
1545 .parent = &core_l3_ick,
1546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1547 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1548 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1549 .recalc = &followparent_recalc,
1550};
1551
1552static struct clk gpmc_fck = {
1553 .name = "gpmc_fck",
1554 .parent = &core_l3_ick,
1555 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1556 ENABLE_ON_INIT,
1557 .recalc = &followparent_recalc,
1558};
1559
1560/* SECURITY_L3_ICK based clocks */
1561
1562static struct clk security_l3_ick = {
1563 .name = "security_l3_ick",
1564 .parent = &l3_ick,
1565 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1566 PARENT_CONTROLS_CLOCK,
1567 .recalc = &followparent_recalc,
1568};
1569
1570static struct clk pka_ick = {
1571 .name = "pka_ick",
1572 .parent = &security_l3_ick,
1573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1574 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1575 .flags = CLOCK_IN_OMAP343X,
1576 .recalc = &followparent_recalc,
1577};
1578
1579/* CORE_L4_ICK based clocks */
1580
1581static struct clk core_l4_ick = {
1582 .name = "core_l4_ick",
1583 .parent = &l4_ick,
1584 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1585 PARENT_CONTROLS_CLOCK,
1586 .recalc = &followparent_recalc,
1587};
1588
1589static struct clk usbtll_ick = {
1590 .name = "usbtll_ick",
1591 .parent = &core_l4_ick,
1592 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1593 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1594 .flags = CLOCK_IN_OMAP3430ES2,
1595 .recalc = &followparent_recalc,
1596};
1597
1598static struct clk mmchs3_ick = {
1599 .name = "mmchs_ick",
1600 .id = 3,
1601 .parent = &core_l4_ick,
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1604 .flags = CLOCK_IN_OMAP3430ES2,
1605 .recalc = &followparent_recalc,
1606};
1607
1608/* Intersystem Communication Registers - chassis mode only */
1609static struct clk icr_ick = {
1610 .name = "icr_ick",
1611 .parent = &core_l4_ick,
1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1613 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1614 .flags = CLOCK_IN_OMAP343X,
1615 .recalc = &followparent_recalc,
1616};
1617
1618static struct clk aes2_ick = {
1619 .name = "aes2_ick",
1620 .parent = &core_l4_ick,
1621 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1622 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1623 .flags = CLOCK_IN_OMAP343X,
1624 .recalc = &followparent_recalc,
1625};
1626
1627static struct clk sha12_ick = {
1628 .name = "sha12_ick",
1629 .parent = &core_l4_ick,
1630 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1631 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1632 .flags = CLOCK_IN_OMAP343X,
1633 .recalc = &followparent_recalc,
1634};
1635
1636static struct clk des2_ick = {
1637 .name = "des2_ick",
1638 .parent = &core_l4_ick,
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1640 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1641 .flags = CLOCK_IN_OMAP343X,
1642 .recalc = &followparent_recalc,
1643};
1644
1645static struct clk mmchs2_ick = {
1646 .name = "mmchs_ick",
1647 .id = 2,
1648 .parent = &core_l4_ick,
1649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1650 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1651 .flags = CLOCK_IN_OMAP343X,
1652 .recalc = &followparent_recalc,
1653};
1654
1655static struct clk mmchs1_ick = {
1656 .name = "mmchs_ick",
1657 .id = 1,
1658 .parent = &core_l4_ick,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1661 .flags = CLOCK_IN_OMAP343X,
1662 .recalc = &followparent_recalc,
1663};
1664
1665static struct clk mspro_ick = {
1666 .name = "mspro_ick",
1667 .parent = &core_l4_ick,
1668 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1669 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1670 .flags = CLOCK_IN_OMAP343X,
1671 .recalc = &followparent_recalc,
1672};
1673
1674static struct clk hdq_ick = {
1675 .name = "hdq_ick",
1676 .parent = &core_l4_ick,
1677 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1678 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1679 .flags = CLOCK_IN_OMAP343X,
1680 .recalc = &followparent_recalc,
1681};
1682
1683static struct clk mcspi4_ick = {
1684 .name = "mcspi_ick",
1685 .id = 4,
1686 .parent = &core_l4_ick,
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1688 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1689 .flags = CLOCK_IN_OMAP343X,
1690 .recalc = &followparent_recalc,
1691};
1692
1693static struct clk mcspi3_ick = {
1694 .name = "mcspi_ick",
1695 .id = 3,
1696 .parent = &core_l4_ick,
1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1698 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1699 .flags = CLOCK_IN_OMAP343X,
1700 .recalc = &followparent_recalc,
1701};
1702
1703static struct clk mcspi2_ick = {
1704 .name = "mcspi_ick",
1705 .id = 2,
1706 .parent = &core_l4_ick,
1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1708 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1709 .flags = CLOCK_IN_OMAP343X,
1710 .recalc = &followparent_recalc,
1711};
1712
1713static struct clk mcspi1_ick = {
1714 .name = "mcspi_ick",
1715 .id = 1,
1716 .parent = &core_l4_ick,
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1719 .flags = CLOCK_IN_OMAP343X,
1720 .recalc = &followparent_recalc,
1721};
1722
1723static struct clk i2c3_ick = {
1724 .name = "i2c_ick",
1725 .id = 3,
1726 .parent = &core_l4_ick,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1729 .flags = CLOCK_IN_OMAP343X,
1730 .recalc = &followparent_recalc,
1731};
1732
1733static struct clk i2c2_ick = {
1734 .name = "i2c_ick",
1735 .id = 2,
1736 .parent = &core_l4_ick,
1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1739 .flags = CLOCK_IN_OMAP343X,
1740 .recalc = &followparent_recalc,
1741};
1742
1743static struct clk i2c1_ick = {
1744 .name = "i2c_ick",
1745 .id = 1,
1746 .parent = &core_l4_ick,
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1749 .flags = CLOCK_IN_OMAP343X,
1750 .recalc = &followparent_recalc,
1751};
1752
1753static struct clk uart2_ick = {
1754 .name = "uart2_ick",
1755 .parent = &core_l4_ick,
1756 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1758 .flags = CLOCK_IN_OMAP343X,
1759 .recalc = &followparent_recalc,
1760};
1761
1762static struct clk uart1_ick = {
1763 .name = "uart1_ick",
1764 .parent = &core_l4_ick,
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1767 .flags = CLOCK_IN_OMAP343X,
1768 .recalc = &followparent_recalc,
1769};
1770
1771static struct clk gpt11_ick = {
1772 .name = "gpt11_ick",
1773 .parent = &core_l4_ick,
1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1775 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1776 .flags = CLOCK_IN_OMAP343X,
1777 .recalc = &followparent_recalc,
1778};
1779
1780static struct clk gpt10_ick = {
1781 .name = "gpt10_ick",
1782 .parent = &core_l4_ick,
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1785 .flags = CLOCK_IN_OMAP343X,
1786 .recalc = &followparent_recalc,
1787};
1788
1789static struct clk mcbsp5_ick = {
1790 .name = "mcbsp5_ick",
1791 .parent = &core_l4_ick,
1792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1793 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1794 .flags = CLOCK_IN_OMAP343X,
1795 .recalc = &followparent_recalc,
1796};
1797
1798static struct clk mcbsp1_ick = {
1799 .name = "mcbsp1_ick",
1800 .parent = &core_l4_ick,
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1803 .flags = CLOCK_IN_OMAP343X,
1804 .recalc = &followparent_recalc,
1805};
1806
1807static struct clk fac_ick = {
1808 .name = "fac_ick",
1809 .parent = &core_l4_ick,
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1812 .flags = CLOCK_IN_OMAP3430ES1,
1813 .recalc = &followparent_recalc,
1814};
1815
1816static struct clk mailboxes_ick = {
1817 .name = "mailboxes_ick",
1818 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1821 .flags = CLOCK_IN_OMAP343X,
1822 .recalc = &followparent_recalc,
1823};
1824
1825static struct clk omapctrl_ick = {
1826 .name = "omapctrl_ick",
1827 .parent = &core_l4_ick,
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1830 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1831 .recalc = &followparent_recalc,
1832};
1833
1834/* SSI_L4_ICK based clocks */
1835
1836static struct clk ssi_l4_ick = {
1837 .name = "ssi_l4_ick",
1838 .parent = &l4_ick,
1839 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1840 .recalc = &followparent_recalc,
1841};
1842
1843static struct clk ssi_ick = {
1844 .name = "ssi_ick",
1845 .parent = &ssi_l4_ick,
1846 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1848 .flags = CLOCK_IN_OMAP343X,
1849 .recalc = &followparent_recalc,
1850};
1851
1852/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1853 * but l4_ick makes more sense to me */
1854
1855static const struct clksel usb_l4_clksel[] = {
1856 { .parent = &l4_ick, .rates = div2_rates },
1857 { .parent = NULL },
1858};
1859
1860static struct clk usb_l4_ick = {
1861 .name = "usb_l4_ick",
1862 .parent = &l4_ick,
1863 .init = &omap2_init_clksel_parent,
1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1866 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1867 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1868 .clksel = usb_l4_clksel,
1869 .flags = CLOCK_IN_OMAP3430ES1,
1870 .recalc = &omap2_clksel_recalc,
1871};
1872
1873/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1874
1875/* SECURITY_L4_ICK2 based clocks */
1876
1877static struct clk security_l4_ick2 = {
1878 .name = "security_l4_ick2",
1879 .parent = &l4_ick,
1880 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1881 PARENT_CONTROLS_CLOCK,
1882 .recalc = &followparent_recalc,
1883};
1884
1885static struct clk aes1_ick = {
1886 .name = "aes1_ick",
1887 .parent = &security_l4_ick2,
1888 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1889 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1890 .flags = CLOCK_IN_OMAP343X,
1891 .recalc = &followparent_recalc,
1892};
1893
1894static struct clk rng_ick = {
1895 .name = "rng_ick",
1896 .parent = &security_l4_ick2,
1897 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1898 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1899 .flags = CLOCK_IN_OMAP343X,
1900 .recalc = &followparent_recalc,
1901};
1902
1903static struct clk sha11_ick = {
1904 .name = "sha11_ick",
1905 .parent = &security_l4_ick2,
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1907 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1908 .flags = CLOCK_IN_OMAP343X,
1909 .recalc = &followparent_recalc,
1910};
1911
1912static struct clk des1_ick = {
1913 .name = "des1_ick",
1914 .parent = &security_l4_ick2,
1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1916 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1917 .flags = CLOCK_IN_OMAP343X,
1918 .recalc = &followparent_recalc,
1919};
1920
1921/* DSS */
1922static const struct clksel dss1_alwon_fck_clksel[] = {
1923 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1924 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1925 { .parent = NULL }
1926};
1927
1928static struct clk dss1_alwon_fck = {
1929 .name = "dss1_alwon_fck",
1930 .parent = &dpll4_m4x2_ck,
1931 .init = &omap2_init_clksel_parent,
1932 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1933 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1934 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1935 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1936 .clksel = dss1_alwon_fck_clksel,
1937 .flags = CLOCK_IN_OMAP343X,
1938 .recalc = &omap2_clksel_recalc,
1939};
1940
1941static struct clk dss_tv_fck = {
1942 .name = "dss_tv_fck",
1943 .parent = &omap_54m_fck,
1944 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1945 .enable_bit = OMAP3430_EN_TV_SHIFT,
1946 .flags = CLOCK_IN_OMAP343X,
1947 .recalc = &followparent_recalc,
1948};
1949
1950static struct clk dss_96m_fck = {
1951 .name = "dss_96m_fck",
1952 .parent = &omap_96m_fck,
1953 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1954 .enable_bit = OMAP3430_EN_TV_SHIFT,
1955 .flags = CLOCK_IN_OMAP343X,
1956 .recalc = &followparent_recalc,
1957};
1958
1959static struct clk dss2_alwon_fck = {
1960 .name = "dss2_alwon_fck",
1961 .parent = &sys_ck,
1962 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1963 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1964 .flags = CLOCK_IN_OMAP343X,
1965 .recalc = &followparent_recalc,
1966};
1967
1968static struct clk dss_ick = {
1969 /* Handles both L3 and L4 clocks */
1970 .name = "dss_ick",
1971 .parent = &l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1973 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1974 .flags = CLOCK_IN_OMAP343X,
1975 .recalc = &followparent_recalc,
1976};
1977
1978/* CAM */
1979
1980static const struct clksel cam_mclk_clksel[] = {
1981 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1982 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1983 { .parent = NULL }
1984};
1985
1986static struct clk cam_mclk = {
1987 .name = "cam_mclk",
1988 .parent = &dpll4_m5x2_ck,
1989 .init = &omap2_init_clksel_parent,
1990 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1991 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1992 .clksel = cam_mclk_clksel,
1993 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1994 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1995 .flags = CLOCK_IN_OMAP343X,
1996 .recalc = &omap2_clksel_recalc,
1997};
1998
1999static struct clk cam_l3_ick = {
2000 .name = "cam_l3_ick",
2001 .parent = &l3_ick,
2002 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2003 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2004 .flags = CLOCK_IN_OMAP343X,
2005 .recalc = &followparent_recalc,
2006};
2007
2008static struct clk cam_l4_ick = {
2009 .name = "cam_l4_ick",
2010 .parent = &l4_ick,
2011 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2012 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2013 .flags = CLOCK_IN_OMAP343X,
2014 .recalc = &followparent_recalc,
2015};
2016
2017/* USBHOST - 3430ES2 only */
2018
2019static struct clk usbhost_120m_fck = {
2020 .name = "usbhost_120m_fck",
2021 .parent = &omap_120m_fck,
2022 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2023 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2024 .flags = CLOCK_IN_OMAP3430ES2,
2025 .recalc = &followparent_recalc,
2026};
2027
2028static struct clk usbhost_48m_fck = {
2029 .name = "usbhost_48m_fck",
2030 .parent = &omap_48m_fck,
2031 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2032 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2033 .flags = CLOCK_IN_OMAP3430ES2,
2034 .recalc = &followparent_recalc,
2035};
2036
2037static struct clk usbhost_l3_ick = {
2038 .name = "usbhost_l3_ick",
2039 .parent = &l3_ick,
2040 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2041 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2042 .flags = CLOCK_IN_OMAP3430ES2,
2043 .recalc = &followparent_recalc,
2044};
2045
2046static struct clk usbhost_l4_ick = {
2047 .name = "usbhost_l4_ick",
2048 .parent = &l4_ick,
2049 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2050 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2051 .flags = CLOCK_IN_OMAP3430ES2,
2052 .recalc = &followparent_recalc,
2053};
2054
2055static struct clk usbhost_sar_fck = {
2056 .name = "usbhost_sar_fck",
2057 .parent = &osc_sys_ck,
2058 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2059 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2060 .flags = CLOCK_IN_OMAP3430ES2,
2061 .recalc = &followparent_recalc,
2062};
2063
2064/* WKUP */
2065
2066static const struct clksel_rate usim_96m_rates[] = {
2067 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2068 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2069 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2070 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2071 { .div = 0 },
2072};
2073
2074static const struct clksel_rate usim_120m_rates[] = {
2075 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2076 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2077 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2078 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2079 { .div = 0 },
2080};
2081
2082static const struct clksel usim_clksel[] = {
2083 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2084 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2085 { .parent = &sys_ck, .rates = div2_rates },
2086 { .parent = NULL },
2087};
2088
2089/* 3430ES2 only */
2090static struct clk usim_fck = {
2091 .name = "usim_fck",
2092 .init = &omap2_init_clksel_parent,
2093 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2094 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2095 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2096 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2097 .clksel = usim_clksel,
2098 .flags = CLOCK_IN_OMAP3430ES2,
2099 .recalc = &omap2_clksel_recalc,
2100};
2101
2102static struct clk gpt1_fck = {
2103 .name = "gpt1_fck",
2104 .init = &omap2_init_clksel_parent,
2105 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2106 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2107 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2108 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2109 .clksel = omap343x_gpt_clksel,
2110 .flags = CLOCK_IN_OMAP343X,
2111 .recalc = &omap2_clksel_recalc,
2112};
2113
2114static struct clk wkup_32k_fck = {
2115 .name = "wkup_32k_fck",
2116 .parent = &omap_32k_fck,
2117 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2118 .recalc = &followparent_recalc,
2119};
2120
2121static struct clk gpio1_fck = {
2122 .name = "gpio1_fck",
2123 .parent = &wkup_32k_fck,
2124 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2125 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2126 .flags = CLOCK_IN_OMAP343X,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk wdt2_fck = {
2131 .name = "wdt2_fck",
2132 .parent = &wkup_32k_fck,
2133 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2134 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2135 .flags = CLOCK_IN_OMAP343X,
2136 .recalc = &followparent_recalc,
2137};
2138
2139static struct clk wkup_l4_ick = {
2140 .name = "wkup_l4_ick",
2141 .parent = &sys_ck,
2142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2143 .recalc = &followparent_recalc,
2144};
2145
2146/* 3430ES2 only */
2147/* Never specifically named in the TRM, so we have to infer a likely name */
2148static struct clk usim_ick = {
2149 .name = "usim_ick",
2150 .parent = &wkup_l4_ick,
2151 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2152 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2153 .flags = CLOCK_IN_OMAP3430ES2,
2154 .recalc = &followparent_recalc,
2155};
2156
2157static struct clk wdt2_ick = {
2158 .name = "wdt2_ick",
2159 .parent = &wkup_l4_ick,
2160 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2161 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2162 .flags = CLOCK_IN_OMAP343X,
2163 .recalc = &followparent_recalc,
2164};
2165
2166static struct clk wdt1_ick = {
2167 .name = "wdt1_ick",
2168 .parent = &wkup_l4_ick,
2169 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2170 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2171 .flags = CLOCK_IN_OMAP343X,
2172 .recalc = &followparent_recalc,
2173};
2174
2175static struct clk gpio1_ick = {
2176 .name = "gpio1_ick",
2177 .parent = &wkup_l4_ick,
2178 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2179 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2180 .flags = CLOCK_IN_OMAP343X,
2181 .recalc = &followparent_recalc,
2182};
2183
2184static struct clk omap_32ksync_ick = {
2185 .name = "omap_32ksync_ick",
2186 .parent = &wkup_l4_ick,
2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2188 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2189 .flags = CLOCK_IN_OMAP343X,
2190 .recalc = &followparent_recalc,
2191};
2192
2193static struct clk gpt12_ick = {
2194 .name = "gpt12_ick",
2195 .parent = &wkup_l4_ick,
2196 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2197 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2198 .flags = CLOCK_IN_OMAP343X,
2199 .recalc = &followparent_recalc,
2200};
2201
2202static struct clk gpt1_ick = {
2203 .name = "gpt1_ick",
2204 .parent = &wkup_l4_ick,
2205 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2206 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2207 .flags = CLOCK_IN_OMAP343X,
2208 .recalc = &followparent_recalc,
2209};
2210
2211
2212
2213/* PER clock domain */
2214
2215static struct clk per_96m_fck = {
2216 .name = "per_96m_fck",
2217 .parent = &omap_96m_alwon_fck,
2218 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2219 PARENT_CONTROLS_CLOCK,
2220 .recalc = &followparent_recalc,
2221};
2222
2223static struct clk per_48m_fck = {
2224 .name = "per_48m_fck",
2225 .parent = &omap_48m_fck,
2226 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2227 PARENT_CONTROLS_CLOCK,
2228 .recalc = &followparent_recalc,
2229};
2230
2231static struct clk uart3_fck = {
2232 .name = "uart3_fck",
2233 .parent = &per_48m_fck,
2234 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2235 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2236 .flags = CLOCK_IN_OMAP343X,
2237 .recalc = &followparent_recalc,
2238};
2239
2240static struct clk gpt2_fck = {
2241 .name = "gpt2_fck",
2242 .init = &omap2_init_clksel_parent,
2243 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2244 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2245 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2246 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2247 .clksel = omap343x_gpt_clksel,
2248 .flags = CLOCK_IN_OMAP343X,
2249 .recalc = &omap2_clksel_recalc,
2250};
2251
2252static struct clk gpt3_fck = {
2253 .name = "gpt3_fck",
2254 .init = &omap2_init_clksel_parent,
2255 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2256 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2257 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2258 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2259 .clksel = omap343x_gpt_clksel,
2260 .flags = CLOCK_IN_OMAP343X,
2261 .recalc = &omap2_clksel_recalc,
2262};
2263
2264static struct clk gpt4_fck = {
2265 .name = "gpt4_fck",
2266 .init = &omap2_init_clksel_parent,
2267 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2268 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2269 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2270 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2271 .clksel = omap343x_gpt_clksel,
2272 .flags = CLOCK_IN_OMAP343X,
2273 .recalc = &omap2_clksel_recalc,
2274};
2275
2276static struct clk gpt5_fck = {
2277 .name = "gpt5_fck",
2278 .init = &omap2_init_clksel_parent,
2279 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2280 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2281 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2282 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2283 .clksel = omap343x_gpt_clksel,
2284 .flags = CLOCK_IN_OMAP343X,
2285 .recalc = &omap2_clksel_recalc,
2286};
2287
2288static struct clk gpt6_fck = {
2289 .name = "gpt6_fck",
2290 .init = &omap2_init_clksel_parent,
2291 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2292 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2293 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2294 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2295 .clksel = omap343x_gpt_clksel,
2296 .flags = CLOCK_IN_OMAP343X,
2297 .recalc = &omap2_clksel_recalc,
2298};
2299
2300static struct clk gpt7_fck = {
2301 .name = "gpt7_fck",
2302 .init = &omap2_init_clksel_parent,
2303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2304 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2305 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2306 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2307 .clksel = omap343x_gpt_clksel,
2308 .flags = CLOCK_IN_OMAP343X,
2309 .recalc = &omap2_clksel_recalc,
2310};
2311
2312static struct clk gpt8_fck = {
2313 .name = "gpt8_fck",
2314 .init = &omap2_init_clksel_parent,
2315 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2316 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2317 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2318 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2319 .clksel = omap343x_gpt_clksel,
2320 .flags = CLOCK_IN_OMAP343X,
2321 .recalc = &omap2_clksel_recalc,
2322};
2323
2324static struct clk gpt9_fck = {
2325 .name = "gpt9_fck",
2326 .init = &omap2_init_clksel_parent,
2327 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2328 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2329 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2330 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2331 .clksel = omap343x_gpt_clksel,
2332 .flags = CLOCK_IN_OMAP343X,
2333 .recalc = &omap2_clksel_recalc,
2334};
2335
2336static struct clk per_32k_alwon_fck = {
2337 .name = "per_32k_alwon_fck",
2338 .parent = &omap_32k_fck,
2339 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2340 .recalc = &followparent_recalc,
2341};
2342
2343static struct clk gpio6_fck = {
2344 .name = "gpio6_fck",
2345 .parent = &per_32k_alwon_fck,
2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2348 .flags = CLOCK_IN_OMAP343X,
2349 .recalc = &followparent_recalc,
2350};
2351
2352static struct clk gpio5_fck = {
2353 .name = "gpio5_fck",
2354 .parent = &per_32k_alwon_fck,
2355 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2356 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2357 .flags = CLOCK_IN_OMAP343X,
2358 .recalc = &followparent_recalc,
2359};
2360
2361static struct clk gpio4_fck = {
2362 .name = "gpio4_fck",
2363 .parent = &per_32k_alwon_fck,
2364 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2365 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2366 .flags = CLOCK_IN_OMAP343X,
2367 .recalc = &followparent_recalc,
2368};
2369
2370static struct clk gpio3_fck = {
2371 .name = "gpio3_fck",
2372 .parent = &per_32k_alwon_fck,
2373 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2374 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2375 .flags = CLOCK_IN_OMAP343X,
2376 .recalc = &followparent_recalc,
2377};
2378
2379static struct clk gpio2_fck = {
2380 .name = "gpio2_fck",
2381 .parent = &per_32k_alwon_fck,
2382 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2383 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2384 .flags = CLOCK_IN_OMAP343X,
2385 .recalc = &followparent_recalc,
2386};
2387
2388static struct clk wdt3_fck = {
2389 .name = "wdt3_fck",
2390 .parent = &per_32k_alwon_fck,
2391 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2392 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2393 .flags = CLOCK_IN_OMAP343X,
2394 .recalc = &followparent_recalc,
2395};
2396
2397static struct clk per_l4_ick = {
2398 .name = "per_l4_ick",
2399 .parent = &l4_ick,
2400 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2401 PARENT_CONTROLS_CLOCK,
2402 .recalc = &followparent_recalc,
2403};
2404
2405static struct clk gpio6_ick = {
2406 .name = "gpio6_ick",
2407 .parent = &per_l4_ick,
2408 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2409 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2410 .flags = CLOCK_IN_OMAP343X,
2411 .recalc = &followparent_recalc,
2412};
2413
2414static struct clk gpio5_ick = {
2415 .name = "gpio5_ick",
2416 .parent = &per_l4_ick,
2417 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2418 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2419 .flags = CLOCK_IN_OMAP343X,
2420 .recalc = &followparent_recalc,
2421};
2422
2423static struct clk gpio4_ick = {
2424 .name = "gpio4_ick",
2425 .parent = &per_l4_ick,
2426 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2427 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2428 .flags = CLOCK_IN_OMAP343X,
2429 .recalc = &followparent_recalc,
2430};
2431
2432static struct clk gpio3_ick = {
2433 .name = "gpio3_ick",
2434 .parent = &per_l4_ick,
2435 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2436 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2437 .flags = CLOCK_IN_OMAP343X,
2438 .recalc = &followparent_recalc,
2439};
2440
2441static struct clk gpio2_ick = {
2442 .name = "gpio2_ick",
2443 .parent = &per_l4_ick,
2444 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2445 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2446 .flags = CLOCK_IN_OMAP343X,
2447 .recalc = &followparent_recalc,
2448};
2449
2450static struct clk wdt3_ick = {
2451 .name = "wdt3_ick",
2452 .parent = &per_l4_ick,
2453 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2454 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2455 .flags = CLOCK_IN_OMAP343X,
2456 .recalc = &followparent_recalc,
2457};
2458
2459static struct clk uart3_ick = {
2460 .name = "uart3_ick",
2461 .parent = &per_l4_ick,
2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2463 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2464 .flags = CLOCK_IN_OMAP343X,
2465 .recalc = &followparent_recalc,
2466};
2467
2468static struct clk gpt9_ick = {
2469 .name = "gpt9_ick",
2470 .parent = &per_l4_ick,
2471 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2472 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2473 .flags = CLOCK_IN_OMAP343X,
2474 .recalc = &followparent_recalc,
2475};
2476
2477static struct clk gpt8_ick = {
2478 .name = "gpt8_ick",
2479 .parent = &per_l4_ick,
2480 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2481 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2482 .flags = CLOCK_IN_OMAP343X,
2483 .recalc = &followparent_recalc,
2484};
2485
2486static struct clk gpt7_ick = {
2487 .name = "gpt7_ick",
2488 .parent = &per_l4_ick,
2489 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2490 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2491 .flags = CLOCK_IN_OMAP343X,
2492 .recalc = &followparent_recalc,
2493};
2494
2495static struct clk gpt6_ick = {
2496 .name = "gpt6_ick",
2497 .parent = &per_l4_ick,
2498 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2499 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2500 .flags = CLOCK_IN_OMAP343X,
2501 .recalc = &followparent_recalc,
2502};
2503
2504static struct clk gpt5_ick = {
2505 .name = "gpt5_ick",
2506 .parent = &per_l4_ick,
2507 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2508 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2509 .flags = CLOCK_IN_OMAP343X,
2510 .recalc = &followparent_recalc,
2511};
2512
2513static struct clk gpt4_ick = {
2514 .name = "gpt4_ick",
2515 .parent = &per_l4_ick,
2516 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2517 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2518 .flags = CLOCK_IN_OMAP343X,
2519 .recalc = &followparent_recalc,
2520};
2521
2522static struct clk gpt3_ick = {
2523 .name = "gpt3_ick",
2524 .parent = &per_l4_ick,
2525 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2526 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2527 .flags = CLOCK_IN_OMAP343X,
2528 .recalc = &followparent_recalc,
2529};
2530
2531static struct clk gpt2_ick = {
2532 .name = "gpt2_ick",
2533 .parent = &per_l4_ick,
2534 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2535 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2536 .flags = CLOCK_IN_OMAP343X,
2537 .recalc = &followparent_recalc,
2538};
2539
2540static struct clk mcbsp2_ick = {
2541 .name = "mcbsp2_ick",
2542 .parent = &per_l4_ick,
2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2544 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2545 .flags = CLOCK_IN_OMAP343X,
2546 .recalc = &followparent_recalc,
2547};
2548
2549static struct clk mcbsp3_ick = {
2550 .name = "mcbsp3_ick",
2551 .parent = &per_l4_ick,
2552 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2553 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2554 .flags = CLOCK_IN_OMAP343X,
2555 .recalc = &followparent_recalc,
2556};
2557
2558static struct clk mcbsp4_ick = {
2559 .name = "mcbsp4_ick",
2560 .parent = &per_l4_ick,
2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2562 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2563 .flags = CLOCK_IN_OMAP343X,
2564 .recalc = &followparent_recalc,
2565};
2566
2567static const struct clksel mcbsp_234_clksel[] = {
2568 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2569 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2570 { .parent = NULL }
2571};
2572
2573static struct clk mcbsp2_fck = {
2574 .name = "mcbsp2_fck",
2575 .init = &omap2_init_clksel_parent,
2576 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2578 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2579 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2580 .clksel = mcbsp_234_clksel,
2581 .flags = CLOCK_IN_OMAP343X,
2582 .recalc = &omap2_clksel_recalc,
2583};
2584
2585static struct clk mcbsp3_fck = {
2586 .name = "mcbsp3_fck",
2587 .init = &omap2_init_clksel_parent,
2588 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2589 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2590 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2591 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2592 .clksel = mcbsp_234_clksel,
2593 .flags = CLOCK_IN_OMAP343X,
2594 .recalc = &omap2_clksel_recalc,
2595};
2596
2597static struct clk mcbsp4_fck = {
2598 .name = "mcbsp4_fck",
2599 .init = &omap2_init_clksel_parent,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2602 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2603 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2604 .clksel = mcbsp_234_clksel,
2605 .flags = CLOCK_IN_OMAP343X,
2606 .recalc = &omap2_clksel_recalc,
2607};
2608
2609/* EMU clocks */
2610
2611/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2612
2613static const struct clksel_rate emu_src_sys_rates[] = {
2614 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2615 { .div = 0 },
2616};
2617
2618static const struct clksel_rate emu_src_core_rates[] = {
2619 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2620 { .div = 0 },
2621};
2622
2623static const struct clksel_rate emu_src_per_rates[] = {
2624 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2625 { .div = 0 },
2626};
2627
2628static const struct clksel_rate emu_src_mpu_rates[] = {
2629 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2630 { .div = 0 },
2631};
2632
2633static const struct clksel emu_src_clksel[] = {
2634 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2635 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2636 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2637 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2638 { .parent = NULL },
2639};
2640
2641/*
2642 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2643 * to switch the source of some of the EMU clocks.
2644 * XXX Are there CLKEN bits for these EMU clks?
2645 */
2646static struct clk emu_src_ck = {
2647 .name = "emu_src_ck",
2648 .init = &omap2_init_clksel_parent,
2649 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2650 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2651 .clksel = emu_src_clksel,
2652 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2653 .recalc = &omap2_clksel_recalc,
2654};
2655
2656static const struct clksel_rate pclk_emu_rates[] = {
2657 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2658 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2659 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2660 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2661 { .div = 0 },
2662};
2663
2664static const struct clksel pclk_emu_clksel[] = {
2665 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2666 { .parent = NULL },
2667};
2668
2669static struct clk pclk_fck = {
2670 .name = "pclk_fck",
2671 .init = &omap2_init_clksel_parent,
2672 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2673 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2674 .clksel = pclk_emu_clksel,
2675 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2676 .recalc = &omap2_clksel_recalc,
2677};
2678
2679static const struct clksel_rate pclkx2_emu_rates[] = {
2680 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2681 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2682 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2683 { .div = 0 },
2684};
2685
2686static const struct clksel pclkx2_emu_clksel[] = {
2687 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2688 { .parent = NULL },
2689};
2690
2691static struct clk pclkx2_fck = {
2692 .name = "pclkx2_fck",
2693 .init = &omap2_init_clksel_parent,
2694 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2695 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2696 .clksel = pclkx2_emu_clksel,
2697 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2698 .recalc = &omap2_clksel_recalc,
2699};
2700
2701static const struct clksel atclk_emu_clksel[] = {
2702 { .parent = &emu_src_ck, .rates = div2_rates },
2703 { .parent = NULL },
2704};
2705
2706static struct clk atclk_fck = {
2707 .name = "atclk_fck",
2708 .init = &omap2_init_clksel_parent,
2709 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2710 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2711 .clksel = atclk_emu_clksel,
2712 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2713 .recalc = &omap2_clksel_recalc,
2714};
2715
2716static struct clk traceclk_src_fck = {
2717 .name = "traceclk_src_fck",
2718 .init = &omap2_init_clksel_parent,
2719 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2720 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2721 .clksel = emu_src_clksel,
2722 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2723 .recalc = &omap2_clksel_recalc,
2724};
2725
2726static const struct clksel_rate traceclk_rates[] = {
2727 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2728 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2729 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2730 { .div = 0 },
2731};
2732
2733static const struct clksel traceclk_clksel[] = {
2734 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2735 { .parent = NULL },
2736};
2737
2738static struct clk traceclk_fck = {
2739 .name = "traceclk_fck",
2740 .init = &omap2_init_clksel_parent,
2741 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2742 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2743 .clksel = traceclk_clksel,
2744 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2745 .recalc = &omap2_clksel_recalc,
2746};
2747
2748/* SR clocks */
2749
2750/* SmartReflex fclk (VDD1) */
2751static struct clk sr1_fck = {
2752 .name = "sr1_fck",
2753 .parent = &sys_ck,
2754 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2755 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2757 .recalc = &followparent_recalc,
2758};
2759
2760/* SmartReflex fclk (VDD2) */
2761static struct clk sr2_fck = {
2762 .name = "sr2_fck",
2763 .parent = &sys_ck,
2764 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2765 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2766 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2767 .recalc = &followparent_recalc,
2768};
2769
2770static struct clk sr_l4_ick = {
2771 .name = "sr_l4_ick",
2772 .parent = &l4_ick,
2773 .flags = CLOCK_IN_OMAP343X,
2774 .recalc = &followparent_recalc,
2775};
2776
2777/* SECURE_32K_FCK clocks */
2778
2779static struct clk gpt12_fck = {
2780 .name = "gpt12_fck",
2781 .parent = &secure_32k_fck,
2782 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2783 .recalc = &followparent_recalc,
2784};
2785
2786static struct clk wdt1_fck = {
2787 .name = "wdt1_fck",
2788 .parent = &secure_32k_fck,
2789 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2790 .recalc = &followparent_recalc,
2791};
2792
2793static struct clk *onchip_34xx_clks[] __initdata = {
2794 &omap_32k_fck,
2795 &virt_12m_ck,
2796 &virt_13m_ck,
2797 &virt_16_8m_ck,
2798 &virt_19_2m_ck,
2799 &virt_26m_ck,
2800 &virt_38_4m_ck,
2801 &osc_sys_ck,
2802 &sys_ck,
2803 &sys_altclk,
2804 &mcbsp_clks,
2805 &sys_clkout1,
2806 &dpll1_ck,
2807 &dpll1_x2_ck,
2808 &dpll1_x2m2_ck,
2809 &dpll2_ck,
2810 &dpll2_m2_ck,
2811 &dpll3_ck,
2812 &core_ck,
2813 &dpll3_x2_ck,
2814 &dpll3_m2_ck,
2815 &dpll3_m2x2_ck,
2816 &dpll3_m3_ck,
2817 &dpll3_m3x2_ck,
2818 &emu_core_alwon_ck,
2819 &dpll4_ck,
2820 &dpll4_x2_ck,
2821 &omap_96m_alwon_fck,
2822 &omap_96m_fck,
2823 &cm_96m_fck,
2824 &virt_omap_54m_fck,
2825 &omap_54m_fck,
2826 &omap_48m_fck,
2827 &omap_12m_fck,
2828 &dpll4_m2_ck,
2829 &dpll4_m2x2_ck,
2830 &dpll4_m3_ck,
2831 &dpll4_m3x2_ck,
2832 &dpll4_m4_ck,
2833 &dpll4_m4x2_ck,
2834 &dpll4_m5_ck,
2835 &dpll4_m5x2_ck,
2836 &dpll4_m6_ck,
2837 &dpll4_m6x2_ck,
2838 &emu_per_alwon_ck,
2839 &dpll5_ck,
2840 &dpll5_m2_ck,
2841 &omap_120m_fck,
2842 &clkout2_src_ck,
2843 &sys_clkout2,
2844 &corex2_fck,
2845 &dpll1_fck,
2846 &mpu_ck,
2847 &arm_fck,
2848 &emu_mpu_alwon_ck,
2849 &dpll2_fck,
2850 &iva2_ck,
2851 &l3_ick,
2852 &l4_ick,
2853 &rm_ick,
2854 &gfx_l3_fck,
2855 &gfx_l3_ick,
2856 &gfx_cg1_ck,
2857 &gfx_cg2_ck,
2858 &sgx_fck,
2859 &sgx_ick,
2860 &d2d_26m_fck,
2861 &gpt10_fck,
2862 &gpt11_fck,
2863 &cpefuse_fck,
2864 &ts_fck,
2865 &usbtll_fck,
2866 &core_96m_fck,
2867 &mmchs3_fck,
2868 &mmchs2_fck,
2869 &mspro_fck,
2870 &mmchs1_fck,
2871 &i2c3_fck,
2872 &i2c2_fck,
2873 &i2c1_fck,
2874 &mcbsp5_fck,
2875 &mcbsp1_fck,
2876 &core_48m_fck,
2877 &mcspi4_fck,
2878 &mcspi3_fck,
2879 &mcspi2_fck,
2880 &mcspi1_fck,
2881 &uart2_fck,
2882 &uart1_fck,
2883 &fshostusb_fck,
2884 &core_12m_fck,
2885 &hdq_fck,
2886 &ssi_ssr_fck,
2887 &ssi_sst_fck,
2888 &core_l3_ick,
2889 &hsotgusb_ick,
2890 &sdrc_ick,
2891 &gpmc_fck,
2892 &security_l3_ick,
2893 &pka_ick,
2894 &core_l4_ick,
2895 &usbtll_ick,
2896 &mmchs3_ick,
2897 &icr_ick,
2898 &aes2_ick,
2899 &sha12_ick,
2900 &des2_ick,
2901 &mmchs2_ick,
2902 &mmchs1_ick,
2903 &mspro_ick,
2904 &hdq_ick,
2905 &mcspi4_ick,
2906 &mcspi3_ick,
2907 &mcspi2_ick,
2908 &mcspi1_ick,
2909 &i2c3_ick,
2910 &i2c2_ick,
2911 &i2c1_ick,
2912 &uart2_ick,
2913 &uart1_ick,
2914 &gpt11_ick,
2915 &gpt10_ick,
2916 &mcbsp5_ick,
2917 &mcbsp1_ick,
2918 &fac_ick,
2919 &mailboxes_ick,
2920 &omapctrl_ick,
2921 &ssi_l4_ick,
2922 &ssi_ick,
2923 &usb_l4_ick,
2924 &security_l4_ick2,
2925 &aes1_ick,
2926 &rng_ick,
2927 &sha11_ick,
2928 &des1_ick,
2929 &dss1_alwon_fck,
2930 &dss_tv_fck,
2931 &dss_96m_fck,
2932 &dss2_alwon_fck,
2933 &dss_ick,
2934 &cam_mclk,
2935 &cam_l3_ick,
2936 &cam_l4_ick,
2937 &usbhost_120m_fck,
2938 &usbhost_48m_fck,
2939 &usbhost_l3_ick,
2940 &usbhost_l4_ick,
2941 &usbhost_sar_fck,
2942 &usim_fck,
2943 &gpt1_fck,
2944 &wkup_32k_fck,
2945 &gpio1_fck,
2946 &wdt2_fck,
2947 &wkup_l4_ick,
2948 &usim_ick,
2949 &wdt2_ick,
2950 &wdt1_ick,
2951 &gpio1_ick,
2952 &omap_32ksync_ick,
2953 &gpt12_ick,
2954 &gpt1_ick,
2955 &per_96m_fck,
2956 &per_48m_fck,
2957 &uart3_fck,
2958 &gpt2_fck,
2959 &gpt3_fck,
2960 &gpt4_fck,
2961 &gpt5_fck,
2962 &gpt6_fck,
2963 &gpt7_fck,
2964 &gpt8_fck,
2965 &gpt9_fck,
2966 &per_32k_alwon_fck,
2967 &gpio6_fck,
2968 &gpio5_fck,
2969 &gpio4_fck,
2970 &gpio3_fck,
2971 &gpio2_fck,
2972 &wdt3_fck,
2973 &per_l4_ick,
2974 &gpio6_ick,
2975 &gpio5_ick,
2976 &gpio4_ick,
2977 &gpio3_ick,
2978 &gpio2_ick,
2979 &wdt3_ick,
2980 &uart3_ick,
2981 &gpt9_ick,
2982 &gpt8_ick,
2983 &gpt7_ick,
2984 &gpt6_ick,
2985 &gpt5_ick,
2986 &gpt4_ick,
2987 &gpt3_ick,
2988 &gpt2_ick,
2989 &mcbsp2_ick,
2990 &mcbsp3_ick,
2991 &mcbsp4_ick,
2992 &mcbsp2_fck,
2993 &mcbsp3_fck,
2994 &mcbsp4_fck,
2995 &emu_src_ck,
2996 &pclk_fck,
2997 &pclkx2_fck,
2998 &atclk_fck,
2999 &traceclk_src_fck,
3000 &traceclk_fck,
3001 &sr1_fck,
3002 &sr2_fck,
3003 &sr_l4_ick,
3004 &secure_32k_fck,
3005 &gpt12_fck,
3006 &wdt1_fck,
3007};
3008
3009#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
new file mode 100644
index 00000000000..20ac3810067
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -0,0 +1,401 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
3
4/*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "cm.h"
18
19/* Bits shared between registers */
20
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22#define OMAP24XX_EN_CAM_SHIFT 31
23#define OMAP24XX_EN_CAM (1 << 31)
24#define OMAP24XX_EN_WDT4_SHIFT 29
25#define OMAP24XX_EN_WDT4 (1 << 29)
26#define OMAP2420_EN_WDT3_SHIFT 28
27#define OMAP2420_EN_WDT3 (1 << 28)
28#define OMAP24XX_EN_MSPRO_SHIFT 27
29#define OMAP24XX_EN_MSPRO (1 << 27)
30#define OMAP24XX_EN_FAC_SHIFT 25
31#define OMAP24XX_EN_FAC (1 << 25)
32#define OMAP2420_EN_EAC_SHIFT 24
33#define OMAP2420_EN_EAC (1 << 24)
34#define OMAP24XX_EN_HDQ_SHIFT 23
35#define OMAP24XX_EN_HDQ (1 << 23)
36#define OMAP2420_EN_I2C2_SHIFT 20
37#define OMAP2420_EN_I2C2 (1 << 20)
38#define OMAP2420_EN_I2C1_SHIFT 19
39#define OMAP2420_EN_I2C1 (1 << 19)
40
41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
42#define OMAP2430_EN_MCBSP5_SHIFT 5
43#define OMAP2430_EN_MCBSP5 (1 << 5)
44#define OMAP2430_EN_MCBSP4_SHIFT 4
45#define OMAP2430_EN_MCBSP4 (1 << 4)
46#define OMAP2430_EN_MCBSP3_SHIFT 3
47#define OMAP2430_EN_MCBSP3 (1 << 3)
48#define OMAP24XX_EN_SSI_SHIFT 1
49#define OMAP24XX_EN_SSI (1 << 1)
50
51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
52#define OMAP24XX_EN_MPU_WDT_SHIFT 3
53#define OMAP24XX_EN_MPU_WDT (1 << 3)
54
55/* Bits specific to each register */
56
57/* CM_IDLEST_MPU */
58/* 2430 only */
59#define OMAP2430_ST_MPU (1 << 0)
60
61/* CM_CLKSEL_MPU */
62#define OMAP24XX_CLKSEL_MPU_SHIFT 0
63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
64
65/* CM_CLKSTCTRL_MPU */
66#define OMAP24XX_AUTOSTATE_MPU (1 << 0)
67
68/* CM_FCLKEN1_CORE specific bits*/
69#define OMAP24XX_EN_TV_SHIFT 2
70#define OMAP24XX_EN_TV (1 << 2)
71#define OMAP24XX_EN_DSS2_SHIFT 1
72#define OMAP24XX_EN_DSS2 (1 << 1)
73#define OMAP24XX_EN_DSS1_SHIFT 0
74#define OMAP24XX_EN_DSS1 (1 << 0)
75
76/* CM_FCLKEN2_CORE specific bits */
77#define OMAP2430_EN_I2CHS2_SHIFT 20
78#define OMAP2430_EN_I2CHS2 (1 << 20)
79#define OMAP2430_EN_I2CHS1_SHIFT 19
80#define OMAP2430_EN_I2CHS1 (1 << 19)
81#define OMAP2430_EN_MMCHSDB2_SHIFT 17
82#define OMAP2430_EN_MMCHSDB2 (1 << 17)
83#define OMAP2430_EN_MMCHSDB1_SHIFT 16
84#define OMAP2430_EN_MMCHSDB1 (1 << 16)
85
86/* CM_ICLKEN1_CORE specific bits */
87#define OMAP24XX_EN_MAILBOXES_SHIFT 30
88#define OMAP24XX_EN_MAILBOXES (1 << 30)
89#define OMAP24XX_EN_DSS_SHIFT 0
90#define OMAP24XX_EN_DSS (1 << 0)
91
92/* CM_ICLKEN2_CORE specific bits */
93
94/* CM_ICLKEN3_CORE */
95/* 2430 only */
96#define OMAP2430_EN_SDRC_SHIFT 2
97#define OMAP2430_EN_SDRC (1 << 2)
98
99/* CM_ICLKEN4_CORE */
100#define OMAP24XX_EN_PKA_SHIFT 4
101#define OMAP24XX_EN_PKA (1 << 4)
102#define OMAP24XX_EN_AES_SHIFT 3
103#define OMAP24XX_EN_AES (1 << 3)
104#define OMAP24XX_EN_RNG_SHIFT 2
105#define OMAP24XX_EN_RNG (1 << 2)
106#define OMAP24XX_EN_SHA_SHIFT 1
107#define OMAP24XX_EN_SHA (1 << 1)
108#define OMAP24XX_EN_DES_SHIFT 0
109#define OMAP24XX_EN_DES (1 << 0)
110
111/* CM_IDLEST1_CORE specific bits */
112#define OMAP24XX_ST_MAILBOXES (1 << 30)
113#define OMAP24XX_ST_WDT4 (1 << 29)
114#define OMAP2420_ST_WDT3 (1 << 28)
115#define OMAP24XX_ST_MSPRO (1 << 27)
116#define OMAP24XX_ST_FAC (1 << 25)
117#define OMAP2420_ST_EAC (1 << 24)
118#define OMAP24XX_ST_HDQ (1 << 23)
119#define OMAP24XX_ST_I2C2 (1 << 20)
120#define OMAP24XX_ST_I2C1 (1 << 19)
121#define OMAP24XX_ST_MCBSP2 (1 << 16)
122#define OMAP24XX_ST_MCBSP1 (1 << 15)
123#define OMAP24XX_ST_DSS (1 << 0)
124
125/* CM_IDLEST2_CORE */
126#define OMAP2430_ST_MCBSP5 (1 << 5)
127#define OMAP2430_ST_MCBSP4 (1 << 4)
128#define OMAP2430_ST_MCBSP3 (1 << 3)
129#define OMAP24XX_ST_SSI (1 << 1)
130
131/* CM_IDLEST3_CORE */
132/* 2430 only */
133#define OMAP2430_ST_SDRC (1 << 2)
134
135/* CM_IDLEST4_CORE */
136#define OMAP24XX_ST_PKA (1 << 4)
137#define OMAP24XX_ST_AES (1 << 3)
138#define OMAP24XX_ST_RNG (1 << 2)
139#define OMAP24XX_ST_SHA (1 << 1)
140#define OMAP24XX_ST_DES (1 << 0)
141
142/* CM_AUTOIDLE1_CORE */
143#define OMAP24XX_AUTO_CAM (1 << 31)
144#define OMAP24XX_AUTO_MAILBOXES (1 << 30)
145#define OMAP24XX_AUTO_WDT4 (1 << 29)
146#define OMAP2420_AUTO_WDT3 (1 << 28)
147#define OMAP24XX_AUTO_MSPRO (1 << 27)
148#define OMAP2420_AUTO_MMC (1 << 26)
149#define OMAP24XX_AUTO_FAC (1 << 25)
150#define OMAP2420_AUTO_EAC (1 << 24)
151#define OMAP24XX_AUTO_HDQ (1 << 23)
152#define OMAP24XX_AUTO_UART2 (1 << 22)
153#define OMAP24XX_AUTO_UART1 (1 << 21)
154#define OMAP24XX_AUTO_I2C2 (1 << 20)
155#define OMAP24XX_AUTO_I2C1 (1 << 19)
156#define OMAP24XX_AUTO_MCSPI2 (1 << 18)
157#define OMAP24XX_AUTO_MCSPI1 (1 << 17)
158#define OMAP24XX_AUTO_MCBSP2 (1 << 16)
159#define OMAP24XX_AUTO_MCBSP1 (1 << 15)
160#define OMAP24XX_AUTO_GPT12 (1 << 14)
161#define OMAP24XX_AUTO_GPT11 (1 << 13)
162#define OMAP24XX_AUTO_GPT10 (1 << 12)
163#define OMAP24XX_AUTO_GPT9 (1 << 11)
164#define OMAP24XX_AUTO_GPT8 (1 << 10)
165#define OMAP24XX_AUTO_GPT7 (1 << 9)
166#define OMAP24XX_AUTO_GPT6 (1 << 8)
167#define OMAP24XX_AUTO_GPT5 (1 << 7)
168#define OMAP24XX_AUTO_GPT4 (1 << 6)
169#define OMAP24XX_AUTO_GPT3 (1 << 5)
170#define OMAP24XX_AUTO_GPT2 (1 << 4)
171#define OMAP2420_AUTO_VLYNQ (1 << 3)
172#define OMAP24XX_AUTO_DSS (1 << 0)
173
174/* CM_AUTOIDLE2_CORE */
175#define OMAP2430_AUTO_MDM_INTC (1 << 11)
176#define OMAP2430_AUTO_GPIO5 (1 << 10)
177#define OMAP2430_AUTO_MCSPI3 (1 << 9)
178#define OMAP2430_AUTO_MMCHS2 (1 << 8)
179#define OMAP2430_AUTO_MMCHS1 (1 << 7)
180#define OMAP2430_AUTO_USBHS (1 << 6)
181#define OMAP2430_AUTO_MCBSP5 (1 << 5)
182#define OMAP2430_AUTO_MCBSP4 (1 << 4)
183#define OMAP2430_AUTO_MCBSP3 (1 << 3)
184#define OMAP24XX_AUTO_UART3 (1 << 2)
185#define OMAP24XX_AUTO_SSI (1 << 1)
186#define OMAP24XX_AUTO_USB (1 << 0)
187
188/* CM_AUTOIDLE3_CORE */
189#define OMAP24XX_AUTO_SDRC (1 << 2)
190#define OMAP24XX_AUTO_GPMC (1 << 1)
191#define OMAP24XX_AUTO_SDMA (1 << 0)
192
193/* CM_AUTOIDLE4_CORE */
194#define OMAP24XX_AUTO_PKA (1 << 4)
195#define OMAP24XX_AUTO_AES (1 << 3)
196#define OMAP24XX_AUTO_RNG (1 << 2)
197#define OMAP24XX_AUTO_SHA (1 << 1)
198#define OMAP24XX_AUTO_DES (1 << 0)
199
200/* CM_CLKSEL1_CORE */
201#define OMAP24XX_CLKSEL_USB_SHIFT 25
202#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
203#define OMAP24XX_CLKSEL_SSI_SHIFT 20
204#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
205#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
206#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
207#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
208#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
209#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
210#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
211#define OMAP24XX_CLKSEL_L4_SHIFT 5
212#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
213#define OMAP24XX_CLKSEL_L3_SHIFT 0
214#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
215
216/* CM_CLKSEL2_CORE */
217#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
218#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
219#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
220#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
221#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
222#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
223#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
224#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
225#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
226#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
227#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
228#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
229#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
230#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
231#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
232#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
233#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
234#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
235#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
236#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
237#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
238#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
239
240/* CM_CLKSTCTRL_CORE */
241#define OMAP24XX_AUTOSTATE_DSS (1 << 2)
242#define OMAP24XX_AUTOSTATE_L4 (1 << 1)
243#define OMAP24XX_AUTOSTATE_L3 (1 << 0)
244
245/* CM_FCLKEN_GFX */
246#define OMAP24XX_EN_3D_SHIFT 2
247#define OMAP24XX_EN_3D (1 << 2)
248#define OMAP24XX_EN_2D_SHIFT 1
249#define OMAP24XX_EN_2D (1 << 1)
250
251/* CM_ICLKEN_GFX specific bits */
252
253/* CM_IDLEST_GFX specific bits */
254
255/* CM_CLKSEL_GFX specific bits */
256
257/* CM_CLKSTCTRL_GFX */
258#define OMAP24XX_AUTOSTATE_GFX (1 << 0)
259
260/* CM_FCLKEN_WKUP specific bits */
261
262/* CM_ICLKEN_WKUP specific bits */
263#define OMAP2430_EN_ICR_SHIFT 6
264#define OMAP2430_EN_ICR (1 << 6)
265#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
266#define OMAP24XX_EN_OMAPCTRL (1 << 5)
267#define OMAP24XX_EN_WDT1_SHIFT 4
268#define OMAP24XX_EN_WDT1 (1 << 4)
269#define OMAP24XX_EN_32KSYNC_SHIFT 1
270#define OMAP24XX_EN_32KSYNC (1 << 1)
271
272/* CM_IDLEST_WKUP specific bits */
273#define OMAP2430_ST_ICR (1 << 6)
274#define OMAP24XX_ST_OMAPCTRL (1 << 5)
275#define OMAP24XX_ST_WDT1 (1 << 4)
276#define OMAP24XX_ST_MPU_WDT (1 << 3)
277#define OMAP24XX_ST_32KSYNC (1 << 1)
278
279/* CM_AUTOIDLE_WKUP */
280#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
281#define OMAP24XX_AUTO_WDT1 (1 << 4)
282#define OMAP24XX_AUTO_MPU_WDT (1 << 3)
283#define OMAP24XX_AUTO_GPIOS (1 << 2)
284#define OMAP24XX_AUTO_32KSYNC (1 << 1)
285#define OMAP24XX_AUTO_GPT1 (1 << 0)
286
287/* CM_CLKSEL_WKUP */
288#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
289#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
290
291/* CM_CLKEN_PLL */
292#define OMAP24XX_EN_54M_PLL_SHIFT 6
293#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
294#define OMAP24XX_EN_96M_PLL_SHIFT 2
295#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
296#define OMAP24XX_EN_DPLL_SHIFT 0
297#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
298
299/* CM_IDLEST_CKGEN */
300#define OMAP24XX_ST_54M_APLL (1 << 9)
301#define OMAP24XX_ST_96M_APLL (1 << 8)
302#define OMAP24XX_ST_54M_CLK (1 << 6)
303#define OMAP24XX_ST_12M_CLK (1 << 5)
304#define OMAP24XX_ST_48M_CLK (1 << 4)
305#define OMAP24XX_ST_96M_CLK (1 << 2)
306#define OMAP24XX_ST_CORE_CLK_SHIFT 0
307#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
308
309/* CM_AUTOIDLE_PLL */
310#define OMAP24XX_AUTO_54M_SHIFT 6
311#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
312#define OMAP24XX_AUTO_96M_SHIFT 2
313#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
314#define OMAP24XX_AUTO_DPLL_SHIFT 0
315#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
316
317/* CM_CLKSEL1_PLL */
318#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
319#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
320#define OMAP24XX_APLLS_CLKIN_SHIFT 23
321#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
322#define OMAP24XX_DPLL_MULT_SHIFT 12
323#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
324#define OMAP24XX_DPLL_DIV_SHIFT 8
325#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
326#define OMAP24XX_54M_SOURCE_SHIFT 5
327#define OMAP24XX_54M_SOURCE (1 << 5)
328#define OMAP2430_96M_SOURCE_SHIFT 4
329#define OMAP2430_96M_SOURCE (1 << 4)
330#define OMAP24XX_48M_SOURCE_SHIFT 3
331#define OMAP24XX_48M_SOURCE (1 << 3)
332#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
333#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
334
335/* CM_CLKSEL2_PLL */
336#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
337#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
338
339/* CM_FCLKEN_DSP */
340#define OMAP2420_EN_IVA_COP_SHIFT 10
341#define OMAP2420_EN_IVA_COP (1 << 10)
342#define OMAP2420_EN_IVA_MPU_SHIFT 8
343#define OMAP2420_EN_IVA_MPU (1 << 8)
344#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
345#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
346
347/* CM_ICLKEN_DSP */
348#define OMAP2420_EN_DSP_IPI_SHIFT 1
349#define OMAP2420_EN_DSP_IPI (1 << 1)
350
351/* CM_IDLEST_DSP */
352#define OMAP2420_ST_IVA (1 << 8)
353#define OMAP2420_ST_IPI (1 << 1)
354#define OMAP24XX_ST_DSP (1 << 0)
355
356/* CM_AUTOIDLE_DSP */
357#define OMAP2420_AUTO_DSP_IPI (1 << 1)
358
359/* CM_CLKSEL_DSP */
360#define OMAP2420_SYNC_IVA (1 << 13)
361#define OMAP2420_CLKSEL_IVA_SHIFT 8
362#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
363#define OMAP24XX_SYNC_DSP (1 << 7)
364#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
365#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
366#define OMAP24XX_CLKSEL_DSP_SHIFT 0
367#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
368
369/* CM_CLKSTCTRL_DSP */
370#define OMAP2420_AUTOSTATE_IVA (1 << 8)
371#define OMAP24XX_AUTOSTATE_DSP (1 << 0)
372
373/* CM_FCLKEN_MDM */
374/* 2430 only */
375#define OMAP2430_EN_OSC_SHIFT 1
376#define OMAP2430_EN_OSC (1 << 1)
377
378/* CM_ICLKEN_MDM */
379/* 2430 only */
380#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
381#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
382
383/* CM_IDLEST_MDM specific bits */
384/* 2430 only */
385
386/* CM_AUTOIDLE_MDM */
387/* 2430 only */
388#define OMAP2430_AUTO_OSC (1 << 1)
389#define OMAP2430_AUTO_MDM (1 << 0)
390
391/* CM_CLKSEL_MDM */
392/* 2430 only */
393#define OMAP2430_SYNC_MDM (1 << 4)
394#define OMAP2430_CLKSEL_MDM_SHIFT 0
395#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
396
397/* CM_CLKSTCTRL_MDM */
398/* 2430 only */
399#define OMAP2430_AUTOSTATE_MDM (1 << 0)
400
401#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
new file mode 100644
index 00000000000..9249129a5f4
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -0,0 +1,673 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
3
4/*
5 * OMAP3430 Clock Management register bits
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "cm.h"
18
19/* Bits shared between registers */
20
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
23#define OMAP3430ES2_EN_MMC3_SHIFT 30
24#define OMAP3430_EN_MSPRO (1 << 23)
25#define OMAP3430_EN_MSPRO_SHIFT 23
26#define OMAP3430_EN_HDQ (1 << 22)
27#define OMAP3430_EN_HDQ_SHIFT 22
28#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
29#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
30#define OMAP3430ES1_EN_D2D (1 << 3)
31#define OMAP3430ES1_EN_D2D_SHIFT 3
32#define OMAP3430_EN_SSI (1 << 0)
33#define OMAP3430_EN_SSI_SHIFT 0
34
35/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
36#define OMAP3430ES2_EN_USBTLL_SHIFT 2
37#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
38
39/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40#define OMAP3430_EN_WDT2 (1 << 5)
41#define OMAP3430_EN_WDT2_SHIFT 5
42
43/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44#define OMAP3430_EN_CAM (1 << 0)
45#define OMAP3430_EN_CAM_SHIFT 0
46
47/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48#define OMAP3430_EN_WDT3 (1 << 12)
49#define OMAP3430_EN_WDT3_SHIFT 12
50
51/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52#define OMAP3430_OVERRIDE_ENABLE (1 << 19)
53
54
55/* Bits specific to each register */
56
57/* CM_FCLKEN_IVA2 */
58#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
59
60/* CM_CLKEN_PLL_IVA2 */
61#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
62#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
63#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
64#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
65#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
66#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
67#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
68#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
69
70/* CM_IDLEST_IVA2 */
71#define OMAP3430_ST_IVA2 (1 << 0)
72
73/* CM_IDLEST_PLL_IVA2 */
74#define OMAP3430_ST_IVA2_CLK (1 << 0)
75
76/* CM_AUTOIDLE_PLL_IVA2 */
77#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
78#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
79
80/* CM_CLKSEL1_PLL_IVA2 */
81#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
82#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
83#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
84#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
85#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
86#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
87
88/* CM_CLKSEL2_PLL_IVA2 */
89#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
90#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
91
92/* CM_CLKSTCTRL_IVA2 */
93#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
94#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
95
96/* CM_CLKSTST_IVA2 */
97#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
98
99/* CM_REVISION specific bits */
100
101/* CM_SYSCONFIG specific bits */
102
103/* CM_CLKEN_PLL_MPU */
104#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
105#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
106#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
107#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
108#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
109#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
110#define OMAP3430_EN_MPU_DPLL_SHIFT 0
111#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
112
113/* CM_IDLEST_MPU */
114#define OMAP3430_ST_MPU (1 << 0)
115
116/* CM_IDLEST_PLL_MPU */
117#define OMAP3430_ST_MPU_CLK (1 << 0)
118#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
119
120/* CM_IDLEST_PLL_MPU */
121#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
122
123/* CM_AUTOIDLE_PLL_MPU */
124#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
125#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
126
127/* CM_CLKSEL1_PLL_MPU */
128#define OMAP3430_MPU_CLK_SRC_SHIFT 19
129#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
130#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
131#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
132#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
133#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
134
135/* CM_CLKSEL2_PLL_MPU */
136#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
137#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
138
139/* CM_CLKSTCTRL_MPU */
140#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
141#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
142
143/* CM_CLKSTST_MPU */
144#define OMAP3430_CLKACTIVITY_MPU (1 << 0)
145
146/* CM_FCLKEN1_CORE specific bits */
147
148/* CM_ICLKEN1_CORE specific bits */
149#define OMAP3430_EN_ICR (1 << 29)
150#define OMAP3430_EN_ICR_SHIFT 29
151#define OMAP3430_EN_AES2 (1 << 28)
152#define OMAP3430_EN_AES2_SHIFT 28
153#define OMAP3430_EN_SHA12 (1 << 27)
154#define OMAP3430_EN_SHA12_SHIFT 27
155#define OMAP3430_EN_DES2 (1 << 26)
156#define OMAP3430_EN_DES2_SHIFT 26
157#define OMAP3430ES1_EN_FAC (1 << 8)
158#define OMAP3430ES1_EN_FAC_SHIFT 8
159#define OMAP3430_EN_MAILBOXES (1 << 7)
160#define OMAP3430_EN_MAILBOXES_SHIFT 7
161#define OMAP3430_EN_OMAPCTRL (1 << 6)
162#define OMAP3430_EN_OMAPCTRL_SHIFT 6
163#define OMAP3430_EN_SDRC (1 << 1)
164#define OMAP3430_EN_SDRC_SHIFT 1
165
166/* CM_ICLKEN2_CORE */
167#define OMAP3430_EN_PKA (1 << 4)
168#define OMAP3430_EN_PKA_SHIFT 4
169#define OMAP3430_EN_AES1 (1 << 3)
170#define OMAP3430_EN_AES1_SHIFT 3
171#define OMAP3430_EN_RNG (1 << 2)
172#define OMAP3430_EN_RNG_SHIFT 2
173#define OMAP3430_EN_SHA11 (1 << 1)
174#define OMAP3430_EN_SHA11_SHIFT 1
175#define OMAP3430_EN_DES1 (1 << 0)
176#define OMAP3430_EN_DES1_SHIFT 0
177
178/* CM_FCLKEN3_CORE specific bits */
179#define OMAP3430ES2_EN_TS_SHIFT 1
180#define OMAP3430ES2_EN_TS_MASK (1 << 1)
181#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
182#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
183
184/* CM_IDLEST1_CORE specific bits */
185#define OMAP3430_ST_ICR (1 << 29)
186#define OMAP3430_ST_AES2 (1 << 28)
187#define OMAP3430_ST_SHA12 (1 << 27)
188#define OMAP3430_ST_DES2 (1 << 26)
189#define OMAP3430_ST_MSPRO (1 << 23)
190#define OMAP3430_ST_HDQ (1 << 22)
191#define OMAP3430ES1_ST_FAC (1 << 8)
192#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
193#define OMAP3430_ST_OMAPCTRL (1 << 6)
194#define OMAP3430_ST_SDMA (1 << 2)
195#define OMAP3430_ST_SDRC (1 << 1)
196#define OMAP3430_ST_SSI (1 << 0)
197
198/* CM_IDLEST2_CORE */
199#define OMAP3430_ST_PKA (1 << 4)
200#define OMAP3430_ST_AES1 (1 << 3)
201#define OMAP3430_ST_RNG (1 << 2)
202#define OMAP3430_ST_SHA11 (1 << 1)
203#define OMAP3430_ST_DES1 (1 << 0)
204
205/* CM_IDLEST3_CORE */
206#define OMAP3430ES2_ST_USBTLL_SHIFT 2
207#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
208
209/* CM_AUTOIDLE1_CORE */
210#define OMAP3430_AUTO_AES2 (1 << 28)
211#define OMAP3430_AUTO_AES2_SHIFT 28
212#define OMAP3430_AUTO_SHA12 (1 << 27)
213#define OMAP3430_AUTO_SHA12_SHIFT 27
214#define OMAP3430_AUTO_DES2 (1 << 26)
215#define OMAP3430_AUTO_DES2_SHIFT 26
216#define OMAP3430_AUTO_MMC2 (1 << 25)
217#define OMAP3430_AUTO_MMC2_SHIFT 25
218#define OMAP3430_AUTO_MMC1 (1 << 24)
219#define OMAP3430_AUTO_MMC1_SHIFT 24
220#define OMAP3430_AUTO_MSPRO (1 << 23)
221#define OMAP3430_AUTO_MSPRO_SHIFT 23
222#define OMAP3430_AUTO_HDQ (1 << 22)
223#define OMAP3430_AUTO_HDQ_SHIFT 22
224#define OMAP3430_AUTO_MCSPI4 (1 << 21)
225#define OMAP3430_AUTO_MCSPI4_SHIFT 21
226#define OMAP3430_AUTO_MCSPI3 (1 << 20)
227#define OMAP3430_AUTO_MCSPI3_SHIFT 20
228#define OMAP3430_AUTO_MCSPI2 (1 << 19)
229#define OMAP3430_AUTO_MCSPI2_SHIFT 19
230#define OMAP3430_AUTO_MCSPI1 (1 << 18)
231#define OMAP3430_AUTO_MCSPI1_SHIFT 18
232#define OMAP3430_AUTO_I2C3 (1 << 17)
233#define OMAP3430_AUTO_I2C3_SHIFT 17
234#define OMAP3430_AUTO_I2C2 (1 << 16)
235#define OMAP3430_AUTO_I2C2_SHIFT 16
236#define OMAP3430_AUTO_I2C1 (1 << 15)
237#define OMAP3430_AUTO_I2C1_SHIFT 15
238#define OMAP3430_AUTO_UART2 (1 << 14)
239#define OMAP3430_AUTO_UART2_SHIFT 14
240#define OMAP3430_AUTO_UART1 (1 << 13)
241#define OMAP3430_AUTO_UART1_SHIFT 13
242#define OMAP3430_AUTO_GPT11 (1 << 12)
243#define OMAP3430_AUTO_GPT11_SHIFT 12
244#define OMAP3430_AUTO_GPT10 (1 << 11)
245#define OMAP3430_AUTO_GPT10_SHIFT 11
246#define OMAP3430_AUTO_MCBSP5 (1 << 10)
247#define OMAP3430_AUTO_MCBSP5_SHIFT 10
248#define OMAP3430_AUTO_MCBSP1 (1 << 9)
249#define OMAP3430_AUTO_MCBSP1_SHIFT 9
250#define OMAP3430ES1_AUTO_FAC (1 << 8)
251#define OMAP3430ES1_AUTO_FAC_SHIFT 8
252#define OMAP3430_AUTO_MAILBOXES (1 << 7)
253#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
254#define OMAP3430_AUTO_OMAPCTRL (1 << 6)
255#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
256#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
257#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
258#define OMAP3430_AUTO_HSOTGUSB (1 << 4)
259#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
260#define OMAP3430ES1_AUTO_D2D (1 << 3)
261#define OMAP3430ES1_AUTO_D2D_SHIFT 3
262#define OMAP3430_AUTO_SSI (1 << 0)
263#define OMAP3430_AUTO_SSI_SHIFT 0
264
265/* CM_AUTOIDLE2_CORE */
266#define OMAP3430_AUTO_PKA (1 << 4)
267#define OMAP3430_AUTO_PKA_SHIFT 4
268#define OMAP3430_AUTO_AES1 (1 << 3)
269#define OMAP3430_AUTO_AES1_SHIFT 3
270#define OMAP3430_AUTO_RNG (1 << 2)
271#define OMAP3430_AUTO_RNG_SHIFT 2
272#define OMAP3430_AUTO_SHA11 (1 << 1)
273#define OMAP3430_AUTO_SHA11_SHIFT 1
274#define OMAP3430_AUTO_DES1 (1 << 0)
275#define OMAP3430_AUTO_DES1_SHIFT 0
276
277/* CM_AUTOIDLE3_CORE */
278#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
279#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
280
281/* CM_CLKSEL_CORE */
282#define OMAP3430_CLKSEL_SSI_SHIFT 8
283#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
284#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
285#define OMAP3430_CLKSEL_GPT11_SHIFT 7
286#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
287#define OMAP3430_CLKSEL_GPT10_SHIFT 6
288#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
289#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
290#define OMAP3430_CLKSEL_L4_SHIFT 2
291#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
292#define OMAP3430_CLKSEL_L3_SHIFT 0
293#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
294
295/* CM_CLKSTCTRL_CORE */
296#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
297#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
298#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
299#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
300#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
301#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
302
303/* CM_CLKSTST_CORE */
304#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
305#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
306#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
307
308/* CM_FCLKEN_GFX */
309#define OMAP3430ES1_EN_3D (1 << 2)
310#define OMAP3430ES1_EN_3D_SHIFT 2
311#define OMAP3430ES1_EN_2D (1 << 1)
312#define OMAP3430ES1_EN_2D_SHIFT 1
313
314/* CM_ICLKEN_GFX specific bits */
315
316/* CM_IDLEST_GFX specific bits */
317
318/* CM_CLKSEL_GFX specific bits */
319
320/* CM_SLEEPDEP_GFX specific bits */
321
322/* CM_CLKSTCTRL_GFX */
323#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
324#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
325
326/* CM_CLKSTST_GFX */
327#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
328
329/* CM_FCLKEN_SGX */
330#define OMAP3430ES2_EN_SGX_SHIFT 1
331#define OMAP3430ES2_EN_SGX_MASK (1 << 1)
332
333/* CM_CLKSEL_SGX */
334#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
335#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
336
337/* CM_FCLKEN_WKUP specific bits */
338#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
339
340/* CM_ICLKEN_WKUP specific bits */
341#define OMAP3430_EN_WDT1 (1 << 4)
342#define OMAP3430_EN_WDT1_SHIFT 4
343#define OMAP3430_EN_32KSYNC (1 << 2)
344#define OMAP3430_EN_32KSYNC_SHIFT 2
345
346/* CM_IDLEST_WKUP specific bits */
347#define OMAP3430_ST_WDT2 (1 << 5)
348#define OMAP3430_ST_WDT1 (1 << 4)
349#define OMAP3430_ST_32KSYNC (1 << 2)
350
351/* CM_AUTOIDLE_WKUP */
352#define OMAP3430_AUTO_WDT2 (1 << 5)
353#define OMAP3430_AUTO_WDT2_SHIFT 5
354#define OMAP3430_AUTO_WDT1 (1 << 4)
355#define OMAP3430_AUTO_WDT1_SHIFT 4
356#define OMAP3430_AUTO_GPIO1 (1 << 3)
357#define OMAP3430_AUTO_GPIO1_SHIFT 3
358#define OMAP3430_AUTO_32KSYNC (1 << 2)
359#define OMAP3430_AUTO_32KSYNC_SHIFT 2
360#define OMAP3430_AUTO_GPT12 (1 << 1)
361#define OMAP3430_AUTO_GPT12_SHIFT 1
362#define OMAP3430_AUTO_GPT1 (1 << 0)
363#define OMAP3430_AUTO_GPT1_SHIFT 0
364
365/* CM_CLKSEL_WKUP */
366#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
367#define OMAP3430_CLKSEL_RM_SHIFT 1
368#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
369#define OMAP3430_CLKSEL_GPT1_SHIFT 0
370#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
371
372/* CM_CLKEN_PLL */
373#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
374#define OMAP3430_PWRDN_CAM_SHIFT 30
375#define OMAP3430_PWRDN_DSS1_SHIFT 29
376#define OMAP3430_PWRDN_TV_SHIFT 28
377#define OMAP3430_PWRDN_96M_SHIFT 27
378#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
379#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
380#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
381#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
382#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
383#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
384#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
385#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
386#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
387#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
388#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
389#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
390#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
391#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
392#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
393#define OMAP3430_EN_CORE_DPLL_SHIFT 0
394#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
395
396/* CM_CLKEN2_PLL */
397#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
398#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
399#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
400#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
401#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
402#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
403#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
404
405/* CM_IDLEST_CKGEN */
406#define OMAP3430_ST_54M_CLK (1 << 5)
407#define OMAP3430_ST_12M_CLK (1 << 4)
408#define OMAP3430_ST_48M_CLK (1 << 3)
409#define OMAP3430_ST_96M_CLK (1 << 2)
410#define OMAP3430_ST_PERIPH_CLK (1 << 1)
411#define OMAP3430_ST_CORE_CLK (1 << 0)
412
413/* CM_IDLEST2_CKGEN */
414#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
415#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
416#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
417#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
418
419/* CM_AUTOIDLE_PLL */
420#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
421#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
422#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
423#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
424
425/* CM_CLKSEL1_PLL */
426/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
427#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
428#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
429#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
430#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
431#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
432#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
433#define OMAP3430_SOURCE_54M (1 << 5)
434#define OMAP3430_SOURCE_48M (1 << 3)
435
436/* CM_CLKSEL2_PLL */
437#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
438#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
439#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
440#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
441
442/* CM_CLKSEL3_PLL */
443#define OMAP3430_DIV_96M_SHIFT 0
444#define OMAP3430_DIV_96M_MASK (0x1f << 0)
445
446/* CM_CLKSEL4_PLL */
447#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
448#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
449#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
450#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
451
452/* CM_CLKSEL5_PLL */
453#define OMAP3430ES2_DIV_120M_SHIFT 0
454#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
455
456/* CM_CLKOUT_CTRL */
457#define OMAP3430_CLKOUT2_EN_SHIFT 7
458#define OMAP3430_CLKOUT2_EN (1 << 7)
459#define OMAP3430_CLKOUT2_DIV_SHIFT 3
460#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
461#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
462#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
463
464/* CM_FCLKEN_DSS */
465#define OMAP3430_EN_TV (1 << 2)
466#define OMAP3430_EN_TV_SHIFT 2
467#define OMAP3430_EN_DSS2 (1 << 1)
468#define OMAP3430_EN_DSS2_SHIFT 1
469#define OMAP3430_EN_DSS1 (1 << 0)
470#define OMAP3430_EN_DSS1_SHIFT 0
471
472/* CM_ICLKEN_DSS */
473#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
474#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
475
476/* CM_IDLEST_DSS */
477#define OMAP3430_ST_DSS (1 << 0)
478
479/* CM_AUTOIDLE_DSS */
480#define OMAP3430_AUTO_DSS (1 << 0)
481#define OMAP3430_AUTO_DSS_SHIFT 0
482
483/* CM_CLKSEL_DSS */
484#define OMAP3430_CLKSEL_TV_SHIFT 8
485#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
486#define OMAP3430_CLKSEL_DSS1_SHIFT 0
487#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
488
489/* CM_SLEEPDEP_DSS specific bits */
490
491/* CM_CLKSTCTRL_DSS */
492#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
493#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
494
495/* CM_CLKSTST_DSS */
496#define OMAP3430_CLKACTIVITY_DSS (1 << 0)
497
498/* CM_FCLKEN_CAM specific bits */
499
500/* CM_ICLKEN_CAM specific bits */
501
502/* CM_IDLEST_CAM */
503#define OMAP3430_ST_CAM (1 << 0)
504
505/* CM_AUTOIDLE_CAM */
506#define OMAP3430_AUTO_CAM (1 << 0)
507#define OMAP3430_AUTO_CAM_SHIFT 0
508
509/* CM_CLKSEL_CAM */
510#define OMAP3430_CLKSEL_CAM_SHIFT 0
511#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
512
513/* CM_SLEEPDEP_CAM specific bits */
514
515/* CM_CLKSTCTRL_CAM */
516#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
517#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
518
519/* CM_CLKSTST_CAM */
520#define OMAP3430_CLKACTIVITY_CAM (1 << 0)
521
522/* CM_FCLKEN_PER specific bits */
523
524/* CM_ICLKEN_PER specific bits */
525
526/* CM_IDLEST_PER */
527#define OMAP3430_ST_WDT3 (1 << 12)
528#define OMAP3430_ST_MCBSP4 (1 << 2)
529#define OMAP3430_ST_MCBSP3 (1 << 1)
530#define OMAP3430_ST_MCBSP2 (1 << 0)
531
532/* CM_AUTOIDLE_PER */
533#define OMAP3430_AUTO_GPIO6 (1 << 17)
534#define OMAP3430_AUTO_GPIO6_SHIFT 17
535#define OMAP3430_AUTO_GPIO5 (1 << 16)
536#define OMAP3430_AUTO_GPIO5_SHIFT 16
537#define OMAP3430_AUTO_GPIO4 (1 << 15)
538#define OMAP3430_AUTO_GPIO4_SHIFT 15
539#define OMAP3430_AUTO_GPIO3 (1 << 14)
540#define OMAP3430_AUTO_GPIO3_SHIFT 14
541#define OMAP3430_AUTO_GPIO2 (1 << 13)
542#define OMAP3430_AUTO_GPIO2_SHIFT 13
543#define OMAP3430_AUTO_WDT3 (1 << 12)
544#define OMAP3430_AUTO_WDT3_SHIFT 12
545#define OMAP3430_AUTO_UART3 (1 << 11)
546#define OMAP3430_AUTO_UART3_SHIFT 11
547#define OMAP3430_AUTO_GPT9 (1 << 10)
548#define OMAP3430_AUTO_GPT9_SHIFT 10
549#define OMAP3430_AUTO_GPT8 (1 << 9)
550#define OMAP3430_AUTO_GPT8_SHIFT 9
551#define OMAP3430_AUTO_GPT7 (1 << 8)
552#define OMAP3430_AUTO_GPT7_SHIFT 8
553#define OMAP3430_AUTO_GPT6 (1 << 7)
554#define OMAP3430_AUTO_GPT6_SHIFT 7
555#define OMAP3430_AUTO_GPT5 (1 << 6)
556#define OMAP3430_AUTO_GPT5_SHIFT 6
557#define OMAP3430_AUTO_GPT4 (1 << 5)
558#define OMAP3430_AUTO_GPT4_SHIFT 5
559#define OMAP3430_AUTO_GPT3 (1 << 4)
560#define OMAP3430_AUTO_GPT3_SHIFT 4
561#define OMAP3430_AUTO_GPT2 (1 << 3)
562#define OMAP3430_AUTO_GPT2_SHIFT 3
563#define OMAP3430_AUTO_MCBSP4 (1 << 2)
564#define OMAP3430_AUTO_MCBSP4_SHIFT 2
565#define OMAP3430_AUTO_MCBSP3 (1 << 1)
566#define OMAP3430_AUTO_MCBSP3_SHIFT 1
567#define OMAP3430_AUTO_MCBSP2 (1 << 0)
568#define OMAP3430_AUTO_MCBSP2_SHIFT 0
569
570/* CM_CLKSEL_PER */
571#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
572#define OMAP3430_CLKSEL_GPT9_SHIFT 7
573#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
574#define OMAP3430_CLKSEL_GPT8_SHIFT 6
575#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
576#define OMAP3430_CLKSEL_GPT7_SHIFT 5
577#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
578#define OMAP3430_CLKSEL_GPT6_SHIFT 4
579#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
580#define OMAP3430_CLKSEL_GPT5_SHIFT 3
581#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
582#define OMAP3430_CLKSEL_GPT4_SHIFT 2
583#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
584#define OMAP3430_CLKSEL_GPT3_SHIFT 1
585#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
586#define OMAP3430_CLKSEL_GPT2_SHIFT 0
587
588/* CM_SLEEPDEP_PER specific bits */
589#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
590
591/* CM_CLKSTCTRL_PER */
592#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
593#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
594
595/* CM_CLKSTST_PER */
596#define OMAP3430_CLKACTIVITY_PER (1 << 0)
597
598/* CM_CLKSEL1_EMU */
599#define OMAP3430_DIV_DPLL4_SHIFT 24
600#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
601#define OMAP3430_DIV_DPLL3_SHIFT 16
602#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
603#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
604#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
605#define OMAP3430_CLKSEL_PCLK_SHIFT 8
606#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
607#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
608#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
609#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
610#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
611#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
612#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
613#define OMAP3430_MUX_CTRL_SHIFT 0
614#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
615
616/* CM_CLKSTCTRL_EMU */
617#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
618#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
619
620/* CM_CLKSTST_EMU */
621#define OMAP3430_CLKACTIVITY_EMU (1 << 0)
622
623/* CM_CLKSEL2_EMU specific bits */
624#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
625#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
626#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
627#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
628
629/* CM_CLKSEL3_EMU specific bits */
630#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
631#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
632#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
633#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
634
635/* CM_POLCTRL */
636#define OMAP3430_CLKOUT2_POL (1 << 0)
637
638/* CM_IDLEST_NEON */
639#define OMAP3430_ST_NEON (1 << 0)
640
641/* CM_CLKSTCTRL_NEON */
642#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
643#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
644
645/* CM_FCLKEN_USBHOST */
646#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
647#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
648#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
649#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
650
651/* CM_ICLKEN_USBHOST */
652#define OMAP3430ES2_EN_USBHOST_SHIFT 0
653#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
654
655/* CM_IDLEST_USBHOST */
656
657/* CM_AUTOIDLE_USBHOST */
658#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
659#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
660
661/* CM_SLEEPDEP_USBHOST */
662#define OMAP3430ES2_EN_MPU_SHIFT 1
663#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
664#define OMAP3430ES2_EN_IVA2_SHIFT 2
665#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
666
667/* CM_CLKSTCTRL_USBHOST */
668#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
669#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
670
671
672
673#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
new file mode 100644
index 00000000000..8489f3029fe
--- /dev/null
+++ b/arch/arm/mach-omap2/cm.h
@@ -0,0 +1,124 @@
1#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
2#define __ARCH_ASM_MACH_OMAP2_CM_H
3
4/*
5 * OMAP2/3 Clock Management (CM) register definitions
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prcm-common.h"
18
19#ifndef __ASSEMBLER__
20#define OMAP_CM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
22#else
23#define OMAP2420_CM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
25#define OMAP2430_CM_REGADDR(module, reg) \
26 IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
27#define OMAP34XX_CM_REGADDR(module, reg) \
28 IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
29#endif
30
31/*
32 * Architecture-specific global CM registers
33 * Use cm_{read,write}_reg() with these registers.
34 * These registers appear once per CM module.
35 */
36
37#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000)
38#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
39#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
40
41#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
42
43/*
44 * Module specific CM registers from CM_BASE + domain offset
45 * Use cm_{read,write}_mod_reg() with these registers.
46 * These register offsets generally appear in more than one PRCM submodule.
47 */
48
49/* Common between 24xx and 34xx */
50
51#define CM_FCLKEN 0x0000
52#define CM_FCLKEN1 CM_FCLKEN
53#define CM_CLKEN CM_FCLKEN
54#define CM_ICLKEN 0x0010
55#define CM_ICLKEN1 CM_ICLKEN
56#define CM_ICLKEN2 0x0014
57#define CM_ICLKEN3 0x0018
58#define CM_IDLEST 0x0020
59#define CM_IDLEST1 CM_IDLEST
60#define CM_IDLEST2 0x0024
61#define CM_AUTOIDLE 0x0030
62#define CM_AUTOIDLE1 CM_AUTOIDLE
63#define CM_AUTOIDLE2 0x0034
64#define CM_AUTOIDLE3 0x0038
65#define CM_CLKSEL 0x0040
66#define CM_CLKSEL1 CM_CLKSEL
67#define CM_CLKSEL2 0x0044
68#define CM_CLKSTCTRL 0x0048
69
70
71/* Architecture-specific registers */
72
73#define OMAP24XX_CM_FCLKEN2 0x0004
74#define OMAP24XX_CM_ICLKEN4 0x001c
75#define OMAP24XX_CM_AUTOIDLE4 0x003c
76
77#define OMAP2430_CM_IDLEST3 0x0028
78
79#define OMAP3430_CM_CLKEN_PLL 0x0004
80#define OMAP3430ES2_CM_CLKEN2 0x0004
81#define OMAP3430ES2_CM_FCLKEN3 0x0008
82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
84#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
85#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
86#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
87#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
88#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL
89#define OMAP3430_CM_CLKSTST 0x004c
90#define OMAP3430ES2_CM_CLKSEL4 0x004c
91#define OMAP3430ES2_CM_CLKSEL5 0x0050
92#define OMAP3430_CM_CLKSEL2_EMU 0x0050
93#define OMAP3430_CM_CLKSEL3_EMU 0x0054
94
95
96/* Clock management domain register get/set */
97
98#ifndef __ASSEMBLER__
99static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
100{
101 __raw_writel(val, OMAP_CM_REGADDR(module, idx));
102}
103
104static inline u32 cm_read_mod_reg(s16 module, s16 idx)
105{
106 return __raw_readl(OMAP_CM_REGADDR(module, idx));
107}
108#endif
109
110/* CM register bits shared between 24XX and 3430 */
111
112/* CM_CLKSEL_GFX */
113#define OMAP_CLKSEL_GFX_SHIFT 0
114#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
115
116/* CM_ICLKEN_GFX */
117#define OMAP_EN_GFX_SHIFT 0
118#define OMAP_EN_GFX (1 << 0)
119
120/* CM_IDLEST_GFX */
121#define OMAP_ST_GFX (1 << 0)
122
123
124#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
new file mode 100644
index 00000000000..a5d86a49c21
--- /dev/null
+++ b/arch/arm/mach-omap2/control.c
@@ -0,0 +1,74 @@
1/*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#undef DEBUG
14
15#include <linux/kernel.h>
16
17#include <asm/io.h>
18
19#include <asm/arch/control.h>
20
21static u32 omap2_ctrl_base;
22
23#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
24 + (reg))
25
26void omap_ctrl_base_set(u32 base)
27{
28 omap2_ctrl_base = base;
29}
30
31u32 omap_ctrl_base_get(void)
32{
33 return omap2_ctrl_base;
34}
35
36u8 omap_ctrl_readb(u16 offset)
37{
38 return __raw_readb(OMAP_CTRL_REGADDR(offset));
39}
40
41u16 omap_ctrl_readw(u16 offset)
42{
43 return __raw_readw(OMAP_CTRL_REGADDR(offset));
44}
45
46u32 omap_ctrl_readl(u16 offset)
47{
48 return __raw_readl(OMAP_CTRL_REGADDR(offset));
49}
50
51void omap_ctrl_writeb(u8 val, u16 offset)
52{
53 pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
54 (u32)OMAP_CTRL_REGADDR(offset));
55
56 __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
57}
58
59void omap_ctrl_writew(u16 val, u16 offset)
60{
61 pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
62 (u32)OMAP_CTRL_REGADDR(offset));
63
64 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
65}
66
67void omap_ctrl_writel(u32 val, u16 offset)
68{
69 pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
70 (u32)OMAP_CTRL_REGADDR(offset));
71
72 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
73}
74
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7..02cede295e8 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
69static void __iomem *gpmc_cs_base = 69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; 70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 71
72static struct clk *gpmc_l3_clk; 72static struct clk *gpmc_fck;
73 73
74static void gpmc_write_reg(int idx, u32 val) 74static void gpmc_write_reg(int idx, u32 val)
75{ 75{
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95} 95}
96 96
97/* TODO: Add support for gpmc_fck to clock framework and use it */
98unsigned long gpmc_get_fclk_period(void) 97unsigned long gpmc_get_fclk_period(void)
99{ 98{
100 /* In picoseconds */ 99 /* In picoseconds */
101 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); 100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
102} 101}
103 102
104unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 103unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
398{ 397{
399 u32 l; 398 u32 l;
400 399
401 gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); 400 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
402 BUG_ON(IS_ERR(gpmc_l3_clk)); 401 if (IS_ERR(gpmc_fck))
402 WARN_ON(1);
403 else
404 clk_enable(gpmc_fck);
403 405
404 l = gpmc_read_reg(GPMC_REVISION); 406 l = gpmc_read_reg(GPMC_REVISION);
405 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 3e5d8cd4ea4..12479081881 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -27,11 +27,16 @@
27#include <asm/arch/clock.h> 27#include <asm/arch/clock.h>
28#include <asm/arch/sram.h> 28#include <asm/arch/sram.h>
29 29
30#include "prcm-regs.h" 30#include "prm.h"
31
31#include "memory.h" 32#include "memory.h"
33#include "sdrc.h"
32 34
35unsigned long omap2_sdrc_base;
36unsigned long omap2_sms_base;
33 37
34static struct memory_timings mem_timings; 38static struct memory_timings mem_timings;
39static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
35 40
36u32 omap2_memory_get_slow_dll_ctrl(void) 41u32 omap2_memory_get_slow_dll_ctrl(void)
37{ 42{
@@ -48,12 +53,60 @@ u32 omap2_memory_get_type(void)
48 return mem_timings.m_type; 53 return mem_timings.m_type;
49} 54}
50 55
56/*
57 * Check the DLL lock state, and return tue if running in unlock mode.
58 * This is needed to compensate for the shifted DLL value in unlock mode.
59 */
60u32 omap2_dll_force_needed(void)
61{
62 /* dlla and dllb are a set */
63 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
64
65 if ((dll_state & (1 << 2)) == (1 << 2))
66 return 1;
67 else
68 return 0;
69}
70
71/*
72 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
73 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
74 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
75 */
76u32 omap2_reprogram_sdrc(u32 level, u32 force)
77{
78 u32 dll_ctrl, m_type;
79 u32 prev = curr_perf_level;
80 unsigned long flags;
81
82 if ((curr_perf_level == level) && !force)
83 return prev;
84
85 if (level == CORE_CLK_SRC_DPLL) {
86 dll_ctrl = omap2_memory_get_slow_dll_ctrl();
87 } else if (level == CORE_CLK_SRC_DPLL_X2) {
88 dll_ctrl = omap2_memory_get_fast_dll_ctrl();
89 } else {
90 return prev;
91 }
92
93 m_type = omap2_memory_get_type();
94
95 local_irq_save(flags);
96 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
97 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
98 curr_perf_level = level;
99 local_irq_restore(flags);
100
101 return prev;
102}
103
51void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 104void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
52{ 105{
53 unsigned long dll_cnt; 106 unsigned long dll_cnt;
54 u32 fast_dll = 0; 107 u32 fast_dll = 0;
55 108
56 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ 109 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
57 110
58 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 111 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
59 * In the case of 2422, its ok to use CS1 instead of CS0. 112 * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +126,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
73 mem_timings.dll_mode = M_LOCK; 126 mem_timings.dll_mode = M_LOCK;
74 127
75 if (mem_timings.base_cs == 0) { 128 if (mem_timings.base_cs == 0) {
76 fast_dll = SDRC_DLLA_CTRL; 129 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
77 dll_cnt = SDRC_DLLA_STATUS & 0xff00; 130 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
78 } else { 131 } else {
79 fast_dll = SDRC_DLLB_CTRL; 132 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
80 dll_cnt = SDRC_DLLB_STATUS & 0xff00; 133 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
81 } 134 }
82 if (force_lock_to_unlock_mode) { 135 if (force_lock_to_unlock_mode) {
83 fast_dll &= ~0xff00; 136 fast_dll &= ~0xff00;
@@ -106,14 +159,13 @@ void __init omap2_init_memory(void)
106{ 159{
107 u32 l; 160 u32 l;
108 161
109 l = SMS_SYSCONFIG; 162 l = sms_read_reg(SMS_SYSCONFIG);
110 l &= ~(0x3 << 3); 163 l &= ~(0x3 << 3);
111 l |= (0x2 << 3); 164 l |= (0x2 << 3);
112 SMS_SYSCONFIG = l; 165 sms_write_reg(l, SMS_SYSCONFIG);
113 166
114 l = SDRC_SYSCONFIG; 167 l = sdrc_read_reg(SDRC_SYSCONFIG);
115 l &= ~(0x3 << 3); 168 l &= ~(0x3 << 3);
116 l |= (0x2 << 3); 169 l |= (0x2 << 3);
117 SDRC_SYSCONFIG = l; 170 sdrc_write_reg(l, SDRC_SYSCONFIG);
118
119} 171}
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea83a0..9a280b50a89 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
32extern u32 omap2_memory_get_slow_dll_ctrl(void); 32extern u32 omap2_memory_get_slow_dll_ctrl(void);
33extern u32 omap2_memory_get_fast_dll_ctrl(void); 33extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void); 34extern u32 omap2_memory_get_type(void);
35u32 omap2_dll_force_needed(void);
36u32 omap2_reprogram_sdrc(u32 level, u32 force);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 05750975d74..930770012a7 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,11 +1,12 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/mux.c 2 * linux/arch/arm/mach-omap2/mux.c
3 * 3 *
4 * OMAP1 pin multiplexing configurations 4 * OMAP2 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2003 - 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
7 * 8 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 9 * Written by Tony Lindgren
9 * 10 *
10 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
@@ -28,13 +29,17 @@
28#include <asm/io.h> 29#include <asm/io.h>
29#include <linux/spinlock.h> 30#include <linux/spinlock.h>
30 31
32#include <asm/arch/control.h>
31#include <asm/arch/mux.h> 33#include <asm/arch/mux.h>
32 34
33#ifdef CONFIG_OMAP_MUX 35#ifdef CONFIG_OMAP_MUX
34 36
37static struct omap_mux_cfg arch_mux_cfg;
38
35/* NOTE: See mux.h for the enumeration */ 39/* NOTE: See mux.h for the enumeration */
36 40
37struct pin_config __initdata_or_module omap24xx_pins[] = { 41#ifdef CONFIG_ARCH_OMAP24XX
42static struct pin_config __initdata_or_module omap24xx_pins[] = {
38/* 43/*
39 * description mux mux pull pull debug 44 * description mux mux pull pull debug
40 * offset mode ena type 45 * offset mode ena type
@@ -77,7 +82,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
77MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) 82MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
78MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) 83MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
79MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) 84MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
85MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
80MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) 86MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
87MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
88MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
89MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
90MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
81MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) 91MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
82MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) 92MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
83MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) 93MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
@@ -102,9 +112,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
102MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) 112MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
103MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) 113MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
104 114
105/* TSC IRQ */
106MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
107
108/* UART3 */ 115/* UART3 */
109MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) 116MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
110MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) 117MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
@@ -167,12 +174,108 @@ MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
167MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) 174MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
168MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) 175MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
169 176
177/* 2430 USB */
178MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
179MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
180MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
181MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
182MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
183MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
184MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
185MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
186MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
187MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
188MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
189
190/* 2430 HS-USB */
191MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
192MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
193MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
194MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
195MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
196MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
197MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
198MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
199MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
200MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
201MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
202MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
203
204/* 2430 McBSP */
205MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
206MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
207MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
208MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
209MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
210MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
211MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
212MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
170}; 213};
171 214
172int __init omap2_mux_init(void) 215#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
216
217#else
218#define omap24xx_pins NULL
219#define OMAP24XX_PINS_SZ 0
220#endif /* CONFIG_ARCH_OMAP24XX */
221
222#define OMAP24XX_PULL_ENA (1 << 3)
223#define OMAP24XX_PULL_UP (1 << 4)
224
225#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
226void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
173{ 227{
174 omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins)); 228 u16 orig;
229 u8 warn = 0, debug = 0;
230
231 orig = omap_ctrl_readb(cfg->mux_reg);
232
233#ifdef CONFIG_OMAP_MUX_DEBUG
234 debug = cfg->debug;
235#endif
236 warn = (orig != reg);
237 if (debug || warn)
238 printk(KERN_WARNING
239 "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
240 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
241 orig, reg);
242}
243#else
244#define omap2_cfg_debug(x, y) do {} while (0)
245#endif
246
247#ifdef CONFIG_ARCH_OMAP24XX
248int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
249{
250 static DEFINE_SPINLOCK(mux_spin_lock);
251 unsigned long flags;
252 u8 reg = 0;
253
254 spin_lock_irqsave(&mux_spin_lock, flags);
255 reg |= cfg->mask & 0x7;
256 if (cfg->pull_val)
257 reg |= OMAP24XX_PULL_ENA;
258 if (cfg->pu_pd_val)
259 reg |= OMAP24XX_PULL_UP;
260 omap2_cfg_debug(cfg, reg);
261 omap_ctrl_writeb(reg, cfg->mux_reg);
262 spin_unlock_irqrestore(&mux_spin_lock, flags);
263
175 return 0; 264 return 0;
176} 265}
266#else
267#define omap24xx_cfg_reg 0
268#endif
269
270int __init omap2_mux_init(void)
271{
272 if (cpu_is_omap24xx()) {
273 arch_mux_cfg.pins = omap24xx_pins;
274 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
275 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
276 }
277
278 return omap_mux_register(&arch_mux_cfg);
279}
177 280
178#endif 281#endif
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
deleted file mode 100644
index 2494091a078..00000000000
--- a/arch/arm/mach-omap2/pm-domain.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/pm-domain.c
3 *
4 * Power domain functions for OMAP2
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Some code based on earlier OMAP2 sample PM code
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/clk.h>
21
22#include <asm/io.h>
23
24#include "prcm-regs.h"
25
26/* Power domain offsets */
27#define PM_MPU_OFFSET 0x100
28#define PM_CORE_OFFSET 0x200
29#define PM_GFX_OFFSET 0x300
30#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
31#define PM_PLL_OFFSET 0x500 /* Autoidle only */
32#define PM_DSP_OFFSET 0x800
33#define PM_MDM_OFFSET 0xc00
34
35/* Power domain wake-up dependency control register */
36#define PM_WKDEP_OFFSET 0xc8
37#define EN_MDM (1 << 5)
38#define EN_WKUP (1 << 4)
39#define EN_GFX (1 << 3)
40#define EN_DSP (1 << 2)
41#define EN_MPU (1 << 1)
42#define EN_CORE (1 << 0)
43
44/* Core power domain state transition control register */
45#define PM_PWSTCTRL_OFFSET 0xe0
46#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
47#define MEM4RETSTATE (1 << 6)
48#define MEM3RETSTATE (1 << 5)
49#define MEM2RETSTATE (1 << 4)
50#define MEM1RETSTATE (1 << 3)
51#define LOGICRETSTATE (1 << 2) /* Logic is retained */
52#define POWERSTATE_OFF 0x3
53#define POWERSTATE_RETENTION 0x1
54#define POWERSTATE_ON 0x0
55
56/* Power domain state register */
57#define PM_PWSTST_OFFSET 0xe4
58
59/* Hardware supervised state transition control register */
60#define CM_CLKSTCTRL_OFFSET 0x48
61#define AUTOSTAT_MPU (1 << 0) /* MPU */
62#define AUTOSTAT_DSS (1 << 2) /* Core */
63#define AUTOSTAT_L4 (1 << 1) /* Core */
64#define AUTOSTAT_L3 (1 << 0) /* Core */
65#define AUTOSTAT_GFX (1 << 0) /* GFX */
66#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
67#define AUTOSTAT_DSP (1 << 0) /* DSP */
68#define AUTOSTAT_MDM (1 << 0) /* MDM */
69
70/* Automatic control of interface clock idling */
71#define CM_AUTOIDLE1_OFFSET 0x30
72#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
73#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
74#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
75#define AUTO_54M(x) (((x) & 0x3) << 6)
76#define AUTO_96M(x) (((x) & 0x3) << 2)
77#define AUTO_DPLL(x) (((x) & 0x3) << 0)
78#define AUTO_STOPPED 0x3
79#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
80#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
81#define AUTO_DISABLED 0x0
82
83/* Voltage control PRCM_VOLTCTRL bits */
84#define AUTO_EXTVOLT (1 << 15)
85#define FORCE_EXTVOLT (1 << 14)
86#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
87#define MEMRETCTRL (1 << 8)
88#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
89#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
90
91#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
92#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
93#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
94
95static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
96{
97 return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
98}
99
100static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
101{
102 prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
103}
104
105static u32 pmdomain_get_powerstate(int domain_offset)
106{
107 return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
108}
109
110static void pmdomain_set_powerstate(u32 state, int domain_offset)
111{
112 prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
113}
114
115static u32 pmdomain_get_clock_autocontrol(int domain_offset)
116{
117 return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
118}
119
120static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
121{
122 prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
123}
124
125static u32 pmdomain_get_clock_autoidle1(int domain_offset)
126{
127 return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
128}
129
130/* Core domain only */
131static u32 pmdomain_get_clock_autoidle2(int domain_offset)
132{
133 return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
134}
135
136/* Core domain only */
137static u32 pmdomain_get_clock_autoidle3(int domain_offset)
138{
139 return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
140}
141
142/* Core domain only */
143static u32 pmdomain_get_clock_autoidle4(int domain_offset)
144{
145 return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
146}
147
148static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
149{
150 prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
151}
152
153/* Core domain only */
154static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
155{
156 prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
157}
158
159/* Core domain only */
160static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
161{
162 prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
163}
164
165/* Core domain only */
166static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
167{
168 prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
169}
170
171/*
172 * Configures power management domains to idle clocks automatically.
173 */
174void pmdomain_set_autoidle(void)
175{
176 u32 val;
177
178 /* Set PLL auto stop for 54M, 96M & DPLL */
179 pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
180 AUTO_96M(AUTO_STOPPED) |
181 AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
182
183 /* External clock input control
184 * REVISIT: Should this be in clock framework?
185 */
186 PRCM_CLKSRC_CTRL |= (0x3 << 3);
187
188 /* Configure number of 32KHz clock cycles for sys_clk */
189 PRCM_CLKSSETUP = 0x00ff;
190
191 /* Configure automatic voltage transition */
192 PRCM_VOLTSETUP = 0;
193 val = PRCM_VOLTCTRL;
194 val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
195 val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
196 PRCM_VOLTCTRL = val;
197
198 /* Disable emulation tools functional clock */
199 PRCM_CLKEMUL_CTRL = 0x0;
200
201 /* Set core memory retention state */
202 val = pmdomain_get_powerstate(PM_CORE_OFFSET);
203 if (cpu_is_omap2420()) {
204 val &= ~(0x7 << 3);
205 val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
206 } else {
207 val &= ~(0xf << 3);
208 val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
209 MEM1RETSTATE);
210 }
211 pmdomain_set_powerstate(val, PM_CORE_OFFSET);
212
213 /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
214 val = SMS_SYSCONFIG;
215 val &= ~(0x3 << 3);
216 val |= (0x2 << 3) | (1 << 0);
217 SMS_SYSCONFIG |= val;
218
219 val = SDRC_SYSCONFIG;
220 val &= ~(0x3 << 3);
221 val |= (0x2 << 3);
222 SDRC_SYSCONFIG = val;
223
224 /* Configure L3 interface for smart idle.
225 * REVISIT: Enable autoidle bit0 ?
226 */
227 val = GPMC_SYSCONFIG;
228 val &= ~(0x3 << 3);
229 val |= (0x2 << 3) | (1 << 0);
230 GPMC_SYSCONFIG = val;
231
232 pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
233 PM_MPU_OFFSET);
234 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
235 if (!cpu_is_omap2420())
236 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
237
238 /* Assume suspend function has saved the state for DSP and GFX */
239 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
240 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
241
242#if 0
243 /* REVISIT: Internal USB needs special handling */
244 force_standby_usb();
245 if (cpu_is_omap2430())
246 force_hsmmc();
247 sdram_self_refresh_on_idle_req(1);
248#endif
249
250 /* Enable clock auto control for all domains.
251 * Note that CORE domain includes also DSS, L4 & L3.
252 */
253 pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
254 pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
255 pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
256 PM_CORE_OFFSET);
257 if (cpu_is_omap2420())
258 pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
259 PM_DSP_OFFSET);
260 else {
261 pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
262 pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
263 }
264
265 /* Enable clock autoidle for all domains */
266 pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
267 if (cpu_is_omap2420()) {
268 pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
269 pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
270 pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
271 } else {
272 pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
273 pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
274 pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
275 pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
276 }
277 pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
278 pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
279}
280
281/*
282 * Initializes power domains by removing wake-up dependencies and powering
283 * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
284 * must re-enable DSP and GFX when used.
285 */
286void __init pmdomain_init(void)
287{
288 /* Remove all domain wakeup dependencies */
289 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
290 pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
291 pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
292 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
293 if (cpu_is_omap2430())
294 pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
295
296 /* Power down DSP and GFX */
297 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
298 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
299}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index baf7d82b458..aad781dcf1b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
23#include <linux/sysfs.h> 23#include <linux/sysfs.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/clk.h>
26 27
27#include <asm/io.h> 28#include <asm/io.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
@@ -36,8 +37,6 @@
36#include <asm/arch/sram.h> 37#include <asm/arch/sram.h>
37#include <asm/arch/pm.h> 38#include <asm/arch/pm.h>
38 39
39#include "prcm-regs.h"
40
41static struct clk *vclk; 40static struct clk *vclk;
42static void (*omap2_sram_idle)(void); 41static void (*omap2_sram_idle)(void);
43static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); 42static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
@@ -78,251 +77,8 @@ static int omap2_pm_prepare(void)
78 return 0; 77 return 0;
79} 78}
80 79
81#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
82 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
83 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
84
85#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
86
87#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
88 OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
89 OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
90
91#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
92
93static void omap2_pm_debug(char * desc)
94{
95 printk("%s:\n", desc);
96
97 preg(CM_CLKSTCTRL_MPU);
98 preg(CM_CLKSTCTRL_CORE);
99 preg(CM_CLKSTCTRL_GFX);
100 preg(CM_CLKSTCTRL_DSP);
101 preg(CM_CLKSTCTRL_MDM);
102
103 preg(PM_PWSTCTRL_MPU);
104 preg(PM_PWSTCTRL_CORE);
105 preg(PM_PWSTCTRL_GFX);
106 preg(PM_PWSTCTRL_DSP);
107 preg(PM_PWSTCTRL_MDM);
108
109 preg(PM_PWSTST_MPU);
110 preg(PM_PWSTST_CORE);
111 preg(PM_PWSTST_GFX);
112 preg(PM_PWSTST_DSP);
113 preg(PM_PWSTST_MDM);
114
115 preg(CM_AUTOIDLE1_CORE);
116 preg(CM_AUTOIDLE2_CORE);
117 preg(CM_AUTOIDLE3_CORE);
118 preg(CM_AUTOIDLE4_CORE);
119 preg(CM_AUTOIDLE_WKUP);
120 preg(CM_AUTOIDLE_PLL);
121 preg(CM_AUTOIDLE_DSP);
122 preg(CM_AUTOIDLE_MDM);
123
124 preg(CM_ICLKEN1_CORE);
125 preg(CM_ICLKEN2_CORE);
126 preg(CM_ICLKEN3_CORE);
127 preg(CM_ICLKEN4_CORE);
128 preg(CM_ICLKEN_GFX);
129 preg(CM_ICLKEN_WKUP);
130 preg(CM_ICLKEN_DSP);
131 preg(CM_ICLKEN_MDM);
132
133 preg(CM_IDLEST1_CORE);
134 preg(CM_IDLEST2_CORE);
135 preg(CM_IDLEST3_CORE);
136 preg(CM_IDLEST4_CORE);
137 preg(CM_IDLEST_GFX);
138 preg(CM_IDLEST_WKUP);
139 preg(CM_IDLEST_CKGEN);
140 preg(CM_IDLEST_DSP);
141 preg(CM_IDLEST_MDM);
142
143 preg(RM_RSTST_MPU);
144 preg(RM_RSTST_GFX);
145 preg(RM_RSTST_WKUP);
146 preg(RM_RSTST_DSP);
147 preg(RM_RSTST_MDM);
148
149 preg(PM_WKDEP_MPU);
150 preg(PM_WKDEP_CORE);
151 preg(PM_WKDEP_GFX);
152 preg(PM_WKDEP_DSP);
153 preg(PM_WKDEP_MDM);
154
155 preg(CM_FCLKEN_WKUP);
156 preg(CM_ICLKEN_WKUP);
157 preg(CM_IDLEST_WKUP);
158 preg(CM_AUTOIDLE_WKUP);
159 preg(CM_CLKSEL_WKUP);
160
161 preg(PM_WKEN_WKUP);
162 preg(PM_WKST_WKUP);
163}
164
165static inline void omap2_pm_save_registers(void)
166{
167 /* Save interrupt registers */
168 OMAP24XX_SAVE(INTC_MIR0);
169 OMAP24XX_SAVE(INTC_MIR1);
170 OMAP24XX_SAVE(INTC_MIR2);
171
172 /* Save power control registers */
173 OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
174 OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
175 OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
176 OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
177 OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
178
179 /* Save power state registers */
180 OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
181 OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
182 OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
183 OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
184 OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
185
186 /* Save autoidle registers */
187 OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
188 OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
189 OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
190 OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
191 OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
192 OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
193 OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
194 OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
195
196 /* Save idle state registers */
197 OMAP24XX_SAVE(CM_IDLEST1_CORE);
198 OMAP24XX_SAVE(CM_IDLEST2_CORE);
199 OMAP24XX_SAVE(CM_IDLEST3_CORE);
200 OMAP24XX_SAVE(CM_IDLEST4_CORE);
201 OMAP24XX_SAVE(CM_IDLEST_GFX);
202 OMAP24XX_SAVE(CM_IDLEST_WKUP);
203 OMAP24XX_SAVE(CM_IDLEST_CKGEN);
204 OMAP24XX_SAVE(CM_IDLEST_DSP);
205 OMAP24XX_SAVE(CM_IDLEST_MDM);
206
207 /* Save clock registers */
208 OMAP24XX_SAVE(CM_FCLKEN1_CORE);
209 OMAP24XX_SAVE(CM_FCLKEN2_CORE);
210 OMAP24XX_SAVE(CM_ICLKEN1_CORE);
211 OMAP24XX_SAVE(CM_ICLKEN2_CORE);
212 OMAP24XX_SAVE(CM_ICLKEN3_CORE);
213 OMAP24XX_SAVE(CM_ICLKEN4_CORE);
214}
215
216static inline void omap2_pm_restore_registers(void)
217{
218 /* Restore clock state registers */
219 OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
220 OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
221 OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
222 OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
223 OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
224
225 /* Restore power state registers */
226 OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
227 OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
228 OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
229 OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
230 OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
231
232 /* Restore idle state registers */
233 OMAP24XX_RESTORE(CM_IDLEST1_CORE);
234 OMAP24XX_RESTORE(CM_IDLEST2_CORE);
235 OMAP24XX_RESTORE(CM_IDLEST3_CORE);
236 OMAP24XX_RESTORE(CM_IDLEST4_CORE);
237 OMAP24XX_RESTORE(CM_IDLEST_GFX);
238 OMAP24XX_RESTORE(CM_IDLEST_WKUP);
239 OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
240 OMAP24XX_RESTORE(CM_IDLEST_DSP);
241 OMAP24XX_RESTORE(CM_IDLEST_MDM);
242
243 /* Restore autoidle registers */
244 OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
245 OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
246 OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
247 OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
248 OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
249 OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
250 OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
251 OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
252
253 /* Restore clock registers */
254 OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
255 OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
256 OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
257 OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
258 OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
259 OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
260
261 /* REVISIT: Clear interrupts here */
262
263 /* Restore interrupt registers */
264 OMAP24XX_RESTORE(INTC_MIR0);
265 OMAP24XX_RESTORE(INTC_MIR1);
266 OMAP24XX_RESTORE(INTC_MIR2);
267}
268
269static int omap2_pm_suspend(void) 80static int omap2_pm_suspend(void)
270{ 81{
271 int processor_type = 0;
272
273 /* REVISIT: 0x21 or 0x26? */
274 if (cpu_is_omap2420())
275 processor_type = 0x21;
276
277 if (!processor_type)
278 return -ENOTSUPP;
279
280 local_irq_disable();
281 local_fiq_disable();
282
283 omap2_pm_save_registers();
284
285 /* Disable interrupts except for the wake events */
286 INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
287 INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
288 INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
289
290 pmdomain_set_autoidle();
291
292 /* Clear old wake-up events */
293 PM_WKST1_CORE = 0;
294 PM_WKST2_CORE = 0;
295 PM_WKST_WKUP = 0;
296
297 /* Enable wake-up events */
298 PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
299 PM_WKEN2_CORE = (1 << 2); /* UART3 */
300 PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
301
302 /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
303 * in the SRAM suspend code */
304 CM_FCLKEN1_CORE = 0;
305 CM_FCLKEN2_CORE = 0;
306 CM_ICLKEN1_CORE = 0;
307 CM_ICLKEN3_CORE = 0;
308 CM_ICLKEN4_CORE = 0;
309
310 omap2_pm_debug("Status before suspend");
311
312 /* Must wait for serial buffers to clear */
313 mdelay(200);
314
315 /* Jump to SRAM suspend code
316 * REVISIT: When is this SDRC_DLLB_CTRL?
317 */
318 omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
319
320 /* Back from sleep */
321 omap2_pm_restore_registers();
322
323 local_fiq_enable();
324 local_irq_enable();
325
326 return 0; 82 return 0;
327} 83}
328 84
@@ -357,30 +113,6 @@ static struct platform_suspend_ops omap_pm_ops = {
357 113
358int __init omap2_pm_init(void) 114int __init omap2_pm_init(void)
359{ 115{
360 printk("Power Management for TI OMAP.\n");
361
362 vclk = clk_get(NULL, "virt_prcm_set");
363 if (IS_ERR(vclk)) {
364 printk(KERN_ERR "Could not get PM vclk\n");
365 return -ENODEV;
366 }
367
368 /*
369 * We copy the assembler sleep/wakeup routines to SRAM.
370 * These routines need to be in SRAM as that's the only
371 * memory the MPU can see when it wakes up.
372 */
373 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
374 omap24xx_idle_loop_suspend_sz);
375
376 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
377 omap24xx_cpu_suspend_sz);
378
379 suspend_set_ops(&omap_pm_ops);
380 pm_idle = omap2_pm_idle;
381
382 pmdomain_init();
383
384 return 0; 116 return 0;
385} 117}
386 118
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
new file mode 100644
index 00000000000..cacb34086e3
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -0,0 +1,317 @@
1#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
3
4/*
5 * OMAP2/3 PRCM base and module definitions
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17
18/* Module offsets from both CM_BASE & PRM_BASE */
19
20/*
21 * Offsets that are the same on 24xx and 34xx
22 *
23 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
24 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
25 */
26#define OCP_MOD 0x000
27#define MPU_MOD 0x100
28#define CORE_MOD 0x200
29#define GFX_MOD 0x300
30#define WKUP_MOD 0x400
31#define PLL_MOD 0x500
32
33
34/* Chip-specific module offsets */
35#define OMAP24XX_DSP_MOD 0x800
36
37#define OMAP2430_MDM_MOD 0xc00
38
39/* IVA2 module is < base on 3430 */
40#define OMAP3430_IVA2_MOD -0x800
41#define OMAP3430ES2_SGX_MOD GFX_MOD
42#define OMAP3430_CCR_MOD PLL_MOD
43#define OMAP3430_DSS_MOD 0x600
44#define OMAP3430_CAM_MOD 0x700
45#define OMAP3430_PER_MOD 0x800
46#define OMAP3430_EMU_MOD 0x900
47#define OMAP3430_GR_MOD 0xa00
48#define OMAP3430_NEON_MOD 0xb00
49#define OMAP3430ES2_USBHOST_MOD 0xc00
50
51
52/* 24XX register bits shared between CM & PRM registers */
53
54/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
55#define OMAP2420_EN_MMC_SHIFT 26
56#define OMAP2420_EN_MMC (1 << 26)
57#define OMAP24XX_EN_UART2_SHIFT 22
58#define OMAP24XX_EN_UART2 (1 << 22)
59#define OMAP24XX_EN_UART1_SHIFT 21
60#define OMAP24XX_EN_UART1 (1 << 21)
61#define OMAP24XX_EN_MCSPI2_SHIFT 18
62#define OMAP24XX_EN_MCSPI2 (1 << 18)
63#define OMAP24XX_EN_MCSPI1_SHIFT 17
64#define OMAP24XX_EN_MCSPI1 (1 << 17)
65#define OMAP24XX_EN_MCBSP2_SHIFT 16
66#define OMAP24XX_EN_MCBSP2 (1 << 16)
67#define OMAP24XX_EN_MCBSP1_SHIFT 15
68#define OMAP24XX_EN_MCBSP1 (1 << 15)
69#define OMAP24XX_EN_GPT12_SHIFT 14
70#define OMAP24XX_EN_GPT12 (1 << 14)
71#define OMAP24XX_EN_GPT11_SHIFT 13
72#define OMAP24XX_EN_GPT11 (1 << 13)
73#define OMAP24XX_EN_GPT10_SHIFT 12
74#define OMAP24XX_EN_GPT10 (1 << 12)
75#define OMAP24XX_EN_GPT9_SHIFT 11
76#define OMAP24XX_EN_GPT9 (1 << 11)
77#define OMAP24XX_EN_GPT8_SHIFT 10
78#define OMAP24XX_EN_GPT8 (1 << 10)
79#define OMAP24XX_EN_GPT7_SHIFT 9
80#define OMAP24XX_EN_GPT7 (1 << 9)
81#define OMAP24XX_EN_GPT6_SHIFT 8
82#define OMAP24XX_EN_GPT6 (1 << 8)
83#define OMAP24XX_EN_GPT5_SHIFT 7
84#define OMAP24XX_EN_GPT5 (1 << 7)
85#define OMAP24XX_EN_GPT4_SHIFT 6
86#define OMAP24XX_EN_GPT4 (1 << 6)
87#define OMAP24XX_EN_GPT3_SHIFT 5
88#define OMAP24XX_EN_GPT3 (1 << 5)
89#define OMAP24XX_EN_GPT2_SHIFT 4
90#define OMAP24XX_EN_GPT2 (1 << 4)
91#define OMAP2420_EN_VLYNQ_SHIFT 3
92#define OMAP2420_EN_VLYNQ (1 << 3)
93
94/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
95#define OMAP2430_EN_GPIO5_SHIFT 10
96#define OMAP2430_EN_GPIO5 (1 << 10)
97#define OMAP2430_EN_MCSPI3_SHIFT 9
98#define OMAP2430_EN_MCSPI3 (1 << 9)
99#define OMAP2430_EN_MMCHS2_SHIFT 8
100#define OMAP2430_EN_MMCHS2 (1 << 8)
101#define OMAP2430_EN_MMCHS1_SHIFT 7
102#define OMAP2430_EN_MMCHS1 (1 << 7)
103#define OMAP24XX_EN_UART3_SHIFT 2
104#define OMAP24XX_EN_UART3 (1 << 2)
105#define OMAP24XX_EN_USB_SHIFT 0
106#define OMAP24XX_EN_USB (1 << 0)
107
108/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
109#define OMAP2430_EN_MDM_INTC_SHIFT 11
110#define OMAP2430_EN_MDM_INTC (1 << 11)
111#define OMAP2430_EN_USBHS_SHIFT 6
112#define OMAP2430_EN_USBHS (1 << 6)
113
114/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
115#define OMAP2420_ST_MMC (1 << 26)
116#define OMAP24XX_ST_UART2 (1 << 22)
117#define OMAP24XX_ST_UART1 (1 << 21)
118#define OMAP24XX_ST_MCSPI2 (1 << 18)
119#define OMAP24XX_ST_MCSPI1 (1 << 17)
120#define OMAP24XX_ST_GPT12 (1 << 14)
121#define OMAP24XX_ST_GPT11 (1 << 13)
122#define OMAP24XX_ST_GPT10 (1 << 12)
123#define OMAP24XX_ST_GPT9 (1 << 11)
124#define OMAP24XX_ST_GPT8 (1 << 10)
125#define OMAP24XX_ST_GPT7 (1 << 9)
126#define OMAP24XX_ST_GPT6 (1 << 8)
127#define OMAP24XX_ST_GPT5 (1 << 7)
128#define OMAP24XX_ST_GPT4 (1 << 6)
129#define OMAP24XX_ST_GPT3 (1 << 5)
130#define OMAP24XX_ST_GPT2 (1 << 4)
131#define OMAP2420_ST_VLYNQ (1 << 3)
132
133/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
134#define OMAP2430_ST_MDM_INTC (1 << 11)
135#define OMAP2430_ST_GPIO5 (1 << 10)
136#define OMAP2430_ST_MCSPI3 (1 << 9)
137#define OMAP2430_ST_MMCHS2 (1 << 8)
138#define OMAP2430_ST_MMCHS1 (1 << 7)
139#define OMAP2430_ST_USBHS (1 << 6)
140#define OMAP24XX_ST_UART3 (1 << 2)
141#define OMAP24XX_ST_USB (1 << 0)
142
143/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
144#define OMAP24XX_EN_GPIOS_SHIFT 2
145#define OMAP24XX_EN_GPIOS (1 << 2)
146#define OMAP24XX_EN_GPT1_SHIFT 0
147#define OMAP24XX_EN_GPT1 (1 << 0)
148
149/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
150#define OMAP24XX_ST_GPIOS (1 << 2)
151#define OMAP24XX_ST_GPT1 (1 << 0)
152
153/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
154#define OMAP2430_ST_MDM (1 << 0)
155
156
157/* 3430 register bits shared between CM & PRM registers */
158
159/* CM_REVISION, PRM_REVISION shared bits */
160#define OMAP3430_REV_SHIFT 0
161#define OMAP3430_REV_MASK (0xff << 0)
162
163/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
164#define OMAP3430_AUTOIDLE (1 << 0)
165
166/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
167#define OMAP3430_EN_MMC2 (1 << 25)
168#define OMAP3430_EN_MMC2_SHIFT 25
169#define OMAP3430_EN_MMC1 (1 << 24)
170#define OMAP3430_EN_MMC1_SHIFT 24
171#define OMAP3430_EN_MCSPI4 (1 << 21)
172#define OMAP3430_EN_MCSPI4_SHIFT 21
173#define OMAP3430_EN_MCSPI3 (1 << 20)
174#define OMAP3430_EN_MCSPI3_SHIFT 20
175#define OMAP3430_EN_MCSPI2 (1 << 19)
176#define OMAP3430_EN_MCSPI2_SHIFT 19
177#define OMAP3430_EN_MCSPI1 (1 << 18)
178#define OMAP3430_EN_MCSPI1_SHIFT 18
179#define OMAP3430_EN_I2C3 (1 << 17)
180#define OMAP3430_EN_I2C3_SHIFT 17
181#define OMAP3430_EN_I2C2 (1 << 16)
182#define OMAP3430_EN_I2C2_SHIFT 16
183#define OMAP3430_EN_I2C1 (1 << 15)
184#define OMAP3430_EN_I2C1_SHIFT 15
185#define OMAP3430_EN_UART2 (1 << 14)
186#define OMAP3430_EN_UART2_SHIFT 14
187#define OMAP3430_EN_UART1 (1 << 13)
188#define OMAP3430_EN_UART1_SHIFT 13
189#define OMAP3430_EN_GPT11 (1 << 12)
190#define OMAP3430_EN_GPT11_SHIFT 12
191#define OMAP3430_EN_GPT10 (1 << 11)
192#define OMAP3430_EN_GPT10_SHIFT 11
193#define OMAP3430_EN_MCBSP5 (1 << 10)
194#define OMAP3430_EN_MCBSP5_SHIFT 10
195#define OMAP3430_EN_MCBSP1 (1 << 9)
196#define OMAP3430_EN_MCBSP1_SHIFT 9
197#define OMAP3430_EN_FSHOSTUSB (1 << 5)
198#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
199#define OMAP3430_EN_D2D (1 << 3)
200#define OMAP3430_EN_D2D_SHIFT 3
201
202/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
203#define OMAP3430_EN_HSOTGUSB (1 << 4)
204#define OMAP3430_EN_HSOTGUSB_SHIFT 4
205
206/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
207#define OMAP3430_ST_MMC2 (1 << 25)
208#define OMAP3430_ST_MMC1 (1 << 24)
209#define OMAP3430_ST_MCSPI4 (1 << 21)
210#define OMAP3430_ST_MCSPI3 (1 << 20)
211#define OMAP3430_ST_MCSPI2 (1 << 19)
212#define OMAP3430_ST_MCSPI1 (1 << 18)
213#define OMAP3430_ST_I2C3 (1 << 17)
214#define OMAP3430_ST_I2C2 (1 << 16)
215#define OMAP3430_ST_I2C1 (1 << 15)
216#define OMAP3430_ST_UART2 (1 << 14)
217#define OMAP3430_ST_UART1 (1 << 13)
218#define OMAP3430_ST_GPT11 (1 << 12)
219#define OMAP3430_ST_GPT10 (1 << 11)
220#define OMAP3430_ST_MCBSP5 (1 << 10)
221#define OMAP3430_ST_MCBSP1 (1 << 9)
222#define OMAP3430_ST_FSHOSTUSB (1 << 5)
223#define OMAP3430_ST_HSOTGUSB (1 << 4)
224#define OMAP3430_ST_D2D (1 << 3)
225
226/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
227#define OMAP3430_EN_GPIO1 (1 << 3)
228#define OMAP3430_EN_GPIO1_SHIFT 3
229#define OMAP3430_EN_GPT1 (1 << 0)
230#define OMAP3430_EN_GPT1_SHIFT 0
231
232/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
233#define OMAP3430_EN_SR2 (1 << 7)
234#define OMAP3430_EN_SR2_SHIFT 7
235#define OMAP3430_EN_SR1 (1 << 6)
236#define OMAP3430_EN_SR1_SHIFT 6
237
238/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
239#define OMAP3430_EN_GPT12 (1 << 1)
240#define OMAP3430_EN_GPT12_SHIFT 1
241
242/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
243#define OMAP3430_ST_SR2 (1 << 7)
244#define OMAP3430_ST_SR1 (1 << 6)
245#define OMAP3430_ST_GPIO1 (1 << 3)
246#define OMAP3430_ST_GPT12 (1 << 1)
247#define OMAP3430_ST_GPT1 (1 << 0)
248
249/*
250 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
251 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
252 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
253 */
254#define OMAP3430_EN_MPU (1 << 1)
255#define OMAP3430_EN_MPU_SHIFT 1
256
257/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
258#define OMAP3430_EN_GPIO6 (1 << 17)
259#define OMAP3430_EN_GPIO6_SHIFT 17
260#define OMAP3430_EN_GPIO5 (1 << 16)
261#define OMAP3430_EN_GPIO5_SHIFT 16
262#define OMAP3430_EN_GPIO4 (1 << 15)
263#define OMAP3430_EN_GPIO4_SHIFT 15
264#define OMAP3430_EN_GPIO3 (1 << 14)
265#define OMAP3430_EN_GPIO3_SHIFT 14
266#define OMAP3430_EN_GPIO2 (1 << 13)
267#define OMAP3430_EN_GPIO2_SHIFT 13
268#define OMAP3430_EN_UART3 (1 << 11)
269#define OMAP3430_EN_UART3_SHIFT 11
270#define OMAP3430_EN_GPT9 (1 << 10)
271#define OMAP3430_EN_GPT9_SHIFT 10
272#define OMAP3430_EN_GPT8 (1 << 9)
273#define OMAP3430_EN_GPT8_SHIFT 9
274#define OMAP3430_EN_GPT7 (1 << 8)
275#define OMAP3430_EN_GPT7_SHIFT 8
276#define OMAP3430_EN_GPT6 (1 << 7)
277#define OMAP3430_EN_GPT6_SHIFT 7
278#define OMAP3430_EN_GPT5 (1 << 6)
279#define OMAP3430_EN_GPT5_SHIFT 6
280#define OMAP3430_EN_GPT4 (1 << 5)
281#define OMAP3430_EN_GPT4_SHIFT 5
282#define OMAP3430_EN_GPT3 (1 << 4)
283#define OMAP3430_EN_GPT3_SHIFT 4
284#define OMAP3430_EN_GPT2 (1 << 3)
285#define OMAP3430_EN_GPT2_SHIFT 3
286
287/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
288/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
289 * be ST_* bits instead? */
290#define OMAP3430_EN_MCBSP4 (1 << 2)
291#define OMAP3430_EN_MCBSP4_SHIFT 2
292#define OMAP3430_EN_MCBSP3 (1 << 1)
293#define OMAP3430_EN_MCBSP3_SHIFT 1
294#define OMAP3430_EN_MCBSP2 (1 << 0)
295#define OMAP3430_EN_MCBSP2_SHIFT 0
296
297/* CM_IDLEST_PER, PM_WKST_PER shared bits */
298#define OMAP3430_ST_GPIO6 (1 << 17)
299#define OMAP3430_ST_GPIO5 (1 << 16)
300#define OMAP3430_ST_GPIO4 (1 << 15)
301#define OMAP3430_ST_GPIO3 (1 << 14)
302#define OMAP3430_ST_GPIO2 (1 << 13)
303#define OMAP3430_ST_UART3 (1 << 11)
304#define OMAP3430_ST_GPT9 (1 << 10)
305#define OMAP3430_ST_GPT8 (1 << 9)
306#define OMAP3430_ST_GPT7 (1 << 8)
307#define OMAP3430_ST_GPT6 (1 << 7)
308#define OMAP3430_ST_GPT5 (1 << 6)
309#define OMAP3430_ST_GPT4 (1 << 5)
310#define OMAP3430_ST_GPT3 (1 << 4)
311#define OMAP3430_ST_GPT2 (1 << 3)
312
313/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
314#define OMAP3430_EN_CORE (1 << 0)
315
316#endif
317
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
deleted file mode 100644
index 5e1c4b53ee9..00000000000
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ /dev/null
@@ -1,483 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/prcm-regs.h
3 *
4 * OMAP24XX Power Reset and Clock Management (PRCM) registers
5 *
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
24#define __ARCH_ARM_MACH_OMAP2_PRCM_H
25
26/* SET_PERFORMANCE_LEVEL PARAMETERS */
27#define PRCM_HALF_SPEED 1
28#define PRCM_FULL_SPEED 2
29
30#ifndef __ASSEMBLER__
31
32#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
33
34#define PRCM_REVISION PRCM_REG32(0x000)
35#define PRCM_SYSCONFIG PRCM_REG32(0x010)
36#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
37#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
38#define PRCM_VOLTCTRL PRCM_REG32(0x050)
39#define PRCM_VOLTST PRCM_REG32(0x054)
40#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
41#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
42#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
43#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
44#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
45#define PRCM_VOLTSETUP PRCM_REG32(0x090)
46#define PRCM_CLKSSETUP PRCM_REG32(0x094)
47#define PRCM_POLCTRL PRCM_REG32(0x098)
48
49/* GENERAL PURPOSE */
50#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
51#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
52#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
53#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
54#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
55#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
56#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
57#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
58#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
59#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
60#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
61#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
62#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
63#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
64#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
65#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
66#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
67#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
68#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
69#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
70
71/* MPU */
72#define CM_CLKSEL_MPU PRCM_REG32(0x140)
73#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
74#define RM_RSTST_MPU PRCM_REG32(0x158)
75#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
76#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
77#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
78#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
79#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
80#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
81
82/* CORE */
83#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
84#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
85#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
86#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
87#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
88#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
89#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
90#define CM_IDLEST1_CORE PRCM_REG32(0x220)
91#define CM_IDLEST2_CORE PRCM_REG32(0x224)
92#define CM_IDLEST3_CORE PRCM_REG32(0x228)
93#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
94#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
95#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
96#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
97#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
98#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
99#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
100#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
101#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
102#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
103#define PM_WKST1_CORE PRCM_REG32(0x2B0)
104#define PM_WKST2_CORE PRCM_REG32(0x2B4)
105#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
106#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
107#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
108
109/* GFX */
110#define CM_FCLKEN_GFX PRCM_REG32(0x300)
111#define CM_ICLKEN_GFX PRCM_REG32(0x310)
112#define CM_IDLEST_GFX PRCM_REG32(0x320)
113#define CM_CLKSEL_GFX PRCM_REG32(0x340)
114#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
115#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
116#define RM_RSTST_GFX PRCM_REG32(0x358)
117#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
118#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
119#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
120
121/* WAKE-UP */
122#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
123#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
124#define CM_IDLEST_WKUP PRCM_REG32(0x420)
125#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
126#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
127#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
128#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
129#define RM_RSTST_WKUP PRCM_REG32(0x458)
130#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
131#define PM_WKST_WKUP PRCM_REG32(0x4B0)
132
133/* CLOCKS */
134#define CM_CLKEN_PLL PRCM_REG32(0x500)
135#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
136#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
137#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
138#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
139
140/* DSP */
141#define CM_FCLKEN_DSP PRCM_REG32(0x800)
142#define CM_ICLKEN_DSP PRCM_REG32(0x810)
143#define CM_IDLEST_DSP PRCM_REG32(0x820)
144#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
145#define CM_CLKSEL_DSP PRCM_REG32(0x840)
146#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
147#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
148#define RM_RSTST_DSP PRCM_REG32(0x858)
149#define PM_WKEN_DSP PRCM_REG32(0x8A0)
150#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
151#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
152#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
153#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
154#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
155
156/* IVA */
157#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
158#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
159
160/* Modem on 2430 */
161#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
162#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
163#define CM_IDLEST_MDM PRCM_REG32(0xC20)
164#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
165#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
166#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
167#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
168#define RM_RSTST_MDM PRCM_REG32(0xC58)
169#define PM_WKEN_MDM PRCM_REG32(0xCA0)
170#define PM_WKST_MDM PRCM_REG32(0xCB0)
171#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
172#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
173#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
174
175#define OMAP24XX_L4_IO_BASE 0x48000000
176
177#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
178#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
179
180#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
181#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
182
183/* FIXME: Move these to timer code */
184#define GPT1_BASE (0x48028000)
185#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
186
187/* Misc sysconfig */
188#define DISPC_SYSCONFIG DISP_REG32(0x410)
189#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
190#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
191#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
192#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
193
194#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
195#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
196#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
197#define GPMC_SYSCONFIG GPMC_REG32(0x010)
198#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
199#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
200#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
201#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
202#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
203#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
204#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
205#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
206
207/* rkw - good cannidates for PM_ to start what nm was trying */
208#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
209#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
210#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
211#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
212#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
213#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
214#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
215#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
216#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
217#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
218#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
219
220/* FIXME: Move these to timer code */
221#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
222#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
223#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
224#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
225#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
226#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
227#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
228#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
229#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
230#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
231#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
232#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
233
234/* FIXME: Move these to gpio code */
235#define OMAP24XX_GPIO_BASE 0x48018000
236#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
237
238#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
239#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
240#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
241#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
242
243#if defined(CONFIG_ARCH_OMAP243X)
244#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
245#endif
246
247/* GP TIMER 1 */
248#define GPTIMER1_TISTAT GPT1_REG32(0x014)
249#define GPTIMER1_TISR GPT1_REG32(0x018)
250#define GPTIMER1_TIER GPT1_REG32(0x01C)
251#define GPTIMER1_TWER GPT1_REG32(0x020)
252#define GPTIMER1_TCLR GPT1_REG32(0x024)
253#define GPTIMER1_TCRR GPT1_REG32(0x028)
254#define GPTIMER1_TLDR GPT1_REG32(0x02C)
255#define GPTIMER1_TTGR GPT1_REG32(0x030)
256#define GPTIMER1_TWPS GPT1_REG32(0x034)
257#define GPTIMER1_TMAR GPT1_REG32(0x038)
258#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
259#define GPTIMER1_TSICR GPT1_REG32(0x040)
260#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
261
262/* rkw -- base fix up please... */
263#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
264
265/* SDRC */
266#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
267#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
268#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
269#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
270#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
271#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
272
273/* GPIO 1 */
274#define GPIO1_BASE GPIOX_BASE(1)
275#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
276#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
277#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
278#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
279#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
280#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
281#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
282#define GPIO1_DATAIN GPIO1_REG32(0x038)
283#define GPIO1_OE GPIO1_REG32(0x034)
284#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
285
286/* GPIO2 */
287#define GPIO2_BASE GPIOX_BASE(2)
288#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
289#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
290#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
291#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
292#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
293#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
294#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
295#define GPIO2_DATAIN GPIO2_REG32(0x038)
296#define GPIO2_OE GPIO2_REG32(0x034)
297#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
298#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
299#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
300
301/* GPIO 3 */
302#define GPIO3_BASE GPIOX_BASE(3)
303#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
304#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
305#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
306#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
307#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
308#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
309#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
310#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
311#define GPIO3_DATAIN GPIO3_REG32(0x038)
312#define GPIO3_OE GPIO3_REG32(0x034)
313#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
314#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
315#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
316#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
317#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
318
319/* GPIO 4 */
320#define GPIO4_BASE GPIOX_BASE(4)
321#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
322#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
323#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
324#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
325#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
326#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
327#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
328#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
329#define GPIO4_DATAIN GPIO4_REG32(0x038)
330#define GPIO4_OE GPIO4_REG32(0x034)
331#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
332#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
333#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
334
335#if defined(CONFIG_ARCH_OMAP243X)
336/* GPIO 5 */
337#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
338#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
339#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
340#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
341#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
342#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
343#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
344#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
345#define GPIO5_DATAIN GPIO5_REG32(0x038)
346#define GPIO5_OE GPIO5_REG32(0x034)
347#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
348#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
349#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
350#endif
351
352/* IO CONFIG */
353#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
354#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
355
356#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
357#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
358#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
359#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
360#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
361#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
362#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
363#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
364#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
365#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
366#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
367
368/* CONTROL */
369#define CONTROL_DEVCONF CONTROL_REG32(0x274)
370#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
371
372/* INTERRUPT CONTROLLER */
373#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
374#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
375
376#define INTC1_U_BASE INTC_REG32(0x000)
377#define INTC_MIR0 INTC_REG32(0x084)
378#define INTC_MIR_SET0 INTC_REG32(0x08C)
379#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
380#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
381#define INTC_MIR1 INTC_REG32(0x0A4)
382#define INTC_MIR_SET1 INTC_REG32(0x0AC)
383#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
384#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
385#define INTC_MIR2 INTC_REG32(0x0C4)
386#define INTC_MIR_SET2 INTC_REG32(0x0CC)
387#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
388#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
389#define INTC_SIR_IRQ INTC_REG32(0x040)
390#define INTC_CONTROL INTC_REG32(0x048)
391#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
392#define INTC_ILR30 INTC_REG32(0x178)
393#define INTC_ILR31 INTC_REG32(0x17C)
394#define INTC_ILR32 INTC_REG32(0x180)
395#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
396#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
397
398/* RAM FIREWALL */
399#define RAMFW_BASE (0x68005000)
400#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
401
402#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
403#define RAMFW_READPERM0 RAMFW_REG32(0x050)
404#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
405
406/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
407//#define DEBUG_BOARD_LED_REGISTER 0x04000014
408
409/* GPMC CS0 */
410#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
411#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
412#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
413#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
414#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
415#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
416#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
417
418/* GPMC CS1 */
419#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
420#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
421#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
422#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
423#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
424#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
425#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
426
427/* GPMC CS3 */
428#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
429#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
430#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
431#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
432#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
433#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
434#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
435
436/* DSS */
437#define DSS_CONTROL DISP_REG32(0x040)
438#define DISPC_CONTROL DISP_REG32(0x440)
439#define DISPC_SYSSTATUS DISP_REG32(0x414)
440#define DISPC_IRQSTATUS DISP_REG32(0x418)
441#define DISPC_IRQENABLE DISP_REG32(0x41C)
442#define DISPC_CONFIG DISP_REG32(0x444)
443#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
444#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
445#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
446#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
447#define DISPC_LINE_NUMBER DISP_REG32(0x460)
448#define DISPC_TIMING_H DISP_REG32(0x464)
449#define DISPC_TIMING_V DISP_REG32(0x468)
450#define DISPC_POL_FREQ DISP_REG32(0x46C)
451#define DISPC_DIVISOR DISP_REG32(0x470)
452#define DISPC_SIZE_DIG DISP_REG32(0x478)
453#define DISPC_SIZE_LCD DISP_REG32(0x47C)
454#define DISPC_GFX_BA0 DISP_REG32(0x480)
455#define DISPC_GFX_BA1 DISP_REG32(0x484)
456#define DISPC_GFX_POSITION DISP_REG32(0x488)
457#define DISPC_GFX_SIZE DISP_REG32(0x48C)
458#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
459#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
460#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
461#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
462#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
463#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
464#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
465#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
466#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
467
468/* HSUSB Suspend */
469#define HSUSB_CTRL __REG8(0x480AC001)
470#define USBOTG_POWER __REG32(0x480AC000)
471
472/* HS MMC */
473#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
474#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
475
476#endif /* __ASSEMBLER__ */
477
478#endif
479
480
481
482
483
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 90f530540c6..b12f423b859 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,19 +17,27 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19 19
20#include "prcm-regs.h" 20#include <asm/io.h>
21
22#include "prm.h"
23#include "prm-regbits-24xx.h"
21 24
22extern void omap2_clk_prepare_for_reboot(void); 25extern void omap2_clk_prepare_for_reboot(void);
23 26
24u32 omap_prcm_get_reset_sources(void) 27u32 omap_prcm_get_reset_sources(void)
25{ 28{
26 return RM_RSTST_WKUP & 0x7f; 29 return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
27} 30}
28EXPORT_SYMBOL(omap_prcm_get_reset_sources); 31EXPORT_SYMBOL(omap_prcm_get_reset_sources);
29 32
30/* Resets clock rates and reboots the system. Only called from system.h */ 33/* Resets clock rates and reboots the system. Only called from system.h */
31void omap_prcm_arch_reset(char mode) 34void omap_prcm_arch_reset(char mode)
32{ 35{
36 u32 wkup;
33 omap2_clk_prepare_for_reboot(); 37 omap2_clk_prepare_for_reboot();
34 RM_RSTCTRL_WKUP |= 2; 38
39 if (cpu_is_omap24xx()) {
40 wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
41 prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
42 }
35} 43}
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
new file mode 100644
index 00000000000..c6d17a3378e
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -0,0 +1,279 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
3
4/*
5 * OMAP24XX Power/Reset Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prm.h"
18
19/* Bits shared between registers */
20
21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22#define OMAP24XX_VOLTTRANS_ST (1 << 2)
23#define OMAP24XX_WKUP2_ST (1 << 1)
24#define OMAP24XX_WKUP1_ST (1 << 0)
25
26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27#define OMAP24XX_VOLTTRANS_EN (1 << 2)
28#define OMAP24XX_WKUP2_EN (1 << 1)
29#define OMAP24XX_WKUP1_EN (1 << 0)
30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU (1 << 1)
33#define OMAP24XX_EN_CORE (1 << 0)
34
35/*
36 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
37 * shared bits
38 */
39#define OMAP24XX_MEMONSTATE_SHIFT 10
40#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
41#define OMAP24XX_MEMRETSTATE (1 << 3)
42
43/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
44#define OMAP24XX_FORCESTATE (1 << 18)
45
46/*
47 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
48 * PM_PWSTST_MDM shared bits
49 */
50#define OMAP24XX_CLKACTIVITY (1 << 19)
51
52/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
53#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
54#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
55
56/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
57#define OMAP2430_MEMSTATEST_SHIFT 10
58#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
59
60/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
61#define OMAP24XX_POWERSTATEST_SHIFT 0
62#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
63
64
65/* Bits specific to each register */
66
67/* PRCM_REVISION */
68#define OMAP24XX_REV_SHIFT 0
69#define OMAP24XX_REV_MASK (0xff << 0)
70
71/* PRCM_SYSCONFIG */
72#define OMAP24XX_AUTOIDLE (1 << 0)
73
74/* PRCM_IRQSTATUS_MPU specific bits */
75#define OMAP2430_DPLL_RECAL_ST (1 << 6)
76#define OMAP24XX_TRANSITION_ST (1 << 5)
77#define OMAP24XX_EVGENOFF_ST (1 << 4)
78#define OMAP24XX_EVGENON_ST (1 << 3)
79
80/* PRCM_IRQENABLE_MPU specific bits */
81#define OMAP2430_DPLL_RECAL_EN (1 << 6)
82#define OMAP24XX_TRANSITION_EN (1 << 5)
83#define OMAP24XX_EVGENOFF_EN (1 << 4)
84#define OMAP24XX_EVGENON_EN (1 << 3)
85
86/* PRCM_VOLTCTRL */
87#define OMAP24XX_AUTO_EXTVOLT (1 << 15)
88#define OMAP24XX_FORCE_EXTVOLT (1 << 14)
89#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
90#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
91#define OMAP24XX_MEMRETCTRL (1 << 8)
92#define OMAP24XX_SETRET_LEVEL_SHIFT 6
93#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
94#define OMAP24XX_VOLT_LEVEL_SHIFT 0
95#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
96
97/* PRCM_VOLTST */
98#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
99#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
100
101/* PRCM_CLKSRC_CTRL specific bits */
102
103/* PRCM_CLKOUT_CTRL */
104#define OMAP2420_CLKOUT2_EN_SHIFT 15
105#define OMAP2420_CLKOUT2_EN (1 << 15)
106#define OMAP2420_CLKOUT2_DIV_SHIFT 11
107#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
108#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
109#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
110#define OMAP24XX_CLKOUT_EN_SHIFT 7
111#define OMAP24XX_CLKOUT_EN (1 << 7)
112#define OMAP24XX_CLKOUT_DIV_SHIFT 3
113#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
114#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
115#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
116
117/* PRCM_CLKEMUL_CTRL */
118#define OMAP24XX_EMULATION_EN_SHIFT 0
119#define OMAP24XX_EMULATION_EN (1 << 0)
120
121/* PRCM_CLKCFG_CTRL */
122#define OMAP24XX_VALID_CONFIG (1 << 0)
123
124/* PRCM_CLKCFG_STATUS */
125#define OMAP24XX_CONFIG_STATUS (1 << 0)
126
127/* PRCM_VOLTSETUP specific bits */
128
129/* PRCM_CLKSSETUP specific bits */
130
131/* PRCM_POLCTRL */
132#define OMAP2420_CLKOUT2_POL (1 << 10)
133#define OMAP24XX_CLKOUT_POL (1 << 9)
134#define OMAP24XX_CLKREQ_POL (1 << 8)
135#define OMAP2430_USE_POWEROK (1 << 2)
136#define OMAP2430_POWEROK_POL (1 << 1)
137#define OMAP24XX_EXTVOL_POL (1 << 0)
138
139/* RM_RSTST_MPU specific bits */
140/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
141
142/* PM_WKDEP_MPU specific bits */
143#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5)
144#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2)
145
146/* PM_EVGENCTRL_MPU specific bits */
147
148/* PM_EVEGENONTIM_MPU specific bits */
149
150/* PM_EVEGENOFFTIM_MPU specific bits */
151
152/* PM_PWSTCTRL_MPU specific bits */
153#define OMAP2430_FORCESTATE (1 << 18)
154
155/* PM_PWSTST_MPU specific bits */
156/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
157
158/* PM_WKEN1_CORE specific bits */
159
160/* PM_WKEN2_CORE specific bits */
161
162/* PM_WKST1_CORE specific bits*/
163
164/* PM_WKST2_CORE specific bits */
165
166/* PM_WKDEP_CORE specific bits*/
167#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)
168#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)
169#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)
170
171/* PM_PWSTCTRL_CORE specific bits */
172#define OMAP24XX_MEMORYCHANGE (1 << 20)
173#define OMAP24XX_MEM3ONSTATE_SHIFT 14
174#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
175#define OMAP24XX_MEM2ONSTATE_SHIFT 12
176#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
177#define OMAP24XX_MEM1ONSTATE_SHIFT 10
178#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
179#define OMAP24XX_MEM3RETSTATE (1 << 5)
180#define OMAP24XX_MEM2RETSTATE (1 << 4)
181#define OMAP24XX_MEM1RETSTATE (1 << 3)
182
183/* PM_PWSTST_CORE specific bits */
184#define OMAP24XX_MEM3STATEST_SHIFT 14
185#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
186#define OMAP24XX_MEM2STATEST_SHIFT 12
187#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
188#define OMAP24XX_MEM1STATEST_SHIFT 10
189#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
190
191/* RM_RSTCTRL_GFX */
192#define OMAP24XX_GFX_RST (1 << 0)
193
194/* RM_RSTST_GFX specific bits */
195#define OMAP24XX_GFX_SW_RST (1 << 4)
196
197/* PM_PWSTCTRL_GFX specific bits */
198
199/* PM_WKDEP_GFX specific bits */
200/* 2430 often calls EN_WAKEUP "EN_WKUP" */
201
202/* RM_RSTCTRL_WKUP specific bits */
203
204/* RM_RSTTIME_WKUP specific bits */
205
206/* RM_RSTST_WKUP specific bits */
207/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
208#define OMAP24XX_EXTWMPU_RST (1 << 6)
209#define OMAP24XX_SECU_WD_RST (1 << 5)
210#define OMAP24XX_MPU_WD_RST (1 << 4)
211#define OMAP24XX_SECU_VIOL_RST (1 << 3)
212
213/* PM_WKEN_WKUP specific bits */
214
215/* PM_WKST_WKUP specific bits */
216
217/* RM_RSTCTRL_DSP */
218#define OMAP2420_RST_IVA (1 << 8)
219#define OMAP24XX_RST2_DSP (1 << 1)
220#define OMAP24XX_RST1_DSP (1 << 0)
221
222/* RM_RSTST_DSP specific bits */
223/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
224#define OMAP2420_IVA_SW_RST (1 << 8)
225#define OMAP24XX_DSP_SW_RST2 (1 << 5)
226#define OMAP24XX_DSP_SW_RST1 (1 << 4)
227
228/* PM_WKDEP_DSP specific bits */
229
230/* PM_PWSTCTRL_DSP specific bits */
231/* 2430 only: MEMONSTATE, MEMRETSTATE */
232#define OMAP2420_MEMIONSTATE_SHIFT 12
233#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
234#define OMAP2420_MEMIRETSTATE (1 << 4)
235
236/* PM_PWSTST_DSP specific bits */
237/* MEMSTATEST is 2430 only */
238#define OMAP2420_MEMISTATEST_SHIFT 12
239#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
240
241/* PRCM_IRQSTATUS_DSP specific bits */
242
243/* PRCM_IRQENABLE_DSP specific bits */
244
245/* RM_RSTCTRL_MDM */
246/* 2430 only */
247#define OMAP2430_PWRON1_MDM (1 << 1)
248#define OMAP2430_RST1_MDM (1 << 0)
249
250/* RM_RSTST_MDM specific bits */
251/* 2430 only */
252#define OMAP2430_MDM_SECU_VIOL (1 << 6)
253#define OMAP2430_MDM_SW_PWRON1 (1 << 5)
254#define OMAP2430_MDM_SW_RST1 (1 << 4)
255
256/* PM_WKEN_MDM */
257/* 2430 only */
258#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)
259
260/* PM_WKST_MDM specific bits */
261/* 2430 only */
262
263/* PM_WKDEP_MDM specific bits */
264/* 2430 only */
265
266/* PM_PWSTCTRL_MDM specific bits */
267/* 2430 only */
268#define OMAP2430_KILLDOMAINWKUP (1 << 19)
269
270/* PM_PWSTST_MDM specific bits */
271/* 2430 only */
272
273/* PRCM_IRQSTATUS_IVA */
274/* 2420 only */
275
276/* PRCM_IRQENABLE_IVA */
277/* 2420 only */
278
279#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
new file mode 100644
index 00000000000..b4686bc345c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -0,0 +1,582 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
3
4/*
5 * OMAP3430 Power/Reset Management register bits
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prm.h"
18
19/* Shared register bits */
20
21/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
22#define OMAP3430_ON_SHIFT 24
23#define OMAP3430_ON_MASK (0xff << 24)
24#define OMAP3430_ONLP_SHIFT 16
25#define OMAP3430_ONLP_MASK (0xff << 16)
26#define OMAP3430_RET_SHIFT 8
27#define OMAP3430_RET_MASK (0xff << 8)
28#define OMAP3430_OFF_SHIFT 0
29#define OMAP3430_OFF_MASK (0xff << 0)
30
31/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
32#define OMAP3430_ERROROFFSET_SHIFT 24
33#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
34#define OMAP3430_ERRORGAIN_SHIFT 16
35#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
36#define OMAP3430_INITVOLTAGE_SHIFT 8
37#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
38#define OMAP3430_TIMEOUTEN (1 << 3)
39#define OMAP3430_INITVDD (1 << 2)
40#define OMAP3430_FORCEUPDATE (1 << 1)
41#define OMAP3430_VPENABLE (1 << 0)
42
43/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
45#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
46#define OMAP3430_VSTEPMIN_SHIFT 0
47#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
48
49/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
50#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
51#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
52#define OMAP3430_VSTEPMAX_SHIFT 0
53#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
54
55/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
56#define OMAP3430_VDDMAX_SHIFT 24
57#define OMAP3430_VDDMAX_MASK (0xff << 24)
58#define OMAP3430_VDDMIN_SHIFT 16
59#define OMAP3430_VDDMIN_MASK (0xff << 16)
60#define OMAP3430_TIMEOUT_SHIFT 0
61#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
62
63/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
64#define OMAP3430_VPVOLTAGE_SHIFT 0
65#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
66
67/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68#define OMAP3430_VPINIDLE (1 << 0)
69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER (1 << 7)
72
73/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
74#define OMAP3430_MEMORYCHANGE (1 << 3)
75
76/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
77#define OMAP3430_LOGICSTATEST (1 << 2)
78
79/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
80#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
81
82/*
83 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
84 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
85 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
86 */
87#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
88#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
89
90/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
91#define OMAP3430_WKUP_ST (1 << 0)
92
93/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
94#define OMAP3430_WKUP_EN (1 << 0)
95
96/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
97#define OMAP3430_GRPSEL_MMC2 (1 << 25)
98#define OMAP3430_GRPSEL_MMC1 (1 << 24)
99#define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
100#define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
101#define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
102#define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
103#define OMAP3430_GRPSEL_I2C3 (1 << 17)
104#define OMAP3430_GRPSEL_I2C2 (1 << 16)
105#define OMAP3430_GRPSEL_I2C1 (1 << 15)
106#define OMAP3430_GRPSEL_UART2 (1 << 14)
107#define OMAP3430_GRPSEL_UART1 (1 << 13)
108#define OMAP3430_GRPSEL_GPT11 (1 << 12)
109#define OMAP3430_GRPSEL_GPT10 (1 << 11)
110#define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
111#define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
112#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
113#define OMAP3430_GRPSEL_D2D (1 << 3)
114
115/*
116 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
117 * PM_PWSTCTRL_PER shared bits
118 */
119#define OMAP3430_MEMONSTATE_SHIFT 16
120#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
121#define OMAP3430_MEMRETSTATE (1 << 8)
122
123/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
124#define OMAP3430_GRPSEL_GPIO6 (1 << 17)
125#define OMAP3430_GRPSEL_GPIO5 (1 << 16)
126#define OMAP3430_GRPSEL_GPIO4 (1 << 15)
127#define OMAP3430_GRPSEL_GPIO3 (1 << 14)
128#define OMAP3430_GRPSEL_GPIO2 (1 << 13)
129#define OMAP3430_GRPSEL_UART3 (1 << 11)
130#define OMAP3430_GRPSEL_GPT9 (1 << 10)
131#define OMAP3430_GRPSEL_GPT8 (1 << 9)
132#define OMAP3430_GRPSEL_GPT7 (1 << 8)
133#define OMAP3430_GRPSEL_GPT6 (1 << 7)
134#define OMAP3430_GRPSEL_GPT5 (1 << 6)
135#define OMAP3430_GRPSEL_GPT4 (1 << 5)
136#define OMAP3430_GRPSEL_GPT3 (1 << 4)
137#define OMAP3430_GRPSEL_GPT2 (1 << 3)
138#define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
139#define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
140#define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
141
142/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
143#define OMAP3430_GRPSEL_IO (1 << 8)
144#define OMAP3430_GRPSEL_SR2 (1 << 7)
145#define OMAP3430_GRPSEL_SR1 (1 << 6)
146#define OMAP3430_GRPSEL_GPIO1 (1 << 3)
147#define OMAP3430_GRPSEL_GPT12 (1 << 1)
148#define OMAP3430_GRPSEL_GPT1 (1 << 0)
149
150/* Bits specific to each register */
151
152/* RM_RSTCTRL_IVA2 */
153#define OMAP3430_RST3_IVA2 (1 << 2)
154#define OMAP3430_RST2_IVA2 (1 << 1)
155#define OMAP3430_RST1_IVA2 (1 << 0)
156
157/* RM_RSTST_IVA2 specific bits */
158#define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
159#define OMAP3430_EMULATION_VHWA_RST (1 << 12)
160#define OMAP3430_EMULATION_IVA2_RST (1 << 11)
161#define OMAP3430_IVA2_SW_RST3 (1 << 10)
162#define OMAP3430_IVA2_SW_RST2 (1 << 9)
163#define OMAP3430_IVA2_SW_RST1 (1 << 8)
164
165/* PM_WKDEP_IVA2 specific bits */
166
167/* PM_PWSTCTRL_IVA2 specific bits */
168#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
169#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
170#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
171#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
172#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
173#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
174#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
175#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
176#define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
177#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
178#define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
179#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
180
181/* PM_PWSTST_IVA2 specific bits */
182#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
183#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
184#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
185#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
186#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
187#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
188#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
189#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
190
191/* PM_PREPWSTST_IVA2 specific bits */
192#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
193#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
194#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
195#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
196#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
197#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
198#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
199#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
200
201/* PRM_IRQSTATUS_IVA2 specific bits */
202#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
203#define OMAP3430_FORCEWKUP_ST (1 << 1)
204
205/* PRM_IRQENABLE_IVA2 specific bits */
206#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
207#define OMAP3430_FORCEWKUP_EN (1 << 1)
208
209/* PRM_REVISION specific bits */
210
211/* PRM_SYSCONFIG specific bits */
212
213/* PRM_IRQSTATUS_MPU specific bits */
214#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
215#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
216#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
217#define OMAP3430_VC_RAERR_ST (1 << 23)
218#define OMAP3430_VC_SAERR_ST (1 << 22)
219#define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
220#define OMAP3430_VP2_EQVALUE_ST (1 << 20)
221#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
222#define OMAP3430_VP2_MAXVDD_ST (1 << 18)
223#define OMAP3430_VP2_MINVDD_ST (1 << 17)
224#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
225#define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
226#define OMAP3430_VP1_EQVALUE_ST (1 << 14)
227#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
228#define OMAP3430_VP1_MAXVDD_ST (1 << 12)
229#define OMAP3430_VP1_MINVDD_ST (1 << 11)
230#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
231#define OMAP3430_IO_ST (1 << 9)
232#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
233#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
234#define OMAP3430_MPU_DPLL_ST (1 << 7)
235#define OMAP3430_MPU_DPLL_ST_SHIFT 7
236#define OMAP3430_PERIPH_DPLL_ST (1 << 6)
237#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
238#define OMAP3430_CORE_DPLL_ST (1 << 5)
239#define OMAP3430_CORE_DPLL_ST_SHIFT 5
240#define OMAP3430_TRANSITION_ST (1 << 4)
241#define OMAP3430_EVGENOFF_ST (1 << 3)
242#define OMAP3430_EVGENON_ST (1 << 2)
243#define OMAP3430_FS_USB_WKUP_ST (1 << 1)
244
245/* PRM_IRQENABLE_MPU specific bits */
246#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
247#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
248#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
249#define OMAP3430_VC_RAERR_EN (1 << 23)
250#define OMAP3430_VC_SAERR_EN (1 << 22)
251#define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
252#define OMAP3430_VP2_EQVALUE_EN (1 << 20)
253#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
254#define OMAP3430_VP2_MAXVDD_EN (1 << 18)
255#define OMAP3430_VP2_MINVDD_EN (1 << 17)
256#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
257#define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
258#define OMAP3430_VP1_EQVALUE_EN (1 << 14)
259#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
260#define OMAP3430_VP1_MAXVDD_EN (1 << 12)
261#define OMAP3430_VP1_MINVDD_EN (1 << 11)
262#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
263#define OMAP3430_IO_EN (1 << 9)
264#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
265#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
266#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
267#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
268#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
269#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
270#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
271#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
272#define OMAP3430_TRANSITION_EN (1 << 4)
273#define OMAP3430_EVGENOFF_EN (1 << 3)
274#define OMAP3430_EVGENON_EN (1 << 2)
275#define OMAP3430_FS_USB_WKUP_EN (1 << 1)
276
277/* RM_RSTST_MPU specific bits */
278#define OMAP3430_EMULATION_MPU_RST (1 << 11)
279
280/* PM_WKDEP_MPU specific bits */
281#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
282#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
283
284/* PM_EVGENCTRL_MPU */
285#define OMAP3430_OFFLOADMODE_SHIFT 3
286#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
287#define OMAP3430_ONLOADMODE_SHIFT 1
288#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
289#define OMAP3430_ENABLE (1 << 0)
290
291/* PM_EVGENONTIM_MPU */
292#define OMAP3430_ONTIMEVAL_SHIFT 0
293#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
294
295/* PM_EVGENOFFTIM_MPU */
296#define OMAP3430_OFFTIMEVAL_SHIFT 0
297#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
298
299/* PM_PWSTCTRL_MPU specific bits */
300#define OMAP3430_L2CACHEONSTATE_SHIFT 16
301#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
302#define OMAP3430_L2CACHERETSTATE (1 << 8)
303#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
304
305/* PM_PWSTST_MPU specific bits */
306#define OMAP3430_L2CACHESTATEST_SHIFT 6
307#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
308#define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
309
310/* PM_PREPWSTST_MPU specific bits */
311#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
312#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
313#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
314
315/* RM_RSTCTRL_CORE */
316#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
317#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
318
319/* RM_RSTST_CORE specific bits */
320#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
321#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
322#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
323
324/* PM_WKEN1_CORE specific bits */
325
326/* PM_MPUGRPSEL1_CORE specific bits */
327#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
328
329/* PM_IVA2GRPSEL1_CORE specific bits */
330
331/* PM_WKST1_CORE specific bits */
332
333/* PM_PWSTCTRL_CORE specific bits */
334#define OMAP3430_MEM2ONSTATE_SHIFT 18
335#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
336#define OMAP3430_MEM1ONSTATE_SHIFT 16
337#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
338#define OMAP3430_MEM2RETSTATE (1 << 9)
339#define OMAP3430_MEM1RETSTATE (1 << 8)
340
341/* PM_PWSTST_CORE specific bits */
342#define OMAP3430_MEM2STATEST_SHIFT 6
343#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
344#define OMAP3430_MEM1STATEST_SHIFT 4
345#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
346
347/* PM_PREPWSTST_CORE specific bits */
348#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
349#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
350#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
351#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
352
353/* RM_RSTST_GFX specific bits */
354
355/* PM_WKDEP_GFX specific bits */
356#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
357
358/* PM_PWSTCTRL_GFX specific bits */
359
360/* PM_PWSTST_GFX specific bits */
361
362/* PM_PREPWSTST_GFX specific bits */
363
364/* PM_WKEN_WKUP specific bits */
365#define OMAP3430_EN_IO (1 << 8)
366
367/* PM_MPUGRPSEL_WKUP specific bits */
368
369/* PM_IVA2GRPSEL_WKUP specific bits */
370
371/* PM_WKST_WKUP specific bits */
372#define OMAP3430_ST_IO (1 << 8)
373
374/* PRM_CLKSEL */
375#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
376#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
377
378/* PRM_CLKOUT_CTRL */
379#define OMAP3430_CLKOUT_EN (1 << 7)
380#define OMAP3430_CLKOUT_EN_SHIFT 7
381
382/* RM_RSTST_DSS specific bits */
383
384/* PM_WKEN_DSS */
385#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
386
387/* PM_WKDEP_DSS specific bits */
388#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
389
390/* PM_PWSTCTRL_DSS specific bits */
391
392/* PM_PWSTST_DSS specific bits */
393
394/* PM_PREPWSTST_DSS specific bits */
395
396/* RM_RSTST_CAM specific bits */
397
398/* PM_WKDEP_CAM specific bits */
399#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
400
401/* PM_PWSTCTRL_CAM specific bits */
402
403/* PM_PWSTST_CAM specific bits */
404
405/* PM_PREPWSTST_CAM specific bits */
406
407/* PM_PWSTCTRL_USBHOST specific bits */
408#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
409
410/* RM_RSTST_PER specific bits */
411
412/* PM_WKEN_PER specific bits */
413
414/* PM_MPUGRPSEL_PER specific bits */
415
416/* PM_IVA2GRPSEL_PER specific bits */
417
418/* PM_WKST_PER specific bits */
419
420/* PM_WKDEP_PER specific bits */
421#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
422
423/* PM_PWSTCTRL_PER specific bits */
424
425/* PM_PWSTST_PER specific bits */
426
427/* PM_PREPWSTST_PER specific bits */
428
429/* RM_RSTST_EMU specific bits */
430
431/* PM_PWSTST_EMU specific bits */
432
433/* PRM_VC_SMPS_SA */
434#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
435#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
436#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
437#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
438
439/* PRM_VC_SMPS_VOL_RA */
440#define OMAP3430_VOLRA1_SHIFT 16
441#define OMAP3430_VOLRA1_MASK (0xff << 16)
442#define OMAP3430_VOLRA0_SHIFT 0
443#define OMAP3430_VOLRA0_MASK (0xff << 0)
444
445/* PRM_VC_SMPS_CMD_RA */
446#define OMAP3430_CMDRA1_SHIFT 16
447#define OMAP3430_CMDRA1_MASK (0xff << 16)
448#define OMAP3430_CMDRA0_SHIFT 0
449#define OMAP3430_CMDRA0_MASK (0xff << 0)
450
451/* PRM_VC_CMD_VAL_0 specific bits */
452
453/* PRM_VC_CMD_VAL_1 specific bits */
454
455/* PRM_VC_CH_CONF */
456#define OMAP3430_CMD1 (1 << 20)
457#define OMAP3430_RACEN1 (1 << 19)
458#define OMAP3430_RAC1 (1 << 18)
459#define OMAP3430_RAV1 (1 << 17)
460#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
461#define OMAP3430_CMD0 (1 << 4)
462#define OMAP3430_RACEN0 (1 << 3)
463#define OMAP3430_RAC0 (1 << 2)
464#define OMAP3430_RAV0 (1 << 1)
465#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
466
467/* PRM_VC_I2C_CFG */
468#define OMAP3430_HSMASTER (1 << 5)
469#define OMAP3430_SREN (1 << 4)
470#define OMAP3430_HSEN (1 << 3)
471#define OMAP3430_MCODE_SHIFT 0
472#define OMAP3430_MCODE_MASK (0x7 << 0)
473
474/* PRM_VC_BYPASS_VAL */
475#define OMAP3430_VALID (1 << 24)
476#define OMAP3430_DATA_SHIFT 16
477#define OMAP3430_DATA_MASK (0xff << 16)
478#define OMAP3430_REGADDR_SHIFT 8
479#define OMAP3430_REGADDR_MASK (0xff << 8)
480#define OMAP3430_SLAVEADDR_SHIFT 0
481#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
482
483/* PRM_RSTCTRL */
484#define OMAP3430_RST_DPLL3 (1 << 2)
485#define OMAP3430_RST_GS (1 << 1)
486
487/* PRM_RSTTIME */
488#define OMAP3430_RSTTIME2_SHIFT 8
489#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
490#define OMAP3430_RSTTIME1_SHIFT 0
491#define OMAP3430_RSTTIME1_MASK (0xff << 0)
492
493/* PRM_RSTST */
494#define OMAP3430_ICECRUSHER_RST (1 << 10)
495#define OMAP3430_ICEPICK_RST (1 << 9)
496#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
497#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
498#define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
499#define OMAP3430_SECURE_WD_RST (1 << 5)
500#define OMAP3430_MPU_WD_RST (1 << 4)
501#define OMAP3430_SECURITY_VIOL_RST (1 << 3)
502#define OMAP3430_GLOBAL_SW_RST (1 << 1)
503#define OMAP3430_GLOBAL_COLD_RST (1 << 0)
504
505/* PRM_VOLTCTRL */
506#define OMAP3430_SEL_VMODE (1 << 4)
507#define OMAP3430_SEL_OFF (1 << 3)
508#define OMAP3430_AUTO_OFF (1 << 2)
509#define OMAP3430_AUTO_RET (1 << 1)
510#define OMAP3430_AUTO_SLEEP (1 << 0)
511
512/* PRM_SRAM_PCHARGE */
513#define OMAP3430_PCHARGE_TIME_SHIFT 0
514#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
515
516/* PRM_CLKSRC_CTRL */
517#define OMAP3430_SYSCLKDIV_SHIFT 6
518#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
519#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
520#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
521#define OMAP3430_SYSCLKSEL_SHIFT 0
522#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
523
524/* PRM_VOLTSETUP1 */
525#define OMAP3430_SETUP_TIME2_SHIFT 16
526#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
527#define OMAP3430_SETUP_TIME1_SHIFT 0
528#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
529
530/* PRM_VOLTOFFSET */
531#define OMAP3430_OFFSET_TIME_SHIFT 0
532#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
533
534/* PRM_CLKSETUP */
535#define OMAP3430_SETUP_TIME_SHIFT 0
536#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
537
538/* PRM_POLCTRL */
539#define OMAP3430_OFFMODE_POL (1 << 3)
540#define OMAP3430_CLKOUT_POL (1 << 2)
541#define OMAP3430_CLKREQ_POL (1 << 1)
542#define OMAP3430_EXTVOL_POL (1 << 0)
543
544/* PRM_VOLTSETUP2 */
545#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
546#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
547
548/* PRM_VP1_CONFIG specific bits */
549
550/* PRM_VP1_VSTEPMIN specific bits */
551
552/* PRM_VP1_VSTEPMAX specific bits */
553
554/* PRM_VP1_VLIMITTO specific bits */
555
556/* PRM_VP1_VOLTAGE specific bits */
557
558/* PRM_VP1_STATUS specific bits */
559
560/* PRM_VP2_CONFIG specific bits */
561
562/* PRM_VP2_VSTEPMIN specific bits */
563
564/* PRM_VP2_VSTEPMAX specific bits */
565
566/* PRM_VP2_VLIMITTO specific bits */
567
568/* PRM_VP2_VOLTAGE specific bits */
569
570/* PRM_VP2_STATUS specific bits */
571
572/* RM_RSTST_NEON specific bits */
573
574/* PM_WKDEP_NEON specific bits */
575
576/* PM_PWSTCTRL_NEON specific bits */
577
578/* PM_PWSTST_NEON specific bits */
579
580/* PM_PREPWSTST_NEON specific bits */
581
582#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
new file mode 100644
index 00000000000..ab7649afd89
--- /dev/null
+++ b/arch/arm/mach-omap2/prm.h
@@ -0,0 +1,316 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include "prcm-common.h"
18
19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
22#else
23#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
25#define OMAP2430_PRM_REGADDR(module, reg) \
26 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
27#define OMAP34XX_PRM_REGADDR(module, reg) \
28 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
29#endif
30
31/*
32 * Architecture-specific global PRM registers
33 * Use prm_{read,write}_reg() with these registers.
34 *
35 * With a few exceptions, these are the register names beginning with
36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
37 * IRQSTATUS and IRQENABLE bits.)
38 *
39 */
40
41#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
43
44#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
45#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
46
47#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
48#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
49#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
50#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
51#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
52#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
53#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
54#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
55#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
56#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
57
58#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
59#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
60
61#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
62#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
63
64
65#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
66#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
67#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
68#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
69#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
70#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
71#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
72#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
73#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
74#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
75#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
76#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
77#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
78#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
79#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
80#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
81#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
82#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
83#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
84#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
85#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
86#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
87#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
88#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
89#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
90#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
91#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
92#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
93#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
94#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
95#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
96
97#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
98#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
99
100/*
101 * Module specific PRM registers from PRM_BASE + domain offset
102 *
103 * Use prm_{read,write}_mod_reg() with these registers.
104 *
105 * With a few exceptions, these are the register names beginning with
106 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
107 * and IRQENABLE bits.)
108 *
109 */
110
111/* Registers appearing on both 24xx and 34xx */
112
113#define RM_RSTCTRL 0x0050
114#define RM_RSTTIME 0x0054
115#define RM_RSTST 0x0058
116
117#define PM_WKEN 0x00a0
118#define PM_WKEN1 PM_WKEN
119#define PM_WKST 0x00b0
120#define PM_WKST1 PM_WKST
121#define PM_WKDEP 0x00c8
122#define PM_EVGENCTRL 0x00d4
123#define PM_EVGENONTIM 0x00d8
124#define PM_EVGENOFFTIM 0x00dc
125#define PM_PWSTCTRL 0x00e0
126#define PM_PWSTST 0x00e4
127
128#define OMAP3430_PM_MPUGRPSEL 0x00a4
129#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
130
131#define OMAP3430_PM_IVAGRPSEL 0x00a8
132#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
133
134#define OMAP3430_PM_PREPWSTST 0x00e8
135
136#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
137#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
138
139
140/* Architecture-specific registers */
141
142#define OMAP24XX_PM_WKEN2 0x00a4
143#define OMAP24XX_PM_WKST2 0x00b4
144
145#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
146#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
147#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
148#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
149
150#ifndef __ASSEMBLER__
151
152/* Power/reset management domain register get/set */
153
154static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
155{
156 __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
157}
158
159static inline u32 prm_read_mod_reg(s16 module, s16 idx)
160{
161 return __raw_readl(OMAP_PRM_REGADDR(module, idx));
162}
163
164#endif
165
166/*
167 * Bits common to specific registers
168 *
169 * The 3430 register and bit names are generally used,
170 * since they tend to make more sense
171 */
172
173/* PM_EVGENONTIM_MPU */
174/* Named PM_EVEGENONTIM_MPU on the 24XX */
175#define OMAP_ONTIMEVAL_SHIFT 0
176#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
177
178/* PM_EVGENOFFTIM_MPU */
179/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
180#define OMAP_OFFTIMEVAL_SHIFT 0
181#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
182
183/* PRM_CLKSETUP and PRCM_VOLTSETUP */
184/* Named PRCM_CLKSSETUP on the 24XX */
185#define OMAP_SETUP_TIME_SHIFT 0
186#define OMAP_SETUP_TIME_MASK (0xffff << 0)
187
188/* PRM_CLKSRC_CTRL */
189/* Named PRCM_CLKSRC_CTRL on the 24XX */
190#define OMAP_SYSCLKDIV_SHIFT 6
191#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
192#define OMAP_AUTOEXTCLKMODE_SHIFT 3
193#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
194#define OMAP_SYSCLKSEL_SHIFT 0
195#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
196
197/* PM_EVGENCTRL_MPU */
198#define OMAP_OFFLOADMODE_SHIFT 3
199#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
200#define OMAP_ONLOADMODE_SHIFT 1
201#define OMAP_ONLOADMODE_MASK (0x3 << 1)
202#define OMAP_ENABLE (1 << 0)
203
204/* PRM_RSTTIME */
205/* Named RM_RSTTIME_WKUP on the 24xx */
206#define OMAP_RSTTIME2_SHIFT 8
207#define OMAP_RSTTIME2_MASK (0x1f << 8)
208#define OMAP_RSTTIME1_SHIFT 0
209#define OMAP_RSTTIME1_MASK (0xff << 0)
210
211
212/* PRM_RSTCTRL */
213/* Named RM_RSTCTRL_WKUP on the 24xx */
214/* 2420 calls RST_DPLL3 'RST_DPLL' */
215#define OMAP_RST_DPLL3 (1 << 2)
216#define OMAP_RST_GS (1 << 1)
217
218
219/*
220 * Bits common to module-shared registers
221 *
222 * Not all registers of a particular type support all of these bits -
223 * check TRM if you are unsure
224 */
225
226/*
227 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
228 *
229 * 2430: PM_PWSTST_MDM
230 *
231 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
232 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
233 * PM_PWSTST_NEON
234 */
235#define OMAP_INTRANSITION (1 << 20)
236
237
238/*
239 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
240 *
241 * 2430: PM_PWSTST_MDM
242 *
243 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
244 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
245 * PM_PWSTST_NEON
246 */
247#define OMAP_POWERSTATEST_SHIFT 0
248#define OMAP_POWERSTATEST_MASK (0x3 << 0)
249
250/*
251 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
252 * called 'COREWKUP_RST'
253 *
254 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
255 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
256 */
257#define OMAP_COREDOMAINWKUP_RST (1 << 3)
258
259/*
260 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
261 *
262 * 2430: RM_RSTST_MDM
263 *
264 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
265 */
266#define OMAP_DOMAINWKUP_RST (1 << 2)
267
268/*
269 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
270 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
271 *
272 * 2430: RM_RSTST_MDM
273 *
274 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
275 */
276#define OMAP_GLOBALWARM_RST (1 << 1)
277#define OMAP_GLOBALCOLD_RST (1 << 0)
278
279/*
280 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
281 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
282 *
283 * 2430: PM_WKDEP_MDM
284 *
285 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
286 * PM_WKDEP_PER
287 */
288#define OMAP_EN_WKUP (1 << 4)
289
290/*
291 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
292 * PM_PWSTCTRL_DSP
293 *
294 * 2430: PM_PWSTCTRL_MDM
295 *
296 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
297 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
298 * PM_PWSTCTRL_NEON
299 */
300#define OMAP_LOGICRETSTATE (1 << 2)
301
302/*
303 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
304 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
305 *
306 * 2430: PM_PWSTCTRL_MDM shared bits
307 *
308 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
309 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
310 * PM_PWSTCTRL_NEON shared bits
311 */
312#define OMAP_POWERSTATE_SHIFT 0
313#define OMAP_POWERSTATE_MASK (0x3 << 0)
314
315
316#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
new file mode 100644
index 00000000000..d7f23bc9550
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -0,0 +1,58 @@
1#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
2#define __ARCH_ARM_MACH_OMAP2_SDRC_H
3
4/*
5 * OMAP2 SDRC register definitions
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#undef DEBUG
17
18#include <asm/arch/sdrc.h>
19
20#ifndef __ASSEMBLER__
21extern unsigned long omap2_sdrc_base;
22extern unsigned long omap2_sms_base;
23
24#define OMAP_SDRC_REGADDR(reg) \
25 (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
26#define OMAP_SMS_REGADDR(reg) \
27 (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
28
29/* SDRC global register get/set */
30
31static inline void sdrc_write_reg(u32 val, u16 reg)
32{
33 __raw_writel(val, OMAP_SDRC_REGADDR(reg));
34}
35
36static inline u32 sdrc_read_reg(u16 reg)
37{
38 return __raw_readl(OMAP_SDRC_REGADDR(reg));
39}
40
41/* SMS global register get/set */
42
43static inline void sms_write_reg(u32 val, u16 reg)
44{
45 __raw_writel(val, OMAP_SMS_REGADDR(reg));
46}
47
48static inline u32 sms_read_reg(u16 reg)
49{
50 return __raw_readl(OMAP_SMS_REGADDR(reg));
51}
52#else
53#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
54#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
55#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
56#endif /* __ASSEMBLER__ */
57
58#endif
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 16247d55785..46ccb9b8b58 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -26,19 +26,10 @@
26#include <asm/arch/io.h> 26#include <asm/arch/io.h>
27#include <asm/arch/pm.h> 27#include <asm/arch/pm.h>
28 28
29#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10) 29#include "sdrc.h"
30#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
31#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
32#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
33#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
34#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
35#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
36 30
37#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60) 31/* First address of reserved address space? apparently valid for OMAP2 & 3 */
38#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
39#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
40#define A_SDRC0_V (0xC0000000) 32#define A_SDRC0_V (0xC0000000)
41#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
42 33
43 .text 34 .text
44 35
@@ -126,17 +117,11 @@ loop2:
126 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 117 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
127 118
128A_SDRC_POWER: 119A_SDRC_POWER:
129 .word A_SDRC_POWER_V 120 .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
130A_SDRC0: 121A_SDRC0:
131 .word A_SDRC0_V 122 .word A_SDRC0_V
132A_CM_CLKSEL2_PLL_S:
133 .word A_CM_CLKSEL2_PLL_V
134A_CM_CLKEN_PLL:
135 .word A_CM_CLKEN_PLL_V
136A_SDRC_DLLA_CTRL_S: 123A_SDRC_DLLA_CTRL_S:
137 .word A_SDRC_DLLA_CTRL_V 124 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
138A_SDRC_MANUAL_S:
139 .word A_SDRC_MANUAL_V
140 125
141ENTRY(omap24xx_cpu_suspend_sz) 126ENTRY(omap24xx_cpu_suspend_sz)
142 .word . - omap24xx_cpu_suspend 127 .word . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index b27576690f8..4a9e4914071 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -27,19 +27,11 @@
27#include <asm/arch/io.h> 27#include <asm/arch/io.h>
28#include <asm/hardware.h> 28#include <asm/hardware.h>
29 29
30#include "prcm-regs.h" 30#include "sdrc.h"
31#include "prm.h"
32#include "cm.h"
31 33
32#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) 34#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
33
34#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
35#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
36#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
37#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
38#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
39#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
40
41#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
42#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
43 35
44 .text 36 .text
45 37
@@ -131,11 +123,11 @@ volt_delay:
131 123
132/* relative load constants */ 124/* relative load constants */
133cm_clksel2_pll: 125cm_clksel2_pll:
134 .word CM_CLKSEL2_PLL_V 126 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
135sdrc_dlla_ctrl: 127sdrc_dlla_ctrl:
136 .word SDRC_DLLA_CTRL_V 128 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
137prcm_voltctrl: 129prcm_voltctrl:
138 .word PRCM_VOLTCTRL_V 130 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
139prcm_mask_val: 131prcm_mask_val:
140 .word 0xFFFF3FFC 132 .word 0xFFFF3FFC
141timer_32ksynct_cr: 133timer_32ksynct_cr:
@@ -225,13 +217,13 @@ volt_delay_c:
225 mov pc, lr @ back to caller 217 mov pc, lr @ back to caller
226 218
227ddr_cm_clksel2_pll: 219ddr_cm_clksel2_pll:
228 .word CM_CLKSEL2_PLL_V 220 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
229ddr_sdrc_dlla_ctrl: 221ddr_sdrc_dlla_ctrl:
230 .word SDRC_DLLA_CTRL_V 222 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
231ddr_sdrc_rfr_ctrl: 223ddr_sdrc_rfr_ctrl:
232 .word SDRC_RFR_CTRL_V 224 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
233ddr_prcm_voltctrl: 225ddr_prcm_voltctrl:
234 .word PRCM_VOLTCTRL_V 226 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
235ddr_prcm_mask_val: 227ddr_prcm_mask_val:
236 .word 0xFFFF3FFC 228 .word 0xFFFF3FFC
237ddr_timer_32ksynct: 229ddr_timer_32ksynct:
@@ -316,17 +308,17 @@ wait_dll_lock:
316 ldmfd sp!, {r0-r12, pc} @ restore regs and return 308 ldmfd sp!, {r0-r12, pc} @ restore regs and return
317 309
318set_config: 310set_config:
319 .word PRCM_CLKCFG_CTRL_V 311 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
320pll_ctl: 312pll_ctl:
321 .word CM_CLKEN_PLL_V 313 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
322pll_stat: 314pll_stat:
323 .word CM_IDLEST_CKGEN_V 315 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
324pll_div: 316pll_div:
325 .word CM_CLKSEL1_PLL_V 317 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
326sdrc_rfr: 318sdrc_rfr:
327 .word SDRC_RFR_CTRL_V 319 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
328dlla_ctrl: 320dlla_ctrl:
329 .word SDRC_DLLA_CTRL_V 321 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
330 322
331ENTRY(sram_set_prcm_sz) 323ENTRY(sram_set_prcm_sz)
332 .word . - sram_set_prcm 324 .word . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3234deedb94..78d05f203ff 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,11 @@
3 * 3 *
4 * OMAP2 GP timer support. 4 * OMAP2 GP timer support.
5 * 5 *
6 * Update to use new clocksource/clockevent layers
7 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 *
10 * Original driver:
6 * Copyright (C) 2005 Nokia Corporation 11 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 12 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * Juha Yrjölä <juha.yrjola@nokia.com> 13 * Juha Yrjölä <juha.yrjola@nokia.com>
@@ -25,24 +30,23 @@
25#include <linux/clk.h> 30#include <linux/clk.h>
26#include <linux/delay.h> 31#include <linux/delay.h>
27#include <linux/irq.h> 32#include <linux/irq.h>
33#include <linux/clocksource.h>
34#include <linux/clockchips.h>
28 35
29#include <asm/mach/time.h> 36#include <asm/mach/time.h>
30#include <asm/arch/dmtimer.h> 37#include <asm/arch/dmtimer.h>
31 38
32static struct omap_dm_timer *gptimer; 39static struct omap_dm_timer *gptimer;
33 40static struct clock_event_device clockevent_gpt;
34static inline void omap2_gp_timer_start(unsigned long load_val)
35{
36 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
37 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
38 omap_dm_timer_start(gptimer);
39}
40 41
41static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 42static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
42{ 43{
43 omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW); 44 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
44 timer_tick(); 45 struct clock_event_device *evt = &clockevent_gpt;
46
47 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
45 48
49 evt->event_handler(evt);
46 return IRQ_HANDLED; 50 return IRQ_HANDLED;
47} 51}
48 52
@@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
52 .handler = omap2_gp_timer_interrupt, 56 .handler = omap2_gp_timer_interrupt,
53}; 57};
54 58
55static void __init omap2_gp_timer_init(void) 59static int omap2_gp_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
56{ 61{
57 u32 tick_period; 62 omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
63 omap_dm_timer_start(gptimer);
64
65 return 0;
66}
67
68static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
69 struct clock_event_device *evt)
70{
71 u32 period;
72
73 omap_dm_timer_stop(gptimer);
74
75 switch (mode) {
76 case CLOCK_EVT_MODE_PERIODIC:
77 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
78 period -= 1;
79
80 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
81 omap_dm_timer_start(gptimer);
82 break;
83 case CLOCK_EVT_MODE_ONESHOT:
84 break;
85 case CLOCK_EVT_MODE_UNUSED:
86 case CLOCK_EVT_MODE_SHUTDOWN:
87 case CLOCK_EVT_MODE_RESUME:
88 break;
89 }
90}
91
92static struct clock_event_device clockevent_gpt = {
93 .name = "gp timer",
94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
95 .shift = 32,
96 .set_next_event = omap2_gp_timer_set_next_event,
97 .set_mode = omap2_gp_timer_set_mode,
98};
99
100static void __init omap2_gp_clockevent_init(void)
101{
102 u32 tick_rate;
58 103
59 omap_dm_timer_init();
60 gptimer = omap_dm_timer_request_specific(1); 104 gptimer = omap_dm_timer_request_specific(1);
61 BUG_ON(gptimer == NULL); 105 BUG_ON(gptimer == NULL);
62 106
107#if defined(CONFIG_OMAP_32K_TIMER)
108 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
109#else
63 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); 110 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
64 tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; 111#endif
65 tick_period -= 1; 112 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
66 113
114 omap2_gp_timer_irq.dev_id = (void *)gptimer;
67 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); 115 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
68 omap2_gp_timer_start(tick_period); 116 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
117
118 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
119 clockevent_gpt.shift);
120 clockevent_gpt.max_delta_ns =
121 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
122 clockevent_gpt.min_delta_ns =
123 clockevent_delta2ns(1, &clockevent_gpt);
124
125 clockevent_gpt.cpumask = cpumask_of_cpu(0);
126 clockevents_register_device(&clockevent_gpt);
127}
128
129#ifdef CONFIG_OMAP_32K_TIMER
130/*
131 * When 32k-timer is enabled, don't use GPTimer for clocksource
132 * instead, just leave default clocksource which uses the 32k
133 * sync counter. See clocksource setup in see plat-omap/common.c.
134 */
135
136static inline void __init omap2_gp_clocksource_init(void) {}
137#else
138/*
139 * clocksource
140 */
141static struct omap_dm_timer *gpt_clocksource;
142static cycle_t clocksource_read_cycles(void)
143{
144 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
145}
146
147static struct clocksource clocksource_gpt = {
148 .name = "gp timer",
149 .rating = 300,
150 .read = clocksource_read_cycles,
151 .mask = CLOCKSOURCE_MASK(32),
152 .shift = 24,
153 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
154};
155
156/* Setup free-running counter for clocksource */
157static void __init omap2_gp_clocksource_init(void)
158{
159 static struct omap_dm_timer *gpt;
160 u32 tick_rate, tick_period;
161 static char err1[] __initdata = KERN_ERR
162 "%s: failed to request dm-timer\n";
163 static char err2[] __initdata = KERN_ERR
164 "%s: can't register clocksource!\n";
165
166 gpt = omap_dm_timer_request();
167 if (!gpt)
168 printk(err1, clocksource_gpt.name);
169 gpt_clocksource = gpt;
170
171 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
172 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
173 tick_period = (tick_rate / HZ) - 1;
174
175 omap_dm_timer_set_load(gpt, 1, 0);
176 omap_dm_timer_start(gpt);
177
178 clocksource_gpt.mult =
179 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
180 if (clocksource_register(&clocksource_gpt))
181 printk(err2, clocksource_gpt.name);
182}
183#endif
184
185static void __init omap2_gp_timer_init(void)
186{
187 omap_dm_timer_init();
188
189 omap2_gp_clockevent_init();
190 omap2_gp_clocksource_init();
69} 191}
70 192
71struct sys_timer omap_timer = { 193struct sys_timer omap_timer = {
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 8f56c255d1e..bc639a30d6d 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,8 +9,6 @@ obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
11 11
12obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
13
14# OCPI interconnect support for 1710, 1610 and 5912 12# OCPI interconnect support for 1710, 1610 and 5912
15obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o 13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
16 14
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 0a603242f36..32a533ba9ad 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -304,6 +304,23 @@ void propagate_rate(struct clk * tclk)
304 } 304 }
305} 305}
306 306
307/**
308 * recalculate_root_clocks - recalculate and propagate all root clocks
309 *
310 * Recalculates all root clocks (clocks with no parent), which if the
311 * clock's .recalc is set correctly, should also propagate their rates.
312 * Called at init.
313 */
314void recalculate_root_clocks(void)
315{
316 struct clk *clkp;
317
318 list_for_each_entry(clkp, &clocks, node) {
319 if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
320 clkp->recalc(clkp);
321 }
322}
323
307int clk_register(struct clk *clk) 324int clk_register(struct clk *clk)
308{ 325{
309 if (clk == NULL || IS_ERR(clk)) 326 if (clk == NULL || IS_ERR(clk))
@@ -358,6 +375,30 @@ void clk_allow_idle(struct clk *clk)
358} 375}
359EXPORT_SYMBOL(clk_allow_idle); 376EXPORT_SYMBOL(clk_allow_idle);
360 377
378void clk_enable_init_clocks(void)
379{
380 struct clk *clkp;
381
382 list_for_each_entry(clkp, &clocks, node) {
383 if (clkp->flags & ENABLE_ON_INIT)
384 clk_enable(clkp);
385 }
386}
387EXPORT_SYMBOL(clk_enable_init_clocks);
388
389#ifdef CONFIG_CPU_FREQ
390void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
391{
392 unsigned long flags;
393
394 spin_lock_irqsave(&clockfw_lock, flags);
395 if (arch_clock->clk_init_cpufreq_table)
396 arch_clock->clk_init_cpufreq_table(table);
397 spin_unlock_irqrestore(&clockfw_lock, flags);
398}
399EXPORT_SYMBOL(clk_init_cpufreq_table);
400#endif
401
361/*-------------------------------------------------------------------------*/ 402/*-------------------------------------------------------------------------*/
362 403
363#ifdef CONFIG_OMAP_RESET_CLOCKS 404#ifdef CONFIG_OMAP_RESET_CLOCKS
@@ -396,3 +437,4 @@ int __init clk_init(struct clk_functions * custom_clocks)
396 437
397 return 0; 438 return 0;
398} 439}
440
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 4f0f9c4e938..bd1cef2c3c1 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -27,11 +27,16 @@
27#include <asm/setup.h> 27#include <asm/setup.h>
28 28
29#include <asm/arch/board.h> 29#include <asm/arch/board.h>
30#include <asm/arch/control.h>
30#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
31#include <asm/arch/fpga.h> 32#include <asm/arch/fpga.h>
32 33
33#include <asm/arch/clock.h> 34#include <asm/arch/clock.h>
34 35
36#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
37# include "../mach-omap2/sdrc.h"
38#endif
39
35#define NO_LENGTH_CHECK 0xffffffff 40#define NO_LENGTH_CHECK 0xffffffff
36 41
37unsigned char omap_bootloader_tag[512]; 42unsigned char omap_bootloader_tag[512];
@@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console);
171 176
172#if defined(CONFIG_ARCH_OMAP16XX) 177#if defined(CONFIG_ARCH_OMAP16XX)
173#define TIMER_32K_SYNCHRONIZED 0xfffbc410 178#define TIMER_32K_SYNCHRONIZED 0xfffbc410
174#elif defined(CONFIG_ARCH_OMAP24XX) 179#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
175#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10) 180#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
176#endif 181#endif
177 182
178#ifdef TIMER_32K_SYNCHRONIZED 183#ifdef TIMER_32K_SYNCHRONIZED
@@ -193,12 +198,35 @@ static struct clocksource clocksource_32k = {
193 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 198 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
194}; 199};
195 200
201/*
202 * Rounds down to nearest nsec.
203 */
204unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
205{
206 return cyc2ns(&clocksource_32k, ticks_32k);
207}
208
209/*
210 * Returns current time from boot in nsecs. It's OK for this to wrap
211 * around for now, as it's just a relative time stamp.
212 */
213unsigned long long sched_clock(void)
214{
215 return omap_32k_ticks_to_nsecs(omap_32k_read());
216}
217
196static int __init omap_init_clocksource_32k(void) 218static int __init omap_init_clocksource_32k(void)
197{ 219{
198 static char err[] __initdata = KERN_ERR 220 static char err[] __initdata = KERN_ERR
199 "%s: can't register clocksource!\n"; 221 "%s: can't register clocksource!\n";
200 222
201 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 223 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
224 struct clk *sync_32k_ick;
225
226 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
227 if (sync_32k_ick)
228 clk_enable(sync_32k_ick);
229
202 clocksource_32k.mult = clocksource_hz2mult(32768, 230 clocksource_32k.mult = clocksource_hz2mult(32768,
203 clocksource_32k.shift); 231 clocksource_32k.shift);
204 232
@@ -210,3 +238,33 @@ static int __init omap_init_clocksource_32k(void)
210arch_initcall(omap_init_clocksource_32k); 238arch_initcall(omap_init_clocksource_32k);
211 239
212#endif /* TIMER_32K_SYNCHRONIZED */ 240#endif /* TIMER_32K_SYNCHRONIZED */
241
242/* Global address base setup code */
243
244#if defined(CONFIG_ARCH_OMAP2420)
245void __init omap2_set_globals_242x(void)
246{
247 omap2_sdrc_base = OMAP2420_SDRC_BASE;
248 omap2_sms_base = OMAP2420_SMS_BASE;
249 omap_ctrl_base_set(OMAP2420_CTRL_BASE);
250}
251#endif
252
253#if defined(CONFIG_ARCH_OMAP2430)
254void __init omap2_set_globals_243x(void)
255{
256 omap2_sdrc_base = OMAP243X_SDRC_BASE;
257 omap2_sms_base = OMAP243X_SMS_BASE;
258 omap_ctrl_base_set(OMAP243X_CTRL_BASE);
259}
260#endif
261
262#if defined(CONFIG_ARCH_OMAP3430)
263void __init omap2_set_globals_343x(void)
264{
265 omap2_sdrc_base = OMAP343X_SDRC_BASE;
266 omap2_sms_base = OMAP343X_SMS_BASE;
267 omap_ctrl_base_set(OMAP343X_CTRL_BASE);
268}
269#endif
270
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8c78e4e57b5..1903a3491ee 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -136,7 +136,6 @@ struct gpio_bank {
136 u16 irq; 136 u16 irq;
137 u16 virtual_irq_start; 137 u16 virtual_irq_start;
138 int method; 138 int method;
139 u32 reserved_map;
140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 139#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
141 u32 suspend_wakeup; 140 u32 suspend_wakeup;
142 u32 saved_wakeup; 141 u32 saved_wakeup;
@@ -149,7 +148,9 @@ struct gpio_bank {
149 u32 saved_fallingdetect; 148 u32 saved_fallingdetect;
150 u32 saved_risingdetect; 149 u32 saved_risingdetect;
151#endif 150#endif
151 u32 level_mask;
152 spinlock_t lock; 152 spinlock_t lock;
153 struct gpio_chip chip;
153}; 154};
154 155
155#define METHOD_MPUIO 0 156#define METHOD_MPUIO 0
@@ -538,10 +539,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
538 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 539 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
539 } 540 }
540 541
541 /* 542 bank->level_mask =
542 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only 543 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
543 * level triggering requested. 544 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
544 */
545} 545}
546#endif 546#endif
547 547
@@ -652,6 +652,12 @@ static int gpio_irq_type(unsigned irq, unsigned type)
652 irq_desc[irq].status |= type; 652 irq_desc[irq].status |= type;
653 } 653 }
654 spin_unlock_irqrestore(&bank->lock, flags); 654 spin_unlock_irqrestore(&bank->lock, flags);
655
656 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
657 __set_irq_handler_unlocked(irq, handle_level_irq);
658 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
659 __set_irq_handler_unlocked(irq, handle_edge_irq);
660
655 return retval; 661 return retval;
656} 662}
657 663
@@ -903,19 +909,17 @@ int omap_request_gpio(int gpio)
903{ 909{
904 struct gpio_bank *bank; 910 struct gpio_bank *bank;
905 unsigned long flags; 911 unsigned long flags;
912 int status;
906 913
907 if (check_gpio(gpio) < 0) 914 if (check_gpio(gpio) < 0)
908 return -EINVAL; 915 return -EINVAL;
909 916
917 status = gpio_request(gpio, NULL);
918 if (status < 0)
919 return status;
920
910 bank = get_gpio_bank(gpio); 921 bank = get_gpio_bank(gpio);
911 spin_lock_irqsave(&bank->lock, flags); 922 spin_lock_irqsave(&bank->lock, flags);
912 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
913 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
914 dump_stack();
915 spin_unlock_irqrestore(&bank->lock, flags);
916 return -1;
917 }
918 bank->reserved_map |= (1 << get_gpio_index(gpio));
919 923
920 /* Set trigger to none. You need to enable the desired trigger with 924 /* Set trigger to none. You need to enable the desired trigger with
921 * request_irq() or set_irq_type(). 925 * request_irq() or set_irq_type().
@@ -945,10 +949,11 @@ void omap_free_gpio(int gpio)
945 return; 949 return;
946 bank = get_gpio_bank(gpio); 950 bank = get_gpio_bank(gpio);
947 spin_lock_irqsave(&bank->lock, flags); 951 spin_lock_irqsave(&bank->lock, flags);
948 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { 952 if (unlikely(!gpiochip_is_requested(&bank->chip,
953 get_gpio_index(gpio)))) {
954 spin_unlock_irqrestore(&bank->lock, flags);
949 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); 955 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
950 dump_stack(); 956 dump_stack();
951 spin_unlock_irqrestore(&bank->lock, flags);
952 return; 957 return;
953 } 958 }
954#ifdef CONFIG_ARCH_OMAP16XX 959#ifdef CONFIG_ARCH_OMAP16XX
@@ -965,9 +970,9 @@ void omap_free_gpio(int gpio)
965 __raw_writel(1 << get_gpio_index(gpio), reg); 970 __raw_writel(1 << get_gpio_index(gpio), reg);
966 } 971 }
967#endif 972#endif
968 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
969 _reset_gpio(bank, gpio); 973 _reset_gpio(bank, gpio);
970 spin_unlock_irqrestore(&bank->lock, flags); 974 spin_unlock_irqrestore(&bank->lock, flags);
975 gpio_free(gpio);
971} 976}
972 977
973/* 978/*
@@ -1022,12 +1027,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1022 isr &= 0x0000ffff; 1027 isr &= 0x0000ffff;
1023 1028
1024 if (cpu_class_is_omap2()) { 1029 if (cpu_class_is_omap2()) {
1025 level_mask = 1030 level_mask = bank->level_mask & enabled;
1026 __raw_readl(bank->base +
1027 OMAP24XX_GPIO_LEVELDETECT0) |
1028 __raw_readl(bank->base +
1029 OMAP24XX_GPIO_LEVELDETECT1);
1030 level_mask &= enabled;
1031 } 1031 }
1032 1032
1033 /* clear edge sensitive interrupts before handler(s) are 1033 /* clear edge sensitive interrupts before handler(s) are
@@ -1052,51 +1052,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1052 gpio_irq = bank->virtual_irq_start; 1052 gpio_irq = bank->virtual_irq_start;
1053 for (; isr != 0; isr >>= 1, gpio_irq++) { 1053 for (; isr != 0; isr >>= 1, gpio_irq++) {
1054 struct irq_desc *d; 1054 struct irq_desc *d;
1055 int irq_mask; 1055
1056 if (!(isr & 1)) 1056 if (!(isr & 1))
1057 continue; 1057 continue;
1058 d = irq_desc + gpio_irq; 1058 d = irq_desc + gpio_irq;
1059 /* Don't run the handler if it's already running
1060 * or was disabled lazely.
1061 */
1062 if (unlikely((d->depth ||
1063 (d->status & IRQ_INPROGRESS)))) {
1064 irq_mask = 1 <<
1065 (gpio_irq - bank->virtual_irq_start);
1066 /* The unmasking will be done by
1067 * enable_irq in case it is disabled or
1068 * after returning from the handler if
1069 * it's already running.
1070 */
1071 _enable_gpio_irqbank(bank, irq_mask, 0);
1072 if (!d->depth) {
1073 /* Level triggered interrupts
1074 * won't ever be reentered
1075 */
1076 BUG_ON(level_mask & irq_mask);
1077 d->status |= IRQ_PENDING;
1078 }
1079 continue;
1080 }
1081 1059
1082 desc_handle_irq(gpio_irq, d); 1060 desc_handle_irq(gpio_irq, d);
1083
1084 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1085 irq_mask = 1 <<
1086 (gpio_irq - bank->virtual_irq_start);
1087 d->status &= ~IRQ_PENDING;
1088 _enable_gpio_irqbank(bank, irq_mask, 1);
1089 retrigger |= irq_mask;
1090 }
1091 } 1061 }
1092
1093 if (cpu_class_is_omap2()) {
1094 /* clear level sensitive interrupts after handler(s) */
1095 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1096 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1097 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1098 }
1099
1100 } 1062 }
1101 /* if bank has any level sensitive GPIO pin interrupt 1063 /* if bank has any level sensitive GPIO pin interrupt
1102 configured, we must unmask the bank interrupt only after 1064 configured, we must unmask the bank interrupt only after
@@ -1135,6 +1097,14 @@ static void gpio_unmask_irq(unsigned int irq)
1135{ 1097{
1136 unsigned int gpio = irq - IH_GPIO_BASE; 1098 unsigned int gpio = irq - IH_GPIO_BASE;
1137 struct gpio_bank *bank = get_irq_chip_data(irq); 1099 struct gpio_bank *bank = get_irq_chip_data(irq);
1100 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1101
1102 /* For level-triggered GPIOs, the clearing must be done after
1103 * the HW source is cleared, thus after the handler has run */
1104 if (bank->level_mask & irq_mask) {
1105 _set_gpio_irqenable(bank, gpio, 0);
1106 _clear_gpio_irqstatus(bank, gpio);
1107 }
1138 1108
1139 _set_gpio_irqenable(bank, gpio, 1); 1109 _set_gpio_irqenable(bank, gpio, 1);
1140} 1110}
@@ -1266,6 +1236,53 @@ static inline void mpuio_init(void) {}
1266 1236
1267/*---------------------------------------------------------------------*/ 1237/*---------------------------------------------------------------------*/
1268 1238
1239/* REVISIT these are stupid implementations! replace by ones that
1240 * don't switch on METHOD_* and which mostly avoid spinlocks
1241 */
1242
1243static int gpio_input(struct gpio_chip *chip, unsigned offset)
1244{
1245 struct gpio_bank *bank;
1246 unsigned long flags;
1247
1248 bank = container_of(chip, struct gpio_bank, chip);
1249 spin_lock_irqsave(&bank->lock, flags);
1250 _set_gpio_direction(bank, offset, 1);
1251 spin_unlock_irqrestore(&bank->lock, flags);
1252 return 0;
1253}
1254
1255static int gpio_get(struct gpio_chip *chip, unsigned offset)
1256{
1257 return omap_get_gpio_datain(chip->base + offset);
1258}
1259
1260static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1261{
1262 struct gpio_bank *bank;
1263 unsigned long flags;
1264
1265 bank = container_of(chip, struct gpio_bank, chip);
1266 spin_lock_irqsave(&bank->lock, flags);
1267 _set_gpio_dataout(bank, offset, value);
1268 _set_gpio_direction(bank, offset, 0);
1269 spin_unlock_irqrestore(&bank->lock, flags);
1270 return 0;
1271}
1272
1273static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1274{
1275 struct gpio_bank *bank;
1276 unsigned long flags;
1277
1278 bank = container_of(chip, struct gpio_bank, chip);
1279 spin_lock_irqsave(&bank->lock, flags);
1280 _set_gpio_dataout(bank, offset, value);
1281 spin_unlock_irqrestore(&bank->lock, flags);
1282}
1283
1284/*---------------------------------------------------------------------*/
1285
1269static int initialized; 1286static int initialized;
1270#if !defined(CONFIG_ARCH_OMAP3) 1287#if !defined(CONFIG_ARCH_OMAP3)
1271static struct clk * gpio_ick; 1288static struct clk * gpio_ick;
@@ -1293,6 +1310,7 @@ static struct lock_class_key gpio_lock_class;
1293static int __init _omap_gpio_init(void) 1310static int __init _omap_gpio_init(void)
1294{ 1311{
1295 int i; 1312 int i;
1313 int gpio = 0;
1296 struct gpio_bank *bank; 1314 struct gpio_bank *bank;
1297#if defined(CONFIG_ARCH_OMAP3) 1315#if defined(CONFIG_ARCH_OMAP3)
1298 char clk_name[11]; 1316 char clk_name[11];
@@ -1423,7 +1441,6 @@ static int __init _omap_gpio_init(void)
1423 int j, gpio_count = 16; 1441 int j, gpio_count = 16;
1424 1442
1425 bank = &gpio_bank[i]; 1443 bank = &gpio_bank[i];
1426 bank->reserved_map = 0;
1427 bank->base = IO_ADDRESS(bank->base); 1444 bank->base = IO_ADDRESS(bank->base);
1428 spin_lock_init(&bank->lock); 1445 spin_lock_init(&bank->lock);
1429 if (bank_is_mpuio(bank)) 1446 if (bank_is_mpuio(bank))
@@ -1461,6 +1478,26 @@ static int __init _omap_gpio_init(void)
1461 gpio_count = 32; 1478 gpio_count = 32;
1462 } 1479 }
1463#endif 1480#endif
1481
1482 /* REVISIT eventually switch from OMAP-specific gpio structs
1483 * over to the generic ones
1484 */
1485 bank->chip.direction_input = gpio_input;
1486 bank->chip.get = gpio_get;
1487 bank->chip.direction_output = gpio_output;
1488 bank->chip.set = gpio_set;
1489 if (bank_is_mpuio(bank)) {
1490 bank->chip.label = "mpuio";
1491 bank->chip.base = OMAP_MPUIO(0);
1492 } else {
1493 bank->chip.label = "gpio";
1494 bank->chip.base = gpio;
1495 gpio += gpio_count;
1496 }
1497 bank->chip.ngpio = gpio_count;
1498
1499 gpiochip_add(&bank->chip);
1500
1464 for (j = bank->virtual_irq_start; 1501 for (j = bank->virtual_irq_start;
1465 j < bank->virtual_irq_start + gpio_count; j++) { 1502 j < bank->virtual_irq_start + gpio_count; j++) {
1466 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); 1503 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
@@ -1757,8 +1794,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1757 1794
1758 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 1795 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1759 unsigned irq, value, is_in, irqstat; 1796 unsigned irq, value, is_in, irqstat;
1797 const char *label;
1760 1798
1761 if (!(bank->reserved_map & mask)) 1799 label = gpiochip_is_requested(&bank->chip, j);
1800 if (!label)
1762 continue; 1801 continue;
1763 1802
1764 irq = bank->virtual_irq_start + j; 1803 irq = bank->virtual_irq_start + j;
@@ -1766,13 +1805,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1766 is_in = gpio_is_input(bank, mask); 1805 is_in = gpio_is_input(bank, mask);
1767 1806
1768 if (bank_is_mpuio(bank)) 1807 if (bank_is_mpuio(bank))
1769 seq_printf(s, "MPUIO %2d: ", j); 1808 seq_printf(s, "MPUIO %2d ", j);
1770 else 1809 else
1771 seq_printf(s, "GPIO %3d: ", gpio); 1810 seq_printf(s, "GPIO %3d ", gpio);
1772 seq_printf(s, "%s %s", 1811 seq_printf(s, "(%10s): %s %s",
1812 label,
1773 is_in ? "in " : "out", 1813 is_in ? "in " : "out",
1774 value ? "hi" : "lo"); 1814 value ? "hi" : "lo");
1775 1815
1816/* FIXME for at least omap2, show pullup/pulldown state */
1817
1776 irqstat = irq_desc[irq].status; 1818 irqstat = irq_desc[irq].status;
1777 if (is_in && ((bank->suspend_wakeup & mask) 1819 if (is_in && ((bank->suspend_wakeup & mask)
1778 || irqstat & IRQ_TYPE_SENSE_MASK)) { 1820 || irqstat & IRQ_TYPE_SENSE_MASK)) {
@@ -1795,10 +1837,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1795 trigger = "high"; 1837 trigger = "high";
1796 break; 1838 break;
1797 case IRQ_TYPE_NONE: 1839 case IRQ_TYPE_NONE:
1798 trigger = "(unspecified)"; 1840 trigger = "(?)";
1799 break; 1841 break;
1800 } 1842 }
1801 seq_printf(s, ", irq-%d %s%s", 1843 seq_printf(s, ", irq-%d %-8s%s",
1802 irq, trigger, 1844 irq, trigger,
1803 (bank->suspend_wakeup & mask) 1845 (bank->suspend_wakeup & mask)
1804 ? " wakeup" : ""); 1846 ? " wakeup" : "");
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 75211f20ccb..6f3f459731c 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -3,9 +3,9 @@
3 * 3 *
4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h 4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5 * 5 *
6 * Copyright (C) 2003 - 2005 Nokia Corporation 6 * Copyright (C) 2003 - 2008 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
@@ -32,21 +32,17 @@
32 32
33#ifdef CONFIG_OMAP_MUX 33#ifdef CONFIG_OMAP_MUX
34 34
35#define OMAP24XX_L4_BASE 0x48000000 35static struct omap_mux_cfg *mux_cfg;
36#define OMAP24XX_PULL_ENA (1 << 3)
37#define OMAP24XX_PULL_UP (1 << 4)
38 36
39static struct pin_config * pin_table; 37int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
40static unsigned long pin_table_sz;
41
42extern struct pin_config * omap730_pins;
43extern struct pin_config * omap1xxx_pins;
44extern struct pin_config * omap24xx_pins;
45
46int __init omap_mux_register(struct pin_config * pins, unsigned long size)
47{ 38{
48 pin_table = pins; 39 if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
49 pin_table_sz = size; 40 || !arch_mux_cfg->cfg_reg) {
41 printk(KERN_ERR "Invalid pin table\n");
42 return -EINVAL;
43 }
44
45 mux_cfg = arch_mux_cfg;
50 46
51 return 0; 47 return 0;
52} 48}
@@ -56,152 +52,26 @@ int __init omap_mux_register(struct pin_config * pins, unsigned long size)
56 */ 52 */
57int __init_or_module omap_cfg_reg(const unsigned long index) 53int __init_or_module omap_cfg_reg(const unsigned long index)
58{ 54{
59 static DEFINE_SPINLOCK(mux_spin_lock); 55 struct pin_config *reg;
60
61 unsigned long flags;
62 struct pin_config *cfg;
63 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
64 pull_orig = 0, pull = 0;
65 unsigned int mask, warn = 0;
66 56
67 if (!pin_table) 57 if (mux_cfg == NULL) {
68 BUG(); 58 printk(KERN_ERR "Pin mux table not initialized\n");
59 return -ENODEV;
60 }
69 61
70 if (index >= pin_table_sz) { 62 if (index >= mux_cfg->size) {
71 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 63 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
72 index, pin_table_sz); 64 index, mux_cfg->size);
73 dump_stack(); 65 dump_stack();
74 return -ENODEV; 66 return -ENODEV;
75 } 67 }
76 68
77 cfg = (struct pin_config *)&pin_table[index]; 69 reg = (struct pin_config *)&mux_cfg->pins[index];
78 if (cpu_is_omap24xx()) {
79 u8 reg = 0;
80
81 reg |= cfg->mask & 0x7;
82 if (cfg->pull_val)
83 reg |= OMAP24XX_PULL_ENA;
84 if(cfg->pu_pd_val)
85 reg |= OMAP24XX_PULL_UP;
86#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
87 {
88 u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
89 u8 debug = 0;
90
91#ifdef CONFIG_OMAP_MUX_DEBUG
92 debug = cfg->debug;
93#endif
94 warn = (orig != reg);
95 if (debug || warn)
96 printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
97 cfg->name,
98 OMAP24XX_L4_BASE + cfg->mux_reg,
99 orig, reg);
100 }
101#endif
102 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
103 70
104 return 0; 71 if (!mux_cfg->cfg_reg)
105 } 72 return -ENODEV;
106
107 /* Check the mux register in question */
108 if (cfg->mux_reg) {
109 unsigned tmp1, tmp2;
110
111 spin_lock_irqsave(&mux_spin_lock, flags);
112 reg_orig = omap_readl(cfg->mux_reg);
113
114 /* The mux registers always seem to be 3 bits long */
115 mask = (0x7 << cfg->mask_offset);
116 tmp1 = reg_orig & mask;
117 reg = reg_orig & ~mask;
118
119 tmp2 = (cfg->mask << cfg->mask_offset);
120 reg |= tmp2;
121
122 if (tmp1 != tmp2)
123 warn = 1;
124
125 omap_writel(reg, cfg->mux_reg);
126 spin_unlock_irqrestore(&mux_spin_lock, flags);
127 }
128
129 /* Check for pull up or pull down selection on 1610 */
130 if (!cpu_is_omap15xx()) {
131 if (cfg->pu_pd_reg && cfg->pull_val) {
132 spin_lock_irqsave(&mux_spin_lock, flags);
133 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
134 mask = 1 << cfg->pull_bit;
135
136 if (cfg->pu_pd_val) {
137 if (!(pu_pd_orig & mask))
138 warn = 1;
139 /* Use pull up */
140 pu_pd = pu_pd_orig | mask;
141 } else {
142 if (pu_pd_orig & mask)
143 warn = 1;
144 /* Use pull down */
145 pu_pd = pu_pd_orig & ~mask;
146 }
147 omap_writel(pu_pd, cfg->pu_pd_reg);
148 spin_unlock_irqrestore(&mux_spin_lock, flags);
149 }
150 }
151
152 /* Check for an associated pull down register */
153 if (cfg->pull_reg) {
154 spin_lock_irqsave(&mux_spin_lock, flags);
155 pull_orig = omap_readl(cfg->pull_reg);
156 mask = 1 << cfg->pull_bit;
157
158 if (cfg->pull_val) {
159 if (pull_orig & mask)
160 warn = 1;
161 /* Low bit = pull enabled */
162 pull = pull_orig & ~mask;
163 } else {
164 if (!(pull_orig & mask))
165 warn = 1;
166 /* High bit = pull disabled */
167 pull = pull_orig | mask;
168 }
169
170 omap_writel(pull, cfg->pull_reg);
171 spin_unlock_irqrestore(&mux_spin_lock, flags);
172 }
173
174 if (warn) {
175#ifdef CONFIG_OMAP_MUX_WARNINGS
176 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
177#endif
178 }
179
180#ifdef CONFIG_OMAP_MUX_DEBUG
181 if (cfg->debug || warn) {
182 printk("MUX: Setting register %s\n", cfg->name);
183 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
184 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
185
186 if (!cpu_is_omap15xx()) {
187 if (cfg->pu_pd_reg && cfg->pull_val) {
188 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
189 cfg->pu_pd_name, cfg->pu_pd_reg,
190 pu_pd_orig, pu_pd);
191 }
192 }
193
194 if (cfg->pull_reg)
195 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
196 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
197 }
198#endif
199 73
200#ifdef CONFIG_OMAP_MUX_ERRORS 74 return mux_cfg->cfg_reg(reg);
201 return warn ? -ETXTBSY : 0;
202#else
203 return 0;
204#endif
205} 75}
206EXPORT_SYMBOL(omap_cfg_reg); 76EXPORT_SYMBOL(omap_cfg_reg);
207#else 77#else
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a5aedf964b8..a619475c4b7 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -33,6 +33,7 @@
33#include <asm/system.h> 33#include <asm/system.h>
34#include <asm/hardware.h> 34#include <asm/hardware.h>
35 35
36#include <asm/arch/control.h>
36#include <asm/arch/mux.h> 37#include <asm/arch/mux.h>
37#include <asm/arch/usb.h> 38#include <asm/arch/usb.h>
38#include <asm/arch/board.h> 39#include <asm/arch/board.h>
@@ -76,7 +77,7 @@
76 77
77/*-------------------------------------------------------------------------*/ 78/*-------------------------------------------------------------------------*/
78 79
79#ifdef CONFIG_ARCH_OMAP_OTG 80#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
80 81
81static struct otg_transceiver *xceiv; 82static struct otg_transceiver *xceiv;
82 83
@@ -110,12 +111,48 @@ EXPORT_SYMBOL(otg_set_transceiver);
110 111
111#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) 112#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
112 113
114static void omap2_usb_devconf_clear(u8 port, u32 mask)
115{
116 u32 r;
117
118 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
119 r &= ~USBTXWRMODEI(port, mask);
120 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
121}
122
123static void omap2_usb_devconf_set(u8 port, u32 mask)
124{
125 u32 r;
126
127 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
128 r |= USBTXWRMODEI(port, mask);
129 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
130}
131
132static void omap2_usb2_disable_5pinbitll(void)
133{
134 u32 r;
135
136 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
137 r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
138 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
139}
140
141static void omap2_usb2_enable_5pinunitll(void)
142{
143 u32 r;
144
145 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
146 r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
147 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
148}
149
113static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) 150static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
114{ 151{
115 u32 syscon1 = 0; 152 u32 syscon1 = 0;
116 153
117 if (cpu_is_omap24xx()) 154 if (cpu_is_omap24xx())
118 CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL); 155 omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
119 156
120 if (nwires == 0) { 157 if (nwires == 0) {
121 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { 158 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
@@ -187,19 +224,19 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
187 case 3: 224 case 3:
188 syscon1 = 2; 225 syscon1 = 2;
189 if (cpu_is_omap24xx()) 226 if (cpu_is_omap24xx())
190 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); 227 omap2_usb_devconf_set(0, USB_BIDIR);
191 break; 228 break;
192 case 4: 229 case 4:
193 syscon1 = 1; 230 syscon1 = 1;
194 if (cpu_is_omap24xx()) 231 if (cpu_is_omap24xx())
195 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR); 232 omap2_usb_devconf_set(0, USB_BIDIR);
196 break; 233 break;
197 case 6: 234 case 6:
198 syscon1 = 3; 235 syscon1 = 3;
199 if (cpu_is_omap24xx()) { 236 if (cpu_is_omap24xx()) {
200 omap_cfg_reg(J19_24XX_USB0_VP); 237 omap_cfg_reg(J19_24XX_USB0_VP);
201 omap_cfg_reg(K20_24XX_USB0_VM); 238 omap_cfg_reg(K20_24XX_USB0_VM);
202 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR); 239 omap2_usb_devconf_set(0, USB_UNIDIR);
203 } else { 240 } else {
204 omap_cfg_reg(AA9_USB0_VP); 241 omap_cfg_reg(AA9_USB0_VP);
205 omap_cfg_reg(R9_USB0_VM); 242 omap_cfg_reg(R9_USB0_VM);
@@ -220,7 +257,7 @@ static u32 __init omap_usb1_init(unsigned nwires)
220 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) 257 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
221 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; 258 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
222 if (cpu_is_omap24xx()) 259 if (cpu_is_omap24xx())
223 CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL); 260 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
224 261
225 if (nwires == 0) 262 if (nwires == 0)
226 return 0; 263 return 0;
@@ -261,17 +298,17 @@ static u32 __init omap_usb1_init(unsigned nwires)
261 * this TLL link is not using DP/DM 298 * this TLL link is not using DP/DM
262 */ 299 */
263 syscon1 = 1; 300 syscon1 = 1;
264 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL); 301 omap2_usb_devconf_set(1, USB_BIDIR_TLL);
265 break; 302 break;
266 case 3: 303 case 3:
267 syscon1 = 2; 304 syscon1 = 2;
268 if (cpu_is_omap24xx()) 305 if (cpu_is_omap24xx())
269 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); 306 omap2_usb_devconf_set(1, USB_BIDIR);
270 break; 307 break;
271 case 4: 308 case 4:
272 syscon1 = 1; 309 syscon1 = 1;
273 if (cpu_is_omap24xx()) 310 if (cpu_is_omap24xx())
274 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR); 311 omap2_usb_devconf_set(1, USB_BIDIR);
275 break; 312 break;
276 case 6: 313 case 6:
277 if (cpu_is_omap24xx()) 314 if (cpu_is_omap24xx())
@@ -295,8 +332,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
295 u32 syscon1 = 0; 332 u32 syscon1 = 0;
296 333
297 if (cpu_is_omap24xx()) { 334 if (cpu_is_omap24xx()) {
298 CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL) 335 omap2_usb2_disable_5pinbitll();
299 | USBT2TLL5PI);
300 alt_pingroup = 0; 336 alt_pingroup = 0;
301 } 337 }
302 338
@@ -343,17 +379,17 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
343 * this TLL link is not using DP/DM 379 * this TLL link is not using DP/DM
344 */ 380 */
345 syscon1 = 1; 381 syscon1 = 1;
346 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL); 382 omap2_usb_devconf_set(2, USB_BIDIR_TLL);
347 break; 383 break;
348 case 3: 384 case 3:
349 syscon1 = 2; 385 syscon1 = 2;
350 if (cpu_is_omap24xx()) 386 if (cpu_is_omap24xx())
351 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); 387 omap2_usb_devconf_set(2, USB_BIDIR);
352 break; 388 break;
353 case 4: 389 case 4:
354 syscon1 = 1; 390 syscon1 = 1;
355 if (cpu_is_omap24xx()) 391 if (cpu_is_omap24xx())
356 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR); 392 omap2_usb_devconf_set(2, USB_BIDIR);
357 break; 393 break;
358 case 5: 394 case 5:
359 if (!cpu_is_omap24xx()) 395 if (!cpu_is_omap24xx())
@@ -364,8 +400,7 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
364 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} 400 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
365 */ 401 */
366 syscon1 = 3; 402 syscon1 = 3;
367 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL) 403 omap2_usb2_enable_5pinunitll();
368 | USBT2TLL5PI;
369 break; 404 break;
370 case 6: 405 case 6:
371 if (cpu_is_omap24xx()) 406 if (cpu_is_omap24xx())
diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
index e66a07a928c..2687b730e2d 100644
--- a/arch/avr32/kernel/setup.c
+++ b/arch/avr32/kernel/setup.c
@@ -163,6 +163,7 @@ add_reserved_region(resource_size_t start, resource_size_t end,
163 new->start = start; 163 new->start = start;
164 new->end = end; 164 new->end = end;
165 new->name = name; 165 new->name = name;
166 new->sibling = next;
166 new->flags = IORESOURCE_MEM; 167 new->flags = IORESOURCE_MEM;
167 168
168 *pprev = new; 169 *pprev = new;
diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c
index cf6f686d9b0..b835c4c0136 100644
--- a/arch/avr32/kernel/traps.c
+++ b/arch/avr32/kernel/traps.c
@@ -178,6 +178,7 @@ static int do_cop_absent(u32 insn)
178 return 0; 178 return 0;
179} 179}
180 180
181#ifdef CONFIG_BUG
181int is_valid_bugaddr(unsigned long pc) 182int is_valid_bugaddr(unsigned long pc)
182{ 183{
183 unsigned short opcode; 184 unsigned short opcode;
@@ -189,6 +190,7 @@ int is_valid_bugaddr(unsigned long pc)
189 190
190 return opcode == AVR32_BUG_OPCODE; 191 return opcode == AVR32_BUG_OPCODE;
191} 192}
193#endif
192 194
193asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs) 195asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
194{ 196{
@@ -197,6 +199,7 @@ asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
197 void __user *pc; 199 void __user *pc;
198 long code; 200 long code;
199 201
202#ifdef CONFIG_BUG
200 if (!user_mode(regs) && (ecr == ECR_ILLEGAL_OPCODE)) { 203 if (!user_mode(regs) && (ecr == ECR_ILLEGAL_OPCODE)) {
201 enum bug_trap_type type; 204 enum bug_trap_type type;
202 205
@@ -211,6 +214,7 @@ asmlinkage void do_illegal_opcode(unsigned long ecr, struct pt_regs *regs)
211 die("Kernel BUG", regs, SIGKILL); 214 die("Kernel BUG", regs, SIGKILL);
212 } 215 }
213 } 216 }
217#endif
214 218
215 local_irq_enable(); 219 local_irq_enable();
216 220
diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S
index d3b9253d862..bf35f33e48c 100644
--- a/arch/frv/kernel/entry-table.S
+++ b/arch/frv/kernel/entry-table.S
@@ -316,8 +316,14 @@ __trap_fixup_kernel_data_tlb_miss:
316 .section .trap.vector 316 .section .trap.vector
317 .org TBR_TT_TRAP0 >> 2 317 .org TBR_TT_TRAP0 >> 2
318 .long system_call 318 .long system_call
319 .rept 126 319 .rept 119
320 .long __entry_unsupported_trap 320 .long __entry_unsupported_trap
321 .endr 321 .endr
322
323 # userspace atomic op emulation, traps 120-126
324 .rept 7
325 .long __entry_atomic_op
326 .endr
327
322 .org TBR_TT_BREAK >> 2 328 .org TBR_TT_BREAK >> 2
323 .long __entry_debug_exception 329 .long __entry_debug_exception
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index f36d7f4a7c2..b8a4b94779b 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -656,6 +656,26 @@ __entry_debug_exception:
656 656
657############################################################################### 657###############################################################################
658# 658#
659# handle atomic operation emulation for userspace
660#
661###############################################################################
662 .globl __entry_atomic_op
663__entry_atomic_op:
664 LEDS 0x6012
665 sethi.p %hi(atomic_operation),gr5
666 setlo %lo(atomic_operation),gr5
667 movsg esfr1,gr8
668 movsg epcr0,gr9
669 movsg esr0,gr10
670
671 # now that we've accessed the exception regs, we can enable exceptions
672 movsg psr,gr4
673 ori gr4,#PSR_ET,gr4
674 movgs gr4,psr
675 jmpl @(gr5,gr0) ; call atomic_operation(esfr1,epcr0,esr0)
676
677###############################################################################
678#
659# handle media exception 679# handle media exception
660# 680#
661############################################################################### 681###############################################################################
diff --git a/arch/frv/kernel/head.inc b/arch/frv/kernel/head.inc
index d424cd2eb21..bff66628b99 100644
--- a/arch/frv/kernel/head.inc
+++ b/arch/frv/kernel/head.inc
@@ -46,5 +46,5 @@
46#ifdef CONFIG_MMU 46#ifdef CONFIG_MMU
47__sdram_base = 0x00000000 /* base address to which SDRAM relocated */ 47__sdram_base = 0x00000000 /* base address to which SDRAM relocated */
48#else 48#else
49__sdram_base = 0xc0000000 /* base address to which SDRAM relocated */ 49__sdram_base = __page_offset /* base address to which SDRAM relocated */
50#endif 50#endif
diff --git a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
index b5275fa9cd0..b06668670fc 100644
--- a/arch/frv/kernel/switch_to.S
+++ b/arch/frv/kernel/switch_to.S
@@ -102,13 +102,6 @@ __switch_to:
102 movgs gr14,lr 102 movgs gr14,lr
103 bar 103 bar
104 104
105 srli gr15,#28,gr5
106 subicc gr5,#0xc,gr0,icc0
107 beq icc0,#0,111f
108 break
109 nop
110111:
111
112 # jump to __switch_back or ret_from_fork as appropriate 105 # jump to __switch_back or ret_from_fork as appropriate
113 # - move prev to GR8 106 # - move prev to GR8
114 movgs gr4,psr 107 movgs gr4,psr
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
index 2e6098c8557..2f7e66877f3 100644
--- a/arch/frv/kernel/traps.c
+++ b/arch/frv/kernel/traps.c
@@ -102,6 +102,233 @@ asmlinkage void illegal_instruction(unsigned long esfr1, unsigned long epcr0, un
102 102
103/*****************************************************************************/ 103/*****************************************************************************/
104/* 104/*
105 * handle atomic operations with errors
106 * - arguments in gr8, gr9, gr10
107 * - original memory value placed in gr5
108 * - replacement memory value placed in gr9
109 */
110asmlinkage void atomic_operation(unsigned long esfr1, unsigned long epcr0,
111 unsigned long esr0)
112{
113 static DEFINE_SPINLOCK(atomic_op_lock);
114 unsigned long x, y, z, *p;
115 mm_segment_t oldfs;
116 siginfo_t info;
117 int ret;
118
119 y = 0;
120 z = 0;
121
122 oldfs = get_fs();
123 if (!user_mode(__frame))
124 set_fs(KERNEL_DS);
125
126 switch (__frame->tbr & TBR_TT) {
127 /* TIRA gr0,#120
128 * u32 __atomic_user_cmpxchg32(u32 *ptr, u32 test, u32 new)
129 */
130 case TBR_TT_ATOMIC_CMPXCHG32:
131 p = (unsigned long *) __frame->gr8;
132 x = __frame->gr9;
133 y = __frame->gr10;
134
135 for (;;) {
136 ret = get_user(z, p);
137 if (ret < 0)
138 goto error;
139
140 if (z != x)
141 goto done;
142
143 spin_lock_irq(&atomic_op_lock);
144
145 if (__get_user(z, p) == 0) {
146 if (z != x)
147 goto done2;
148
149 if (__put_user(y, p) == 0)
150 goto done2;
151 goto error2;
152 }
153
154 spin_unlock_irq(&atomic_op_lock);
155 }
156
157 /* TIRA gr0,#121
158 * u32 __atomic_kernel_xchg32(void *v, u32 new)
159 */
160 case TBR_TT_ATOMIC_XCHG32:
161 p = (unsigned long *) __frame->gr8;
162 y = __frame->gr9;
163
164 for (;;) {
165 ret = get_user(z, p);
166 if (ret < 0)
167 goto error;
168
169 spin_lock_irq(&atomic_op_lock);
170
171 if (__get_user(z, p) == 0) {
172 if (__put_user(y, p) == 0)
173 goto done2;
174 goto error2;
175 }
176
177 spin_unlock_irq(&atomic_op_lock);
178 }
179
180 /* TIRA gr0,#122
181 * ulong __atomic_kernel_XOR_return(ulong i, ulong *v)
182 */
183 case TBR_TT_ATOMIC_XOR:
184 p = (unsigned long *) __frame->gr8;
185 x = __frame->gr9;
186
187 for (;;) {
188 ret = get_user(z, p);
189 if (ret < 0)
190 goto error;
191
192 spin_lock_irq(&atomic_op_lock);
193
194 if (__get_user(z, p) == 0) {
195 y = x ^ z;
196 if (__put_user(y, p) == 0)
197 goto done2;
198 goto error2;
199 }
200
201 spin_unlock_irq(&atomic_op_lock);
202 }
203
204 /* TIRA gr0,#123
205 * ulong __atomic_kernel_OR_return(ulong i, ulong *v)
206 */
207 case TBR_TT_ATOMIC_OR:
208 p = (unsigned long *) __frame->gr8;
209 x = __frame->gr9;
210
211 for (;;) {
212 ret = get_user(z, p);
213 if (ret < 0)
214 goto error;
215
216 spin_lock_irq(&atomic_op_lock);
217
218 if (__get_user(z, p) == 0) {
219 y = x ^ z;
220 if (__put_user(y, p) == 0)
221 goto done2;
222 goto error2;
223 }
224
225 spin_unlock_irq(&atomic_op_lock);
226 }
227
228 /* TIRA gr0,#124
229 * ulong __atomic_kernel_AND_return(ulong i, ulong *v)
230 */
231 case TBR_TT_ATOMIC_AND:
232 p = (unsigned long *) __frame->gr8;
233 x = __frame->gr9;
234
235 for (;;) {
236 ret = get_user(z, p);
237 if (ret < 0)
238 goto error;
239
240 spin_lock_irq(&atomic_op_lock);
241
242 if (__get_user(z, p) == 0) {
243 y = x & z;
244 if (__put_user(y, p) == 0)
245 goto done2;
246 goto error2;
247 }
248
249 spin_unlock_irq(&atomic_op_lock);
250 }
251
252 /* TIRA gr0,#125
253 * int __atomic_user_sub_return(atomic_t *v, int i)
254 */
255 case TBR_TT_ATOMIC_SUB:
256 p = (unsigned long *) __frame->gr8;
257 x = __frame->gr9;
258
259 for (;;) {
260 ret = get_user(z, p);
261 if (ret < 0)
262 goto error;
263
264 spin_lock_irq(&atomic_op_lock);
265
266 if (__get_user(z, p) == 0) {
267 y = z - x;
268 if (__put_user(y, p) == 0)
269 goto done2;
270 goto error2;
271 }
272
273 spin_unlock_irq(&atomic_op_lock);
274 }
275
276 /* TIRA gr0,#126
277 * int __atomic_user_add_return(atomic_t *v, int i)
278 */
279 case TBR_TT_ATOMIC_ADD:
280 p = (unsigned long *) __frame->gr8;
281 x = __frame->gr9;
282
283 for (;;) {
284 ret = get_user(z, p);
285 if (ret < 0)
286 goto error;
287
288 spin_lock_irq(&atomic_op_lock);
289
290 if (__get_user(z, p) == 0) {
291 y = z + x;
292 if (__put_user(y, p) == 0)
293 goto done2;
294 goto error2;
295 }
296
297 spin_unlock_irq(&atomic_op_lock);
298 }
299
300 default:
301 BUG();
302 }
303
304done2:
305 spin_unlock_irq(&atomic_op_lock);
306done:
307 if (!user_mode(__frame))
308 set_fs(oldfs);
309 __frame->gr5 = z;
310 __frame->gr9 = y;
311 return;
312
313error2:
314 spin_unlock_irq(&atomic_op_lock);
315error:
316 if (!user_mode(__frame))
317 set_fs(oldfs);
318 __frame->pc -= 4;
319
320 die_if_kernel("-- Atomic Op Error --\n");
321
322 info.si_signo = SIGSEGV;
323 info.si_code = SEGV_ACCERR;
324 info.si_errno = 0;
325 info.si_addr = (void *) __frame->pc;
326
327 force_sig_info(info.si_signo, &info, current);
328}
329
330/*****************************************************************************/
331/*
105 * 332 *
106 */ 333 */
107asmlinkage void media_exception(unsigned long msr0, unsigned long msr1) 334asmlinkage void media_exception(unsigned long msr0, unsigned long msr1)
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 2cba605cb59..b15173f28a2 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -13,6 +13,8 @@
13# Copyright (C) 1994 by Hamish Macdonald 13# Copyright (C) 1994 by Hamish Macdonald
14# 14#
15 15
16KBUILD_DEFCONFIG := amiga_defconfig
17
16# override top level makefile 18# override top level makefile
17AS += -m68020 19AS += -m68020
18LDFLAGS := -m m68kelf 20LDFLAGS := -m m68kelf
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index 5649fbae430..e4195837136 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:23 2005 4# Wed Apr 2 20:46:06 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-amiga" 27CONFIG_LOCALVERSION="-amiga"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
80CONFIG_M68040=y 128CONFIG_M68040=y
81CONFIG_M68060=y 129CONFIG_M68060=y
82CONFIG_MMU_MOTOROLA=y 130CONFIG_MMU_MOTOROLA=y
83CONFIG_M68KFPU_EMU=y 131# CONFIG_M68KFPU_EMU is not set
84CONFIG_M68KFPU_EMU_EXTRAPREC=y
85# CONFIG_M68KFPU_EMU_ONLY is not set
86# CONFIG_ADVANCED is not set 132# CONFIG_ADVANCED is not set
133CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
134CONFIG_NODES_SHIFT=3
135CONFIG_SELECT_MEMORY_MODEL=y
136# CONFIG_FLATMEM_MANUAL is not set
137CONFIG_DISCONTIGMEM_MANUAL=y
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_DISCONTIGMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141CONFIG_NEED_MULTIPLE_NODES=y
142# CONFIG_SPARSEMEM_STATIC is not set
143# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
144CONFIG_SPLIT_PTLOCK_CPUS=4
145# CONFIG_RESOURCES_64BIT is not set
146CONFIG_ZONE_DMA_FLAG=1
147CONFIG_BOUNCE=y
148CONFIG_VIRT_TO_BUS=y
87 149
88# 150#
89# General setup 151# General setup
@@ -97,47 +159,288 @@ CONFIG_AMIGA_PCMCIA=y
97CONFIG_PROC_HARDWARE=y 159CONFIG_PROC_HARDWARE=y
98CONFIG_ISA=y 160CONFIG_ISA=y
99CONFIG_GENERIC_ISA_DMA=y 161CONFIG_GENERIC_ISA_DMA=y
162CONFIG_ZONE_DMA=y
163# CONFIG_ARCH_SUPPORTS_MSI is not set
100CONFIG_ZORRO_NAMES=y 164CONFIG_ZORRO_NAMES=y
101 165
102# 166#
103# Device Drivers 167# Networking
104# 168#
169CONFIG_NET=y
105 170
106# 171#
107# Generic Driver Options 172# Networking options
108# 173#
109CONFIG_STANDALONE=y 174CONFIG_PACKET=y
110CONFIG_PREVENT_FIRMWARE_BUILD=y 175# CONFIG_PACKET_MMAP is not set
111CONFIG_FW_LOADER=m 176CONFIG_UNIX=y
112# CONFIG_DEBUG_DRIVER is not set 177CONFIG_XFRM=y
178# CONFIG_XFRM_USER is not set
179# CONFIG_XFRM_SUB_POLICY is not set
180CONFIG_XFRM_MIGRATE=y
181# CONFIG_XFRM_STATISTICS is not set
182CONFIG_NET_KEY=y
183CONFIG_NET_KEY_MIGRATE=y
184CONFIG_INET=y
185# CONFIG_IP_MULTICAST is not set
186# CONFIG_IP_ADVANCED_ROUTER is not set
187CONFIG_IP_FIB_HASH=y
188# CONFIG_IP_PNP is not set
189CONFIG_NET_IPIP=m
190CONFIG_NET_IPGRE=m
191# CONFIG_ARPD is not set
192CONFIG_SYN_COOKIES=y
193CONFIG_INET_AH=m
194CONFIG_INET_ESP=m
195CONFIG_INET_IPCOMP=m
196CONFIG_INET_XFRM_TUNNEL=m
197CONFIG_INET_TUNNEL=m
198CONFIG_INET_XFRM_MODE_TRANSPORT=m
199CONFIG_INET_XFRM_MODE_TUNNEL=m
200CONFIG_INET_XFRM_MODE_BEET=m
201CONFIG_INET_LRO=m
202CONFIG_INET_DIAG=m
203CONFIG_INET_TCP_DIAG=m
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_CUBIC=y
206CONFIG_DEFAULT_TCP_CONG="cubic"
207# CONFIG_TCP_MD5SIG is not set
208# CONFIG_IP_VS is not set
209CONFIG_IPV6=m
210CONFIG_IPV6_PRIVACY=y
211CONFIG_IPV6_ROUTER_PREF=y
212CONFIG_IPV6_ROUTE_INFO=y
213# CONFIG_IPV6_OPTIMISTIC_DAD is not set
214CONFIG_INET6_AH=m
215CONFIG_INET6_ESP=m
216CONFIG_INET6_IPCOMP=m
217# CONFIG_IPV6_MIP6 is not set
218CONFIG_INET6_XFRM_TUNNEL=m
219CONFIG_INET6_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_TRANSPORT=m
221CONFIG_INET6_XFRM_MODE_TUNNEL=m
222CONFIG_INET6_XFRM_MODE_BEET=m
223CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
224CONFIG_IPV6_SIT=m
225CONFIG_IPV6_TUNNEL=m
226# CONFIG_IPV6_MULTIPLE_TABLES is not set
227# CONFIG_NETWORK_SECMARK is not set
228CONFIG_NETFILTER=y
229# CONFIG_NETFILTER_DEBUG is not set
230CONFIG_NETFILTER_ADVANCED=y
231
232#
233# Core Netfilter Configuration
234#
235CONFIG_NETFILTER_NETLINK=m
236CONFIG_NETFILTER_NETLINK_QUEUE=m
237CONFIG_NETFILTER_NETLINK_LOG=m
238CONFIG_NF_CONNTRACK=m
239CONFIG_NF_CT_ACCT=y
240CONFIG_NF_CONNTRACK_MARK=y
241# CONFIG_NF_CONNTRACK_EVENTS is not set
242CONFIG_NF_CT_PROTO_GRE=m
243CONFIG_NF_CT_PROTO_SCTP=m
244CONFIG_NF_CT_PROTO_UDPLITE=m
245CONFIG_NF_CONNTRACK_AMANDA=m
246CONFIG_NF_CONNTRACK_FTP=m
247CONFIG_NF_CONNTRACK_H323=m
248CONFIG_NF_CONNTRACK_IRC=m
249CONFIG_NF_CONNTRACK_NETBIOS_NS=m
250CONFIG_NF_CONNTRACK_PPTP=m
251CONFIG_NF_CONNTRACK_SANE=m
252CONFIG_NF_CONNTRACK_SIP=m
253CONFIG_NF_CONNTRACK_TFTP=m
254# CONFIG_NF_CT_NETLINK is not set
255CONFIG_NETFILTER_XTABLES=m
256CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
257CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
258CONFIG_NETFILTER_XT_TARGET_DSCP=m
259CONFIG_NETFILTER_XT_TARGET_MARK=m
260CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
261CONFIG_NETFILTER_XT_TARGET_NFLOG=m
262CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
263CONFIG_NETFILTER_XT_TARGET_RATEEST=m
264CONFIG_NETFILTER_XT_TARGET_TRACE=m
265CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
266CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
267CONFIG_NETFILTER_XT_MATCH_COMMENT=m
268CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
269CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
270CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
271CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
272CONFIG_NETFILTER_XT_MATCH_DCCP=m
273CONFIG_NETFILTER_XT_MATCH_DSCP=m
274CONFIG_NETFILTER_XT_MATCH_ESP=m
275CONFIG_NETFILTER_XT_MATCH_HELPER=m
276CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
277CONFIG_NETFILTER_XT_MATCH_LENGTH=m
278CONFIG_NETFILTER_XT_MATCH_LIMIT=m
279CONFIG_NETFILTER_XT_MATCH_MAC=m
280CONFIG_NETFILTER_XT_MATCH_MARK=m
281CONFIG_NETFILTER_XT_MATCH_OWNER=m
282CONFIG_NETFILTER_XT_MATCH_POLICY=m
283CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
284CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
285CONFIG_NETFILTER_XT_MATCH_QUOTA=m
286CONFIG_NETFILTER_XT_MATCH_RATEEST=m
287CONFIG_NETFILTER_XT_MATCH_REALM=m
288CONFIG_NETFILTER_XT_MATCH_SCTP=m
289CONFIG_NETFILTER_XT_MATCH_STATE=m
290CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
291CONFIG_NETFILTER_XT_MATCH_STRING=m
292CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
293CONFIG_NETFILTER_XT_MATCH_TIME=m
294CONFIG_NETFILTER_XT_MATCH_U32=m
295CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
113 296
114# 297#
115# Memory Technology Devices (MTD) 298# IP: Netfilter Configuration
116# 299#
117# CONFIG_MTD is not set 300CONFIG_NF_CONNTRACK_IPV4=m
301CONFIG_NF_CONNTRACK_PROC_COMPAT=y
302CONFIG_IP_NF_QUEUE=m
303CONFIG_IP_NF_IPTABLES=m
304CONFIG_IP_NF_MATCH_RECENT=m
305CONFIG_IP_NF_MATCH_ECN=m
306CONFIG_IP_NF_MATCH_AH=m
307CONFIG_IP_NF_MATCH_TTL=m
308CONFIG_IP_NF_MATCH_ADDRTYPE=m
309CONFIG_IP_NF_FILTER=m
310CONFIG_IP_NF_TARGET_REJECT=m
311CONFIG_IP_NF_TARGET_LOG=m
312CONFIG_IP_NF_TARGET_ULOG=m
313CONFIG_NF_NAT=m
314CONFIG_NF_NAT_NEEDED=y
315CONFIG_IP_NF_TARGET_MASQUERADE=m
316CONFIG_IP_NF_TARGET_REDIRECT=m
317CONFIG_IP_NF_TARGET_NETMAP=m
318CONFIG_NF_NAT_SNMP_BASIC=m
319CONFIG_NF_NAT_PROTO_GRE=m
320CONFIG_NF_NAT_FTP=m
321CONFIG_NF_NAT_IRC=m
322CONFIG_NF_NAT_TFTP=m
323CONFIG_NF_NAT_AMANDA=m
324CONFIG_NF_NAT_PPTP=m
325CONFIG_NF_NAT_H323=m
326CONFIG_NF_NAT_SIP=m
327CONFIG_IP_NF_MANGLE=m
328CONFIG_IP_NF_TARGET_ECN=m
329CONFIG_IP_NF_TARGET_TTL=m
330CONFIG_IP_NF_TARGET_CLUSTERIP=m
331CONFIG_IP_NF_RAW=m
332CONFIG_IP_NF_ARPTABLES=m
333CONFIG_IP_NF_ARPFILTER=m
334CONFIG_IP_NF_ARP_MANGLE=m
335
336#
337# IPv6: Netfilter Configuration
338#
339CONFIG_NF_CONNTRACK_IPV6=m
340CONFIG_IP6_NF_QUEUE=m
341CONFIG_IP6_NF_IPTABLES=m
342CONFIG_IP6_NF_MATCH_RT=m
343CONFIG_IP6_NF_MATCH_OPTS=m
344CONFIG_IP6_NF_MATCH_FRAG=m
345CONFIG_IP6_NF_MATCH_HL=m
346CONFIG_IP6_NF_MATCH_IPV6HEADER=m
347CONFIG_IP6_NF_MATCH_AH=m
348CONFIG_IP6_NF_MATCH_MH=m
349CONFIG_IP6_NF_MATCH_EUI64=m
350CONFIG_IP6_NF_FILTER=m
351CONFIG_IP6_NF_TARGET_LOG=m
352CONFIG_IP6_NF_TARGET_REJECT=m
353CONFIG_IP6_NF_MANGLE=m
354CONFIG_IP6_NF_TARGET_HL=m
355CONFIG_IP6_NF_RAW=m
356CONFIG_IP_DCCP=m
357CONFIG_INET_DCCP_DIAG=m
358CONFIG_IP_DCCP_ACKVEC=y
359
360#
361# DCCP CCIDs Configuration (EXPERIMENTAL)
362#
363CONFIG_IP_DCCP_CCID2=m
364# CONFIG_IP_DCCP_CCID2_DEBUG is not set
365CONFIG_IP_DCCP_CCID3=m
366# CONFIG_IP_DCCP_CCID3_DEBUG is not set
367CONFIG_IP_DCCP_CCID3_RTO=100
368CONFIG_IP_DCCP_TFRC_LIB=m
369CONFIG_IP_SCTP=m
370# CONFIG_SCTP_DBG_MSG is not set
371# CONFIG_SCTP_DBG_OBJCNT is not set
372# CONFIG_SCTP_HMAC_NONE is not set
373# CONFIG_SCTP_HMAC_SHA1 is not set
374CONFIG_SCTP_HMAC_MD5=y
375# CONFIG_TIPC is not set
376# CONFIG_ATM is not set
377# CONFIG_BRIDGE is not set
378# CONFIG_VLAN_8021Q is not set
379# CONFIG_DECNET is not set
380CONFIG_LLC=m
381# CONFIG_LLC2 is not set
382# CONFIG_IPX is not set
383CONFIG_ATALK=m
384# CONFIG_DEV_APPLETALK is not set
385# CONFIG_X25 is not set
386# CONFIG_LAPB is not set
387# CONFIG_ECONET is not set
388# CONFIG_WAN_ROUTER is not set
389# CONFIG_NET_SCHED is not set
390CONFIG_NET_CLS_ROUTE=y
118 391
119# 392#
120# Parallel port support 393# Network testing
121# 394#
395# CONFIG_NET_PKTGEN is not set
396# CONFIG_HAMRADIO is not set
397# CONFIG_CAN is not set
398# CONFIG_IRDA is not set
399# CONFIG_BT is not set
400# CONFIG_AF_RXRPC is not set
401
402#
403# Wireless
404#
405# CONFIG_CFG80211 is not set
406CONFIG_WIRELESS_EXT=y
407# CONFIG_MAC80211 is not set
408CONFIG_IEEE80211=m
409# CONFIG_IEEE80211_DEBUG is not set
410CONFIG_IEEE80211_CRYPT_WEP=m
411CONFIG_IEEE80211_CRYPT_CCMP=m
412CONFIG_IEEE80211_CRYPT_TKIP=m
413CONFIG_IEEE80211_SOFTMAC=m
414# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
415# CONFIG_RFKILL is not set
416# CONFIG_NET_9P is not set
417
418#
419# Device Drivers
420#
421
422#
423# Generic Driver Options
424#
425CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430CONFIG_CONNECTOR=m
431# CONFIG_MTD is not set
122CONFIG_PARPORT=m 432CONFIG_PARPORT=m
123# CONFIG_PARPORT_PC is not set 433# CONFIG_PARPORT_PC is not set
124CONFIG_PARPORT_NOT_PC=y
125CONFIG_PARPORT_AMIGA=m 434CONFIG_PARPORT_AMIGA=m
126CONFIG_PARPORT_MFC3=m 435CONFIG_PARPORT_MFC3=m
127# CONFIG_PARPORT_GSC is not set 436# CONFIG_PARPORT_GSC is not set
437# CONFIG_PARPORT_AX88796 is not set
128CONFIG_PARPORT_1284=y 438CONFIG_PARPORT_1284=y
129 439CONFIG_PARPORT_NOT_PC=y
130#
131# Plug and Play support
132#
133# CONFIG_PNP is not set 440# CONFIG_PNP is not set
134 441CONFIG_BLK_DEV=y
135#
136# Block devices
137#
138CONFIG_AMIGA_FLOPPY=y 442CONFIG_AMIGA_FLOPPY=y
139CONFIG_AMIGA_Z2RAM=y 443CONFIG_AMIGA_Z2RAM=y
140# CONFIG_PARIDE is not set
141# CONFIG_BLK_DEV_COW_COMMON is not set 444# CONFIG_BLK_DEV_COW_COMMON is not set
142CONFIG_BLK_DEV_LOOP=y 445CONFIG_BLK_DEV_LOOP=y
143CONFIG_BLK_DEV_CRYPTOLOOP=m 446CONFIG_BLK_DEV_CRYPTOLOOP=m
@@ -145,56 +448,66 @@ CONFIG_BLK_DEV_NBD=m
145CONFIG_BLK_DEV_RAM=y 448CONFIG_BLK_DEV_RAM=y
146CONFIG_BLK_DEV_RAM_COUNT=16 449CONFIG_BLK_DEV_RAM_COUNT=16
147CONFIG_BLK_DEV_RAM_SIZE=4096 450CONFIG_BLK_DEV_RAM_SIZE=4096
148CONFIG_BLK_DEV_INITRD=y 451# CONFIG_BLK_DEV_XIP is not set
149CONFIG_INITRAMFS_SOURCE=""
150CONFIG_CDROM_PKTCDVD=m 452CONFIG_CDROM_PKTCDVD=m
151CONFIG_CDROM_PKTCDVD_BUFFERS=8 453CONFIG_CDROM_PKTCDVD_BUFFERS=8
152# CONFIG_CDROM_PKTCDVD_WCACHE is not set 454# CONFIG_CDROM_PKTCDVD_WCACHE is not set
153
154#
155# IO Schedulers
156#
157CONFIG_IOSCHED_NOOP=y
158CONFIG_IOSCHED_AS=y
159CONFIG_IOSCHED_DEADLINE=y
160CONFIG_IOSCHED_CFQ=y
161CONFIG_ATA_OVER_ETH=m 455CONFIG_ATA_OVER_ETH=m
162 456CONFIG_MISC_DEVICES=y
163# 457# CONFIG_EEPROM_93CX6 is not set
164# ATA/ATAPI/MFM/RLL support 458# CONFIG_ENCLOSURE_SERVICES is not set
165# 459CONFIG_HAVE_IDE=y
166CONFIG_IDE=y 460CONFIG_IDE=y
167CONFIG_BLK_DEV_IDE=y 461CONFIG_BLK_DEV_IDE=y
168 462
169# 463#
170# Please see Documentation/ide.txt for help/info on IDE drives 464# Please see Documentation/ide/ide.txt for help/info on IDE drives
171# 465#
172# CONFIG_BLK_DEV_IDE_SATA is not set 466# CONFIG_BLK_DEV_IDE_SATA is not set
173CONFIG_BLK_DEV_IDEDISK=y 467CONFIG_BLK_DEV_IDEDISK=y
174# CONFIG_IDEDISK_MULTI_MODE is not set 468# CONFIG_IDEDISK_MULTI_MODE is not set
175CONFIG_BLK_DEV_IDECD=y 469CONFIG_BLK_DEV_IDECD=y
176CONFIG_BLK_DEV_IDETAPE=m 470CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
471# CONFIG_BLK_DEV_IDETAPE is not set
177CONFIG_BLK_DEV_IDEFLOPPY=m 472CONFIG_BLK_DEV_IDEFLOPPY=m
178# CONFIG_BLK_DEV_IDESCSI is not set 473# CONFIG_BLK_DEV_IDESCSI is not set
179# CONFIG_IDE_TASK_IOCTL is not set 474# CONFIG_IDE_TASK_IOCTL is not set
475CONFIG_IDE_PROC_FS=y
180 476
181# 477#
182# IDE chipset support/bugfixes 478# IDE chipset support/bugfixes
183# 479#
184CONFIG_IDE_GENERIC=y 480# CONFIG_IDE_GENERIC is not set
185# CONFIG_IDE_ARM is not set 481# CONFIG_BLK_DEV_PLATFORM is not set
186CONFIG_BLK_DEV_GAYLE=y 482CONFIG_BLK_DEV_GAYLE=y
187CONFIG_BLK_DEV_IDEDOUBLER=y 483CONFIG_BLK_DEV_IDEDOUBLER=y
188CONFIG_BLK_DEV_BUDDHA=y 484CONFIG_BLK_DEV_BUDDHA=y
189# CONFIG_IDE_CHIPSETS is not set 485
486#
487# Other IDE chipsets support
488#
489
490#
491# Note: most of these also require special kernel boot parameters
492#
493# CONFIG_BLK_DEV_4DRIVES is not set
494# CONFIG_BLK_DEV_ALI14XX is not set
495# CONFIG_BLK_DEV_DTC2278 is not set
496# CONFIG_BLK_DEV_HT6560B is not set
497# CONFIG_BLK_DEV_QD65XX is not set
498# CONFIG_BLK_DEV_UMC8672 is not set
190# CONFIG_BLK_DEV_IDEDMA is not set 499# CONFIG_BLK_DEV_IDEDMA is not set
191# CONFIG_IDEDMA_AUTO is not set 500# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
192# CONFIG_BLK_DEV_HD is not set 501# CONFIG_BLK_DEV_HD is not set
193 502
194# 503#
195# SCSI device support 504# SCSI device support
196# 505#
506CONFIG_RAID_ATTRS=m
197CONFIG_SCSI=y 507CONFIG_SCSI=y
508CONFIG_SCSI_DMA=y
509CONFIG_SCSI_TGT=m
510# CONFIG_SCSI_NETLINK is not set
198CONFIG_SCSI_PROC_FS=y 511CONFIG_SCSI_PROC_FS=y
199 512
200# 513#
@@ -206,6 +519,7 @@ CONFIG_CHR_DEV_OSST=m
206CONFIG_BLK_DEV_SR=y 519CONFIG_BLK_DEV_SR=y
207CONFIG_BLK_DEV_SR_VENDOR=y 520CONFIG_BLK_DEV_SR_VENDOR=y
208CONFIG_CHR_DEV_SG=m 521CONFIG_CHR_DEV_SG=m
522# CONFIG_CHR_DEV_SCH is not set
209 523
210# 524#
211# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 525# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -213,30 +527,34 @@ CONFIG_CHR_DEV_SG=m
213# CONFIG_SCSI_MULTI_LUN is not set 527# CONFIG_SCSI_MULTI_LUN is not set
214CONFIG_SCSI_CONSTANTS=y 528CONFIG_SCSI_CONSTANTS=y
215# CONFIG_SCSI_LOGGING is not set 529# CONFIG_SCSI_LOGGING is not set
530# CONFIG_SCSI_SCAN_ASYNC is not set
531CONFIG_SCSI_WAIT_SCAN=m
216 532
217# 533#
218# SCSI Transport Attributes 534# SCSI Transports
219# 535#
220# CONFIG_SCSI_SPI_ATTRS is not set 536CONFIG_SCSI_SPI_ATTRS=y
221# CONFIG_SCSI_FC_ATTRS is not set 537# CONFIG_SCSI_FC_ATTRS is not set
222# CONFIG_SCSI_ISCSI_ATTRS is not set 538CONFIG_SCSI_ISCSI_ATTRS=m
223 539CONFIG_SCSI_SAS_ATTRS=m
224# 540CONFIG_SCSI_SAS_LIBSAS=m
225# SCSI low-level drivers 541CONFIG_SCSI_SAS_HOST_SMP=y
226# 542# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
543CONFIG_SCSI_SRP_ATTRS=m
544CONFIG_SCSI_SRP_TGT_ATTRS=y
545CONFIG_SCSI_LOWLEVEL=y
546CONFIG_ISCSI_TCP=m
227# CONFIG_SCSI_AHA152X is not set 547# CONFIG_SCSI_AHA152X is not set
228# CONFIG_SCSI_AIC7XXX_OLD is not set 548# CONFIG_SCSI_AIC7XXX_OLD is not set
549# CONFIG_SCSI_ADVANSYS is not set
229# CONFIG_SCSI_IN2000 is not set 550# CONFIG_SCSI_IN2000 is not set
230# CONFIG_SCSI_SATA is not set
231# CONFIG_SCSI_DTC3280 is not set 551# CONFIG_SCSI_DTC3280 is not set
232# CONFIG_SCSI_FUTURE_DOMAIN is not set 552# CONFIG_SCSI_FUTURE_DOMAIN is not set
233# CONFIG_SCSI_GENERIC_NCR5380 is not set 553# CONFIG_SCSI_GENERIC_NCR5380 is not set
234# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set 554# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
235# CONFIG_SCSI_PPA is not set
236# CONFIG_SCSI_IMM is not set
237# CONFIG_SCSI_NCR53C406A is not set 555# CONFIG_SCSI_NCR53C406A is not set
556CONFIG_53C700_BE_BUS=y
238# CONFIG_SCSI_PAS16 is not set 557# CONFIG_SCSI_PAS16 is not set
239# CONFIG_SCSI_PSI240I is not set
240# CONFIG_SCSI_QLOGIC_FAS is not set 558# CONFIG_SCSI_QLOGIC_FAS is not set
241# CONFIG_SCSI_SYM53C416 is not set 559# CONFIG_SCSI_SYM53C416 is not set
242# CONFIG_SCSI_T128 is not set 560# CONFIG_SCSI_T128 is not set
@@ -244,243 +562,42 @@ CONFIG_SCSI_CONSTANTS=y
244CONFIG_A3000_SCSI=y 562CONFIG_A3000_SCSI=y
245CONFIG_A2091_SCSI=y 563CONFIG_A2091_SCSI=y
246CONFIG_GVP11_SCSI=y 564CONFIG_GVP11_SCSI=y
247CONFIG_CYBERSTORM_SCSI=y 565CONFIG_SCSI_A4000T=y
248CONFIG_CYBERSTORMII_SCSI=y 566CONFIG_SCSI_ZORRO7XX=y
249CONFIG_BLZ2060_SCSI=y
250CONFIG_BLZ1230_SCSI=y
251CONFIG_FASTLANE_SCSI=y
252CONFIG_OKTAGON_SCSI=y
253
254#
255# Old CD-ROM drivers (not SCSI, not IDE)
256#
257# CONFIG_CD_NO_IDESCSI is not set
258
259#
260# Multi-device support (RAID and LVM)
261#
262CONFIG_MD=y 567CONFIG_MD=y
263CONFIG_BLK_DEV_MD=m 568CONFIG_BLK_DEV_MD=m
264CONFIG_MD_LINEAR=m 569CONFIG_MD_LINEAR=m
265CONFIG_MD_RAID0=m 570CONFIG_MD_RAID0=m
266CONFIG_MD_RAID1=m 571CONFIG_MD_RAID1=m
267# CONFIG_MD_RAID10 is not set 572# CONFIG_MD_RAID10 is not set
268CONFIG_MD_RAID5=m 573CONFIG_MD_RAID456=m
269CONFIG_MD_RAID6=m 574CONFIG_MD_RAID5_RESHAPE=y
270CONFIG_MD_MULTIPATH=m 575CONFIG_MD_MULTIPATH=m
271# CONFIG_MD_FAULTY is not set 576# CONFIG_MD_FAULTY is not set
272CONFIG_BLK_DEV_DM=m 577CONFIG_BLK_DEV_DM=m
578# CONFIG_DM_DEBUG is not set
273CONFIG_DM_CRYPT=m 579CONFIG_DM_CRYPT=m
274CONFIG_DM_SNAPSHOT=m 580CONFIG_DM_SNAPSHOT=m
275CONFIG_DM_MIRROR=m 581CONFIG_DM_MIRROR=m
276CONFIG_DM_ZERO=m 582CONFIG_DM_ZERO=m
277CONFIG_DM_MULTIPATH=m 583CONFIG_DM_MULTIPATH=m
278CONFIG_DM_MULTIPATH_EMC=m 584CONFIG_DM_MULTIPATH_EMC=m
279 585CONFIG_DM_MULTIPATH_RDAC=m
280# 586CONFIG_DM_MULTIPATH_HP=m
281# Fusion MPT device support 587# CONFIG_DM_DELAY is not set
282# 588CONFIG_DM_UEVENT=y
283
284#
285# IEEE 1394 (FireWire) support
286#
287
288#
289# I2O device support
290#
291
292#
293# Networking support
294#
295CONFIG_NET=y
296
297#
298# Networking options
299#
300CONFIG_PACKET=y
301# CONFIG_PACKET_MMAP is not set
302CONFIG_UNIX=y
303CONFIG_NET_KEY=y
304CONFIG_INET=y
305# CONFIG_IP_MULTICAST is not set
306# CONFIG_IP_ADVANCED_ROUTER is not set
307# CONFIG_IP_PNP is not set
308CONFIG_NET_IPIP=m
309CONFIG_NET_IPGRE=m
310# CONFIG_ARPD is not set
311CONFIG_SYN_COOKIES=y
312CONFIG_INET_AH=m
313CONFIG_INET_ESP=m
314CONFIG_INET_IPCOMP=m
315CONFIG_INET_TUNNEL=m
316CONFIG_IP_TCPDIAG=m
317CONFIG_IP_TCPDIAG_IPV6=y
318
319#
320# IP: Virtual Server Configuration
321#
322# CONFIG_IP_VS is not set
323CONFIG_IPV6=m
324CONFIG_IPV6_PRIVACY=y
325CONFIG_INET6_AH=m
326CONFIG_INET6_ESP=m
327CONFIG_INET6_IPCOMP=m
328CONFIG_INET6_TUNNEL=m
329CONFIG_IPV6_TUNNEL=m
330CONFIG_NETFILTER=y
331# CONFIG_NETFILTER_DEBUG is not set
332
333#
334# IP: Netfilter Configuration
335#
336CONFIG_IP_NF_CONNTRACK=m
337# CONFIG_IP_NF_CT_ACCT is not set
338CONFIG_IP_NF_CONNTRACK_MARK=y
339# CONFIG_IP_NF_CT_PROTO_SCTP is not set
340CONFIG_IP_NF_FTP=m
341CONFIG_IP_NF_IRC=m
342CONFIG_IP_NF_TFTP=m
343CONFIG_IP_NF_AMANDA=m
344CONFIG_IP_NF_QUEUE=m
345CONFIG_IP_NF_IPTABLES=m
346CONFIG_IP_NF_MATCH_LIMIT=m
347CONFIG_IP_NF_MATCH_IPRANGE=m
348CONFIG_IP_NF_MATCH_MAC=m
349CONFIG_IP_NF_MATCH_PKTTYPE=m
350CONFIG_IP_NF_MATCH_MARK=m
351CONFIG_IP_NF_MATCH_MULTIPORT=m
352CONFIG_IP_NF_MATCH_TOS=m
353CONFIG_IP_NF_MATCH_RECENT=m
354CONFIG_IP_NF_MATCH_ECN=m
355CONFIG_IP_NF_MATCH_DSCP=m
356CONFIG_IP_NF_MATCH_AH_ESP=m
357CONFIG_IP_NF_MATCH_LENGTH=m
358CONFIG_IP_NF_MATCH_TTL=m
359CONFIG_IP_NF_MATCH_TCPMSS=m
360CONFIG_IP_NF_MATCH_HELPER=m
361CONFIG_IP_NF_MATCH_STATE=m
362CONFIG_IP_NF_MATCH_CONNTRACK=m
363CONFIG_IP_NF_MATCH_OWNER=m
364CONFIG_IP_NF_MATCH_ADDRTYPE=m
365CONFIG_IP_NF_MATCH_REALM=m
366# CONFIG_IP_NF_MATCH_SCTP is not set
367# CONFIG_IP_NF_MATCH_COMMENT is not set
368CONFIG_IP_NF_MATCH_CONNMARK=m
369CONFIG_IP_NF_MATCH_HASHLIMIT=m
370CONFIG_IP_NF_FILTER=m
371CONFIG_IP_NF_TARGET_REJECT=m
372CONFIG_IP_NF_TARGET_LOG=m
373CONFIG_IP_NF_TARGET_ULOG=m
374CONFIG_IP_NF_TARGET_TCPMSS=m
375CONFIG_IP_NF_NAT=m
376CONFIG_IP_NF_NAT_NEEDED=y
377CONFIG_IP_NF_TARGET_MASQUERADE=m
378CONFIG_IP_NF_TARGET_REDIRECT=m
379CONFIG_IP_NF_TARGET_NETMAP=m
380CONFIG_IP_NF_TARGET_SAME=m
381CONFIG_IP_NF_NAT_SNMP_BASIC=m
382CONFIG_IP_NF_NAT_IRC=m
383CONFIG_IP_NF_NAT_FTP=m
384CONFIG_IP_NF_NAT_TFTP=m
385CONFIG_IP_NF_NAT_AMANDA=m
386CONFIG_IP_NF_MANGLE=m
387CONFIG_IP_NF_TARGET_TOS=m
388CONFIG_IP_NF_TARGET_ECN=m
389CONFIG_IP_NF_TARGET_DSCP=m
390CONFIG_IP_NF_TARGET_MARK=m
391CONFIG_IP_NF_TARGET_CLASSIFY=m
392CONFIG_IP_NF_TARGET_CONNMARK=m
393# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
394CONFIG_IP_NF_RAW=m
395CONFIG_IP_NF_TARGET_NOTRACK=m
396CONFIG_IP_NF_ARPTABLES=m
397CONFIG_IP_NF_ARPFILTER=m
398CONFIG_IP_NF_ARP_MANGLE=m
399
400#
401# IPv6: Netfilter Configuration (EXPERIMENTAL)
402#
403CONFIG_IP6_NF_QUEUE=m
404CONFIG_IP6_NF_IPTABLES=m
405CONFIG_IP6_NF_MATCH_LIMIT=m
406CONFIG_IP6_NF_MATCH_MAC=m
407CONFIG_IP6_NF_MATCH_RT=m
408CONFIG_IP6_NF_MATCH_OPTS=m
409CONFIG_IP6_NF_MATCH_FRAG=m
410CONFIG_IP6_NF_MATCH_HL=m
411CONFIG_IP6_NF_MATCH_MULTIPORT=m
412CONFIG_IP6_NF_MATCH_OWNER=m
413CONFIG_IP6_NF_MATCH_MARK=m
414CONFIG_IP6_NF_MATCH_IPV6HEADER=m
415CONFIG_IP6_NF_MATCH_AHESP=m
416CONFIG_IP6_NF_MATCH_LENGTH=m
417CONFIG_IP6_NF_MATCH_EUI64=m
418CONFIG_IP6_NF_FILTER=m
419CONFIG_IP6_NF_TARGET_LOG=m
420CONFIG_IP6_NF_MANGLE=m
421CONFIG_IP6_NF_TARGET_MARK=m
422CONFIG_IP6_NF_RAW=m
423CONFIG_XFRM=y
424CONFIG_XFRM_USER=m
425
426#
427# SCTP Configuration (EXPERIMENTAL)
428#
429CONFIG_IP_SCTP=m
430# CONFIG_SCTP_DBG_MSG is not set
431# CONFIG_SCTP_DBG_OBJCNT is not set
432# CONFIG_SCTP_HMAC_NONE is not set
433# CONFIG_SCTP_HMAC_SHA1 is not set
434CONFIG_SCTP_HMAC_MD5=y
435# CONFIG_ATM is not set
436# CONFIG_BRIDGE is not set
437# CONFIG_VLAN_8021Q is not set
438# CONFIG_DECNET is not set
439CONFIG_LLC=m
440# CONFIG_LLC2 is not set
441CONFIG_IPX=m
442# CONFIG_IPX_INTERN is not set
443CONFIG_ATALK=m
444# CONFIG_DEV_APPLETALK is not set
445# CONFIG_X25 is not set
446# CONFIG_LAPB is not set
447# CONFIG_NET_DIVERT is not set
448# CONFIG_ECONET is not set
449# CONFIG_WAN_ROUTER is not set
450
451#
452# QoS and/or fair queueing
453#
454# CONFIG_NET_SCHED is not set
455CONFIG_NET_CLS_ROUTE=y
456
457#
458# Network testing
459#
460# CONFIG_NET_PKTGEN is not set
461CONFIG_NETPOLL=y
462# CONFIG_NETPOLL_RX is not set
463# CONFIG_NETPOLL_TRAP is not set
464CONFIG_NET_POLL_CONTROLLER=y
465# CONFIG_HAMRADIO is not set
466# CONFIG_IRDA is not set
467# CONFIG_BT is not set
468CONFIG_NETDEVICES=y 589CONFIG_NETDEVICES=y
590# CONFIG_NETDEVICES_MULTIQUEUE is not set
469CONFIG_DUMMY=m 591CONFIG_DUMMY=m
470# CONFIG_BONDING is not set 592# CONFIG_BONDING is not set
593CONFIG_MACVLAN=m
471CONFIG_EQUALIZER=m 594CONFIG_EQUALIZER=m
472# CONFIG_TUN is not set 595# CONFIG_TUN is not set
473 596CONFIG_VETH=m
474#
475# ARCnet devices
476#
477# CONFIG_ARCNET is not set 597# CONFIG_ARCNET is not set
478 598# CONFIG_PHYLIB is not set
479#
480# Ethernet (10 or 100Mbit)
481#
482CONFIG_NET_ETHERNET=y 599CONFIG_NET_ETHERNET=y
483CONFIG_MII=m 600# CONFIG_MII is not set
484CONFIG_ARIADNE=m 601CONFIG_ARIADNE=m
485CONFIG_A2065=m 602CONFIG_A2065=m
486CONFIG_HYDRA=m 603CONFIG_HYDRA=m
@@ -493,32 +610,24 @@ CONFIG_APNE=m
493# CONFIG_DEPCA is not set 610# CONFIG_DEPCA is not set
494# CONFIG_HP100 is not set 611# CONFIG_HP100 is not set
495# CONFIG_NET_ISA is not set 612# CONFIG_NET_ISA is not set
613# CONFIG_IBM_NEW_EMAC_ZMII is not set
614# CONFIG_IBM_NEW_EMAC_RGMII is not set
615# CONFIG_IBM_NEW_EMAC_TAH is not set
616# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
496# CONFIG_NET_PCI is not set 617# CONFIG_NET_PCI is not set
618# CONFIG_B44 is not set
497# CONFIG_NET_POCKET is not set 619# CONFIG_NET_POCKET is not set
498 620# CONFIG_NETDEV_1000 is not set
499# 621# CONFIG_NETDEV_10000 is not set
500# Ethernet (1000 Mbit)
501#
502
503#
504# Ethernet (10000 Mbit)
505#
506
507#
508# Token Ring devices
509#
510# CONFIG_TR is not set 622# CONFIG_TR is not set
511 623
512# 624#
513# Wireless LAN (non-hamradio) 625# Wireless LAN
514#
515# CONFIG_NET_RADIO is not set
516
517#
518# Wan interfaces
519# 626#
627# CONFIG_WLAN_PRE80211 is not set
628# CONFIG_WLAN_80211 is not set
520# CONFIG_WAN is not set 629# CONFIG_WAN is not set
521CONFIG_PLIP=m 630# CONFIG_PLIP is not set
522CONFIG_PPP=m 631CONFIG_PPP=m
523# CONFIG_PPP_MULTILINK is not set 632# CONFIG_PPP_MULTILINK is not set
524CONFIG_PPP_FILTER=y 633CONFIG_PPP_FILTER=y
@@ -526,28 +635,28 @@ CONFIG_PPP_ASYNC=m
526CONFIG_PPP_SYNC_TTY=m 635CONFIG_PPP_SYNC_TTY=m
527CONFIG_PPP_DEFLATE=m 636CONFIG_PPP_DEFLATE=m
528CONFIG_PPP_BSDCOMP=m 637CONFIG_PPP_BSDCOMP=m
638CONFIG_PPP_MPPE=m
529CONFIG_PPPOE=m 639CONFIG_PPPOE=m
640CONFIG_PPPOL2TP=m
530CONFIG_SLIP=m 641CONFIG_SLIP=m
531CONFIG_SLIP_COMPRESSED=y 642CONFIG_SLIP_COMPRESSED=y
643CONFIG_SLHC=m
532CONFIG_SLIP_SMART=y 644CONFIG_SLIP_SMART=y
533CONFIG_SLIP_MODE_SLIP6=y 645CONFIG_SLIP_MODE_SLIP6=y
534CONFIG_SHAPER=m
535CONFIG_NETCONSOLE=m 646CONFIG_NETCONSOLE=m
536 647CONFIG_NETCONSOLE_DYNAMIC=y
537# 648CONFIG_NETPOLL=y
538# ISDN subsystem 649# CONFIG_NETPOLL_TRAP is not set
539# 650CONFIG_NET_POLL_CONTROLLER=y
540# CONFIG_ISDN is not set 651# CONFIG_ISDN is not set
541
542#
543# Telephony Support
544#
545# CONFIG_PHONE is not set 652# CONFIG_PHONE is not set
546 653
547# 654#
548# Input device support 655# Input device support
549# 656#
550CONFIG_INPUT=y 657CONFIG_INPUT=y
658CONFIG_INPUT_FF_MEMLESS=m
659# CONFIG_INPUT_POLLDEV is not set
551 660
552# 661#
553# Userland interfaces 662# Userland interfaces
@@ -557,7 +666,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
557CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 666CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
558CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 667CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
559# CONFIG_INPUT_JOYDEV is not set 668# CONFIG_INPUT_JOYDEV is not set
560# CONFIG_INPUT_TSDEV is not set
561# CONFIG_INPUT_EVDEV is not set 669# CONFIG_INPUT_EVDEV is not set
562# CONFIG_INPUT_EVBUG is not set 670# CONFIG_INPUT_EVBUG is not set
563 671
@@ -570,6 +678,7 @@ CONFIG_INPUT_KEYBOARD=y
570# CONFIG_KEYBOARD_LKKBD is not set 678# CONFIG_KEYBOARD_LKKBD is not set
571# CONFIG_KEYBOARD_XTKBD is not set 679# CONFIG_KEYBOARD_XTKBD is not set
572# CONFIG_KEYBOARD_NEWTON is not set 680# CONFIG_KEYBOARD_NEWTON is not set
681# CONFIG_KEYBOARD_STOWAWAY is not set
573CONFIG_KEYBOARD_AMIGA=y 682CONFIG_KEYBOARD_AMIGA=y
574CONFIG_INPUT_MOUSE=y 683CONFIG_INPUT_MOUSE=y
575# CONFIG_MOUSE_PS2 is not set 684# CONFIG_MOUSE_PS2 is not set
@@ -577,7 +686,7 @@ CONFIG_INPUT_MOUSE=y
577# CONFIG_MOUSE_INPORT is not set 686# CONFIG_MOUSE_INPORT is not set
578# CONFIG_MOUSE_LOGIBM is not set 687# CONFIG_MOUSE_LOGIBM is not set
579# CONFIG_MOUSE_PC110PAD is not set 688# CONFIG_MOUSE_PC110PAD is not set
580CONFIG_MOUSE_AMIGA=y 689CONFIG_MOUSE_AMIGA=m
581# CONFIG_MOUSE_VSXXXAA is not set 690# CONFIG_MOUSE_VSXXXAA is not set
582CONFIG_INPUT_JOYSTICK=y 691CONFIG_INPUT_JOYSTICK=y
583# CONFIG_JOYSTICK_ANALOG is not set 692# CONFIG_JOYSTICK_ANALOG is not set
@@ -603,16 +712,16 @@ CONFIG_INPUT_JOYSTICK=y
603# CONFIG_JOYSTICK_TURBOGRAFX is not set 712# CONFIG_JOYSTICK_TURBOGRAFX is not set
604CONFIG_JOYSTICK_AMIGA=m 713CONFIG_JOYSTICK_AMIGA=m
605# CONFIG_JOYSTICK_JOYDUMP is not set 714# CONFIG_JOYSTICK_JOYDUMP is not set
715# CONFIG_INPUT_TABLET is not set
606# CONFIG_INPUT_TOUCHSCREEN is not set 716# CONFIG_INPUT_TOUCHSCREEN is not set
607# CONFIG_INPUT_MISC is not set 717CONFIG_INPUT_MISC=y
718CONFIG_INPUT_M68K_BEEP=m
719# CONFIG_INPUT_UINPUT is not set
608 720
609# 721#
610# Hardware I/O ports 722# Hardware I/O ports
611# 723#
612CONFIG_SERIO=m 724# CONFIG_SERIO is not set
613CONFIG_SERIO_SERPORT=m
614# CONFIG_SERIO_PARKBD is not set
615# CONFIG_SERIO_RAW is not set
616# CONFIG_GAMEPORT is not set 725# CONFIG_GAMEPORT is not set
617 726
618# 727#
@@ -621,6 +730,7 @@ CONFIG_SERIO_SERPORT=m
621CONFIG_VT=y 730CONFIG_VT=y
622CONFIG_VT_CONSOLE=y 731CONFIG_VT_CONSOLE=y
623CONFIG_HW_CONSOLE=y 732CONFIG_HW_CONSOLE=y
733CONFIG_VT_HW_CONSOLE_BINDING=y
624# CONFIG_SERIAL_NONSTANDARD is not set 734# CONFIG_SERIAL_NONSTANDARD is not set
625CONFIG_A2232=m 735CONFIG_A2232=m
626 736
@@ -638,94 +748,102 @@ CONFIG_LEGACY_PTY_COUNT=256
638CONFIG_PRINTER=m 748CONFIG_PRINTER=m
639# CONFIG_LP_CONSOLE is not set 749# CONFIG_LP_CONSOLE is not set
640# CONFIG_PPDEV is not set 750# CONFIG_PPDEV is not set
641# CONFIG_TIPAR is not set
642
643#
644# IPMI
645#
646# CONFIG_IPMI_HANDLER is not set 751# CONFIG_IPMI_HANDLER is not set
647 752# CONFIG_HW_RANDOM is not set
648#
649# Watchdog Cards
650#
651# CONFIG_WATCHDOG is not set
652CONFIG_GEN_RTC=m 753CONFIG_GEN_RTC=m
653CONFIG_GEN_RTC_X=y 754CONFIG_GEN_RTC_X=y
654# CONFIG_DTLK is not set 755# CONFIG_DTLK is not set
655# CONFIG_R3964 is not set 756# CONFIG_R3964 is not set
656
657#
658# Ftape, the floppy tape device driver
659#
660# CONFIG_DRM is not set
661# CONFIG_RAW_DRIVER is not set 757# CONFIG_RAW_DRIVER is not set
662 758# CONFIG_TCG_TPM is not set
663#
664# TPM devices
665#
666
667#
668# I2C support
669#
670# CONFIG_I2C is not set 759# CONFIG_I2C is not set
671 760
672# 761#
673# Dallas's 1-wire bus 762# SPI support
674# 763#
764# CONFIG_SPI is not set
765# CONFIG_SPI_MASTER is not set
675# CONFIG_W1 is not set 766# CONFIG_W1 is not set
767# CONFIG_POWER_SUPPLY is not set
768# CONFIG_HWMON is not set
769# CONFIG_THERMAL is not set
770# CONFIG_WATCHDOG is not set
676 771
677# 772#
678# Misc devices 773# Sonics Silicon Backplane
679# 774#
775CONFIG_SSB_POSSIBLE=y
776# CONFIG_SSB is not set
680 777
681# 778#
682# Multimedia devices 779# Multifunction device drivers
683# 780#
684# CONFIG_VIDEO_DEV is not set 781# CONFIG_MFD_SM501 is not set
685 782
686# 783#
687# Digital Video Broadcasting Devices 784# Multimedia devices
688# 785#
689# CONFIG_DVB is not set 786# CONFIG_VIDEO_DEV is not set
787# CONFIG_DVB_CORE is not set
788# CONFIG_DAB is not set
690 789
691# 790#
692# Graphics support 791# Graphics support
693# 792#
793# CONFIG_VGASTATE is not set
794# CONFIG_VIDEO_OUTPUT_CONTROL is not set
694CONFIG_FB=y 795CONFIG_FB=y
796# CONFIG_FIRMWARE_EDID is not set
797# CONFIG_FB_DDC is not set
695CONFIG_FB_CFB_FILLRECT=y 798CONFIG_FB_CFB_FILLRECT=y
696CONFIG_FB_CFB_COPYAREA=y 799CONFIG_FB_CFB_COPYAREA=y
697CONFIG_FB_CFB_IMAGEBLIT=y 800CONFIG_FB_CFB_IMAGEBLIT=y
698CONFIG_FB_SOFT_CURSOR=y 801# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
802# CONFIG_FB_SYS_FILLRECT is not set
803# CONFIG_FB_SYS_COPYAREA is not set
804# CONFIG_FB_SYS_IMAGEBLIT is not set
805# CONFIG_FB_SYS_FOPS is not set
806CONFIG_FB_DEFERRED_IO=y
807# CONFIG_FB_SVGALIB is not set
699# CONFIG_FB_MACMODES is not set 808# CONFIG_FB_MACMODES is not set
700CONFIG_FB_MODE_HELPERS=y 809# CONFIG_FB_BACKLIGHT is not set
810# CONFIG_FB_MODE_HELPERS is not set
701# CONFIG_FB_TILEBLITTING is not set 811# CONFIG_FB_TILEBLITTING is not set
702CONFIG_FB_CIRRUS=m 812
813#
814# Frame buffer hardware drivers
815#
816CONFIG_FB_CIRRUS=y
703CONFIG_FB_AMIGA=y 817CONFIG_FB_AMIGA=y
704CONFIG_FB_AMIGA_OCS=y 818CONFIG_FB_AMIGA_OCS=y
705CONFIG_FB_AMIGA_ECS=y 819CONFIG_FB_AMIGA_ECS=y
706CONFIG_FB_AMIGA_AGA=y 820CONFIG_FB_AMIGA_AGA=y
707CONFIG_FB_FM2=y 821CONFIG_FB_FM2=y
822# CONFIG_FB_UVESA is not set
708# CONFIG_FB_S1D13XXX is not set 823# CONFIG_FB_S1D13XXX is not set
709# CONFIG_FB_VIRTUAL is not set 824# CONFIG_FB_VIRTUAL is not set
825# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
826
827#
828# Display device support
829#
830# CONFIG_DISPLAY_SUPPORT is not set
710 831
711# 832#
712# Console display driver support 833# Console display driver support
713# 834#
714CONFIG_DUMMY_CONSOLE=y 835CONFIG_DUMMY_CONSOLE=y
715CONFIG_FRAMEBUFFER_CONSOLE=y 836CONFIG_FRAMEBUFFER_CONSOLE=y
837# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
838# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
716# CONFIG_FONTS is not set 839# CONFIG_FONTS is not set
717CONFIG_FONT_8x8=y 840CONFIG_FONT_8x8=y
718CONFIG_FONT_8x16=y 841CONFIG_FONT_8x16=y
719CONFIG_FONT_PEARL_8x8=y 842CONFIG_FONT_PEARL_8x8=y
720
721#
722# Logo configuration
723#
724CONFIG_LOGO=y 843CONFIG_LOGO=y
725CONFIG_LOGO_LINUX_MONO=y 844CONFIG_LOGO_LINUX_MONO=y
726CONFIG_LOGO_LINUX_VGA16=y 845CONFIG_LOGO_LINUX_VGA16=y
727CONFIG_LOGO_LINUX_CLUT224=y 846CONFIG_LOGO_LINUX_CLUT224=y
728# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
729 847
730# 848#
731# Sound 849# Sound
@@ -733,27 +851,21 @@ CONFIG_LOGO_LINUX_CLUT224=y
733CONFIG_SOUND=m 851CONFIG_SOUND=m
734CONFIG_DMASOUND_PAULA=m 852CONFIG_DMASOUND_PAULA=m
735CONFIG_DMASOUND=m 853CONFIG_DMASOUND=m
736 854CONFIG_HID_SUPPORT=y
737# 855CONFIG_HID=m
738# USB support 856# CONFIG_HID_DEBUG is not set
739# 857CONFIG_HIDRAW=y
740# CONFIG_USB_ARCH_HAS_HCD is not set 858# CONFIG_USB_SUPPORT is not set
741# CONFIG_USB_ARCH_HAS_OHCI is not set
742
743#
744# USB Gadget Support
745#
746# CONFIG_USB_GADGET is not set
747
748#
749# MMC/SD Card support
750#
751# CONFIG_MMC is not set 859# CONFIG_MMC is not set
860# CONFIG_MEMSTICK is not set
861# CONFIG_NEW_LEDS is not set
862# CONFIG_RTC_CLASS is not set
863# CONFIG_AUXDISPLAY is not set
752 864
753# 865#
754# InfiniBand support 866# Userspace I/O
755# 867#
756# CONFIG_INFINIBAND is not set 868# CONFIG_UIO is not set
757 869
758# 870#
759# Character devices 871# Character devices
@@ -768,10 +880,11 @@ CONFIG_MULTIFACE_III_TTY=m
768# 880#
769CONFIG_EXT2_FS=y 881CONFIG_EXT2_FS=y
770# CONFIG_EXT2_FS_XATTR is not set 882# CONFIG_EXT2_FS_XATTR is not set
883# CONFIG_EXT2_FS_XIP is not set
771CONFIG_EXT3_FS=y 884CONFIG_EXT3_FS=y
772# CONFIG_EXT3_FS_XATTR is not set 885# CONFIG_EXT3_FS_XATTR is not set
886# CONFIG_EXT4DEV_FS is not set
773CONFIG_JBD=y 887CONFIG_JBD=y
774# CONFIG_JBD_DEBUG is not set
775CONFIG_REISERFS_FS=m 888CONFIG_REISERFS_FS=m
776# CONFIG_REISERFS_CHECK is not set 889# CONFIG_REISERFS_CHECK is not set
777# CONFIG_REISERFS_PROC_INFO is not set 890# CONFIG_REISERFS_PROC_INFO is not set
@@ -782,25 +895,29 @@ CONFIG_JFS_FS=m
782# CONFIG_JFS_DEBUG is not set 895# CONFIG_JFS_DEBUG is not set
783# CONFIG_JFS_STATISTICS is not set 896# CONFIG_JFS_STATISTICS is not set
784CONFIG_FS_POSIX_ACL=y 897CONFIG_FS_POSIX_ACL=y
785
786#
787# XFS support
788#
789CONFIG_XFS_FS=m 898CONFIG_XFS_FS=m
790CONFIG_XFS_EXPORT=y
791# CONFIG_XFS_RT is not set
792# CONFIG_XFS_QUOTA is not set 899# CONFIG_XFS_QUOTA is not set
793# CONFIG_XFS_SECURITY is not set 900# CONFIG_XFS_SECURITY is not set
794# CONFIG_XFS_POSIX_ACL is not set 901# CONFIG_XFS_POSIX_ACL is not set
795CONFIG_MINIX_FS=y 902# CONFIG_XFS_RT is not set
796# CONFIG_ROMFS_FS is not set 903CONFIG_GFS2_FS=m
904CONFIG_GFS2_FS_LOCKING_NOLOCK=m
905CONFIG_GFS2_FS_LOCKING_DLM=m
906CONFIG_OCFS2_FS=m
907# CONFIG_OCFS2_DEBUG_MASKLOG is not set
908# CONFIG_OCFS2_DEBUG_FS is not set
909CONFIG_DNOTIFY=y
910CONFIG_INOTIFY=y
911CONFIG_INOTIFY_USER=y
797CONFIG_QUOTA=y 912CONFIG_QUOTA=y
913CONFIG_QUOTA_NETLINK_INTERFACE=y
914# CONFIG_PRINT_QUOTA_WARNING is not set
798# CONFIG_QFMT_V1 is not set 915# CONFIG_QFMT_V1 is not set
799# CONFIG_QFMT_V2 is not set 916# CONFIG_QFMT_V2 is not set
800CONFIG_QUOTACTL=y 917CONFIG_QUOTACTL=y
801CONFIG_DNOTIFY=y
802CONFIG_AUTOFS_FS=m 918CONFIG_AUTOFS_FS=m
803CONFIG_AUTOFS4_FS=m 919CONFIG_AUTOFS4_FS=m
920CONFIG_FUSE_FS=m
804 921
805# 922#
806# CD-ROM/DVD Filesystems 923# CD-ROM/DVD Filesystems
@@ -808,7 +925,6 @@ CONFIG_AUTOFS4_FS=m
808CONFIG_ISO9660_FS=y 925CONFIG_ISO9660_FS=y
809CONFIG_JOLIET=y 926CONFIG_JOLIET=y
810CONFIG_ZISOFS=y 927CONFIG_ZISOFS=y
811CONFIG_ZISOFS_FS=y
812CONFIG_UDF_FS=m 928CONFIG_UDF_FS=m
813CONFIG_UDF_NLS=y 929CONFIG_UDF_NLS=y
814 930
@@ -827,19 +943,18 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
827# 943#
828CONFIG_PROC_FS=y 944CONFIG_PROC_FS=y
829CONFIG_PROC_KCORE=y 945CONFIG_PROC_KCORE=y
946CONFIG_PROC_SYSCTL=y
830CONFIG_SYSFS=y 947CONFIG_SYSFS=y
831# CONFIG_DEVFS_FS is not set
832# CONFIG_DEVPTS_FS_XATTR is not set
833CONFIG_TMPFS=y 948CONFIG_TMPFS=y
834# CONFIG_TMPFS_XATTR is not set 949# CONFIG_TMPFS_POSIX_ACL is not set
835# CONFIG_HUGETLB_PAGE is not set 950# CONFIG_HUGETLB_PAGE is not set
836CONFIG_RAMFS=y 951CONFIG_CONFIGFS_FS=m
837 952
838# 953#
839# Miscellaneous filesystems 954# Miscellaneous filesystems
840# 955#
841# CONFIG_ADFS_FS is not set 956# CONFIG_ADFS_FS is not set
842CONFIG_AFFS_FS=y 957CONFIG_AFFS_FS=m
843CONFIG_HFS_FS=m 958CONFIG_HFS_FS=m
844CONFIG_HFSPLUS_FS=m 959CONFIG_HFSPLUS_FS=m
845# CONFIG_BEFS_FS is not set 960# CONFIG_BEFS_FS is not set
@@ -847,43 +962,39 @@ CONFIG_HFSPLUS_FS=m
847# CONFIG_EFS_FS is not set 962# CONFIG_EFS_FS is not set
848CONFIG_CRAMFS=m 963CONFIG_CRAMFS=m
849# CONFIG_VXFS_FS is not set 964# CONFIG_VXFS_FS is not set
965CONFIG_MINIX_FS=y
850CONFIG_HPFS_FS=m 966CONFIG_HPFS_FS=m
851# CONFIG_QNX4FS_FS is not set 967# CONFIG_QNX4FS_FS is not set
968# CONFIG_ROMFS_FS is not set
852CONFIG_SYSV_FS=m 969CONFIG_SYSV_FS=m
853CONFIG_UFS_FS=m 970CONFIG_UFS_FS=m
854# CONFIG_UFS_FS_WRITE is not set 971# CONFIG_UFS_FS_WRITE is not set
855 972# CONFIG_UFS_DEBUG is not set
856# 973CONFIG_NETWORK_FILESYSTEMS=y
857# Network File Systems
858#
859CONFIG_NFS_FS=m 974CONFIG_NFS_FS=m
860CONFIG_NFS_V3=y 975CONFIG_NFS_V3=y
976# CONFIG_NFS_V3_ACL is not set
861CONFIG_NFS_V4=y 977CONFIG_NFS_V4=y
862# CONFIG_NFS_DIRECTIO is not set 978# CONFIG_NFS_DIRECTIO is not set
863CONFIG_NFSD=m 979CONFIG_NFSD=m
864CONFIG_NFSD_V3=y 980CONFIG_NFSD_V3=y
865CONFIG_NFSD_V4=y 981# CONFIG_NFSD_V3_ACL is not set
982# CONFIG_NFSD_V4 is not set
866CONFIG_NFSD_TCP=y 983CONFIG_NFSD_TCP=y
867CONFIG_LOCKD=m 984CONFIG_LOCKD=m
868CONFIG_LOCKD_V4=y 985CONFIG_LOCKD_V4=y
869CONFIG_EXPORTFS=m 986CONFIG_EXPORTFS=m
987CONFIG_NFS_COMMON=y
870CONFIG_SUNRPC=m 988CONFIG_SUNRPC=m
871CONFIG_SUNRPC_GSS=m 989CONFIG_SUNRPC_GSS=m
990CONFIG_SUNRPC_BIND34=y
872CONFIG_RPCSEC_GSS_KRB5=m 991CONFIG_RPCSEC_GSS_KRB5=m
873# CONFIG_RPCSEC_GSS_SPKM3 is not set 992# CONFIG_RPCSEC_GSS_SPKM3 is not set
874CONFIG_SMB_FS=m 993CONFIG_SMB_FS=m
875CONFIG_SMB_NLS_DEFAULT=y 994CONFIG_SMB_NLS_DEFAULT=y
876CONFIG_SMB_NLS_REMOTE="cp437" 995CONFIG_SMB_NLS_REMOTE="cp437"
877# CONFIG_CIFS is not set 996# CONFIG_CIFS is not set
878CONFIG_NCP_FS=m 997# CONFIG_NCP_FS is not set
879# CONFIG_NCPFS_PACKET_SIGNING is not set
880# CONFIG_NCPFS_IOCTL_LOCKING is not set
881# CONFIG_NCPFS_STRONG is not set
882CONFIG_NCPFS_NFS_NS=y
883CONFIG_NCPFS_OS2_NS=y
884# CONFIG_NCPFS_SMALLDOS is not set
885CONFIG_NCPFS_NLS=y
886# CONFIG_NCPFS_EXTRAS is not set
887CONFIG_CODA_FS=m 998CONFIG_CODA_FS=m
888# CONFIG_CODA_FS_OLD_API is not set 999# CONFIG_CODA_FS_OLD_API is not set
889# CONFIG_AFS_FS is not set 1000# CONFIG_AFS_FS is not set
@@ -894,10 +1005,6 @@ CONFIG_CODA_FS=m
894# CONFIG_PARTITION_ADVANCED is not set 1005# CONFIG_PARTITION_ADVANCED is not set
895CONFIG_AMIGA_PARTITION=y 1006CONFIG_AMIGA_PARTITION=y
896CONFIG_MSDOS_PARTITION=y 1007CONFIG_MSDOS_PARTITION=y
897
898#
899# Native Language Support
900#
901CONFIG_NLS=y 1008CONFIG_NLS=y
902CONFIG_NLS_DEFAULT="iso8859-1" 1009CONFIG_NLS_DEFAULT="iso8859-1"
903CONFIG_NLS_CODEPAGE_437=y 1010CONFIG_NLS_CODEPAGE_437=y
@@ -938,35 +1045,42 @@ CONFIG_NLS_ISO8859_15=m
938CONFIG_NLS_KOI8_R=m 1045CONFIG_NLS_KOI8_R=m
939CONFIG_NLS_KOI8_U=m 1046CONFIG_NLS_KOI8_U=m
940CONFIG_NLS_UTF8=m 1047CONFIG_NLS_UTF8=m
1048CONFIG_DLM=m
1049# CONFIG_DLM_DEBUG is not set
941 1050
942# 1051#
943# Kernel hacking 1052# Kernel hacking
944# 1053#
945# CONFIG_PRINTK_TIME is not set 1054# CONFIG_PRINTK_TIME is not set
946CONFIG_DEBUG_KERNEL=y 1055CONFIG_ENABLE_WARN_DEPRECATED=y
1056CONFIG_ENABLE_MUST_CHECK=y
947CONFIG_MAGIC_SYSRQ=y 1057CONFIG_MAGIC_SYSRQ=y
948CONFIG_LOG_BUF_SHIFT=16 1058# CONFIG_UNUSED_SYMBOLS is not set
949# CONFIG_SCHEDSTATS is not set
950# CONFIG_DEBUG_SLAB is not set
951# CONFIG_DEBUG_SPINLOCK is not set
952# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
953# CONFIG_DEBUG_KOBJECT is not set
954CONFIG_DEBUG_BUGVERBOSE=y
955# CONFIG_DEBUG_INFO is not set
956# CONFIG_DEBUG_FS is not set 1059# CONFIG_DEBUG_FS is not set
957# CONFIG_FRAME_POINTER is not set 1060# CONFIG_HEADERS_CHECK is not set
1061# CONFIG_DEBUG_KERNEL is not set
1062CONFIG_DEBUG_BUGVERBOSE=y
1063# CONFIG_SAMPLES is not set
958 1064
959# 1065#
960# Security options 1066# Security options
961# 1067#
962# CONFIG_KEYS is not set 1068# CONFIG_KEYS is not set
963# CONFIG_SECURITY is not set 1069# CONFIG_SECURITY is not set
964 1070# CONFIG_SECURITY_FILE_CAPABILITIES is not set
965# 1071CONFIG_XOR_BLOCKS=m
966# Cryptographic options 1072CONFIG_ASYNC_CORE=m
967# 1073CONFIG_ASYNC_MEMCPY=m
1074CONFIG_ASYNC_XOR=m
968CONFIG_CRYPTO=y 1075CONFIG_CRYPTO=y
1076CONFIG_CRYPTO_ALGAPI=y
1077CONFIG_CRYPTO_AEAD=m
1078CONFIG_CRYPTO_BLKCIPHER=m
1079CONFIG_CRYPTO_SEQIV=m
1080CONFIG_CRYPTO_HASH=y
1081CONFIG_CRYPTO_MANAGER=y
969CONFIG_CRYPTO_HMAC=y 1082CONFIG_CRYPTO_HMAC=y
1083CONFIG_CRYPTO_XCBC=m
970CONFIG_CRYPTO_NULL=m 1084CONFIG_CRYPTO_NULL=m
971CONFIG_CRYPTO_MD4=m 1085CONFIG_CRYPTO_MD4=m
972CONFIG_CRYPTO_MD5=m 1086CONFIG_CRYPTO_MD5=m
@@ -975,9 +1089,21 @@ CONFIG_CRYPTO_SHA256=m
975CONFIG_CRYPTO_SHA512=m 1089CONFIG_CRYPTO_SHA512=m
976CONFIG_CRYPTO_WP512=m 1090CONFIG_CRYPTO_WP512=m
977CONFIG_CRYPTO_TGR192=m 1091CONFIG_CRYPTO_TGR192=m
1092CONFIG_CRYPTO_GF128MUL=m
1093CONFIG_CRYPTO_ECB=m
1094CONFIG_CRYPTO_CBC=m
1095CONFIG_CRYPTO_PCBC=m
1096CONFIG_CRYPTO_LRW=m
1097CONFIG_CRYPTO_XTS=m
1098CONFIG_CRYPTO_CTR=m
1099CONFIG_CRYPTO_GCM=m
1100CONFIG_CRYPTO_CCM=m
1101CONFIG_CRYPTO_CRYPTD=m
978CONFIG_CRYPTO_DES=m 1102CONFIG_CRYPTO_DES=m
1103CONFIG_CRYPTO_FCRYPT=m
979CONFIG_CRYPTO_BLOWFISH=m 1104CONFIG_CRYPTO_BLOWFISH=m
980CONFIG_CRYPTO_TWOFISH=m 1105CONFIG_CRYPTO_TWOFISH=m
1106CONFIG_CRYPTO_TWOFISH_COMMON=m
981CONFIG_CRYPTO_SERPENT=m 1107CONFIG_CRYPTO_SERPENT=m
982CONFIG_CRYPTO_AES=m 1108CONFIG_CRYPTO_AES=m
983CONFIG_CRYPTO_CAST5=m 1109CONFIG_CRYPTO_CAST5=m
@@ -986,20 +1112,35 @@ CONFIG_CRYPTO_TEA=m
986CONFIG_CRYPTO_ARC4=m 1112CONFIG_CRYPTO_ARC4=m
987CONFIG_CRYPTO_KHAZAD=m 1113CONFIG_CRYPTO_KHAZAD=m
988CONFIG_CRYPTO_ANUBIS=m 1114CONFIG_CRYPTO_ANUBIS=m
1115CONFIG_CRYPTO_SEED=m
1116CONFIG_CRYPTO_SALSA20=m
989CONFIG_CRYPTO_DEFLATE=m 1117CONFIG_CRYPTO_DEFLATE=m
990CONFIG_CRYPTO_MICHAEL_MIC=m 1118CONFIG_CRYPTO_MICHAEL_MIC=m
991CONFIG_CRYPTO_CRC32C=m 1119CONFIG_CRYPTO_CRC32C=m
1120CONFIG_CRYPTO_CAMELLIA=m
992CONFIG_CRYPTO_TEST=m 1121CONFIG_CRYPTO_TEST=m
993 1122CONFIG_CRYPTO_AUTHENC=m
994# 1123CONFIG_CRYPTO_LZO=m
995# Hardware crypto devices 1124# CONFIG_CRYPTO_HW is not set
996#
997 1125
998# 1126#
999# Library routines 1127# Library routines
1000# 1128#
1129CONFIG_BITREVERSE=y
1001CONFIG_CRC_CCITT=m 1130CONFIG_CRC_CCITT=m
1131CONFIG_CRC16=m
1132# CONFIG_CRC_ITU_T is not set
1002CONFIG_CRC32=y 1133CONFIG_CRC32=y
1134# CONFIG_CRC7 is not set
1003CONFIG_LIBCRC32C=m 1135CONFIG_LIBCRC32C=m
1004CONFIG_ZLIB_INFLATE=y 1136CONFIG_ZLIB_INFLATE=y
1005CONFIG_ZLIB_DEFLATE=m 1137CONFIG_ZLIB_DEFLATE=m
1138CONFIG_LZO_COMPRESS=m
1139CONFIG_LZO_DECOMPRESS=m
1140CONFIG_TEXTSEARCH=y
1141CONFIG_TEXTSEARCH_KMP=m
1142CONFIG_TEXTSEARCH_BM=m
1143CONFIG_TEXTSEARCH_FSM=m
1144CONFIG_PLIST=y
1145CONFIG_HAS_IOMEM=y
1146CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index 63024b0b7ac..e61196cd7fa 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:27 2005 4# Wed Apr 2 20:46:07 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-apollo" 27CONFIG_LOCALVERSION="-apollo"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
80CONFIG_M68040=y 128CONFIG_M68040=y
81CONFIG_M68060=y 129CONFIG_M68060=y
82CONFIG_MMU_MOTOROLA=y 130CONFIG_MMU_MOTOROLA=y
83CONFIG_M68KFPU_EMU=y 131# CONFIG_M68KFPU_EMU is not set
84CONFIG_M68KFPU_EMU_EXTRAPREC=y
85# CONFIG_M68KFPU_EMU_ONLY is not set
86# CONFIG_ADVANCED is not set 132# CONFIG_ADVANCED is not set
133CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
134CONFIG_NODES_SHIFT=3
135CONFIG_SELECT_MEMORY_MODEL=y
136# CONFIG_FLATMEM_MANUAL is not set
137CONFIG_DISCONTIGMEM_MANUAL=y
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_DISCONTIGMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141CONFIG_NEED_MULTIPLE_NODES=y
142# CONFIG_SPARSEMEM_STATIC is not set
143# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
144CONFIG_SPLIT_PTLOCK_CPUS=4
145# CONFIG_RESOURCES_64BIT is not set
146CONFIG_ZONE_DMA_FLAG=1
147CONFIG_BOUNCE=y
148CONFIG_VIRT_TO_BUS=y
87 149
88# 150#
89# General setup 151# General setup
@@ -93,134 +155,11 @@ CONFIG_BINFMT_AOUT=m
93CONFIG_BINFMT_MISC=m 155CONFIG_BINFMT_MISC=m
94CONFIG_HEARTBEAT=y 156CONFIG_HEARTBEAT=y
95CONFIG_PROC_HARDWARE=y 157CONFIG_PROC_HARDWARE=y
158CONFIG_ZONE_DMA=y
159# CONFIG_ARCH_SUPPORTS_MSI is not set
96 160
97# 161#
98# Device Drivers 162# Networking
99#
100
101#
102# Generic Driver Options
103#
104CONFIG_STANDALONE=y
105CONFIG_PREVENT_FIRMWARE_BUILD=y
106CONFIG_FW_LOADER=m
107# CONFIG_DEBUG_DRIVER is not set
108
109#
110# Memory Technology Devices (MTD)
111#
112# CONFIG_MTD is not set
113
114#
115# Parallel port support
116#
117# CONFIG_PARPORT is not set
118
119#
120# Plug and Play support
121#
122
123#
124# Block devices
125#
126# CONFIG_BLK_DEV_COW_COMMON is not set
127CONFIG_BLK_DEV_LOOP=y
128CONFIG_BLK_DEV_CRYPTOLOOP=m
129CONFIG_BLK_DEV_NBD=m
130CONFIG_BLK_DEV_RAM=y
131CONFIG_BLK_DEV_RAM_COUNT=16
132CONFIG_BLK_DEV_RAM_SIZE=4096
133CONFIG_BLK_DEV_INITRD=y
134CONFIG_INITRAMFS_SOURCE=""
135CONFIG_CDROM_PKTCDVD=m
136CONFIG_CDROM_PKTCDVD_BUFFERS=8
137# CONFIG_CDROM_PKTCDVD_WCACHE is not set
138
139#
140# IO Schedulers
141#
142CONFIG_IOSCHED_NOOP=y
143CONFIG_IOSCHED_AS=y
144CONFIG_IOSCHED_DEADLINE=y
145CONFIG_IOSCHED_CFQ=y
146CONFIG_ATA_OVER_ETH=m
147
148#
149# ATA/ATAPI/MFM/RLL support
150#
151# CONFIG_IDE is not set
152
153#
154# SCSI device support
155#
156CONFIG_SCSI=y
157CONFIG_SCSI_PROC_FS=y
158
159#
160# SCSI support type (disk, tape, CD-ROM)
161#
162CONFIG_BLK_DEV_SD=y
163CONFIG_CHR_DEV_ST=m
164# CONFIG_CHR_DEV_OSST is not set
165CONFIG_BLK_DEV_SR=y
166CONFIG_BLK_DEV_SR_VENDOR=y
167CONFIG_CHR_DEV_SG=m
168
169#
170# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
171#
172# CONFIG_SCSI_MULTI_LUN is not set
173CONFIG_SCSI_CONSTANTS=y
174# CONFIG_SCSI_LOGGING is not set
175
176#
177# SCSI Transport Attributes
178#
179# CONFIG_SCSI_SPI_ATTRS is not set
180# CONFIG_SCSI_FC_ATTRS is not set
181# CONFIG_SCSI_ISCSI_ATTRS is not set
182
183#
184# SCSI low-level drivers
185#
186# CONFIG_SCSI_SATA is not set
187# CONFIG_SCSI_DEBUG is not set
188
189#
190# Multi-device support (RAID and LVM)
191#
192CONFIG_MD=y
193CONFIG_BLK_DEV_MD=m
194CONFIG_MD_LINEAR=m
195CONFIG_MD_RAID0=m
196CONFIG_MD_RAID1=m
197# CONFIG_MD_RAID10 is not set
198CONFIG_MD_RAID5=m
199CONFIG_MD_RAID6=m
200CONFIG_MD_MULTIPATH=m
201# CONFIG_MD_FAULTY is not set
202CONFIG_BLK_DEV_DM=m
203CONFIG_DM_CRYPT=m
204CONFIG_DM_SNAPSHOT=m
205CONFIG_DM_MIRROR=m
206CONFIG_DM_ZERO=m
207CONFIG_DM_MULTIPATH=m
208CONFIG_DM_MULTIPATH_EMC=m
209
210#
211# Fusion MPT device support
212#
213
214#
215# IEEE 1394 (FireWire) support
216#
217
218#
219# I2O device support
220#
221
222#
223# Networking support
224# 163#
225CONFIG_NET=y 164CONFIG_NET=y
226 165
@@ -230,10 +169,17 @@ CONFIG_NET=y
230CONFIG_PACKET=y 169CONFIG_PACKET=y
231# CONFIG_PACKET_MMAP is not set 170# CONFIG_PACKET_MMAP is not set
232CONFIG_UNIX=y 171CONFIG_UNIX=y
172CONFIG_XFRM=y
173# CONFIG_XFRM_USER is not set
174# CONFIG_XFRM_SUB_POLICY is not set
175CONFIG_XFRM_MIGRATE=y
176# CONFIG_XFRM_STATISTICS is not set
233CONFIG_NET_KEY=y 177CONFIG_NET_KEY=y
178CONFIG_NET_KEY_MIGRATE=y
234CONFIG_INET=y 179CONFIG_INET=y
235# CONFIG_IP_MULTICAST is not set 180# CONFIG_IP_MULTICAST is not set
236# CONFIG_IP_ADVANCED_ROUTER is not set 181# CONFIG_IP_ADVANCED_ROUTER is not set
182CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y 183CONFIG_IP_PNP=y
238CONFIG_IP_PNP_DHCP=y 184CONFIG_IP_PNP_DHCP=y
239CONFIG_IP_PNP_BOOTP=y 185CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +191,199 @@ CONFIG_SYN_COOKIES=y
245CONFIG_INET_AH=m 191CONFIG_INET_AH=m
246CONFIG_INET_ESP=m 192CONFIG_INET_ESP=m
247CONFIG_INET_IPCOMP=m 193CONFIG_INET_IPCOMP=m
194CONFIG_INET_XFRM_TUNNEL=m
248CONFIG_INET_TUNNEL=m 195CONFIG_INET_TUNNEL=m
249CONFIG_IP_TCPDIAG=m 196CONFIG_INET_XFRM_MODE_TRANSPORT=m
250CONFIG_IP_TCPDIAG_IPV6=y 197CONFIG_INET_XFRM_MODE_TUNNEL=m
251 198CONFIG_INET_XFRM_MODE_BEET=m
252# 199CONFIG_INET_LRO=m
253# IP: Virtual Server Configuration 200CONFIG_INET_DIAG=m
254# 201CONFIG_INET_TCP_DIAG=m
202# CONFIG_TCP_CONG_ADVANCED is not set
203CONFIG_TCP_CONG_CUBIC=y
204CONFIG_DEFAULT_TCP_CONG="cubic"
205# CONFIG_TCP_MD5SIG is not set
255# CONFIG_IP_VS is not set 206# CONFIG_IP_VS is not set
256CONFIG_IPV6=m 207CONFIG_IPV6=m
257CONFIG_IPV6_PRIVACY=y 208CONFIG_IPV6_PRIVACY=y
209CONFIG_IPV6_ROUTER_PREF=y
210CONFIG_IPV6_ROUTE_INFO=y
211# CONFIG_IPV6_OPTIMISTIC_DAD is not set
258CONFIG_INET6_AH=m 212CONFIG_INET6_AH=m
259CONFIG_INET6_ESP=m 213CONFIG_INET6_ESP=m
260CONFIG_INET6_IPCOMP=m 214CONFIG_INET6_IPCOMP=m
215# CONFIG_IPV6_MIP6 is not set
216CONFIG_INET6_XFRM_TUNNEL=m
261CONFIG_INET6_TUNNEL=m 217CONFIG_INET6_TUNNEL=m
218CONFIG_INET6_XFRM_MODE_TRANSPORT=m
219CONFIG_INET6_XFRM_MODE_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_BEET=m
221CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
222CONFIG_IPV6_SIT=m
262CONFIG_IPV6_TUNNEL=m 223CONFIG_IPV6_TUNNEL=m
224# CONFIG_IPV6_MULTIPLE_TABLES is not set
225# CONFIG_NETWORK_SECMARK is not set
263CONFIG_NETFILTER=y 226CONFIG_NETFILTER=y
264# CONFIG_NETFILTER_DEBUG is not set 227# CONFIG_NETFILTER_DEBUG is not set
228CONFIG_NETFILTER_ADVANCED=y
229
230#
231# Core Netfilter Configuration
232#
233CONFIG_NETFILTER_NETLINK=m
234CONFIG_NETFILTER_NETLINK_QUEUE=m
235CONFIG_NETFILTER_NETLINK_LOG=m
236CONFIG_NF_CONNTRACK=m
237CONFIG_NF_CT_ACCT=y
238CONFIG_NF_CONNTRACK_MARK=y
239# CONFIG_NF_CONNTRACK_EVENTS is not set
240CONFIG_NF_CT_PROTO_GRE=m
241CONFIG_NF_CT_PROTO_SCTP=m
242CONFIG_NF_CT_PROTO_UDPLITE=m
243CONFIG_NF_CONNTRACK_AMANDA=m
244CONFIG_NF_CONNTRACK_FTP=m
245CONFIG_NF_CONNTRACK_H323=m
246CONFIG_NF_CONNTRACK_IRC=m
247CONFIG_NF_CONNTRACK_NETBIOS_NS=m
248CONFIG_NF_CONNTRACK_PPTP=m
249CONFIG_NF_CONNTRACK_SANE=m
250CONFIG_NF_CONNTRACK_SIP=m
251CONFIG_NF_CONNTRACK_TFTP=m
252# CONFIG_NF_CT_NETLINK is not set
253CONFIG_NETFILTER_XTABLES=m
254CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
255CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
256CONFIG_NETFILTER_XT_TARGET_DSCP=m
257CONFIG_NETFILTER_XT_TARGET_MARK=m
258CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
259CONFIG_NETFILTER_XT_TARGET_NFLOG=m
260CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
261CONFIG_NETFILTER_XT_TARGET_RATEEST=m
262CONFIG_NETFILTER_XT_TARGET_TRACE=m
263CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
264CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
265CONFIG_NETFILTER_XT_MATCH_COMMENT=m
266CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
267CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
268CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
269CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
270CONFIG_NETFILTER_XT_MATCH_DCCP=m
271CONFIG_NETFILTER_XT_MATCH_DSCP=m
272CONFIG_NETFILTER_XT_MATCH_ESP=m
273CONFIG_NETFILTER_XT_MATCH_HELPER=m
274CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
275CONFIG_NETFILTER_XT_MATCH_LENGTH=m
276CONFIG_NETFILTER_XT_MATCH_LIMIT=m
277CONFIG_NETFILTER_XT_MATCH_MAC=m
278CONFIG_NETFILTER_XT_MATCH_MARK=m
279CONFIG_NETFILTER_XT_MATCH_OWNER=m
280CONFIG_NETFILTER_XT_MATCH_POLICY=m
281CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
282CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
283CONFIG_NETFILTER_XT_MATCH_QUOTA=m
284CONFIG_NETFILTER_XT_MATCH_RATEEST=m
285CONFIG_NETFILTER_XT_MATCH_REALM=m
286CONFIG_NETFILTER_XT_MATCH_SCTP=m
287CONFIG_NETFILTER_XT_MATCH_STATE=m
288CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
289CONFIG_NETFILTER_XT_MATCH_STRING=m
290CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
291CONFIG_NETFILTER_XT_MATCH_TIME=m
292CONFIG_NETFILTER_XT_MATCH_U32=m
293CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
265 294
266# 295#
267# IP: Netfilter Configuration 296# IP: Netfilter Configuration
268# 297#
269CONFIG_IP_NF_CONNTRACK=m 298CONFIG_NF_CONNTRACK_IPV4=m
270# CONFIG_IP_NF_CT_ACCT is not set 299CONFIG_NF_CONNTRACK_PROC_COMPAT=y
271CONFIG_IP_NF_CONNTRACK_MARK=y
272# CONFIG_IP_NF_CT_PROTO_SCTP is not set
273CONFIG_IP_NF_FTP=m
274CONFIG_IP_NF_IRC=m
275CONFIG_IP_NF_TFTP=m
276CONFIG_IP_NF_AMANDA=m
277CONFIG_IP_NF_QUEUE=m 300CONFIG_IP_NF_QUEUE=m
278CONFIG_IP_NF_IPTABLES=m 301CONFIG_IP_NF_IPTABLES=m
279CONFIG_IP_NF_MATCH_LIMIT=m
280CONFIG_IP_NF_MATCH_IPRANGE=m
281CONFIG_IP_NF_MATCH_MAC=m
282CONFIG_IP_NF_MATCH_PKTTYPE=m
283CONFIG_IP_NF_MATCH_MARK=m
284CONFIG_IP_NF_MATCH_MULTIPORT=m
285CONFIG_IP_NF_MATCH_TOS=m
286CONFIG_IP_NF_MATCH_RECENT=m 302CONFIG_IP_NF_MATCH_RECENT=m
287CONFIG_IP_NF_MATCH_ECN=m 303CONFIG_IP_NF_MATCH_ECN=m
288CONFIG_IP_NF_MATCH_DSCP=m 304CONFIG_IP_NF_MATCH_AH=m
289CONFIG_IP_NF_MATCH_AH_ESP=m
290CONFIG_IP_NF_MATCH_LENGTH=m
291CONFIG_IP_NF_MATCH_TTL=m 305CONFIG_IP_NF_MATCH_TTL=m
292CONFIG_IP_NF_MATCH_TCPMSS=m
293CONFIG_IP_NF_MATCH_HELPER=m
294CONFIG_IP_NF_MATCH_STATE=m
295CONFIG_IP_NF_MATCH_CONNTRACK=m
296CONFIG_IP_NF_MATCH_OWNER=m
297CONFIG_IP_NF_MATCH_ADDRTYPE=m 306CONFIG_IP_NF_MATCH_ADDRTYPE=m
298CONFIG_IP_NF_MATCH_REALM=m
299# CONFIG_IP_NF_MATCH_SCTP is not set
300# CONFIG_IP_NF_MATCH_COMMENT is not set
301CONFIG_IP_NF_MATCH_CONNMARK=m
302CONFIG_IP_NF_MATCH_HASHLIMIT=m
303CONFIG_IP_NF_FILTER=m 307CONFIG_IP_NF_FILTER=m
304CONFIG_IP_NF_TARGET_REJECT=m 308CONFIG_IP_NF_TARGET_REJECT=m
305CONFIG_IP_NF_TARGET_LOG=m 309CONFIG_IP_NF_TARGET_LOG=m
306CONFIG_IP_NF_TARGET_ULOG=m 310CONFIG_IP_NF_TARGET_ULOG=m
307CONFIG_IP_NF_TARGET_TCPMSS=m 311CONFIG_NF_NAT=m
308CONFIG_IP_NF_NAT=m 312CONFIG_NF_NAT_NEEDED=y
309CONFIG_IP_NF_NAT_NEEDED=y
310CONFIG_IP_NF_TARGET_MASQUERADE=m 313CONFIG_IP_NF_TARGET_MASQUERADE=m
311CONFIG_IP_NF_TARGET_REDIRECT=m 314CONFIG_IP_NF_TARGET_REDIRECT=m
312CONFIG_IP_NF_TARGET_NETMAP=m 315CONFIG_IP_NF_TARGET_NETMAP=m
313CONFIG_IP_NF_TARGET_SAME=m 316CONFIG_NF_NAT_SNMP_BASIC=m
314CONFIG_IP_NF_NAT_SNMP_BASIC=m 317CONFIG_NF_NAT_PROTO_GRE=m
315CONFIG_IP_NF_NAT_IRC=m 318CONFIG_NF_NAT_FTP=m
316CONFIG_IP_NF_NAT_FTP=m 319CONFIG_NF_NAT_IRC=m
317CONFIG_IP_NF_NAT_TFTP=m 320CONFIG_NF_NAT_TFTP=m
318CONFIG_IP_NF_NAT_AMANDA=m 321CONFIG_NF_NAT_AMANDA=m
322CONFIG_NF_NAT_PPTP=m
323CONFIG_NF_NAT_H323=m
324CONFIG_NF_NAT_SIP=m
319CONFIG_IP_NF_MANGLE=m 325CONFIG_IP_NF_MANGLE=m
320CONFIG_IP_NF_TARGET_TOS=m
321CONFIG_IP_NF_TARGET_ECN=m 326CONFIG_IP_NF_TARGET_ECN=m
322CONFIG_IP_NF_TARGET_DSCP=m 327CONFIG_IP_NF_TARGET_TTL=m
323CONFIG_IP_NF_TARGET_MARK=m 328CONFIG_IP_NF_TARGET_CLUSTERIP=m
324CONFIG_IP_NF_TARGET_CLASSIFY=m
325CONFIG_IP_NF_TARGET_CONNMARK=m
326# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
327CONFIG_IP_NF_RAW=m 329CONFIG_IP_NF_RAW=m
328CONFIG_IP_NF_TARGET_NOTRACK=m
329CONFIG_IP_NF_ARPTABLES=m 330CONFIG_IP_NF_ARPTABLES=m
330CONFIG_IP_NF_ARPFILTER=m 331CONFIG_IP_NF_ARPFILTER=m
331CONFIG_IP_NF_ARP_MANGLE=m 332CONFIG_IP_NF_ARP_MANGLE=m
332 333
333# 334#
334# IPv6: Netfilter Configuration (EXPERIMENTAL) 335# IPv6: Netfilter Configuration
335# 336#
337CONFIG_NF_CONNTRACK_IPV6=m
336CONFIG_IP6_NF_QUEUE=m 338CONFIG_IP6_NF_QUEUE=m
337CONFIG_IP6_NF_IPTABLES=m 339CONFIG_IP6_NF_IPTABLES=m
338CONFIG_IP6_NF_MATCH_LIMIT=m
339CONFIG_IP6_NF_MATCH_MAC=m
340CONFIG_IP6_NF_MATCH_RT=m 340CONFIG_IP6_NF_MATCH_RT=m
341CONFIG_IP6_NF_MATCH_OPTS=m 341CONFIG_IP6_NF_MATCH_OPTS=m
342CONFIG_IP6_NF_MATCH_FRAG=m 342CONFIG_IP6_NF_MATCH_FRAG=m
343CONFIG_IP6_NF_MATCH_HL=m 343CONFIG_IP6_NF_MATCH_HL=m
344CONFIG_IP6_NF_MATCH_MULTIPORT=m
345CONFIG_IP6_NF_MATCH_OWNER=m
346CONFIG_IP6_NF_MATCH_MARK=m
347CONFIG_IP6_NF_MATCH_IPV6HEADER=m 344CONFIG_IP6_NF_MATCH_IPV6HEADER=m
348CONFIG_IP6_NF_MATCH_AHESP=m 345CONFIG_IP6_NF_MATCH_AH=m
349CONFIG_IP6_NF_MATCH_LENGTH=m 346CONFIG_IP6_NF_MATCH_MH=m
350CONFIG_IP6_NF_MATCH_EUI64=m 347CONFIG_IP6_NF_MATCH_EUI64=m
351CONFIG_IP6_NF_FILTER=m 348CONFIG_IP6_NF_FILTER=m
352CONFIG_IP6_NF_TARGET_LOG=m 349CONFIG_IP6_NF_TARGET_LOG=m
350CONFIG_IP6_NF_TARGET_REJECT=m
353CONFIG_IP6_NF_MANGLE=m 351CONFIG_IP6_NF_MANGLE=m
354CONFIG_IP6_NF_TARGET_MARK=m 352CONFIG_IP6_NF_TARGET_HL=m
355CONFIG_IP6_NF_RAW=m 353CONFIG_IP6_NF_RAW=m
356CONFIG_XFRM=y 354CONFIG_IP_DCCP=m
357CONFIG_XFRM_USER=m 355CONFIG_INET_DCCP_DIAG=m
356CONFIG_IP_DCCP_ACKVEC=y
358 357
359# 358#
360# SCTP Configuration (EXPERIMENTAL) 359# DCCP CCIDs Configuration (EXPERIMENTAL)
361# 360#
361CONFIG_IP_DCCP_CCID2=m
362# CONFIG_IP_DCCP_CCID2_DEBUG is not set
363CONFIG_IP_DCCP_CCID3=m
364# CONFIG_IP_DCCP_CCID3_DEBUG is not set
365CONFIG_IP_DCCP_CCID3_RTO=100
366CONFIG_IP_DCCP_TFRC_LIB=m
362CONFIG_IP_SCTP=m 367CONFIG_IP_SCTP=m
363# CONFIG_SCTP_DBG_MSG is not set 368# CONFIG_SCTP_DBG_MSG is not set
364# CONFIG_SCTP_DBG_OBJCNT is not set 369# CONFIG_SCTP_DBG_OBJCNT is not set
365# CONFIG_SCTP_HMAC_NONE is not set 370# CONFIG_SCTP_HMAC_NONE is not set
366# CONFIG_SCTP_HMAC_SHA1 is not set 371# CONFIG_SCTP_HMAC_SHA1 is not set
367CONFIG_SCTP_HMAC_MD5=y 372CONFIG_SCTP_HMAC_MD5=y
373# CONFIG_TIPC is not set
368# CONFIG_ATM is not set 374# CONFIG_ATM is not set
369# CONFIG_BRIDGE is not set 375# CONFIG_BRIDGE is not set
370# CONFIG_VLAN_8021Q is not set 376# CONFIG_VLAN_8021Q is not set
371# CONFIG_DECNET is not set 377# CONFIG_DECNET is not set
372CONFIG_LLC=m 378CONFIG_LLC=m
373# CONFIG_LLC2 is not set 379# CONFIG_LLC2 is not set
374CONFIG_IPX=m 380# CONFIG_IPX is not set
375# CONFIG_IPX_INTERN is not set
376CONFIG_ATALK=m 381CONFIG_ATALK=m
377# CONFIG_DEV_APPLETALK is not set 382# CONFIG_DEV_APPLETALK is not set
378# CONFIG_X25 is not set 383# CONFIG_X25 is not set
379# CONFIG_LAPB is not set 384# CONFIG_LAPB is not set
380# CONFIG_NET_DIVERT is not set
381# CONFIG_ECONET is not set 385# CONFIG_ECONET is not set
382# CONFIG_WAN_ROUTER is not set 386# CONFIG_WAN_ROUTER is not set
383
384#
385# QoS and/or fair queueing
386#
387# CONFIG_NET_SCHED is not set 387# CONFIG_NET_SCHED is not set
388CONFIG_NET_CLS_ROUTE=y 388CONFIG_NET_CLS_ROUTE=y
389 389
@@ -391,46 +391,154 @@ CONFIG_NET_CLS_ROUTE=y
391# Network testing 391# Network testing
392# 392#
393# CONFIG_NET_PKTGEN is not set 393# CONFIG_NET_PKTGEN is not set
394CONFIG_NETPOLL=y
395# CONFIG_NETPOLL_RX is not set
396# CONFIG_NETPOLL_TRAP is not set
397CONFIG_NET_POLL_CONTROLLER=y
398# CONFIG_HAMRADIO is not set 394# CONFIG_HAMRADIO is not set
395# CONFIG_CAN is not set
399# CONFIG_IRDA is not set 396# CONFIG_IRDA is not set
400# CONFIG_BT is not set 397# CONFIG_BT is not set
401CONFIG_NETDEVICES=y 398# CONFIG_AF_RXRPC is not set
402CONFIG_DUMMY=m
403# CONFIG_BONDING is not set
404CONFIG_EQUALIZER=m
405# CONFIG_TUN is not set
406 399
407# 400#
408# Ethernet (10 or 100Mbit) 401# Wireless
409# 402#
410CONFIG_NET_ETHERNET=y 403# CONFIG_CFG80211 is not set
411CONFIG_MII=m 404CONFIG_WIRELESS_EXT=y
412CONFIG_APOLLO_ELPLUS=y 405# CONFIG_MAC80211 is not set
406CONFIG_IEEE80211=m
407# CONFIG_IEEE80211_DEBUG is not set
408CONFIG_IEEE80211_CRYPT_WEP=m
409CONFIG_IEEE80211_CRYPT_CCMP=m
410CONFIG_IEEE80211_CRYPT_TKIP=m
411CONFIG_IEEE80211_SOFTMAC=m
412# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
413# CONFIG_RFKILL is not set
414# CONFIG_NET_9P is not set
413 415
414# 416#
415# Ethernet (1000 Mbit) 417# Device Drivers
416# 418#
417 419
418# 420#
419# Ethernet (10000 Mbit) 421# Generic Driver Options
420# 422#
423CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
424CONFIG_STANDALONE=y
425CONFIG_PREVENT_FIRMWARE_BUILD=y
426CONFIG_FW_LOADER=m
427# CONFIG_SYS_HYPERVISOR is not set
428CONFIG_CONNECTOR=m
429# CONFIG_MTD is not set
430# CONFIG_PARPORT is not set
431CONFIG_BLK_DEV=y
432# CONFIG_BLK_DEV_COW_COMMON is not set
433CONFIG_BLK_DEV_LOOP=y
434CONFIG_BLK_DEV_CRYPTOLOOP=m
435CONFIG_BLK_DEV_NBD=m
436CONFIG_BLK_DEV_RAM=y
437CONFIG_BLK_DEV_RAM_COUNT=16
438CONFIG_BLK_DEV_RAM_SIZE=4096
439# CONFIG_BLK_DEV_XIP is not set
440CONFIG_CDROM_PKTCDVD=m
441CONFIG_CDROM_PKTCDVD_BUFFERS=8
442# CONFIG_CDROM_PKTCDVD_WCACHE is not set
443CONFIG_ATA_OVER_ETH=m
444CONFIG_MISC_DEVICES=y
445# CONFIG_EEPROM_93CX6 is not set
446# CONFIG_ENCLOSURE_SERVICES is not set
447CONFIG_HAVE_IDE=y
448# CONFIG_IDE is not set
421 449
422# 450#
423# Token Ring devices 451# SCSI device support
424# 452#
453CONFIG_RAID_ATTRS=m
454CONFIG_SCSI=y
455CONFIG_SCSI_DMA=y
456CONFIG_SCSI_TGT=m
457# CONFIG_SCSI_NETLINK is not set
458CONFIG_SCSI_PROC_FS=y
425 459
426# 460#
427# Wireless LAN (non-hamradio) 461# SCSI support type (disk, tape, CD-ROM)
428# 462#
429# CONFIG_NET_RADIO is not set 463CONFIG_BLK_DEV_SD=y
464CONFIG_CHR_DEV_ST=m
465CONFIG_CHR_DEV_OSST=m
466CONFIG_BLK_DEV_SR=y
467CONFIG_BLK_DEV_SR_VENDOR=y
468CONFIG_CHR_DEV_SG=m
469# CONFIG_CHR_DEV_SCH is not set
470
471#
472# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
473#
474# CONFIG_SCSI_MULTI_LUN is not set
475CONFIG_SCSI_CONSTANTS=y
476# CONFIG_SCSI_LOGGING is not set
477# CONFIG_SCSI_SCAN_ASYNC is not set
478CONFIG_SCSI_WAIT_SCAN=m
479
480#
481# SCSI Transports
482#
483# CONFIG_SCSI_SPI_ATTRS is not set
484# CONFIG_SCSI_FC_ATTRS is not set
485CONFIG_SCSI_ISCSI_ATTRS=m
486CONFIG_SCSI_SAS_ATTRS=m
487CONFIG_SCSI_SAS_LIBSAS=m
488CONFIG_SCSI_SAS_HOST_SMP=y
489# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
490CONFIG_SCSI_SRP_ATTRS=m
491CONFIG_SCSI_SRP_TGT_ATTRS=y
492CONFIG_SCSI_LOWLEVEL=y
493CONFIG_ISCSI_TCP=m
494# CONFIG_SCSI_DEBUG is not set
495CONFIG_MD=y
496CONFIG_BLK_DEV_MD=m
497CONFIG_MD_LINEAR=m
498CONFIG_MD_RAID0=m
499CONFIG_MD_RAID1=m
500# CONFIG_MD_RAID10 is not set
501CONFIG_MD_RAID456=m
502CONFIG_MD_RAID5_RESHAPE=y
503CONFIG_MD_MULTIPATH=m
504# CONFIG_MD_FAULTY is not set
505CONFIG_BLK_DEV_DM=m
506# CONFIG_DM_DEBUG is not set
507CONFIG_DM_CRYPT=m
508CONFIG_DM_SNAPSHOT=m
509CONFIG_DM_MIRROR=m
510CONFIG_DM_ZERO=m
511CONFIG_DM_MULTIPATH=m
512CONFIG_DM_MULTIPATH_EMC=m
513CONFIG_DM_MULTIPATH_RDAC=m
514CONFIG_DM_MULTIPATH_HP=m
515# CONFIG_DM_DELAY is not set
516CONFIG_DM_UEVENT=y
517CONFIG_NETDEVICES=y
518# CONFIG_NETDEVICES_MULTIQUEUE is not set
519CONFIG_DUMMY=m
520# CONFIG_BONDING is not set
521CONFIG_MACVLAN=m
522CONFIG_EQUALIZER=m
523# CONFIG_TUN is not set
524CONFIG_VETH=m
525# CONFIG_PHYLIB is not set
526CONFIG_NET_ETHERNET=y
527# CONFIG_MII is not set
528CONFIG_APOLLO_ELPLUS=y
529# CONFIG_IBM_NEW_EMAC_ZMII is not set
530# CONFIG_IBM_NEW_EMAC_RGMII is not set
531# CONFIG_IBM_NEW_EMAC_TAH is not set
532# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
533# CONFIG_B44 is not set
534# CONFIG_NETDEV_1000 is not set
535# CONFIG_NETDEV_10000 is not set
430 536
431# 537#
432# Wan interfaces 538# Wireless LAN
433# 539#
540# CONFIG_WLAN_PRE80211 is not set
541# CONFIG_WLAN_80211 is not set
434# CONFIG_WAN is not set 542# CONFIG_WAN is not set
435CONFIG_PPP=m 543CONFIG_PPP=m
436# CONFIG_PPP_MULTILINK is not set 544# CONFIG_PPP_MULTILINK is not set
@@ -439,28 +547,28 @@ CONFIG_PPP_ASYNC=m
439CONFIG_PPP_SYNC_TTY=m 547CONFIG_PPP_SYNC_TTY=m
440CONFIG_PPP_DEFLATE=m 548CONFIG_PPP_DEFLATE=m
441CONFIG_PPP_BSDCOMP=m 549CONFIG_PPP_BSDCOMP=m
550CONFIG_PPP_MPPE=m
442CONFIG_PPPOE=m 551CONFIG_PPPOE=m
552CONFIG_PPPOL2TP=m
443CONFIG_SLIP=m 553CONFIG_SLIP=m
444CONFIG_SLIP_COMPRESSED=y 554CONFIG_SLIP_COMPRESSED=y
555CONFIG_SLHC=m
445CONFIG_SLIP_SMART=y 556CONFIG_SLIP_SMART=y
446CONFIG_SLIP_MODE_SLIP6=y 557CONFIG_SLIP_MODE_SLIP6=y
447CONFIG_SHAPER=m
448CONFIG_NETCONSOLE=m 558CONFIG_NETCONSOLE=m
449 559CONFIG_NETCONSOLE_DYNAMIC=y
450# 560CONFIG_NETPOLL=y
451# ISDN subsystem 561# CONFIG_NETPOLL_TRAP is not set
452# 562CONFIG_NET_POLL_CONTROLLER=y
453# CONFIG_ISDN is not set 563# CONFIG_ISDN is not set
454
455#
456# Telephony Support
457#
458# CONFIG_PHONE is not set 564# CONFIG_PHONE is not set
459 565
460# 566#
461# Input device support 567# Input device support
462# 568#
463CONFIG_INPUT=y 569CONFIG_INPUT=y
570CONFIG_INPUT_FF_MEMLESS=m
571# CONFIG_INPUT_POLLDEV is not set
464 572
465# 573#
466# Userland interfaces 574# Userland interfaces
@@ -470,7 +578,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
470CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 578CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
471CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 579CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
472# CONFIG_INPUT_JOYDEV is not set 580# CONFIG_INPUT_JOYDEV is not set
473# CONFIG_INPUT_TSDEV is not set
474# CONFIG_INPUT_EVDEV is not set 581# CONFIG_INPUT_EVDEV is not set
475# CONFIG_INPUT_EVBUG is not set 582# CONFIG_INPUT_EVBUG is not set
476 583
@@ -483,11 +590,19 @@ CONFIG_INPUT_KEYBOARD=y
483# CONFIG_KEYBOARD_LKKBD is not set 590# CONFIG_KEYBOARD_LKKBD is not set
484# CONFIG_KEYBOARD_XTKBD is not set 591# CONFIG_KEYBOARD_XTKBD is not set
485# CONFIG_KEYBOARD_NEWTON is not set 592# CONFIG_KEYBOARD_NEWTON is not set
593# CONFIG_KEYBOARD_STOWAWAY is not set
486CONFIG_INPUT_MOUSE=y 594CONFIG_INPUT_MOUSE=y
487CONFIG_MOUSE_PS2=m 595CONFIG_MOUSE_PS2=m
596CONFIG_MOUSE_PS2_ALPS=y
597CONFIG_MOUSE_PS2_LOGIPS2PP=y
598CONFIG_MOUSE_PS2_SYNAPTICS=y
599CONFIG_MOUSE_PS2_LIFEBOOK=y
600CONFIG_MOUSE_PS2_TRACKPOINT=y
601# CONFIG_MOUSE_PS2_TOUCHKIT is not set
488CONFIG_MOUSE_SERIAL=m 602CONFIG_MOUSE_SERIAL=m
489# CONFIG_MOUSE_VSXXXAA is not set 603# CONFIG_MOUSE_VSXXXAA is not set
490# CONFIG_INPUT_JOYSTICK is not set 604# CONFIG_INPUT_JOYSTICK is not set
605# CONFIG_INPUT_TABLET is not set
491# CONFIG_INPUT_TOUCHSCREEN is not set 606# CONFIG_INPUT_TOUCHSCREEN is not set
492# CONFIG_INPUT_MISC is not set 607# CONFIG_INPUT_MISC is not set
493 608
@@ -495,7 +610,7 @@ CONFIG_MOUSE_SERIAL=m
495# Hardware I/O ports 610# Hardware I/O ports
496# 611#
497CONFIG_SERIO=m 612CONFIG_SERIO=m
498CONFIG_SERIO_SERPORT=m 613# CONFIG_SERIO_SERPORT is not set
499CONFIG_SERIO_LIBPS2=m 614CONFIG_SERIO_LIBPS2=m
500# CONFIG_SERIO_RAW is not set 615# CONFIG_SERIO_RAW is not set
501# CONFIG_GAMEPORT is not set 616# CONFIG_GAMEPORT is not set
@@ -506,6 +621,7 @@ CONFIG_SERIO_LIBPS2=m
506CONFIG_VT=y 621CONFIG_VT=y
507CONFIG_VT_CONSOLE=y 622CONFIG_VT_CONSOLE=y
508CONFIG_HW_CONSOLE=y 623CONFIG_HW_CONSOLE=y
624CONFIG_VT_HW_CONSOLE_BINDING=y
509# CONFIG_SERIAL_NONSTANDARD is not set 625# CONFIG_SERIAL_NONSTANDARD is not set
510 626
511# 627#
@@ -519,90 +635,114 @@ CONFIG_HW_CONSOLE=y
519CONFIG_UNIX98_PTYS=y 635CONFIG_UNIX98_PTYS=y
520CONFIG_LEGACY_PTYS=y 636CONFIG_LEGACY_PTYS=y
521CONFIG_LEGACY_PTY_COUNT=256 637CONFIG_LEGACY_PTY_COUNT=256
522
523#
524# IPMI
525#
526# CONFIG_IPMI_HANDLER is not set 638# CONFIG_IPMI_HANDLER is not set
527 639# CONFIG_HW_RANDOM is not set
528# 640CONFIG_GEN_RTC=m
529# Watchdog Cards
530#
531# CONFIG_WATCHDOG is not set
532CONFIG_GEN_RTC=y
533CONFIG_GEN_RTC_X=y 641CONFIG_GEN_RTC_X=y
534# CONFIG_DTLK is not set
535# CONFIG_R3964 is not set 642# CONFIG_R3964 is not set
536
537#
538# Ftape, the floppy tape device driver
539#
540# CONFIG_DRM is not set
541# CONFIG_RAW_DRIVER is not set 643# CONFIG_RAW_DRIVER is not set
644# CONFIG_TCG_TPM is not set
645# CONFIG_I2C is not set
542 646
543# 647#
544# TPM devices 648# SPI support
545# 649#
650# CONFIG_SPI is not set
651# CONFIG_SPI_MASTER is not set
652# CONFIG_W1 is not set
653# CONFIG_POWER_SUPPLY is not set
654# CONFIG_HWMON is not set
655# CONFIG_THERMAL is not set
656# CONFIG_WATCHDOG is not set
546 657
547# 658#
548# I2C support 659# Sonics Silicon Backplane
549# 660#
550# CONFIG_I2C is not set 661CONFIG_SSB_POSSIBLE=y
662# CONFIG_SSB is not set
551 663
552# 664#
553# Dallas's 1-wire bus 665# Multifunction device drivers
554# 666#
555# CONFIG_W1 is not set 667# CONFIG_MFD_SM501 is not set
556 668
557# 669#
558# Misc devices 670# Multimedia devices
559# 671#
672# CONFIG_VIDEO_DEV is not set
673# CONFIG_DVB_CORE is not set
674# CONFIG_DAB is not set
560 675
561# 676#
562# Multimedia devices 677# Graphics support
563# 678#
564# CONFIG_VIDEO_DEV is not set 679# CONFIG_VGASTATE is not set
680# CONFIG_VIDEO_OUTPUT_CONTROL is not set
681CONFIG_FB=y
682# CONFIG_FIRMWARE_EDID is not set
683# CONFIG_FB_DDC is not set
684CONFIG_FB_CFB_FILLRECT=y
685# CONFIG_FB_CFB_COPYAREA is not set
686CONFIG_FB_CFB_IMAGEBLIT=y
687# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
688# CONFIG_FB_SYS_FILLRECT is not set
689# CONFIG_FB_SYS_COPYAREA is not set
690# CONFIG_FB_SYS_IMAGEBLIT is not set
691# CONFIG_FB_SYS_FOPS is not set
692CONFIG_FB_DEFERRED_IO=y
693# CONFIG_FB_SVGALIB is not set
694# CONFIG_FB_MACMODES is not set
695# CONFIG_FB_BACKLIGHT is not set
696# CONFIG_FB_MODE_HELPERS is not set
697# CONFIG_FB_TILEBLITTING is not set
565 698
566# 699#
567# Digital Video Broadcasting Devices 700# Frame buffer hardware drivers
568# 701#
569# CONFIG_DVB is not set 702CONFIG_FB_APOLLO=y
703# CONFIG_FB_UVESA is not set
704# CONFIG_FB_S1D13XXX is not set
705# CONFIG_FB_VIRTUAL is not set
706# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
570 707
571# 708#
572# Graphics support 709# Display device support
573# 710#
574# CONFIG_FB is not set 711# CONFIG_DISPLAY_SUPPORT is not set
575 712
576# 713#
577# Console display driver support 714# Console display driver support
578# 715#
579CONFIG_DUMMY_CONSOLE=y 716CONFIG_DUMMY_CONSOLE=y
717CONFIG_FRAMEBUFFER_CONSOLE=y
718# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
719# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
720# CONFIG_FONTS is not set
721CONFIG_FONT_8x8=y
722CONFIG_FONT_8x16=y
723CONFIG_LOGO=y
724CONFIG_LOGO_LINUX_MONO=y
725# CONFIG_LOGO_LINUX_VGA16 is not set
726# CONFIG_LOGO_LINUX_CLUT224 is not set
580 727
581# 728#
582# Sound 729# Sound
583# 730#
584# CONFIG_SOUND is not set 731# CONFIG_SOUND is not set
585 732CONFIG_HID_SUPPORT=y
586# 733CONFIG_HID=m
587# USB support 734# CONFIG_HID_DEBUG is not set
588# 735CONFIG_HIDRAW=y
589# CONFIG_USB_ARCH_HAS_HCD is not set 736# CONFIG_USB_SUPPORT is not set
590# CONFIG_USB_ARCH_HAS_OHCI is not set
591
592#
593# USB Gadget Support
594#
595# CONFIG_USB_GADGET is not set
596
597#
598# MMC/SD Card support
599#
600# CONFIG_MMC is not set 737# CONFIG_MMC is not set
738# CONFIG_MEMSTICK is not set
739# CONFIG_NEW_LEDS is not set
740# CONFIG_RTC_CLASS is not set
601 741
602# 742#
603# InfiniBand support 743# Userspace I/O
604# 744#
605# CONFIG_INFINIBAND is not set 745# CONFIG_UIO is not set
606 746
607# 747#
608# Character devices 748# Character devices
@@ -615,10 +755,11 @@ CONFIG_SERIAL_CONSOLE=y
615# 755#
616CONFIG_EXT2_FS=y 756CONFIG_EXT2_FS=y
617# CONFIG_EXT2_FS_XATTR is not set 757# CONFIG_EXT2_FS_XATTR is not set
758# CONFIG_EXT2_FS_XIP is not set
618CONFIG_EXT3_FS=y 759CONFIG_EXT3_FS=y
619# CONFIG_EXT3_FS_XATTR is not set 760# CONFIG_EXT3_FS_XATTR is not set
761# CONFIG_EXT4DEV_FS is not set
620CONFIG_JBD=y 762CONFIG_JBD=y
621# CONFIG_JBD_DEBUG is not set
622CONFIG_REISERFS_FS=m 763CONFIG_REISERFS_FS=m
623# CONFIG_REISERFS_CHECK is not set 764# CONFIG_REISERFS_CHECK is not set
624# CONFIG_REISERFS_PROC_INFO is not set 765# CONFIG_REISERFS_PROC_INFO is not set
@@ -629,25 +770,29 @@ CONFIG_JFS_FS=m
629# CONFIG_JFS_DEBUG is not set 770# CONFIG_JFS_DEBUG is not set
630# CONFIG_JFS_STATISTICS is not set 771# CONFIG_JFS_STATISTICS is not set
631CONFIG_FS_POSIX_ACL=y 772CONFIG_FS_POSIX_ACL=y
632
633#
634# XFS support
635#
636CONFIG_XFS_FS=m 773CONFIG_XFS_FS=m
637CONFIG_XFS_EXPORT=y
638# CONFIG_XFS_RT is not set
639# CONFIG_XFS_QUOTA is not set 774# CONFIG_XFS_QUOTA is not set
640# CONFIG_XFS_SECURITY is not set 775# CONFIG_XFS_SECURITY is not set
641# CONFIG_XFS_POSIX_ACL is not set 776# CONFIG_XFS_POSIX_ACL is not set
642CONFIG_MINIX_FS=y 777# CONFIG_XFS_RT is not set
643# CONFIG_ROMFS_FS is not set 778CONFIG_GFS2_FS=m
779CONFIG_GFS2_FS_LOCKING_NOLOCK=m
780CONFIG_GFS2_FS_LOCKING_DLM=m
781CONFIG_OCFS2_FS=m
782# CONFIG_OCFS2_DEBUG_MASKLOG is not set
783# CONFIG_OCFS2_DEBUG_FS is not set
784CONFIG_DNOTIFY=y
785CONFIG_INOTIFY=y
786CONFIG_INOTIFY_USER=y
644CONFIG_QUOTA=y 787CONFIG_QUOTA=y
788CONFIG_QUOTA_NETLINK_INTERFACE=y
789# CONFIG_PRINT_QUOTA_WARNING is not set
645# CONFIG_QFMT_V1 is not set 790# CONFIG_QFMT_V1 is not set
646# CONFIG_QFMT_V2 is not set 791# CONFIG_QFMT_V2 is not set
647CONFIG_QUOTACTL=y 792CONFIG_QUOTACTL=y
648CONFIG_DNOTIFY=y
649CONFIG_AUTOFS_FS=m 793CONFIG_AUTOFS_FS=m
650CONFIG_AUTOFS4_FS=m 794CONFIG_AUTOFS4_FS=m
795CONFIG_FUSE_FS=m
651 796
652# 797#
653# CD-ROM/DVD Filesystems 798# CD-ROM/DVD Filesystems
@@ -655,7 +800,6 @@ CONFIG_AUTOFS4_FS=m
655CONFIG_ISO9660_FS=y 800CONFIG_ISO9660_FS=y
656CONFIG_JOLIET=y 801CONFIG_JOLIET=y
657CONFIG_ZISOFS=y 802CONFIG_ZISOFS=y
658CONFIG_ZISOFS_FS=y
659CONFIG_UDF_FS=m 803CONFIG_UDF_FS=m
660CONFIG_UDF_NLS=y 804CONFIG_UDF_NLS=y
661 805
@@ -674,13 +818,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
674# 818#
675CONFIG_PROC_FS=y 819CONFIG_PROC_FS=y
676CONFIG_PROC_KCORE=y 820CONFIG_PROC_KCORE=y
821CONFIG_PROC_SYSCTL=y
677CONFIG_SYSFS=y 822CONFIG_SYSFS=y
678# CONFIG_DEVFS_FS is not set
679# CONFIG_DEVPTS_FS_XATTR is not set
680CONFIG_TMPFS=y 823CONFIG_TMPFS=y
681# CONFIG_TMPFS_XATTR is not set 824# CONFIG_TMPFS_POSIX_ACL is not set
682# CONFIG_HUGETLB_PAGE is not set 825# CONFIG_HUGETLB_PAGE is not set
683CONFIG_RAMFS=y 826CONFIG_CONFIGFS_FS=m
684 827
685# 828#
686# Miscellaneous filesystems 829# Miscellaneous filesystems
@@ -694,44 +837,40 @@ CONFIG_HFSPLUS_FS=m
694# CONFIG_EFS_FS is not set 837# CONFIG_EFS_FS is not set
695CONFIG_CRAMFS=m 838CONFIG_CRAMFS=m
696# CONFIG_VXFS_FS is not set 839# CONFIG_VXFS_FS is not set
840CONFIG_MINIX_FS=y
697CONFIG_HPFS_FS=m 841CONFIG_HPFS_FS=m
698# CONFIG_QNX4FS_FS is not set 842# CONFIG_QNX4FS_FS is not set
843# CONFIG_ROMFS_FS is not set
699CONFIG_SYSV_FS=m 844CONFIG_SYSV_FS=m
700CONFIG_UFS_FS=m 845CONFIG_UFS_FS=m
701# CONFIG_UFS_FS_WRITE is not set 846# CONFIG_UFS_FS_WRITE is not set
702 847# CONFIG_UFS_DEBUG is not set
703# 848CONFIG_NETWORK_FILESYSTEMS=y
704# Network File Systems
705#
706CONFIG_NFS_FS=y 849CONFIG_NFS_FS=y
707CONFIG_NFS_V3=y 850CONFIG_NFS_V3=y
851# CONFIG_NFS_V3_ACL is not set
708CONFIG_NFS_V4=y 852CONFIG_NFS_V4=y
709# CONFIG_NFS_DIRECTIO is not set 853# CONFIG_NFS_DIRECTIO is not set
710CONFIG_NFSD=m 854CONFIG_NFSD=m
711CONFIG_NFSD_V3=y 855CONFIG_NFSD_V3=y
712CONFIG_NFSD_V4=y 856# CONFIG_NFSD_V3_ACL is not set
857# CONFIG_NFSD_V4 is not set
713CONFIG_NFSD_TCP=y 858CONFIG_NFSD_TCP=y
714CONFIG_ROOT_NFS=y 859CONFIG_ROOT_NFS=y
715CONFIG_LOCKD=y 860CONFIG_LOCKD=y
716CONFIG_LOCKD_V4=y 861CONFIG_LOCKD_V4=y
717CONFIG_EXPORTFS=m 862CONFIG_EXPORTFS=m
863CONFIG_NFS_COMMON=y
718CONFIG_SUNRPC=y 864CONFIG_SUNRPC=y
719CONFIG_SUNRPC_GSS=y 865CONFIG_SUNRPC_GSS=y
866CONFIG_SUNRPC_BIND34=y
720CONFIG_RPCSEC_GSS_KRB5=y 867CONFIG_RPCSEC_GSS_KRB5=y
721# CONFIG_RPCSEC_GSS_SPKM3 is not set 868# CONFIG_RPCSEC_GSS_SPKM3 is not set
722CONFIG_SMB_FS=m 869CONFIG_SMB_FS=m
723CONFIG_SMB_NLS_DEFAULT=y 870CONFIG_SMB_NLS_DEFAULT=y
724CONFIG_SMB_NLS_REMOTE="cp437" 871CONFIG_SMB_NLS_REMOTE="cp437"
725# CONFIG_CIFS is not set 872# CONFIG_CIFS is not set
726CONFIG_NCP_FS=m 873# CONFIG_NCP_FS is not set
727# CONFIG_NCPFS_PACKET_SIGNING is not set
728# CONFIG_NCPFS_IOCTL_LOCKING is not set
729# CONFIG_NCPFS_STRONG is not set
730CONFIG_NCPFS_NFS_NS=y
731CONFIG_NCPFS_OS2_NS=y
732# CONFIG_NCPFS_SMALLDOS is not set
733CONFIG_NCPFS_NLS=y
734# CONFIG_NCPFS_EXTRAS is not set
735CONFIG_CODA_FS=m 874CONFIG_CODA_FS=m
736# CONFIG_CODA_FS_OLD_API is not set 875# CONFIG_CODA_FS_OLD_API is not set
737# CONFIG_AFS_FS is not set 876# CONFIG_AFS_FS is not set
@@ -741,10 +880,6 @@ CONFIG_CODA_FS=m
741# 880#
742# CONFIG_PARTITION_ADVANCED is not set 881# CONFIG_PARTITION_ADVANCED is not set
743CONFIG_MSDOS_PARTITION=y 882CONFIG_MSDOS_PARTITION=y
744
745#
746# Native Language Support
747#
748CONFIG_NLS=y 883CONFIG_NLS=y
749CONFIG_NLS_DEFAULT="iso8859-1" 884CONFIG_NLS_DEFAULT="iso8859-1"
750CONFIG_NLS_CODEPAGE_437=y 885CONFIG_NLS_CODEPAGE_437=y
@@ -785,35 +920,42 @@ CONFIG_NLS_ISO8859_15=m
785CONFIG_NLS_KOI8_R=m 920CONFIG_NLS_KOI8_R=m
786CONFIG_NLS_KOI8_U=m 921CONFIG_NLS_KOI8_U=m
787CONFIG_NLS_UTF8=m 922CONFIG_NLS_UTF8=m
923CONFIG_DLM=m
924# CONFIG_DLM_DEBUG is not set
788 925
789# 926#
790# Kernel hacking 927# Kernel hacking
791# 928#
792# CONFIG_PRINTK_TIME is not set 929# CONFIG_PRINTK_TIME is not set
793CONFIG_DEBUG_KERNEL=y 930CONFIG_ENABLE_WARN_DEPRECATED=y
931CONFIG_ENABLE_MUST_CHECK=y
794CONFIG_MAGIC_SYSRQ=y 932CONFIG_MAGIC_SYSRQ=y
795CONFIG_LOG_BUF_SHIFT=16 933# CONFIG_UNUSED_SYMBOLS is not set
796# CONFIG_SCHEDSTATS is not set
797# CONFIG_DEBUG_SLAB is not set
798# CONFIG_DEBUG_SPINLOCK is not set
799# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
800# CONFIG_DEBUG_KOBJECT is not set
801CONFIG_DEBUG_BUGVERBOSE=y
802# CONFIG_DEBUG_INFO is not set
803# CONFIG_DEBUG_FS is not set 934# CONFIG_DEBUG_FS is not set
804# CONFIG_FRAME_POINTER is not set 935# CONFIG_HEADERS_CHECK is not set
936# CONFIG_DEBUG_KERNEL is not set
937CONFIG_DEBUG_BUGVERBOSE=y
938# CONFIG_SAMPLES is not set
805 939
806# 940#
807# Security options 941# Security options
808# 942#
809# CONFIG_KEYS is not set 943# CONFIG_KEYS is not set
810# CONFIG_SECURITY is not set 944# CONFIG_SECURITY is not set
811 945# CONFIG_SECURITY_FILE_CAPABILITIES is not set
812# 946CONFIG_XOR_BLOCKS=m
813# Cryptographic options 947CONFIG_ASYNC_CORE=m
814# 948CONFIG_ASYNC_MEMCPY=m
949CONFIG_ASYNC_XOR=m
815CONFIG_CRYPTO=y 950CONFIG_CRYPTO=y
951CONFIG_CRYPTO_ALGAPI=y
952CONFIG_CRYPTO_AEAD=m
953CONFIG_CRYPTO_BLKCIPHER=y
954CONFIG_CRYPTO_SEQIV=m
955CONFIG_CRYPTO_HASH=y
956CONFIG_CRYPTO_MANAGER=y
816CONFIG_CRYPTO_HMAC=y 957CONFIG_CRYPTO_HMAC=y
958CONFIG_CRYPTO_XCBC=m
817CONFIG_CRYPTO_NULL=m 959CONFIG_CRYPTO_NULL=m
818CONFIG_CRYPTO_MD4=m 960CONFIG_CRYPTO_MD4=m
819CONFIG_CRYPTO_MD5=y 961CONFIG_CRYPTO_MD5=y
@@ -822,9 +964,21 @@ CONFIG_CRYPTO_SHA256=m
822CONFIG_CRYPTO_SHA512=m 964CONFIG_CRYPTO_SHA512=m
823CONFIG_CRYPTO_WP512=m 965CONFIG_CRYPTO_WP512=m
824CONFIG_CRYPTO_TGR192=m 966CONFIG_CRYPTO_TGR192=m
967CONFIG_CRYPTO_GF128MUL=m
968CONFIG_CRYPTO_ECB=m
969CONFIG_CRYPTO_CBC=y
970CONFIG_CRYPTO_PCBC=m
971CONFIG_CRYPTO_LRW=m
972CONFIG_CRYPTO_XTS=m
973CONFIG_CRYPTO_CTR=m
974CONFIG_CRYPTO_GCM=m
975CONFIG_CRYPTO_CCM=m
976CONFIG_CRYPTO_CRYPTD=m
825CONFIG_CRYPTO_DES=y 977CONFIG_CRYPTO_DES=y
978CONFIG_CRYPTO_FCRYPT=m
826CONFIG_CRYPTO_BLOWFISH=m 979CONFIG_CRYPTO_BLOWFISH=m
827CONFIG_CRYPTO_TWOFISH=m 980CONFIG_CRYPTO_TWOFISH=m
981CONFIG_CRYPTO_TWOFISH_COMMON=m
828CONFIG_CRYPTO_SERPENT=m 982CONFIG_CRYPTO_SERPENT=m
829CONFIG_CRYPTO_AES=m 983CONFIG_CRYPTO_AES=m
830CONFIG_CRYPTO_CAST5=m 984CONFIG_CRYPTO_CAST5=m
@@ -833,20 +987,35 @@ CONFIG_CRYPTO_TEA=m
833CONFIG_CRYPTO_ARC4=m 987CONFIG_CRYPTO_ARC4=m
834CONFIG_CRYPTO_KHAZAD=m 988CONFIG_CRYPTO_KHAZAD=m
835CONFIG_CRYPTO_ANUBIS=m 989CONFIG_CRYPTO_ANUBIS=m
990CONFIG_CRYPTO_SEED=m
991CONFIG_CRYPTO_SALSA20=m
836CONFIG_CRYPTO_DEFLATE=m 992CONFIG_CRYPTO_DEFLATE=m
837CONFIG_CRYPTO_MICHAEL_MIC=m 993CONFIG_CRYPTO_MICHAEL_MIC=m
838CONFIG_CRYPTO_CRC32C=m 994CONFIG_CRYPTO_CRC32C=m
995CONFIG_CRYPTO_CAMELLIA=m
839CONFIG_CRYPTO_TEST=m 996CONFIG_CRYPTO_TEST=m
840 997CONFIG_CRYPTO_AUTHENC=m
841# 998CONFIG_CRYPTO_LZO=m
842# Hardware crypto devices 999# CONFIG_CRYPTO_HW is not set
843#
844 1000
845# 1001#
846# Library routines 1002# Library routines
847# 1003#
1004CONFIG_BITREVERSE=y
848CONFIG_CRC_CCITT=m 1005CONFIG_CRC_CCITT=m
1006CONFIG_CRC16=m
1007# CONFIG_CRC_ITU_T is not set
849CONFIG_CRC32=y 1008CONFIG_CRC32=y
1009# CONFIG_CRC7 is not set
850CONFIG_LIBCRC32C=m 1010CONFIG_LIBCRC32C=m
851CONFIG_ZLIB_INFLATE=y 1011CONFIG_ZLIB_INFLATE=y
852CONFIG_ZLIB_DEFLATE=m 1012CONFIG_ZLIB_DEFLATE=m
1013CONFIG_LZO_COMPRESS=m
1014CONFIG_LZO_DECOMPRESS=m
1015CONFIG_TEXTSEARCH=y
1016CONFIG_TEXTSEARCH_KMP=m
1017CONFIG_TEXTSEARCH_BM=m
1018CONFIG_TEXTSEARCH_FSM=m
1019CONFIG_PLIST=y
1020CONFIG_HAS_IOMEM=y
1021CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 6433da2d2ce..ba7f971bb02 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:32 2005 4# Wed Apr 2 20:46:09 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-atari" 27CONFIG_LOCALVERSION="-atari"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
80CONFIG_M68040=y 128CONFIG_M68040=y
81CONFIG_M68060=y 129CONFIG_M68060=y
82CONFIG_MMU_MOTOROLA=y 130CONFIG_MMU_MOTOROLA=y
83CONFIG_M68KFPU_EMU=y 131# CONFIG_M68KFPU_EMU is not set
84CONFIG_M68KFPU_EMU_EXTRAPREC=y
85# CONFIG_M68KFPU_EMU_ONLY is not set
86# CONFIG_ADVANCED is not set 132# CONFIG_ADVANCED is not set
133CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
134CONFIG_NODES_SHIFT=3
135CONFIG_SELECT_MEMORY_MODEL=y
136# CONFIG_FLATMEM_MANUAL is not set
137CONFIG_DISCONTIGMEM_MANUAL=y
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_DISCONTIGMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141CONFIG_NEED_MULTIPLE_NODES=y
142# CONFIG_SPARSEMEM_STATIC is not set
143# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
144CONFIG_SPLIT_PTLOCK_CPUS=4
145# CONFIG_RESOURCES_64BIT is not set
146CONFIG_ZONE_DMA_FLAG=1
147CONFIG_BOUNCE=y
148CONFIG_VIRT_TO_BUS=y
87 149
88# 150#
89# General setup 151# General setup
@@ -94,166 +156,11 @@ CONFIG_BINFMT_MISC=m
94CONFIG_STRAM_PROC=y 156CONFIG_STRAM_PROC=y
95CONFIG_HEARTBEAT=y 157CONFIG_HEARTBEAT=y
96CONFIG_PROC_HARDWARE=y 158CONFIG_PROC_HARDWARE=y
159CONFIG_ZONE_DMA=y
160# CONFIG_ARCH_SUPPORTS_MSI is not set
97 161
98# 162#
99# Device Drivers 163# Networking
100#
101
102#
103# Generic Driver Options
104#
105CONFIG_STANDALONE=y
106CONFIG_PREVENT_FIRMWARE_BUILD=y
107CONFIG_FW_LOADER=m
108# CONFIG_DEBUG_DRIVER is not set
109
110#
111# Memory Technology Devices (MTD)
112#
113# CONFIG_MTD is not set
114
115#
116# Parallel port support
117#
118CONFIG_PARPORT=m
119# CONFIG_PARPORT_PC is not set
120CONFIG_PARPORT_NOT_PC=y
121CONFIG_PARPORT_ATARI=m
122# CONFIG_PARPORT_GSC is not set
123CONFIG_PARPORT_1284=y
124
125#
126# Plug and Play support
127#
128
129#
130# Block devices
131#
132CONFIG_ATARI_FLOPPY=y
133# CONFIG_PARIDE is not set
134# CONFIG_BLK_DEV_COW_COMMON is not set
135CONFIG_BLK_DEV_LOOP=y
136CONFIG_BLK_DEV_CRYPTOLOOP=m
137CONFIG_BLK_DEV_NBD=m
138CONFIG_BLK_DEV_RAM=y
139CONFIG_BLK_DEV_RAM_COUNT=16
140CONFIG_BLK_DEV_RAM_SIZE=4096
141CONFIG_BLK_DEV_INITRD=y
142CONFIG_INITRAMFS_SOURCE=""
143CONFIG_CDROM_PKTCDVD=m
144CONFIG_CDROM_PKTCDVD_BUFFERS=8
145# CONFIG_CDROM_PKTCDVD_WCACHE is not set
146
147#
148# IO Schedulers
149#
150CONFIG_IOSCHED_NOOP=y
151CONFIG_IOSCHED_AS=y
152CONFIG_IOSCHED_DEADLINE=y
153CONFIG_IOSCHED_CFQ=y
154CONFIG_ATA_OVER_ETH=m
155
156#
157# ATA/ATAPI/MFM/RLL support
158#
159CONFIG_IDE=y
160CONFIG_BLK_DEV_IDE=y
161
162#
163# Please see Documentation/ide.txt for help/info on IDE drives
164#
165# CONFIG_BLK_DEV_IDE_SATA is not set
166CONFIG_BLK_DEV_IDEDISK=y
167# CONFIG_IDEDISK_MULTI_MODE is not set
168CONFIG_BLK_DEV_IDECD=y
169CONFIG_BLK_DEV_IDETAPE=m
170CONFIG_BLK_DEV_IDEFLOPPY=m
171# CONFIG_BLK_DEV_IDESCSI is not set
172# CONFIG_IDE_TASK_IOCTL is not set
173
174#
175# IDE chipset support/bugfixes
176#
177CONFIG_IDE_GENERIC=y
178# CONFIG_IDE_ARM is not set
179CONFIG_BLK_DEV_FALCON_IDE=y
180# CONFIG_BLK_DEV_IDEDMA is not set
181# CONFIG_IDEDMA_AUTO is not set
182# CONFIG_BLK_DEV_HD is not set
183
184#
185# SCSI device support
186#
187CONFIG_SCSI=y
188CONFIG_SCSI_PROC_FS=y
189
190#
191# SCSI support type (disk, tape, CD-ROM)
192#
193CONFIG_BLK_DEV_SD=y
194CONFIG_CHR_DEV_ST=m
195# CONFIG_CHR_DEV_OSST is not set
196CONFIG_BLK_DEV_SR=y
197CONFIG_BLK_DEV_SR_VENDOR=y
198CONFIG_CHR_DEV_SG=m
199
200#
201# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
202#
203# CONFIG_SCSI_MULTI_LUN is not set
204CONFIG_SCSI_CONSTANTS=y
205# CONFIG_SCSI_LOGGING is not set
206
207#
208# SCSI Transport Attributes
209#
210# CONFIG_SCSI_SPI_ATTRS is not set
211# CONFIG_SCSI_FC_ATTRS is not set
212# CONFIG_SCSI_ISCSI_ATTRS is not set
213
214#
215# SCSI low-level drivers
216#
217# CONFIG_SCSI_SATA is not set
218# CONFIG_SCSI_PPA is not set
219# CONFIG_SCSI_IMM is not set
220# CONFIG_SCSI_DEBUG is not set
221
222#
223# Multi-device support (RAID and LVM)
224#
225CONFIG_MD=y
226CONFIG_BLK_DEV_MD=m
227CONFIG_MD_LINEAR=m
228CONFIG_MD_RAID0=m
229CONFIG_MD_RAID1=m
230# CONFIG_MD_RAID10 is not set
231CONFIG_MD_RAID5=m
232CONFIG_MD_RAID6=m
233CONFIG_MD_MULTIPATH=m
234# CONFIG_MD_FAULTY is not set
235CONFIG_BLK_DEV_DM=m
236CONFIG_DM_CRYPT=m
237CONFIG_DM_SNAPSHOT=m
238CONFIG_DM_MIRROR=m
239CONFIG_DM_ZERO=m
240CONFIG_DM_MULTIPATH=m
241CONFIG_DM_MULTIPATH_EMC=m
242
243#
244# Fusion MPT device support
245#
246
247#
248# IEEE 1394 (FireWire) support
249#
250
251#
252# I2O device support
253#
254
255#
256# Networking support
257# 164#
258CONFIG_NET=y 165CONFIG_NET=y
259 166
@@ -263,10 +170,17 @@ CONFIG_NET=y
263CONFIG_PACKET=y 170CONFIG_PACKET=y
264# CONFIG_PACKET_MMAP is not set 171# CONFIG_PACKET_MMAP is not set
265CONFIG_UNIX=y 172CONFIG_UNIX=y
173CONFIG_XFRM=y
174# CONFIG_XFRM_USER is not set
175# CONFIG_XFRM_SUB_POLICY is not set
176CONFIG_XFRM_MIGRATE=y
177# CONFIG_XFRM_STATISTICS is not set
266CONFIG_NET_KEY=y 178CONFIG_NET_KEY=y
179CONFIG_NET_KEY_MIGRATE=y
267CONFIG_INET=y 180CONFIG_INET=y
268# CONFIG_IP_MULTICAST is not set 181# CONFIG_IP_MULTICAST is not set
269# CONFIG_IP_ADVANCED_ROUTER is not set 182# CONFIG_IP_ADVANCED_ROUTER is not set
183CONFIG_IP_FIB_HASH=y
270# CONFIG_IP_PNP is not set 184# CONFIG_IP_PNP is not set
271CONFIG_NET_IPIP=m 185CONFIG_NET_IPIP=m
272CONFIG_NET_IPGRE=m 186CONFIG_NET_IPGRE=m
@@ -275,145 +189,199 @@ CONFIG_SYN_COOKIES=y
275CONFIG_INET_AH=m 189CONFIG_INET_AH=m
276CONFIG_INET_ESP=m 190CONFIG_INET_ESP=m
277CONFIG_INET_IPCOMP=m 191CONFIG_INET_IPCOMP=m
192CONFIG_INET_XFRM_TUNNEL=m
278CONFIG_INET_TUNNEL=m 193CONFIG_INET_TUNNEL=m
279CONFIG_IP_TCPDIAG=m 194CONFIG_INET_XFRM_MODE_TRANSPORT=m
280CONFIG_IP_TCPDIAG_IPV6=y 195CONFIG_INET_XFRM_MODE_TUNNEL=m
281 196CONFIG_INET_XFRM_MODE_BEET=m
282# 197CONFIG_INET_LRO=m
283# IP: Virtual Server Configuration 198CONFIG_INET_DIAG=m
284# 199CONFIG_INET_TCP_DIAG=m
200# CONFIG_TCP_CONG_ADVANCED is not set
201CONFIG_TCP_CONG_CUBIC=y
202CONFIG_DEFAULT_TCP_CONG="cubic"
203# CONFIG_TCP_MD5SIG is not set
285# CONFIG_IP_VS is not set 204# CONFIG_IP_VS is not set
286CONFIG_IPV6=m 205CONFIG_IPV6=m
287CONFIG_IPV6_PRIVACY=y 206CONFIG_IPV6_PRIVACY=y
207CONFIG_IPV6_ROUTER_PREF=y
208CONFIG_IPV6_ROUTE_INFO=y
209# CONFIG_IPV6_OPTIMISTIC_DAD is not set
288CONFIG_INET6_AH=m 210CONFIG_INET6_AH=m
289CONFIG_INET6_ESP=m 211CONFIG_INET6_ESP=m
290CONFIG_INET6_IPCOMP=m 212CONFIG_INET6_IPCOMP=m
213# CONFIG_IPV6_MIP6 is not set
214CONFIG_INET6_XFRM_TUNNEL=m
291CONFIG_INET6_TUNNEL=m 215CONFIG_INET6_TUNNEL=m
216CONFIG_INET6_XFRM_MODE_TRANSPORT=m
217CONFIG_INET6_XFRM_MODE_TUNNEL=m
218CONFIG_INET6_XFRM_MODE_BEET=m
219CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
220CONFIG_IPV6_SIT=m
292CONFIG_IPV6_TUNNEL=m 221CONFIG_IPV6_TUNNEL=m
222# CONFIG_IPV6_MULTIPLE_TABLES is not set
223# CONFIG_NETWORK_SECMARK is not set
293CONFIG_NETFILTER=y 224CONFIG_NETFILTER=y
294# CONFIG_NETFILTER_DEBUG is not set 225# CONFIG_NETFILTER_DEBUG is not set
226CONFIG_NETFILTER_ADVANCED=y
227
228#
229# Core Netfilter Configuration
230#
231CONFIG_NETFILTER_NETLINK=m
232CONFIG_NETFILTER_NETLINK_QUEUE=m
233CONFIG_NETFILTER_NETLINK_LOG=m
234CONFIG_NF_CONNTRACK=m
235CONFIG_NF_CT_ACCT=y
236CONFIG_NF_CONNTRACK_MARK=y
237# CONFIG_NF_CONNTRACK_EVENTS is not set
238CONFIG_NF_CT_PROTO_GRE=m
239CONFIG_NF_CT_PROTO_SCTP=m
240CONFIG_NF_CT_PROTO_UDPLITE=m
241CONFIG_NF_CONNTRACK_AMANDA=m
242CONFIG_NF_CONNTRACK_FTP=m
243CONFIG_NF_CONNTRACK_H323=m
244CONFIG_NF_CONNTRACK_IRC=m
245CONFIG_NF_CONNTRACK_NETBIOS_NS=m
246CONFIG_NF_CONNTRACK_PPTP=m
247CONFIG_NF_CONNTRACK_SANE=m
248CONFIG_NF_CONNTRACK_SIP=m
249CONFIG_NF_CONNTRACK_TFTP=m
250# CONFIG_NF_CT_NETLINK is not set
251CONFIG_NETFILTER_XTABLES=m
252CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
253CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
254CONFIG_NETFILTER_XT_TARGET_DSCP=m
255CONFIG_NETFILTER_XT_TARGET_MARK=m
256CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
257CONFIG_NETFILTER_XT_TARGET_NFLOG=m
258CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
259CONFIG_NETFILTER_XT_TARGET_RATEEST=m
260CONFIG_NETFILTER_XT_TARGET_TRACE=m
261CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
262CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
263CONFIG_NETFILTER_XT_MATCH_COMMENT=m
264CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
265CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
266CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
267CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
268CONFIG_NETFILTER_XT_MATCH_DCCP=m
269CONFIG_NETFILTER_XT_MATCH_DSCP=m
270CONFIG_NETFILTER_XT_MATCH_ESP=m
271CONFIG_NETFILTER_XT_MATCH_HELPER=m
272CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
273CONFIG_NETFILTER_XT_MATCH_LENGTH=m
274CONFIG_NETFILTER_XT_MATCH_LIMIT=m
275CONFIG_NETFILTER_XT_MATCH_MAC=m
276CONFIG_NETFILTER_XT_MATCH_MARK=m
277CONFIG_NETFILTER_XT_MATCH_OWNER=m
278CONFIG_NETFILTER_XT_MATCH_POLICY=m
279CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
280CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
281CONFIG_NETFILTER_XT_MATCH_QUOTA=m
282CONFIG_NETFILTER_XT_MATCH_RATEEST=m
283CONFIG_NETFILTER_XT_MATCH_REALM=m
284CONFIG_NETFILTER_XT_MATCH_SCTP=m
285CONFIG_NETFILTER_XT_MATCH_STATE=m
286CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
287CONFIG_NETFILTER_XT_MATCH_STRING=m
288CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
289CONFIG_NETFILTER_XT_MATCH_TIME=m
290CONFIG_NETFILTER_XT_MATCH_U32=m
291CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
295 292
296# 293#
297# IP: Netfilter Configuration 294# IP: Netfilter Configuration
298# 295#
299CONFIG_IP_NF_CONNTRACK=m 296CONFIG_NF_CONNTRACK_IPV4=m
300# CONFIG_IP_NF_CT_ACCT is not set 297CONFIG_NF_CONNTRACK_PROC_COMPAT=y
301CONFIG_IP_NF_CONNTRACK_MARK=y
302# CONFIG_IP_NF_CT_PROTO_SCTP is not set
303CONFIG_IP_NF_FTP=m
304CONFIG_IP_NF_IRC=m
305CONFIG_IP_NF_TFTP=m
306CONFIG_IP_NF_AMANDA=m
307CONFIG_IP_NF_QUEUE=m 298CONFIG_IP_NF_QUEUE=m
308CONFIG_IP_NF_IPTABLES=m 299CONFIG_IP_NF_IPTABLES=m
309CONFIG_IP_NF_MATCH_LIMIT=m
310CONFIG_IP_NF_MATCH_IPRANGE=m
311CONFIG_IP_NF_MATCH_MAC=m
312CONFIG_IP_NF_MATCH_PKTTYPE=m
313CONFIG_IP_NF_MATCH_MARK=m
314CONFIG_IP_NF_MATCH_MULTIPORT=m
315CONFIG_IP_NF_MATCH_TOS=m
316CONFIG_IP_NF_MATCH_RECENT=m 300CONFIG_IP_NF_MATCH_RECENT=m
317CONFIG_IP_NF_MATCH_ECN=m 301CONFIG_IP_NF_MATCH_ECN=m
318CONFIG_IP_NF_MATCH_DSCP=m 302CONFIG_IP_NF_MATCH_AH=m
319CONFIG_IP_NF_MATCH_AH_ESP=m
320CONFIG_IP_NF_MATCH_LENGTH=m
321CONFIG_IP_NF_MATCH_TTL=m 303CONFIG_IP_NF_MATCH_TTL=m
322CONFIG_IP_NF_MATCH_TCPMSS=m
323CONFIG_IP_NF_MATCH_HELPER=m
324CONFIG_IP_NF_MATCH_STATE=m
325CONFIG_IP_NF_MATCH_CONNTRACK=m
326CONFIG_IP_NF_MATCH_OWNER=m
327CONFIG_IP_NF_MATCH_ADDRTYPE=m 304CONFIG_IP_NF_MATCH_ADDRTYPE=m
328CONFIG_IP_NF_MATCH_REALM=m
329# CONFIG_IP_NF_MATCH_SCTP is not set
330# CONFIG_IP_NF_MATCH_COMMENT is not set
331CONFIG_IP_NF_MATCH_CONNMARK=m
332CONFIG_IP_NF_MATCH_HASHLIMIT=m
333CONFIG_IP_NF_FILTER=m 305CONFIG_IP_NF_FILTER=m
334CONFIG_IP_NF_TARGET_REJECT=m 306CONFIG_IP_NF_TARGET_REJECT=m
335CONFIG_IP_NF_TARGET_LOG=m 307CONFIG_IP_NF_TARGET_LOG=m
336CONFIG_IP_NF_TARGET_ULOG=m 308CONFIG_IP_NF_TARGET_ULOG=m
337CONFIG_IP_NF_TARGET_TCPMSS=m 309CONFIG_NF_NAT=m
338CONFIG_IP_NF_NAT=m 310CONFIG_NF_NAT_NEEDED=y
339CONFIG_IP_NF_NAT_NEEDED=y
340CONFIG_IP_NF_TARGET_MASQUERADE=m 311CONFIG_IP_NF_TARGET_MASQUERADE=m
341CONFIG_IP_NF_TARGET_REDIRECT=m 312CONFIG_IP_NF_TARGET_REDIRECT=m
342CONFIG_IP_NF_TARGET_NETMAP=m 313CONFIG_IP_NF_TARGET_NETMAP=m
343CONFIG_IP_NF_TARGET_SAME=m 314CONFIG_NF_NAT_SNMP_BASIC=m
344CONFIG_IP_NF_NAT_SNMP_BASIC=m 315CONFIG_NF_NAT_PROTO_GRE=m
345CONFIG_IP_NF_NAT_IRC=m 316CONFIG_NF_NAT_FTP=m
346CONFIG_IP_NF_NAT_FTP=m 317CONFIG_NF_NAT_IRC=m
347CONFIG_IP_NF_NAT_TFTP=m 318CONFIG_NF_NAT_TFTP=m
348CONFIG_IP_NF_NAT_AMANDA=m 319CONFIG_NF_NAT_AMANDA=m
320CONFIG_NF_NAT_PPTP=m
321CONFIG_NF_NAT_H323=m
322CONFIG_NF_NAT_SIP=m
349CONFIG_IP_NF_MANGLE=m 323CONFIG_IP_NF_MANGLE=m
350CONFIG_IP_NF_TARGET_TOS=m
351CONFIG_IP_NF_TARGET_ECN=m 324CONFIG_IP_NF_TARGET_ECN=m
352CONFIG_IP_NF_TARGET_DSCP=m 325CONFIG_IP_NF_TARGET_TTL=m
353CONFIG_IP_NF_TARGET_MARK=m 326CONFIG_IP_NF_TARGET_CLUSTERIP=m
354CONFIG_IP_NF_TARGET_CLASSIFY=m
355CONFIG_IP_NF_TARGET_CONNMARK=m
356# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
357CONFIG_IP_NF_RAW=m 327CONFIG_IP_NF_RAW=m
358CONFIG_IP_NF_TARGET_NOTRACK=m
359CONFIG_IP_NF_ARPTABLES=m 328CONFIG_IP_NF_ARPTABLES=m
360CONFIG_IP_NF_ARPFILTER=m 329CONFIG_IP_NF_ARPFILTER=m
361CONFIG_IP_NF_ARP_MANGLE=m 330CONFIG_IP_NF_ARP_MANGLE=m
362 331
363# 332#
364# IPv6: Netfilter Configuration (EXPERIMENTAL) 333# IPv6: Netfilter Configuration
365# 334#
335CONFIG_NF_CONNTRACK_IPV6=m
366CONFIG_IP6_NF_QUEUE=m 336CONFIG_IP6_NF_QUEUE=m
367CONFIG_IP6_NF_IPTABLES=m 337CONFIG_IP6_NF_IPTABLES=m
368CONFIG_IP6_NF_MATCH_LIMIT=m
369CONFIG_IP6_NF_MATCH_MAC=m
370CONFIG_IP6_NF_MATCH_RT=m 338CONFIG_IP6_NF_MATCH_RT=m
371CONFIG_IP6_NF_MATCH_OPTS=m 339CONFIG_IP6_NF_MATCH_OPTS=m
372CONFIG_IP6_NF_MATCH_FRAG=m 340CONFIG_IP6_NF_MATCH_FRAG=m
373CONFIG_IP6_NF_MATCH_HL=m 341CONFIG_IP6_NF_MATCH_HL=m
374CONFIG_IP6_NF_MATCH_MULTIPORT=m
375CONFIG_IP6_NF_MATCH_OWNER=m
376CONFIG_IP6_NF_MATCH_MARK=m
377CONFIG_IP6_NF_MATCH_IPV6HEADER=m 342CONFIG_IP6_NF_MATCH_IPV6HEADER=m
378CONFIG_IP6_NF_MATCH_AHESP=m 343CONFIG_IP6_NF_MATCH_AH=m
379CONFIG_IP6_NF_MATCH_LENGTH=m 344CONFIG_IP6_NF_MATCH_MH=m
380CONFIG_IP6_NF_MATCH_EUI64=m 345CONFIG_IP6_NF_MATCH_EUI64=m
381CONFIG_IP6_NF_FILTER=m 346CONFIG_IP6_NF_FILTER=m
382CONFIG_IP6_NF_TARGET_LOG=m 347CONFIG_IP6_NF_TARGET_LOG=m
348CONFIG_IP6_NF_TARGET_REJECT=m
383CONFIG_IP6_NF_MANGLE=m 349CONFIG_IP6_NF_MANGLE=m
384CONFIG_IP6_NF_TARGET_MARK=m 350CONFIG_IP6_NF_TARGET_HL=m
385CONFIG_IP6_NF_RAW=m 351CONFIG_IP6_NF_RAW=m
386CONFIG_XFRM=y 352CONFIG_IP_DCCP=m
387CONFIG_XFRM_USER=m 353CONFIG_INET_DCCP_DIAG=m
354CONFIG_IP_DCCP_ACKVEC=y
388 355
389# 356#
390# SCTP Configuration (EXPERIMENTAL) 357# DCCP CCIDs Configuration (EXPERIMENTAL)
391# 358#
359CONFIG_IP_DCCP_CCID2=m
360# CONFIG_IP_DCCP_CCID2_DEBUG is not set
361CONFIG_IP_DCCP_CCID3=m
362# CONFIG_IP_DCCP_CCID3_DEBUG is not set
363CONFIG_IP_DCCP_CCID3_RTO=100
364CONFIG_IP_DCCP_TFRC_LIB=m
392CONFIG_IP_SCTP=m 365CONFIG_IP_SCTP=m
393# CONFIG_SCTP_DBG_MSG is not set 366# CONFIG_SCTP_DBG_MSG is not set
394# CONFIG_SCTP_DBG_OBJCNT is not set 367# CONFIG_SCTP_DBG_OBJCNT is not set
395# CONFIG_SCTP_HMAC_NONE is not set 368# CONFIG_SCTP_HMAC_NONE is not set
396# CONFIG_SCTP_HMAC_SHA1 is not set 369# CONFIG_SCTP_HMAC_SHA1 is not set
397CONFIG_SCTP_HMAC_MD5=y 370CONFIG_SCTP_HMAC_MD5=y
371# CONFIG_TIPC is not set
398# CONFIG_ATM is not set 372# CONFIG_ATM is not set
399# CONFIG_BRIDGE is not set 373# CONFIG_BRIDGE is not set
400# CONFIG_VLAN_8021Q is not set 374# CONFIG_VLAN_8021Q is not set
401# CONFIG_DECNET is not set 375# CONFIG_DECNET is not set
402CONFIG_LLC=m 376CONFIG_LLC=m
403# CONFIG_LLC2 is not set 377# CONFIG_LLC2 is not set
404CONFIG_IPX=m 378# CONFIG_IPX is not set
405# CONFIG_IPX_INTERN is not set
406CONFIG_ATALK=m 379CONFIG_ATALK=m
407# CONFIG_DEV_APPLETALK is not set 380# CONFIG_DEV_APPLETALK is not set
408# CONFIG_X25 is not set 381# CONFIG_X25 is not set
409# CONFIG_LAPB is not set 382# CONFIG_LAPB is not set
410# CONFIG_NET_DIVERT is not set
411# CONFIG_ECONET is not set 383# CONFIG_ECONET is not set
412# CONFIG_WAN_ROUTER is not set 384# CONFIG_WAN_ROUTER is not set
413
414#
415# QoS and/or fair queueing
416#
417# CONFIG_NET_SCHED is not set 385# CONFIG_NET_SCHED is not set
418CONFIG_NET_CLS_ROUTE=y 386CONFIG_NET_CLS_ROUTE=y
419 387
@@ -421,46 +389,189 @@ CONFIG_NET_CLS_ROUTE=y
421# Network testing 389# Network testing
422# 390#
423# CONFIG_NET_PKTGEN is not set 391# CONFIG_NET_PKTGEN is not set
424CONFIG_NETPOLL=y
425# CONFIG_NETPOLL_RX is not set
426# CONFIG_NETPOLL_TRAP is not set
427CONFIG_NET_POLL_CONTROLLER=y
428# CONFIG_HAMRADIO is not set 392# CONFIG_HAMRADIO is not set
393# CONFIG_CAN is not set
429# CONFIG_IRDA is not set 394# CONFIG_IRDA is not set
430# CONFIG_BT is not set 395# CONFIG_BT is not set
431CONFIG_NETDEVICES=y 396# CONFIG_AF_RXRPC is not set
432CONFIG_DUMMY=m
433# CONFIG_BONDING is not set
434CONFIG_EQUALIZER=m
435# CONFIG_TUN is not set
436 397
437# 398#
438# Ethernet (10 or 100Mbit) 399# Wireless
439# 400#
440CONFIG_NET_ETHERNET=y 401# CONFIG_CFG80211 is not set
441CONFIG_MII=m 402CONFIG_WIRELESS_EXT=y
442CONFIG_ATARILANCE=m 403# CONFIG_MAC80211 is not set
404CONFIG_IEEE80211=m
405# CONFIG_IEEE80211_DEBUG is not set
406CONFIG_IEEE80211_CRYPT_WEP=m
407CONFIG_IEEE80211_CRYPT_CCMP=m
408CONFIG_IEEE80211_CRYPT_TKIP=m
409CONFIG_IEEE80211_SOFTMAC=m
410# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
411# CONFIG_RFKILL is not set
412# CONFIG_NET_9P is not set
413
414#
415# Device Drivers
416#
417
418#
419# Generic Driver Options
420#
421CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
422CONFIG_STANDALONE=y
423CONFIG_PREVENT_FIRMWARE_BUILD=y
424CONFIG_FW_LOADER=m
425# CONFIG_SYS_HYPERVISOR is not set
426CONFIG_CONNECTOR=m
427# CONFIG_MTD is not set
428CONFIG_PARPORT=m
429CONFIG_PARPORT_ATARI=m
430# CONFIG_PARPORT_GSC is not set
431# CONFIG_PARPORT_AX88796 is not set
432CONFIG_PARPORT_1284=y
433CONFIG_PARPORT_NOT_PC=y
434CONFIG_BLK_DEV=y
435CONFIG_ATARI_FLOPPY=y
436# CONFIG_BLK_DEV_COW_COMMON is not set
437CONFIG_BLK_DEV_LOOP=y
438CONFIG_BLK_DEV_CRYPTOLOOP=m
439CONFIG_BLK_DEV_NBD=m
440CONFIG_BLK_DEV_RAM=y
441CONFIG_BLK_DEV_RAM_COUNT=16
442CONFIG_BLK_DEV_RAM_SIZE=4096
443# CONFIG_BLK_DEV_XIP is not set
444CONFIG_CDROM_PKTCDVD=m
445CONFIG_CDROM_PKTCDVD_BUFFERS=8
446# CONFIG_CDROM_PKTCDVD_WCACHE is not set
447CONFIG_ATA_OVER_ETH=m
448CONFIG_MISC_DEVICES=y
449# CONFIG_EEPROM_93CX6 is not set
450# CONFIG_ENCLOSURE_SERVICES is not set
451CONFIG_HAVE_IDE=y
452CONFIG_IDE=y
453CONFIG_BLK_DEV_IDE=y
454
455#
456# Please see Documentation/ide/ide.txt for help/info on IDE drives
457#
458# CONFIG_BLK_DEV_IDE_SATA is not set
459CONFIG_BLK_DEV_IDEDISK=y
460# CONFIG_IDEDISK_MULTI_MODE is not set
461CONFIG_BLK_DEV_IDECD=y
462CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
463# CONFIG_BLK_DEV_IDETAPE is not set
464CONFIG_BLK_DEV_IDEFLOPPY=m
465# CONFIG_BLK_DEV_IDESCSI is not set
466# CONFIG_IDE_TASK_IOCTL is not set
467CONFIG_IDE_PROC_FS=y
443 468
444# 469#
445# Ethernet (1000 Mbit) 470# IDE chipset support/bugfixes
446# 471#
472# CONFIG_IDE_GENERIC is not set
473# CONFIG_BLK_DEV_PLATFORM is not set
474CONFIG_BLK_DEV_FALCON_IDE=y
475# CONFIG_BLK_DEV_IDEDMA is not set
476# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
477# CONFIG_BLK_DEV_HD is not set
447 478
448# 479#
449# Ethernet (10000 Mbit) 480# SCSI device support
450# 481#
482CONFIG_RAID_ATTRS=m
483CONFIG_SCSI=y
484CONFIG_SCSI_DMA=y
485CONFIG_SCSI_TGT=m
486# CONFIG_SCSI_NETLINK is not set
487CONFIG_SCSI_PROC_FS=y
451 488
452# 489#
453# Token Ring devices 490# SCSI support type (disk, tape, CD-ROM)
491#
492CONFIG_BLK_DEV_SD=y
493CONFIG_CHR_DEV_ST=m
494CONFIG_CHR_DEV_OSST=m
495CONFIG_BLK_DEV_SR=y
496CONFIG_BLK_DEV_SR_VENDOR=y
497CONFIG_CHR_DEV_SG=m
498# CONFIG_CHR_DEV_SCH is not set
499
500#
501# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
454# 502#
503# CONFIG_SCSI_MULTI_LUN is not set
504CONFIG_SCSI_CONSTANTS=y
505# CONFIG_SCSI_LOGGING is not set
506# CONFIG_SCSI_SCAN_ASYNC is not set
507CONFIG_SCSI_WAIT_SCAN=m
455 508
456# 509#
457# Wireless LAN (non-hamradio) 510# SCSI Transports
458# 511#
459# CONFIG_NET_RADIO is not set 512CONFIG_SCSI_SPI_ATTRS=y
513# CONFIG_SCSI_FC_ATTRS is not set
514CONFIG_SCSI_ISCSI_ATTRS=m
515CONFIG_SCSI_SAS_ATTRS=m
516CONFIG_SCSI_SAS_LIBSAS=m
517CONFIG_SCSI_SAS_HOST_SMP=y
518# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
519CONFIG_SCSI_SRP_ATTRS=m
520CONFIG_SCSI_SRP_TGT_ATTRS=y
521CONFIG_SCSI_LOWLEVEL=y
522CONFIG_ISCSI_TCP=m
523# CONFIG_SCSI_DEBUG is not set
524CONFIG_ATARI_SCSI=y
525# CONFIG_ATARI_SCSI_TOSHIBA_DELAY is not set
526# CONFIG_ATARI_SCSI_RESET_BOOT is not set
527CONFIG_MD=y
528CONFIG_BLK_DEV_MD=m
529CONFIG_MD_LINEAR=m
530CONFIG_MD_RAID0=m
531CONFIG_MD_RAID1=m
532# CONFIG_MD_RAID10 is not set
533CONFIG_MD_RAID456=m
534CONFIG_MD_RAID5_RESHAPE=y
535CONFIG_MD_MULTIPATH=m
536# CONFIG_MD_FAULTY is not set
537CONFIG_BLK_DEV_DM=m
538# CONFIG_DM_DEBUG is not set
539CONFIG_DM_CRYPT=m
540CONFIG_DM_SNAPSHOT=m
541CONFIG_DM_MIRROR=m
542CONFIG_DM_ZERO=m
543CONFIG_DM_MULTIPATH=m
544CONFIG_DM_MULTIPATH_EMC=m
545CONFIG_DM_MULTIPATH_RDAC=m
546CONFIG_DM_MULTIPATH_HP=m
547# CONFIG_DM_DELAY is not set
548CONFIG_DM_UEVENT=y
549CONFIG_NETDEVICES=y
550# CONFIG_NETDEVICES_MULTIQUEUE is not set
551CONFIG_DUMMY=m
552# CONFIG_BONDING is not set
553CONFIG_MACVLAN=m
554CONFIG_EQUALIZER=m
555# CONFIG_TUN is not set
556CONFIG_VETH=m
557# CONFIG_PHYLIB is not set
558CONFIG_NET_ETHERNET=y
559CONFIG_MII=m
560CONFIG_ATARILANCE=m
561# CONFIG_IBM_NEW_EMAC_ZMII is not set
562# CONFIG_IBM_NEW_EMAC_RGMII is not set
563# CONFIG_IBM_NEW_EMAC_TAH is not set
564# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
565# CONFIG_B44 is not set
566# CONFIG_NET_POCKET is not set
567# CONFIG_NETDEV_1000 is not set
568# CONFIG_NETDEV_10000 is not set
460 569
461# 570#
462# Wan interfaces 571# Wireless LAN
463# 572#
573# CONFIG_WLAN_PRE80211 is not set
574# CONFIG_WLAN_80211 is not set
464# CONFIG_WAN is not set 575# CONFIG_WAN is not set
465# CONFIG_PLIP is not set 576# CONFIG_PLIP is not set
466CONFIG_PPP=m 577CONFIG_PPP=m
@@ -470,28 +581,28 @@ CONFIG_PPP_ASYNC=m
470CONFIG_PPP_SYNC_TTY=m 581CONFIG_PPP_SYNC_TTY=m
471CONFIG_PPP_DEFLATE=m 582CONFIG_PPP_DEFLATE=m
472CONFIG_PPP_BSDCOMP=m 583CONFIG_PPP_BSDCOMP=m
584CONFIG_PPP_MPPE=m
473CONFIG_PPPOE=m 585CONFIG_PPPOE=m
586CONFIG_PPPOL2TP=m
474CONFIG_SLIP=m 587CONFIG_SLIP=m
475CONFIG_SLIP_COMPRESSED=y 588CONFIG_SLIP_COMPRESSED=y
589CONFIG_SLHC=m
476CONFIG_SLIP_SMART=y 590CONFIG_SLIP_SMART=y
477CONFIG_SLIP_MODE_SLIP6=y 591CONFIG_SLIP_MODE_SLIP6=y
478CONFIG_SHAPER=m
479CONFIG_NETCONSOLE=m 592CONFIG_NETCONSOLE=m
480 593CONFIG_NETCONSOLE_DYNAMIC=y
481# 594CONFIG_NETPOLL=y
482# ISDN subsystem 595# CONFIG_NETPOLL_TRAP is not set
483# 596CONFIG_NET_POLL_CONTROLLER=y
484# CONFIG_ISDN is not set 597# CONFIG_ISDN is not set
485
486#
487# Telephony Support
488#
489# CONFIG_PHONE is not set 598# CONFIG_PHONE is not set
490 599
491# 600#
492# Input device support 601# Input device support
493# 602#
494CONFIG_INPUT=y 603CONFIG_INPUT=y
604CONFIG_INPUT_FF_MEMLESS=m
605# CONFIG_INPUT_POLLDEV is not set
495 606
496# 607#
497# Userland interfaces 608# Userland interfaces
@@ -501,7 +612,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
501CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 612CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
502CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 613CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
503# CONFIG_INPUT_JOYDEV is not set 614# CONFIG_INPUT_JOYDEV is not set
504# CONFIG_INPUT_TSDEV is not set
505# CONFIG_INPUT_EVDEV is not set 615# CONFIG_INPUT_EVDEV is not set
506# CONFIG_INPUT_EVBUG is not set 616# CONFIG_INPUT_EVBUG is not set
507 617
@@ -509,26 +619,37 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
509# Input Device Drivers 619# Input Device Drivers
510# 620#
511CONFIG_INPUT_KEYBOARD=y 621CONFIG_INPUT_KEYBOARD=y
512CONFIG_KEYBOARD_ATKBD=y 622# CONFIG_KEYBOARD_ATKBD is not set
513# CONFIG_KEYBOARD_SUNKBD is not set 623# CONFIG_KEYBOARD_SUNKBD is not set
514# CONFIG_KEYBOARD_LKKBD is not set 624# CONFIG_KEYBOARD_LKKBD is not set
515# CONFIG_KEYBOARD_XTKBD is not set 625# CONFIG_KEYBOARD_XTKBD is not set
516# CONFIG_KEYBOARD_NEWTON is not set 626# CONFIG_KEYBOARD_NEWTON is not set
627# CONFIG_KEYBOARD_STOWAWAY is not set
628CONFIG_ATARI_KBD_CORE=y
629CONFIG_KEYBOARD_ATARI=y
517CONFIG_INPUT_MOUSE=y 630CONFIG_INPUT_MOUSE=y
518CONFIG_MOUSE_PS2=y 631CONFIG_MOUSE_PS2=y
632CONFIG_MOUSE_PS2_ALPS=y
633CONFIG_MOUSE_PS2_LOGIPS2PP=y
634CONFIG_MOUSE_PS2_SYNAPTICS=y
635CONFIG_MOUSE_PS2_LIFEBOOK=y
636CONFIG_MOUSE_PS2_TRACKPOINT=y
637# CONFIG_MOUSE_PS2_TOUCHKIT is not set
519# CONFIG_MOUSE_SERIAL is not set 638# CONFIG_MOUSE_SERIAL is not set
639CONFIG_MOUSE_ATARI=m
520# CONFIG_MOUSE_VSXXXAA is not set 640# CONFIG_MOUSE_VSXXXAA is not set
521# CONFIG_INPUT_JOYSTICK is not set 641# CONFIG_INPUT_JOYSTICK is not set
642# CONFIG_INPUT_TABLET is not set
522# CONFIG_INPUT_TOUCHSCREEN is not set 643# CONFIG_INPUT_TOUCHSCREEN is not set
523CONFIG_INPUT_MISC=y 644CONFIG_INPUT_MISC=y
524CONFIG_INPUT_M68K_BEEP=m 645CONFIG_INPUT_M68K_BEEP=m
525CONFIG_INPUT_UINPUT=m 646# CONFIG_INPUT_UINPUT is not set
526 647
527# 648#
528# Hardware I/O ports 649# Hardware I/O ports
529# 650#
530CONFIG_SERIO=y 651CONFIG_SERIO=y
531CONFIG_SERIO_SERPORT=y 652# CONFIG_SERIO_SERPORT is not set
532# CONFIG_SERIO_PARKBD is not set 653# CONFIG_SERIO_PARKBD is not set
533CONFIG_SERIO_LIBPS2=y 654CONFIG_SERIO_LIBPS2=y
534# CONFIG_SERIO_RAW is not set 655# CONFIG_SERIO_RAW is not set
@@ -540,6 +661,7 @@ CONFIG_SERIO_LIBPS2=y
540CONFIG_VT=y 661CONFIG_VT=y
541CONFIG_VT_CONSOLE=y 662CONFIG_VT_CONSOLE=y
542CONFIG_HW_CONSOLE=y 663CONFIG_HW_CONSOLE=y
664CONFIG_VT_HW_CONSOLE_BINDING=y
543# CONFIG_SERIAL_NONSTANDARD is not set 665# CONFIG_SERIAL_NONSTANDARD is not set
544 666
545# 667#
@@ -556,86 +678,97 @@ CONFIG_LEGACY_PTY_COUNT=256
556CONFIG_PRINTER=m 678CONFIG_PRINTER=m
557# CONFIG_LP_CONSOLE is not set 679# CONFIG_LP_CONSOLE is not set
558# CONFIG_PPDEV is not set 680# CONFIG_PPDEV is not set
559# CONFIG_TIPAR is not set
560
561#
562# IPMI
563#
564# CONFIG_IPMI_HANDLER is not set 681# CONFIG_IPMI_HANDLER is not set
565 682# CONFIG_HW_RANDOM is not set
566#
567# Watchdog Cards
568#
569# CONFIG_WATCHDOG is not set
570CONFIG_NVRAM=y 683CONFIG_NVRAM=y
571CONFIG_GEN_RTC=y 684CONFIG_GEN_RTC=m
572CONFIG_GEN_RTC_X=y 685CONFIG_GEN_RTC_X=y
573# CONFIG_DTLK is not set
574# CONFIG_R3964 is not set 686# CONFIG_R3964 is not set
575
576#
577# Ftape, the floppy tape device driver
578#
579# CONFIG_DRM is not set
580# CONFIG_RAW_DRIVER is not set 687# CONFIG_RAW_DRIVER is not set
581 688# CONFIG_TCG_TPM is not set
582#
583# TPM devices
584#
585
586#
587# I2C support
588#
589# CONFIG_I2C is not set 689# CONFIG_I2C is not set
590 690
591# 691#
592# Dallas's 1-wire bus 692# SPI support
593# 693#
694# CONFIG_SPI is not set
695# CONFIG_SPI_MASTER is not set
594# CONFIG_W1 is not set 696# CONFIG_W1 is not set
697# CONFIG_POWER_SUPPLY is not set
698# CONFIG_HWMON is not set
699# CONFIG_THERMAL is not set
700# CONFIG_WATCHDOG is not set
595 701
596# 702#
597# Misc devices 703# Sonics Silicon Backplane
598# 704#
705CONFIG_SSB_POSSIBLE=y
706# CONFIG_SSB is not set
599 707
600# 708#
601# Multimedia devices 709# Multifunction device drivers
602# 710#
603# CONFIG_VIDEO_DEV is not set 711# CONFIG_MFD_SM501 is not set
604 712
605# 713#
606# Digital Video Broadcasting Devices 714# Multimedia devices
607# 715#
608# CONFIG_DVB is not set 716# CONFIG_VIDEO_DEV is not set
717# CONFIG_DVB_CORE is not set
718# CONFIG_DAB is not set
609 719
610# 720#
611# Graphics support 721# Graphics support
612# 722#
723# CONFIG_VGASTATE is not set
724# CONFIG_VIDEO_OUTPUT_CONTROL is not set
613CONFIG_FB=y 725CONFIG_FB=y
614# CONFIG_FB_CFB_FILLRECT is not set 726# CONFIG_FIRMWARE_EDID is not set
615# CONFIG_FB_CFB_COPYAREA is not set 727# CONFIG_FB_DDC is not set
616# CONFIG_FB_CFB_IMAGEBLIT is not set 728CONFIG_FB_CFB_FILLRECT=y
617# CONFIG_FB_SOFT_CURSOR is not set 729CONFIG_FB_CFB_COPYAREA=y
730CONFIG_FB_CFB_IMAGEBLIT=y
731# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
732# CONFIG_FB_SYS_FILLRECT is not set
733# CONFIG_FB_SYS_COPYAREA is not set
734# CONFIG_FB_SYS_IMAGEBLIT is not set
735# CONFIG_FB_SYS_FOPS is not set
736CONFIG_FB_DEFERRED_IO=y
737# CONFIG_FB_SVGALIB is not set
618# CONFIG_FB_MACMODES is not set 738# CONFIG_FB_MACMODES is not set
619CONFIG_FB_MODE_HELPERS=y 739# CONFIG_FB_BACKLIGHT is not set
740# CONFIG_FB_MODE_HELPERS is not set
620# CONFIG_FB_TILEBLITTING is not set 741# CONFIG_FB_TILEBLITTING is not set
621# CONFIG_FB_ATY is not set 742
743#
744# Frame buffer hardware drivers
745#
746CONFIG_FB_ATARI=y
747# CONFIG_FB_UVESA is not set
622# CONFIG_FB_S1D13XXX is not set 748# CONFIG_FB_S1D13XXX is not set
749# CONFIG_FB_ATY is not set
623# CONFIG_FB_VIRTUAL is not set 750# CONFIG_FB_VIRTUAL is not set
751# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
752
753#
754# Display device support
755#
756# CONFIG_DISPLAY_SUPPORT is not set
624 757
625# 758#
626# Console display driver support 759# Console display driver support
627# 760#
628CONFIG_DUMMY_CONSOLE=y 761CONFIG_DUMMY_CONSOLE=y
629CONFIG_FRAMEBUFFER_CONSOLE=y 762CONFIG_FRAMEBUFFER_CONSOLE=y
763# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
764# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
630# CONFIG_FONTS is not set 765# CONFIG_FONTS is not set
631CONFIG_FONT_8x8=y 766CONFIG_FONT_8x8=y
632CONFIG_FONT_8x16=y 767CONFIG_FONT_8x16=y
633 768CONFIG_LOGO=y
634# 769CONFIG_LOGO_LINUX_MONO=y
635# Logo configuration 770CONFIG_LOGO_LINUX_VGA16=y
636# 771CONFIG_LOGO_LINUX_CLUT224=y
637# CONFIG_LOGO is not set
638# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
639 772
640# 773#
641# Sound 774# Sound
@@ -643,27 +776,21 @@ CONFIG_FONT_8x16=y
643CONFIG_SOUND=m 776CONFIG_SOUND=m
644CONFIG_DMASOUND_ATARI=m 777CONFIG_DMASOUND_ATARI=m
645CONFIG_DMASOUND=m 778CONFIG_DMASOUND=m
646 779CONFIG_HID_SUPPORT=y
647# 780CONFIG_HID=m
648# USB support 781# CONFIG_HID_DEBUG is not set
649# 782CONFIG_HIDRAW=y
650# CONFIG_USB_ARCH_HAS_HCD is not set 783# CONFIG_USB_SUPPORT is not set
651# CONFIG_USB_ARCH_HAS_OHCI is not set
652
653#
654# USB Gadget Support
655#
656# CONFIG_USB_GADGET is not set
657
658#
659# MMC/SD Card support
660#
661# CONFIG_MMC is not set 784# CONFIG_MMC is not set
785# CONFIG_MEMSTICK is not set
786# CONFIG_NEW_LEDS is not set
787# CONFIG_RTC_CLASS is not set
788# CONFIG_AUXDISPLAY is not set
662 789
663# 790#
664# InfiniBand support 791# Userspace I/O
665# 792#
666# CONFIG_INFINIBAND is not set 793# CONFIG_UIO is not set
667 794
668# 795#
669# Character devices 796# Character devices
@@ -680,38 +807,44 @@ CONFIG_ATARI_DSP56K=m
680# 807#
681CONFIG_EXT2_FS=y 808CONFIG_EXT2_FS=y
682# CONFIG_EXT2_FS_XATTR is not set 809# CONFIG_EXT2_FS_XATTR is not set
810# CONFIG_EXT2_FS_XIP is not set
683CONFIG_EXT3_FS=y 811CONFIG_EXT3_FS=y
684# CONFIG_EXT3_FS_XATTR is not set 812# CONFIG_EXT3_FS_XATTR is not set
813# CONFIG_EXT4DEV_FS is not set
685CONFIG_JBD=y 814CONFIG_JBD=y
686# CONFIG_JBD_DEBUG is not set
687CONFIG_REISERFS_FS=m 815CONFIG_REISERFS_FS=m
688# CONFIG_REISERFS_CHECK is not set 816# CONFIG_REISERFS_CHECK is not set
689CONFIG_REISERFS_PROC_INFO=y 817# CONFIG_REISERFS_PROC_INFO is not set
690# CONFIG_REISERFS_FS_XATTR is not set 818# CONFIG_REISERFS_FS_XATTR is not set
691CONFIG_JFS_FS=m 819CONFIG_JFS_FS=m
692# CONFIG_JFS_POSIX_ACL is not set 820# CONFIG_JFS_POSIX_ACL is not set
693# CONFIG_JFS_SECURITY is not set 821# CONFIG_JFS_SECURITY is not set
694# CONFIG_JFS_DEBUG is not set 822# CONFIG_JFS_DEBUG is not set
695# CONFIG_JFS_STATISTICS is not set 823# CONFIG_JFS_STATISTICS is not set
696 824CONFIG_FS_POSIX_ACL=y
697#
698# XFS support
699#
700CONFIG_XFS_FS=m 825CONFIG_XFS_FS=m
701CONFIG_XFS_EXPORT=y
702# CONFIG_XFS_RT is not set
703# CONFIG_XFS_QUOTA is not set 826# CONFIG_XFS_QUOTA is not set
704# CONFIG_XFS_SECURITY is not set 827# CONFIG_XFS_SECURITY is not set
705# CONFIG_XFS_POSIX_ACL is not set 828# CONFIG_XFS_POSIX_ACL is not set
706CONFIG_MINIX_FS=y 829# CONFIG_XFS_RT is not set
707# CONFIG_ROMFS_FS is not set 830CONFIG_GFS2_FS=m
831CONFIG_GFS2_FS_LOCKING_NOLOCK=m
832CONFIG_GFS2_FS_LOCKING_DLM=m
833CONFIG_OCFS2_FS=m
834# CONFIG_OCFS2_DEBUG_MASKLOG is not set
835# CONFIG_OCFS2_DEBUG_FS is not set
836CONFIG_DNOTIFY=y
837CONFIG_INOTIFY=y
838CONFIG_INOTIFY_USER=y
708CONFIG_QUOTA=y 839CONFIG_QUOTA=y
840CONFIG_QUOTA_NETLINK_INTERFACE=y
841# CONFIG_PRINT_QUOTA_WARNING is not set
709# CONFIG_QFMT_V1 is not set 842# CONFIG_QFMT_V1 is not set
710# CONFIG_QFMT_V2 is not set 843# CONFIG_QFMT_V2 is not set
711CONFIG_QUOTACTL=y 844CONFIG_QUOTACTL=y
712CONFIG_DNOTIFY=y
713CONFIG_AUTOFS_FS=m 845CONFIG_AUTOFS_FS=m
714CONFIG_AUTOFS4_FS=m 846CONFIG_AUTOFS4_FS=m
847CONFIG_FUSE_FS=m
715 848
716# 849#
717# CD-ROM/DVD Filesystems 850# CD-ROM/DVD Filesystems
@@ -719,7 +852,6 @@ CONFIG_AUTOFS4_FS=m
719CONFIG_ISO9660_FS=y 852CONFIG_ISO9660_FS=y
720CONFIG_JOLIET=y 853CONFIG_JOLIET=y
721CONFIG_ZISOFS=y 854CONFIG_ZISOFS=y
722CONFIG_ZISOFS_FS=y
723CONFIG_UDF_FS=m 855CONFIG_UDF_FS=m
724CONFIG_UDF_NLS=y 856CONFIG_UDF_NLS=y
725 857
@@ -738,13 +870,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
738# 870#
739CONFIG_PROC_FS=y 871CONFIG_PROC_FS=y
740CONFIG_PROC_KCORE=y 872CONFIG_PROC_KCORE=y
873CONFIG_PROC_SYSCTL=y
741CONFIG_SYSFS=y 874CONFIG_SYSFS=y
742# CONFIG_DEVFS_FS is not set
743# CONFIG_DEVPTS_FS_XATTR is not set
744CONFIG_TMPFS=y 875CONFIG_TMPFS=y
745# CONFIG_TMPFS_XATTR is not set 876# CONFIG_TMPFS_POSIX_ACL is not set
746# CONFIG_HUGETLB_PAGE is not set 877# CONFIG_HUGETLB_PAGE is not set
747CONFIG_RAMFS=y 878CONFIG_CONFIGFS_FS=m
748 879
749# 880#
750# Miscellaneous filesystems 881# Miscellaneous filesystems
@@ -758,42 +889,38 @@ CONFIG_HFSPLUS_FS=m
758# CONFIG_EFS_FS is not set 889# CONFIG_EFS_FS is not set
759CONFIG_CRAMFS=m 890CONFIG_CRAMFS=m
760# CONFIG_VXFS_FS is not set 891# CONFIG_VXFS_FS is not set
892CONFIG_MINIX_FS=y
761CONFIG_HPFS_FS=m 893CONFIG_HPFS_FS=m
762# CONFIG_QNX4FS_FS is not set 894# CONFIG_QNX4FS_FS is not set
895# CONFIG_ROMFS_FS is not set
763CONFIG_SYSV_FS=m 896CONFIG_SYSV_FS=m
764CONFIG_UFS_FS=m 897CONFIG_UFS_FS=m
765# CONFIG_UFS_FS_WRITE is not set 898# CONFIG_UFS_FS_WRITE is not set
766 899# CONFIG_UFS_DEBUG is not set
767# 900CONFIG_NETWORK_FILESYSTEMS=y
768# Network File Systems
769#
770CONFIG_NFS_FS=m 901CONFIG_NFS_FS=m
771CONFIG_NFS_V3=y 902CONFIG_NFS_V3=y
903# CONFIG_NFS_V3_ACL is not set
772# CONFIG_NFS_V4 is not set 904# CONFIG_NFS_V4 is not set
773# CONFIG_NFS_DIRECTIO is not set 905# CONFIG_NFS_DIRECTIO is not set
774CONFIG_NFSD=m 906CONFIG_NFSD=m
775CONFIG_NFSD_V3=y 907CONFIG_NFSD_V3=y
908# CONFIG_NFSD_V3_ACL is not set
776# CONFIG_NFSD_V4 is not set 909# CONFIG_NFSD_V4 is not set
777CONFIG_NFSD_TCP=y 910CONFIG_NFSD_TCP=y
778CONFIG_LOCKD=m 911CONFIG_LOCKD=m
779CONFIG_LOCKD_V4=y 912CONFIG_LOCKD_V4=y
780CONFIG_EXPORTFS=m 913CONFIG_EXPORTFS=m
914CONFIG_NFS_COMMON=y
781CONFIG_SUNRPC=m 915CONFIG_SUNRPC=m
916CONFIG_SUNRPC_BIND34=y
782# CONFIG_RPCSEC_GSS_KRB5 is not set 917# CONFIG_RPCSEC_GSS_KRB5 is not set
783# CONFIG_RPCSEC_GSS_SPKM3 is not set 918# CONFIG_RPCSEC_GSS_SPKM3 is not set
784CONFIG_SMB_FS=m 919CONFIG_SMB_FS=m
785CONFIG_SMB_NLS_DEFAULT=y 920CONFIG_SMB_NLS_DEFAULT=y
786CONFIG_SMB_NLS_REMOTE="cp437" 921CONFIG_SMB_NLS_REMOTE="cp437"
787# CONFIG_CIFS is not set 922# CONFIG_CIFS is not set
788CONFIG_NCP_FS=m 923# CONFIG_NCP_FS is not set
789# CONFIG_NCPFS_PACKET_SIGNING is not set
790# CONFIG_NCPFS_IOCTL_LOCKING is not set
791# CONFIG_NCPFS_STRONG is not set
792CONFIG_NCPFS_NFS_NS=y
793CONFIG_NCPFS_OS2_NS=y
794# CONFIG_NCPFS_SMALLDOS is not set
795CONFIG_NCPFS_NLS=y
796# CONFIG_NCPFS_EXTRAS is not set
797CONFIG_CODA_FS=m 924CONFIG_CODA_FS=m
798# CONFIG_CODA_FS_OLD_API is not set 925# CONFIG_CODA_FS_OLD_API is not set
799# CONFIG_AFS_FS is not set 926# CONFIG_AFS_FS is not set
@@ -804,10 +931,6 @@ CONFIG_CODA_FS=m
804# CONFIG_PARTITION_ADVANCED is not set 931# CONFIG_PARTITION_ADVANCED is not set
805CONFIG_ATARI_PARTITION=y 932CONFIG_ATARI_PARTITION=y
806CONFIG_MSDOS_PARTITION=y 933CONFIG_MSDOS_PARTITION=y
807
808#
809# Native Language Support
810#
811CONFIG_NLS=y 934CONFIG_NLS=y
812CONFIG_NLS_DEFAULT="iso8859-1" 935CONFIG_NLS_DEFAULT="iso8859-1"
813CONFIG_NLS_CODEPAGE_437=y 936CONFIG_NLS_CODEPAGE_437=y
@@ -848,35 +971,42 @@ CONFIG_NLS_ISO8859_15=m
848CONFIG_NLS_KOI8_R=m 971CONFIG_NLS_KOI8_R=m
849CONFIG_NLS_KOI8_U=m 972CONFIG_NLS_KOI8_U=m
850CONFIG_NLS_UTF8=m 973CONFIG_NLS_UTF8=m
974CONFIG_DLM=m
975# CONFIG_DLM_DEBUG is not set
851 976
852# 977#
853# Kernel hacking 978# Kernel hacking
854# 979#
855# CONFIG_PRINTK_TIME is not set 980# CONFIG_PRINTK_TIME is not set
856CONFIG_DEBUG_KERNEL=y 981CONFIG_ENABLE_WARN_DEPRECATED=y
982CONFIG_ENABLE_MUST_CHECK=y
857CONFIG_MAGIC_SYSRQ=y 983CONFIG_MAGIC_SYSRQ=y
858CONFIG_LOG_BUF_SHIFT=16 984# CONFIG_UNUSED_SYMBOLS is not set
859# CONFIG_SCHEDSTATS is not set
860# CONFIG_DEBUG_SLAB is not set
861# CONFIG_DEBUG_SPINLOCK is not set
862# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
863# CONFIG_DEBUG_KOBJECT is not set
864CONFIG_DEBUG_BUGVERBOSE=y
865# CONFIG_DEBUG_INFO is not set
866# CONFIG_DEBUG_FS is not set 985# CONFIG_DEBUG_FS is not set
867# CONFIG_FRAME_POINTER is not set 986# CONFIG_HEADERS_CHECK is not set
987# CONFIG_DEBUG_KERNEL is not set
988CONFIG_DEBUG_BUGVERBOSE=y
989# CONFIG_SAMPLES is not set
868 990
869# 991#
870# Security options 992# Security options
871# 993#
872# CONFIG_KEYS is not set 994# CONFIG_KEYS is not set
873# CONFIG_SECURITY is not set 995# CONFIG_SECURITY is not set
874 996# CONFIG_SECURITY_FILE_CAPABILITIES is not set
875# 997CONFIG_XOR_BLOCKS=m
876# Cryptographic options 998CONFIG_ASYNC_CORE=m
877# 999CONFIG_ASYNC_MEMCPY=m
1000CONFIG_ASYNC_XOR=m
878CONFIG_CRYPTO=y 1001CONFIG_CRYPTO=y
1002CONFIG_CRYPTO_ALGAPI=y
1003CONFIG_CRYPTO_AEAD=m
1004CONFIG_CRYPTO_BLKCIPHER=m
1005CONFIG_CRYPTO_SEQIV=m
1006CONFIG_CRYPTO_HASH=y
1007CONFIG_CRYPTO_MANAGER=y
879CONFIG_CRYPTO_HMAC=y 1008CONFIG_CRYPTO_HMAC=y
1009CONFIG_CRYPTO_XCBC=m
880CONFIG_CRYPTO_NULL=m 1010CONFIG_CRYPTO_NULL=m
881CONFIG_CRYPTO_MD4=m 1011CONFIG_CRYPTO_MD4=m
882CONFIG_CRYPTO_MD5=m 1012CONFIG_CRYPTO_MD5=m
@@ -885,9 +1015,21 @@ CONFIG_CRYPTO_SHA256=m
885CONFIG_CRYPTO_SHA512=m 1015CONFIG_CRYPTO_SHA512=m
886CONFIG_CRYPTO_WP512=m 1016CONFIG_CRYPTO_WP512=m
887CONFIG_CRYPTO_TGR192=m 1017CONFIG_CRYPTO_TGR192=m
1018CONFIG_CRYPTO_GF128MUL=m
1019CONFIG_CRYPTO_ECB=m
1020CONFIG_CRYPTO_CBC=m
1021CONFIG_CRYPTO_PCBC=m
1022CONFIG_CRYPTO_LRW=m
1023CONFIG_CRYPTO_XTS=m
1024CONFIG_CRYPTO_CTR=m
1025CONFIG_CRYPTO_GCM=m
1026CONFIG_CRYPTO_CCM=m
1027CONFIG_CRYPTO_CRYPTD=m
888CONFIG_CRYPTO_DES=m 1028CONFIG_CRYPTO_DES=m
1029CONFIG_CRYPTO_FCRYPT=m
889CONFIG_CRYPTO_BLOWFISH=m 1030CONFIG_CRYPTO_BLOWFISH=m
890CONFIG_CRYPTO_TWOFISH=m 1031CONFIG_CRYPTO_TWOFISH=m
1032CONFIG_CRYPTO_TWOFISH_COMMON=m
891CONFIG_CRYPTO_SERPENT=m 1033CONFIG_CRYPTO_SERPENT=m
892CONFIG_CRYPTO_AES=m 1034CONFIG_CRYPTO_AES=m
893CONFIG_CRYPTO_CAST5=m 1035CONFIG_CRYPTO_CAST5=m
@@ -896,20 +1038,35 @@ CONFIG_CRYPTO_TEA=m
896CONFIG_CRYPTO_ARC4=m 1038CONFIG_CRYPTO_ARC4=m
897CONFIG_CRYPTO_KHAZAD=m 1039CONFIG_CRYPTO_KHAZAD=m
898CONFIG_CRYPTO_ANUBIS=m 1040CONFIG_CRYPTO_ANUBIS=m
1041CONFIG_CRYPTO_SEED=m
1042CONFIG_CRYPTO_SALSA20=m
899CONFIG_CRYPTO_DEFLATE=m 1043CONFIG_CRYPTO_DEFLATE=m
900CONFIG_CRYPTO_MICHAEL_MIC=m 1044CONFIG_CRYPTO_MICHAEL_MIC=m
901CONFIG_CRYPTO_CRC32C=m 1045CONFIG_CRYPTO_CRC32C=m
1046CONFIG_CRYPTO_CAMELLIA=m
902CONFIG_CRYPTO_TEST=m 1047CONFIG_CRYPTO_TEST=m
903 1048CONFIG_CRYPTO_AUTHENC=m
904# 1049CONFIG_CRYPTO_LZO=m
905# Hardware crypto devices 1050# CONFIG_CRYPTO_HW is not set
906#
907 1051
908# 1052#
909# Library routines 1053# Library routines
910# 1054#
1055CONFIG_BITREVERSE=y
911CONFIG_CRC_CCITT=m 1056CONFIG_CRC_CCITT=m
1057CONFIG_CRC16=y
1058# CONFIG_CRC_ITU_T is not set
912CONFIG_CRC32=y 1059CONFIG_CRC32=y
1060# CONFIG_CRC7 is not set
913CONFIG_LIBCRC32C=m 1061CONFIG_LIBCRC32C=m
914CONFIG_ZLIB_INFLATE=y 1062CONFIG_ZLIB_INFLATE=y
915CONFIG_ZLIB_DEFLATE=m 1063CONFIG_ZLIB_DEFLATE=m
1064CONFIG_LZO_COMPRESS=m
1065CONFIG_LZO_DECOMPRESS=m
1066CONFIG_TEXTSEARCH=y
1067CONFIG_TEXTSEARCH_KMP=m
1068CONFIG_TEXTSEARCH_BM=m
1069CONFIG_TEXTSEARCH_FSM=m
1070CONFIG_PLIST=y
1071CONFIG_HAS_IOMEM=y
1072CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index da2a23a2146..ed98eff708c 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:37 2005 4# Wed Apr 2 20:46:10 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-bvme6000" 27CONFIG_LOCALVERSION="-bvme6000"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68060=y
85CONFIG_MMU_MOTOROLA=y 133CONFIG_MMU_MOTOROLA=y
86# CONFIG_M68KFPU_EMU is not set 134# CONFIG_M68KFPU_EMU is not set
87# CONFIG_ADVANCED is not set 135# CONFIG_ADVANCED is not set
136CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
137CONFIG_NODES_SHIFT=3
138CONFIG_SELECT_MEMORY_MODEL=y
139# CONFIG_FLATMEM_MANUAL is not set
140CONFIG_DISCONTIGMEM_MANUAL=y
141# CONFIG_SPARSEMEM_MANUAL is not set
142CONFIG_DISCONTIGMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y
144CONFIG_NEED_MULTIPLE_NODES=y
145# CONFIG_SPARSEMEM_STATIC is not set
146# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
147CONFIG_SPLIT_PTLOCK_CPUS=4
148# CONFIG_RESOURCES_64BIT is not set
149CONFIG_ZONE_DMA_FLAG=1
150CONFIG_BOUNCE=y
151CONFIG_VIRT_TO_BUS=y
88 152
89# 153#
90# General setup 154# General setup
@@ -93,134 +157,11 @@ CONFIG_BINFMT_ELF=y
93CONFIG_BINFMT_AOUT=m 157CONFIG_BINFMT_AOUT=m
94CONFIG_BINFMT_MISC=m 158CONFIG_BINFMT_MISC=m
95CONFIG_PROC_HARDWARE=y 159CONFIG_PROC_HARDWARE=y
160CONFIG_ZONE_DMA=y
161# CONFIG_ARCH_SUPPORTS_MSI is not set
96 162
97# 163#
98# Device Drivers 164# Networking
99#
100
101#
102# Generic Driver Options
103#
104CONFIG_STANDALONE=y
105CONFIG_PREVENT_FIRMWARE_BUILD=y
106CONFIG_FW_LOADER=m
107# CONFIG_DEBUG_DRIVER is not set
108
109#
110# Memory Technology Devices (MTD)
111#
112# CONFIG_MTD is not set
113
114#
115# Parallel port support
116#
117# CONFIG_PARPORT is not set
118
119#
120# Plug and Play support
121#
122
123#
124# Block devices
125#
126# CONFIG_BLK_DEV_COW_COMMON is not set
127CONFIG_BLK_DEV_LOOP=y
128CONFIG_BLK_DEV_CRYPTOLOOP=m
129CONFIG_BLK_DEV_NBD=m
130CONFIG_BLK_DEV_RAM=y
131CONFIG_BLK_DEV_RAM_COUNT=16
132CONFIG_BLK_DEV_RAM_SIZE=4096
133CONFIG_BLK_DEV_INITRD=y
134CONFIG_INITRAMFS_SOURCE=""
135CONFIG_CDROM_PKTCDVD=m
136CONFIG_CDROM_PKTCDVD_BUFFERS=8
137# CONFIG_CDROM_PKTCDVD_WCACHE is not set
138
139#
140# IO Schedulers
141#
142CONFIG_IOSCHED_NOOP=y
143CONFIG_IOSCHED_AS=y
144CONFIG_IOSCHED_DEADLINE=y
145CONFIG_IOSCHED_CFQ=y
146CONFIG_ATA_OVER_ETH=m
147
148#
149# ATA/ATAPI/MFM/RLL support
150#
151# CONFIG_IDE is not set
152
153#
154# SCSI device support
155#
156CONFIG_SCSI=y
157CONFIG_SCSI_PROC_FS=y
158
159#
160# SCSI support type (disk, tape, CD-ROM)
161#
162CONFIG_BLK_DEV_SD=y
163CONFIG_CHR_DEV_ST=m
164# CONFIG_CHR_DEV_OSST is not set
165CONFIG_BLK_DEV_SR=y
166CONFIG_BLK_DEV_SR_VENDOR=y
167CONFIG_CHR_DEV_SG=m
168
169#
170# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
171#
172# CONFIG_SCSI_MULTI_LUN is not set
173CONFIG_SCSI_CONSTANTS=y
174# CONFIG_SCSI_LOGGING is not set
175
176#
177# SCSI Transport Attributes
178#
179# CONFIG_SCSI_SPI_ATTRS is not set
180# CONFIG_SCSI_FC_ATTRS is not set
181# CONFIG_SCSI_ISCSI_ATTRS is not set
182
183#
184# SCSI low-level drivers
185#
186# CONFIG_SCSI_SATA is not set
187# CONFIG_SCSI_DEBUG is not set
188
189#
190# Multi-device support (RAID and LVM)
191#
192CONFIG_MD=y
193CONFIG_BLK_DEV_MD=m
194CONFIG_MD_LINEAR=m
195CONFIG_MD_RAID0=m
196CONFIG_MD_RAID1=m
197# CONFIG_MD_RAID10 is not set
198CONFIG_MD_RAID5=m
199CONFIG_MD_RAID6=m
200CONFIG_MD_MULTIPATH=m
201# CONFIG_MD_FAULTY is not set
202CONFIG_BLK_DEV_DM=m
203CONFIG_DM_CRYPT=m
204CONFIG_DM_SNAPSHOT=m
205CONFIG_DM_MIRROR=m
206CONFIG_DM_ZERO=m
207CONFIG_DM_MULTIPATH=m
208CONFIG_DM_MULTIPATH_EMC=m
209
210#
211# Fusion MPT device support
212#
213
214#
215# IEEE 1394 (FireWire) support
216#
217
218#
219# I2O device support
220#
221
222#
223# Networking support
224# 165#
225CONFIG_NET=y 166CONFIG_NET=y
226 167
@@ -230,10 +171,17 @@ CONFIG_NET=y
230CONFIG_PACKET=y 171CONFIG_PACKET=y
231# CONFIG_PACKET_MMAP is not set 172# CONFIG_PACKET_MMAP is not set
232CONFIG_UNIX=y 173CONFIG_UNIX=y
174CONFIG_XFRM=y
175# CONFIG_XFRM_USER is not set
176# CONFIG_XFRM_SUB_POLICY is not set
177CONFIG_XFRM_MIGRATE=y
178# CONFIG_XFRM_STATISTICS is not set
233CONFIG_NET_KEY=y 179CONFIG_NET_KEY=y
180CONFIG_NET_KEY_MIGRATE=y
234CONFIG_INET=y 181CONFIG_INET=y
235# CONFIG_IP_MULTICAST is not set 182# CONFIG_IP_MULTICAST is not set
236# CONFIG_IP_ADVANCED_ROUTER is not set 183# CONFIG_IP_ADVANCED_ROUTER is not set
184CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y 185CONFIG_IP_PNP=y
238CONFIG_IP_PNP_DHCP=y 186CONFIG_IP_PNP_DHCP=y
239CONFIG_IP_PNP_BOOTP=y 187CONFIG_IP_PNP_BOOTP=y
@@ -245,126 +193,186 @@ CONFIG_SYN_COOKIES=y
245CONFIG_INET_AH=m 193CONFIG_INET_AH=m
246CONFIG_INET_ESP=m 194CONFIG_INET_ESP=m
247CONFIG_INET_IPCOMP=m 195CONFIG_INET_IPCOMP=m
196CONFIG_INET_XFRM_TUNNEL=m
248CONFIG_INET_TUNNEL=m 197CONFIG_INET_TUNNEL=m
249CONFIG_IP_TCPDIAG=m 198CONFIG_INET_XFRM_MODE_TRANSPORT=m
250CONFIG_IP_TCPDIAG_IPV6=y 199CONFIG_INET_XFRM_MODE_TUNNEL=m
251 200CONFIG_INET_XFRM_MODE_BEET=m
252# 201CONFIG_INET_LRO=m
253# IP: Virtual Server Configuration 202CONFIG_INET_DIAG=m
254# 203CONFIG_INET_TCP_DIAG=m
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_CUBIC=y
206CONFIG_DEFAULT_TCP_CONG="cubic"
207# CONFIG_TCP_MD5SIG is not set
255# CONFIG_IP_VS is not set 208# CONFIG_IP_VS is not set
256CONFIG_IPV6=m 209CONFIG_IPV6=m
257CONFIG_IPV6_PRIVACY=y 210CONFIG_IPV6_PRIVACY=y
211CONFIG_IPV6_ROUTER_PREF=y
212CONFIG_IPV6_ROUTE_INFO=y
213# CONFIG_IPV6_OPTIMISTIC_DAD is not set
258CONFIG_INET6_AH=m 214CONFIG_INET6_AH=m
259CONFIG_INET6_ESP=m 215CONFIG_INET6_ESP=m
260CONFIG_INET6_IPCOMP=m 216CONFIG_INET6_IPCOMP=m
217# CONFIG_IPV6_MIP6 is not set
218CONFIG_INET6_XFRM_TUNNEL=m
261CONFIG_INET6_TUNNEL=m 219CONFIG_INET6_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_TRANSPORT=m
221CONFIG_INET6_XFRM_MODE_TUNNEL=m
222CONFIG_INET6_XFRM_MODE_BEET=m
223CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
224CONFIG_IPV6_SIT=m
262CONFIG_IPV6_TUNNEL=m 225CONFIG_IPV6_TUNNEL=m
226# CONFIG_IPV6_MULTIPLE_TABLES is not set
227# CONFIG_NETWORK_SECMARK is not set
263CONFIG_NETFILTER=y 228CONFIG_NETFILTER=y
264# CONFIG_NETFILTER_DEBUG is not set 229# CONFIG_NETFILTER_DEBUG is not set
230CONFIG_NETFILTER_ADVANCED=y
231
232#
233# Core Netfilter Configuration
234#
235CONFIG_NETFILTER_NETLINK=m
236CONFIG_NETFILTER_NETLINK_QUEUE=m
237CONFIG_NETFILTER_NETLINK_LOG=m
238CONFIG_NF_CONNTRACK=m
239CONFIG_NF_CT_ACCT=y
240CONFIG_NF_CONNTRACK_MARK=y
241# CONFIG_NF_CONNTRACK_EVENTS is not set
242CONFIG_NF_CT_PROTO_GRE=m
243CONFIG_NF_CT_PROTO_SCTP=m
244CONFIG_NF_CT_PROTO_UDPLITE=m
245CONFIG_NF_CONNTRACK_AMANDA=m
246CONFIG_NF_CONNTRACK_FTP=m
247CONFIG_NF_CONNTRACK_H323=m
248CONFIG_NF_CONNTRACK_IRC=m
249CONFIG_NF_CONNTRACK_NETBIOS_NS=m
250CONFIG_NF_CONNTRACK_PPTP=m
251CONFIG_NF_CONNTRACK_SANE=m
252CONFIG_NF_CONNTRACK_SIP=m
253CONFIG_NF_CONNTRACK_TFTP=m
254# CONFIG_NF_CT_NETLINK is not set
255CONFIG_NETFILTER_XTABLES=m
256CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
257CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
258CONFIG_NETFILTER_XT_TARGET_DSCP=m
259CONFIG_NETFILTER_XT_TARGET_MARK=m
260CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
261CONFIG_NETFILTER_XT_TARGET_NFLOG=m
262CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
263CONFIG_NETFILTER_XT_TARGET_RATEEST=m
264CONFIG_NETFILTER_XT_TARGET_TRACE=m
265CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
266CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
267CONFIG_NETFILTER_XT_MATCH_COMMENT=m
268CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
269CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
270CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
271CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
272CONFIG_NETFILTER_XT_MATCH_DCCP=m
273CONFIG_NETFILTER_XT_MATCH_DSCP=m
274CONFIG_NETFILTER_XT_MATCH_ESP=m
275CONFIG_NETFILTER_XT_MATCH_HELPER=m
276CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
277CONFIG_NETFILTER_XT_MATCH_LENGTH=m
278CONFIG_NETFILTER_XT_MATCH_LIMIT=m
279CONFIG_NETFILTER_XT_MATCH_MAC=m
280CONFIG_NETFILTER_XT_MATCH_MARK=m
281CONFIG_NETFILTER_XT_MATCH_OWNER=m
282CONFIG_NETFILTER_XT_MATCH_POLICY=m
283CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
284CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
285CONFIG_NETFILTER_XT_MATCH_QUOTA=m
286CONFIG_NETFILTER_XT_MATCH_RATEEST=m
287CONFIG_NETFILTER_XT_MATCH_REALM=m
288CONFIG_NETFILTER_XT_MATCH_SCTP=m
289CONFIG_NETFILTER_XT_MATCH_STATE=m
290CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
291CONFIG_NETFILTER_XT_MATCH_STRING=m
292CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
293CONFIG_NETFILTER_XT_MATCH_TIME=m
294CONFIG_NETFILTER_XT_MATCH_U32=m
295CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
265 296
266# 297#
267# IP: Netfilter Configuration 298# IP: Netfilter Configuration
268# 299#
269CONFIG_IP_NF_CONNTRACK=m 300CONFIG_NF_CONNTRACK_IPV4=m
270# CONFIG_IP_NF_CT_ACCT is not set 301CONFIG_NF_CONNTRACK_PROC_COMPAT=y
271CONFIG_IP_NF_CONNTRACK_MARK=y
272# CONFIG_IP_NF_CT_PROTO_SCTP is not set
273CONFIG_IP_NF_FTP=m
274CONFIG_IP_NF_IRC=m
275CONFIG_IP_NF_TFTP=m
276CONFIG_IP_NF_AMANDA=m
277CONFIG_IP_NF_QUEUE=m 302CONFIG_IP_NF_QUEUE=m
278CONFIG_IP_NF_IPTABLES=m 303CONFIG_IP_NF_IPTABLES=m
279CONFIG_IP_NF_MATCH_LIMIT=m
280CONFIG_IP_NF_MATCH_IPRANGE=m
281CONFIG_IP_NF_MATCH_MAC=m
282CONFIG_IP_NF_MATCH_PKTTYPE=m
283CONFIG_IP_NF_MATCH_MARK=m
284CONFIG_IP_NF_MATCH_MULTIPORT=m
285CONFIG_IP_NF_MATCH_TOS=m
286CONFIG_IP_NF_MATCH_RECENT=m 304CONFIG_IP_NF_MATCH_RECENT=m
287CONFIG_IP_NF_MATCH_ECN=m 305CONFIG_IP_NF_MATCH_ECN=m
288CONFIG_IP_NF_MATCH_DSCP=m 306CONFIG_IP_NF_MATCH_AH=m
289CONFIG_IP_NF_MATCH_AH_ESP=m
290CONFIG_IP_NF_MATCH_LENGTH=m
291CONFIG_IP_NF_MATCH_TTL=m 307CONFIG_IP_NF_MATCH_TTL=m
292CONFIG_IP_NF_MATCH_TCPMSS=m
293CONFIG_IP_NF_MATCH_HELPER=m
294CONFIG_IP_NF_MATCH_STATE=m
295CONFIG_IP_NF_MATCH_CONNTRACK=m
296CONFIG_IP_NF_MATCH_OWNER=m
297CONFIG_IP_NF_MATCH_ADDRTYPE=m 308CONFIG_IP_NF_MATCH_ADDRTYPE=m
298CONFIG_IP_NF_MATCH_REALM=m
299# CONFIG_IP_NF_MATCH_SCTP is not set
300# CONFIG_IP_NF_MATCH_COMMENT is not set
301CONFIG_IP_NF_MATCH_CONNMARK=m
302CONFIG_IP_NF_MATCH_HASHLIMIT=m
303CONFIG_IP_NF_FILTER=m 309CONFIG_IP_NF_FILTER=m
304CONFIG_IP_NF_TARGET_REJECT=m 310CONFIG_IP_NF_TARGET_REJECT=m
305CONFIG_IP_NF_TARGET_LOG=m 311CONFIG_IP_NF_TARGET_LOG=m
306CONFIG_IP_NF_TARGET_ULOG=m 312CONFIG_IP_NF_TARGET_ULOG=m
307CONFIG_IP_NF_TARGET_TCPMSS=m 313CONFIG_NF_NAT=m
308CONFIG_IP_NF_NAT=m 314CONFIG_NF_NAT_NEEDED=y
309CONFIG_IP_NF_NAT_NEEDED=y
310CONFIG_IP_NF_TARGET_MASQUERADE=m 315CONFIG_IP_NF_TARGET_MASQUERADE=m
311CONFIG_IP_NF_TARGET_REDIRECT=m 316CONFIG_IP_NF_TARGET_REDIRECT=m
312CONFIG_IP_NF_TARGET_NETMAP=m 317CONFIG_IP_NF_TARGET_NETMAP=m
313CONFIG_IP_NF_TARGET_SAME=m 318CONFIG_NF_NAT_SNMP_BASIC=m
314CONFIG_IP_NF_NAT_SNMP_BASIC=m 319CONFIG_NF_NAT_PROTO_GRE=m
315CONFIG_IP_NF_NAT_IRC=m 320CONFIG_NF_NAT_FTP=m
316CONFIG_IP_NF_NAT_FTP=m 321CONFIG_NF_NAT_IRC=m
317CONFIG_IP_NF_NAT_TFTP=m 322CONFIG_NF_NAT_TFTP=m
318CONFIG_IP_NF_NAT_AMANDA=m 323CONFIG_NF_NAT_AMANDA=m
324CONFIG_NF_NAT_PPTP=m
325CONFIG_NF_NAT_H323=m
326CONFIG_NF_NAT_SIP=m
319CONFIG_IP_NF_MANGLE=m 327CONFIG_IP_NF_MANGLE=m
320CONFIG_IP_NF_TARGET_TOS=m
321CONFIG_IP_NF_TARGET_ECN=m 328CONFIG_IP_NF_TARGET_ECN=m
322CONFIG_IP_NF_TARGET_DSCP=m 329CONFIG_IP_NF_TARGET_TTL=m
323CONFIG_IP_NF_TARGET_MARK=m 330CONFIG_IP_NF_TARGET_CLUSTERIP=m
324CONFIG_IP_NF_TARGET_CLASSIFY=m
325CONFIG_IP_NF_TARGET_CONNMARK=m
326# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
327CONFIG_IP_NF_RAW=m 331CONFIG_IP_NF_RAW=m
328CONFIG_IP_NF_TARGET_NOTRACK=m
329CONFIG_IP_NF_ARPTABLES=m 332CONFIG_IP_NF_ARPTABLES=m
330CONFIG_IP_NF_ARPFILTER=m 333CONFIG_IP_NF_ARPFILTER=m
331CONFIG_IP_NF_ARP_MANGLE=m 334CONFIG_IP_NF_ARP_MANGLE=m
332 335
333# 336#
334# IPv6: Netfilter Configuration (EXPERIMENTAL) 337# IPv6: Netfilter Configuration
335# 338#
339CONFIG_NF_CONNTRACK_IPV6=m
336CONFIG_IP6_NF_QUEUE=m 340CONFIG_IP6_NF_QUEUE=m
337CONFIG_IP6_NF_IPTABLES=m 341CONFIG_IP6_NF_IPTABLES=m
338CONFIG_IP6_NF_MATCH_LIMIT=m
339CONFIG_IP6_NF_MATCH_MAC=m
340CONFIG_IP6_NF_MATCH_RT=m 342CONFIG_IP6_NF_MATCH_RT=m
341CONFIG_IP6_NF_MATCH_OPTS=m 343CONFIG_IP6_NF_MATCH_OPTS=m
342CONFIG_IP6_NF_MATCH_FRAG=m 344CONFIG_IP6_NF_MATCH_FRAG=m
343CONFIG_IP6_NF_MATCH_HL=m 345CONFIG_IP6_NF_MATCH_HL=m
344CONFIG_IP6_NF_MATCH_MULTIPORT=m
345CONFIG_IP6_NF_MATCH_OWNER=m
346CONFIG_IP6_NF_MATCH_MARK=m
347CONFIG_IP6_NF_MATCH_IPV6HEADER=m 346CONFIG_IP6_NF_MATCH_IPV6HEADER=m
348CONFIG_IP6_NF_MATCH_AHESP=m 347CONFIG_IP6_NF_MATCH_AH=m
349CONFIG_IP6_NF_MATCH_LENGTH=m 348CONFIG_IP6_NF_MATCH_MH=m
350CONFIG_IP6_NF_MATCH_EUI64=m 349CONFIG_IP6_NF_MATCH_EUI64=m
351CONFIG_IP6_NF_FILTER=m 350CONFIG_IP6_NF_FILTER=m
352CONFIG_IP6_NF_TARGET_LOG=m 351CONFIG_IP6_NF_TARGET_LOG=m
352CONFIG_IP6_NF_TARGET_REJECT=m
353CONFIG_IP6_NF_MANGLE=m 353CONFIG_IP6_NF_MANGLE=m
354CONFIG_IP6_NF_TARGET_MARK=m 354CONFIG_IP6_NF_TARGET_HL=m
355CONFIG_IP6_NF_RAW=m 355CONFIG_IP6_NF_RAW=m
356CONFIG_XFRM=y 356CONFIG_IP_DCCP=m
357CONFIG_XFRM_USER=m 357CONFIG_INET_DCCP_DIAG=m
358CONFIG_IP_DCCP_ACKVEC=y
358 359
359# 360#
360# SCTP Configuration (EXPERIMENTAL) 361# DCCP CCIDs Configuration (EXPERIMENTAL)
361# 362#
363CONFIG_IP_DCCP_CCID2=m
364# CONFIG_IP_DCCP_CCID2_DEBUG is not set
365CONFIG_IP_DCCP_CCID3=m
366# CONFIG_IP_DCCP_CCID3_DEBUG is not set
367CONFIG_IP_DCCP_CCID3_RTO=100
368CONFIG_IP_DCCP_TFRC_LIB=m
362CONFIG_IP_SCTP=m 369CONFIG_IP_SCTP=m
363# CONFIG_SCTP_DBG_MSG is not set 370# CONFIG_SCTP_DBG_MSG is not set
364# CONFIG_SCTP_DBG_OBJCNT is not set 371# CONFIG_SCTP_DBG_OBJCNT is not set
365# CONFIG_SCTP_HMAC_NONE is not set 372# CONFIG_SCTP_HMAC_NONE is not set
366# CONFIG_SCTP_HMAC_SHA1 is not set 373# CONFIG_SCTP_HMAC_SHA1 is not set
367CONFIG_SCTP_HMAC_MD5=y 374CONFIG_SCTP_HMAC_MD5=y
375# CONFIG_TIPC is not set
368# CONFIG_ATM is not set 376# CONFIG_ATM is not set
369# CONFIG_BRIDGE is not set 377# CONFIG_BRIDGE is not set
370# CONFIG_VLAN_8021Q is not set 378# CONFIG_VLAN_8021Q is not set
@@ -376,13 +384,8 @@ CONFIG_ATALK=m
376# CONFIG_DEV_APPLETALK is not set 384# CONFIG_DEV_APPLETALK is not set
377# CONFIG_X25 is not set 385# CONFIG_X25 is not set
378# CONFIG_LAPB is not set 386# CONFIG_LAPB is not set
379# CONFIG_NET_DIVERT is not set
380# CONFIG_ECONET is not set 387# CONFIG_ECONET is not set
381# CONFIG_WAN_ROUTER is not set 388# CONFIG_WAN_ROUTER is not set
382
383#
384# QoS and/or fair queueing
385#
386# CONFIG_NET_SCHED is not set 389# CONFIG_NET_SCHED is not set
387CONFIG_NET_CLS_ROUTE=y 390CONFIG_NET_CLS_ROUTE=y
388 391
@@ -390,76 +393,186 @@ CONFIG_NET_CLS_ROUTE=y
390# Network testing 393# Network testing
391# 394#
392# CONFIG_NET_PKTGEN is not set 395# CONFIG_NET_PKTGEN is not set
393CONFIG_NETPOLL=y
394# CONFIG_NETPOLL_RX is not set
395# CONFIG_NETPOLL_TRAP is not set
396CONFIG_NET_POLL_CONTROLLER=y
397# CONFIG_HAMRADIO is not set 396# CONFIG_HAMRADIO is not set
397# CONFIG_CAN is not set
398# CONFIG_IRDA is not set 398# CONFIG_IRDA is not set
399# CONFIG_BT is not set 399# CONFIG_BT is not set
400CONFIG_NETDEVICES=y 400# CONFIG_AF_RXRPC is not set
401CONFIG_DUMMY=m
402# CONFIG_BONDING is not set
403CONFIG_EQUALIZER=m
404# CONFIG_TUN is not set
405 401
406# 402#
407# Ethernet (10 or 100Mbit) 403# Wireless
408# 404#
409CONFIG_NET_ETHERNET=y 405# CONFIG_CFG80211 is not set
410CONFIG_MII=m 406CONFIG_WIRELESS_EXT=y
411CONFIG_BVME6000_NET=y 407# CONFIG_MAC80211 is not set
408CONFIG_IEEE80211=m
409# CONFIG_IEEE80211_DEBUG is not set
410CONFIG_IEEE80211_CRYPT_WEP=m
411CONFIG_IEEE80211_CRYPT_CCMP=m
412CONFIG_IEEE80211_CRYPT_TKIP=m
413CONFIG_IEEE80211_SOFTMAC=m
414# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
415# CONFIG_RFKILL is not set
416# CONFIG_NET_9P is not set
412 417
413# 418#
414# Ethernet (1000 Mbit) 419# Device Drivers
415# 420#
416 421
417# 422#
418# Ethernet (10000 Mbit) 423# Generic Driver Options
419# 424#
425CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430CONFIG_CONNECTOR=m
431# CONFIG_MTD is not set
432# CONFIG_PARPORT is not set
433CONFIG_BLK_DEV=y
434# CONFIG_BLK_DEV_COW_COMMON is not set
435CONFIG_BLK_DEV_LOOP=y
436CONFIG_BLK_DEV_CRYPTOLOOP=m
437CONFIG_BLK_DEV_NBD=m
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=16
440CONFIG_BLK_DEV_RAM_SIZE=4096
441# CONFIG_BLK_DEV_XIP is not set
442CONFIG_CDROM_PKTCDVD=m
443CONFIG_CDROM_PKTCDVD_BUFFERS=8
444# CONFIG_CDROM_PKTCDVD_WCACHE is not set
445CONFIG_ATA_OVER_ETH=m
446CONFIG_MISC_DEVICES=y
447# CONFIG_EEPROM_93CX6 is not set
448# CONFIG_ENCLOSURE_SERVICES is not set
449CONFIG_HAVE_IDE=y
450# CONFIG_IDE is not set
420 451
421# 452#
422# Token Ring devices 453# SCSI device support
423# 454#
455CONFIG_RAID_ATTRS=m
456CONFIG_SCSI=y
457CONFIG_SCSI_DMA=y
458CONFIG_SCSI_TGT=m
459# CONFIG_SCSI_NETLINK is not set
460CONFIG_SCSI_PROC_FS=y
424 461
425# 462#
426# Wireless LAN (non-hamradio) 463# SCSI support type (disk, tape, CD-ROM)
427# 464#
428# CONFIG_NET_RADIO is not set 465CONFIG_BLK_DEV_SD=y
466CONFIG_CHR_DEV_ST=m
467CONFIG_CHR_DEV_OSST=m
468CONFIG_BLK_DEV_SR=y
469CONFIG_BLK_DEV_SR_VENDOR=y
470CONFIG_CHR_DEV_SG=m
471# CONFIG_CHR_DEV_SCH is not set
472
473#
474# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
475#
476# CONFIG_SCSI_MULTI_LUN is not set
477CONFIG_SCSI_CONSTANTS=y
478# CONFIG_SCSI_LOGGING is not set
479# CONFIG_SCSI_SCAN_ASYNC is not set
480CONFIG_SCSI_WAIT_SCAN=m
481
482#
483# SCSI Transports
484#
485CONFIG_SCSI_SPI_ATTRS=y
486# CONFIG_SCSI_FC_ATTRS is not set
487CONFIG_SCSI_ISCSI_ATTRS=m
488CONFIG_SCSI_SAS_ATTRS=m
489CONFIG_SCSI_SAS_LIBSAS=m
490CONFIG_SCSI_SAS_HOST_SMP=y
491# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
492CONFIG_SCSI_SRP_ATTRS=m
493CONFIG_SCSI_SRP_TGT_ATTRS=y
494CONFIG_SCSI_LOWLEVEL=y
495CONFIG_ISCSI_TCP=m
496CONFIG_53C700_BE_BUS=y
497# CONFIG_SCSI_DEBUG is not set
498CONFIG_BVME6000_SCSI=y
499CONFIG_MD=y
500CONFIG_BLK_DEV_MD=m
501CONFIG_MD_LINEAR=m
502CONFIG_MD_RAID0=m
503CONFIG_MD_RAID1=m
504# CONFIG_MD_RAID10 is not set
505CONFIG_MD_RAID456=m
506CONFIG_MD_RAID5_RESHAPE=y
507CONFIG_MD_MULTIPATH=m
508# CONFIG_MD_FAULTY is not set
509CONFIG_BLK_DEV_DM=m
510# CONFIG_DM_DEBUG is not set
511CONFIG_DM_CRYPT=m
512CONFIG_DM_SNAPSHOT=m
513CONFIG_DM_MIRROR=m
514CONFIG_DM_ZERO=m
515CONFIG_DM_MULTIPATH=m
516CONFIG_DM_MULTIPATH_EMC=m
517CONFIG_DM_MULTIPATH_RDAC=m
518CONFIG_DM_MULTIPATH_HP=m
519# CONFIG_DM_DELAY is not set
520CONFIG_DM_UEVENT=y
521CONFIG_NETDEVICES=y
522# CONFIG_NETDEVICES_MULTIQUEUE is not set
523CONFIG_DUMMY=m
524# CONFIG_BONDING is not set
525CONFIG_MACVLAN=m
526CONFIG_EQUALIZER=m
527# CONFIG_TUN is not set
528CONFIG_VETH=m
529# CONFIG_PHYLIB is not set
530CONFIG_NET_ETHERNET=y
531# CONFIG_MII is not set
532CONFIG_BVME6000_NET=y
533# CONFIG_IBM_NEW_EMAC_ZMII is not set
534# CONFIG_IBM_NEW_EMAC_RGMII is not set
535# CONFIG_IBM_NEW_EMAC_TAH is not set
536# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
537# CONFIG_B44 is not set
538# CONFIG_NETDEV_1000 is not set
539# CONFIG_NETDEV_10000 is not set
429 540
430# 541#
431# Wan interfaces 542# Wireless LAN
432# 543#
544# CONFIG_WLAN_PRE80211 is not set
545# CONFIG_WLAN_80211 is not set
433# CONFIG_WAN is not set 546# CONFIG_WAN is not set
434CONFIG_PPP=m 547CONFIG_PPP=m
435# CONFIG_PPP_MULTILINK is not set 548# CONFIG_PPP_MULTILINK is not set
436# CONFIG_PPP_FILTER is not set 549CONFIG_PPP_FILTER=y
437CONFIG_PPP_ASYNC=m 550CONFIG_PPP_ASYNC=m
438CONFIG_PPP_SYNC_TTY=m 551CONFIG_PPP_SYNC_TTY=m
439CONFIG_PPP_DEFLATE=m 552CONFIG_PPP_DEFLATE=m
440CONFIG_PPP_BSDCOMP=m 553CONFIG_PPP_BSDCOMP=m
554CONFIG_PPP_MPPE=m
441CONFIG_PPPOE=m 555CONFIG_PPPOE=m
556CONFIG_PPPOL2TP=m
442CONFIG_SLIP=m 557CONFIG_SLIP=m
443CONFIG_SLIP_COMPRESSED=y 558CONFIG_SLIP_COMPRESSED=y
559CONFIG_SLHC=m
444CONFIG_SLIP_SMART=y 560CONFIG_SLIP_SMART=y
445CONFIG_SLIP_MODE_SLIP6=y 561CONFIG_SLIP_MODE_SLIP6=y
446CONFIG_SHAPER=m
447CONFIG_NETCONSOLE=m 562CONFIG_NETCONSOLE=m
448 563CONFIG_NETCONSOLE_DYNAMIC=y
449# 564CONFIG_NETPOLL=y
450# ISDN subsystem 565# CONFIG_NETPOLL_TRAP is not set
451# 566CONFIG_NET_POLL_CONTROLLER=y
452# CONFIG_ISDN is not set 567# CONFIG_ISDN is not set
453
454#
455# Telephony Support
456#
457# CONFIG_PHONE is not set 568# CONFIG_PHONE is not set
458 569
459# 570#
460# Input device support 571# Input device support
461# 572#
462CONFIG_INPUT=y 573CONFIG_INPUT=y
574CONFIG_INPUT_FF_MEMLESS=m
575# CONFIG_INPUT_POLLDEV is not set
463 576
464# 577#
465# Userland interfaces 578# Userland interfaces
@@ -469,7 +582,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
469CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 582CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
470CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 583CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
471# CONFIG_INPUT_JOYDEV is not set 584# CONFIG_INPUT_JOYDEV is not set
472# CONFIG_INPUT_TSDEV is not set
473# CONFIG_INPUT_EVDEV is not set 585# CONFIG_INPUT_EVDEV is not set
474# CONFIG_INPUT_EVBUG is not set 586# CONFIG_INPUT_EVBUG is not set
475 587
@@ -482,11 +594,19 @@ CONFIG_INPUT_KEYBOARD=y
482# CONFIG_KEYBOARD_LKKBD is not set 594# CONFIG_KEYBOARD_LKKBD is not set
483# CONFIG_KEYBOARD_XTKBD is not set 595# CONFIG_KEYBOARD_XTKBD is not set
484# CONFIG_KEYBOARD_NEWTON is not set 596# CONFIG_KEYBOARD_NEWTON is not set
597# CONFIG_KEYBOARD_STOWAWAY is not set
485CONFIG_INPUT_MOUSE=y 598CONFIG_INPUT_MOUSE=y
486CONFIG_MOUSE_PS2=m 599CONFIG_MOUSE_PS2=m
600CONFIG_MOUSE_PS2_ALPS=y
601CONFIG_MOUSE_PS2_LOGIPS2PP=y
602CONFIG_MOUSE_PS2_SYNAPTICS=y
603CONFIG_MOUSE_PS2_LIFEBOOK=y
604CONFIG_MOUSE_PS2_TRACKPOINT=y
605# CONFIG_MOUSE_PS2_TOUCHKIT is not set
487CONFIG_MOUSE_SERIAL=m 606CONFIG_MOUSE_SERIAL=m
488# CONFIG_MOUSE_VSXXXAA is not set 607# CONFIG_MOUSE_VSXXXAA is not set
489# CONFIG_INPUT_JOYSTICK is not set 608# CONFIG_INPUT_JOYSTICK is not set
609# CONFIG_INPUT_TABLET is not set
490# CONFIG_INPUT_TOUCHSCREEN is not set 610# CONFIG_INPUT_TOUCHSCREEN is not set
491# CONFIG_INPUT_MISC is not set 611# CONFIG_INPUT_MISC is not set
492 612
@@ -494,7 +614,7 @@ CONFIG_MOUSE_SERIAL=m
494# Hardware I/O ports 614# Hardware I/O ports
495# 615#
496CONFIG_SERIO=m 616CONFIG_SERIO=m
497CONFIG_SERIO_SERPORT=m 617# CONFIG_SERIO_SERPORT is not set
498CONFIG_SERIO_LIBPS2=m 618CONFIG_SERIO_LIBPS2=m
499# CONFIG_SERIO_RAW is not set 619# CONFIG_SERIO_RAW is not set
500# CONFIG_GAMEPORT is not set 620# CONFIG_GAMEPORT is not set
@@ -505,6 +625,7 @@ CONFIG_SERIO_LIBPS2=m
505CONFIG_VT=y 625CONFIG_VT=y
506CONFIG_VT_CONSOLE=y 626CONFIG_VT_CONSOLE=y
507CONFIG_HW_CONSOLE=y 627CONFIG_HW_CONSOLE=y
628CONFIG_VT_HW_CONSOLE_BINDING=y
508# CONFIG_SERIAL_NONSTANDARD is not set 629# CONFIG_SERIAL_NONSTANDARD is not set
509 630
510# 631#
@@ -518,59 +639,56 @@ CONFIG_HW_CONSOLE=y
518CONFIG_UNIX98_PTYS=y 639CONFIG_UNIX98_PTYS=y
519CONFIG_LEGACY_PTYS=y 640CONFIG_LEGACY_PTYS=y
520CONFIG_LEGACY_PTY_COUNT=256 641CONFIG_LEGACY_PTY_COUNT=256
521
522#
523# IPMI
524#
525# CONFIG_IPMI_HANDLER is not set 642# CONFIG_IPMI_HANDLER is not set
526 643# CONFIG_HW_RANDOM is not set
527#
528# Watchdog Cards
529#
530# CONFIG_WATCHDOG is not set
531CONFIG_GEN_RTC=m 644CONFIG_GEN_RTC=m
532CONFIG_GEN_RTC_X=y 645CONFIG_GEN_RTC_X=y
533# CONFIG_DTLK is not set
534# CONFIG_R3964 is not set 646# CONFIG_R3964 is not set
535
536#
537# Ftape, the floppy tape device driver
538#
539# CONFIG_DRM is not set
540# CONFIG_RAW_DRIVER is not set 647# CONFIG_RAW_DRIVER is not set
648# CONFIG_TCG_TPM is not set
649# CONFIG_I2C is not set
541 650
542# 651#
543# TPM devices 652# SPI support
544#
545
546#
547# I2C support
548# 653#
549# CONFIG_I2C is not set 654# CONFIG_SPI is not set
655# CONFIG_SPI_MASTER is not set
656# CONFIG_W1 is not set
657# CONFIG_POWER_SUPPLY is not set
658# CONFIG_HWMON is not set
659# CONFIG_THERMAL is not set
660# CONFIG_WATCHDOG is not set
550 661
551# 662#
552# Dallas's 1-wire bus 663# Sonics Silicon Backplane
553# 664#
554# CONFIG_W1 is not set 665CONFIG_SSB_POSSIBLE=y
666# CONFIG_SSB is not set
555 667
556# 668#
557# Misc devices 669# Multifunction device drivers
558# 670#
671# CONFIG_MFD_SM501 is not set
559 672
560# 673#
561# Multimedia devices 674# Multimedia devices
562# 675#
563# CONFIG_VIDEO_DEV is not set 676# CONFIG_VIDEO_DEV is not set
677# CONFIG_DVB_CORE is not set
678# CONFIG_DAB is not set
564 679
565# 680#
566# Digital Video Broadcasting Devices 681# Graphics support
567# 682#
568# CONFIG_DVB is not set 683# CONFIG_VGASTATE is not set
684# CONFIG_VIDEO_OUTPUT_CONTROL is not set
685# CONFIG_FB is not set
686# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
569 687
570# 688#
571# Graphics support 689# Display device support
572# 690#
573# CONFIG_FB is not set 691# CONFIG_DISPLAY_SUPPORT is not set
574 692
575# 693#
576# Console display driver support 694# Console display driver support
@@ -581,27 +699,20 @@ CONFIG_DUMMY_CONSOLE=y
581# Sound 699# Sound
582# 700#
583# CONFIG_SOUND is not set 701# CONFIG_SOUND is not set
584 702CONFIG_HID_SUPPORT=y
585# 703CONFIG_HID=m
586# USB support 704# CONFIG_HID_DEBUG is not set
587# 705CONFIG_HIDRAW=y
588# CONFIG_USB_ARCH_HAS_HCD is not set 706# CONFIG_USB_SUPPORT is not set
589# CONFIG_USB_ARCH_HAS_OHCI is not set
590
591#
592# USB Gadget Support
593#
594# CONFIG_USB_GADGET is not set
595
596#
597# MMC/SD Card support
598#
599# CONFIG_MMC is not set 707# CONFIG_MMC is not set
708# CONFIG_MEMSTICK is not set
709# CONFIG_NEW_LEDS is not set
710# CONFIG_RTC_CLASS is not set
600 711
601# 712#
602# InfiniBand support 713# Userspace I/O
603# 714#
604# CONFIG_INFINIBAND is not set 715# CONFIG_UIO is not set
605 716
606# 717#
607# Character devices 718# Character devices
@@ -614,10 +725,11 @@ CONFIG_SERIAL_CONSOLE=y
614# 725#
615CONFIG_EXT2_FS=y 726CONFIG_EXT2_FS=y
616# CONFIG_EXT2_FS_XATTR is not set 727# CONFIG_EXT2_FS_XATTR is not set
728# CONFIG_EXT2_FS_XIP is not set
617CONFIG_EXT3_FS=y 729CONFIG_EXT3_FS=y
618# CONFIG_EXT3_FS_XATTR is not set 730# CONFIG_EXT3_FS_XATTR is not set
731# CONFIG_EXT4DEV_FS is not set
619CONFIG_JBD=y 732CONFIG_JBD=y
620# CONFIG_JBD_DEBUG is not set
621CONFIG_REISERFS_FS=m 733CONFIG_REISERFS_FS=m
622# CONFIG_REISERFS_CHECK is not set 734# CONFIG_REISERFS_CHECK is not set
623# CONFIG_REISERFS_PROC_INFO is not set 735# CONFIG_REISERFS_PROC_INFO is not set
@@ -628,25 +740,29 @@ CONFIG_JFS_FS=m
628# CONFIG_JFS_DEBUG is not set 740# CONFIG_JFS_DEBUG is not set
629# CONFIG_JFS_STATISTICS is not set 741# CONFIG_JFS_STATISTICS is not set
630CONFIG_FS_POSIX_ACL=y 742CONFIG_FS_POSIX_ACL=y
631
632#
633# XFS support
634#
635CONFIG_XFS_FS=m 743CONFIG_XFS_FS=m
636CONFIG_XFS_EXPORT=y
637# CONFIG_XFS_RT is not set
638# CONFIG_XFS_QUOTA is not set 744# CONFIG_XFS_QUOTA is not set
639# CONFIG_XFS_SECURITY is not set 745# CONFIG_XFS_SECURITY is not set
640# CONFIG_XFS_POSIX_ACL is not set 746# CONFIG_XFS_POSIX_ACL is not set
641CONFIG_MINIX_FS=y 747# CONFIG_XFS_RT is not set
642# CONFIG_ROMFS_FS is not set 748CONFIG_GFS2_FS=m
749CONFIG_GFS2_FS_LOCKING_NOLOCK=m
750CONFIG_GFS2_FS_LOCKING_DLM=m
751CONFIG_OCFS2_FS=m
752# CONFIG_OCFS2_DEBUG_MASKLOG is not set
753# CONFIG_OCFS2_DEBUG_FS is not set
754CONFIG_DNOTIFY=y
755CONFIG_INOTIFY=y
756CONFIG_INOTIFY_USER=y
643CONFIG_QUOTA=y 757CONFIG_QUOTA=y
758CONFIG_QUOTA_NETLINK_INTERFACE=y
759# CONFIG_PRINT_QUOTA_WARNING is not set
644# CONFIG_QFMT_V1 is not set 760# CONFIG_QFMT_V1 is not set
645# CONFIG_QFMT_V2 is not set 761# CONFIG_QFMT_V2 is not set
646CONFIG_QUOTACTL=y 762CONFIG_QUOTACTL=y
647CONFIG_DNOTIFY=y
648CONFIG_AUTOFS_FS=m 763CONFIG_AUTOFS_FS=m
649CONFIG_AUTOFS4_FS=m 764CONFIG_AUTOFS4_FS=m
765CONFIG_FUSE_FS=m
650 766
651# 767#
652# CD-ROM/DVD Filesystems 768# CD-ROM/DVD Filesystems
@@ -654,7 +770,6 @@ CONFIG_AUTOFS4_FS=m
654CONFIG_ISO9660_FS=y 770CONFIG_ISO9660_FS=y
655CONFIG_JOLIET=y 771CONFIG_JOLIET=y
656CONFIG_ZISOFS=y 772CONFIG_ZISOFS=y
657CONFIG_ZISOFS_FS=y
658CONFIG_UDF_FS=m 773CONFIG_UDF_FS=m
659CONFIG_UDF_NLS=y 774CONFIG_UDF_NLS=y
660 775
@@ -673,13 +788,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
673# 788#
674CONFIG_PROC_FS=y 789CONFIG_PROC_FS=y
675CONFIG_PROC_KCORE=y 790CONFIG_PROC_KCORE=y
791CONFIG_PROC_SYSCTL=y
676CONFIG_SYSFS=y 792CONFIG_SYSFS=y
677# CONFIG_DEVFS_FS is not set
678# CONFIG_DEVPTS_FS_XATTR is not set
679CONFIG_TMPFS=y 793CONFIG_TMPFS=y
680# CONFIG_TMPFS_XATTR is not set 794# CONFIG_TMPFS_POSIX_ACL is not set
681# CONFIG_HUGETLB_PAGE is not set 795# CONFIG_HUGETLB_PAGE is not set
682CONFIG_RAMFS=y 796CONFIG_CONFIGFS_FS=m
683 797
684# 798#
685# Miscellaneous filesystems 799# Miscellaneous filesystems
@@ -693,44 +807,40 @@ CONFIG_HFSPLUS_FS=m
693# CONFIG_EFS_FS is not set 807# CONFIG_EFS_FS is not set
694CONFIG_CRAMFS=m 808CONFIG_CRAMFS=m
695# CONFIG_VXFS_FS is not set 809# CONFIG_VXFS_FS is not set
810CONFIG_MINIX_FS=y
696CONFIG_HPFS_FS=m 811CONFIG_HPFS_FS=m
697# CONFIG_QNX4FS_FS is not set 812# CONFIG_QNX4FS_FS is not set
813# CONFIG_ROMFS_FS is not set
698CONFIG_SYSV_FS=m 814CONFIG_SYSV_FS=m
699CONFIG_UFS_FS=m 815CONFIG_UFS_FS=m
700# CONFIG_UFS_FS_WRITE is not set 816# CONFIG_UFS_FS_WRITE is not set
701 817# CONFIG_UFS_DEBUG is not set
702# 818CONFIG_NETWORK_FILESYSTEMS=y
703# Network File Systems
704#
705CONFIG_NFS_FS=y 819CONFIG_NFS_FS=y
706CONFIG_NFS_V3=y 820CONFIG_NFS_V3=y
821# CONFIG_NFS_V3_ACL is not set
707CONFIG_NFS_V4=y 822CONFIG_NFS_V4=y
708# CONFIG_NFS_DIRECTIO is not set 823# CONFIG_NFS_DIRECTIO is not set
709CONFIG_NFSD=m 824CONFIG_NFSD=m
710CONFIG_NFSD_V3=y 825CONFIG_NFSD_V3=y
711CONFIG_NFSD_V4=y 826# CONFIG_NFSD_V3_ACL is not set
827# CONFIG_NFSD_V4 is not set
712CONFIG_NFSD_TCP=y 828CONFIG_NFSD_TCP=y
713CONFIG_ROOT_NFS=y 829CONFIG_ROOT_NFS=y
714CONFIG_LOCKD=y 830CONFIG_LOCKD=y
715CONFIG_LOCKD_V4=y 831CONFIG_LOCKD_V4=y
716CONFIG_EXPORTFS=m 832CONFIG_EXPORTFS=m
833CONFIG_NFS_COMMON=y
717CONFIG_SUNRPC=y 834CONFIG_SUNRPC=y
718CONFIG_SUNRPC_GSS=y 835CONFIG_SUNRPC_GSS=y
836CONFIG_SUNRPC_BIND34=y
719CONFIG_RPCSEC_GSS_KRB5=y 837CONFIG_RPCSEC_GSS_KRB5=y
720# CONFIG_RPCSEC_GSS_SPKM3 is not set 838# CONFIG_RPCSEC_GSS_SPKM3 is not set
721CONFIG_SMB_FS=m 839CONFIG_SMB_FS=m
722CONFIG_SMB_NLS_DEFAULT=y 840CONFIG_SMB_NLS_DEFAULT=y
723CONFIG_SMB_NLS_REMOTE="cp437" 841CONFIG_SMB_NLS_REMOTE="cp437"
724# CONFIG_CIFS is not set 842# CONFIG_CIFS is not set
725CONFIG_NCP_FS=m 843# CONFIG_NCP_FS is not set
726# CONFIG_NCPFS_PACKET_SIGNING is not set
727# CONFIG_NCPFS_IOCTL_LOCKING is not set
728# CONFIG_NCPFS_STRONG is not set
729CONFIG_NCPFS_NFS_NS=y
730CONFIG_NCPFS_OS2_NS=y
731# CONFIG_NCPFS_SMALLDOS is not set
732CONFIG_NCPFS_NLS=y
733# CONFIG_NCPFS_EXTRAS is not set
734CONFIG_CODA_FS=m 844CONFIG_CODA_FS=m
735# CONFIG_CODA_FS_OLD_API is not set 845# CONFIG_CODA_FS_OLD_API is not set
736# CONFIG_AFS_FS is not set 846# CONFIG_AFS_FS is not set
@@ -740,10 +850,7 @@ CONFIG_CODA_FS=m
740# 850#
741# CONFIG_PARTITION_ADVANCED is not set 851# CONFIG_PARTITION_ADVANCED is not set
742CONFIG_MSDOS_PARTITION=y 852CONFIG_MSDOS_PARTITION=y
743 853CONFIG_SYSV68_PARTITION=y
744#
745# Native Language Support
746#
747CONFIG_NLS=y 854CONFIG_NLS=y
748CONFIG_NLS_DEFAULT="iso8859-1" 855CONFIG_NLS_DEFAULT="iso8859-1"
749CONFIG_NLS_CODEPAGE_437=y 856CONFIG_NLS_CODEPAGE_437=y
@@ -784,35 +891,42 @@ CONFIG_NLS_ISO8859_15=m
784CONFIG_NLS_KOI8_R=m 891CONFIG_NLS_KOI8_R=m
785CONFIG_NLS_KOI8_U=m 892CONFIG_NLS_KOI8_U=m
786CONFIG_NLS_UTF8=m 893CONFIG_NLS_UTF8=m
894CONFIG_DLM=m
895# CONFIG_DLM_DEBUG is not set
787 896
788# 897#
789# Kernel hacking 898# Kernel hacking
790# 899#
791# CONFIG_PRINTK_TIME is not set 900# CONFIG_PRINTK_TIME is not set
792CONFIG_DEBUG_KERNEL=y 901CONFIG_ENABLE_WARN_DEPRECATED=y
902CONFIG_ENABLE_MUST_CHECK=y
793CONFIG_MAGIC_SYSRQ=y 903CONFIG_MAGIC_SYSRQ=y
794CONFIG_LOG_BUF_SHIFT=16 904# CONFIG_UNUSED_SYMBOLS is not set
795# CONFIG_SCHEDSTATS is not set
796# CONFIG_DEBUG_SLAB is not set
797# CONFIG_DEBUG_SPINLOCK is not set
798# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
799# CONFIG_DEBUG_KOBJECT is not set
800CONFIG_DEBUG_BUGVERBOSE=y
801# CONFIG_DEBUG_INFO is not set
802# CONFIG_DEBUG_FS is not set 905# CONFIG_DEBUG_FS is not set
803# CONFIG_FRAME_POINTER is not set 906# CONFIG_HEADERS_CHECK is not set
907# CONFIG_DEBUG_KERNEL is not set
908CONFIG_DEBUG_BUGVERBOSE=y
909# CONFIG_SAMPLES is not set
804 910
805# 911#
806# Security options 912# Security options
807# 913#
808# CONFIG_KEYS is not set 914# CONFIG_KEYS is not set
809# CONFIG_SECURITY is not set 915# CONFIG_SECURITY is not set
810 916# CONFIG_SECURITY_FILE_CAPABILITIES is not set
811# 917CONFIG_XOR_BLOCKS=m
812# Cryptographic options 918CONFIG_ASYNC_CORE=m
813# 919CONFIG_ASYNC_MEMCPY=m
920CONFIG_ASYNC_XOR=m
814CONFIG_CRYPTO=y 921CONFIG_CRYPTO=y
922CONFIG_CRYPTO_ALGAPI=y
923CONFIG_CRYPTO_AEAD=m
924CONFIG_CRYPTO_BLKCIPHER=y
925CONFIG_CRYPTO_SEQIV=m
926CONFIG_CRYPTO_HASH=y
927CONFIG_CRYPTO_MANAGER=y
815CONFIG_CRYPTO_HMAC=y 928CONFIG_CRYPTO_HMAC=y
929CONFIG_CRYPTO_XCBC=m
816CONFIG_CRYPTO_NULL=m 930CONFIG_CRYPTO_NULL=m
817CONFIG_CRYPTO_MD4=m 931CONFIG_CRYPTO_MD4=m
818CONFIG_CRYPTO_MD5=y 932CONFIG_CRYPTO_MD5=y
@@ -821,9 +935,21 @@ CONFIG_CRYPTO_SHA256=m
821CONFIG_CRYPTO_SHA512=m 935CONFIG_CRYPTO_SHA512=m
822CONFIG_CRYPTO_WP512=m 936CONFIG_CRYPTO_WP512=m
823CONFIG_CRYPTO_TGR192=m 937CONFIG_CRYPTO_TGR192=m
938CONFIG_CRYPTO_GF128MUL=m
939CONFIG_CRYPTO_ECB=m
940CONFIG_CRYPTO_CBC=y
941CONFIG_CRYPTO_PCBC=m
942CONFIG_CRYPTO_LRW=m
943CONFIG_CRYPTO_XTS=m
944CONFIG_CRYPTO_CTR=m
945CONFIG_CRYPTO_GCM=m
946CONFIG_CRYPTO_CCM=m
947CONFIG_CRYPTO_CRYPTD=m
824CONFIG_CRYPTO_DES=y 948CONFIG_CRYPTO_DES=y
949CONFIG_CRYPTO_FCRYPT=m
825CONFIG_CRYPTO_BLOWFISH=m 950CONFIG_CRYPTO_BLOWFISH=m
826CONFIG_CRYPTO_TWOFISH=m 951CONFIG_CRYPTO_TWOFISH=m
952CONFIG_CRYPTO_TWOFISH_COMMON=m
827CONFIG_CRYPTO_SERPENT=m 953CONFIG_CRYPTO_SERPENT=m
828CONFIG_CRYPTO_AES=m 954CONFIG_CRYPTO_AES=m
829CONFIG_CRYPTO_CAST5=m 955CONFIG_CRYPTO_CAST5=m
@@ -832,20 +958,35 @@ CONFIG_CRYPTO_TEA=m
832CONFIG_CRYPTO_ARC4=m 958CONFIG_CRYPTO_ARC4=m
833CONFIG_CRYPTO_KHAZAD=m 959CONFIG_CRYPTO_KHAZAD=m
834CONFIG_CRYPTO_ANUBIS=m 960CONFIG_CRYPTO_ANUBIS=m
961CONFIG_CRYPTO_SEED=m
962CONFIG_CRYPTO_SALSA20=m
835CONFIG_CRYPTO_DEFLATE=m 963CONFIG_CRYPTO_DEFLATE=m
836CONFIG_CRYPTO_MICHAEL_MIC=m 964CONFIG_CRYPTO_MICHAEL_MIC=m
837CONFIG_CRYPTO_CRC32C=m 965CONFIG_CRYPTO_CRC32C=m
966CONFIG_CRYPTO_CAMELLIA=m
838CONFIG_CRYPTO_TEST=m 967CONFIG_CRYPTO_TEST=m
839 968CONFIG_CRYPTO_AUTHENC=m
840# 969CONFIG_CRYPTO_LZO=m
841# Hardware crypto devices 970# CONFIG_CRYPTO_HW is not set
842#
843 971
844# 972#
845# Library routines 973# Library routines
846# 974#
975CONFIG_BITREVERSE=m
847CONFIG_CRC_CCITT=m 976CONFIG_CRC_CCITT=m
977CONFIG_CRC16=m
978# CONFIG_CRC_ITU_T is not set
848CONFIG_CRC32=m 979CONFIG_CRC32=m
980# CONFIG_CRC7 is not set
849CONFIG_LIBCRC32C=m 981CONFIG_LIBCRC32C=m
850CONFIG_ZLIB_INFLATE=y 982CONFIG_ZLIB_INFLATE=y
851CONFIG_ZLIB_DEFLATE=m 983CONFIG_ZLIB_DEFLATE=m
984CONFIG_LZO_COMPRESS=m
985CONFIG_LZO_DECOMPRESS=m
986CONFIG_TEXTSEARCH=y
987CONFIG_TEXTSEARCH_KMP=m
988CONFIG_TEXTSEARCH_BM=m
989CONFIG_TEXTSEARCH_FSM=m
990CONFIG_PLIST=y
991CONFIG_HAS_IOMEM=y
992CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 51251883adf..38b68c70e56 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:41 2005 4# Wed Apr 2 20:46:12 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-hp300" 27CONFIG_LOCALVERSION="-hp300"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -81,10 +129,24 @@ CONFIG_M68030=y
81CONFIG_M68040=y 129CONFIG_M68040=y
82CONFIG_M68060=y 130CONFIG_M68060=y
83CONFIG_MMU_MOTOROLA=y 131CONFIG_MMU_MOTOROLA=y
84CONFIG_M68KFPU_EMU=y 132# CONFIG_M68KFPU_EMU is not set
85CONFIG_M68KFPU_EMU_EXTRAPREC=y
86# CONFIG_M68KFPU_EMU_ONLY is not set
87# CONFIG_ADVANCED is not set 133# CONFIG_ADVANCED is not set
134CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
135CONFIG_NODES_SHIFT=3
136CONFIG_SELECT_MEMORY_MODEL=y
137# CONFIG_FLATMEM_MANUAL is not set
138CONFIG_DISCONTIGMEM_MANUAL=y
139# CONFIG_SPARSEMEM_MANUAL is not set
140CONFIG_DISCONTIGMEM=y
141CONFIG_FLAT_NODE_MEM_MAP=y
142CONFIG_NEED_MULTIPLE_NODES=y
143# CONFIG_SPARSEMEM_STATIC is not set
144# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
145CONFIG_SPLIT_PTLOCK_CPUS=4
146# CONFIG_RESOURCES_64BIT is not set
147CONFIG_ZONE_DMA_FLAG=1
148CONFIG_BOUNCE=y
149CONFIG_VIRT_TO_BUS=y
88 150
89# 151#
90# General setup 152# General setup
@@ -94,134 +156,11 @@ CONFIG_BINFMT_AOUT=m
94CONFIG_BINFMT_MISC=m 156CONFIG_BINFMT_MISC=m
95CONFIG_HEARTBEAT=y 157CONFIG_HEARTBEAT=y
96CONFIG_PROC_HARDWARE=y 158CONFIG_PROC_HARDWARE=y
159CONFIG_ZONE_DMA=y
160# CONFIG_ARCH_SUPPORTS_MSI is not set
97 161
98# 162#
99# Device Drivers 163# Networking
100#
101
102#
103# Generic Driver Options
104#
105CONFIG_STANDALONE=y
106CONFIG_PREVENT_FIRMWARE_BUILD=y
107CONFIG_FW_LOADER=m
108# CONFIG_DEBUG_DRIVER is not set
109
110#
111# Memory Technology Devices (MTD)
112#
113# CONFIG_MTD is not set
114
115#
116# Parallel port support
117#
118# CONFIG_PARPORT is not set
119
120#
121# Plug and Play support
122#
123
124#
125# Block devices
126#
127# CONFIG_BLK_DEV_COW_COMMON is not set
128CONFIG_BLK_DEV_LOOP=y
129CONFIG_BLK_DEV_CRYPTOLOOP=m
130CONFIG_BLK_DEV_NBD=m
131CONFIG_BLK_DEV_RAM=y
132CONFIG_BLK_DEV_RAM_COUNT=16
133CONFIG_BLK_DEV_RAM_SIZE=4096
134CONFIG_BLK_DEV_INITRD=y
135CONFIG_INITRAMFS_SOURCE=""
136CONFIG_CDROM_PKTCDVD=m
137CONFIG_CDROM_PKTCDVD_BUFFERS=8
138# CONFIG_CDROM_PKTCDVD_WCACHE is not set
139
140#
141# IO Schedulers
142#
143CONFIG_IOSCHED_NOOP=y
144CONFIG_IOSCHED_AS=y
145CONFIG_IOSCHED_DEADLINE=y
146CONFIG_IOSCHED_CFQ=y
147CONFIG_ATA_OVER_ETH=m
148
149#
150# ATA/ATAPI/MFM/RLL support
151#
152# CONFIG_IDE is not set
153
154#
155# SCSI device support
156#
157CONFIG_SCSI=y
158CONFIG_SCSI_PROC_FS=y
159
160#
161# SCSI support type (disk, tape, CD-ROM)
162#
163CONFIG_BLK_DEV_SD=y
164CONFIG_CHR_DEV_ST=m
165# CONFIG_CHR_DEV_OSST is not set
166CONFIG_BLK_DEV_SR=y
167CONFIG_BLK_DEV_SR_VENDOR=y
168CONFIG_CHR_DEV_SG=m
169
170#
171# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
172#
173# CONFIG_SCSI_MULTI_LUN is not set
174CONFIG_SCSI_CONSTANTS=y
175# CONFIG_SCSI_LOGGING is not set
176
177#
178# SCSI Transport Attributes
179#
180# CONFIG_SCSI_SPI_ATTRS is not set
181# CONFIG_SCSI_FC_ATTRS is not set
182# CONFIG_SCSI_ISCSI_ATTRS is not set
183
184#
185# SCSI low-level drivers
186#
187# CONFIG_SCSI_SATA is not set
188# CONFIG_SCSI_DEBUG is not set
189
190#
191# Multi-device support (RAID and LVM)
192#
193CONFIG_MD=y
194CONFIG_BLK_DEV_MD=m
195CONFIG_MD_LINEAR=m
196CONFIG_MD_RAID0=m
197CONFIG_MD_RAID1=m
198# CONFIG_MD_RAID10 is not set
199CONFIG_MD_RAID5=m
200CONFIG_MD_RAID6=m
201CONFIG_MD_MULTIPATH=m
202# CONFIG_MD_FAULTY is not set
203CONFIG_BLK_DEV_DM=m
204CONFIG_DM_CRYPT=m
205CONFIG_DM_SNAPSHOT=m
206CONFIG_DM_MIRROR=m
207CONFIG_DM_ZERO=m
208CONFIG_DM_MULTIPATH=m
209CONFIG_DM_MULTIPATH_EMC=m
210
211#
212# Fusion MPT device support
213#
214
215#
216# IEEE 1394 (FireWire) support
217#
218
219#
220# I2O device support
221#
222
223#
224# Networking support
225# 164#
226CONFIG_NET=y 165CONFIG_NET=y
227 166
@@ -231,10 +170,17 @@ CONFIG_NET=y
231CONFIG_PACKET=y 170CONFIG_PACKET=y
232# CONFIG_PACKET_MMAP is not set 171# CONFIG_PACKET_MMAP is not set
233CONFIG_UNIX=y 172CONFIG_UNIX=y
173CONFIG_XFRM=y
174# CONFIG_XFRM_USER is not set
175# CONFIG_XFRM_SUB_POLICY is not set
176CONFIG_XFRM_MIGRATE=y
177# CONFIG_XFRM_STATISTICS is not set
234CONFIG_NET_KEY=y 178CONFIG_NET_KEY=y
179CONFIG_NET_KEY_MIGRATE=y
235CONFIG_INET=y 180CONFIG_INET=y
236# CONFIG_IP_MULTICAST is not set 181# CONFIG_IP_MULTICAST is not set
237# CONFIG_IP_ADVANCED_ROUTER is not set 182# CONFIG_IP_ADVANCED_ROUTER is not set
183CONFIG_IP_FIB_HASH=y
238CONFIG_IP_PNP=y 184CONFIG_IP_PNP=y
239CONFIG_IP_PNP_DHCP=y 185CONFIG_IP_PNP_DHCP=y
240CONFIG_IP_PNP_BOOTP=y 186CONFIG_IP_PNP_BOOTP=y
@@ -246,145 +192,199 @@ CONFIG_SYN_COOKIES=y
246CONFIG_INET_AH=m 192CONFIG_INET_AH=m
247CONFIG_INET_ESP=m 193CONFIG_INET_ESP=m
248CONFIG_INET_IPCOMP=m 194CONFIG_INET_IPCOMP=m
195CONFIG_INET_XFRM_TUNNEL=m
249CONFIG_INET_TUNNEL=m 196CONFIG_INET_TUNNEL=m
250CONFIG_IP_TCPDIAG=m 197CONFIG_INET_XFRM_MODE_TRANSPORT=m
251CONFIG_IP_TCPDIAG_IPV6=y 198CONFIG_INET_XFRM_MODE_TUNNEL=m
252 199CONFIG_INET_XFRM_MODE_BEET=m
253# 200CONFIG_INET_LRO=m
254# IP: Virtual Server Configuration 201CONFIG_INET_DIAG=m
255# 202CONFIG_INET_TCP_DIAG=m
203# CONFIG_TCP_CONG_ADVANCED is not set
204CONFIG_TCP_CONG_CUBIC=y
205CONFIG_DEFAULT_TCP_CONG="cubic"
206# CONFIG_TCP_MD5SIG is not set
256# CONFIG_IP_VS is not set 207# CONFIG_IP_VS is not set
257CONFIG_IPV6=m 208CONFIG_IPV6=m
258CONFIG_IPV6_PRIVACY=y 209CONFIG_IPV6_PRIVACY=y
210CONFIG_IPV6_ROUTER_PREF=y
211CONFIG_IPV6_ROUTE_INFO=y
212# CONFIG_IPV6_OPTIMISTIC_DAD is not set
259CONFIG_INET6_AH=m 213CONFIG_INET6_AH=m
260CONFIG_INET6_ESP=m 214CONFIG_INET6_ESP=m
261CONFIG_INET6_IPCOMP=m 215CONFIG_INET6_IPCOMP=m
216# CONFIG_IPV6_MIP6 is not set
217CONFIG_INET6_XFRM_TUNNEL=m
262CONFIG_INET6_TUNNEL=m 218CONFIG_INET6_TUNNEL=m
219CONFIG_INET6_XFRM_MODE_TRANSPORT=m
220CONFIG_INET6_XFRM_MODE_TUNNEL=m
221CONFIG_INET6_XFRM_MODE_BEET=m
222CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
223CONFIG_IPV6_SIT=m
263CONFIG_IPV6_TUNNEL=m 224CONFIG_IPV6_TUNNEL=m
225# CONFIG_IPV6_MULTIPLE_TABLES is not set
226# CONFIG_NETWORK_SECMARK is not set
264CONFIG_NETFILTER=y 227CONFIG_NETFILTER=y
265# CONFIG_NETFILTER_DEBUG is not set 228# CONFIG_NETFILTER_DEBUG is not set
229CONFIG_NETFILTER_ADVANCED=y
230
231#
232# Core Netfilter Configuration
233#
234CONFIG_NETFILTER_NETLINK=m
235CONFIG_NETFILTER_NETLINK_QUEUE=m
236CONFIG_NETFILTER_NETLINK_LOG=m
237CONFIG_NF_CONNTRACK=m
238CONFIG_NF_CT_ACCT=y
239CONFIG_NF_CONNTRACK_MARK=y
240# CONFIG_NF_CONNTRACK_EVENTS is not set
241CONFIG_NF_CT_PROTO_GRE=m
242CONFIG_NF_CT_PROTO_SCTP=m
243CONFIG_NF_CT_PROTO_UDPLITE=m
244CONFIG_NF_CONNTRACK_AMANDA=m
245CONFIG_NF_CONNTRACK_FTP=m
246CONFIG_NF_CONNTRACK_H323=m
247CONFIG_NF_CONNTRACK_IRC=m
248CONFIG_NF_CONNTRACK_NETBIOS_NS=m
249CONFIG_NF_CONNTRACK_PPTP=m
250CONFIG_NF_CONNTRACK_SANE=m
251CONFIG_NF_CONNTRACK_SIP=m
252CONFIG_NF_CONNTRACK_TFTP=m
253# CONFIG_NF_CT_NETLINK is not set
254CONFIG_NETFILTER_XTABLES=m
255CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
256CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
257CONFIG_NETFILTER_XT_TARGET_DSCP=m
258CONFIG_NETFILTER_XT_TARGET_MARK=m
259CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
260CONFIG_NETFILTER_XT_TARGET_NFLOG=m
261CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
262CONFIG_NETFILTER_XT_TARGET_RATEEST=m
263CONFIG_NETFILTER_XT_TARGET_TRACE=m
264CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
265CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
266CONFIG_NETFILTER_XT_MATCH_COMMENT=m
267CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
268CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
269CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
270CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
271CONFIG_NETFILTER_XT_MATCH_DCCP=m
272CONFIG_NETFILTER_XT_MATCH_DSCP=m
273CONFIG_NETFILTER_XT_MATCH_ESP=m
274CONFIG_NETFILTER_XT_MATCH_HELPER=m
275CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
276CONFIG_NETFILTER_XT_MATCH_LENGTH=m
277CONFIG_NETFILTER_XT_MATCH_LIMIT=m
278CONFIG_NETFILTER_XT_MATCH_MAC=m
279CONFIG_NETFILTER_XT_MATCH_MARK=m
280CONFIG_NETFILTER_XT_MATCH_OWNER=m
281CONFIG_NETFILTER_XT_MATCH_POLICY=m
282CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
283CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
284CONFIG_NETFILTER_XT_MATCH_QUOTA=m
285CONFIG_NETFILTER_XT_MATCH_RATEEST=m
286CONFIG_NETFILTER_XT_MATCH_REALM=m
287CONFIG_NETFILTER_XT_MATCH_SCTP=m
288CONFIG_NETFILTER_XT_MATCH_STATE=m
289CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
290CONFIG_NETFILTER_XT_MATCH_STRING=m
291CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
292CONFIG_NETFILTER_XT_MATCH_TIME=m
293CONFIG_NETFILTER_XT_MATCH_U32=m
294CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
266 295
267# 296#
268# IP: Netfilter Configuration 297# IP: Netfilter Configuration
269# 298#
270CONFIG_IP_NF_CONNTRACK=m 299CONFIG_NF_CONNTRACK_IPV4=m
271# CONFIG_IP_NF_CT_ACCT is not set 300CONFIG_NF_CONNTRACK_PROC_COMPAT=y
272CONFIG_IP_NF_CONNTRACK_MARK=y
273# CONFIG_IP_NF_CT_PROTO_SCTP is not set
274CONFIG_IP_NF_FTP=m
275CONFIG_IP_NF_IRC=m
276CONFIG_IP_NF_TFTP=m
277CONFIG_IP_NF_AMANDA=m
278CONFIG_IP_NF_QUEUE=m 301CONFIG_IP_NF_QUEUE=m
279CONFIG_IP_NF_IPTABLES=m 302CONFIG_IP_NF_IPTABLES=m
280CONFIG_IP_NF_MATCH_LIMIT=m
281CONFIG_IP_NF_MATCH_IPRANGE=m
282CONFIG_IP_NF_MATCH_MAC=m
283CONFIG_IP_NF_MATCH_PKTTYPE=m
284CONFIG_IP_NF_MATCH_MARK=m
285CONFIG_IP_NF_MATCH_MULTIPORT=m
286CONFIG_IP_NF_MATCH_TOS=m
287CONFIG_IP_NF_MATCH_RECENT=m 303CONFIG_IP_NF_MATCH_RECENT=m
288CONFIG_IP_NF_MATCH_ECN=m 304CONFIG_IP_NF_MATCH_ECN=m
289CONFIG_IP_NF_MATCH_DSCP=m 305CONFIG_IP_NF_MATCH_AH=m
290CONFIG_IP_NF_MATCH_AH_ESP=m
291CONFIG_IP_NF_MATCH_LENGTH=m
292CONFIG_IP_NF_MATCH_TTL=m 306CONFIG_IP_NF_MATCH_TTL=m
293CONFIG_IP_NF_MATCH_TCPMSS=m
294CONFIG_IP_NF_MATCH_HELPER=m
295CONFIG_IP_NF_MATCH_STATE=m
296CONFIG_IP_NF_MATCH_CONNTRACK=m
297CONFIG_IP_NF_MATCH_OWNER=m
298CONFIG_IP_NF_MATCH_ADDRTYPE=m 307CONFIG_IP_NF_MATCH_ADDRTYPE=m
299CONFIG_IP_NF_MATCH_REALM=m
300# CONFIG_IP_NF_MATCH_SCTP is not set
301# CONFIG_IP_NF_MATCH_COMMENT is not set
302CONFIG_IP_NF_MATCH_CONNMARK=m
303CONFIG_IP_NF_MATCH_HASHLIMIT=m
304CONFIG_IP_NF_FILTER=m 308CONFIG_IP_NF_FILTER=m
305CONFIG_IP_NF_TARGET_REJECT=m 309CONFIG_IP_NF_TARGET_REJECT=m
306CONFIG_IP_NF_TARGET_LOG=m 310CONFIG_IP_NF_TARGET_LOG=m
307CONFIG_IP_NF_TARGET_ULOG=m 311CONFIG_IP_NF_TARGET_ULOG=m
308CONFIG_IP_NF_TARGET_TCPMSS=m 312CONFIG_NF_NAT=m
309CONFIG_IP_NF_NAT=m 313CONFIG_NF_NAT_NEEDED=y
310CONFIG_IP_NF_NAT_NEEDED=y
311CONFIG_IP_NF_TARGET_MASQUERADE=m 314CONFIG_IP_NF_TARGET_MASQUERADE=m
312CONFIG_IP_NF_TARGET_REDIRECT=m 315CONFIG_IP_NF_TARGET_REDIRECT=m
313CONFIG_IP_NF_TARGET_NETMAP=m 316CONFIG_IP_NF_TARGET_NETMAP=m
314CONFIG_IP_NF_TARGET_SAME=m 317CONFIG_NF_NAT_SNMP_BASIC=m
315CONFIG_IP_NF_NAT_SNMP_BASIC=m 318CONFIG_NF_NAT_PROTO_GRE=m
316CONFIG_IP_NF_NAT_IRC=m 319CONFIG_NF_NAT_FTP=m
317CONFIG_IP_NF_NAT_FTP=m 320CONFIG_NF_NAT_IRC=m
318CONFIG_IP_NF_NAT_TFTP=m 321CONFIG_NF_NAT_TFTP=m
319CONFIG_IP_NF_NAT_AMANDA=m 322CONFIG_NF_NAT_AMANDA=m
323CONFIG_NF_NAT_PPTP=m
324CONFIG_NF_NAT_H323=m
325CONFIG_NF_NAT_SIP=m
320CONFIG_IP_NF_MANGLE=m 326CONFIG_IP_NF_MANGLE=m
321CONFIG_IP_NF_TARGET_TOS=m
322CONFIG_IP_NF_TARGET_ECN=m 327CONFIG_IP_NF_TARGET_ECN=m
323CONFIG_IP_NF_TARGET_DSCP=m 328CONFIG_IP_NF_TARGET_TTL=m
324CONFIG_IP_NF_TARGET_MARK=m 329CONFIG_IP_NF_TARGET_CLUSTERIP=m
325CONFIG_IP_NF_TARGET_CLASSIFY=m
326CONFIG_IP_NF_TARGET_CONNMARK=m
327# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
328CONFIG_IP_NF_RAW=m 330CONFIG_IP_NF_RAW=m
329CONFIG_IP_NF_TARGET_NOTRACK=m
330CONFIG_IP_NF_ARPTABLES=m 331CONFIG_IP_NF_ARPTABLES=m
331CONFIG_IP_NF_ARPFILTER=m 332CONFIG_IP_NF_ARPFILTER=m
332CONFIG_IP_NF_ARP_MANGLE=m 333CONFIG_IP_NF_ARP_MANGLE=m
333 334
334# 335#
335# IPv6: Netfilter Configuration (EXPERIMENTAL) 336# IPv6: Netfilter Configuration
336# 337#
338CONFIG_NF_CONNTRACK_IPV6=m
337CONFIG_IP6_NF_QUEUE=m 339CONFIG_IP6_NF_QUEUE=m
338CONFIG_IP6_NF_IPTABLES=m 340CONFIG_IP6_NF_IPTABLES=m
339CONFIG_IP6_NF_MATCH_LIMIT=m
340CONFIG_IP6_NF_MATCH_MAC=m
341CONFIG_IP6_NF_MATCH_RT=m 341CONFIG_IP6_NF_MATCH_RT=m
342CONFIG_IP6_NF_MATCH_OPTS=m 342CONFIG_IP6_NF_MATCH_OPTS=m
343CONFIG_IP6_NF_MATCH_FRAG=m 343CONFIG_IP6_NF_MATCH_FRAG=m
344CONFIG_IP6_NF_MATCH_HL=m 344CONFIG_IP6_NF_MATCH_HL=m
345CONFIG_IP6_NF_MATCH_MULTIPORT=m
346CONFIG_IP6_NF_MATCH_OWNER=m
347CONFIG_IP6_NF_MATCH_MARK=m
348CONFIG_IP6_NF_MATCH_IPV6HEADER=m 345CONFIG_IP6_NF_MATCH_IPV6HEADER=m
349CONFIG_IP6_NF_MATCH_AHESP=m 346CONFIG_IP6_NF_MATCH_AH=m
350CONFIG_IP6_NF_MATCH_LENGTH=m 347CONFIG_IP6_NF_MATCH_MH=m
351CONFIG_IP6_NF_MATCH_EUI64=m 348CONFIG_IP6_NF_MATCH_EUI64=m
352CONFIG_IP6_NF_FILTER=m 349CONFIG_IP6_NF_FILTER=m
353CONFIG_IP6_NF_TARGET_LOG=m 350CONFIG_IP6_NF_TARGET_LOG=m
351CONFIG_IP6_NF_TARGET_REJECT=m
354CONFIG_IP6_NF_MANGLE=m 352CONFIG_IP6_NF_MANGLE=m
355CONFIG_IP6_NF_TARGET_MARK=m 353CONFIG_IP6_NF_TARGET_HL=m
356CONFIG_IP6_NF_RAW=m 354CONFIG_IP6_NF_RAW=m
357CONFIG_XFRM=y 355CONFIG_IP_DCCP=m
358CONFIG_XFRM_USER=m 356CONFIG_INET_DCCP_DIAG=m
357CONFIG_IP_DCCP_ACKVEC=y
359 358
360# 359#
361# SCTP Configuration (EXPERIMENTAL) 360# DCCP CCIDs Configuration (EXPERIMENTAL)
362# 361#
362CONFIG_IP_DCCP_CCID2=m
363# CONFIG_IP_DCCP_CCID2_DEBUG is not set
364CONFIG_IP_DCCP_CCID3=m
365# CONFIG_IP_DCCP_CCID3_DEBUG is not set
366CONFIG_IP_DCCP_CCID3_RTO=100
367CONFIG_IP_DCCP_TFRC_LIB=m
363CONFIG_IP_SCTP=m 368CONFIG_IP_SCTP=m
364# CONFIG_SCTP_DBG_MSG is not set 369# CONFIG_SCTP_DBG_MSG is not set
365# CONFIG_SCTP_DBG_OBJCNT is not set 370# CONFIG_SCTP_DBG_OBJCNT is not set
366# CONFIG_SCTP_HMAC_NONE is not set 371# CONFIG_SCTP_HMAC_NONE is not set
367# CONFIG_SCTP_HMAC_SHA1 is not set 372# CONFIG_SCTP_HMAC_SHA1 is not set
368CONFIG_SCTP_HMAC_MD5=y 373CONFIG_SCTP_HMAC_MD5=y
374# CONFIG_TIPC is not set
369# CONFIG_ATM is not set 375# CONFIG_ATM is not set
370# CONFIG_BRIDGE is not set 376# CONFIG_BRIDGE is not set
371# CONFIG_VLAN_8021Q is not set 377# CONFIG_VLAN_8021Q is not set
372# CONFIG_DECNET is not set 378# CONFIG_DECNET is not set
373CONFIG_LLC=m 379CONFIG_LLC=m
374# CONFIG_LLC2 is not set 380# CONFIG_LLC2 is not set
375CONFIG_IPX=m 381# CONFIG_IPX is not set
376# CONFIG_IPX_INTERN is not set
377CONFIG_ATALK=m 382CONFIG_ATALK=m
378# CONFIG_DEV_APPLETALK is not set 383# CONFIG_DEV_APPLETALK is not set
379# CONFIG_X25 is not set 384# CONFIG_X25 is not set
380# CONFIG_LAPB is not set 385# CONFIG_LAPB is not set
381# CONFIG_NET_DIVERT is not set
382# CONFIG_ECONET is not set 386# CONFIG_ECONET is not set
383# CONFIG_WAN_ROUTER is not set 387# CONFIG_WAN_ROUTER is not set
384
385#
386# QoS and/or fair queueing
387#
388# CONFIG_NET_SCHED is not set 388# CONFIG_NET_SCHED is not set
389CONFIG_NET_CLS_ROUTE=y 389CONFIG_NET_CLS_ROUTE=y
390 390
@@ -392,46 +392,154 @@ CONFIG_NET_CLS_ROUTE=y
392# Network testing 392# Network testing
393# 393#
394# CONFIG_NET_PKTGEN is not set 394# CONFIG_NET_PKTGEN is not set
395CONFIG_NETPOLL=y
396# CONFIG_NETPOLL_RX is not set
397# CONFIG_NETPOLL_TRAP is not set
398CONFIG_NET_POLL_CONTROLLER=y
399# CONFIG_HAMRADIO is not set 395# CONFIG_HAMRADIO is not set
396# CONFIG_CAN is not set
400# CONFIG_IRDA is not set 397# CONFIG_IRDA is not set
401# CONFIG_BT is not set 398# CONFIG_BT is not set
402CONFIG_NETDEVICES=y 399# CONFIG_AF_RXRPC is not set
403CONFIG_DUMMY=m
404# CONFIG_BONDING is not set
405CONFIG_EQUALIZER=m
406# CONFIG_TUN is not set
407 400
408# 401#
409# Ethernet (10 or 100Mbit) 402# Wireless
410# 403#
411CONFIG_NET_ETHERNET=y 404# CONFIG_CFG80211 is not set
412CONFIG_MII=m 405CONFIG_WIRELESS_EXT=y
413CONFIG_HPLANCE=y 406# CONFIG_MAC80211 is not set
407CONFIG_IEEE80211=m
408# CONFIG_IEEE80211_DEBUG is not set
409CONFIG_IEEE80211_CRYPT_WEP=m
410CONFIG_IEEE80211_CRYPT_CCMP=m
411CONFIG_IEEE80211_CRYPT_TKIP=m
412CONFIG_IEEE80211_SOFTMAC=m
413# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
414# CONFIG_RFKILL is not set
415# CONFIG_NET_9P is not set
414 416
415# 417#
416# Ethernet (1000 Mbit) 418# Device Drivers
417# 419#
418 420
419# 421#
420# Ethernet (10000 Mbit) 422# Generic Driver Options
421# 423#
424CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
425CONFIG_STANDALONE=y
426CONFIG_PREVENT_FIRMWARE_BUILD=y
427CONFIG_FW_LOADER=m
428# CONFIG_SYS_HYPERVISOR is not set
429CONFIG_CONNECTOR=m
430# CONFIG_MTD is not set
431# CONFIG_PARPORT is not set
432CONFIG_BLK_DEV=y
433# CONFIG_BLK_DEV_COW_COMMON is not set
434CONFIG_BLK_DEV_LOOP=y
435CONFIG_BLK_DEV_CRYPTOLOOP=m
436CONFIG_BLK_DEV_NBD=m
437CONFIG_BLK_DEV_RAM=y
438CONFIG_BLK_DEV_RAM_COUNT=16
439CONFIG_BLK_DEV_RAM_SIZE=4096
440# CONFIG_BLK_DEV_XIP is not set
441CONFIG_CDROM_PKTCDVD=m
442CONFIG_CDROM_PKTCDVD_BUFFERS=8
443# CONFIG_CDROM_PKTCDVD_WCACHE is not set
444CONFIG_ATA_OVER_ETH=m
445CONFIG_MISC_DEVICES=y
446# CONFIG_EEPROM_93CX6 is not set
447# CONFIG_ENCLOSURE_SERVICES is not set
448CONFIG_HAVE_IDE=y
449# CONFIG_IDE is not set
422 450
423# 451#
424# Token Ring devices 452# SCSI device support
425# 453#
454CONFIG_RAID_ATTRS=m
455CONFIG_SCSI=y
456CONFIG_SCSI_DMA=y
457CONFIG_SCSI_TGT=m
458# CONFIG_SCSI_NETLINK is not set
459CONFIG_SCSI_PROC_FS=y
426 460
427# 461#
428# Wireless LAN (non-hamradio) 462# SCSI support type (disk, tape, CD-ROM)
429# 463#
430# CONFIG_NET_RADIO is not set 464CONFIG_BLK_DEV_SD=y
465CONFIG_CHR_DEV_ST=m
466CONFIG_CHR_DEV_OSST=m
467CONFIG_BLK_DEV_SR=y
468CONFIG_BLK_DEV_SR_VENDOR=y
469CONFIG_CHR_DEV_SG=m
470# CONFIG_CHR_DEV_SCH is not set
471
472#
473# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
474#
475# CONFIG_SCSI_MULTI_LUN is not set
476CONFIG_SCSI_CONSTANTS=y
477# CONFIG_SCSI_LOGGING is not set
478# CONFIG_SCSI_SCAN_ASYNC is not set
479CONFIG_SCSI_WAIT_SCAN=m
480
481#
482# SCSI Transports
483#
484# CONFIG_SCSI_SPI_ATTRS is not set
485# CONFIG_SCSI_FC_ATTRS is not set
486CONFIG_SCSI_ISCSI_ATTRS=m
487CONFIG_SCSI_SAS_ATTRS=m
488CONFIG_SCSI_SAS_LIBSAS=m
489CONFIG_SCSI_SAS_HOST_SMP=y
490# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
491CONFIG_SCSI_SRP_ATTRS=m
492CONFIG_SCSI_SRP_TGT_ATTRS=y
493CONFIG_SCSI_LOWLEVEL=y
494CONFIG_ISCSI_TCP=m
495# CONFIG_SCSI_DEBUG is not set
496CONFIG_MD=y
497CONFIG_BLK_DEV_MD=m
498CONFIG_MD_LINEAR=m
499CONFIG_MD_RAID0=m
500CONFIG_MD_RAID1=m
501# CONFIG_MD_RAID10 is not set
502CONFIG_MD_RAID456=m
503CONFIG_MD_RAID5_RESHAPE=y
504CONFIG_MD_MULTIPATH=m
505# CONFIG_MD_FAULTY is not set
506CONFIG_BLK_DEV_DM=m
507# CONFIG_DM_DEBUG is not set
508CONFIG_DM_CRYPT=m
509CONFIG_DM_SNAPSHOT=m
510CONFIG_DM_MIRROR=m
511CONFIG_DM_ZERO=m
512CONFIG_DM_MULTIPATH=m
513CONFIG_DM_MULTIPATH_EMC=m
514CONFIG_DM_MULTIPATH_RDAC=m
515CONFIG_DM_MULTIPATH_HP=m
516# CONFIG_DM_DELAY is not set
517CONFIG_DM_UEVENT=y
518CONFIG_NETDEVICES=y
519# CONFIG_NETDEVICES_MULTIQUEUE is not set
520CONFIG_DUMMY=m
521# CONFIG_BONDING is not set
522CONFIG_MACVLAN=m
523CONFIG_EQUALIZER=m
524# CONFIG_TUN is not set
525CONFIG_VETH=m
526# CONFIG_PHYLIB is not set
527CONFIG_NET_ETHERNET=y
528# CONFIG_MII is not set
529CONFIG_HPLANCE=y
530# CONFIG_IBM_NEW_EMAC_ZMII is not set
531# CONFIG_IBM_NEW_EMAC_RGMII is not set
532# CONFIG_IBM_NEW_EMAC_TAH is not set
533# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
534# CONFIG_B44 is not set
535# CONFIG_NETDEV_1000 is not set
536# CONFIG_NETDEV_10000 is not set
431 537
432# 538#
433# Wan interfaces 539# Wireless LAN
434# 540#
541# CONFIG_WLAN_PRE80211 is not set
542# CONFIG_WLAN_80211 is not set
435# CONFIG_WAN is not set 543# CONFIG_WAN is not set
436CONFIG_PPP=m 544CONFIG_PPP=m
437# CONFIG_PPP_MULTILINK is not set 545# CONFIG_PPP_MULTILINK is not set
@@ -440,28 +548,28 @@ CONFIG_PPP_ASYNC=m
440CONFIG_PPP_SYNC_TTY=m 548CONFIG_PPP_SYNC_TTY=m
441CONFIG_PPP_DEFLATE=m 549CONFIG_PPP_DEFLATE=m
442CONFIG_PPP_BSDCOMP=m 550CONFIG_PPP_BSDCOMP=m
551CONFIG_PPP_MPPE=m
443CONFIG_PPPOE=m 552CONFIG_PPPOE=m
553CONFIG_PPPOL2TP=m
444CONFIG_SLIP=m 554CONFIG_SLIP=m
445CONFIG_SLIP_COMPRESSED=y 555CONFIG_SLIP_COMPRESSED=y
556CONFIG_SLHC=m
446CONFIG_SLIP_SMART=y 557CONFIG_SLIP_SMART=y
447CONFIG_SLIP_MODE_SLIP6=y 558CONFIG_SLIP_MODE_SLIP6=y
448CONFIG_SHAPER=m
449CONFIG_NETCONSOLE=m 559CONFIG_NETCONSOLE=m
450 560CONFIG_NETCONSOLE_DYNAMIC=y
451# 561CONFIG_NETPOLL=y
452# ISDN subsystem 562# CONFIG_NETPOLL_TRAP is not set
453# 563CONFIG_NET_POLL_CONTROLLER=y
454# CONFIG_ISDN is not set 564# CONFIG_ISDN is not set
455
456#
457# Telephony Support
458#
459# CONFIG_PHONE is not set 565# CONFIG_PHONE is not set
460 566
461# 567#
462# Input device support 568# Input device support
463# 569#
464CONFIG_INPUT=y 570CONFIG_INPUT=y
571CONFIG_INPUT_FF_MEMLESS=m
572# CONFIG_INPUT_POLLDEV is not set
465 573
466# 574#
467# Userland interfaces 575# Userland interfaces
@@ -471,7 +579,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
471CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 579CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
472CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 580CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
473# CONFIG_INPUT_JOYDEV is not set 581# CONFIG_INPUT_JOYDEV is not set
474# CONFIG_INPUT_TSDEV is not set
475# CONFIG_INPUT_EVDEV is not set 582# CONFIG_INPUT_EVDEV is not set
476# CONFIG_INPUT_EVBUG is not set 583# CONFIG_INPUT_EVBUG is not set
477 584
@@ -484,19 +591,35 @@ CONFIG_INPUT_KEYBOARD=y
484# CONFIG_KEYBOARD_LKKBD is not set 591# CONFIG_KEYBOARD_LKKBD is not set
485# CONFIG_KEYBOARD_XTKBD is not set 592# CONFIG_KEYBOARD_XTKBD is not set
486# CONFIG_KEYBOARD_NEWTON is not set 593# CONFIG_KEYBOARD_NEWTON is not set
594# CONFIG_KEYBOARD_STOWAWAY is not set
595CONFIG_KEYBOARD_HIL_OLD=y
596CONFIG_KEYBOARD_HIL=y
487CONFIG_INPUT_MOUSE=y 597CONFIG_INPUT_MOUSE=y
488CONFIG_MOUSE_PS2=m 598CONFIG_MOUSE_PS2=m
599CONFIG_MOUSE_PS2_ALPS=y
600CONFIG_MOUSE_PS2_LOGIPS2PP=y
601CONFIG_MOUSE_PS2_SYNAPTICS=y
602CONFIG_MOUSE_PS2_LIFEBOOK=y
603CONFIG_MOUSE_PS2_TRACKPOINT=y
604# CONFIG_MOUSE_PS2_TOUCHKIT is not set
489CONFIG_MOUSE_SERIAL=m 605CONFIG_MOUSE_SERIAL=m
490# CONFIG_MOUSE_VSXXXAA is not set 606# CONFIG_MOUSE_VSXXXAA is not set
607CONFIG_MOUSE_HIL=m
491# CONFIG_INPUT_JOYSTICK is not set 608# CONFIG_INPUT_JOYSTICK is not set
609# CONFIG_INPUT_TABLET is not set
492# CONFIG_INPUT_TOUCHSCREEN is not set 610# CONFIG_INPUT_TOUCHSCREEN is not set
493# CONFIG_INPUT_MISC is not set 611CONFIG_INPUT_MISC=y
612# CONFIG_INPUT_M68K_BEEP is not set
613# CONFIG_INPUT_UINPUT is not set
614CONFIG_HP_SDC_RTC=m
494 615
495# 616#
496# Hardware I/O ports 617# Hardware I/O ports
497# 618#
498CONFIG_SERIO=m 619CONFIG_SERIO=y
499CONFIG_SERIO_SERPORT=m 620# CONFIG_SERIO_SERPORT is not set
621CONFIG_HP_SDC=y
622CONFIG_HIL_MLC=y
500CONFIG_SERIO_LIBPS2=m 623CONFIG_SERIO_LIBPS2=m
501# CONFIG_SERIO_RAW is not set 624# CONFIG_SERIO_RAW is not set
502# CONFIG_GAMEPORT is not set 625# CONFIG_GAMEPORT is not set
@@ -507,6 +630,7 @@ CONFIG_SERIO_LIBPS2=m
507CONFIG_VT=y 630CONFIG_VT=y
508CONFIG_VT_CONSOLE=y 631CONFIG_VT_CONSOLE=y
509CONFIG_HW_CONSOLE=y 632CONFIG_HW_CONSOLE=y
633CONFIG_VT_HW_CONSOLE_BINDING=y
510# CONFIG_SERIAL_NONSTANDARD is not set 634# CONFIG_SERIAL_NONSTANDARD is not set
511 635
512# 636#
@@ -520,90 +644,114 @@ CONFIG_HW_CONSOLE=y
520CONFIG_UNIX98_PTYS=y 644CONFIG_UNIX98_PTYS=y
521CONFIG_LEGACY_PTYS=y 645CONFIG_LEGACY_PTYS=y
522CONFIG_LEGACY_PTY_COUNT=256 646CONFIG_LEGACY_PTY_COUNT=256
523
524#
525# IPMI
526#
527# CONFIG_IPMI_HANDLER is not set 647# CONFIG_IPMI_HANDLER is not set
528 648# CONFIG_HW_RANDOM is not set
529# 649CONFIG_GEN_RTC=m
530# Watchdog Cards
531#
532# CONFIG_WATCHDOG is not set
533CONFIG_GEN_RTC=y
534CONFIG_GEN_RTC_X=y 650CONFIG_GEN_RTC_X=y
535# CONFIG_DTLK is not set
536# CONFIG_R3964 is not set 651# CONFIG_R3964 is not set
537
538#
539# Ftape, the floppy tape device driver
540#
541# CONFIG_DRM is not set
542# CONFIG_RAW_DRIVER is not set 652# CONFIG_RAW_DRIVER is not set
653# CONFIG_TCG_TPM is not set
654# CONFIG_I2C is not set
543 655
544# 656#
545# TPM devices 657# SPI support
546# 658#
659# CONFIG_SPI is not set
660# CONFIG_SPI_MASTER is not set
661# CONFIG_W1 is not set
662# CONFIG_POWER_SUPPLY is not set
663# CONFIG_HWMON is not set
664# CONFIG_THERMAL is not set
665# CONFIG_WATCHDOG is not set
547 666
548# 667#
549# I2C support 668# Sonics Silicon Backplane
550# 669#
551# CONFIG_I2C is not set 670CONFIG_SSB_POSSIBLE=y
671# CONFIG_SSB is not set
552 672
553# 673#
554# Dallas's 1-wire bus 674# Multifunction device drivers
555# 675#
556# CONFIG_W1 is not set 676# CONFIG_MFD_SM501 is not set
557 677
558# 678#
559# Misc devices 679# Multimedia devices
560# 680#
681# CONFIG_VIDEO_DEV is not set
682# CONFIG_DVB_CORE is not set
683# CONFIG_DAB is not set
561 684
562# 685#
563# Multimedia devices 686# Graphics support
564# 687#
565# CONFIG_VIDEO_DEV is not set 688# CONFIG_VGASTATE is not set
689# CONFIG_VIDEO_OUTPUT_CONTROL is not set
690CONFIG_FB=y
691# CONFIG_FIRMWARE_EDID is not set
692# CONFIG_FB_DDC is not set
693CONFIG_FB_CFB_FILLRECT=y
694# CONFIG_FB_CFB_COPYAREA is not set
695CONFIG_FB_CFB_IMAGEBLIT=y
696# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
697# CONFIG_FB_SYS_FILLRECT is not set
698# CONFIG_FB_SYS_COPYAREA is not set
699# CONFIG_FB_SYS_IMAGEBLIT is not set
700# CONFIG_FB_SYS_FOPS is not set
701CONFIG_FB_DEFERRED_IO=y
702# CONFIG_FB_SVGALIB is not set
703# CONFIG_FB_MACMODES is not set
704# CONFIG_FB_BACKLIGHT is not set
705# CONFIG_FB_MODE_HELPERS is not set
706# CONFIG_FB_TILEBLITTING is not set
566 707
567# 708#
568# Digital Video Broadcasting Devices 709# Frame buffer hardware drivers
569# 710#
570# CONFIG_DVB is not set 711CONFIG_FB_HP300=y
712# CONFIG_FB_UVESA is not set
713# CONFIG_FB_S1D13XXX is not set
714# CONFIG_FB_VIRTUAL is not set
715# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
571 716
572# 717#
573# Graphics support 718# Display device support
574# 719#
575# CONFIG_FB is not set 720# CONFIG_DISPLAY_SUPPORT is not set
576 721
577# 722#
578# Console display driver support 723# Console display driver support
579# 724#
580CONFIG_DUMMY_CONSOLE=y 725CONFIG_DUMMY_CONSOLE=y
726CONFIG_FRAMEBUFFER_CONSOLE=y
727# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
728# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
729# CONFIG_FONTS is not set
730CONFIG_FONT_8x8=y
731CONFIG_FONT_8x16=y
732CONFIG_LOGO=y
733# CONFIG_LOGO_LINUX_MONO is not set
734# CONFIG_LOGO_LINUX_VGA16 is not set
735CONFIG_LOGO_LINUX_CLUT224=y
581 736
582# 737#
583# Sound 738# Sound
584# 739#
585# CONFIG_SOUND is not set 740# CONFIG_SOUND is not set
586 741CONFIG_HID_SUPPORT=y
587# 742CONFIG_HID=m
588# USB support 743# CONFIG_HID_DEBUG is not set
589# 744CONFIG_HIDRAW=y
590# CONFIG_USB_ARCH_HAS_HCD is not set 745# CONFIG_USB_SUPPORT is not set
591# CONFIG_USB_ARCH_HAS_OHCI is not set
592
593#
594# USB Gadget Support
595#
596# CONFIG_USB_GADGET is not set
597
598#
599# MMC/SD Card support
600#
601# CONFIG_MMC is not set 746# CONFIG_MMC is not set
747# CONFIG_MEMSTICK is not set
748# CONFIG_NEW_LEDS is not set
749# CONFIG_RTC_CLASS is not set
602 750
603# 751#
604# InfiniBand support 752# Userspace I/O
605# 753#
606# CONFIG_INFINIBAND is not set 754# CONFIG_UIO is not set
607 755
608# 756#
609# Character devices 757# Character devices
@@ -614,10 +762,11 @@ CONFIG_DUMMY_CONSOLE=y
614# 762#
615CONFIG_EXT2_FS=y 763CONFIG_EXT2_FS=y
616# CONFIG_EXT2_FS_XATTR is not set 764# CONFIG_EXT2_FS_XATTR is not set
765# CONFIG_EXT2_FS_XIP is not set
617CONFIG_EXT3_FS=y 766CONFIG_EXT3_FS=y
618# CONFIG_EXT3_FS_XATTR is not set 767# CONFIG_EXT3_FS_XATTR is not set
768# CONFIG_EXT4DEV_FS is not set
619CONFIG_JBD=y 769CONFIG_JBD=y
620# CONFIG_JBD_DEBUG is not set
621CONFIG_REISERFS_FS=m 770CONFIG_REISERFS_FS=m
622# CONFIG_REISERFS_CHECK is not set 771# CONFIG_REISERFS_CHECK is not set
623# CONFIG_REISERFS_PROC_INFO is not set 772# CONFIG_REISERFS_PROC_INFO is not set
@@ -628,25 +777,29 @@ CONFIG_JFS_FS=m
628# CONFIG_JFS_DEBUG is not set 777# CONFIG_JFS_DEBUG is not set
629# CONFIG_JFS_STATISTICS is not set 778# CONFIG_JFS_STATISTICS is not set
630CONFIG_FS_POSIX_ACL=y 779CONFIG_FS_POSIX_ACL=y
631
632#
633# XFS support
634#
635CONFIG_XFS_FS=m 780CONFIG_XFS_FS=m
636CONFIG_XFS_EXPORT=y
637# CONFIG_XFS_RT is not set
638# CONFIG_XFS_QUOTA is not set 781# CONFIG_XFS_QUOTA is not set
639# CONFIG_XFS_SECURITY is not set 782# CONFIG_XFS_SECURITY is not set
640# CONFIG_XFS_POSIX_ACL is not set 783# CONFIG_XFS_POSIX_ACL is not set
641CONFIG_MINIX_FS=y 784# CONFIG_XFS_RT is not set
642# CONFIG_ROMFS_FS is not set 785CONFIG_GFS2_FS=m
786CONFIG_GFS2_FS_LOCKING_NOLOCK=m
787CONFIG_GFS2_FS_LOCKING_DLM=m
788CONFIG_OCFS2_FS=m
789# CONFIG_OCFS2_DEBUG_MASKLOG is not set
790# CONFIG_OCFS2_DEBUG_FS is not set
791CONFIG_DNOTIFY=y
792CONFIG_INOTIFY=y
793CONFIG_INOTIFY_USER=y
643CONFIG_QUOTA=y 794CONFIG_QUOTA=y
795CONFIG_QUOTA_NETLINK_INTERFACE=y
796# CONFIG_PRINT_QUOTA_WARNING is not set
644# CONFIG_QFMT_V1 is not set 797# CONFIG_QFMT_V1 is not set
645# CONFIG_QFMT_V2 is not set 798# CONFIG_QFMT_V2 is not set
646CONFIG_QUOTACTL=y 799CONFIG_QUOTACTL=y
647CONFIG_DNOTIFY=y
648CONFIG_AUTOFS_FS=m 800CONFIG_AUTOFS_FS=m
649CONFIG_AUTOFS4_FS=m 801CONFIG_AUTOFS4_FS=m
802CONFIG_FUSE_FS=m
650 803
651# 804#
652# CD-ROM/DVD Filesystems 805# CD-ROM/DVD Filesystems
@@ -654,7 +807,6 @@ CONFIG_AUTOFS4_FS=m
654CONFIG_ISO9660_FS=y 807CONFIG_ISO9660_FS=y
655CONFIG_JOLIET=y 808CONFIG_JOLIET=y
656CONFIG_ZISOFS=y 809CONFIG_ZISOFS=y
657CONFIG_ZISOFS_FS=y
658CONFIG_UDF_FS=m 810CONFIG_UDF_FS=m
659CONFIG_UDF_NLS=y 811CONFIG_UDF_NLS=y
660 812
@@ -673,13 +825,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
673# 825#
674CONFIG_PROC_FS=y 826CONFIG_PROC_FS=y
675CONFIG_PROC_KCORE=y 827CONFIG_PROC_KCORE=y
828CONFIG_PROC_SYSCTL=y
676CONFIG_SYSFS=y 829CONFIG_SYSFS=y
677# CONFIG_DEVFS_FS is not set
678# CONFIG_DEVPTS_FS_XATTR is not set
679CONFIG_TMPFS=y 830CONFIG_TMPFS=y
680# CONFIG_TMPFS_XATTR is not set 831# CONFIG_TMPFS_POSIX_ACL is not set
681# CONFIG_HUGETLB_PAGE is not set 832# CONFIG_HUGETLB_PAGE is not set
682CONFIG_RAMFS=y 833CONFIG_CONFIGFS_FS=m
683 834
684# 835#
685# Miscellaneous filesystems 836# Miscellaneous filesystems
@@ -693,44 +844,40 @@ CONFIG_HFSPLUS_FS=m
693# CONFIG_EFS_FS is not set 844# CONFIG_EFS_FS is not set
694CONFIG_CRAMFS=m 845CONFIG_CRAMFS=m
695# CONFIG_VXFS_FS is not set 846# CONFIG_VXFS_FS is not set
847CONFIG_MINIX_FS=y
696CONFIG_HPFS_FS=m 848CONFIG_HPFS_FS=m
697# CONFIG_QNX4FS_FS is not set 849# CONFIG_QNX4FS_FS is not set
850# CONFIG_ROMFS_FS is not set
698CONFIG_SYSV_FS=m 851CONFIG_SYSV_FS=m
699CONFIG_UFS_FS=m 852CONFIG_UFS_FS=m
700# CONFIG_UFS_FS_WRITE is not set 853# CONFIG_UFS_FS_WRITE is not set
701 854# CONFIG_UFS_DEBUG is not set
702# 855CONFIG_NETWORK_FILESYSTEMS=y
703# Network File Systems
704#
705CONFIG_NFS_FS=y 856CONFIG_NFS_FS=y
706CONFIG_NFS_V3=y 857CONFIG_NFS_V3=y
858# CONFIG_NFS_V3_ACL is not set
707CONFIG_NFS_V4=y 859CONFIG_NFS_V4=y
708# CONFIG_NFS_DIRECTIO is not set 860# CONFIG_NFS_DIRECTIO is not set
709CONFIG_NFSD=m 861CONFIG_NFSD=m
710CONFIG_NFSD_V3=y 862CONFIG_NFSD_V3=y
711CONFIG_NFSD_V4=y 863# CONFIG_NFSD_V3_ACL is not set
864# CONFIG_NFSD_V4 is not set
712CONFIG_NFSD_TCP=y 865CONFIG_NFSD_TCP=y
713CONFIG_ROOT_NFS=y 866CONFIG_ROOT_NFS=y
714CONFIG_LOCKD=y 867CONFIG_LOCKD=y
715CONFIG_LOCKD_V4=y 868CONFIG_LOCKD_V4=y
716CONFIG_EXPORTFS=m 869CONFIG_EXPORTFS=m
870CONFIG_NFS_COMMON=y
717CONFIG_SUNRPC=y 871CONFIG_SUNRPC=y
718CONFIG_SUNRPC_GSS=y 872CONFIG_SUNRPC_GSS=y
873CONFIG_SUNRPC_BIND34=y
719CONFIG_RPCSEC_GSS_KRB5=y 874CONFIG_RPCSEC_GSS_KRB5=y
720# CONFIG_RPCSEC_GSS_SPKM3 is not set 875# CONFIG_RPCSEC_GSS_SPKM3 is not set
721CONFIG_SMB_FS=m 876CONFIG_SMB_FS=m
722CONFIG_SMB_NLS_DEFAULT=y 877CONFIG_SMB_NLS_DEFAULT=y
723CONFIG_SMB_NLS_REMOTE="cp437" 878CONFIG_SMB_NLS_REMOTE="cp437"
724# CONFIG_CIFS is not set 879# CONFIG_CIFS is not set
725CONFIG_NCP_FS=m 880# CONFIG_NCP_FS is not set
726# CONFIG_NCPFS_PACKET_SIGNING is not set
727# CONFIG_NCPFS_IOCTL_LOCKING is not set
728# CONFIG_NCPFS_STRONG is not set
729CONFIG_NCPFS_NFS_NS=y
730CONFIG_NCPFS_OS2_NS=y
731# CONFIG_NCPFS_SMALLDOS is not set
732CONFIG_NCPFS_NLS=y
733# CONFIG_NCPFS_EXTRAS is not set
734CONFIG_CODA_FS=m 881CONFIG_CODA_FS=m
735# CONFIG_CODA_FS_OLD_API is not set 882# CONFIG_CODA_FS_OLD_API is not set
736# CONFIG_AFS_FS is not set 883# CONFIG_AFS_FS is not set
@@ -740,10 +887,6 @@ CONFIG_CODA_FS=m
740# 887#
741# CONFIG_PARTITION_ADVANCED is not set 888# CONFIG_PARTITION_ADVANCED is not set
742CONFIG_MSDOS_PARTITION=y 889CONFIG_MSDOS_PARTITION=y
743
744#
745# Native Language Support
746#
747CONFIG_NLS=y 890CONFIG_NLS=y
748CONFIG_NLS_DEFAULT="iso8859-1" 891CONFIG_NLS_DEFAULT="iso8859-1"
749CONFIG_NLS_CODEPAGE_437=y 892CONFIG_NLS_CODEPAGE_437=y
@@ -784,35 +927,42 @@ CONFIG_NLS_ISO8859_15=m
784CONFIG_NLS_KOI8_R=m 927CONFIG_NLS_KOI8_R=m
785CONFIG_NLS_KOI8_U=m 928CONFIG_NLS_KOI8_U=m
786CONFIG_NLS_UTF8=m 929CONFIG_NLS_UTF8=m
930CONFIG_DLM=m
931# CONFIG_DLM_DEBUG is not set
787 932
788# 933#
789# Kernel hacking 934# Kernel hacking
790# 935#
791# CONFIG_PRINTK_TIME is not set 936# CONFIG_PRINTK_TIME is not set
792CONFIG_DEBUG_KERNEL=y 937CONFIG_ENABLE_WARN_DEPRECATED=y
938CONFIG_ENABLE_MUST_CHECK=y
793CONFIG_MAGIC_SYSRQ=y 939CONFIG_MAGIC_SYSRQ=y
794CONFIG_LOG_BUF_SHIFT=16 940# CONFIG_UNUSED_SYMBOLS is not set
795# CONFIG_SCHEDSTATS is not set
796# CONFIG_DEBUG_SLAB is not set
797# CONFIG_DEBUG_SPINLOCK is not set
798# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
799# CONFIG_DEBUG_KOBJECT is not set
800CONFIG_DEBUG_BUGVERBOSE=y
801# CONFIG_DEBUG_INFO is not set
802# CONFIG_DEBUG_FS is not set 941# CONFIG_DEBUG_FS is not set
803# CONFIG_FRAME_POINTER is not set 942# CONFIG_HEADERS_CHECK is not set
943# CONFIG_DEBUG_KERNEL is not set
944CONFIG_DEBUG_BUGVERBOSE=y
945# CONFIG_SAMPLES is not set
804 946
805# 947#
806# Security options 948# Security options
807# 949#
808# CONFIG_KEYS is not set 950# CONFIG_KEYS is not set
809# CONFIG_SECURITY is not set 951# CONFIG_SECURITY is not set
810 952# CONFIG_SECURITY_FILE_CAPABILITIES is not set
811# 953CONFIG_XOR_BLOCKS=m
812# Cryptographic options 954CONFIG_ASYNC_CORE=m
813# 955CONFIG_ASYNC_MEMCPY=m
956CONFIG_ASYNC_XOR=m
814CONFIG_CRYPTO=y 957CONFIG_CRYPTO=y
958CONFIG_CRYPTO_ALGAPI=y
959CONFIG_CRYPTO_AEAD=m
960CONFIG_CRYPTO_BLKCIPHER=y
961CONFIG_CRYPTO_SEQIV=m
962CONFIG_CRYPTO_HASH=y
963CONFIG_CRYPTO_MANAGER=y
815CONFIG_CRYPTO_HMAC=y 964CONFIG_CRYPTO_HMAC=y
965CONFIG_CRYPTO_XCBC=m
816CONFIG_CRYPTO_NULL=m 966CONFIG_CRYPTO_NULL=m
817CONFIG_CRYPTO_MD4=m 967CONFIG_CRYPTO_MD4=m
818CONFIG_CRYPTO_MD5=y 968CONFIG_CRYPTO_MD5=y
@@ -821,9 +971,21 @@ CONFIG_CRYPTO_SHA256=m
821CONFIG_CRYPTO_SHA512=m 971CONFIG_CRYPTO_SHA512=m
822CONFIG_CRYPTO_WP512=m 972CONFIG_CRYPTO_WP512=m
823CONFIG_CRYPTO_TGR192=m 973CONFIG_CRYPTO_TGR192=m
974CONFIG_CRYPTO_GF128MUL=m
975CONFIG_CRYPTO_ECB=m
976CONFIG_CRYPTO_CBC=y
977CONFIG_CRYPTO_PCBC=m
978CONFIG_CRYPTO_LRW=m
979CONFIG_CRYPTO_XTS=m
980CONFIG_CRYPTO_CTR=m
981CONFIG_CRYPTO_GCM=m
982CONFIG_CRYPTO_CCM=m
983CONFIG_CRYPTO_CRYPTD=m
824CONFIG_CRYPTO_DES=y 984CONFIG_CRYPTO_DES=y
985CONFIG_CRYPTO_FCRYPT=m
825CONFIG_CRYPTO_BLOWFISH=m 986CONFIG_CRYPTO_BLOWFISH=m
826CONFIG_CRYPTO_TWOFISH=m 987CONFIG_CRYPTO_TWOFISH=m
988CONFIG_CRYPTO_TWOFISH_COMMON=m
827CONFIG_CRYPTO_SERPENT=m 989CONFIG_CRYPTO_SERPENT=m
828CONFIG_CRYPTO_AES=m 990CONFIG_CRYPTO_AES=m
829CONFIG_CRYPTO_CAST5=m 991CONFIG_CRYPTO_CAST5=m
@@ -832,20 +994,35 @@ CONFIG_CRYPTO_TEA=m
832CONFIG_CRYPTO_ARC4=m 994CONFIG_CRYPTO_ARC4=m
833CONFIG_CRYPTO_KHAZAD=m 995CONFIG_CRYPTO_KHAZAD=m
834CONFIG_CRYPTO_ANUBIS=m 996CONFIG_CRYPTO_ANUBIS=m
997CONFIG_CRYPTO_SEED=m
998CONFIG_CRYPTO_SALSA20=m
835CONFIG_CRYPTO_DEFLATE=m 999CONFIG_CRYPTO_DEFLATE=m
836CONFIG_CRYPTO_MICHAEL_MIC=m 1000CONFIG_CRYPTO_MICHAEL_MIC=m
837CONFIG_CRYPTO_CRC32C=m 1001CONFIG_CRYPTO_CRC32C=m
1002CONFIG_CRYPTO_CAMELLIA=m
838CONFIG_CRYPTO_TEST=m 1003CONFIG_CRYPTO_TEST=m
839 1004CONFIG_CRYPTO_AUTHENC=m
840# 1005CONFIG_CRYPTO_LZO=m
841# Hardware crypto devices 1006# CONFIG_CRYPTO_HW is not set
842#
843 1007
844# 1008#
845# Library routines 1009# Library routines
846# 1010#
1011CONFIG_BITREVERSE=y
847CONFIG_CRC_CCITT=m 1012CONFIG_CRC_CCITT=m
1013CONFIG_CRC16=m
1014# CONFIG_CRC_ITU_T is not set
848CONFIG_CRC32=y 1015CONFIG_CRC32=y
1016# CONFIG_CRC7 is not set
849CONFIG_LIBCRC32C=m 1017CONFIG_LIBCRC32C=m
850CONFIG_ZLIB_INFLATE=y 1018CONFIG_ZLIB_INFLATE=y
851CONFIG_ZLIB_DEFLATE=m 1019CONFIG_ZLIB_DEFLATE=m
1020CONFIG_LZO_COMPRESS=m
1021CONFIG_LZO_DECOMPRESS=m
1022CONFIG_TEXTSEARCH=y
1023CONFIG_TEXTSEARCH_KMP=m
1024CONFIG_TEXTSEARCH_BM=m
1025CONFIG_TEXTSEARCH_FSM=m
1026CONFIG_PLIST=y
1027CONFIG_HAS_IOMEM=y
1028CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index ff9dffa5b86..738bca695a8 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:45 2005 4# Wed Apr 2 20:46:14 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-mac" 27CONFIG_LOCALVERSION="-mac"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -82,10 +130,24 @@ CONFIG_M68030=y
82CONFIG_M68040=y 130CONFIG_M68040=y
83# CONFIG_M68060 is not set 131# CONFIG_M68060 is not set
84CONFIG_MMU_MOTOROLA=y 132CONFIG_MMU_MOTOROLA=y
85CONFIG_M68KFPU_EMU=y 133# CONFIG_M68KFPU_EMU is not set
86CONFIG_M68KFPU_EMU_EXTRAPREC=y
87# CONFIG_M68KFPU_EMU_ONLY is not set
88# CONFIG_ADVANCED is not set 134# CONFIG_ADVANCED is not set
135CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
136CONFIG_NODES_SHIFT=3
137CONFIG_SELECT_MEMORY_MODEL=y
138# CONFIG_FLATMEM_MANUAL is not set
139CONFIG_DISCONTIGMEM_MANUAL=y
140# CONFIG_SPARSEMEM_MANUAL is not set
141CONFIG_DISCONTIGMEM=y
142CONFIG_FLAT_NODE_MEM_MAP=y
143CONFIG_NEED_MULTIPLE_NODES=y
144# CONFIG_SPARSEMEM_STATIC is not set
145# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
146CONFIG_SPLIT_PTLOCK_CPUS=4
147# CONFIG_RESOURCES_64BIT is not set
148CONFIG_ZONE_DMA_FLAG=1
149CONFIG_BOUNCE=y
150CONFIG_VIRT_TO_BUS=y
89 151
90# 152#
91# General setup 153# General setup
@@ -95,171 +157,11 @@ CONFIG_BINFMT_AOUT=m
95CONFIG_BINFMT_MISC=m 157CONFIG_BINFMT_MISC=m
96# CONFIG_HEARTBEAT is not set 158# CONFIG_HEARTBEAT is not set
97CONFIG_PROC_HARDWARE=y 159CONFIG_PROC_HARDWARE=y
160CONFIG_ZONE_DMA=y
161# CONFIG_ARCH_SUPPORTS_MSI is not set
98 162
99# 163#
100# Device Drivers 164# Networking
101#
102
103#
104# Generic Driver Options
105#
106CONFIG_STANDALONE=y
107CONFIG_PREVENT_FIRMWARE_BUILD=y
108CONFIG_FW_LOADER=m
109# CONFIG_DEBUG_DRIVER is not set
110
111#
112# Memory Technology Devices (MTD)
113#
114# CONFIG_MTD is not set
115
116#
117# Parallel port support
118#
119# CONFIG_PARPORT is not set
120
121#
122# Plug and Play support
123#
124
125#
126# Block devices
127#
128# CONFIG_BLK_DEV_COW_COMMON is not set
129CONFIG_BLK_DEV_LOOP=y
130CONFIG_BLK_DEV_CRYPTOLOOP=m
131CONFIG_BLK_DEV_NBD=m
132CONFIG_BLK_DEV_RAM=y
133CONFIG_BLK_DEV_RAM_COUNT=16
134CONFIG_BLK_DEV_RAM_SIZE=4096
135CONFIG_BLK_DEV_INITRD=y
136CONFIG_INITRAMFS_SOURCE=""
137CONFIG_CDROM_PKTCDVD=m
138CONFIG_CDROM_PKTCDVD_BUFFERS=8
139# CONFIG_CDROM_PKTCDVD_WCACHE is not set
140
141#
142# IO Schedulers
143#
144CONFIG_IOSCHED_NOOP=y
145CONFIG_IOSCHED_AS=y
146CONFIG_IOSCHED_DEADLINE=y
147CONFIG_IOSCHED_CFQ=y
148CONFIG_ATA_OVER_ETH=m
149
150#
151# ATA/ATAPI/MFM/RLL support
152#
153CONFIG_IDE=y
154CONFIG_BLK_DEV_IDE=y
155
156#
157# Please see Documentation/ide.txt for help/info on IDE drives
158#
159# CONFIG_BLK_DEV_IDE_SATA is not set
160CONFIG_BLK_DEV_IDEDISK=y
161# CONFIG_IDEDISK_MULTI_MODE is not set
162CONFIG_BLK_DEV_IDECD=y
163CONFIG_BLK_DEV_IDETAPE=m
164CONFIG_BLK_DEV_IDEFLOPPY=m
165# CONFIG_BLK_DEV_IDESCSI is not set
166# CONFIG_IDE_TASK_IOCTL is not set
167
168#
169# IDE chipset support/bugfixes
170#
171CONFIG_IDE_GENERIC=y
172# CONFIG_IDE_ARM is not set
173CONFIG_BLK_DEV_MAC_IDE=y
174# CONFIG_BLK_DEV_IDEDMA is not set
175# CONFIG_IDEDMA_AUTO is not set
176# CONFIG_BLK_DEV_HD is not set
177
178#
179# SCSI device support
180#
181CONFIG_SCSI=y
182CONFIG_SCSI_PROC_FS=y
183
184#
185# SCSI support type (disk, tape, CD-ROM)
186#
187CONFIG_BLK_DEV_SD=y
188CONFIG_CHR_DEV_ST=m
189CONFIG_CHR_DEV_OSST=m
190CONFIG_BLK_DEV_SR=y
191CONFIG_BLK_DEV_SR_VENDOR=y
192CONFIG_CHR_DEV_SG=m
193
194#
195# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
196#
197# CONFIG_SCSI_MULTI_LUN is not set
198CONFIG_SCSI_CONSTANTS=y
199# CONFIG_SCSI_LOGGING is not set
200
201#
202# SCSI Transport Attributes
203#
204# CONFIG_SCSI_SPI_ATTRS is not set
205# CONFIG_SCSI_FC_ATTRS is not set
206# CONFIG_SCSI_ISCSI_ATTRS is not set
207
208#
209# SCSI low-level drivers
210#
211# CONFIG_SCSI_SATA is not set
212# CONFIG_SCSI_DEBUG is not set
213CONFIG_MAC_SCSI=y
214CONFIG_SCSI_MAC_ESP=y
215
216#
217# Multi-device support (RAID and LVM)
218#
219CONFIG_MD=y
220CONFIG_BLK_DEV_MD=m
221CONFIG_MD_LINEAR=m
222CONFIG_MD_RAID0=m
223CONFIG_MD_RAID1=m
224# CONFIG_MD_RAID10 is not set
225CONFIG_MD_RAID5=m
226CONFIG_MD_RAID6=m
227CONFIG_MD_MULTIPATH=m
228# CONFIG_MD_FAULTY is not set
229CONFIG_BLK_DEV_DM=m
230CONFIG_DM_CRYPT=m
231CONFIG_DM_SNAPSHOT=m
232CONFIG_DM_MIRROR=m
233CONFIG_DM_ZERO=m
234CONFIG_DM_MULTIPATH=m
235CONFIG_DM_MULTIPATH_EMC=m
236
237#
238# Fusion MPT device support
239#
240
241#
242# IEEE 1394 (FireWire) support
243#
244
245#
246# I2O device support
247#
248
249#
250# Macintosh device drivers
251#
252CONFIG_ADB=y
253CONFIG_ADB_MACII=y
254CONFIG_ADB_MACIISI=y
255CONFIG_ADB_IOP=y
256CONFIG_ADB_PMU68K=y
257CONFIG_ADB_CUDA=y
258CONFIG_INPUT_ADBHID=y
259CONFIG_MAC_EMUMOUSEBTN=y
260
261#
262# Networking support
263# 165#
264CONFIG_NET=y 166CONFIG_NET=y
265 167
@@ -269,10 +171,17 @@ CONFIG_NET=y
269CONFIG_PACKET=y 171CONFIG_PACKET=y
270# CONFIG_PACKET_MMAP is not set 172# CONFIG_PACKET_MMAP is not set
271CONFIG_UNIX=y 173CONFIG_UNIX=y
174CONFIG_XFRM=y
175# CONFIG_XFRM_USER is not set
176# CONFIG_XFRM_SUB_POLICY is not set
177CONFIG_XFRM_MIGRATE=y
178# CONFIG_XFRM_STATISTICS is not set
272CONFIG_NET_KEY=y 179CONFIG_NET_KEY=y
180CONFIG_NET_KEY_MIGRATE=y
273CONFIG_INET=y 181CONFIG_INET=y
274# CONFIG_IP_MULTICAST is not set 182# CONFIG_IP_MULTICAST is not set
275# CONFIG_IP_ADVANCED_ROUTER is not set 183# CONFIG_IP_ADVANCED_ROUTER is not set
184CONFIG_IP_FIB_HASH=y
276# CONFIG_IP_PNP is not set 185# CONFIG_IP_PNP is not set
277CONFIG_NET_IPIP=m 186CONFIG_NET_IPIP=m
278CONFIG_NET_IPGRE=m 187CONFIG_NET_IPGRE=m
@@ -281,148 +190,202 @@ CONFIG_SYN_COOKIES=y
281CONFIG_INET_AH=m 190CONFIG_INET_AH=m
282CONFIG_INET_ESP=m 191CONFIG_INET_ESP=m
283CONFIG_INET_IPCOMP=m 192CONFIG_INET_IPCOMP=m
193CONFIG_INET_XFRM_TUNNEL=m
284CONFIG_INET_TUNNEL=m 194CONFIG_INET_TUNNEL=m
285CONFIG_IP_TCPDIAG=m 195CONFIG_INET_XFRM_MODE_TRANSPORT=m
286CONFIG_IP_TCPDIAG_IPV6=y 196CONFIG_INET_XFRM_MODE_TUNNEL=m
287 197CONFIG_INET_XFRM_MODE_BEET=m
288# 198CONFIG_INET_LRO=m
289# IP: Virtual Server Configuration 199CONFIG_INET_DIAG=m
290# 200CONFIG_INET_TCP_DIAG=m
201# CONFIG_TCP_CONG_ADVANCED is not set
202CONFIG_TCP_CONG_CUBIC=y
203CONFIG_DEFAULT_TCP_CONG="cubic"
204# CONFIG_TCP_MD5SIG is not set
291# CONFIG_IP_VS is not set 205# CONFIG_IP_VS is not set
292CONFIG_IPV6=m 206CONFIG_IPV6=m
293CONFIG_IPV6_PRIVACY=y 207CONFIG_IPV6_PRIVACY=y
208CONFIG_IPV6_ROUTER_PREF=y
209CONFIG_IPV6_ROUTE_INFO=y
210# CONFIG_IPV6_OPTIMISTIC_DAD is not set
294CONFIG_INET6_AH=m 211CONFIG_INET6_AH=m
295CONFIG_INET6_ESP=m 212CONFIG_INET6_ESP=m
296CONFIG_INET6_IPCOMP=m 213CONFIG_INET6_IPCOMP=m
214# CONFIG_IPV6_MIP6 is not set
215CONFIG_INET6_XFRM_TUNNEL=m
297CONFIG_INET6_TUNNEL=m 216CONFIG_INET6_TUNNEL=m
217CONFIG_INET6_XFRM_MODE_TRANSPORT=m
218CONFIG_INET6_XFRM_MODE_TUNNEL=m
219CONFIG_INET6_XFRM_MODE_BEET=m
220CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
221CONFIG_IPV6_SIT=m
298CONFIG_IPV6_TUNNEL=m 222CONFIG_IPV6_TUNNEL=m
223# CONFIG_IPV6_MULTIPLE_TABLES is not set
224# CONFIG_NETWORK_SECMARK is not set
299CONFIG_NETFILTER=y 225CONFIG_NETFILTER=y
300# CONFIG_NETFILTER_DEBUG is not set 226# CONFIG_NETFILTER_DEBUG is not set
227CONFIG_NETFILTER_ADVANCED=y
228
229#
230# Core Netfilter Configuration
231#
232CONFIG_NETFILTER_NETLINK=m
233CONFIG_NETFILTER_NETLINK_QUEUE=m
234CONFIG_NETFILTER_NETLINK_LOG=m
235CONFIG_NF_CONNTRACK=m
236CONFIG_NF_CT_ACCT=y
237CONFIG_NF_CONNTRACK_MARK=y
238# CONFIG_NF_CONNTRACK_EVENTS is not set
239CONFIG_NF_CT_PROTO_GRE=m
240CONFIG_NF_CT_PROTO_SCTP=m
241CONFIG_NF_CT_PROTO_UDPLITE=m
242CONFIG_NF_CONNTRACK_AMANDA=m
243CONFIG_NF_CONNTRACK_FTP=m
244CONFIG_NF_CONNTRACK_H323=m
245CONFIG_NF_CONNTRACK_IRC=m
246CONFIG_NF_CONNTRACK_NETBIOS_NS=m
247CONFIG_NF_CONNTRACK_PPTP=m
248CONFIG_NF_CONNTRACK_SANE=m
249CONFIG_NF_CONNTRACK_SIP=m
250CONFIG_NF_CONNTRACK_TFTP=m
251# CONFIG_NF_CT_NETLINK is not set
252CONFIG_NETFILTER_XTABLES=m
253CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
254CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
255CONFIG_NETFILTER_XT_TARGET_DSCP=m
256CONFIG_NETFILTER_XT_TARGET_MARK=m
257CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
258CONFIG_NETFILTER_XT_TARGET_NFLOG=m
259CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
260CONFIG_NETFILTER_XT_TARGET_RATEEST=m
261CONFIG_NETFILTER_XT_TARGET_TRACE=m
262CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
263CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
264CONFIG_NETFILTER_XT_MATCH_COMMENT=m
265CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
266CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
267CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
268CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
269CONFIG_NETFILTER_XT_MATCH_DCCP=m
270CONFIG_NETFILTER_XT_MATCH_DSCP=m
271CONFIG_NETFILTER_XT_MATCH_ESP=m
272CONFIG_NETFILTER_XT_MATCH_HELPER=m
273CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
274CONFIG_NETFILTER_XT_MATCH_LENGTH=m
275CONFIG_NETFILTER_XT_MATCH_LIMIT=m
276CONFIG_NETFILTER_XT_MATCH_MAC=m
277CONFIG_NETFILTER_XT_MATCH_MARK=m
278CONFIG_NETFILTER_XT_MATCH_OWNER=m
279CONFIG_NETFILTER_XT_MATCH_POLICY=m
280CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
281CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
282CONFIG_NETFILTER_XT_MATCH_QUOTA=m
283CONFIG_NETFILTER_XT_MATCH_RATEEST=m
284CONFIG_NETFILTER_XT_MATCH_REALM=m
285CONFIG_NETFILTER_XT_MATCH_SCTP=m
286CONFIG_NETFILTER_XT_MATCH_STATE=m
287CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
288CONFIG_NETFILTER_XT_MATCH_STRING=m
289CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
290CONFIG_NETFILTER_XT_MATCH_TIME=m
291CONFIG_NETFILTER_XT_MATCH_U32=m
292CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
301 293
302# 294#
303# IP: Netfilter Configuration 295# IP: Netfilter Configuration
304# 296#
305CONFIG_IP_NF_CONNTRACK=m 297CONFIG_NF_CONNTRACK_IPV4=m
306# CONFIG_IP_NF_CT_ACCT is not set 298CONFIG_NF_CONNTRACK_PROC_COMPAT=y
307CONFIG_IP_NF_CONNTRACK_MARK=y
308# CONFIG_IP_NF_CT_PROTO_SCTP is not set
309CONFIG_IP_NF_FTP=m
310CONFIG_IP_NF_IRC=m
311CONFIG_IP_NF_TFTP=m
312CONFIG_IP_NF_AMANDA=m
313CONFIG_IP_NF_QUEUE=m 299CONFIG_IP_NF_QUEUE=m
314CONFIG_IP_NF_IPTABLES=m 300CONFIG_IP_NF_IPTABLES=m
315CONFIG_IP_NF_MATCH_LIMIT=m
316CONFIG_IP_NF_MATCH_IPRANGE=m
317CONFIG_IP_NF_MATCH_MAC=m
318CONFIG_IP_NF_MATCH_PKTTYPE=m
319CONFIG_IP_NF_MATCH_MARK=m
320CONFIG_IP_NF_MATCH_MULTIPORT=m
321CONFIG_IP_NF_MATCH_TOS=m
322CONFIG_IP_NF_MATCH_RECENT=m 301CONFIG_IP_NF_MATCH_RECENT=m
323CONFIG_IP_NF_MATCH_ECN=m 302CONFIG_IP_NF_MATCH_ECN=m
324CONFIG_IP_NF_MATCH_DSCP=m 303CONFIG_IP_NF_MATCH_AH=m
325CONFIG_IP_NF_MATCH_AH_ESP=m
326CONFIG_IP_NF_MATCH_LENGTH=m
327CONFIG_IP_NF_MATCH_TTL=m 304CONFIG_IP_NF_MATCH_TTL=m
328CONFIG_IP_NF_MATCH_TCPMSS=m
329CONFIG_IP_NF_MATCH_HELPER=m
330CONFIG_IP_NF_MATCH_STATE=m
331CONFIG_IP_NF_MATCH_CONNTRACK=m
332CONFIG_IP_NF_MATCH_OWNER=m
333CONFIG_IP_NF_MATCH_ADDRTYPE=m 305CONFIG_IP_NF_MATCH_ADDRTYPE=m
334CONFIG_IP_NF_MATCH_REALM=m
335# CONFIG_IP_NF_MATCH_SCTP is not set
336# CONFIG_IP_NF_MATCH_COMMENT is not set
337CONFIG_IP_NF_MATCH_CONNMARK=m
338CONFIG_IP_NF_MATCH_HASHLIMIT=m
339CONFIG_IP_NF_FILTER=m 306CONFIG_IP_NF_FILTER=m
340CONFIG_IP_NF_TARGET_REJECT=m 307CONFIG_IP_NF_TARGET_REJECT=m
341CONFIG_IP_NF_TARGET_LOG=m 308CONFIG_IP_NF_TARGET_LOG=m
342CONFIG_IP_NF_TARGET_ULOG=m 309CONFIG_IP_NF_TARGET_ULOG=m
343CONFIG_IP_NF_TARGET_TCPMSS=m 310CONFIG_NF_NAT=m
344CONFIG_IP_NF_NAT=m 311CONFIG_NF_NAT_NEEDED=y
345CONFIG_IP_NF_NAT_NEEDED=y
346CONFIG_IP_NF_TARGET_MASQUERADE=m 312CONFIG_IP_NF_TARGET_MASQUERADE=m
347CONFIG_IP_NF_TARGET_REDIRECT=m 313CONFIG_IP_NF_TARGET_REDIRECT=m
348CONFIG_IP_NF_TARGET_NETMAP=m 314CONFIG_IP_NF_TARGET_NETMAP=m
349CONFIG_IP_NF_TARGET_SAME=m 315CONFIG_NF_NAT_SNMP_BASIC=m
350CONFIG_IP_NF_NAT_SNMP_BASIC=m 316CONFIG_NF_NAT_PROTO_GRE=m
351CONFIG_IP_NF_NAT_IRC=m 317CONFIG_NF_NAT_FTP=m
352CONFIG_IP_NF_NAT_FTP=m 318CONFIG_NF_NAT_IRC=m
353CONFIG_IP_NF_NAT_TFTP=m 319CONFIG_NF_NAT_TFTP=m
354CONFIG_IP_NF_NAT_AMANDA=m 320CONFIG_NF_NAT_AMANDA=m
321CONFIG_NF_NAT_PPTP=m
322CONFIG_NF_NAT_H323=m
323CONFIG_NF_NAT_SIP=m
355CONFIG_IP_NF_MANGLE=m 324CONFIG_IP_NF_MANGLE=m
356CONFIG_IP_NF_TARGET_TOS=m
357CONFIG_IP_NF_TARGET_ECN=m 325CONFIG_IP_NF_TARGET_ECN=m
358CONFIG_IP_NF_TARGET_DSCP=m 326CONFIG_IP_NF_TARGET_TTL=m
359CONFIG_IP_NF_TARGET_MARK=m 327CONFIG_IP_NF_TARGET_CLUSTERIP=m
360CONFIG_IP_NF_TARGET_CLASSIFY=m
361CONFIG_IP_NF_TARGET_CONNMARK=m
362# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
363CONFIG_IP_NF_RAW=m 328CONFIG_IP_NF_RAW=m
364CONFIG_IP_NF_TARGET_NOTRACK=m
365CONFIG_IP_NF_ARPTABLES=m 329CONFIG_IP_NF_ARPTABLES=m
366CONFIG_IP_NF_ARPFILTER=m 330CONFIG_IP_NF_ARPFILTER=m
367CONFIG_IP_NF_ARP_MANGLE=m 331CONFIG_IP_NF_ARP_MANGLE=m
368 332
369# 333#
370# IPv6: Netfilter Configuration (EXPERIMENTAL) 334# IPv6: Netfilter Configuration
371# 335#
336CONFIG_NF_CONNTRACK_IPV6=m
372CONFIG_IP6_NF_QUEUE=m 337CONFIG_IP6_NF_QUEUE=m
373CONFIG_IP6_NF_IPTABLES=m 338CONFIG_IP6_NF_IPTABLES=m
374CONFIG_IP6_NF_MATCH_LIMIT=m
375CONFIG_IP6_NF_MATCH_MAC=m
376CONFIG_IP6_NF_MATCH_RT=m 339CONFIG_IP6_NF_MATCH_RT=m
377CONFIG_IP6_NF_MATCH_OPTS=m 340CONFIG_IP6_NF_MATCH_OPTS=m
378CONFIG_IP6_NF_MATCH_FRAG=m 341CONFIG_IP6_NF_MATCH_FRAG=m
379CONFIG_IP6_NF_MATCH_HL=m 342CONFIG_IP6_NF_MATCH_HL=m
380CONFIG_IP6_NF_MATCH_MULTIPORT=m
381CONFIG_IP6_NF_MATCH_OWNER=m
382CONFIG_IP6_NF_MATCH_MARK=m
383CONFIG_IP6_NF_MATCH_IPV6HEADER=m 343CONFIG_IP6_NF_MATCH_IPV6HEADER=m
384CONFIG_IP6_NF_MATCH_AHESP=m 344CONFIG_IP6_NF_MATCH_AH=m
385CONFIG_IP6_NF_MATCH_LENGTH=m 345CONFIG_IP6_NF_MATCH_MH=m
386CONFIG_IP6_NF_MATCH_EUI64=m 346CONFIG_IP6_NF_MATCH_EUI64=m
387CONFIG_IP6_NF_FILTER=m 347CONFIG_IP6_NF_FILTER=m
388CONFIG_IP6_NF_TARGET_LOG=m 348CONFIG_IP6_NF_TARGET_LOG=m
349CONFIG_IP6_NF_TARGET_REJECT=m
389CONFIG_IP6_NF_MANGLE=m 350CONFIG_IP6_NF_MANGLE=m
390CONFIG_IP6_NF_TARGET_MARK=m 351CONFIG_IP6_NF_TARGET_HL=m
391CONFIG_IP6_NF_RAW=m 352CONFIG_IP6_NF_RAW=m
392CONFIG_XFRM=y 353CONFIG_IP_DCCP=m
393CONFIG_XFRM_USER=m 354CONFIG_INET_DCCP_DIAG=m
355CONFIG_IP_DCCP_ACKVEC=y
394 356
395# 357#
396# SCTP Configuration (EXPERIMENTAL) 358# DCCP CCIDs Configuration (EXPERIMENTAL)
397# 359#
360CONFIG_IP_DCCP_CCID2=m
361# CONFIG_IP_DCCP_CCID2_DEBUG is not set
362CONFIG_IP_DCCP_CCID3=m
363# CONFIG_IP_DCCP_CCID3_DEBUG is not set
364CONFIG_IP_DCCP_CCID3_RTO=100
365CONFIG_IP_DCCP_TFRC_LIB=m
398CONFIG_IP_SCTP=m 366CONFIG_IP_SCTP=m
399# CONFIG_SCTP_DBG_MSG is not set 367# CONFIG_SCTP_DBG_MSG is not set
400# CONFIG_SCTP_DBG_OBJCNT is not set 368# CONFIG_SCTP_DBG_OBJCNT is not set
401# CONFIG_SCTP_HMAC_NONE is not set 369# CONFIG_SCTP_HMAC_NONE is not set
402# CONFIG_SCTP_HMAC_SHA1 is not set 370# CONFIG_SCTP_HMAC_SHA1 is not set
403CONFIG_SCTP_HMAC_MD5=y 371CONFIG_SCTP_HMAC_MD5=y
372# CONFIG_TIPC is not set
404# CONFIG_ATM is not set 373# CONFIG_ATM is not set
405# CONFIG_BRIDGE is not set 374# CONFIG_BRIDGE is not set
406# CONFIG_VLAN_8021Q is not set 375# CONFIG_VLAN_8021Q is not set
407# CONFIG_DECNET is not set 376# CONFIG_DECNET is not set
408CONFIG_LLC=m 377CONFIG_LLC=m
409# CONFIG_LLC2 is not set 378# CONFIG_LLC2 is not set
410CONFIG_IPX=m 379# CONFIG_IPX is not set
411# CONFIG_IPX_INTERN is not set
412CONFIG_ATALK=m 380CONFIG_ATALK=m
413CONFIG_DEV_APPLETALK=y 381CONFIG_DEV_APPLETALK=m
414CONFIG_IPDDP=m 382CONFIG_IPDDP=m
415CONFIG_IPDDP_ENCAP=y 383CONFIG_IPDDP_ENCAP=y
416CONFIG_IPDDP_DECAP=y 384CONFIG_IPDDP_DECAP=y
417# CONFIG_X25 is not set 385# CONFIG_X25 is not set
418# CONFIG_LAPB is not set 386# CONFIG_LAPB is not set
419# CONFIG_NET_DIVERT is not set
420# CONFIG_ECONET is not set 387# CONFIG_ECONET is not set
421# CONFIG_WAN_ROUTER is not set 388# CONFIG_WAN_ROUTER is not set
422
423#
424# QoS and/or fair queueing
425#
426# CONFIG_NET_SCHED is not set 389# CONFIG_NET_SCHED is not set
427CONFIG_NET_CLS_ROUTE=y 390CONFIG_NET_CLS_ROUTE=y
428 391
@@ -430,80 +393,223 @@ CONFIG_NET_CLS_ROUTE=y
430# Network testing 393# Network testing
431# 394#
432# CONFIG_NET_PKTGEN is not set 395# CONFIG_NET_PKTGEN is not set
433CONFIG_NETPOLL=y
434# CONFIG_NETPOLL_RX is not set
435# CONFIG_NETPOLL_TRAP is not set
436CONFIG_NET_POLL_CONTROLLER=y
437# CONFIG_HAMRADIO is not set 396# CONFIG_HAMRADIO is not set
397# CONFIG_CAN is not set
438# CONFIG_IRDA is not set 398# CONFIG_IRDA is not set
439# CONFIG_BT is not set 399# CONFIG_BT is not set
440CONFIG_NETDEVICES=y 400# CONFIG_AF_RXRPC is not set
441CONFIG_DUMMY=m
442# CONFIG_BONDING is not set
443CONFIG_EQUALIZER=m
444# CONFIG_TUN is not set
445 401
446# 402#
447# Ethernet (10 or 100Mbit) 403# Wireless
448# 404#
449CONFIG_NET_ETHERNET=y 405# CONFIG_CFG80211 is not set
450# CONFIG_MII is not set 406CONFIG_WIRELESS_EXT=y
451CONFIG_MAC8390=y 407# CONFIG_MAC80211 is not set
452CONFIG_MAC89x0=y 408CONFIG_IEEE80211=m
453CONFIG_MACSONIC=y 409# CONFIG_IEEE80211_DEBUG is not set
454CONFIG_MACMACE=y 410CONFIG_IEEE80211_CRYPT_WEP=m
455# CONFIG_NET_VENDOR_SMC is not set 411CONFIG_IEEE80211_CRYPT_CCMP=m
412CONFIG_IEEE80211_CRYPT_TKIP=m
413CONFIG_IEEE80211_SOFTMAC=m
414# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
415# CONFIG_RFKILL is not set
416# CONFIG_NET_9P is not set
417
418#
419# Device Drivers
420#
421
422#
423# Generic Driver Options
424#
425CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430CONFIG_CONNECTOR=m
431# CONFIG_MTD is not set
432# CONFIG_PARPORT is not set
433CONFIG_BLK_DEV=y
434# CONFIG_BLK_DEV_COW_COMMON is not set
435CONFIG_BLK_DEV_LOOP=y
436CONFIG_BLK_DEV_CRYPTOLOOP=m
437CONFIG_BLK_DEV_NBD=m
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=16
440CONFIG_BLK_DEV_RAM_SIZE=4096
441# CONFIG_BLK_DEV_XIP is not set
442CONFIG_CDROM_PKTCDVD=m
443CONFIG_CDROM_PKTCDVD_BUFFERS=8
444# CONFIG_CDROM_PKTCDVD_WCACHE is not set
445CONFIG_ATA_OVER_ETH=m
446CONFIG_MISC_DEVICES=y
447# CONFIG_EEPROM_93CX6 is not set
448# CONFIG_ENCLOSURE_SERVICES is not set
449CONFIG_HAVE_IDE=y
450CONFIG_IDE=y
451CONFIG_BLK_DEV_IDE=y
456 452
457# 453#
458# Ethernet (1000 Mbit) 454# Please see Documentation/ide/ide.txt for help/info on IDE drives
455#
456# CONFIG_BLK_DEV_IDE_SATA is not set
457CONFIG_BLK_DEV_IDEDISK=y
458# CONFIG_IDEDISK_MULTI_MODE is not set
459CONFIG_BLK_DEV_IDECD=y
460CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
461# CONFIG_BLK_DEV_IDETAPE is not set
462CONFIG_BLK_DEV_IDEFLOPPY=m
463# CONFIG_BLK_DEV_IDESCSI is not set
464# CONFIG_IDE_TASK_IOCTL is not set
465CONFIG_IDE_PROC_FS=y
466
467#
468# IDE chipset support/bugfixes
459# 469#
470# CONFIG_IDE_GENERIC is not set
471# CONFIG_BLK_DEV_PLATFORM is not set
472CONFIG_BLK_DEV_MAC_IDE=y
473# CONFIG_BLK_DEV_IDEDMA is not set
474# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
475# CONFIG_BLK_DEV_HD is not set
460 476
461# 477#
462# Ethernet (10000 Mbit) 478# SCSI device support
463# 479#
480CONFIG_RAID_ATTRS=m
481CONFIG_SCSI=y
482CONFIG_SCSI_DMA=y
483CONFIG_SCSI_TGT=m
484# CONFIG_SCSI_NETLINK is not set
485CONFIG_SCSI_PROC_FS=y
464 486
465# 487#
466# Token Ring devices 488# SCSI support type (disk, tape, CD-ROM)
467# 489#
490CONFIG_BLK_DEV_SD=y
491CONFIG_CHR_DEV_ST=m
492CONFIG_CHR_DEV_OSST=m
493CONFIG_BLK_DEV_SR=y
494CONFIG_BLK_DEV_SR_VENDOR=y
495CONFIG_CHR_DEV_SG=m
496# CONFIG_CHR_DEV_SCH is not set
468 497
469# 498#
470# Wireless LAN (non-hamradio) 499# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
471# 500#
472# CONFIG_NET_RADIO is not set 501# CONFIG_SCSI_MULTI_LUN is not set
502CONFIG_SCSI_CONSTANTS=y
503# CONFIG_SCSI_LOGGING is not set
504# CONFIG_SCSI_SCAN_ASYNC is not set
505CONFIG_SCSI_WAIT_SCAN=m
473 506
474# 507#
475# Wan interfaces 508# SCSI Transports
476# 509#
510CONFIG_SCSI_SPI_ATTRS=y
511# CONFIG_SCSI_FC_ATTRS is not set
512CONFIG_SCSI_ISCSI_ATTRS=m
513CONFIG_SCSI_SAS_ATTRS=m
514CONFIG_SCSI_SAS_LIBSAS=m
515CONFIG_SCSI_SAS_HOST_SMP=y
516# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
517CONFIG_SCSI_SRP_ATTRS=m
518CONFIG_SCSI_SRP_TGT_ATTRS=y
519CONFIG_SCSI_LOWLEVEL=y
520CONFIG_ISCSI_TCP=m
521# CONFIG_SCSI_DEBUG is not set
522CONFIG_MAC_SCSI=y
523CONFIG_MD=y
524CONFIG_BLK_DEV_MD=m
525CONFIG_MD_LINEAR=m
526CONFIG_MD_RAID0=m
527CONFIG_MD_RAID1=m
528# CONFIG_MD_RAID10 is not set
529CONFIG_MD_RAID456=m
530CONFIG_MD_RAID5_RESHAPE=y
531CONFIG_MD_MULTIPATH=m
532# CONFIG_MD_FAULTY is not set
533CONFIG_BLK_DEV_DM=m
534# CONFIG_DM_DEBUG is not set
535CONFIG_DM_CRYPT=m
536CONFIG_DM_SNAPSHOT=m
537CONFIG_DM_MIRROR=m
538CONFIG_DM_ZERO=m
539CONFIG_DM_MULTIPATH=m
540CONFIG_DM_MULTIPATH_EMC=m
541CONFIG_DM_MULTIPATH_RDAC=m
542CONFIG_DM_MULTIPATH_HP=m
543# CONFIG_DM_DELAY is not set
544CONFIG_DM_UEVENT=y
545CONFIG_MACINTOSH_DRIVERS=y
546CONFIG_ADB=y
547CONFIG_ADB_MACII=y
548CONFIG_ADB_MACIISI=y
549CONFIG_ADB_IOP=y
550CONFIG_ADB_PMU68K=y
551CONFIG_ADB_CUDA=y
552CONFIG_INPUT_ADBHID=y
553CONFIG_MAC_EMUMOUSEBTN=y
554CONFIG_NETDEVICES=y
555# CONFIG_NETDEVICES_MULTIQUEUE is not set
556CONFIG_DUMMY=m
557# CONFIG_BONDING is not set
558CONFIG_MACVLAN=m
559CONFIG_EQUALIZER=m
560# CONFIG_TUN is not set
561CONFIG_VETH=m
562# CONFIG_PHYLIB is not set
563CONFIG_NET_ETHERNET=y
564# CONFIG_MII is not set
565CONFIG_MAC8390=y
566CONFIG_MAC89x0=m
567CONFIG_MACSONIC=m
568CONFIG_MACMACE=y
569# CONFIG_NET_VENDOR_SMC is not set
570# CONFIG_IBM_NEW_EMAC_ZMII is not set
571# CONFIG_IBM_NEW_EMAC_RGMII is not set
572# CONFIG_IBM_NEW_EMAC_TAH is not set
573# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
574# CONFIG_B44 is not set
575# CONFIG_NETDEV_1000 is not set
576# CONFIG_NETDEV_10000 is not set
577
578#
579# Wireless LAN
580#
581# CONFIG_WLAN_PRE80211 is not set
582# CONFIG_WLAN_80211 is not set
477# CONFIG_WAN is not set 583# CONFIG_WAN is not set
478CONFIG_PPP=m 584CONFIG_PPP=m
479# CONFIG_PPP_MULTILINK is not set 585# CONFIG_PPP_MULTILINK is not set
480CONFIG_PPP_FILTER=y 586CONFIG_PPP_FILTER=y
481# CONFIG_PPP_ASYNC is not set 587CONFIG_PPP_ASYNC=m
482# CONFIG_PPP_SYNC_TTY is not set 588CONFIG_PPP_SYNC_TTY=m
483CONFIG_PPP_DEFLATE=m 589CONFIG_PPP_DEFLATE=m
484CONFIG_PPP_BSDCOMP=m 590CONFIG_PPP_BSDCOMP=m
591CONFIG_PPP_MPPE=m
485CONFIG_PPPOE=m 592CONFIG_PPPOE=m
593CONFIG_PPPOL2TP=m
486CONFIG_SLIP=m 594CONFIG_SLIP=m
487CONFIG_SLIP_COMPRESSED=y 595CONFIG_SLIP_COMPRESSED=y
596CONFIG_SLHC=m
488CONFIG_SLIP_SMART=y 597CONFIG_SLIP_SMART=y
489CONFIG_SLIP_MODE_SLIP6=y 598CONFIG_SLIP_MODE_SLIP6=y
490CONFIG_SHAPER=m
491CONFIG_NETCONSOLE=m 599CONFIG_NETCONSOLE=m
492 600CONFIG_NETCONSOLE_DYNAMIC=y
493# 601CONFIG_NETPOLL=y
494# ISDN subsystem 602# CONFIG_NETPOLL_TRAP is not set
495# 603CONFIG_NET_POLL_CONTROLLER=y
496# CONFIG_ISDN is not set 604# CONFIG_ISDN is not set
497
498#
499# Telephony Support
500#
501# CONFIG_PHONE is not set 605# CONFIG_PHONE is not set
502 606
503# 607#
504# Input device support 608# Input device support
505# 609#
506CONFIG_INPUT=y 610CONFIG_INPUT=y
611CONFIG_INPUT_FF_MEMLESS=m
612# CONFIG_INPUT_POLLDEV is not set
507 613
508# 614#
509# Userland interfaces 615# Userland interfaces
@@ -513,7 +619,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
513CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 619CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
514CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 620CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
515# CONFIG_INPUT_JOYDEV is not set 621# CONFIG_INPUT_JOYDEV is not set
516# CONFIG_INPUT_TSDEV is not set
517# CONFIG_INPUT_EVDEV is not set 622# CONFIG_INPUT_EVDEV is not set
518# CONFIG_INPUT_EVBUG is not set 623# CONFIG_INPUT_EVBUG is not set
519 624
@@ -526,19 +631,29 @@ CONFIG_INPUT_KEYBOARD=y
526# CONFIG_KEYBOARD_LKKBD is not set 631# CONFIG_KEYBOARD_LKKBD is not set
527# CONFIG_KEYBOARD_XTKBD is not set 632# CONFIG_KEYBOARD_XTKBD is not set
528# CONFIG_KEYBOARD_NEWTON is not set 633# CONFIG_KEYBOARD_NEWTON is not set
634# CONFIG_KEYBOARD_STOWAWAY is not set
529CONFIG_INPUT_MOUSE=y 635CONFIG_INPUT_MOUSE=y
530CONFIG_MOUSE_PS2=m 636CONFIG_MOUSE_PS2=m
637CONFIG_MOUSE_PS2_ALPS=y
638CONFIG_MOUSE_PS2_LOGIPS2PP=y
639CONFIG_MOUSE_PS2_SYNAPTICS=y
640CONFIG_MOUSE_PS2_LIFEBOOK=y
641CONFIG_MOUSE_PS2_TRACKPOINT=y
642# CONFIG_MOUSE_PS2_TOUCHKIT is not set
531CONFIG_MOUSE_SERIAL=m 643CONFIG_MOUSE_SERIAL=m
532# CONFIG_MOUSE_VSXXXAA is not set 644# CONFIG_MOUSE_VSXXXAA is not set
533# CONFIG_INPUT_JOYSTICK is not set 645# CONFIG_INPUT_JOYSTICK is not set
646# CONFIG_INPUT_TABLET is not set
534# CONFIG_INPUT_TOUCHSCREEN is not set 647# CONFIG_INPUT_TOUCHSCREEN is not set
535# CONFIG_INPUT_MISC is not set 648CONFIG_INPUT_MISC=y
649CONFIG_INPUT_M68K_BEEP=m
650# CONFIG_INPUT_UINPUT is not set
536 651
537# 652#
538# Hardware I/O ports 653# Hardware I/O ports
539# 654#
540CONFIG_SERIO=m 655CONFIG_SERIO=m
541CONFIG_SERIO_SERPORT=m 656# CONFIG_SERIO_SERPORT is not set
542CONFIG_SERIO_LIBPS2=m 657CONFIG_SERIO_LIBPS2=m
543# CONFIG_SERIO_RAW is not set 658# CONFIG_SERIO_RAW is not set
544# CONFIG_GAMEPORT is not set 659# CONFIG_GAMEPORT is not set
@@ -549,6 +664,7 @@ CONFIG_SERIO_LIBPS2=m
549CONFIG_VT=y 664CONFIG_VT=y
550CONFIG_VT_CONSOLE=y 665CONFIG_VT_CONSOLE=y
551CONFIG_HW_CONSOLE=y 666CONFIG_HW_CONSOLE=y
667CONFIG_VT_HW_CONSOLE_BINDING=y
552# CONFIG_SERIAL_NONSTANDARD is not set 668# CONFIG_SERIAL_NONSTANDARD is not set
553 669
554# 670#
@@ -562,116 +678,117 @@ CONFIG_HW_CONSOLE=y
562CONFIG_UNIX98_PTYS=y 678CONFIG_UNIX98_PTYS=y
563CONFIG_LEGACY_PTYS=y 679CONFIG_LEGACY_PTYS=y
564CONFIG_LEGACY_PTY_COUNT=256 680CONFIG_LEGACY_PTY_COUNT=256
565
566#
567# IPMI
568#
569# CONFIG_IPMI_HANDLER is not set 681# CONFIG_IPMI_HANDLER is not set
570 682# CONFIG_HW_RANDOM is not set
571#
572# Watchdog Cards
573#
574# CONFIG_WATCHDOG is not set
575CONFIG_GEN_RTC=m 683CONFIG_GEN_RTC=m
576CONFIG_GEN_RTC_X=y 684CONFIG_GEN_RTC_X=y
577# CONFIG_DTLK is not set
578# CONFIG_R3964 is not set 685# CONFIG_R3964 is not set
579
580#
581# Ftape, the floppy tape device driver
582#
583# CONFIG_DRM is not set
584# CONFIG_RAW_DRIVER is not set 686# CONFIG_RAW_DRIVER is not set
585 687# CONFIG_TCG_TPM is not set
586#
587# TPM devices
588#
589
590#
591# I2C support
592#
593# CONFIG_I2C is not set 688# CONFIG_I2C is not set
594 689
595# 690#
596# Dallas's 1-wire bus 691# SPI support
597# 692#
693# CONFIG_SPI is not set
694# CONFIG_SPI_MASTER is not set
598# CONFIG_W1 is not set 695# CONFIG_W1 is not set
696# CONFIG_POWER_SUPPLY is not set
697# CONFIG_HWMON is not set
698# CONFIG_THERMAL is not set
699# CONFIG_WATCHDOG is not set
599 700
600# 701#
601# Misc devices 702# Sonics Silicon Backplane
602# 703#
704CONFIG_SSB_POSSIBLE=y
705# CONFIG_SSB is not set
603 706
604# 707#
605# Multimedia devices 708# Multifunction device drivers
606# 709#
607# CONFIG_VIDEO_DEV is not set 710# CONFIG_MFD_SM501 is not set
608 711
609# 712#
610# Digital Video Broadcasting Devices 713# Multimedia devices
611# 714#
612# CONFIG_DVB is not set 715# CONFIG_VIDEO_DEV is not set
716# CONFIG_DVB_CORE is not set
717# CONFIG_DAB is not set
613 718
614# 719#
615# Graphics support 720# Graphics support
616# 721#
722# CONFIG_VGASTATE is not set
723# CONFIG_VIDEO_OUTPUT_CONTROL is not set
617CONFIG_FB=y 724CONFIG_FB=y
725# CONFIG_FIRMWARE_EDID is not set
726# CONFIG_FB_DDC is not set
618CONFIG_FB_CFB_FILLRECT=y 727CONFIG_FB_CFB_FILLRECT=y
619CONFIG_FB_CFB_COPYAREA=y 728CONFIG_FB_CFB_COPYAREA=y
620CONFIG_FB_CFB_IMAGEBLIT=y 729CONFIG_FB_CFB_IMAGEBLIT=y
621CONFIG_FB_SOFT_CURSOR=y 730# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
731# CONFIG_FB_SYS_FILLRECT is not set
732# CONFIG_FB_SYS_COPYAREA is not set
733# CONFIG_FB_SYS_IMAGEBLIT is not set
734# CONFIG_FB_SYS_FOPS is not set
735CONFIG_FB_DEFERRED_IO=y
736# CONFIG_FB_SVGALIB is not set
622CONFIG_FB_MACMODES=y 737CONFIG_FB_MACMODES=y
623CONFIG_FB_MODE_HELPERS=y 738# CONFIG_FB_BACKLIGHT is not set
739# CONFIG_FB_MODE_HELPERS is not set
624# CONFIG_FB_TILEBLITTING is not set 740# CONFIG_FB_TILEBLITTING is not set
741
742#
743# Frame buffer hardware drivers
744#
625CONFIG_FB_VALKYRIE=y 745CONFIG_FB_VALKYRIE=y
626CONFIG_FB_MAC=y 746CONFIG_FB_MAC=y
747# CONFIG_FB_UVESA is not set
627# CONFIG_FB_S1D13XXX is not set 748# CONFIG_FB_S1D13XXX is not set
628# CONFIG_FB_VIRTUAL is not set 749# CONFIG_FB_VIRTUAL is not set
750# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
751
752#
753# Display device support
754#
755# CONFIG_DISPLAY_SUPPORT is not set
629 756
630# 757#
631# Console display driver support 758# Console display driver support
632# 759#
633CONFIG_DUMMY_CONSOLE=y 760CONFIG_DUMMY_CONSOLE=y
634CONFIG_FRAMEBUFFER_CONSOLE=y 761CONFIG_FRAMEBUFFER_CONSOLE=y
762# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
763# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
635# CONFIG_FONTS is not set 764# CONFIG_FONTS is not set
636CONFIG_FONT_8x8=y 765CONFIG_FONT_8x8=y
637CONFIG_FONT_8x16=y 766CONFIG_FONT_8x16=y
638CONFIG_FONT_6x11=y 767CONFIG_FONT_6x11=y
639
640#
641# Logo configuration
642#
643CONFIG_LOGO=y 768CONFIG_LOGO=y
644CONFIG_LOGO_LINUX_MONO=y 769CONFIG_LOGO_LINUX_MONO=y
645CONFIG_LOGO_LINUX_VGA16=y 770CONFIG_LOGO_LINUX_VGA16=y
646CONFIG_LOGO_LINUX_CLUT224=y 771CONFIG_LOGO_LINUX_CLUT224=y
647CONFIG_LOGO_MAC_CLUT224=y 772CONFIG_LOGO_MAC_CLUT224=y
648# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
649 773
650# 774#
651# Sound 775# Sound
652# 776#
653# CONFIG_SOUND is not set 777# CONFIG_SOUND is not set
654 778CONFIG_HID_SUPPORT=y
655# 779CONFIG_HID=m
656# USB support 780# CONFIG_HID_DEBUG is not set
657# 781CONFIG_HIDRAW=y
658# CONFIG_USB_ARCH_HAS_HCD is not set 782# CONFIG_USB_SUPPORT is not set
659# CONFIG_USB_ARCH_HAS_OHCI is not set
660
661#
662# USB Gadget Support
663#
664# CONFIG_USB_GADGET is not set
665
666#
667# MMC/SD Card support
668#
669# CONFIG_MMC is not set 783# CONFIG_MMC is not set
784# CONFIG_MEMSTICK is not set
785# CONFIG_NEW_LEDS is not set
786# CONFIG_RTC_CLASS is not set
670 787
671# 788#
672# InfiniBand support 789# Userspace I/O
673# 790#
674# CONFIG_INFINIBAND is not set 791# CONFIG_UIO is not set
675 792
676# 793#
677# Character devices 794# Character devices
@@ -685,10 +802,11 @@ CONFIG_SERIAL_CONSOLE=y
685# 802#
686CONFIG_EXT2_FS=y 803CONFIG_EXT2_FS=y
687# CONFIG_EXT2_FS_XATTR is not set 804# CONFIG_EXT2_FS_XATTR is not set
805# CONFIG_EXT2_FS_XIP is not set
688CONFIG_EXT3_FS=y 806CONFIG_EXT3_FS=y
689# CONFIG_EXT3_FS_XATTR is not set 807# CONFIG_EXT3_FS_XATTR is not set
808# CONFIG_EXT4DEV_FS is not set
690CONFIG_JBD=y 809CONFIG_JBD=y
691# CONFIG_JBD_DEBUG is not set
692CONFIG_REISERFS_FS=m 810CONFIG_REISERFS_FS=m
693# CONFIG_REISERFS_CHECK is not set 811# CONFIG_REISERFS_CHECK is not set
694# CONFIG_REISERFS_PROC_INFO is not set 812# CONFIG_REISERFS_PROC_INFO is not set
@@ -699,25 +817,29 @@ CONFIG_JFS_FS=m
699# CONFIG_JFS_DEBUG is not set 817# CONFIG_JFS_DEBUG is not set
700# CONFIG_JFS_STATISTICS is not set 818# CONFIG_JFS_STATISTICS is not set
701CONFIG_FS_POSIX_ACL=y 819CONFIG_FS_POSIX_ACL=y
702
703#
704# XFS support
705#
706CONFIG_XFS_FS=m 820CONFIG_XFS_FS=m
707CONFIG_XFS_EXPORT=y
708# CONFIG_XFS_RT is not set
709# CONFIG_XFS_QUOTA is not set 821# CONFIG_XFS_QUOTA is not set
710# CONFIG_XFS_SECURITY is not set 822# CONFIG_XFS_SECURITY is not set
711# CONFIG_XFS_POSIX_ACL is not set 823# CONFIG_XFS_POSIX_ACL is not set
712CONFIG_MINIX_FS=y 824# CONFIG_XFS_RT is not set
713# CONFIG_ROMFS_FS is not set 825CONFIG_GFS2_FS=m
826CONFIG_GFS2_FS_LOCKING_NOLOCK=m
827CONFIG_GFS2_FS_LOCKING_DLM=m
828CONFIG_OCFS2_FS=m
829# CONFIG_OCFS2_DEBUG_MASKLOG is not set
830# CONFIG_OCFS2_DEBUG_FS is not set
831CONFIG_DNOTIFY=y
832CONFIG_INOTIFY=y
833CONFIG_INOTIFY_USER=y
714CONFIG_QUOTA=y 834CONFIG_QUOTA=y
835CONFIG_QUOTA_NETLINK_INTERFACE=y
836# CONFIG_PRINT_QUOTA_WARNING is not set
715# CONFIG_QFMT_V1 is not set 837# CONFIG_QFMT_V1 is not set
716# CONFIG_QFMT_V2 is not set 838# CONFIG_QFMT_V2 is not set
717CONFIG_QUOTACTL=y 839CONFIG_QUOTACTL=y
718CONFIG_DNOTIFY=y
719CONFIG_AUTOFS_FS=m 840CONFIG_AUTOFS_FS=m
720CONFIG_AUTOFS4_FS=m 841CONFIG_AUTOFS4_FS=m
842CONFIG_FUSE_FS=m
721 843
722# 844#
723# CD-ROM/DVD Filesystems 845# CD-ROM/DVD Filesystems
@@ -725,7 +847,6 @@ CONFIG_AUTOFS4_FS=m
725CONFIG_ISO9660_FS=y 847CONFIG_ISO9660_FS=y
726CONFIG_JOLIET=y 848CONFIG_JOLIET=y
727CONFIG_ZISOFS=y 849CONFIG_ZISOFS=y
728CONFIG_ZISOFS_FS=y
729CONFIG_UDF_FS=m 850CONFIG_UDF_FS=m
730CONFIG_UDF_NLS=y 851CONFIG_UDF_NLS=y
731 852
@@ -744,13 +865,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
744# 865#
745CONFIG_PROC_FS=y 866CONFIG_PROC_FS=y
746CONFIG_PROC_KCORE=y 867CONFIG_PROC_KCORE=y
868CONFIG_PROC_SYSCTL=y
747CONFIG_SYSFS=y 869CONFIG_SYSFS=y
748# CONFIG_DEVFS_FS is not set
749# CONFIG_DEVPTS_FS_XATTR is not set
750CONFIG_TMPFS=y 870CONFIG_TMPFS=y
751# CONFIG_TMPFS_XATTR is not set 871# CONFIG_TMPFS_POSIX_ACL is not set
752# CONFIG_HUGETLB_PAGE is not set 872# CONFIG_HUGETLB_PAGE is not set
753CONFIG_RAMFS=y 873CONFIG_CONFIGFS_FS=m
754 874
755# 875#
756# Miscellaneous filesystems 876# Miscellaneous filesystems
@@ -764,43 +884,39 @@ CONFIG_HFSPLUS_FS=y
764# CONFIG_EFS_FS is not set 884# CONFIG_EFS_FS is not set
765CONFIG_CRAMFS=m 885CONFIG_CRAMFS=m
766# CONFIG_VXFS_FS is not set 886# CONFIG_VXFS_FS is not set
887CONFIG_MINIX_FS=y
767CONFIG_HPFS_FS=m 888CONFIG_HPFS_FS=m
768# CONFIG_QNX4FS_FS is not set 889# CONFIG_QNX4FS_FS is not set
890# CONFIG_ROMFS_FS is not set
769CONFIG_SYSV_FS=m 891CONFIG_SYSV_FS=m
770CONFIG_UFS_FS=m 892CONFIG_UFS_FS=m
771# CONFIG_UFS_FS_WRITE is not set 893# CONFIG_UFS_FS_WRITE is not set
772 894# CONFIG_UFS_DEBUG is not set
773# 895CONFIG_NETWORK_FILESYSTEMS=y
774# Network File Systems
775#
776CONFIG_NFS_FS=m 896CONFIG_NFS_FS=m
777CONFIG_NFS_V3=y 897CONFIG_NFS_V3=y
898# CONFIG_NFS_V3_ACL is not set
778CONFIG_NFS_V4=y 899CONFIG_NFS_V4=y
779# CONFIG_NFS_DIRECTIO is not set 900# CONFIG_NFS_DIRECTIO is not set
780CONFIG_NFSD=m 901CONFIG_NFSD=m
781CONFIG_NFSD_V3=y 902CONFIG_NFSD_V3=y
782CONFIG_NFSD_V4=y 903# CONFIG_NFSD_V3_ACL is not set
904# CONFIG_NFSD_V4 is not set
783CONFIG_NFSD_TCP=y 905CONFIG_NFSD_TCP=y
784CONFIG_LOCKD=m 906CONFIG_LOCKD=m
785CONFIG_LOCKD_V4=y 907CONFIG_LOCKD_V4=y
786CONFIG_EXPORTFS=m 908CONFIG_EXPORTFS=m
909CONFIG_NFS_COMMON=y
787CONFIG_SUNRPC=m 910CONFIG_SUNRPC=m
788CONFIG_SUNRPC_GSS=m 911CONFIG_SUNRPC_GSS=m
912CONFIG_SUNRPC_BIND34=y
789CONFIG_RPCSEC_GSS_KRB5=m 913CONFIG_RPCSEC_GSS_KRB5=m
790# CONFIG_RPCSEC_GSS_SPKM3 is not set 914# CONFIG_RPCSEC_GSS_SPKM3 is not set
791CONFIG_SMB_FS=m 915CONFIG_SMB_FS=m
792CONFIG_SMB_NLS_DEFAULT=y 916CONFIG_SMB_NLS_DEFAULT=y
793CONFIG_SMB_NLS_REMOTE="cp437" 917CONFIG_SMB_NLS_REMOTE="cp437"
794# CONFIG_CIFS is not set 918# CONFIG_CIFS is not set
795CONFIG_NCP_FS=m 919# CONFIG_NCP_FS is not set
796# CONFIG_NCPFS_PACKET_SIGNING is not set
797# CONFIG_NCPFS_IOCTL_LOCKING is not set
798# CONFIG_NCPFS_STRONG is not set
799CONFIG_NCPFS_NFS_NS=y
800CONFIG_NCPFS_OS2_NS=y
801# CONFIG_NCPFS_SMALLDOS is not set
802CONFIG_NCPFS_NLS=y
803# CONFIG_NCPFS_EXTRAS is not set
804CONFIG_CODA_FS=m 920CONFIG_CODA_FS=m
805# CONFIG_CODA_FS_OLD_API is not set 921# CONFIG_CODA_FS_OLD_API is not set
806# CONFIG_AFS_FS is not set 922# CONFIG_AFS_FS is not set
@@ -808,27 +924,9 @@ CONFIG_CODA_FS=m
808# 924#
809# Partition Types 925# Partition Types
810# 926#
811CONFIG_PARTITION_ADVANCED=y 927# CONFIG_PARTITION_ADVANCED is not set
812# CONFIG_ACORN_PARTITION is not set
813# CONFIG_OSF_PARTITION is not set
814CONFIG_AMIGA_PARTITION=y
815CONFIG_ATARI_PARTITION=y
816CONFIG_MAC_PARTITION=y 928CONFIG_MAC_PARTITION=y
817CONFIG_MSDOS_PARTITION=y 929CONFIG_MSDOS_PARTITION=y
818CONFIG_BSD_DISKLABEL=y
819CONFIG_MINIX_SUBPARTITION=y
820CONFIG_SOLARIS_X86_PARTITION=y
821CONFIG_UNIXWARE_DISKLABEL=y
822CONFIG_LDM_PARTITION=y
823CONFIG_LDM_DEBUG=y
824# CONFIG_SGI_PARTITION is not set
825# CONFIG_ULTRIX_PARTITION is not set
826CONFIG_SUN_PARTITION=y
827# CONFIG_EFI_PARTITION is not set
828
829#
830# Native Language Support
831#
832CONFIG_NLS=y 930CONFIG_NLS=y
833CONFIG_NLS_DEFAULT="iso8859-1" 931CONFIG_NLS_DEFAULT="iso8859-1"
834CONFIG_NLS_CODEPAGE_437=y 932CONFIG_NLS_CODEPAGE_437=y
@@ -869,46 +967,65 @@ CONFIG_NLS_ISO8859_15=m
869CONFIG_NLS_KOI8_R=m 967CONFIG_NLS_KOI8_R=m
870CONFIG_NLS_KOI8_U=m 968CONFIG_NLS_KOI8_U=m
871CONFIG_NLS_UTF8=y 969CONFIG_NLS_UTF8=y
970CONFIG_DLM=m
971# CONFIG_DLM_DEBUG is not set
872 972
873# 973#
874# Kernel hacking 974# Kernel hacking
875# 975#
876# CONFIG_PRINTK_TIME is not set 976# CONFIG_PRINTK_TIME is not set
877CONFIG_DEBUG_KERNEL=y 977CONFIG_ENABLE_WARN_DEPRECATED=y
978CONFIG_ENABLE_MUST_CHECK=y
878CONFIG_MAGIC_SYSRQ=y 979CONFIG_MAGIC_SYSRQ=y
879CONFIG_LOG_BUF_SHIFT=16 980# CONFIG_UNUSED_SYMBOLS is not set
880# CONFIG_SCHEDSTATS is not set
881# CONFIG_DEBUG_SLAB is not set
882# CONFIG_DEBUG_SPINLOCK is not set
883# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
884# CONFIG_DEBUG_KOBJECT is not set
885CONFIG_DEBUG_BUGVERBOSE=y
886# CONFIG_DEBUG_INFO is not set
887# CONFIG_DEBUG_FS is not set 981# CONFIG_DEBUG_FS is not set
888# CONFIG_FRAME_POINTER is not set 982# CONFIG_HEADERS_CHECK is not set
983# CONFIG_DEBUG_KERNEL is not set
984CONFIG_DEBUG_BUGVERBOSE=y
985# CONFIG_SAMPLES is not set
889 986
890# 987#
891# Security options 988# Security options
892# 989#
893# CONFIG_KEYS is not set 990# CONFIG_KEYS is not set
894# CONFIG_SECURITY is not set 991# CONFIG_SECURITY is not set
895 992# CONFIG_SECURITY_FILE_CAPABILITIES is not set
896# 993CONFIG_XOR_BLOCKS=m
897# Cryptographic options 994CONFIG_ASYNC_CORE=m
898# 995CONFIG_ASYNC_MEMCPY=m
996CONFIG_ASYNC_XOR=m
899CONFIG_CRYPTO=y 997CONFIG_CRYPTO=y
998CONFIG_CRYPTO_ALGAPI=y
999CONFIG_CRYPTO_AEAD=m
1000CONFIG_CRYPTO_BLKCIPHER=m
1001CONFIG_CRYPTO_SEQIV=m
1002CONFIG_CRYPTO_HASH=y
1003CONFIG_CRYPTO_MANAGER=y
900CONFIG_CRYPTO_HMAC=y 1004CONFIG_CRYPTO_HMAC=y
1005CONFIG_CRYPTO_XCBC=m
901CONFIG_CRYPTO_NULL=m 1006CONFIG_CRYPTO_NULL=m
902CONFIG_CRYPTO_MD4=m 1007CONFIG_CRYPTO_MD4=m
903CONFIG_CRYPTO_MD5=y 1008CONFIG_CRYPTO_MD5=m
904CONFIG_CRYPTO_SHA1=m 1009CONFIG_CRYPTO_SHA1=m
905CONFIG_CRYPTO_SHA256=m 1010CONFIG_CRYPTO_SHA256=m
906CONFIG_CRYPTO_SHA512=m 1011CONFIG_CRYPTO_SHA512=m
907CONFIG_CRYPTO_WP512=m 1012CONFIG_CRYPTO_WP512=m
908CONFIG_CRYPTO_TGR192=m 1013CONFIG_CRYPTO_TGR192=m
1014CONFIG_CRYPTO_GF128MUL=m
1015CONFIG_CRYPTO_ECB=m
1016CONFIG_CRYPTO_CBC=m
1017CONFIG_CRYPTO_PCBC=m
1018CONFIG_CRYPTO_LRW=m
1019CONFIG_CRYPTO_XTS=m
1020CONFIG_CRYPTO_CTR=m
1021CONFIG_CRYPTO_GCM=m
1022CONFIG_CRYPTO_CCM=m
1023CONFIG_CRYPTO_CRYPTD=m
909CONFIG_CRYPTO_DES=m 1024CONFIG_CRYPTO_DES=m
1025CONFIG_CRYPTO_FCRYPT=m
910CONFIG_CRYPTO_BLOWFISH=m 1026CONFIG_CRYPTO_BLOWFISH=m
911CONFIG_CRYPTO_TWOFISH=m 1027CONFIG_CRYPTO_TWOFISH=m
1028CONFIG_CRYPTO_TWOFISH_COMMON=m
912CONFIG_CRYPTO_SERPENT=m 1029CONFIG_CRYPTO_SERPENT=m
913CONFIG_CRYPTO_AES=m 1030CONFIG_CRYPTO_AES=m
914CONFIG_CRYPTO_CAST5=m 1031CONFIG_CRYPTO_CAST5=m
@@ -917,20 +1034,35 @@ CONFIG_CRYPTO_TEA=m
917CONFIG_CRYPTO_ARC4=m 1034CONFIG_CRYPTO_ARC4=m
918CONFIG_CRYPTO_KHAZAD=m 1035CONFIG_CRYPTO_KHAZAD=m
919CONFIG_CRYPTO_ANUBIS=m 1036CONFIG_CRYPTO_ANUBIS=m
1037CONFIG_CRYPTO_SEED=m
1038CONFIG_CRYPTO_SALSA20=m
920CONFIG_CRYPTO_DEFLATE=m 1039CONFIG_CRYPTO_DEFLATE=m
921CONFIG_CRYPTO_MICHAEL_MIC=m 1040CONFIG_CRYPTO_MICHAEL_MIC=m
922CONFIG_CRYPTO_CRC32C=m 1041CONFIG_CRYPTO_CRC32C=m
1042CONFIG_CRYPTO_CAMELLIA=m
923CONFIG_CRYPTO_TEST=m 1043CONFIG_CRYPTO_TEST=m
924 1044CONFIG_CRYPTO_AUTHENC=m
925# 1045CONFIG_CRYPTO_LZO=m
926# Hardware crypto devices 1046# CONFIG_CRYPTO_HW is not set
927#
928 1047
929# 1048#
930# Library routines 1049# Library routines
931# 1050#
1051CONFIG_BITREVERSE=y
932CONFIG_CRC_CCITT=m 1052CONFIG_CRC_CCITT=m
1053CONFIG_CRC16=m
1054# CONFIG_CRC_ITU_T is not set
933CONFIG_CRC32=y 1055CONFIG_CRC32=y
1056# CONFIG_CRC7 is not set
934CONFIG_LIBCRC32C=m 1057CONFIG_LIBCRC32C=m
935CONFIG_ZLIB_INFLATE=y 1058CONFIG_ZLIB_INFLATE=y
936CONFIG_ZLIB_DEFLATE=m 1059CONFIG_ZLIB_DEFLATE=m
1060CONFIG_LZO_COMPRESS=m
1061CONFIG_LZO_DECOMPRESS=m
1062CONFIG_TEXTSEARCH=y
1063CONFIG_TEXTSEARCH_KMP=m
1064CONFIG_TEXTSEARCH_BM=m
1065CONFIG_TEXTSEARCH_FSM=m
1066CONFIG_PLIST=y
1067CONFIG_HAS_IOMEM=y
1068CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index f0d5534f683..f40b1724254 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:50 2005 4# Wed Apr 2 20:46:17 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-mvme147" 27CONFIG_LOCALVERSION="-mvme147"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68030=y
85CONFIG_MMU_MOTOROLA=y 133CONFIG_MMU_MOTOROLA=y
86# CONFIG_M68KFPU_EMU is not set 134# CONFIG_M68KFPU_EMU is not set
87# CONFIG_ADVANCED is not set 135# CONFIG_ADVANCED is not set
136CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
137CONFIG_NODES_SHIFT=3
138CONFIG_SELECT_MEMORY_MODEL=y
139# CONFIG_FLATMEM_MANUAL is not set
140CONFIG_DISCONTIGMEM_MANUAL=y
141# CONFIG_SPARSEMEM_MANUAL is not set
142CONFIG_DISCONTIGMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y
144CONFIG_NEED_MULTIPLE_NODES=y
145# CONFIG_SPARSEMEM_STATIC is not set
146# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
147CONFIG_SPLIT_PTLOCK_CPUS=4
148# CONFIG_RESOURCES_64BIT is not set
149CONFIG_ZONE_DMA_FLAG=1
150CONFIG_BOUNCE=y
151CONFIG_VIRT_TO_BUS=y
88 152
89# 153#
90# General setup 154# General setup
@@ -93,135 +157,11 @@ CONFIG_BINFMT_ELF=y
93CONFIG_BINFMT_AOUT=m 157CONFIG_BINFMT_AOUT=m
94CONFIG_BINFMT_MISC=m 158CONFIG_BINFMT_MISC=m
95CONFIG_PROC_HARDWARE=y 159CONFIG_PROC_HARDWARE=y
160CONFIG_ZONE_DMA=y
161# CONFIG_ARCH_SUPPORTS_MSI is not set
96 162
97# 163#
98# Device Drivers 164# Networking
99#
100
101#
102# Generic Driver Options
103#
104CONFIG_STANDALONE=y
105CONFIG_PREVENT_FIRMWARE_BUILD=y
106CONFIG_FW_LOADER=m
107# CONFIG_DEBUG_DRIVER is not set
108
109#
110# Memory Technology Devices (MTD)
111#
112# CONFIG_MTD is not set
113
114#
115# Parallel port support
116#
117# CONFIG_PARPORT is not set
118
119#
120# Plug and Play support
121#
122
123#
124# Block devices
125#
126# CONFIG_BLK_DEV_COW_COMMON is not set
127CONFIG_BLK_DEV_LOOP=y
128CONFIG_BLK_DEV_CRYPTOLOOP=m
129CONFIG_BLK_DEV_NBD=m
130CONFIG_BLK_DEV_RAM=y
131CONFIG_BLK_DEV_RAM_COUNT=16
132CONFIG_BLK_DEV_RAM_SIZE=4096
133CONFIG_BLK_DEV_INITRD=y
134CONFIG_INITRAMFS_SOURCE=""
135CONFIG_CDROM_PKTCDVD=m
136CONFIG_CDROM_PKTCDVD_BUFFERS=8
137# CONFIG_CDROM_PKTCDVD_WCACHE is not set
138
139#
140# IO Schedulers
141#
142CONFIG_IOSCHED_NOOP=y
143CONFIG_IOSCHED_AS=y
144CONFIG_IOSCHED_DEADLINE=y
145CONFIG_IOSCHED_CFQ=y
146CONFIG_ATA_OVER_ETH=m
147
148#
149# ATA/ATAPI/MFM/RLL support
150#
151# CONFIG_IDE is not set
152
153#
154# SCSI device support
155#
156CONFIG_SCSI=y
157CONFIG_SCSI_PROC_FS=y
158
159#
160# SCSI support type (disk, tape, CD-ROM)
161#
162CONFIG_BLK_DEV_SD=y
163CONFIG_CHR_DEV_ST=m
164# CONFIG_CHR_DEV_OSST is not set
165CONFIG_BLK_DEV_SR=y
166CONFIG_BLK_DEV_SR_VENDOR=y
167CONFIG_CHR_DEV_SG=m
168
169#
170# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
171#
172# CONFIG_SCSI_MULTI_LUN is not set
173CONFIG_SCSI_CONSTANTS=y
174# CONFIG_SCSI_LOGGING is not set
175
176#
177# SCSI Transport Attributes
178#
179# CONFIG_SCSI_SPI_ATTRS is not set
180# CONFIG_SCSI_FC_ATTRS is not set
181# CONFIG_SCSI_ISCSI_ATTRS is not set
182
183#
184# SCSI low-level drivers
185#
186# CONFIG_SCSI_SATA is not set
187# CONFIG_SCSI_DEBUG is not set
188CONFIG_MVME147_SCSI=y
189
190#
191# Multi-device support (RAID and LVM)
192#
193CONFIG_MD=y
194CONFIG_BLK_DEV_MD=m
195CONFIG_MD_LINEAR=m
196CONFIG_MD_RAID0=m
197CONFIG_MD_RAID1=m
198# CONFIG_MD_RAID10 is not set
199CONFIG_MD_RAID5=m
200CONFIG_MD_RAID6=m
201CONFIG_MD_MULTIPATH=m
202# CONFIG_MD_FAULTY is not set
203CONFIG_BLK_DEV_DM=m
204CONFIG_DM_CRYPT=m
205CONFIG_DM_SNAPSHOT=m
206CONFIG_DM_MIRROR=m
207CONFIG_DM_ZERO=m
208CONFIG_DM_MULTIPATH=m
209CONFIG_DM_MULTIPATH_EMC=m
210
211#
212# Fusion MPT device support
213#
214
215#
216# IEEE 1394 (FireWire) support
217#
218
219#
220# I2O device support
221#
222
223#
224# Networking support
225# 165#
226CONFIG_NET=y 166CONFIG_NET=y
227 167
@@ -231,10 +171,17 @@ CONFIG_NET=y
231CONFIG_PACKET=y 171CONFIG_PACKET=y
232# CONFIG_PACKET_MMAP is not set 172# CONFIG_PACKET_MMAP is not set
233CONFIG_UNIX=y 173CONFIG_UNIX=y
174CONFIG_XFRM=y
175# CONFIG_XFRM_USER is not set
176# CONFIG_XFRM_SUB_POLICY is not set
177CONFIG_XFRM_MIGRATE=y
178# CONFIG_XFRM_STATISTICS is not set
234CONFIG_NET_KEY=y 179CONFIG_NET_KEY=y
180CONFIG_NET_KEY_MIGRATE=y
235CONFIG_INET=y 181CONFIG_INET=y
236# CONFIG_IP_MULTICAST is not set 182# CONFIG_IP_MULTICAST is not set
237# CONFIG_IP_ADVANCED_ROUTER is not set 183# CONFIG_IP_ADVANCED_ROUTER is not set
184CONFIG_IP_FIB_HASH=y
238CONFIG_IP_PNP=y 185CONFIG_IP_PNP=y
239CONFIG_IP_PNP_DHCP=y 186CONFIG_IP_PNP_DHCP=y
240CONFIG_IP_PNP_BOOTP=y 187CONFIG_IP_PNP_BOOTP=y
@@ -246,145 +193,199 @@ CONFIG_SYN_COOKIES=y
246CONFIG_INET_AH=m 193CONFIG_INET_AH=m
247CONFIG_INET_ESP=m 194CONFIG_INET_ESP=m
248CONFIG_INET_IPCOMP=m 195CONFIG_INET_IPCOMP=m
196CONFIG_INET_XFRM_TUNNEL=m
249CONFIG_INET_TUNNEL=m 197CONFIG_INET_TUNNEL=m
250CONFIG_IP_TCPDIAG=m 198CONFIG_INET_XFRM_MODE_TRANSPORT=m
251CONFIG_IP_TCPDIAG_IPV6=y 199CONFIG_INET_XFRM_MODE_TUNNEL=m
252 200CONFIG_INET_XFRM_MODE_BEET=m
253# 201CONFIG_INET_LRO=m
254# IP: Virtual Server Configuration 202CONFIG_INET_DIAG=m
255# 203CONFIG_INET_TCP_DIAG=m
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_CUBIC=y
206CONFIG_DEFAULT_TCP_CONG="cubic"
207# CONFIG_TCP_MD5SIG is not set
256# CONFIG_IP_VS is not set 208# CONFIG_IP_VS is not set
257CONFIG_IPV6=m 209CONFIG_IPV6=m
258CONFIG_IPV6_PRIVACY=y 210CONFIG_IPV6_PRIVACY=y
211CONFIG_IPV6_ROUTER_PREF=y
212CONFIG_IPV6_ROUTE_INFO=y
213# CONFIG_IPV6_OPTIMISTIC_DAD is not set
259CONFIG_INET6_AH=m 214CONFIG_INET6_AH=m
260CONFIG_INET6_ESP=m 215CONFIG_INET6_ESP=m
261CONFIG_INET6_IPCOMP=m 216CONFIG_INET6_IPCOMP=m
217# CONFIG_IPV6_MIP6 is not set
218CONFIG_INET6_XFRM_TUNNEL=m
262CONFIG_INET6_TUNNEL=m 219CONFIG_INET6_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_TRANSPORT=m
221CONFIG_INET6_XFRM_MODE_TUNNEL=m
222CONFIG_INET6_XFRM_MODE_BEET=m
223CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
224CONFIG_IPV6_SIT=m
263CONFIG_IPV6_TUNNEL=m 225CONFIG_IPV6_TUNNEL=m
226# CONFIG_IPV6_MULTIPLE_TABLES is not set
227# CONFIG_NETWORK_SECMARK is not set
264CONFIG_NETFILTER=y 228CONFIG_NETFILTER=y
265# CONFIG_NETFILTER_DEBUG is not set 229# CONFIG_NETFILTER_DEBUG is not set
230CONFIG_NETFILTER_ADVANCED=y
231
232#
233# Core Netfilter Configuration
234#
235CONFIG_NETFILTER_NETLINK=m
236CONFIG_NETFILTER_NETLINK_QUEUE=m
237CONFIG_NETFILTER_NETLINK_LOG=m
238CONFIG_NF_CONNTRACK=m
239CONFIG_NF_CT_ACCT=y
240CONFIG_NF_CONNTRACK_MARK=y
241# CONFIG_NF_CONNTRACK_EVENTS is not set
242CONFIG_NF_CT_PROTO_GRE=m
243CONFIG_NF_CT_PROTO_SCTP=m
244CONFIG_NF_CT_PROTO_UDPLITE=m
245CONFIG_NF_CONNTRACK_AMANDA=m
246CONFIG_NF_CONNTRACK_FTP=m
247CONFIG_NF_CONNTRACK_H323=m
248CONFIG_NF_CONNTRACK_IRC=m
249CONFIG_NF_CONNTRACK_NETBIOS_NS=m
250CONFIG_NF_CONNTRACK_PPTP=m
251CONFIG_NF_CONNTRACK_SANE=m
252CONFIG_NF_CONNTRACK_SIP=m
253CONFIG_NF_CONNTRACK_TFTP=m
254# CONFIG_NF_CT_NETLINK is not set
255CONFIG_NETFILTER_XTABLES=m
256CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
257CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
258CONFIG_NETFILTER_XT_TARGET_DSCP=m
259CONFIG_NETFILTER_XT_TARGET_MARK=m
260CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
261CONFIG_NETFILTER_XT_TARGET_NFLOG=m
262CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
263CONFIG_NETFILTER_XT_TARGET_RATEEST=m
264CONFIG_NETFILTER_XT_TARGET_TRACE=m
265CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
266CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
267CONFIG_NETFILTER_XT_MATCH_COMMENT=m
268CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
269CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
270CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
271CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
272CONFIG_NETFILTER_XT_MATCH_DCCP=m
273CONFIG_NETFILTER_XT_MATCH_DSCP=m
274CONFIG_NETFILTER_XT_MATCH_ESP=m
275CONFIG_NETFILTER_XT_MATCH_HELPER=m
276CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
277CONFIG_NETFILTER_XT_MATCH_LENGTH=m
278CONFIG_NETFILTER_XT_MATCH_LIMIT=m
279CONFIG_NETFILTER_XT_MATCH_MAC=m
280CONFIG_NETFILTER_XT_MATCH_MARK=m
281CONFIG_NETFILTER_XT_MATCH_OWNER=m
282CONFIG_NETFILTER_XT_MATCH_POLICY=m
283CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
284CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
285CONFIG_NETFILTER_XT_MATCH_QUOTA=m
286CONFIG_NETFILTER_XT_MATCH_RATEEST=m
287CONFIG_NETFILTER_XT_MATCH_REALM=m
288CONFIG_NETFILTER_XT_MATCH_SCTP=m
289CONFIG_NETFILTER_XT_MATCH_STATE=m
290CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
291CONFIG_NETFILTER_XT_MATCH_STRING=m
292CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
293CONFIG_NETFILTER_XT_MATCH_TIME=m
294CONFIG_NETFILTER_XT_MATCH_U32=m
295CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
266 296
267# 297#
268# IP: Netfilter Configuration 298# IP: Netfilter Configuration
269# 299#
270CONFIG_IP_NF_CONNTRACK=m 300CONFIG_NF_CONNTRACK_IPV4=m
271# CONFIG_IP_NF_CT_ACCT is not set 301CONFIG_NF_CONNTRACK_PROC_COMPAT=y
272CONFIG_IP_NF_CONNTRACK_MARK=y
273# CONFIG_IP_NF_CT_PROTO_SCTP is not set
274CONFIG_IP_NF_FTP=m
275CONFIG_IP_NF_IRC=m
276CONFIG_IP_NF_TFTP=m
277CONFIG_IP_NF_AMANDA=m
278CONFIG_IP_NF_QUEUE=m 302CONFIG_IP_NF_QUEUE=m
279CONFIG_IP_NF_IPTABLES=m 303CONFIG_IP_NF_IPTABLES=m
280CONFIG_IP_NF_MATCH_LIMIT=m
281CONFIG_IP_NF_MATCH_IPRANGE=m
282CONFIG_IP_NF_MATCH_MAC=m
283CONFIG_IP_NF_MATCH_PKTTYPE=m
284CONFIG_IP_NF_MATCH_MARK=m
285CONFIG_IP_NF_MATCH_MULTIPORT=m
286CONFIG_IP_NF_MATCH_TOS=m
287CONFIG_IP_NF_MATCH_RECENT=m 304CONFIG_IP_NF_MATCH_RECENT=m
288CONFIG_IP_NF_MATCH_ECN=m 305CONFIG_IP_NF_MATCH_ECN=m
289CONFIG_IP_NF_MATCH_DSCP=m 306CONFIG_IP_NF_MATCH_AH=m
290CONFIG_IP_NF_MATCH_AH_ESP=m
291CONFIG_IP_NF_MATCH_LENGTH=m
292CONFIG_IP_NF_MATCH_TTL=m 307CONFIG_IP_NF_MATCH_TTL=m
293CONFIG_IP_NF_MATCH_TCPMSS=m
294CONFIG_IP_NF_MATCH_HELPER=m
295CONFIG_IP_NF_MATCH_STATE=m
296CONFIG_IP_NF_MATCH_CONNTRACK=m
297CONFIG_IP_NF_MATCH_OWNER=m
298CONFIG_IP_NF_MATCH_ADDRTYPE=m 308CONFIG_IP_NF_MATCH_ADDRTYPE=m
299CONFIG_IP_NF_MATCH_REALM=m
300# CONFIG_IP_NF_MATCH_SCTP is not set
301# CONFIG_IP_NF_MATCH_COMMENT is not set
302CONFIG_IP_NF_MATCH_CONNMARK=m
303CONFIG_IP_NF_MATCH_HASHLIMIT=m
304CONFIG_IP_NF_FILTER=m 309CONFIG_IP_NF_FILTER=m
305CONFIG_IP_NF_TARGET_REJECT=m 310CONFIG_IP_NF_TARGET_REJECT=m
306CONFIG_IP_NF_TARGET_LOG=m 311CONFIG_IP_NF_TARGET_LOG=m
307CONFIG_IP_NF_TARGET_ULOG=m 312CONFIG_IP_NF_TARGET_ULOG=m
308CONFIG_IP_NF_TARGET_TCPMSS=m 313CONFIG_NF_NAT=m
309CONFIG_IP_NF_NAT=m 314CONFIG_NF_NAT_NEEDED=y
310CONFIG_IP_NF_NAT_NEEDED=y
311CONFIG_IP_NF_TARGET_MASQUERADE=m 315CONFIG_IP_NF_TARGET_MASQUERADE=m
312CONFIG_IP_NF_TARGET_REDIRECT=m 316CONFIG_IP_NF_TARGET_REDIRECT=m
313CONFIG_IP_NF_TARGET_NETMAP=m 317CONFIG_IP_NF_TARGET_NETMAP=m
314CONFIG_IP_NF_TARGET_SAME=m 318CONFIG_NF_NAT_SNMP_BASIC=m
315CONFIG_IP_NF_NAT_SNMP_BASIC=m 319CONFIG_NF_NAT_PROTO_GRE=m
316CONFIG_IP_NF_NAT_IRC=m 320CONFIG_NF_NAT_FTP=m
317CONFIG_IP_NF_NAT_FTP=m 321CONFIG_NF_NAT_IRC=m
318CONFIG_IP_NF_NAT_TFTP=m 322CONFIG_NF_NAT_TFTP=m
319CONFIG_IP_NF_NAT_AMANDA=m 323CONFIG_NF_NAT_AMANDA=m
324CONFIG_NF_NAT_PPTP=m
325CONFIG_NF_NAT_H323=m
326CONFIG_NF_NAT_SIP=m
320CONFIG_IP_NF_MANGLE=m 327CONFIG_IP_NF_MANGLE=m
321CONFIG_IP_NF_TARGET_TOS=m
322CONFIG_IP_NF_TARGET_ECN=m 328CONFIG_IP_NF_TARGET_ECN=m
323CONFIG_IP_NF_TARGET_DSCP=m 329CONFIG_IP_NF_TARGET_TTL=m
324CONFIG_IP_NF_TARGET_MARK=m 330CONFIG_IP_NF_TARGET_CLUSTERIP=m
325CONFIG_IP_NF_TARGET_CLASSIFY=m
326CONFIG_IP_NF_TARGET_CONNMARK=m
327# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
328CONFIG_IP_NF_RAW=m 331CONFIG_IP_NF_RAW=m
329CONFIG_IP_NF_TARGET_NOTRACK=m
330CONFIG_IP_NF_ARPTABLES=m 332CONFIG_IP_NF_ARPTABLES=m
331CONFIG_IP_NF_ARPFILTER=m 333CONFIG_IP_NF_ARPFILTER=m
332CONFIG_IP_NF_ARP_MANGLE=m 334CONFIG_IP_NF_ARP_MANGLE=m
333 335
334# 336#
335# IPv6: Netfilter Configuration (EXPERIMENTAL) 337# IPv6: Netfilter Configuration
336# 338#
339CONFIG_NF_CONNTRACK_IPV6=m
337CONFIG_IP6_NF_QUEUE=m 340CONFIG_IP6_NF_QUEUE=m
338CONFIG_IP6_NF_IPTABLES=m 341CONFIG_IP6_NF_IPTABLES=m
339CONFIG_IP6_NF_MATCH_LIMIT=m
340CONFIG_IP6_NF_MATCH_MAC=m
341CONFIG_IP6_NF_MATCH_RT=m 342CONFIG_IP6_NF_MATCH_RT=m
342CONFIG_IP6_NF_MATCH_OPTS=m 343CONFIG_IP6_NF_MATCH_OPTS=m
343CONFIG_IP6_NF_MATCH_FRAG=m 344CONFIG_IP6_NF_MATCH_FRAG=m
344CONFIG_IP6_NF_MATCH_HL=m 345CONFIG_IP6_NF_MATCH_HL=m
345CONFIG_IP6_NF_MATCH_MULTIPORT=m
346CONFIG_IP6_NF_MATCH_OWNER=m
347CONFIG_IP6_NF_MATCH_MARK=m
348CONFIG_IP6_NF_MATCH_IPV6HEADER=m 346CONFIG_IP6_NF_MATCH_IPV6HEADER=m
349CONFIG_IP6_NF_MATCH_AHESP=m 347CONFIG_IP6_NF_MATCH_AH=m
350CONFIG_IP6_NF_MATCH_LENGTH=m 348CONFIG_IP6_NF_MATCH_MH=m
351CONFIG_IP6_NF_MATCH_EUI64=m 349CONFIG_IP6_NF_MATCH_EUI64=m
352CONFIG_IP6_NF_FILTER=m 350CONFIG_IP6_NF_FILTER=m
353CONFIG_IP6_NF_TARGET_LOG=m 351CONFIG_IP6_NF_TARGET_LOG=m
352CONFIG_IP6_NF_TARGET_REJECT=m
354CONFIG_IP6_NF_MANGLE=m 353CONFIG_IP6_NF_MANGLE=m
355CONFIG_IP6_NF_TARGET_MARK=m 354CONFIG_IP6_NF_TARGET_HL=m
356CONFIG_IP6_NF_RAW=m 355CONFIG_IP6_NF_RAW=m
357CONFIG_XFRM=y 356CONFIG_IP_DCCP=m
358CONFIG_XFRM_USER=m 357CONFIG_INET_DCCP_DIAG=m
358CONFIG_IP_DCCP_ACKVEC=y
359 359
360# 360#
361# SCTP Configuration (EXPERIMENTAL) 361# DCCP CCIDs Configuration (EXPERIMENTAL)
362# 362#
363CONFIG_IP_DCCP_CCID2=m
364# CONFIG_IP_DCCP_CCID2_DEBUG is not set
365CONFIG_IP_DCCP_CCID3=m
366# CONFIG_IP_DCCP_CCID3_DEBUG is not set
367CONFIG_IP_DCCP_CCID3_RTO=100
368CONFIG_IP_DCCP_TFRC_LIB=m
363CONFIG_IP_SCTP=m 369CONFIG_IP_SCTP=m
364# CONFIG_SCTP_DBG_MSG is not set 370# CONFIG_SCTP_DBG_MSG is not set
365# CONFIG_SCTP_DBG_OBJCNT is not set 371# CONFIG_SCTP_DBG_OBJCNT is not set
366# CONFIG_SCTP_HMAC_NONE is not set 372# CONFIG_SCTP_HMAC_NONE is not set
367# CONFIG_SCTP_HMAC_SHA1 is not set 373# CONFIG_SCTP_HMAC_SHA1 is not set
368CONFIG_SCTP_HMAC_MD5=y 374CONFIG_SCTP_HMAC_MD5=y
375# CONFIG_TIPC is not set
369# CONFIG_ATM is not set 376# CONFIG_ATM is not set
370# CONFIG_BRIDGE is not set 377# CONFIG_BRIDGE is not set
371# CONFIG_VLAN_8021Q is not set 378# CONFIG_VLAN_8021Q is not set
372# CONFIG_DECNET is not set 379# CONFIG_DECNET is not set
373CONFIG_LLC=m 380CONFIG_LLC=m
374# CONFIG_LLC2 is not set 381# CONFIG_LLC2 is not set
375CONFIG_IPX=m 382# CONFIG_IPX is not set
376# CONFIG_IPX_INTERN is not set
377CONFIG_ATALK=m 383CONFIG_ATALK=m
378# CONFIG_DEV_APPLETALK is not set 384# CONFIG_DEV_APPLETALK is not set
379# CONFIG_X25 is not set 385# CONFIG_X25 is not set
380# CONFIG_LAPB is not set 386# CONFIG_LAPB is not set
381# CONFIG_NET_DIVERT is not set
382# CONFIG_ECONET is not set 387# CONFIG_ECONET is not set
383# CONFIG_WAN_ROUTER is not set 388# CONFIG_WAN_ROUTER is not set
384
385#
386# QoS and/or fair queueing
387#
388# CONFIG_NET_SCHED is not set 389# CONFIG_NET_SCHED is not set
389CONFIG_NET_CLS_ROUTE=y 390CONFIG_NET_CLS_ROUTE=y
390 391
@@ -392,46 +393,155 @@ CONFIG_NET_CLS_ROUTE=y
392# Network testing 393# Network testing
393# 394#
394# CONFIG_NET_PKTGEN is not set 395# CONFIG_NET_PKTGEN is not set
395CONFIG_NETPOLL=y
396# CONFIG_NETPOLL_RX is not set
397# CONFIG_NETPOLL_TRAP is not set
398CONFIG_NET_POLL_CONTROLLER=y
399# CONFIG_HAMRADIO is not set 396# CONFIG_HAMRADIO is not set
397# CONFIG_CAN is not set
400# CONFIG_IRDA is not set 398# CONFIG_IRDA is not set
401# CONFIG_BT is not set 399# CONFIG_BT is not set
402CONFIG_NETDEVICES=y 400# CONFIG_AF_RXRPC is not set
403CONFIG_DUMMY=m
404# CONFIG_BONDING is not set
405CONFIG_EQUALIZER=m
406# CONFIG_TUN is not set
407 401
408# 402#
409# Ethernet (10 or 100Mbit) 403# Wireless
410# 404#
411CONFIG_NET_ETHERNET=y 405# CONFIG_CFG80211 is not set
412CONFIG_MII=m 406CONFIG_WIRELESS_EXT=y
413CONFIG_MVME147_NET=y 407# CONFIG_MAC80211 is not set
408CONFIG_IEEE80211=m
409# CONFIG_IEEE80211_DEBUG is not set
410CONFIG_IEEE80211_CRYPT_WEP=m
411CONFIG_IEEE80211_CRYPT_CCMP=m
412CONFIG_IEEE80211_CRYPT_TKIP=m
413CONFIG_IEEE80211_SOFTMAC=m
414# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
415# CONFIG_RFKILL is not set
416# CONFIG_NET_9P is not set
414 417
415# 418#
416# Ethernet (1000 Mbit) 419# Device Drivers
420#
421
422#
423# Generic Driver Options
424#
425CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430CONFIG_CONNECTOR=m
431# CONFIG_MTD is not set
432# CONFIG_PARPORT is not set
433CONFIG_BLK_DEV=y
434# CONFIG_BLK_DEV_COW_COMMON is not set
435CONFIG_BLK_DEV_LOOP=y
436CONFIG_BLK_DEV_CRYPTOLOOP=m
437CONFIG_BLK_DEV_NBD=m
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=16
440CONFIG_BLK_DEV_RAM_SIZE=4096
441# CONFIG_BLK_DEV_XIP is not set
442CONFIG_CDROM_PKTCDVD=m
443CONFIG_CDROM_PKTCDVD_BUFFERS=8
444# CONFIG_CDROM_PKTCDVD_WCACHE is not set
445CONFIG_ATA_OVER_ETH=m
446CONFIG_MISC_DEVICES=y
447# CONFIG_EEPROM_93CX6 is not set
448# CONFIG_ENCLOSURE_SERVICES is not set
449CONFIG_HAVE_IDE=y
450# CONFIG_IDE is not set
451
452#
453# SCSI device support
417# 454#
455CONFIG_RAID_ATTRS=m
456CONFIG_SCSI=y
457CONFIG_SCSI_DMA=y
458CONFIG_SCSI_TGT=m
459# CONFIG_SCSI_NETLINK is not set
460CONFIG_SCSI_PROC_FS=y
418 461
419# 462#
420# Ethernet (10000 Mbit) 463# SCSI support type (disk, tape, CD-ROM)
421# 464#
465CONFIG_BLK_DEV_SD=y
466CONFIG_CHR_DEV_ST=m
467CONFIG_CHR_DEV_OSST=m
468CONFIG_BLK_DEV_SR=y
469CONFIG_BLK_DEV_SR_VENDOR=y
470CONFIG_CHR_DEV_SG=m
471# CONFIG_CHR_DEV_SCH is not set
422 472
423# 473#
424# Token Ring devices 474# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
425# 475#
476# CONFIG_SCSI_MULTI_LUN is not set
477CONFIG_SCSI_CONSTANTS=y
478# CONFIG_SCSI_LOGGING is not set
479# CONFIG_SCSI_SCAN_ASYNC is not set
480CONFIG_SCSI_WAIT_SCAN=m
426 481
427# 482#
428# Wireless LAN (non-hamradio) 483# SCSI Transports
429# 484#
430# CONFIG_NET_RADIO is not set 485CONFIG_SCSI_SPI_ATTRS=y
486# CONFIG_SCSI_FC_ATTRS is not set
487CONFIG_SCSI_ISCSI_ATTRS=m
488CONFIG_SCSI_SAS_ATTRS=m
489CONFIG_SCSI_SAS_LIBSAS=m
490CONFIG_SCSI_SAS_HOST_SMP=y
491# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
492CONFIG_SCSI_SRP_ATTRS=m
493CONFIG_SCSI_SRP_TGT_ATTRS=y
494CONFIG_SCSI_LOWLEVEL=y
495CONFIG_ISCSI_TCP=m
496# CONFIG_SCSI_DEBUG is not set
497CONFIG_MVME147_SCSI=y
498CONFIG_MD=y
499CONFIG_BLK_DEV_MD=m
500CONFIG_MD_LINEAR=m
501CONFIG_MD_RAID0=m
502CONFIG_MD_RAID1=m
503# CONFIG_MD_RAID10 is not set
504CONFIG_MD_RAID456=m
505CONFIG_MD_RAID5_RESHAPE=y
506CONFIG_MD_MULTIPATH=m
507# CONFIG_MD_FAULTY is not set
508CONFIG_BLK_DEV_DM=m
509# CONFIG_DM_DEBUG is not set
510CONFIG_DM_CRYPT=m
511CONFIG_DM_SNAPSHOT=m
512CONFIG_DM_MIRROR=m
513CONFIG_DM_ZERO=m
514CONFIG_DM_MULTIPATH=m
515CONFIG_DM_MULTIPATH_EMC=m
516CONFIG_DM_MULTIPATH_RDAC=m
517CONFIG_DM_MULTIPATH_HP=m
518# CONFIG_DM_DELAY is not set
519CONFIG_DM_UEVENT=y
520CONFIG_NETDEVICES=y
521# CONFIG_NETDEVICES_MULTIQUEUE is not set
522CONFIG_DUMMY=m
523# CONFIG_BONDING is not set
524CONFIG_MACVLAN=m
525CONFIG_EQUALIZER=m
526# CONFIG_TUN is not set
527CONFIG_VETH=m
528# CONFIG_PHYLIB is not set
529CONFIG_NET_ETHERNET=y
530# CONFIG_MII is not set
531CONFIG_MVME147_NET=y
532# CONFIG_IBM_NEW_EMAC_ZMII is not set
533# CONFIG_IBM_NEW_EMAC_RGMII is not set
534# CONFIG_IBM_NEW_EMAC_TAH is not set
535# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
536# CONFIG_B44 is not set
537# CONFIG_NETDEV_1000 is not set
538# CONFIG_NETDEV_10000 is not set
431 539
432# 540#
433# Wan interfaces 541# Wireless LAN
434# 542#
543# CONFIG_WLAN_PRE80211 is not set
544# CONFIG_WLAN_80211 is not set
435# CONFIG_WAN is not set 545# CONFIG_WAN is not set
436CONFIG_PPP=m 546CONFIG_PPP=m
437# CONFIG_PPP_MULTILINK is not set 547# CONFIG_PPP_MULTILINK is not set
@@ -440,28 +550,28 @@ CONFIG_PPP_ASYNC=m
440CONFIG_PPP_SYNC_TTY=m 550CONFIG_PPP_SYNC_TTY=m
441CONFIG_PPP_DEFLATE=m 551CONFIG_PPP_DEFLATE=m
442CONFIG_PPP_BSDCOMP=m 552CONFIG_PPP_BSDCOMP=m
553CONFIG_PPP_MPPE=m
443CONFIG_PPPOE=m 554CONFIG_PPPOE=m
555CONFIG_PPPOL2TP=m
444CONFIG_SLIP=m 556CONFIG_SLIP=m
445CONFIG_SLIP_COMPRESSED=y 557CONFIG_SLIP_COMPRESSED=y
558CONFIG_SLHC=m
446CONFIG_SLIP_SMART=y 559CONFIG_SLIP_SMART=y
447CONFIG_SLIP_MODE_SLIP6=y 560CONFIG_SLIP_MODE_SLIP6=y
448CONFIG_SHAPER=m
449CONFIG_NETCONSOLE=m 561CONFIG_NETCONSOLE=m
450 562CONFIG_NETCONSOLE_DYNAMIC=y
451# 563CONFIG_NETPOLL=y
452# ISDN subsystem 564# CONFIG_NETPOLL_TRAP is not set
453# 565CONFIG_NET_POLL_CONTROLLER=y
454# CONFIG_ISDN is not set 566# CONFIG_ISDN is not set
455
456#
457# Telephony Support
458#
459# CONFIG_PHONE is not set 567# CONFIG_PHONE is not set
460 568
461# 569#
462# Input device support 570# Input device support
463# 571#
464CONFIG_INPUT=y 572CONFIG_INPUT=y
573CONFIG_INPUT_FF_MEMLESS=m
574# CONFIG_INPUT_POLLDEV is not set
465 575
466# 576#
467# Userland interfaces 577# Userland interfaces
@@ -471,7 +581,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
471CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 581CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
472CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 582CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
473# CONFIG_INPUT_JOYDEV is not set 583# CONFIG_INPUT_JOYDEV is not set
474# CONFIG_INPUT_TSDEV is not set
475# CONFIG_INPUT_EVDEV is not set 584# CONFIG_INPUT_EVDEV is not set
476# CONFIG_INPUT_EVBUG is not set 585# CONFIG_INPUT_EVBUG is not set
477 586
@@ -484,11 +593,19 @@ CONFIG_INPUT_KEYBOARD=y
484# CONFIG_KEYBOARD_LKKBD is not set 593# CONFIG_KEYBOARD_LKKBD is not set
485# CONFIG_KEYBOARD_XTKBD is not set 594# CONFIG_KEYBOARD_XTKBD is not set
486# CONFIG_KEYBOARD_NEWTON is not set 595# CONFIG_KEYBOARD_NEWTON is not set
596# CONFIG_KEYBOARD_STOWAWAY is not set
487CONFIG_INPUT_MOUSE=y 597CONFIG_INPUT_MOUSE=y
488CONFIG_MOUSE_PS2=m 598CONFIG_MOUSE_PS2=m
599CONFIG_MOUSE_PS2_ALPS=y
600CONFIG_MOUSE_PS2_LOGIPS2PP=y
601CONFIG_MOUSE_PS2_SYNAPTICS=y
602CONFIG_MOUSE_PS2_LIFEBOOK=y
603CONFIG_MOUSE_PS2_TRACKPOINT=y
604# CONFIG_MOUSE_PS2_TOUCHKIT is not set
489CONFIG_MOUSE_SERIAL=m 605CONFIG_MOUSE_SERIAL=m
490# CONFIG_MOUSE_VSXXXAA is not set 606# CONFIG_MOUSE_VSXXXAA is not set
491# CONFIG_INPUT_JOYSTICK is not set 607# CONFIG_INPUT_JOYSTICK is not set
608# CONFIG_INPUT_TABLET is not set
492# CONFIG_INPUT_TOUCHSCREEN is not set 609# CONFIG_INPUT_TOUCHSCREEN is not set
493# CONFIG_INPUT_MISC is not set 610# CONFIG_INPUT_MISC is not set
494 611
@@ -496,7 +613,7 @@ CONFIG_MOUSE_SERIAL=m
496# Hardware I/O ports 613# Hardware I/O ports
497# 614#
498CONFIG_SERIO=m 615CONFIG_SERIO=m
499CONFIG_SERIO_SERPORT=m 616# CONFIG_SERIO_SERPORT is not set
500CONFIG_SERIO_LIBPS2=m 617CONFIG_SERIO_LIBPS2=m
501# CONFIG_SERIO_RAW is not set 618# CONFIG_SERIO_RAW is not set
502# CONFIG_GAMEPORT is not set 619# CONFIG_GAMEPORT is not set
@@ -507,6 +624,7 @@ CONFIG_SERIO_LIBPS2=m
507CONFIG_VT=y 624CONFIG_VT=y
508CONFIG_VT_CONSOLE=y 625CONFIG_VT_CONSOLE=y
509CONFIG_HW_CONSOLE=y 626CONFIG_HW_CONSOLE=y
627CONFIG_VT_HW_CONSOLE_BINDING=y
510# CONFIG_SERIAL_NONSTANDARD is not set 628# CONFIG_SERIAL_NONSTANDARD is not set
511 629
512# 630#
@@ -520,112 +638,80 @@ CONFIG_HW_CONSOLE=y
520CONFIG_UNIX98_PTYS=y 638CONFIG_UNIX98_PTYS=y
521CONFIG_LEGACY_PTYS=y 639CONFIG_LEGACY_PTYS=y
522CONFIG_LEGACY_PTY_COUNT=256 640CONFIG_LEGACY_PTY_COUNT=256
523
524#
525# IPMI
526#
527# CONFIG_IPMI_HANDLER is not set 641# CONFIG_IPMI_HANDLER is not set
528 642# CONFIG_HW_RANDOM is not set
529#
530# Watchdog Cards
531#
532# CONFIG_WATCHDOG is not set
533CONFIG_GEN_RTC=m 643CONFIG_GEN_RTC=m
534CONFIG_GEN_RTC_X=y 644CONFIG_GEN_RTC_X=y
535# CONFIG_DTLK is not set
536# CONFIG_R3964 is not set 645# CONFIG_R3964 is not set
537
538#
539# Ftape, the floppy tape device driver
540#
541# CONFIG_DRM is not set
542# CONFIG_RAW_DRIVER is not set 646# CONFIG_RAW_DRIVER is not set
647# CONFIG_TCG_TPM is not set
648# CONFIG_I2C is not set
543 649
544# 650#
545# TPM devices 651# SPI support
546#
547
548#
549# I2C support
550# 652#
551# CONFIG_I2C is not set 653# CONFIG_SPI is not set
654# CONFIG_SPI_MASTER is not set
655# CONFIG_W1 is not set
656# CONFIG_POWER_SUPPLY is not set
657# CONFIG_HWMON is not set
658# CONFIG_THERMAL is not set
659# CONFIG_WATCHDOG is not set
552 660
553# 661#
554# Dallas's 1-wire bus 662# Sonics Silicon Backplane
555# 663#
556# CONFIG_W1 is not set 664CONFIG_SSB_POSSIBLE=y
665# CONFIG_SSB is not set
557 666
558# 667#
559# Misc devices 668# Multifunction device drivers
560# 669#
670# CONFIG_MFD_SM501 is not set
561 671
562# 672#
563# Multimedia devices 673# Multimedia devices
564# 674#
565# CONFIG_VIDEO_DEV is not set 675# CONFIG_VIDEO_DEV is not set
676# CONFIG_DVB_CORE is not set
677# CONFIG_DAB is not set
566 678
567# 679#
568# Digital Video Broadcasting Devices 680# Graphics support
569# 681#
570# CONFIG_DVB is not set 682# CONFIG_VGASTATE is not set
683# CONFIG_VIDEO_OUTPUT_CONTROL is not set
684# CONFIG_FB is not set
685# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
571 686
572# 687#
573# Graphics support 688# Display device support
574# 689#
575CONFIG_FB=y 690# CONFIG_DISPLAY_SUPPORT is not set
576# CONFIG_FB_CFB_FILLRECT is not set
577# CONFIG_FB_CFB_COPYAREA is not set
578# CONFIG_FB_CFB_IMAGEBLIT is not set
579# CONFIG_FB_SOFT_CURSOR is not set
580# CONFIG_FB_MACMODES is not set
581CONFIG_FB_MODE_HELPERS=y
582# CONFIG_FB_TILEBLITTING is not set
583# CONFIG_FB_S1D13XXX is not set
584# CONFIG_FB_VIRTUAL is not set
585 691
586# 692#
587# Console display driver support 693# Console display driver support
588# 694#
589CONFIG_DUMMY_CONSOLE=y 695CONFIG_DUMMY_CONSOLE=y
590CONFIG_FRAMEBUFFER_CONSOLE=y
591# CONFIG_FONTS is not set
592CONFIG_FONT_8x8=y
593CONFIG_FONT_8x16=y
594
595#
596# Logo configuration
597#
598CONFIG_LOGO=y
599CONFIG_LOGO_LINUX_MONO=y
600CONFIG_LOGO_LINUX_VGA16=y
601CONFIG_LOGO_LINUX_CLUT224=y
602# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
603 696
604# 697#
605# Sound 698# Sound
606# 699#
607# CONFIG_SOUND is not set 700# CONFIG_SOUND is not set
608 701CONFIG_HID_SUPPORT=y
609# 702CONFIG_HID=m
610# USB support 703# CONFIG_HID_DEBUG is not set
611# 704CONFIG_HIDRAW=y
612# CONFIG_USB_ARCH_HAS_HCD is not set 705# CONFIG_USB_SUPPORT is not set
613# CONFIG_USB_ARCH_HAS_OHCI is not set
614
615#
616# USB Gadget Support
617#
618# CONFIG_USB_GADGET is not set
619
620#
621# MMC/SD Card support
622#
623# CONFIG_MMC is not set 706# CONFIG_MMC is not set
707# CONFIG_MEMSTICK is not set
708# CONFIG_NEW_LEDS is not set
709# CONFIG_RTC_CLASS is not set
624 710
625# 711#
626# InfiniBand support 712# Userspace I/O
627# 713#
628# CONFIG_INFINIBAND is not set 714# CONFIG_UIO is not set
629 715
630# 716#
631# Character devices 717# Character devices
@@ -638,10 +724,11 @@ CONFIG_SERIAL_CONSOLE=y
638# 724#
639CONFIG_EXT2_FS=y 725CONFIG_EXT2_FS=y
640# CONFIG_EXT2_FS_XATTR is not set 726# CONFIG_EXT2_FS_XATTR is not set
727# CONFIG_EXT2_FS_XIP is not set
641CONFIG_EXT3_FS=y 728CONFIG_EXT3_FS=y
642# CONFIG_EXT3_FS_XATTR is not set 729# CONFIG_EXT3_FS_XATTR is not set
730# CONFIG_EXT4DEV_FS is not set
643CONFIG_JBD=y 731CONFIG_JBD=y
644# CONFIG_JBD_DEBUG is not set
645CONFIG_REISERFS_FS=m 732CONFIG_REISERFS_FS=m
646# CONFIG_REISERFS_CHECK is not set 733# CONFIG_REISERFS_CHECK is not set
647# CONFIG_REISERFS_PROC_INFO is not set 734# CONFIG_REISERFS_PROC_INFO is not set
@@ -652,25 +739,29 @@ CONFIG_JFS_FS=m
652# CONFIG_JFS_DEBUG is not set 739# CONFIG_JFS_DEBUG is not set
653# CONFIG_JFS_STATISTICS is not set 740# CONFIG_JFS_STATISTICS is not set
654CONFIG_FS_POSIX_ACL=y 741CONFIG_FS_POSIX_ACL=y
655
656#
657# XFS support
658#
659CONFIG_XFS_FS=m 742CONFIG_XFS_FS=m
660CONFIG_XFS_EXPORT=y
661# CONFIG_XFS_RT is not set
662# CONFIG_XFS_QUOTA is not set 743# CONFIG_XFS_QUOTA is not set
663# CONFIG_XFS_SECURITY is not set 744# CONFIG_XFS_SECURITY is not set
664# CONFIG_XFS_POSIX_ACL is not set 745# CONFIG_XFS_POSIX_ACL is not set
665CONFIG_MINIX_FS=y 746# CONFIG_XFS_RT is not set
666# CONFIG_ROMFS_FS is not set 747CONFIG_GFS2_FS=m
748CONFIG_GFS2_FS_LOCKING_NOLOCK=m
749CONFIG_GFS2_FS_LOCKING_DLM=m
750CONFIG_OCFS2_FS=m
751# CONFIG_OCFS2_DEBUG_MASKLOG is not set
752# CONFIG_OCFS2_DEBUG_FS is not set
753CONFIG_DNOTIFY=y
754CONFIG_INOTIFY=y
755CONFIG_INOTIFY_USER=y
667CONFIG_QUOTA=y 756CONFIG_QUOTA=y
757CONFIG_QUOTA_NETLINK_INTERFACE=y
758# CONFIG_PRINT_QUOTA_WARNING is not set
668# CONFIG_QFMT_V1 is not set 759# CONFIG_QFMT_V1 is not set
669# CONFIG_QFMT_V2 is not set 760# CONFIG_QFMT_V2 is not set
670CONFIG_QUOTACTL=y 761CONFIG_QUOTACTL=y
671CONFIG_DNOTIFY=y
672CONFIG_AUTOFS_FS=m 762CONFIG_AUTOFS_FS=m
673CONFIG_AUTOFS4_FS=m 763CONFIG_AUTOFS4_FS=m
764CONFIG_FUSE_FS=m
674 765
675# 766#
676# CD-ROM/DVD Filesystems 767# CD-ROM/DVD Filesystems
@@ -678,7 +769,6 @@ CONFIG_AUTOFS4_FS=m
678CONFIG_ISO9660_FS=y 769CONFIG_ISO9660_FS=y
679CONFIG_JOLIET=y 770CONFIG_JOLIET=y
680CONFIG_ZISOFS=y 771CONFIG_ZISOFS=y
681CONFIG_ZISOFS_FS=y
682CONFIG_UDF_FS=m 772CONFIG_UDF_FS=m
683CONFIG_UDF_NLS=y 773CONFIG_UDF_NLS=y
684 774
@@ -697,15 +787,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
697# 787#
698CONFIG_PROC_FS=y 788CONFIG_PROC_FS=y
699CONFIG_PROC_KCORE=y 789CONFIG_PROC_KCORE=y
790CONFIG_PROC_SYSCTL=y
700CONFIG_SYSFS=y 791CONFIG_SYSFS=y
701CONFIG_DEVFS_FS=y
702# CONFIG_DEVFS_MOUNT is not set
703# CONFIG_DEVFS_DEBUG is not set
704# CONFIG_DEVPTS_FS_XATTR is not set
705CONFIG_TMPFS=y 792CONFIG_TMPFS=y
706# CONFIG_TMPFS_XATTR is not set 793# CONFIG_TMPFS_POSIX_ACL is not set
707# CONFIG_HUGETLB_PAGE is not set 794# CONFIG_HUGETLB_PAGE is not set
708CONFIG_RAMFS=y 795CONFIG_CONFIGFS_FS=m
709 796
710# 797#
711# Miscellaneous filesystems 798# Miscellaneous filesystems
@@ -719,44 +806,40 @@ CONFIG_HFSPLUS_FS=m
719# CONFIG_EFS_FS is not set 806# CONFIG_EFS_FS is not set
720CONFIG_CRAMFS=m 807CONFIG_CRAMFS=m
721# CONFIG_VXFS_FS is not set 808# CONFIG_VXFS_FS is not set
809CONFIG_MINIX_FS=y
722CONFIG_HPFS_FS=m 810CONFIG_HPFS_FS=m
723# CONFIG_QNX4FS_FS is not set 811# CONFIG_QNX4FS_FS is not set
812# CONFIG_ROMFS_FS is not set
724CONFIG_SYSV_FS=m 813CONFIG_SYSV_FS=m
725CONFIG_UFS_FS=m 814CONFIG_UFS_FS=m
726# CONFIG_UFS_FS_WRITE is not set 815# CONFIG_UFS_FS_WRITE is not set
727 816# CONFIG_UFS_DEBUG is not set
728# 817CONFIG_NETWORK_FILESYSTEMS=y
729# Network File Systems
730#
731CONFIG_NFS_FS=y 818CONFIG_NFS_FS=y
732CONFIG_NFS_V3=y 819CONFIG_NFS_V3=y
820# CONFIG_NFS_V3_ACL is not set
733CONFIG_NFS_V4=y 821CONFIG_NFS_V4=y
734# CONFIG_NFS_DIRECTIO is not set 822# CONFIG_NFS_DIRECTIO is not set
735CONFIG_NFSD=m 823CONFIG_NFSD=m
736CONFIG_NFSD_V3=y 824CONFIG_NFSD_V3=y
737CONFIG_NFSD_V4=y 825# CONFIG_NFSD_V3_ACL is not set
826# CONFIG_NFSD_V4 is not set
738CONFIG_NFSD_TCP=y 827CONFIG_NFSD_TCP=y
739CONFIG_ROOT_NFS=y 828CONFIG_ROOT_NFS=y
740CONFIG_LOCKD=y 829CONFIG_LOCKD=y
741CONFIG_LOCKD_V4=y 830CONFIG_LOCKD_V4=y
742CONFIG_EXPORTFS=m 831CONFIG_EXPORTFS=m
832CONFIG_NFS_COMMON=y
743CONFIG_SUNRPC=y 833CONFIG_SUNRPC=y
744CONFIG_SUNRPC_GSS=y 834CONFIG_SUNRPC_GSS=y
835CONFIG_SUNRPC_BIND34=y
745CONFIG_RPCSEC_GSS_KRB5=y 836CONFIG_RPCSEC_GSS_KRB5=y
746# CONFIG_RPCSEC_GSS_SPKM3 is not set 837# CONFIG_RPCSEC_GSS_SPKM3 is not set
747CONFIG_SMB_FS=m 838CONFIG_SMB_FS=m
748CONFIG_SMB_NLS_DEFAULT=y 839CONFIG_SMB_NLS_DEFAULT=y
749CONFIG_SMB_NLS_REMOTE="cp437" 840CONFIG_SMB_NLS_REMOTE="cp437"
750# CONFIG_CIFS is not set 841# CONFIG_CIFS is not set
751CONFIG_NCP_FS=m 842# CONFIG_NCP_FS is not set
752# CONFIG_NCPFS_PACKET_SIGNING is not set
753# CONFIG_NCPFS_IOCTL_LOCKING is not set
754# CONFIG_NCPFS_STRONG is not set
755# CONFIG_NCPFS_NFS_NS is not set
756# CONFIG_NCPFS_OS2_NS is not set
757# CONFIG_NCPFS_SMALLDOS is not set
758CONFIG_NCPFS_NLS=y
759# CONFIG_NCPFS_EXTRAS is not set
760CONFIG_CODA_FS=m 843CONFIG_CODA_FS=m
761# CONFIG_CODA_FS_OLD_API is not set 844# CONFIG_CODA_FS_OLD_API is not set
762# CONFIG_AFS_FS is not set 845# CONFIG_AFS_FS is not set
@@ -766,10 +849,7 @@ CONFIG_CODA_FS=m
766# 849#
767# CONFIG_PARTITION_ADVANCED is not set 850# CONFIG_PARTITION_ADVANCED is not set
768CONFIG_MSDOS_PARTITION=y 851CONFIG_MSDOS_PARTITION=y
769 852CONFIG_SYSV68_PARTITION=y
770#
771# Native Language Support
772#
773CONFIG_NLS=y 853CONFIG_NLS=y
774CONFIG_NLS_DEFAULT="iso8859-1" 854CONFIG_NLS_DEFAULT="iso8859-1"
775CONFIG_NLS_CODEPAGE_437=y 855CONFIG_NLS_CODEPAGE_437=y
@@ -810,35 +890,42 @@ CONFIG_NLS_ISO8859_15=m
810CONFIG_NLS_KOI8_R=m 890CONFIG_NLS_KOI8_R=m
811CONFIG_NLS_KOI8_U=m 891CONFIG_NLS_KOI8_U=m
812CONFIG_NLS_UTF8=m 892CONFIG_NLS_UTF8=m
893CONFIG_DLM=m
894# CONFIG_DLM_DEBUG is not set
813 895
814# 896#
815# Kernel hacking 897# Kernel hacking
816# 898#
817# CONFIG_PRINTK_TIME is not set 899# CONFIG_PRINTK_TIME is not set
818CONFIG_DEBUG_KERNEL=y 900CONFIG_ENABLE_WARN_DEPRECATED=y
901CONFIG_ENABLE_MUST_CHECK=y
819CONFIG_MAGIC_SYSRQ=y 902CONFIG_MAGIC_SYSRQ=y
820CONFIG_LOG_BUF_SHIFT=16 903# CONFIG_UNUSED_SYMBOLS is not set
821# CONFIG_SCHEDSTATS is not set
822# CONFIG_DEBUG_SLAB is not set
823# CONFIG_DEBUG_SPINLOCK is not set
824# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
825# CONFIG_DEBUG_KOBJECT is not set
826CONFIG_DEBUG_BUGVERBOSE=y
827# CONFIG_DEBUG_INFO is not set
828# CONFIG_DEBUG_FS is not set 904# CONFIG_DEBUG_FS is not set
829# CONFIG_FRAME_POINTER is not set 905# CONFIG_HEADERS_CHECK is not set
906# CONFIG_DEBUG_KERNEL is not set
907CONFIG_DEBUG_BUGVERBOSE=y
908# CONFIG_SAMPLES is not set
830 909
831# 910#
832# Security options 911# Security options
833# 912#
834# CONFIG_KEYS is not set 913# CONFIG_KEYS is not set
835# CONFIG_SECURITY is not set 914# CONFIG_SECURITY is not set
836 915# CONFIG_SECURITY_FILE_CAPABILITIES is not set
837# 916CONFIG_XOR_BLOCKS=m
838# Cryptographic options 917CONFIG_ASYNC_CORE=m
839# 918CONFIG_ASYNC_MEMCPY=m
919CONFIG_ASYNC_XOR=m
840CONFIG_CRYPTO=y 920CONFIG_CRYPTO=y
921CONFIG_CRYPTO_ALGAPI=y
922CONFIG_CRYPTO_AEAD=m
923CONFIG_CRYPTO_BLKCIPHER=y
924CONFIG_CRYPTO_SEQIV=m
925CONFIG_CRYPTO_HASH=y
926CONFIG_CRYPTO_MANAGER=y
841CONFIG_CRYPTO_HMAC=y 927CONFIG_CRYPTO_HMAC=y
928CONFIG_CRYPTO_XCBC=m
842CONFIG_CRYPTO_NULL=m 929CONFIG_CRYPTO_NULL=m
843CONFIG_CRYPTO_MD4=m 930CONFIG_CRYPTO_MD4=m
844CONFIG_CRYPTO_MD5=y 931CONFIG_CRYPTO_MD5=y
@@ -847,9 +934,21 @@ CONFIG_CRYPTO_SHA256=m
847CONFIG_CRYPTO_SHA512=m 934CONFIG_CRYPTO_SHA512=m
848CONFIG_CRYPTO_WP512=m 935CONFIG_CRYPTO_WP512=m
849CONFIG_CRYPTO_TGR192=m 936CONFIG_CRYPTO_TGR192=m
937CONFIG_CRYPTO_GF128MUL=m
938CONFIG_CRYPTO_ECB=m
939CONFIG_CRYPTO_CBC=y
940CONFIG_CRYPTO_PCBC=m
941CONFIG_CRYPTO_LRW=m
942CONFIG_CRYPTO_XTS=m
943CONFIG_CRYPTO_CTR=m
944CONFIG_CRYPTO_GCM=m
945CONFIG_CRYPTO_CCM=m
946CONFIG_CRYPTO_CRYPTD=m
850CONFIG_CRYPTO_DES=y 947CONFIG_CRYPTO_DES=y
948CONFIG_CRYPTO_FCRYPT=m
851CONFIG_CRYPTO_BLOWFISH=m 949CONFIG_CRYPTO_BLOWFISH=m
852CONFIG_CRYPTO_TWOFISH=m 950CONFIG_CRYPTO_TWOFISH=m
951CONFIG_CRYPTO_TWOFISH_COMMON=m
853CONFIG_CRYPTO_SERPENT=m 952CONFIG_CRYPTO_SERPENT=m
854CONFIG_CRYPTO_AES=m 953CONFIG_CRYPTO_AES=m
855CONFIG_CRYPTO_CAST5=m 954CONFIG_CRYPTO_CAST5=m
@@ -858,20 +957,35 @@ CONFIG_CRYPTO_TEA=m
858CONFIG_CRYPTO_ARC4=m 957CONFIG_CRYPTO_ARC4=m
859CONFIG_CRYPTO_KHAZAD=m 958CONFIG_CRYPTO_KHAZAD=m
860CONFIG_CRYPTO_ANUBIS=m 959CONFIG_CRYPTO_ANUBIS=m
960CONFIG_CRYPTO_SEED=m
961CONFIG_CRYPTO_SALSA20=m
861CONFIG_CRYPTO_DEFLATE=m 962CONFIG_CRYPTO_DEFLATE=m
862CONFIG_CRYPTO_MICHAEL_MIC=m 963CONFIG_CRYPTO_MICHAEL_MIC=m
863CONFIG_CRYPTO_CRC32C=m 964CONFIG_CRYPTO_CRC32C=m
965CONFIG_CRYPTO_CAMELLIA=m
864CONFIG_CRYPTO_TEST=m 966CONFIG_CRYPTO_TEST=m
865 967CONFIG_CRYPTO_AUTHENC=m
866# 968CONFIG_CRYPTO_LZO=m
867# Hardware crypto devices 969# CONFIG_CRYPTO_HW is not set
868#
869 970
870# 971#
871# Library routines 972# Library routines
872# 973#
974CONFIG_BITREVERSE=y
873CONFIG_CRC_CCITT=m 975CONFIG_CRC_CCITT=m
976CONFIG_CRC16=m
977# CONFIG_CRC_ITU_T is not set
874CONFIG_CRC32=y 978CONFIG_CRC32=y
979# CONFIG_CRC7 is not set
875CONFIG_LIBCRC32C=m 980CONFIG_LIBCRC32C=m
876CONFIG_ZLIB_INFLATE=y 981CONFIG_ZLIB_INFLATE=y
877CONFIG_ZLIB_DEFLATE=m 982CONFIG_ZLIB_DEFLATE=m
983CONFIG_LZO_COMPRESS=m
984CONFIG_LZO_DECOMPRESS=m
985CONFIG_TEXTSEARCH=y
986CONFIG_TEXTSEARCH_KMP=m
987CONFIG_TEXTSEARCH_BM=m
988CONFIG_TEXTSEARCH_FSM=m
989CONFIG_PLIST=y
990CONFIG_HAS_IOMEM=y
991CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index 1d5c46ff3c8..e9ccc774334 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:53 2005 4# Wed Apr 2 20:46:19 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-mvme16x" 27CONFIG_LOCALVERSION="-mvme16x"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -85,6 +133,22 @@ CONFIG_M68060=y
85CONFIG_MMU_MOTOROLA=y 133CONFIG_MMU_MOTOROLA=y
86# CONFIG_M68KFPU_EMU is not set 134# CONFIG_M68KFPU_EMU is not set
87# CONFIG_ADVANCED is not set 135# CONFIG_ADVANCED is not set
136CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
137CONFIG_NODES_SHIFT=3
138CONFIG_SELECT_MEMORY_MODEL=y
139# CONFIG_FLATMEM_MANUAL is not set
140CONFIG_DISCONTIGMEM_MANUAL=y
141# CONFIG_SPARSEMEM_MANUAL is not set
142CONFIG_DISCONTIGMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y
144CONFIG_NEED_MULTIPLE_NODES=y
145# CONFIG_SPARSEMEM_STATIC is not set
146# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
147CONFIG_SPLIT_PTLOCK_CPUS=4
148# CONFIG_RESOURCES_64BIT is not set
149CONFIG_ZONE_DMA_FLAG=1
150CONFIG_BOUNCE=y
151CONFIG_VIRT_TO_BUS=y
88 152
89# 153#
90# General setup 154# General setup
@@ -93,134 +157,11 @@ CONFIG_BINFMT_ELF=y
93CONFIG_BINFMT_AOUT=m 157CONFIG_BINFMT_AOUT=m
94CONFIG_BINFMT_MISC=m 158CONFIG_BINFMT_MISC=m
95CONFIG_PROC_HARDWARE=y 159CONFIG_PROC_HARDWARE=y
160CONFIG_ZONE_DMA=y
161# CONFIG_ARCH_SUPPORTS_MSI is not set
96 162
97# 163#
98# Device Drivers 164# Networking
99#
100
101#
102# Generic Driver Options
103#
104CONFIG_STANDALONE=y
105CONFIG_PREVENT_FIRMWARE_BUILD=y
106CONFIG_FW_LOADER=m
107# CONFIG_DEBUG_DRIVER is not set
108
109#
110# Memory Technology Devices (MTD)
111#
112# CONFIG_MTD is not set
113
114#
115# Parallel port support
116#
117# CONFIG_PARPORT is not set
118
119#
120# Plug and Play support
121#
122
123#
124# Block devices
125#
126# CONFIG_BLK_DEV_COW_COMMON is not set
127CONFIG_BLK_DEV_LOOP=y
128CONFIG_BLK_DEV_CRYPTOLOOP=m
129CONFIG_BLK_DEV_NBD=m
130CONFIG_BLK_DEV_RAM=y
131CONFIG_BLK_DEV_RAM_COUNT=16
132CONFIG_BLK_DEV_RAM_SIZE=4096
133CONFIG_BLK_DEV_INITRD=y
134CONFIG_INITRAMFS_SOURCE=""
135CONFIG_CDROM_PKTCDVD=m
136CONFIG_CDROM_PKTCDVD_BUFFERS=8
137# CONFIG_CDROM_PKTCDVD_WCACHE is not set
138
139#
140# IO Schedulers
141#
142CONFIG_IOSCHED_NOOP=y
143CONFIG_IOSCHED_AS=y
144CONFIG_IOSCHED_DEADLINE=y
145CONFIG_IOSCHED_CFQ=y
146CONFIG_ATA_OVER_ETH=m
147
148#
149# ATA/ATAPI/MFM/RLL support
150#
151# CONFIG_IDE is not set
152
153#
154# SCSI device support
155#
156CONFIG_SCSI=y
157CONFIG_SCSI_PROC_FS=y
158
159#
160# SCSI support type (disk, tape, CD-ROM)
161#
162CONFIG_BLK_DEV_SD=y
163CONFIG_CHR_DEV_ST=m
164# CONFIG_CHR_DEV_OSST is not set
165CONFIG_BLK_DEV_SR=y
166CONFIG_BLK_DEV_SR_VENDOR=y
167CONFIG_CHR_DEV_SG=m
168
169#
170# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
171#
172# CONFIG_SCSI_MULTI_LUN is not set
173CONFIG_SCSI_CONSTANTS=y
174# CONFIG_SCSI_LOGGING is not set
175
176#
177# SCSI Transport Attributes
178#
179# CONFIG_SCSI_SPI_ATTRS is not set
180# CONFIG_SCSI_FC_ATTRS is not set
181# CONFIG_SCSI_ISCSI_ATTRS is not set
182
183#
184# SCSI low-level drivers
185#
186# CONFIG_SCSI_SATA is not set
187# CONFIG_SCSI_DEBUG is not set
188
189#
190# Multi-device support (RAID and LVM)
191#
192CONFIG_MD=y
193CONFIG_BLK_DEV_MD=m
194CONFIG_MD_LINEAR=m
195CONFIG_MD_RAID0=m
196CONFIG_MD_RAID1=m
197# CONFIG_MD_RAID10 is not set
198CONFIG_MD_RAID5=m
199CONFIG_MD_RAID6=m
200CONFIG_MD_MULTIPATH=m
201# CONFIG_MD_FAULTY is not set
202CONFIG_BLK_DEV_DM=m
203CONFIG_DM_CRYPT=m
204CONFIG_DM_SNAPSHOT=m
205CONFIG_DM_MIRROR=m
206CONFIG_DM_ZERO=m
207CONFIG_DM_MULTIPATH=m
208CONFIG_DM_MULTIPATH_EMC=m
209
210#
211# Fusion MPT device support
212#
213
214#
215# IEEE 1394 (FireWire) support
216#
217
218#
219# I2O device support
220#
221
222#
223# Networking support
224# 165#
225CONFIG_NET=y 166CONFIG_NET=y
226 167
@@ -230,10 +171,17 @@ CONFIG_NET=y
230CONFIG_PACKET=y 171CONFIG_PACKET=y
231# CONFIG_PACKET_MMAP is not set 172# CONFIG_PACKET_MMAP is not set
232CONFIG_UNIX=y 173CONFIG_UNIX=y
174CONFIG_XFRM=y
175# CONFIG_XFRM_USER is not set
176# CONFIG_XFRM_SUB_POLICY is not set
177CONFIG_XFRM_MIGRATE=y
178# CONFIG_XFRM_STATISTICS is not set
233CONFIG_NET_KEY=y 179CONFIG_NET_KEY=y
180CONFIG_NET_KEY_MIGRATE=y
234CONFIG_INET=y 181CONFIG_INET=y
235# CONFIG_IP_MULTICAST is not set 182# CONFIG_IP_MULTICAST is not set
236# CONFIG_IP_ADVANCED_ROUTER is not set 183# CONFIG_IP_ADVANCED_ROUTER is not set
184CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y 185CONFIG_IP_PNP=y
238CONFIG_IP_PNP_DHCP=y 186CONFIG_IP_PNP_DHCP=y
239CONFIG_IP_PNP_BOOTP=y 187CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +193,199 @@ CONFIG_SYN_COOKIES=y
245CONFIG_INET_AH=m 193CONFIG_INET_AH=m
246CONFIG_INET_ESP=m 194CONFIG_INET_ESP=m
247CONFIG_INET_IPCOMP=m 195CONFIG_INET_IPCOMP=m
196CONFIG_INET_XFRM_TUNNEL=m
248CONFIG_INET_TUNNEL=m 197CONFIG_INET_TUNNEL=m
249CONFIG_IP_TCPDIAG=m 198CONFIG_INET_XFRM_MODE_TRANSPORT=m
250CONFIG_IP_TCPDIAG_IPV6=y 199CONFIG_INET_XFRM_MODE_TUNNEL=m
251 200CONFIG_INET_XFRM_MODE_BEET=m
252# 201CONFIG_INET_LRO=m
253# IP: Virtual Server Configuration 202CONFIG_INET_DIAG=m
254# 203CONFIG_INET_TCP_DIAG=m
204# CONFIG_TCP_CONG_ADVANCED is not set
205CONFIG_TCP_CONG_CUBIC=y
206CONFIG_DEFAULT_TCP_CONG="cubic"
207# CONFIG_TCP_MD5SIG is not set
255# CONFIG_IP_VS is not set 208# CONFIG_IP_VS is not set
256CONFIG_IPV6=m 209CONFIG_IPV6=m
257CONFIG_IPV6_PRIVACY=y 210CONFIG_IPV6_PRIVACY=y
211CONFIG_IPV6_ROUTER_PREF=y
212CONFIG_IPV6_ROUTE_INFO=y
213# CONFIG_IPV6_OPTIMISTIC_DAD is not set
258CONFIG_INET6_AH=m 214CONFIG_INET6_AH=m
259CONFIG_INET6_ESP=m 215CONFIG_INET6_ESP=m
260CONFIG_INET6_IPCOMP=m 216CONFIG_INET6_IPCOMP=m
217# CONFIG_IPV6_MIP6 is not set
218CONFIG_INET6_XFRM_TUNNEL=m
261CONFIG_INET6_TUNNEL=m 219CONFIG_INET6_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_TRANSPORT=m
221CONFIG_INET6_XFRM_MODE_TUNNEL=m
222CONFIG_INET6_XFRM_MODE_BEET=m
223CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
224CONFIG_IPV6_SIT=m
262CONFIG_IPV6_TUNNEL=m 225CONFIG_IPV6_TUNNEL=m
226# CONFIG_IPV6_MULTIPLE_TABLES is not set
227# CONFIG_NETWORK_SECMARK is not set
263CONFIG_NETFILTER=y 228CONFIG_NETFILTER=y
264# CONFIG_NETFILTER_DEBUG is not set 229# CONFIG_NETFILTER_DEBUG is not set
230CONFIG_NETFILTER_ADVANCED=y
231
232#
233# Core Netfilter Configuration
234#
235CONFIG_NETFILTER_NETLINK=m
236CONFIG_NETFILTER_NETLINK_QUEUE=m
237CONFIG_NETFILTER_NETLINK_LOG=m
238CONFIG_NF_CONNTRACK=m
239CONFIG_NF_CT_ACCT=y
240CONFIG_NF_CONNTRACK_MARK=y
241# CONFIG_NF_CONNTRACK_EVENTS is not set
242CONFIG_NF_CT_PROTO_GRE=m
243CONFIG_NF_CT_PROTO_SCTP=m
244CONFIG_NF_CT_PROTO_UDPLITE=m
245CONFIG_NF_CONNTRACK_AMANDA=m
246CONFIG_NF_CONNTRACK_FTP=m
247CONFIG_NF_CONNTRACK_H323=m
248CONFIG_NF_CONNTRACK_IRC=m
249CONFIG_NF_CONNTRACK_NETBIOS_NS=m
250CONFIG_NF_CONNTRACK_PPTP=m
251CONFIG_NF_CONNTRACK_SANE=m
252CONFIG_NF_CONNTRACK_SIP=m
253CONFIG_NF_CONNTRACK_TFTP=m
254# CONFIG_NF_CT_NETLINK is not set
255CONFIG_NETFILTER_XTABLES=m
256CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
257CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
258CONFIG_NETFILTER_XT_TARGET_DSCP=m
259CONFIG_NETFILTER_XT_TARGET_MARK=m
260CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
261CONFIG_NETFILTER_XT_TARGET_NFLOG=m
262CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
263CONFIG_NETFILTER_XT_TARGET_RATEEST=m
264CONFIG_NETFILTER_XT_TARGET_TRACE=m
265CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
266CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
267CONFIG_NETFILTER_XT_MATCH_COMMENT=m
268CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
269CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
270CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
271CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
272CONFIG_NETFILTER_XT_MATCH_DCCP=m
273CONFIG_NETFILTER_XT_MATCH_DSCP=m
274CONFIG_NETFILTER_XT_MATCH_ESP=m
275CONFIG_NETFILTER_XT_MATCH_HELPER=m
276CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
277CONFIG_NETFILTER_XT_MATCH_LENGTH=m
278CONFIG_NETFILTER_XT_MATCH_LIMIT=m
279CONFIG_NETFILTER_XT_MATCH_MAC=m
280CONFIG_NETFILTER_XT_MATCH_MARK=m
281CONFIG_NETFILTER_XT_MATCH_OWNER=m
282CONFIG_NETFILTER_XT_MATCH_POLICY=m
283CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
284CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
285CONFIG_NETFILTER_XT_MATCH_QUOTA=m
286CONFIG_NETFILTER_XT_MATCH_RATEEST=m
287CONFIG_NETFILTER_XT_MATCH_REALM=m
288CONFIG_NETFILTER_XT_MATCH_SCTP=m
289CONFIG_NETFILTER_XT_MATCH_STATE=m
290CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
291CONFIG_NETFILTER_XT_MATCH_STRING=m
292CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
293CONFIG_NETFILTER_XT_MATCH_TIME=m
294CONFIG_NETFILTER_XT_MATCH_U32=m
295CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
265 296
266# 297#
267# IP: Netfilter Configuration 298# IP: Netfilter Configuration
268# 299#
269CONFIG_IP_NF_CONNTRACK=m 300CONFIG_NF_CONNTRACK_IPV4=m
270# CONFIG_IP_NF_CT_ACCT is not set 301CONFIG_NF_CONNTRACK_PROC_COMPAT=y
271CONFIG_IP_NF_CONNTRACK_MARK=y
272# CONFIG_IP_NF_CT_PROTO_SCTP is not set
273CONFIG_IP_NF_FTP=m
274CONFIG_IP_NF_IRC=m
275CONFIG_IP_NF_TFTP=m
276CONFIG_IP_NF_AMANDA=m
277CONFIG_IP_NF_QUEUE=m 302CONFIG_IP_NF_QUEUE=m
278CONFIG_IP_NF_IPTABLES=m 303CONFIG_IP_NF_IPTABLES=m
279CONFIG_IP_NF_MATCH_LIMIT=m
280CONFIG_IP_NF_MATCH_IPRANGE=m
281CONFIG_IP_NF_MATCH_MAC=m
282CONFIG_IP_NF_MATCH_PKTTYPE=m
283CONFIG_IP_NF_MATCH_MARK=m
284CONFIG_IP_NF_MATCH_MULTIPORT=m
285CONFIG_IP_NF_MATCH_TOS=m
286CONFIG_IP_NF_MATCH_RECENT=m 304CONFIG_IP_NF_MATCH_RECENT=m
287CONFIG_IP_NF_MATCH_ECN=m 305CONFIG_IP_NF_MATCH_ECN=m
288CONFIG_IP_NF_MATCH_DSCP=m 306CONFIG_IP_NF_MATCH_AH=m
289CONFIG_IP_NF_MATCH_AH_ESP=m
290CONFIG_IP_NF_MATCH_LENGTH=m
291CONFIG_IP_NF_MATCH_TTL=m 307CONFIG_IP_NF_MATCH_TTL=m
292CONFIG_IP_NF_MATCH_TCPMSS=m
293CONFIG_IP_NF_MATCH_HELPER=m
294CONFIG_IP_NF_MATCH_STATE=m
295CONFIG_IP_NF_MATCH_CONNTRACK=m
296CONFIG_IP_NF_MATCH_OWNER=m
297CONFIG_IP_NF_MATCH_ADDRTYPE=m 308CONFIG_IP_NF_MATCH_ADDRTYPE=m
298CONFIG_IP_NF_MATCH_REALM=m
299# CONFIG_IP_NF_MATCH_SCTP is not set
300# CONFIG_IP_NF_MATCH_COMMENT is not set
301CONFIG_IP_NF_MATCH_CONNMARK=m
302CONFIG_IP_NF_MATCH_HASHLIMIT=m
303CONFIG_IP_NF_FILTER=m 309CONFIG_IP_NF_FILTER=m
304CONFIG_IP_NF_TARGET_REJECT=m 310CONFIG_IP_NF_TARGET_REJECT=m
305CONFIG_IP_NF_TARGET_LOG=m 311CONFIG_IP_NF_TARGET_LOG=m
306CONFIG_IP_NF_TARGET_ULOG=m 312CONFIG_IP_NF_TARGET_ULOG=m
307CONFIG_IP_NF_TARGET_TCPMSS=m 313CONFIG_NF_NAT=m
308CONFIG_IP_NF_NAT=m 314CONFIG_NF_NAT_NEEDED=y
309CONFIG_IP_NF_NAT_NEEDED=y
310CONFIG_IP_NF_TARGET_MASQUERADE=m 315CONFIG_IP_NF_TARGET_MASQUERADE=m
311CONFIG_IP_NF_TARGET_REDIRECT=m 316CONFIG_IP_NF_TARGET_REDIRECT=m
312CONFIG_IP_NF_TARGET_NETMAP=m 317CONFIG_IP_NF_TARGET_NETMAP=m
313CONFIG_IP_NF_TARGET_SAME=m 318CONFIG_NF_NAT_SNMP_BASIC=m
314CONFIG_IP_NF_NAT_SNMP_BASIC=m 319CONFIG_NF_NAT_PROTO_GRE=m
315CONFIG_IP_NF_NAT_IRC=m 320CONFIG_NF_NAT_FTP=m
316CONFIG_IP_NF_NAT_FTP=m 321CONFIG_NF_NAT_IRC=m
317CONFIG_IP_NF_NAT_TFTP=m 322CONFIG_NF_NAT_TFTP=m
318CONFIG_IP_NF_NAT_AMANDA=m 323CONFIG_NF_NAT_AMANDA=m
324CONFIG_NF_NAT_PPTP=m
325CONFIG_NF_NAT_H323=m
326CONFIG_NF_NAT_SIP=m
319CONFIG_IP_NF_MANGLE=m 327CONFIG_IP_NF_MANGLE=m
320CONFIG_IP_NF_TARGET_TOS=m
321CONFIG_IP_NF_TARGET_ECN=m 328CONFIG_IP_NF_TARGET_ECN=m
322CONFIG_IP_NF_TARGET_DSCP=m 329CONFIG_IP_NF_TARGET_TTL=m
323CONFIG_IP_NF_TARGET_MARK=m 330CONFIG_IP_NF_TARGET_CLUSTERIP=m
324CONFIG_IP_NF_TARGET_CLASSIFY=m
325CONFIG_IP_NF_TARGET_CONNMARK=m
326# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
327CONFIG_IP_NF_RAW=m 331CONFIG_IP_NF_RAW=m
328CONFIG_IP_NF_TARGET_NOTRACK=m
329CONFIG_IP_NF_ARPTABLES=m 332CONFIG_IP_NF_ARPTABLES=m
330CONFIG_IP_NF_ARPFILTER=m 333CONFIG_IP_NF_ARPFILTER=m
331CONFIG_IP_NF_ARP_MANGLE=m 334CONFIG_IP_NF_ARP_MANGLE=m
332 335
333# 336#
334# IPv6: Netfilter Configuration (EXPERIMENTAL) 337# IPv6: Netfilter Configuration
335# 338#
339CONFIG_NF_CONNTRACK_IPV6=m
336CONFIG_IP6_NF_QUEUE=m 340CONFIG_IP6_NF_QUEUE=m
337CONFIG_IP6_NF_IPTABLES=m 341CONFIG_IP6_NF_IPTABLES=m
338CONFIG_IP6_NF_MATCH_LIMIT=m
339CONFIG_IP6_NF_MATCH_MAC=m
340CONFIG_IP6_NF_MATCH_RT=m 342CONFIG_IP6_NF_MATCH_RT=m
341CONFIG_IP6_NF_MATCH_OPTS=m 343CONFIG_IP6_NF_MATCH_OPTS=m
342CONFIG_IP6_NF_MATCH_FRAG=m 344CONFIG_IP6_NF_MATCH_FRAG=m
343CONFIG_IP6_NF_MATCH_HL=m 345CONFIG_IP6_NF_MATCH_HL=m
344CONFIG_IP6_NF_MATCH_MULTIPORT=m
345CONFIG_IP6_NF_MATCH_OWNER=m
346CONFIG_IP6_NF_MATCH_MARK=m
347CONFIG_IP6_NF_MATCH_IPV6HEADER=m 346CONFIG_IP6_NF_MATCH_IPV6HEADER=m
348CONFIG_IP6_NF_MATCH_AHESP=m 347CONFIG_IP6_NF_MATCH_AH=m
349CONFIG_IP6_NF_MATCH_LENGTH=m 348CONFIG_IP6_NF_MATCH_MH=m
350CONFIG_IP6_NF_MATCH_EUI64=m 349CONFIG_IP6_NF_MATCH_EUI64=m
351CONFIG_IP6_NF_FILTER=m 350CONFIG_IP6_NF_FILTER=m
352CONFIG_IP6_NF_TARGET_LOG=m 351CONFIG_IP6_NF_TARGET_LOG=m
352CONFIG_IP6_NF_TARGET_REJECT=m
353CONFIG_IP6_NF_MANGLE=m 353CONFIG_IP6_NF_MANGLE=m
354CONFIG_IP6_NF_TARGET_MARK=m 354CONFIG_IP6_NF_TARGET_HL=m
355CONFIG_IP6_NF_RAW=m 355CONFIG_IP6_NF_RAW=m
356CONFIG_XFRM=y 356CONFIG_IP_DCCP=m
357CONFIG_XFRM_USER=m 357CONFIG_INET_DCCP_DIAG=m
358CONFIG_IP_DCCP_ACKVEC=y
358 359
359# 360#
360# SCTP Configuration (EXPERIMENTAL) 361# DCCP CCIDs Configuration (EXPERIMENTAL)
361# 362#
363CONFIG_IP_DCCP_CCID2=m
364# CONFIG_IP_DCCP_CCID2_DEBUG is not set
365CONFIG_IP_DCCP_CCID3=m
366# CONFIG_IP_DCCP_CCID3_DEBUG is not set
367CONFIG_IP_DCCP_CCID3_RTO=100
368CONFIG_IP_DCCP_TFRC_LIB=m
362CONFIG_IP_SCTP=m 369CONFIG_IP_SCTP=m
363# CONFIG_SCTP_DBG_MSG is not set 370# CONFIG_SCTP_DBG_MSG is not set
364# CONFIG_SCTP_DBG_OBJCNT is not set 371# CONFIG_SCTP_DBG_OBJCNT is not set
365# CONFIG_SCTP_HMAC_NONE is not set 372# CONFIG_SCTP_HMAC_NONE is not set
366# CONFIG_SCTP_HMAC_SHA1 is not set 373# CONFIG_SCTP_HMAC_SHA1 is not set
367CONFIG_SCTP_HMAC_MD5=y 374CONFIG_SCTP_HMAC_MD5=y
375# CONFIG_TIPC is not set
368# CONFIG_ATM is not set 376# CONFIG_ATM is not set
369# CONFIG_BRIDGE is not set 377# CONFIG_BRIDGE is not set
370# CONFIG_VLAN_8021Q is not set 378# CONFIG_VLAN_8021Q is not set
371# CONFIG_DECNET is not set 379# CONFIG_DECNET is not set
372CONFIG_LLC=m 380CONFIG_LLC=m
373# CONFIG_LLC2 is not set 381# CONFIG_LLC2 is not set
374CONFIG_IPX=m 382# CONFIG_IPX is not set
375# CONFIG_IPX_INTERN is not set
376CONFIG_ATALK=m 383CONFIG_ATALK=m
377# CONFIG_DEV_APPLETALK is not set 384# CONFIG_DEV_APPLETALK is not set
378# CONFIG_X25 is not set 385# CONFIG_X25 is not set
379# CONFIG_LAPB is not set 386# CONFIG_LAPB is not set
380# CONFIG_NET_DIVERT is not set
381# CONFIG_ECONET is not set 387# CONFIG_ECONET is not set
382# CONFIG_WAN_ROUTER is not set 388# CONFIG_WAN_ROUTER is not set
383
384#
385# QoS and/or fair queueing
386#
387# CONFIG_NET_SCHED is not set 389# CONFIG_NET_SCHED is not set
388CONFIG_NET_CLS_ROUTE=y 390CONFIG_NET_CLS_ROUTE=y
389 391
@@ -391,46 +393,156 @@ CONFIG_NET_CLS_ROUTE=y
391# Network testing 393# Network testing
392# 394#
393# CONFIG_NET_PKTGEN is not set 395# CONFIG_NET_PKTGEN is not set
394CONFIG_NETPOLL=y
395# CONFIG_NETPOLL_RX is not set
396# CONFIG_NETPOLL_TRAP is not set
397CONFIG_NET_POLL_CONTROLLER=y
398# CONFIG_HAMRADIO is not set 396# CONFIG_HAMRADIO is not set
397# CONFIG_CAN is not set
399# CONFIG_IRDA is not set 398# CONFIG_IRDA is not set
400# CONFIG_BT is not set 399# CONFIG_BT is not set
401CONFIG_NETDEVICES=y 400# CONFIG_AF_RXRPC is not set
402CONFIG_DUMMY=m
403# CONFIG_BONDING is not set
404CONFIG_EQUALIZER=m
405# CONFIG_TUN is not set
406 401
407# 402#
408# Ethernet (10 or 100Mbit) 403# Wireless
409# 404#
410CONFIG_NET_ETHERNET=y 405# CONFIG_CFG80211 is not set
411CONFIG_MII=m 406CONFIG_WIRELESS_EXT=y
412CONFIG_MVME16x_NET=y 407# CONFIG_MAC80211 is not set
408CONFIG_IEEE80211=m
409# CONFIG_IEEE80211_DEBUG is not set
410CONFIG_IEEE80211_CRYPT_WEP=m
411CONFIG_IEEE80211_CRYPT_CCMP=m
412CONFIG_IEEE80211_CRYPT_TKIP=m
413CONFIG_IEEE80211_SOFTMAC=m
414# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
415# CONFIG_RFKILL is not set
416# CONFIG_NET_9P is not set
413 417
414# 418#
415# Ethernet (1000 Mbit) 419# Device Drivers
416# 420#
417 421
418# 422#
419# Ethernet (10000 Mbit) 423# Generic Driver Options
420# 424#
425CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430CONFIG_CONNECTOR=m
431# CONFIG_MTD is not set
432# CONFIG_PARPORT is not set
433CONFIG_BLK_DEV=y
434# CONFIG_BLK_DEV_COW_COMMON is not set
435CONFIG_BLK_DEV_LOOP=y
436CONFIG_BLK_DEV_CRYPTOLOOP=m
437CONFIG_BLK_DEV_NBD=m
438CONFIG_BLK_DEV_RAM=y
439CONFIG_BLK_DEV_RAM_COUNT=16
440CONFIG_BLK_DEV_RAM_SIZE=4096
441# CONFIG_BLK_DEV_XIP is not set
442CONFIG_CDROM_PKTCDVD=m
443CONFIG_CDROM_PKTCDVD_BUFFERS=8
444# CONFIG_CDROM_PKTCDVD_WCACHE is not set
445CONFIG_ATA_OVER_ETH=m
446CONFIG_MISC_DEVICES=y
447# CONFIG_EEPROM_93CX6 is not set
448# CONFIG_ENCLOSURE_SERVICES is not set
449CONFIG_HAVE_IDE=y
450# CONFIG_IDE is not set
451
452#
453# SCSI device support
454#
455CONFIG_RAID_ATTRS=m
456CONFIG_SCSI=y
457CONFIG_SCSI_DMA=y
458CONFIG_SCSI_TGT=m
459# CONFIG_SCSI_NETLINK is not set
460CONFIG_SCSI_PROC_FS=y
421 461
422# 462#
423# Token Ring devices 463# SCSI support type (disk, tape, CD-ROM)
424# 464#
465CONFIG_BLK_DEV_SD=y
466CONFIG_CHR_DEV_ST=m
467CONFIG_CHR_DEV_OSST=m
468CONFIG_BLK_DEV_SR=y
469CONFIG_BLK_DEV_SR_VENDOR=y
470CONFIG_CHR_DEV_SG=m
471# CONFIG_CHR_DEV_SCH is not set
425 472
426# 473#
427# Wireless LAN (non-hamradio) 474# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
428# 475#
429# CONFIG_NET_RADIO is not set 476# CONFIG_SCSI_MULTI_LUN is not set
477CONFIG_SCSI_CONSTANTS=y
478# CONFIG_SCSI_LOGGING is not set
479# CONFIG_SCSI_SCAN_ASYNC is not set
480CONFIG_SCSI_WAIT_SCAN=m
430 481
431# 482#
432# Wan interfaces 483# SCSI Transports
484#
485CONFIG_SCSI_SPI_ATTRS=y
486# CONFIG_SCSI_FC_ATTRS is not set
487CONFIG_SCSI_ISCSI_ATTRS=m
488CONFIG_SCSI_SAS_ATTRS=m
489CONFIG_SCSI_SAS_LIBSAS=m
490CONFIG_SCSI_SAS_HOST_SMP=y
491# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
492CONFIG_SCSI_SRP_ATTRS=m
493CONFIG_SCSI_SRP_TGT_ATTRS=y
494CONFIG_SCSI_LOWLEVEL=y
495CONFIG_ISCSI_TCP=m
496CONFIG_53C700_BE_BUS=y
497# CONFIG_SCSI_DEBUG is not set
498CONFIG_MVME16x_SCSI=y
499CONFIG_MD=y
500CONFIG_BLK_DEV_MD=m
501CONFIG_MD_LINEAR=m
502CONFIG_MD_RAID0=m
503CONFIG_MD_RAID1=m
504# CONFIG_MD_RAID10 is not set
505CONFIG_MD_RAID456=m
506CONFIG_MD_RAID5_RESHAPE=y
507CONFIG_MD_MULTIPATH=m
508# CONFIG_MD_FAULTY is not set
509CONFIG_BLK_DEV_DM=m
510# CONFIG_DM_DEBUG is not set
511CONFIG_DM_CRYPT=m
512CONFIG_DM_SNAPSHOT=m
513CONFIG_DM_MIRROR=m
514CONFIG_DM_ZERO=m
515CONFIG_DM_MULTIPATH=m
516CONFIG_DM_MULTIPATH_EMC=m
517CONFIG_DM_MULTIPATH_RDAC=m
518CONFIG_DM_MULTIPATH_HP=m
519# CONFIG_DM_DELAY is not set
520CONFIG_DM_UEVENT=y
521CONFIG_NETDEVICES=y
522# CONFIG_NETDEVICES_MULTIQUEUE is not set
523CONFIG_DUMMY=m
524# CONFIG_BONDING is not set
525CONFIG_MACVLAN=m
526CONFIG_EQUALIZER=m
527# CONFIG_TUN is not set
528CONFIG_VETH=m
529# CONFIG_PHYLIB is not set
530CONFIG_NET_ETHERNET=y
531# CONFIG_MII is not set
532CONFIG_MVME16x_NET=y
533# CONFIG_IBM_NEW_EMAC_ZMII is not set
534# CONFIG_IBM_NEW_EMAC_RGMII is not set
535# CONFIG_IBM_NEW_EMAC_TAH is not set
536# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
537# CONFIG_B44 is not set
538# CONFIG_NETDEV_1000 is not set
539# CONFIG_NETDEV_10000 is not set
540
433# 541#
542# Wireless LAN
543#
544# CONFIG_WLAN_PRE80211 is not set
545# CONFIG_WLAN_80211 is not set
434# CONFIG_WAN is not set 546# CONFIG_WAN is not set
435CONFIG_PPP=m 547CONFIG_PPP=m
436# CONFIG_PPP_MULTILINK is not set 548# CONFIG_PPP_MULTILINK is not set
@@ -439,28 +551,28 @@ CONFIG_PPP_ASYNC=m
439CONFIG_PPP_SYNC_TTY=m 551CONFIG_PPP_SYNC_TTY=m
440CONFIG_PPP_DEFLATE=m 552CONFIG_PPP_DEFLATE=m
441CONFIG_PPP_BSDCOMP=m 553CONFIG_PPP_BSDCOMP=m
554CONFIG_PPP_MPPE=m
442CONFIG_PPPOE=m 555CONFIG_PPPOE=m
556CONFIG_PPPOL2TP=m
443CONFIG_SLIP=m 557CONFIG_SLIP=m
444CONFIG_SLIP_COMPRESSED=y 558CONFIG_SLIP_COMPRESSED=y
559CONFIG_SLHC=m
445CONFIG_SLIP_SMART=y 560CONFIG_SLIP_SMART=y
446CONFIG_SLIP_MODE_SLIP6=y 561CONFIG_SLIP_MODE_SLIP6=y
447CONFIG_SHAPER=m
448CONFIG_NETCONSOLE=m 562CONFIG_NETCONSOLE=m
449 563CONFIG_NETCONSOLE_DYNAMIC=y
450# 564CONFIG_NETPOLL=y
451# ISDN subsystem 565# CONFIG_NETPOLL_TRAP is not set
452# 566CONFIG_NET_POLL_CONTROLLER=y
453# CONFIG_ISDN is not set 567# CONFIG_ISDN is not set
454
455#
456# Telephony Support
457#
458# CONFIG_PHONE is not set 568# CONFIG_PHONE is not set
459 569
460# 570#
461# Input device support 571# Input device support
462# 572#
463CONFIG_INPUT=y 573CONFIG_INPUT=y
574CONFIG_INPUT_FF_MEMLESS=m
575# CONFIG_INPUT_POLLDEV is not set
464 576
465# 577#
466# Userland interfaces 578# Userland interfaces
@@ -470,7 +582,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
470CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 582CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
471CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 583CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
472# CONFIG_INPUT_JOYDEV is not set 584# CONFIG_INPUT_JOYDEV is not set
473# CONFIG_INPUT_TSDEV is not set
474# CONFIG_INPUT_EVDEV is not set 585# CONFIG_INPUT_EVDEV is not set
475# CONFIG_INPUT_EVBUG is not set 586# CONFIG_INPUT_EVBUG is not set
476 587
@@ -483,11 +594,19 @@ CONFIG_INPUT_KEYBOARD=y
483# CONFIG_KEYBOARD_LKKBD is not set 594# CONFIG_KEYBOARD_LKKBD is not set
484# CONFIG_KEYBOARD_XTKBD is not set 595# CONFIG_KEYBOARD_XTKBD is not set
485# CONFIG_KEYBOARD_NEWTON is not set 596# CONFIG_KEYBOARD_NEWTON is not set
597# CONFIG_KEYBOARD_STOWAWAY is not set
486CONFIG_INPUT_MOUSE=y 598CONFIG_INPUT_MOUSE=y
487CONFIG_MOUSE_PS2=m 599CONFIG_MOUSE_PS2=m
600CONFIG_MOUSE_PS2_ALPS=y
601CONFIG_MOUSE_PS2_LOGIPS2PP=y
602CONFIG_MOUSE_PS2_SYNAPTICS=y
603CONFIG_MOUSE_PS2_LIFEBOOK=y
604CONFIG_MOUSE_PS2_TRACKPOINT=y
605# CONFIG_MOUSE_PS2_TOUCHKIT is not set
488CONFIG_MOUSE_SERIAL=m 606CONFIG_MOUSE_SERIAL=m
489# CONFIG_MOUSE_VSXXXAA is not set 607# CONFIG_MOUSE_VSXXXAA is not set
490# CONFIG_INPUT_JOYSTICK is not set 608# CONFIG_INPUT_JOYSTICK is not set
609# CONFIG_INPUT_TABLET is not set
491# CONFIG_INPUT_TOUCHSCREEN is not set 610# CONFIG_INPUT_TOUCHSCREEN is not set
492# CONFIG_INPUT_MISC is not set 611# CONFIG_INPUT_MISC is not set
493 612
@@ -495,7 +614,7 @@ CONFIG_MOUSE_SERIAL=m
495# Hardware I/O ports 614# Hardware I/O ports
496# 615#
497CONFIG_SERIO=m 616CONFIG_SERIO=m
498CONFIG_SERIO_SERPORT=m 617# CONFIG_SERIO_SERPORT is not set
499CONFIG_SERIO_LIBPS2=m 618CONFIG_SERIO_LIBPS2=m
500# CONFIG_SERIO_RAW is not set 619# CONFIG_SERIO_RAW is not set
501# CONFIG_GAMEPORT is not set 620# CONFIG_GAMEPORT is not set
@@ -506,6 +625,7 @@ CONFIG_SERIO_LIBPS2=m
506CONFIG_VT=y 625CONFIG_VT=y
507CONFIG_VT_CONSOLE=y 626CONFIG_VT_CONSOLE=y
508CONFIG_HW_CONSOLE=y 627CONFIG_HW_CONSOLE=y
628CONFIG_VT_HW_CONSOLE_BINDING=y
509# CONFIG_SERIAL_NONSTANDARD is not set 629# CONFIG_SERIAL_NONSTANDARD is not set
510 630
511# 631#
@@ -519,116 +639,85 @@ CONFIG_HW_CONSOLE=y
519CONFIG_UNIX98_PTYS=y 639CONFIG_UNIX98_PTYS=y
520CONFIG_LEGACY_PTYS=y 640CONFIG_LEGACY_PTYS=y
521CONFIG_LEGACY_PTY_COUNT=256 641CONFIG_LEGACY_PTY_COUNT=256
522
523#
524# IPMI
525#
526# CONFIG_IPMI_HANDLER is not set 642# CONFIG_IPMI_HANDLER is not set
527 643# CONFIG_HW_RANDOM is not set
528#
529# Watchdog Cards
530#
531# CONFIG_WATCHDOG is not set
532CONFIG_GEN_RTC=m 644CONFIG_GEN_RTC=m
533CONFIG_GEN_RTC_X=y 645CONFIG_GEN_RTC_X=y
534# CONFIG_DTLK is not set
535# CONFIG_R3964 is not set 646# CONFIG_R3964 is not set
536
537#
538# Ftape, the floppy tape device driver
539#
540# CONFIG_DRM is not set
541# CONFIG_RAW_DRIVER is not set 647# CONFIG_RAW_DRIVER is not set
648# CONFIG_TCG_TPM is not set
649# CONFIG_I2C is not set
542 650
543# 651#
544# TPM devices 652# SPI support
545# 653#
654# CONFIG_SPI is not set
655# CONFIG_SPI_MASTER is not set
656# CONFIG_W1 is not set
657# CONFIG_POWER_SUPPLY is not set
658# CONFIG_HWMON is not set
659# CONFIG_THERMAL is not set
660# CONFIG_WATCHDOG is not set
546 661
547# 662#
548# I2C support 663# Sonics Silicon Backplane
549# 664#
550# CONFIG_I2C is not set 665CONFIG_SSB_POSSIBLE=y
666# CONFIG_SSB is not set
551 667
552# 668#
553# Dallas's 1-wire bus 669# Multifunction device drivers
554#
555# CONFIG_W1 is not set
556
557#
558# Misc devices
559# 670#
671# CONFIG_MFD_SM501 is not set
560 672
561# 673#
562# Multimedia devices 674# Multimedia devices
563# 675#
564# CONFIG_VIDEO_DEV is not set 676# CONFIG_VIDEO_DEV is not set
677# CONFIG_DVB_CORE is not set
678# CONFIG_DAB is not set
565 679
566# 680#
567# Digital Video Broadcasting Devices 681# Graphics support
568# 682#
569# CONFIG_DVB is not set 683# CONFIG_VGASTATE is not set
684# CONFIG_VIDEO_OUTPUT_CONTROL is not set
685# CONFIG_FB is not set
686# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
570 687
571# 688#
572# Graphics support 689# Display device support
573# 690#
574CONFIG_FB=y 691# CONFIG_DISPLAY_SUPPORT is not set
575# CONFIG_FB_CFB_FILLRECT is not set
576# CONFIG_FB_CFB_COPYAREA is not set
577# CONFIG_FB_CFB_IMAGEBLIT is not set
578# CONFIG_FB_SOFT_CURSOR is not set
579# CONFIG_FB_MACMODES is not set
580CONFIG_FB_MODE_HELPERS=y
581# CONFIG_FB_TILEBLITTING is not set
582# CONFIG_FB_S1D13XXX is not set
583# CONFIG_FB_VIRTUAL is not set
584 692
585# 693#
586# Console display driver support 694# Console display driver support
587# 695#
588CONFIG_DUMMY_CONSOLE=y 696CONFIG_DUMMY_CONSOLE=y
589CONFIG_FRAMEBUFFER_CONSOLE=y
590# CONFIG_FONTS is not set
591CONFIG_FONT_8x8=y
592CONFIG_FONT_8x16=y
593
594#
595# Logo configuration
596#
597CONFIG_LOGO=y
598CONFIG_LOGO_LINUX_MONO=y
599CONFIG_LOGO_LINUX_VGA16=y
600CONFIG_LOGO_LINUX_CLUT224=y
601# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
602 697
603# 698#
604# Sound 699# Sound
605# 700#
606# CONFIG_SOUND is not set 701# CONFIG_SOUND is not set
607 702CONFIG_HID_SUPPORT=y
608# 703CONFIG_HID=m
609# USB support 704# CONFIG_HID_DEBUG is not set
610# 705CONFIG_HIDRAW=y
611# CONFIG_USB_ARCH_HAS_HCD is not set 706# CONFIG_USB_SUPPORT is not set
612# CONFIG_USB_ARCH_HAS_OHCI is not set
613
614#
615# USB Gadget Support
616#
617# CONFIG_USB_GADGET is not set
618
619#
620# MMC/SD Card support
621#
622# CONFIG_MMC is not set 707# CONFIG_MMC is not set
708# CONFIG_MEMSTICK is not set
709# CONFIG_NEW_LEDS is not set
710# CONFIG_RTC_CLASS is not set
623 711
624# 712#
625# InfiniBand support 713# Userspace I/O
626# 714#
627# CONFIG_INFINIBAND is not set 715# CONFIG_UIO is not set
628 716
629# 717#
630# Character devices 718# Character devices
631# 719#
720CONFIG_SERIAL167=y
632CONFIG_MVME162_SCC=y 721CONFIG_MVME162_SCC=y
633CONFIG_SERIAL_CONSOLE=y 722CONFIG_SERIAL_CONSOLE=y
634 723
@@ -637,10 +726,11 @@ CONFIG_SERIAL_CONSOLE=y
637# 726#
638CONFIG_EXT2_FS=y 727CONFIG_EXT2_FS=y
639# CONFIG_EXT2_FS_XATTR is not set 728# CONFIG_EXT2_FS_XATTR is not set
729# CONFIG_EXT2_FS_XIP is not set
640CONFIG_EXT3_FS=y 730CONFIG_EXT3_FS=y
641# CONFIG_EXT3_FS_XATTR is not set 731# CONFIG_EXT3_FS_XATTR is not set
732# CONFIG_EXT4DEV_FS is not set
642CONFIG_JBD=y 733CONFIG_JBD=y
643# CONFIG_JBD_DEBUG is not set
644CONFIG_REISERFS_FS=m 734CONFIG_REISERFS_FS=m
645# CONFIG_REISERFS_CHECK is not set 735# CONFIG_REISERFS_CHECK is not set
646# CONFIG_REISERFS_PROC_INFO is not set 736# CONFIG_REISERFS_PROC_INFO is not set
@@ -651,25 +741,29 @@ CONFIG_JFS_FS=m
651# CONFIG_JFS_DEBUG is not set 741# CONFIG_JFS_DEBUG is not set
652# CONFIG_JFS_STATISTICS is not set 742# CONFIG_JFS_STATISTICS is not set
653CONFIG_FS_POSIX_ACL=y 743CONFIG_FS_POSIX_ACL=y
654
655#
656# XFS support
657#
658CONFIG_XFS_FS=m 744CONFIG_XFS_FS=m
659CONFIG_XFS_EXPORT=y
660# CONFIG_XFS_RT is not set
661# CONFIG_XFS_QUOTA is not set 745# CONFIG_XFS_QUOTA is not set
662# CONFIG_XFS_SECURITY is not set 746# CONFIG_XFS_SECURITY is not set
663# CONFIG_XFS_POSIX_ACL is not set 747# CONFIG_XFS_POSIX_ACL is not set
664CONFIG_MINIX_FS=y 748# CONFIG_XFS_RT is not set
665# CONFIG_ROMFS_FS is not set 749CONFIG_GFS2_FS=m
750CONFIG_GFS2_FS_LOCKING_NOLOCK=m
751CONFIG_GFS2_FS_LOCKING_DLM=m
752CONFIG_OCFS2_FS=m
753# CONFIG_OCFS2_DEBUG_MASKLOG is not set
754# CONFIG_OCFS2_DEBUG_FS is not set
755CONFIG_DNOTIFY=y
756CONFIG_INOTIFY=y
757CONFIG_INOTIFY_USER=y
666CONFIG_QUOTA=y 758CONFIG_QUOTA=y
759CONFIG_QUOTA_NETLINK_INTERFACE=y
760# CONFIG_PRINT_QUOTA_WARNING is not set
667# CONFIG_QFMT_V1 is not set 761# CONFIG_QFMT_V1 is not set
668# CONFIG_QFMT_V2 is not set 762# CONFIG_QFMT_V2 is not set
669CONFIG_QUOTACTL=y 763CONFIG_QUOTACTL=y
670CONFIG_DNOTIFY=y
671CONFIG_AUTOFS_FS=m 764CONFIG_AUTOFS_FS=m
672CONFIG_AUTOFS4_FS=m 765CONFIG_AUTOFS4_FS=m
766CONFIG_FUSE_FS=m
673 767
674# 768#
675# CD-ROM/DVD Filesystems 769# CD-ROM/DVD Filesystems
@@ -677,7 +771,6 @@ CONFIG_AUTOFS4_FS=m
677CONFIG_ISO9660_FS=y 771CONFIG_ISO9660_FS=y
678CONFIG_JOLIET=y 772CONFIG_JOLIET=y
679CONFIG_ZISOFS=y 773CONFIG_ZISOFS=y
680CONFIG_ZISOFS_FS=y
681CONFIG_UDF_FS=m 774CONFIG_UDF_FS=m
682CONFIG_UDF_NLS=y 775CONFIG_UDF_NLS=y
683 776
@@ -696,15 +789,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
696# 789#
697CONFIG_PROC_FS=y 790CONFIG_PROC_FS=y
698CONFIG_PROC_KCORE=y 791CONFIG_PROC_KCORE=y
792CONFIG_PROC_SYSCTL=y
699CONFIG_SYSFS=y 793CONFIG_SYSFS=y
700CONFIG_DEVFS_FS=y
701# CONFIG_DEVFS_MOUNT is not set
702# CONFIG_DEVFS_DEBUG is not set
703# CONFIG_DEVPTS_FS_XATTR is not set
704CONFIG_TMPFS=y 794CONFIG_TMPFS=y
705# CONFIG_TMPFS_XATTR is not set 795# CONFIG_TMPFS_POSIX_ACL is not set
706# CONFIG_HUGETLB_PAGE is not set 796# CONFIG_HUGETLB_PAGE is not set
707CONFIG_RAMFS=y 797CONFIG_CONFIGFS_FS=m
708 798
709# 799#
710# Miscellaneous filesystems 800# Miscellaneous filesystems
@@ -718,44 +808,40 @@ CONFIG_HFSPLUS_FS=m
718# CONFIG_EFS_FS is not set 808# CONFIG_EFS_FS is not set
719CONFIG_CRAMFS=m 809CONFIG_CRAMFS=m
720# CONFIG_VXFS_FS is not set 810# CONFIG_VXFS_FS is not set
811CONFIG_MINIX_FS=y
721CONFIG_HPFS_FS=m 812CONFIG_HPFS_FS=m
722# CONFIG_QNX4FS_FS is not set 813# CONFIG_QNX4FS_FS is not set
814# CONFIG_ROMFS_FS is not set
723CONFIG_SYSV_FS=m 815CONFIG_SYSV_FS=m
724CONFIG_UFS_FS=m 816CONFIG_UFS_FS=m
725# CONFIG_UFS_FS_WRITE is not set 817# CONFIG_UFS_FS_WRITE is not set
726 818# CONFIG_UFS_DEBUG is not set
727# 819CONFIG_NETWORK_FILESYSTEMS=y
728# Network File Systems
729#
730CONFIG_NFS_FS=y 820CONFIG_NFS_FS=y
731CONFIG_NFS_V3=y 821CONFIG_NFS_V3=y
822# CONFIG_NFS_V3_ACL is not set
732CONFIG_NFS_V4=y 823CONFIG_NFS_V4=y
733# CONFIG_NFS_DIRECTIO is not set 824# CONFIG_NFS_DIRECTIO is not set
734CONFIG_NFSD=m 825CONFIG_NFSD=m
735CONFIG_NFSD_V3=y 826CONFIG_NFSD_V3=y
736CONFIG_NFSD_V4=y 827# CONFIG_NFSD_V3_ACL is not set
828# CONFIG_NFSD_V4 is not set
737CONFIG_NFSD_TCP=y 829CONFIG_NFSD_TCP=y
738CONFIG_ROOT_NFS=y 830CONFIG_ROOT_NFS=y
739CONFIG_LOCKD=y 831CONFIG_LOCKD=y
740CONFIG_LOCKD_V4=y 832CONFIG_LOCKD_V4=y
741CONFIG_EXPORTFS=m 833CONFIG_EXPORTFS=m
834CONFIG_NFS_COMMON=y
742CONFIG_SUNRPC=y 835CONFIG_SUNRPC=y
743CONFIG_SUNRPC_GSS=y 836CONFIG_SUNRPC_GSS=y
837CONFIG_SUNRPC_BIND34=y
744CONFIG_RPCSEC_GSS_KRB5=y 838CONFIG_RPCSEC_GSS_KRB5=y
745# CONFIG_RPCSEC_GSS_SPKM3 is not set 839# CONFIG_RPCSEC_GSS_SPKM3 is not set
746CONFIG_SMB_FS=m 840CONFIG_SMB_FS=m
747CONFIG_SMB_NLS_DEFAULT=y 841CONFIG_SMB_NLS_DEFAULT=y
748CONFIG_SMB_NLS_REMOTE="cp437" 842CONFIG_SMB_NLS_REMOTE="cp437"
749# CONFIG_CIFS is not set 843# CONFIG_CIFS is not set
750CONFIG_NCP_FS=m 844# CONFIG_NCP_FS is not set
751# CONFIG_NCPFS_PACKET_SIGNING is not set
752# CONFIG_NCPFS_IOCTL_LOCKING is not set
753# CONFIG_NCPFS_STRONG is not set
754# CONFIG_NCPFS_NFS_NS is not set
755# CONFIG_NCPFS_OS2_NS is not set
756# CONFIG_NCPFS_SMALLDOS is not set
757CONFIG_NCPFS_NLS=y
758# CONFIG_NCPFS_EXTRAS is not set
759CONFIG_CODA_FS=m 845CONFIG_CODA_FS=m
760# CONFIG_CODA_FS_OLD_API is not set 846# CONFIG_CODA_FS_OLD_API is not set
761# CONFIG_AFS_FS is not set 847# CONFIG_AFS_FS is not set
@@ -765,10 +851,7 @@ CONFIG_CODA_FS=m
765# 851#
766# CONFIG_PARTITION_ADVANCED is not set 852# CONFIG_PARTITION_ADVANCED is not set
767CONFIG_MSDOS_PARTITION=y 853CONFIG_MSDOS_PARTITION=y
768 854CONFIG_SYSV68_PARTITION=y
769#
770# Native Language Support
771#
772CONFIG_NLS=y 855CONFIG_NLS=y
773CONFIG_NLS_DEFAULT="iso8859-1" 856CONFIG_NLS_DEFAULT="iso8859-1"
774CONFIG_NLS_CODEPAGE_437=y 857CONFIG_NLS_CODEPAGE_437=y
@@ -809,35 +892,42 @@ CONFIG_NLS_ISO8859_15=m
809CONFIG_NLS_KOI8_R=m 892CONFIG_NLS_KOI8_R=m
810CONFIG_NLS_KOI8_U=m 893CONFIG_NLS_KOI8_U=m
811CONFIG_NLS_UTF8=m 894CONFIG_NLS_UTF8=m
895CONFIG_DLM=m
896# CONFIG_DLM_DEBUG is not set
812 897
813# 898#
814# Kernel hacking 899# Kernel hacking
815# 900#
816# CONFIG_PRINTK_TIME is not set 901# CONFIG_PRINTK_TIME is not set
817CONFIG_DEBUG_KERNEL=y 902CONFIG_ENABLE_WARN_DEPRECATED=y
903CONFIG_ENABLE_MUST_CHECK=y
818CONFIG_MAGIC_SYSRQ=y 904CONFIG_MAGIC_SYSRQ=y
819CONFIG_LOG_BUF_SHIFT=16 905# CONFIG_UNUSED_SYMBOLS is not set
820# CONFIG_SCHEDSTATS is not set
821# CONFIG_DEBUG_SLAB is not set
822# CONFIG_DEBUG_SPINLOCK is not set
823# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
824# CONFIG_DEBUG_KOBJECT is not set
825CONFIG_DEBUG_BUGVERBOSE=y
826# CONFIG_DEBUG_INFO is not set
827# CONFIG_DEBUG_FS is not set 906# CONFIG_DEBUG_FS is not set
828# CONFIG_FRAME_POINTER is not set 907# CONFIG_HEADERS_CHECK is not set
908# CONFIG_DEBUG_KERNEL is not set
909CONFIG_DEBUG_BUGVERBOSE=y
910# CONFIG_SAMPLES is not set
829 911
830# 912#
831# Security options 913# Security options
832# 914#
833# CONFIG_KEYS is not set 915# CONFIG_KEYS is not set
834# CONFIG_SECURITY is not set 916# CONFIG_SECURITY is not set
835 917# CONFIG_SECURITY_FILE_CAPABILITIES is not set
836# 918CONFIG_XOR_BLOCKS=m
837# Cryptographic options 919CONFIG_ASYNC_CORE=m
838# 920CONFIG_ASYNC_MEMCPY=m
921CONFIG_ASYNC_XOR=m
839CONFIG_CRYPTO=y 922CONFIG_CRYPTO=y
923CONFIG_CRYPTO_ALGAPI=y
924CONFIG_CRYPTO_AEAD=m
925CONFIG_CRYPTO_BLKCIPHER=y
926CONFIG_CRYPTO_SEQIV=m
927CONFIG_CRYPTO_HASH=y
928CONFIG_CRYPTO_MANAGER=y
840CONFIG_CRYPTO_HMAC=y 929CONFIG_CRYPTO_HMAC=y
930CONFIG_CRYPTO_XCBC=m
841CONFIG_CRYPTO_NULL=m 931CONFIG_CRYPTO_NULL=m
842CONFIG_CRYPTO_MD4=m 932CONFIG_CRYPTO_MD4=m
843CONFIG_CRYPTO_MD5=y 933CONFIG_CRYPTO_MD5=y
@@ -846,9 +936,21 @@ CONFIG_CRYPTO_SHA256=m
846CONFIG_CRYPTO_SHA512=m 936CONFIG_CRYPTO_SHA512=m
847CONFIG_CRYPTO_WP512=m 937CONFIG_CRYPTO_WP512=m
848CONFIG_CRYPTO_TGR192=m 938CONFIG_CRYPTO_TGR192=m
939CONFIG_CRYPTO_GF128MUL=m
940CONFIG_CRYPTO_ECB=m
941CONFIG_CRYPTO_CBC=y
942CONFIG_CRYPTO_PCBC=m
943CONFIG_CRYPTO_LRW=m
944CONFIG_CRYPTO_XTS=m
945CONFIG_CRYPTO_CTR=m
946CONFIG_CRYPTO_GCM=m
947CONFIG_CRYPTO_CCM=m
948CONFIG_CRYPTO_CRYPTD=m
849CONFIG_CRYPTO_DES=y 949CONFIG_CRYPTO_DES=y
950CONFIG_CRYPTO_FCRYPT=m
850CONFIG_CRYPTO_BLOWFISH=m 951CONFIG_CRYPTO_BLOWFISH=m
851CONFIG_CRYPTO_TWOFISH=m 952CONFIG_CRYPTO_TWOFISH=m
953CONFIG_CRYPTO_TWOFISH_COMMON=m
852CONFIG_CRYPTO_SERPENT=m 954CONFIG_CRYPTO_SERPENT=m
853CONFIG_CRYPTO_AES=m 955CONFIG_CRYPTO_AES=m
854CONFIG_CRYPTO_CAST5=m 956CONFIG_CRYPTO_CAST5=m
@@ -857,20 +959,35 @@ CONFIG_CRYPTO_TEA=m
857CONFIG_CRYPTO_ARC4=m 959CONFIG_CRYPTO_ARC4=m
858CONFIG_CRYPTO_KHAZAD=m 960CONFIG_CRYPTO_KHAZAD=m
859CONFIG_CRYPTO_ANUBIS=m 961CONFIG_CRYPTO_ANUBIS=m
962CONFIG_CRYPTO_SEED=m
963CONFIG_CRYPTO_SALSA20=m
860CONFIG_CRYPTO_DEFLATE=m 964CONFIG_CRYPTO_DEFLATE=m
861CONFIG_CRYPTO_MICHAEL_MIC=m 965CONFIG_CRYPTO_MICHAEL_MIC=m
862CONFIG_CRYPTO_CRC32C=m 966CONFIG_CRYPTO_CRC32C=m
967CONFIG_CRYPTO_CAMELLIA=m
863CONFIG_CRYPTO_TEST=m 968CONFIG_CRYPTO_TEST=m
864 969CONFIG_CRYPTO_AUTHENC=m
865# 970CONFIG_CRYPTO_LZO=m
866# Hardware crypto devices 971# CONFIG_CRYPTO_HW is not set
867#
868 972
869# 973#
870# Library routines 974# Library routines
871# 975#
976CONFIG_BITREVERSE=y
872CONFIG_CRC_CCITT=m 977CONFIG_CRC_CCITT=m
978CONFIG_CRC16=m
979# CONFIG_CRC_ITU_T is not set
873CONFIG_CRC32=y 980CONFIG_CRC32=y
981# CONFIG_CRC7 is not set
874CONFIG_LIBCRC32C=m 982CONFIG_LIBCRC32C=m
875CONFIG_ZLIB_INFLATE=y 983CONFIG_ZLIB_INFLATE=y
876CONFIG_ZLIB_DEFLATE=m 984CONFIG_ZLIB_DEFLATE=m
985CONFIG_LZO_COMPRESS=m
986CONFIG_LZO_DECOMPRESS=m
987CONFIG_TEXTSEARCH=y
988CONFIG_TEXTSEARCH_KMP=m
989CONFIG_TEXTSEARCH_BM=m
990CONFIG_TEXTSEARCH_FSM=m
991CONFIG_PLIST=y
992CONFIG_HAS_IOMEM=y
993CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 856238634d4..165658fe73e 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -1,63 +1,112 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:34:58 2005 4# Wed Apr 2 20:46:20 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_ARCH_MAY_HAVE_PC_FDC=y
16CONFIG_NO_IOPORT=y
17# CONFIG_NO_DMA is not set
18CONFIG_ARCH_SUPPORTS_AOUT=y
19CONFIG_HZ=100
20CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 21
12# 22#
13# Code maturity level options 23# General setup
14# 24#
15CONFIG_EXPERIMENTAL=y 25CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 26CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 27CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-q40" 28CONFIG_LOCALVERSION="-q40"
29CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 30CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 31CONFIG_SYSVIPC=y
32CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 33CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 34CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 35# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 36# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 37# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 38# CONFIG_IKCONFIG is not set
39CONFIG_LOG_BUF_SHIFT=14
40# CONFIG_CGROUPS is not set
41# CONFIG_GROUP_SCHED is not set
42# CONFIG_SYSFS_DEPRECATED_V2 is not set
43CONFIG_RELAY=y
44CONFIG_NAMESPACES=y
45# CONFIG_UTS_NS is not set
46# CONFIG_IPC_NS is not set
47# CONFIG_USER_NS is not set
48# CONFIG_PID_NS is not set
49CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE=""
51# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
52CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 53# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 56CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 57# CONFIG_KALLSYMS_EXTRA_PASS is not set
58CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 59CONFIG_PRINTK=y
39CONFIG_BUG=y 60CONFIG_BUG=y
61CONFIG_ELF_CORE=y
62# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 63CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 64CONFIG_FUTEX=y
65CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 66CONFIG_EPOLL=y
67CONFIG_SIGNALFD=y
68CONFIG_TIMERFD=y
69CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 70CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 71CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 72CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 73# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 74# CONFIG_SLOB is not set
75# CONFIG_PROFILING is not set
76# CONFIG_MARKERS is not set
77# CONFIG_HAVE_OPROFILE is not set
78# CONFIG_HAVE_KPROBES is not set
79# CONFIG_HAVE_KRETPROBES is not set
80CONFIG_PROC_PAGE_MONITOR=y
81CONFIG_SLABINFO=y
82CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 83# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 84CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 85CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 86CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 87# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 88# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 89# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 90CONFIG_KMOD=y
91CONFIG_BLOCK=y
92# CONFIG_LBD is not set
93# CONFIG_BLK_DEV_IO_TRACE is not set
94# CONFIG_LSF is not set
95CONFIG_BLK_DEV_BSG=y
96
97#
98# IO Schedulers
99#
100CONFIG_IOSCHED_NOOP=y
101CONFIG_IOSCHED_AS=y
102CONFIG_IOSCHED_DEADLINE=y
103CONFIG_IOSCHED_CFQ=y
104CONFIG_DEFAULT_AS=y
105# CONFIG_DEFAULT_DEADLINE is not set
106# CONFIG_DEFAULT_CFQ is not set
107# CONFIG_DEFAULT_NOOP is not set
108CONFIG_DEFAULT_IOSCHED="anticipatory"
109CONFIG_CLASSIC_RCU=y
61 110
62# 111#
63# Platform dependent setup 112# Platform dependent setup
@@ -80,10 +129,24 @@ CONFIG_Q40=y
80CONFIG_M68040=y 129CONFIG_M68040=y
81CONFIG_M68060=y 130CONFIG_M68060=y
82CONFIG_MMU_MOTOROLA=y 131CONFIG_MMU_MOTOROLA=y
83CONFIG_M68KFPU_EMU=y 132# CONFIG_M68KFPU_EMU is not set
84CONFIG_M68KFPU_EMU_EXTRAPREC=y
85# CONFIG_M68KFPU_EMU_ONLY is not set
86# CONFIG_ADVANCED is not set 133# CONFIG_ADVANCED is not set
134CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
135CONFIG_NODES_SHIFT=3
136CONFIG_SELECT_MEMORY_MODEL=y
137# CONFIG_FLATMEM_MANUAL is not set
138CONFIG_DISCONTIGMEM_MANUAL=y
139# CONFIG_SPARSEMEM_MANUAL is not set
140CONFIG_DISCONTIGMEM=y
141CONFIG_FLAT_NODE_MEM_MAP=y
142CONFIG_NEED_MULTIPLE_NODES=y
143# CONFIG_SPARSEMEM_STATIC is not set
144# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
145CONFIG_SPLIT_PTLOCK_CPUS=4
146# CONFIG_RESOURCES_64BIT is not set
147CONFIG_ZONE_DMA_FLAG=1
148CONFIG_BOUNCE=y
149CONFIG_VIRT_TO_BUS=y
87 150
88# 151#
89# General setup 152# General setup
@@ -91,41 +154,282 @@ CONFIG_M68KFPU_EMU_EXTRAPREC=y
91CONFIG_BINFMT_ELF=y 154CONFIG_BINFMT_ELF=y
92CONFIG_BINFMT_AOUT=m 155CONFIG_BINFMT_AOUT=m
93CONFIG_BINFMT_MISC=m 156CONFIG_BINFMT_MISC=m
94# CONFIG_HEARTBEAT is not set 157CONFIG_HEARTBEAT=y
95CONFIG_PROC_HARDWARE=y 158CONFIG_PROC_HARDWARE=y
96CONFIG_ISA=y 159CONFIG_ISA=y
97CONFIG_GENERIC_ISA_DMA=y 160CONFIG_GENERIC_ISA_DMA=y
161CONFIG_ZONE_DMA=y
162# CONFIG_ARCH_SUPPORTS_MSI is not set
98 163
99# 164#
100# Device Drivers 165# Networking
101# 166#
167CONFIG_NET=y
102 168
103# 169#
104# Generic Driver Options 170# Networking options
105# 171#
106CONFIG_STANDALONE=y 172CONFIG_PACKET=y
107CONFIG_PREVENT_FIRMWARE_BUILD=y 173# CONFIG_PACKET_MMAP is not set
108CONFIG_FW_LOADER=m 174CONFIG_UNIX=y
109# CONFIG_DEBUG_DRIVER is not set 175CONFIG_XFRM=y
176# CONFIG_XFRM_USER is not set
177# CONFIG_XFRM_SUB_POLICY is not set
178CONFIG_XFRM_MIGRATE=y
179# CONFIG_XFRM_STATISTICS is not set
180CONFIG_NET_KEY=y
181CONFIG_NET_KEY_MIGRATE=y
182CONFIG_INET=y
183# CONFIG_IP_MULTICAST is not set
184# CONFIG_IP_ADVANCED_ROUTER is not set
185CONFIG_IP_FIB_HASH=y
186# CONFIG_IP_PNP is not set
187CONFIG_NET_IPIP=m
188CONFIG_NET_IPGRE=m
189# CONFIG_ARPD is not set
190CONFIG_SYN_COOKIES=y
191CONFIG_INET_AH=m
192CONFIG_INET_ESP=m
193CONFIG_INET_IPCOMP=m
194CONFIG_INET_XFRM_TUNNEL=m
195CONFIG_INET_TUNNEL=m
196CONFIG_INET_XFRM_MODE_TRANSPORT=m
197CONFIG_INET_XFRM_MODE_TUNNEL=m
198CONFIG_INET_XFRM_MODE_BEET=m
199CONFIG_INET_LRO=m
200CONFIG_INET_DIAG=m
201CONFIG_INET_TCP_DIAG=m
202# CONFIG_TCP_CONG_ADVANCED is not set
203CONFIG_TCP_CONG_CUBIC=y
204CONFIG_DEFAULT_TCP_CONG="cubic"
205# CONFIG_TCP_MD5SIG is not set
206# CONFIG_IP_VS is not set
207CONFIG_IPV6=m
208CONFIG_IPV6_PRIVACY=y
209CONFIG_IPV6_ROUTER_PREF=y
210CONFIG_IPV6_ROUTE_INFO=y
211# CONFIG_IPV6_OPTIMISTIC_DAD is not set
212CONFIG_INET6_AH=m
213CONFIG_INET6_ESP=m
214CONFIG_INET6_IPCOMP=m
215# CONFIG_IPV6_MIP6 is not set
216CONFIG_INET6_XFRM_TUNNEL=m
217CONFIG_INET6_TUNNEL=m
218CONFIG_INET6_XFRM_MODE_TRANSPORT=m
219CONFIG_INET6_XFRM_MODE_TUNNEL=m
220CONFIG_INET6_XFRM_MODE_BEET=m
221CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
222CONFIG_IPV6_SIT=m
223CONFIG_IPV6_TUNNEL=m
224# CONFIG_IPV6_MULTIPLE_TABLES is not set
225# CONFIG_NETWORK_SECMARK is not set
226CONFIG_NETFILTER=y
227# CONFIG_NETFILTER_DEBUG is not set
228CONFIG_NETFILTER_ADVANCED=y
229
230#
231# Core Netfilter Configuration
232#
233CONFIG_NETFILTER_NETLINK=m
234CONFIG_NETFILTER_NETLINK_QUEUE=m
235CONFIG_NETFILTER_NETLINK_LOG=m
236CONFIG_NF_CONNTRACK=m
237CONFIG_NF_CT_ACCT=y
238CONFIG_NF_CONNTRACK_MARK=y
239# CONFIG_NF_CONNTRACK_EVENTS is not set
240CONFIG_NF_CT_PROTO_GRE=m
241CONFIG_NF_CT_PROTO_SCTP=m
242CONFIG_NF_CT_PROTO_UDPLITE=m
243CONFIG_NF_CONNTRACK_AMANDA=m
244CONFIG_NF_CONNTRACK_FTP=m
245CONFIG_NF_CONNTRACK_H323=m
246CONFIG_NF_CONNTRACK_IRC=m
247CONFIG_NF_CONNTRACK_NETBIOS_NS=m
248CONFIG_NF_CONNTRACK_PPTP=m
249CONFIG_NF_CONNTRACK_SANE=m
250CONFIG_NF_CONNTRACK_SIP=m
251CONFIG_NF_CONNTRACK_TFTP=m
252# CONFIG_NF_CT_NETLINK is not set
253CONFIG_NETFILTER_XTABLES=m
254CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
255CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
256CONFIG_NETFILTER_XT_TARGET_DSCP=m
257CONFIG_NETFILTER_XT_TARGET_MARK=m
258CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
259CONFIG_NETFILTER_XT_TARGET_NFLOG=m
260CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
261CONFIG_NETFILTER_XT_TARGET_RATEEST=m
262CONFIG_NETFILTER_XT_TARGET_TRACE=m
263CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
264CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
265CONFIG_NETFILTER_XT_MATCH_COMMENT=m
266CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
267CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
268CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
269CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
270CONFIG_NETFILTER_XT_MATCH_DCCP=m
271CONFIG_NETFILTER_XT_MATCH_DSCP=m
272CONFIG_NETFILTER_XT_MATCH_ESP=m
273CONFIG_NETFILTER_XT_MATCH_HELPER=m
274CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
275CONFIG_NETFILTER_XT_MATCH_LENGTH=m
276CONFIG_NETFILTER_XT_MATCH_LIMIT=m
277CONFIG_NETFILTER_XT_MATCH_MAC=m
278CONFIG_NETFILTER_XT_MATCH_MARK=m
279CONFIG_NETFILTER_XT_MATCH_OWNER=m
280CONFIG_NETFILTER_XT_MATCH_POLICY=m
281CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
282CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
283CONFIG_NETFILTER_XT_MATCH_QUOTA=m
284CONFIG_NETFILTER_XT_MATCH_RATEEST=m
285CONFIG_NETFILTER_XT_MATCH_REALM=m
286CONFIG_NETFILTER_XT_MATCH_SCTP=m
287CONFIG_NETFILTER_XT_MATCH_STATE=m
288CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
289CONFIG_NETFILTER_XT_MATCH_STRING=m
290CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
291CONFIG_NETFILTER_XT_MATCH_TIME=m
292CONFIG_NETFILTER_XT_MATCH_U32=m
293CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
110 294
111# 295#
112# Memory Technology Devices (MTD) 296# IP: Netfilter Configuration
113# 297#
114# CONFIG_MTD is not set 298CONFIG_NF_CONNTRACK_IPV4=m
299CONFIG_NF_CONNTRACK_PROC_COMPAT=y
300CONFIG_IP_NF_QUEUE=m
301CONFIG_IP_NF_IPTABLES=m
302CONFIG_IP_NF_MATCH_RECENT=m
303CONFIG_IP_NF_MATCH_ECN=m
304CONFIG_IP_NF_MATCH_AH=m
305CONFIG_IP_NF_MATCH_TTL=m
306CONFIG_IP_NF_MATCH_ADDRTYPE=m
307CONFIG_IP_NF_FILTER=m
308CONFIG_IP_NF_TARGET_REJECT=m
309CONFIG_IP_NF_TARGET_LOG=m
310CONFIG_IP_NF_TARGET_ULOG=m
311CONFIG_NF_NAT=m
312CONFIG_NF_NAT_NEEDED=y
313CONFIG_IP_NF_TARGET_MASQUERADE=m
314CONFIG_IP_NF_TARGET_REDIRECT=m
315CONFIG_IP_NF_TARGET_NETMAP=m
316CONFIG_NF_NAT_SNMP_BASIC=m
317CONFIG_NF_NAT_PROTO_GRE=m
318CONFIG_NF_NAT_FTP=m
319CONFIG_NF_NAT_IRC=m
320CONFIG_NF_NAT_TFTP=m
321CONFIG_NF_NAT_AMANDA=m
322CONFIG_NF_NAT_PPTP=m
323CONFIG_NF_NAT_H323=m
324CONFIG_NF_NAT_SIP=m
325CONFIG_IP_NF_MANGLE=m
326CONFIG_IP_NF_TARGET_ECN=m
327CONFIG_IP_NF_TARGET_TTL=m
328CONFIG_IP_NF_TARGET_CLUSTERIP=m
329CONFIG_IP_NF_RAW=m
330CONFIG_IP_NF_ARPTABLES=m
331CONFIG_IP_NF_ARPFILTER=m
332CONFIG_IP_NF_ARP_MANGLE=m
115 333
116# 334#
117# Parallel port support 335# IPv6: Netfilter Configuration
118# 336#
119# CONFIG_PARPORT is not set 337CONFIG_NF_CONNTRACK_IPV6=m
338CONFIG_IP6_NF_QUEUE=m
339CONFIG_IP6_NF_IPTABLES=m
340CONFIG_IP6_NF_MATCH_RT=m
341CONFIG_IP6_NF_MATCH_OPTS=m
342CONFIG_IP6_NF_MATCH_FRAG=m
343CONFIG_IP6_NF_MATCH_HL=m
344CONFIG_IP6_NF_MATCH_IPV6HEADER=m
345CONFIG_IP6_NF_MATCH_AH=m
346CONFIG_IP6_NF_MATCH_MH=m
347CONFIG_IP6_NF_MATCH_EUI64=m
348CONFIG_IP6_NF_FILTER=m
349CONFIG_IP6_NF_TARGET_LOG=m
350CONFIG_IP6_NF_TARGET_REJECT=m
351CONFIG_IP6_NF_MANGLE=m
352CONFIG_IP6_NF_TARGET_HL=m
353CONFIG_IP6_NF_RAW=m
354CONFIG_IP_DCCP=m
355CONFIG_INET_DCCP_DIAG=m
356CONFIG_IP_DCCP_ACKVEC=y
120 357
121# 358#
122# Plug and Play support 359# DCCP CCIDs Configuration (EXPERIMENTAL)
123# 360#
124# CONFIG_PNP is not set 361CONFIG_IP_DCCP_CCID2=m
362# CONFIG_IP_DCCP_CCID2_DEBUG is not set
363CONFIG_IP_DCCP_CCID3=m
364# CONFIG_IP_DCCP_CCID3_DEBUG is not set
365CONFIG_IP_DCCP_CCID3_RTO=100
366CONFIG_IP_DCCP_TFRC_LIB=m
367CONFIG_IP_SCTP=m
368# CONFIG_SCTP_DBG_MSG is not set
369# CONFIG_SCTP_DBG_OBJCNT is not set
370# CONFIG_SCTP_HMAC_NONE is not set
371# CONFIG_SCTP_HMAC_SHA1 is not set
372CONFIG_SCTP_HMAC_MD5=y
373# CONFIG_TIPC is not set
374# CONFIG_ATM is not set
375# CONFIG_BRIDGE is not set
376# CONFIG_VLAN_8021Q is not set
377# CONFIG_DECNET is not set
378CONFIG_LLC=m
379# CONFIG_LLC2 is not set
380# CONFIG_IPX is not set
381CONFIG_ATALK=m
382# CONFIG_DEV_APPLETALK is not set
383# CONFIG_X25 is not set
384# CONFIG_LAPB is not set
385# CONFIG_ECONET is not set
386# CONFIG_WAN_ROUTER is not set
387# CONFIG_NET_SCHED is not set
388CONFIG_NET_CLS_ROUTE=y
125 389
126# 390#
127# Block devices 391# Network testing
128# 392#
393# CONFIG_NET_PKTGEN is not set
394# CONFIG_HAMRADIO is not set
395# CONFIG_CAN is not set
396# CONFIG_IRDA is not set
397# CONFIG_BT is not set
398# CONFIG_AF_RXRPC is not set
399
400#
401# Wireless
402#
403# CONFIG_CFG80211 is not set
404CONFIG_WIRELESS_EXT=y
405# CONFIG_MAC80211 is not set
406CONFIG_IEEE80211=m
407# CONFIG_IEEE80211_DEBUG is not set
408CONFIG_IEEE80211_CRYPT_WEP=m
409CONFIG_IEEE80211_CRYPT_CCMP=m
410CONFIG_IEEE80211_CRYPT_TKIP=m
411CONFIG_IEEE80211_SOFTMAC=m
412# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
413# CONFIG_RFKILL is not set
414# CONFIG_NET_9P is not set
415
416#
417# Device Drivers
418#
419
420#
421# Generic Driver Options
422#
423CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
424CONFIG_STANDALONE=y
425CONFIG_PREVENT_FIRMWARE_BUILD=y
426CONFIG_FW_LOADER=m
427# CONFIG_SYS_HYPERVISOR is not set
428CONFIG_CONNECTOR=m
429# CONFIG_MTD is not set
430# CONFIG_PARPORT is not set
431# CONFIG_PNP is not set
432CONFIG_BLK_DEV=y
129# CONFIG_BLK_DEV_FD is not set 433# CONFIG_BLK_DEV_FD is not set
130# CONFIG_BLK_DEV_COW_COMMON is not set 434# CONFIG_BLK_DEV_COW_COMMON is not set
131CONFIG_BLK_DEV_LOOP=y 435CONFIG_BLK_DEV_LOOP=y
@@ -134,54 +438,64 @@ CONFIG_BLK_DEV_NBD=m
134CONFIG_BLK_DEV_RAM=y 438CONFIG_BLK_DEV_RAM=y
135CONFIG_BLK_DEV_RAM_COUNT=16 439CONFIG_BLK_DEV_RAM_COUNT=16
136CONFIG_BLK_DEV_RAM_SIZE=4096 440CONFIG_BLK_DEV_RAM_SIZE=4096
137CONFIG_BLK_DEV_INITRD=y 441# CONFIG_BLK_DEV_XIP is not set
138CONFIG_INITRAMFS_SOURCE=""
139CONFIG_CDROM_PKTCDVD=m 442CONFIG_CDROM_PKTCDVD=m
140CONFIG_CDROM_PKTCDVD_BUFFERS=8 443CONFIG_CDROM_PKTCDVD_BUFFERS=8
141# CONFIG_CDROM_PKTCDVD_WCACHE is not set 444# CONFIG_CDROM_PKTCDVD_WCACHE is not set
142
143#
144# IO Schedulers
145#
146CONFIG_IOSCHED_NOOP=y
147CONFIG_IOSCHED_AS=y
148CONFIG_IOSCHED_DEADLINE=y
149CONFIG_IOSCHED_CFQ=y
150CONFIG_ATA_OVER_ETH=m 445CONFIG_ATA_OVER_ETH=m
151 446CONFIG_MISC_DEVICES=y
152# 447# CONFIG_EEPROM_93CX6 is not set
153# ATA/ATAPI/MFM/RLL support 448# CONFIG_ENCLOSURE_SERVICES is not set
154# 449CONFIG_HAVE_IDE=y
155CONFIG_IDE=y 450CONFIG_IDE=y
156CONFIG_BLK_DEV_IDE=y 451CONFIG_BLK_DEV_IDE=y
157 452
158# 453#
159# Please see Documentation/ide.txt for help/info on IDE drives 454# Please see Documentation/ide/ide.txt for help/info on IDE drives
160# 455#
161# CONFIG_BLK_DEV_IDE_SATA is not set 456# CONFIG_BLK_DEV_IDE_SATA is not set
162CONFIG_BLK_DEV_IDEDISK=y 457CONFIG_BLK_DEV_IDEDISK=y
163# CONFIG_IDEDISK_MULTI_MODE is not set 458# CONFIG_IDEDISK_MULTI_MODE is not set
164CONFIG_BLK_DEV_IDECD=y 459CONFIG_BLK_DEV_IDECD=y
165CONFIG_BLK_DEV_IDETAPE=m 460CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
461# CONFIG_BLK_DEV_IDETAPE is not set
166CONFIG_BLK_DEV_IDEFLOPPY=m 462CONFIG_BLK_DEV_IDEFLOPPY=m
167# CONFIG_BLK_DEV_IDESCSI is not set 463# CONFIG_BLK_DEV_IDESCSI is not set
168# CONFIG_IDE_TASK_IOCTL is not set 464# CONFIG_IDE_TASK_IOCTL is not set
465CONFIG_IDE_PROC_FS=y
169 466
170# 467#
171# IDE chipset support/bugfixes 468# IDE chipset support/bugfixes
172# 469#
173CONFIG_IDE_GENERIC=y 470# CONFIG_IDE_GENERIC is not set
174# CONFIG_IDE_ARM is not set 471# CONFIG_BLK_DEV_PLATFORM is not set
175CONFIG_BLK_DEV_Q40IDE=y 472CONFIG_BLK_DEV_Q40IDE=y
176# CONFIG_IDE_CHIPSETS is not set 473
474#
475# Other IDE chipsets support
476#
477
478#
479# Note: most of these also require special kernel boot parameters
480#
481# CONFIG_BLK_DEV_4DRIVES is not set
482# CONFIG_BLK_DEV_ALI14XX is not set
483# CONFIG_BLK_DEV_DTC2278 is not set
484# CONFIG_BLK_DEV_HT6560B is not set
485# CONFIG_BLK_DEV_QD65XX is not set
486# CONFIG_BLK_DEV_UMC8672 is not set
177# CONFIG_BLK_DEV_IDEDMA is not set 487# CONFIG_BLK_DEV_IDEDMA is not set
178# CONFIG_IDEDMA_AUTO is not set 488# CONFIG_IDE_ARCH_OBSOLETE_INIT is not set
179# CONFIG_BLK_DEV_HD is not set 489# CONFIG_BLK_DEV_HD is not set
180 490
181# 491#
182# SCSI device support 492# SCSI device support
183# 493#
494CONFIG_RAID_ATTRS=m
184CONFIG_SCSI=y 495CONFIG_SCSI=y
496CONFIG_SCSI_DMA=y
497CONFIG_SCSI_TGT=m
498# CONFIG_SCSI_NETLINK is not set
185CONFIG_SCSI_PROC_FS=y 499CONFIG_SCSI_PROC_FS=y
186 500
187# 501#
@@ -189,10 +503,11 @@ CONFIG_SCSI_PROC_FS=y
189# 503#
190CONFIG_BLK_DEV_SD=y 504CONFIG_BLK_DEV_SD=y
191CONFIG_CHR_DEV_ST=m 505CONFIG_CHR_DEV_ST=m
192# CONFIG_CHR_DEV_OSST is not set 506CONFIG_CHR_DEV_OSST=m
193CONFIG_BLK_DEV_SR=y 507CONFIG_BLK_DEV_SR=y
194CONFIG_BLK_DEV_SR_VENDOR=y 508CONFIG_BLK_DEV_SR_VENDOR=y
195CONFIG_CHR_DEV_SG=m 509CONFIG_CHR_DEV_SG=m
510# CONFIG_CHR_DEV_SCH is not set
196 511
197# 512#
198# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 513# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -200,266 +515,71 @@ CONFIG_CHR_DEV_SG=m
200# CONFIG_SCSI_MULTI_LUN is not set 515# CONFIG_SCSI_MULTI_LUN is not set
201CONFIG_SCSI_CONSTANTS=y 516CONFIG_SCSI_CONSTANTS=y
202# CONFIG_SCSI_LOGGING is not set 517# CONFIG_SCSI_LOGGING is not set
518# CONFIG_SCSI_SCAN_ASYNC is not set
519CONFIG_SCSI_WAIT_SCAN=m
203 520
204# 521#
205# SCSI Transport Attributes 522# SCSI Transports
206# 523#
207# CONFIG_SCSI_SPI_ATTRS is not set 524# CONFIG_SCSI_SPI_ATTRS is not set
208# CONFIG_SCSI_FC_ATTRS is not set 525# CONFIG_SCSI_FC_ATTRS is not set
209# CONFIG_SCSI_ISCSI_ATTRS is not set 526CONFIG_SCSI_ISCSI_ATTRS=m
210 527CONFIG_SCSI_SAS_ATTRS=m
211# 528CONFIG_SCSI_SAS_LIBSAS=m
212# SCSI low-level drivers 529CONFIG_SCSI_SAS_HOST_SMP=y
213# 530# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
531CONFIG_SCSI_SRP_ATTRS=m
532CONFIG_SCSI_SRP_TGT_ATTRS=y
533CONFIG_SCSI_LOWLEVEL=y
534CONFIG_ISCSI_TCP=m
214# CONFIG_SCSI_AHA152X is not set 535# CONFIG_SCSI_AHA152X is not set
215# CONFIG_SCSI_AIC7XXX_OLD is not set 536# CONFIG_SCSI_AIC7XXX_OLD is not set
537# CONFIG_SCSI_ADVANSYS is not set
216# CONFIG_SCSI_IN2000 is not set 538# CONFIG_SCSI_IN2000 is not set
217# CONFIG_SCSI_SATA is not set
218# CONFIG_SCSI_DTC3280 is not set 539# CONFIG_SCSI_DTC3280 is not set
219# CONFIG_SCSI_FUTURE_DOMAIN is not set 540# CONFIG_SCSI_FUTURE_DOMAIN is not set
220# CONFIG_SCSI_GENERIC_NCR5380 is not set 541# CONFIG_SCSI_GENERIC_NCR5380 is not set
221# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set 542# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
222# CONFIG_SCSI_NCR53C406A is not set 543# CONFIG_SCSI_NCR53C406A is not set
223# CONFIG_SCSI_PAS16 is not set 544# CONFIG_SCSI_PAS16 is not set
224# CONFIG_SCSI_PSI240I is not set
225# CONFIG_SCSI_QLOGIC_FAS is not set 545# CONFIG_SCSI_QLOGIC_FAS is not set
226# CONFIG_SCSI_SYM53C416 is not set 546# CONFIG_SCSI_SYM53C416 is not set
227# CONFIG_SCSI_T128 is not set 547# CONFIG_SCSI_T128 is not set
228# CONFIG_SCSI_DEBUG is not set 548# CONFIG_SCSI_DEBUG is not set
229
230#
231# Old CD-ROM drivers (not SCSI, not IDE)
232#
233# CONFIG_CD_NO_IDESCSI is not set
234
235#
236# Multi-device support (RAID and LVM)
237#
238CONFIG_MD=y 549CONFIG_MD=y
239CONFIG_BLK_DEV_MD=m 550CONFIG_BLK_DEV_MD=m
240CONFIG_MD_LINEAR=m 551CONFIG_MD_LINEAR=m
241CONFIG_MD_RAID0=m 552CONFIG_MD_RAID0=m
242CONFIG_MD_RAID1=m 553CONFIG_MD_RAID1=m
243# CONFIG_MD_RAID10 is not set 554# CONFIG_MD_RAID10 is not set
244CONFIG_MD_RAID5=m 555CONFIG_MD_RAID456=m
245CONFIG_MD_RAID6=m 556CONFIG_MD_RAID5_RESHAPE=y
246CONFIG_MD_MULTIPATH=m 557CONFIG_MD_MULTIPATH=m
247# CONFIG_MD_FAULTY is not set 558# CONFIG_MD_FAULTY is not set
248CONFIG_BLK_DEV_DM=m 559CONFIG_BLK_DEV_DM=m
560# CONFIG_DM_DEBUG is not set
249CONFIG_DM_CRYPT=m 561CONFIG_DM_CRYPT=m
250CONFIG_DM_SNAPSHOT=m 562CONFIG_DM_SNAPSHOT=m
251CONFIG_DM_MIRROR=m 563CONFIG_DM_MIRROR=m
252CONFIG_DM_ZERO=m 564CONFIG_DM_ZERO=m
253CONFIG_DM_MULTIPATH=m 565CONFIG_DM_MULTIPATH=m
254CONFIG_DM_MULTIPATH_EMC=m 566CONFIG_DM_MULTIPATH_EMC=m
255 567CONFIG_DM_MULTIPATH_RDAC=m
256# 568CONFIG_DM_MULTIPATH_HP=m
257# Fusion MPT device support 569# CONFIG_DM_DELAY is not set
258# 570CONFIG_DM_UEVENT=y
259
260#
261# IEEE 1394 (FireWire) support
262#
263
264#
265# I2O device support
266#
267
268#
269# Networking support
270#
271CONFIG_NET=y
272
273#
274# Networking options
275#
276CONFIG_PACKET=y
277# CONFIG_PACKET_MMAP is not set
278CONFIG_UNIX=y
279CONFIG_NET_KEY=y
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282# CONFIG_IP_ADVANCED_ROUTER is not set
283CONFIG_IP_PNP=y
284CONFIG_IP_PNP_DHCP=y
285CONFIG_IP_PNP_BOOTP=y
286CONFIG_IP_PNP_RARP=y
287CONFIG_NET_IPIP=m
288CONFIG_NET_IPGRE=m
289# CONFIG_ARPD is not set
290CONFIG_SYN_COOKIES=y
291CONFIG_INET_AH=m
292CONFIG_INET_ESP=m
293CONFIG_INET_IPCOMP=m
294CONFIG_INET_TUNNEL=m
295CONFIG_IP_TCPDIAG=m
296CONFIG_IP_TCPDIAG_IPV6=y
297
298#
299# IP: Virtual Server Configuration
300#
301# CONFIG_IP_VS is not set
302CONFIG_IPV6=m
303CONFIG_IPV6_PRIVACY=y
304CONFIG_INET6_AH=m
305CONFIG_INET6_ESP=m
306CONFIG_INET6_IPCOMP=m
307CONFIG_INET6_TUNNEL=m
308CONFIG_IPV6_TUNNEL=m
309CONFIG_NETFILTER=y
310# CONFIG_NETFILTER_DEBUG is not set
311
312#
313# IP: Netfilter Configuration
314#
315CONFIG_IP_NF_CONNTRACK=m
316# CONFIG_IP_NF_CT_ACCT is not set
317CONFIG_IP_NF_CONNTRACK_MARK=y
318# CONFIG_IP_NF_CT_PROTO_SCTP is not set
319CONFIG_IP_NF_FTP=m
320CONFIG_IP_NF_IRC=m
321CONFIG_IP_NF_TFTP=m
322CONFIG_IP_NF_AMANDA=m
323CONFIG_IP_NF_QUEUE=m
324CONFIG_IP_NF_IPTABLES=m
325CONFIG_IP_NF_MATCH_LIMIT=m
326CONFIG_IP_NF_MATCH_IPRANGE=m
327CONFIG_IP_NF_MATCH_MAC=m
328CONFIG_IP_NF_MATCH_PKTTYPE=m
329CONFIG_IP_NF_MATCH_MARK=m
330CONFIG_IP_NF_MATCH_MULTIPORT=m
331CONFIG_IP_NF_MATCH_TOS=m
332CONFIG_IP_NF_MATCH_RECENT=m
333CONFIG_IP_NF_MATCH_ECN=m
334CONFIG_IP_NF_MATCH_DSCP=m
335CONFIG_IP_NF_MATCH_AH_ESP=m
336CONFIG_IP_NF_MATCH_LENGTH=m
337CONFIG_IP_NF_MATCH_TTL=m
338CONFIG_IP_NF_MATCH_TCPMSS=m
339CONFIG_IP_NF_MATCH_HELPER=m
340CONFIG_IP_NF_MATCH_STATE=m
341CONFIG_IP_NF_MATCH_CONNTRACK=m
342CONFIG_IP_NF_MATCH_OWNER=m
343CONFIG_IP_NF_MATCH_ADDRTYPE=m
344CONFIG_IP_NF_MATCH_REALM=m
345# CONFIG_IP_NF_MATCH_SCTP is not set
346# CONFIG_IP_NF_MATCH_COMMENT is not set
347CONFIG_IP_NF_MATCH_CONNMARK=m
348CONFIG_IP_NF_MATCH_HASHLIMIT=m
349CONFIG_IP_NF_FILTER=m
350CONFIG_IP_NF_TARGET_REJECT=m
351CONFIG_IP_NF_TARGET_LOG=m
352CONFIG_IP_NF_TARGET_ULOG=m
353CONFIG_IP_NF_TARGET_TCPMSS=m
354CONFIG_IP_NF_NAT=m
355CONFIG_IP_NF_NAT_NEEDED=y
356CONFIG_IP_NF_TARGET_MASQUERADE=m
357CONFIG_IP_NF_TARGET_REDIRECT=m
358CONFIG_IP_NF_TARGET_NETMAP=m
359CONFIG_IP_NF_TARGET_SAME=m
360CONFIG_IP_NF_NAT_SNMP_BASIC=m
361CONFIG_IP_NF_NAT_IRC=m
362CONFIG_IP_NF_NAT_FTP=m
363CONFIG_IP_NF_NAT_TFTP=m
364CONFIG_IP_NF_NAT_AMANDA=m
365CONFIG_IP_NF_MANGLE=m
366CONFIG_IP_NF_TARGET_TOS=m
367CONFIG_IP_NF_TARGET_ECN=m
368CONFIG_IP_NF_TARGET_DSCP=m
369CONFIG_IP_NF_TARGET_MARK=m
370CONFIG_IP_NF_TARGET_CLASSIFY=m
371CONFIG_IP_NF_TARGET_CONNMARK=m
372# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
373CONFIG_IP_NF_RAW=m
374CONFIG_IP_NF_TARGET_NOTRACK=m
375CONFIG_IP_NF_ARPTABLES=m
376CONFIG_IP_NF_ARPFILTER=m
377CONFIG_IP_NF_ARP_MANGLE=m
378
379#
380# IPv6: Netfilter Configuration (EXPERIMENTAL)
381#
382CONFIG_IP6_NF_QUEUE=m
383CONFIG_IP6_NF_IPTABLES=m
384CONFIG_IP6_NF_MATCH_LIMIT=m
385CONFIG_IP6_NF_MATCH_MAC=m
386CONFIG_IP6_NF_MATCH_RT=m
387CONFIG_IP6_NF_MATCH_OPTS=m
388CONFIG_IP6_NF_MATCH_FRAG=m
389CONFIG_IP6_NF_MATCH_HL=m
390CONFIG_IP6_NF_MATCH_MULTIPORT=m
391CONFIG_IP6_NF_MATCH_OWNER=m
392CONFIG_IP6_NF_MATCH_MARK=m
393CONFIG_IP6_NF_MATCH_IPV6HEADER=m
394CONFIG_IP6_NF_MATCH_AHESP=m
395CONFIG_IP6_NF_MATCH_LENGTH=m
396CONFIG_IP6_NF_MATCH_EUI64=m
397CONFIG_IP6_NF_FILTER=m
398CONFIG_IP6_NF_TARGET_LOG=m
399CONFIG_IP6_NF_MANGLE=m
400CONFIG_IP6_NF_TARGET_MARK=m
401CONFIG_IP6_NF_RAW=m
402CONFIG_XFRM=y
403# CONFIG_XFRM_USER is not set
404
405#
406# SCTP Configuration (EXPERIMENTAL)
407#
408CONFIG_IP_SCTP=m
409# CONFIG_SCTP_DBG_MSG is not set
410# CONFIG_SCTP_DBG_OBJCNT is not set
411# CONFIG_SCTP_HMAC_NONE is not set
412# CONFIG_SCTP_HMAC_SHA1 is not set
413CONFIG_SCTP_HMAC_MD5=y
414# CONFIG_ATM is not set
415# CONFIG_BRIDGE is not set
416# CONFIG_VLAN_8021Q is not set
417# CONFIG_DECNET is not set
418CONFIG_LLC=m
419# CONFIG_LLC2 is not set
420CONFIG_IPX=m
421# CONFIG_IPX_INTERN is not set
422CONFIG_ATALK=m
423# CONFIG_DEV_APPLETALK is not set
424# CONFIG_X25 is not set
425# CONFIG_LAPB is not set
426# CONFIG_NET_DIVERT is not set
427# CONFIG_ECONET is not set
428# CONFIG_WAN_ROUTER is not set
429
430#
431# QoS and/or fair queueing
432#
433# CONFIG_NET_SCHED is not set
434CONFIG_NET_CLS_ROUTE=y
435
436#
437# Network testing
438#
439# CONFIG_NET_PKTGEN is not set
440CONFIG_NETPOLL=y
441# CONFIG_NETPOLL_RX is not set
442# CONFIG_NETPOLL_TRAP is not set
443CONFIG_NET_POLL_CONTROLLER=y
444# CONFIG_HAMRADIO is not set
445# CONFIG_IRDA is not set
446# CONFIG_BT is not set
447CONFIG_NETDEVICES=y 571CONFIG_NETDEVICES=y
572# CONFIG_NETDEVICES_MULTIQUEUE is not set
448CONFIG_DUMMY=m 573CONFIG_DUMMY=m
449# CONFIG_BONDING is not set 574# CONFIG_BONDING is not set
575CONFIG_MACVLAN=m
450CONFIG_EQUALIZER=m 576CONFIG_EQUALIZER=m
451# CONFIG_TUN is not set 577# CONFIG_TUN is not set
452 578CONFIG_VETH=m
453#
454# ARCnet devices
455#
456# CONFIG_ARCNET is not set 579# CONFIG_ARCNET is not set
457 580# CONFIG_PHYLIB is not set
458#
459# Ethernet (10 or 100Mbit)
460#
461CONFIG_NET_ETHERNET=y 581CONFIG_NET_ETHERNET=y
462CONFIG_MII=m 582# CONFIG_MII is not set
463# CONFIG_NET_VENDOR_3COM is not set 583# CONFIG_NET_VENDOR_3COM is not set
464# CONFIG_NET_VENDOR_SMC is not set 584# CONFIG_NET_VENDOR_SMC is not set
465# CONFIG_NET_VENDOR_RACAL is not set 585# CONFIG_NET_VENDOR_RACAL is not set
@@ -468,30 +588,21 @@ CONFIG_MII=m
468# CONFIG_HP100 is not set 588# CONFIG_HP100 is not set
469# CONFIG_NET_ISA is not set 589# CONFIG_NET_ISA is not set
470CONFIG_NE2000=m 590CONFIG_NE2000=m
591# CONFIG_IBM_NEW_EMAC_ZMII is not set
592# CONFIG_IBM_NEW_EMAC_RGMII is not set
593# CONFIG_IBM_NEW_EMAC_TAH is not set
594# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
471# CONFIG_NET_PCI is not set 595# CONFIG_NET_PCI is not set
472# CONFIG_NET_POCKET is not set 596# CONFIG_B44 is not set
473 597# CONFIG_NETDEV_1000 is not set
474# 598# CONFIG_NETDEV_10000 is not set
475# Ethernet (1000 Mbit)
476#
477
478#
479# Ethernet (10000 Mbit)
480#
481
482#
483# Token Ring devices
484#
485# CONFIG_TR is not set 599# CONFIG_TR is not set
486 600
487# 601#
488# Wireless LAN (non-hamradio) 602# Wireless LAN
489#
490# CONFIG_NET_RADIO is not set
491
492#
493# Wan interfaces
494# 603#
604# CONFIG_WLAN_PRE80211 is not set
605# CONFIG_WLAN_80211 is not set
495# CONFIG_WAN is not set 606# CONFIG_WAN is not set
496CONFIG_PPP=m 607CONFIG_PPP=m
497# CONFIG_PPP_MULTILINK is not set 608# CONFIG_PPP_MULTILINK is not set
@@ -500,28 +611,28 @@ CONFIG_PPP_ASYNC=m
500CONFIG_PPP_SYNC_TTY=m 611CONFIG_PPP_SYNC_TTY=m
501CONFIG_PPP_DEFLATE=m 612CONFIG_PPP_DEFLATE=m
502CONFIG_PPP_BSDCOMP=m 613CONFIG_PPP_BSDCOMP=m
614CONFIG_PPP_MPPE=m
503CONFIG_PPPOE=m 615CONFIG_PPPOE=m
616CONFIG_PPPOL2TP=m
504CONFIG_SLIP=m 617CONFIG_SLIP=m
505CONFIG_SLIP_COMPRESSED=y 618CONFIG_SLIP_COMPRESSED=y
619CONFIG_SLHC=m
506CONFIG_SLIP_SMART=y 620CONFIG_SLIP_SMART=y
507CONFIG_SLIP_MODE_SLIP6=y 621CONFIG_SLIP_MODE_SLIP6=y
508CONFIG_SHAPER=m
509CONFIG_NETCONSOLE=m 622CONFIG_NETCONSOLE=m
510 623CONFIG_NETCONSOLE_DYNAMIC=y
511# 624CONFIG_NETPOLL=y
512# ISDN subsystem 625# CONFIG_NETPOLL_TRAP is not set
513# 626CONFIG_NET_POLL_CONTROLLER=y
514# CONFIG_ISDN is not set 627# CONFIG_ISDN is not set
515
516#
517# Telephony Support
518#
519# CONFIG_PHONE is not set 628# CONFIG_PHONE is not set
520 629
521# 630#
522# Input device support 631# Input device support
523# 632#
524CONFIG_INPUT=y 633CONFIG_INPUT=y
634CONFIG_INPUT_FF_MEMLESS=m
635# CONFIG_INPUT_POLLDEV is not set
525 636
526# 637#
527# Userland interfaces 638# Userland interfaces
@@ -531,7 +642,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
531CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 642CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
532CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 643CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
533# CONFIG_INPUT_JOYDEV is not set 644# CONFIG_INPUT_JOYDEV is not set
534# CONFIG_INPUT_TSDEV is not set
535# CONFIG_INPUT_EVDEV is not set 645# CONFIG_INPUT_EVDEV is not set
536# CONFIG_INPUT_EVBUG is not set 646# CONFIG_INPUT_EVBUG is not set
537 647
@@ -544,22 +654,32 @@ CONFIG_INPUT_KEYBOARD=y
544# CONFIG_KEYBOARD_LKKBD is not set 654# CONFIG_KEYBOARD_LKKBD is not set
545# CONFIG_KEYBOARD_XTKBD is not set 655# CONFIG_KEYBOARD_XTKBD is not set
546# CONFIG_KEYBOARD_NEWTON is not set 656# CONFIG_KEYBOARD_NEWTON is not set
657# CONFIG_KEYBOARD_STOWAWAY is not set
547CONFIG_INPUT_MOUSE=y 658CONFIG_INPUT_MOUSE=y
548CONFIG_MOUSE_PS2=m 659CONFIG_MOUSE_PS2=m
660CONFIG_MOUSE_PS2_ALPS=y
661CONFIG_MOUSE_PS2_LOGIPS2PP=y
662CONFIG_MOUSE_PS2_SYNAPTICS=y
663CONFIG_MOUSE_PS2_LIFEBOOK=y
664CONFIG_MOUSE_PS2_TRACKPOINT=y
665# CONFIG_MOUSE_PS2_TOUCHKIT is not set
549CONFIG_MOUSE_SERIAL=m 666CONFIG_MOUSE_SERIAL=m
550# CONFIG_MOUSE_INPORT is not set 667# CONFIG_MOUSE_INPORT is not set
551# CONFIG_MOUSE_LOGIBM is not set 668# CONFIG_MOUSE_LOGIBM is not set
552# CONFIG_MOUSE_PC110PAD is not set 669# CONFIG_MOUSE_PC110PAD is not set
553# CONFIG_MOUSE_VSXXXAA is not set 670# CONFIG_MOUSE_VSXXXAA is not set
554# CONFIG_INPUT_JOYSTICK is not set 671# CONFIG_INPUT_JOYSTICK is not set
672# CONFIG_INPUT_TABLET is not set
555# CONFIG_INPUT_TOUCHSCREEN is not set 673# CONFIG_INPUT_TOUCHSCREEN is not set
556# CONFIG_INPUT_MISC is not set 674CONFIG_INPUT_MISC=y
675CONFIG_INPUT_M68K_BEEP=m
676# CONFIG_INPUT_UINPUT is not set
557 677
558# 678#
559# Hardware I/O ports 679# Hardware I/O ports
560# 680#
561CONFIG_SERIO=m 681CONFIG_SERIO=m
562CONFIG_SERIO_SERPORT=m 682# CONFIG_SERIO_SERPORT is not set
563CONFIG_SERIO_Q40KBD=m 683CONFIG_SERIO_Q40KBD=m
564CONFIG_SERIO_LIBPS2=m 684CONFIG_SERIO_LIBPS2=m
565# CONFIG_SERIO_RAW is not set 685# CONFIG_SERIO_RAW is not set
@@ -571,6 +691,7 @@ CONFIG_SERIO_LIBPS2=m
571CONFIG_VT=y 691CONFIG_VT=y
572CONFIG_VT_CONSOLE=y 692CONFIG_VT_CONSOLE=y
573CONFIG_HW_CONSOLE=y 693CONFIG_HW_CONSOLE=y
694CONFIG_VT_HW_CONSOLE_BINDING=y
574# CONFIG_SERIAL_NONSTANDARD is not set 695# CONFIG_SERIAL_NONSTANDARD is not set
575 696
576# 697#
@@ -584,115 +705,117 @@ CONFIG_HW_CONSOLE=y
584CONFIG_UNIX98_PTYS=y 705CONFIG_UNIX98_PTYS=y
585CONFIG_LEGACY_PTYS=y 706CONFIG_LEGACY_PTYS=y
586CONFIG_LEGACY_PTY_COUNT=256 707CONFIG_LEGACY_PTY_COUNT=256
587
588#
589# IPMI
590#
591# CONFIG_IPMI_HANDLER is not set 708# CONFIG_IPMI_HANDLER is not set
592 709# CONFIG_HW_RANDOM is not set
593#
594# Watchdog Cards
595#
596# CONFIG_WATCHDOG is not set
597CONFIG_GEN_RTC=m 710CONFIG_GEN_RTC=m
598CONFIG_GEN_RTC_X=y 711CONFIG_GEN_RTC_X=y
599# CONFIG_DTLK is not set 712# CONFIG_DTLK is not set
600# CONFIG_R3964 is not set 713# CONFIG_R3964 is not set
601
602#
603# Ftape, the floppy tape device driver
604#
605# CONFIG_DRM is not set
606# CONFIG_RAW_DRIVER is not set 714# CONFIG_RAW_DRIVER is not set
607 715# CONFIG_TCG_TPM is not set
608#
609# TPM devices
610#
611
612#
613# I2C support
614#
615# CONFIG_I2C is not set 716# CONFIG_I2C is not set
616 717
617# 718#
618# Dallas's 1-wire bus 719# SPI support
619# 720#
721# CONFIG_SPI is not set
722# CONFIG_SPI_MASTER is not set
620# CONFIG_W1 is not set 723# CONFIG_W1 is not set
724# CONFIG_POWER_SUPPLY is not set
725# CONFIG_HWMON is not set
726# CONFIG_THERMAL is not set
727# CONFIG_WATCHDOG is not set
621 728
622# 729#
623# Misc devices 730# Sonics Silicon Backplane
624# 731#
732CONFIG_SSB_POSSIBLE=y
733# CONFIG_SSB is not set
625 734
626# 735#
627# Multimedia devices 736# Multifunction device drivers
628# 737#
629# CONFIG_VIDEO_DEV is not set 738# CONFIG_MFD_SM501 is not set
630 739
631# 740#
632# Digital Video Broadcasting Devices 741# Multimedia devices
633# 742#
634# CONFIG_DVB is not set 743# CONFIG_VIDEO_DEV is not set
744# CONFIG_DVB_CORE is not set
745# CONFIG_DAB is not set
635 746
636# 747#
637# Graphics support 748# Graphics support
638# 749#
750# CONFIG_VGASTATE is not set
751# CONFIG_VIDEO_OUTPUT_CONTROL is not set
639CONFIG_FB=y 752CONFIG_FB=y
753# CONFIG_FIRMWARE_EDID is not set
754# CONFIG_FB_DDC is not set
640CONFIG_FB_CFB_FILLRECT=y 755CONFIG_FB_CFB_FILLRECT=y
641CONFIG_FB_CFB_COPYAREA=y 756CONFIG_FB_CFB_COPYAREA=y
642CONFIG_FB_CFB_IMAGEBLIT=y 757CONFIG_FB_CFB_IMAGEBLIT=y
643CONFIG_FB_SOFT_CURSOR=y 758# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
759# CONFIG_FB_SYS_FILLRECT is not set
760# CONFIG_FB_SYS_COPYAREA is not set
761# CONFIG_FB_SYS_IMAGEBLIT is not set
762# CONFIG_FB_SYS_FOPS is not set
763CONFIG_FB_DEFERRED_IO=y
764# CONFIG_FB_SVGALIB is not set
644# CONFIG_FB_MACMODES is not set 765# CONFIG_FB_MACMODES is not set
645CONFIG_FB_MODE_HELPERS=y 766# CONFIG_FB_BACKLIGHT is not set
767# CONFIG_FB_MODE_HELPERS is not set
646# CONFIG_FB_TILEBLITTING is not set 768# CONFIG_FB_TILEBLITTING is not set
769
770#
771# Frame buffer hardware drivers
772#
647CONFIG_FB_Q40=y 773CONFIG_FB_Q40=y
774# CONFIG_FB_UVESA is not set
648# CONFIG_FB_S1D13XXX is not set 775# CONFIG_FB_S1D13XXX is not set
649# CONFIG_FB_VIRTUAL is not set 776# CONFIG_FB_VIRTUAL is not set
777# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
778
779#
780# Display device support
781#
782# CONFIG_DISPLAY_SUPPORT is not set
650 783
651# 784#
652# Console display driver support 785# Console display driver support
653# 786#
654CONFIG_DUMMY_CONSOLE=y 787CONFIG_DUMMY_CONSOLE=y
655CONFIG_FRAMEBUFFER_CONSOLE=y 788CONFIG_FRAMEBUFFER_CONSOLE=y
789# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
790# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
656# CONFIG_FONTS is not set 791# CONFIG_FONTS is not set
657CONFIG_FONT_8x8=y 792CONFIG_FONT_8x8=y
658CONFIG_FONT_8x16=y 793CONFIG_FONT_8x16=y
659
660#
661# Logo configuration
662#
663CONFIG_LOGO=y 794CONFIG_LOGO=y
664CONFIG_LOGO_LINUX_MONO=y 795CONFIG_LOGO_LINUX_MONO=y
665CONFIG_LOGO_LINUX_VGA16=y 796CONFIG_LOGO_LINUX_VGA16=y
666CONFIG_LOGO_LINUX_CLUT224=y 797CONFIG_LOGO_LINUX_CLUT224=y
667# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
668 798
669# 799#
670# Sound 800# Sound
671# 801#
672CONFIG_SOUND=y 802CONFIG_SOUND=m
673CONFIG_DMASOUND_Q40=y 803CONFIG_DMASOUND_Q40=m
674CONFIG_DMASOUND=y 804CONFIG_DMASOUND=m
675 805CONFIG_HID_SUPPORT=y
676# 806CONFIG_HID=m
677# USB support 807# CONFIG_HID_DEBUG is not set
678# 808CONFIG_HIDRAW=y
679# CONFIG_USB_ARCH_HAS_HCD is not set 809# CONFIG_USB_SUPPORT is not set
680# CONFIG_USB_ARCH_HAS_OHCI is not set
681
682#
683# USB Gadget Support
684#
685# CONFIG_USB_GADGET is not set
686
687#
688# MMC/SD Card support
689#
690# CONFIG_MMC is not set 810# CONFIG_MMC is not set
811# CONFIG_MEMSTICK is not set
812# CONFIG_NEW_LEDS is not set
813# CONFIG_RTC_CLASS is not set
691 814
692# 815#
693# InfiniBand support 816# Userspace I/O
694# 817#
695# CONFIG_INFINIBAND is not set 818# CONFIG_UIO is not set
696 819
697# 820#
698# Character devices 821# Character devices
@@ -703,10 +826,11 @@ CONFIG_DMASOUND=y
703# 826#
704CONFIG_EXT2_FS=y 827CONFIG_EXT2_FS=y
705# CONFIG_EXT2_FS_XATTR is not set 828# CONFIG_EXT2_FS_XATTR is not set
829# CONFIG_EXT2_FS_XIP is not set
706CONFIG_EXT3_FS=y 830CONFIG_EXT3_FS=y
707# CONFIG_EXT3_FS_XATTR is not set 831# CONFIG_EXT3_FS_XATTR is not set
832# CONFIG_EXT4DEV_FS is not set
708CONFIG_JBD=y 833CONFIG_JBD=y
709# CONFIG_JBD_DEBUG is not set
710CONFIG_REISERFS_FS=m 834CONFIG_REISERFS_FS=m
711# CONFIG_REISERFS_CHECK is not set 835# CONFIG_REISERFS_CHECK is not set
712# CONFIG_REISERFS_PROC_INFO is not set 836# CONFIG_REISERFS_PROC_INFO is not set
@@ -717,25 +841,29 @@ CONFIG_JFS_FS=m
717# CONFIG_JFS_DEBUG is not set 841# CONFIG_JFS_DEBUG is not set
718# CONFIG_JFS_STATISTICS is not set 842# CONFIG_JFS_STATISTICS is not set
719CONFIG_FS_POSIX_ACL=y 843CONFIG_FS_POSIX_ACL=y
720
721#
722# XFS support
723#
724CONFIG_XFS_FS=m 844CONFIG_XFS_FS=m
725CONFIG_XFS_EXPORT=y
726# CONFIG_XFS_RT is not set
727# CONFIG_XFS_QUOTA is not set 845# CONFIG_XFS_QUOTA is not set
728# CONFIG_XFS_SECURITY is not set 846# CONFIG_XFS_SECURITY is not set
729# CONFIG_XFS_POSIX_ACL is not set 847# CONFIG_XFS_POSIX_ACL is not set
730CONFIG_MINIX_FS=y 848# CONFIG_XFS_RT is not set
731# CONFIG_ROMFS_FS is not set 849CONFIG_GFS2_FS=m
850CONFIG_GFS2_FS_LOCKING_NOLOCK=m
851CONFIG_GFS2_FS_LOCKING_DLM=m
852CONFIG_OCFS2_FS=m
853# CONFIG_OCFS2_DEBUG_MASKLOG is not set
854# CONFIG_OCFS2_DEBUG_FS is not set
855CONFIG_DNOTIFY=y
856CONFIG_INOTIFY=y
857CONFIG_INOTIFY_USER=y
732CONFIG_QUOTA=y 858CONFIG_QUOTA=y
859CONFIG_QUOTA_NETLINK_INTERFACE=y
860# CONFIG_PRINT_QUOTA_WARNING is not set
733# CONFIG_QFMT_V1 is not set 861# CONFIG_QFMT_V1 is not set
734# CONFIG_QFMT_V2 is not set 862# CONFIG_QFMT_V2 is not set
735CONFIG_QUOTACTL=y 863CONFIG_QUOTACTL=y
736CONFIG_DNOTIFY=y
737CONFIG_AUTOFS_FS=m 864CONFIG_AUTOFS_FS=m
738CONFIG_AUTOFS4_FS=m 865CONFIG_AUTOFS4_FS=m
866CONFIG_FUSE_FS=m
739 867
740# 868#
741# CD-ROM/DVD Filesystems 869# CD-ROM/DVD Filesystems
@@ -743,7 +871,6 @@ CONFIG_AUTOFS4_FS=m
743CONFIG_ISO9660_FS=y 871CONFIG_ISO9660_FS=y
744CONFIG_JOLIET=y 872CONFIG_JOLIET=y
745CONFIG_ZISOFS=y 873CONFIG_ZISOFS=y
746CONFIG_ZISOFS_FS=y
747CONFIG_UDF_FS=m 874CONFIG_UDF_FS=m
748CONFIG_UDF_NLS=y 875CONFIG_UDF_NLS=y
749 876
@@ -762,13 +889,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
762# 889#
763CONFIG_PROC_FS=y 890CONFIG_PROC_FS=y
764CONFIG_PROC_KCORE=y 891CONFIG_PROC_KCORE=y
892CONFIG_PROC_SYSCTL=y
765CONFIG_SYSFS=y 893CONFIG_SYSFS=y
766# CONFIG_DEVFS_FS is not set
767# CONFIG_DEVPTS_FS_XATTR is not set
768CONFIG_TMPFS=y 894CONFIG_TMPFS=y
769# CONFIG_TMPFS_XATTR is not set 895# CONFIG_TMPFS_POSIX_ACL is not set
770# CONFIG_HUGETLB_PAGE is not set 896# CONFIG_HUGETLB_PAGE is not set
771CONFIG_RAMFS=y 897CONFIG_CONFIGFS_FS=m
772 898
773# 899#
774# Miscellaneous filesystems 900# Miscellaneous filesystems
@@ -782,44 +908,39 @@ CONFIG_HFSPLUS_FS=m
782# CONFIG_EFS_FS is not set 908# CONFIG_EFS_FS is not set
783CONFIG_CRAMFS=m 909CONFIG_CRAMFS=m
784# CONFIG_VXFS_FS is not set 910# CONFIG_VXFS_FS is not set
911CONFIG_MINIX_FS=y
785CONFIG_HPFS_FS=m 912CONFIG_HPFS_FS=m
786# CONFIG_QNX4FS_FS is not set 913# CONFIG_QNX4FS_FS is not set
914# CONFIG_ROMFS_FS is not set
787CONFIG_SYSV_FS=m 915CONFIG_SYSV_FS=m
788CONFIG_UFS_FS=m 916CONFIG_UFS_FS=m
789CONFIG_UFS_FS_WRITE=y 917# CONFIG_UFS_FS_WRITE is not set
790 918# CONFIG_UFS_DEBUG is not set
791# 919CONFIG_NETWORK_FILESYSTEMS=y
792# Network File Systems
793#
794CONFIG_NFS_FS=y 920CONFIG_NFS_FS=y
795CONFIG_NFS_V3=y 921CONFIG_NFS_V3=y
922# CONFIG_NFS_V3_ACL is not set
796CONFIG_NFS_V4=y 923CONFIG_NFS_V4=y
797# CONFIG_NFS_DIRECTIO is not set 924# CONFIG_NFS_DIRECTIO is not set
798CONFIG_NFSD=m 925CONFIG_NFSD=m
799CONFIG_NFSD_V3=y 926CONFIG_NFSD_V3=y
800CONFIG_NFSD_V4=y 927# CONFIG_NFSD_V3_ACL is not set
928# CONFIG_NFSD_V4 is not set
801CONFIG_NFSD_TCP=y 929CONFIG_NFSD_TCP=y
802CONFIG_ROOT_NFS=y
803CONFIG_LOCKD=y 930CONFIG_LOCKD=y
804CONFIG_LOCKD_V4=y 931CONFIG_LOCKD_V4=y
805CONFIG_EXPORTFS=m 932CONFIG_EXPORTFS=m
933CONFIG_NFS_COMMON=y
806CONFIG_SUNRPC=y 934CONFIG_SUNRPC=y
807CONFIG_SUNRPC_GSS=y 935CONFIG_SUNRPC_GSS=y
936CONFIG_SUNRPC_BIND34=y
808CONFIG_RPCSEC_GSS_KRB5=y 937CONFIG_RPCSEC_GSS_KRB5=y
809# CONFIG_RPCSEC_GSS_SPKM3 is not set 938# CONFIG_RPCSEC_GSS_SPKM3 is not set
810CONFIG_SMB_FS=m 939CONFIG_SMB_FS=m
811CONFIG_SMB_NLS_DEFAULT=y 940CONFIG_SMB_NLS_DEFAULT=y
812CONFIG_SMB_NLS_REMOTE="cp437" 941CONFIG_SMB_NLS_REMOTE="cp437"
813# CONFIG_CIFS is not set 942# CONFIG_CIFS is not set
814CONFIG_NCP_FS=m 943# CONFIG_NCP_FS is not set
815# CONFIG_NCPFS_PACKET_SIGNING is not set
816# CONFIG_NCPFS_IOCTL_LOCKING is not set
817# CONFIG_NCPFS_STRONG is not set
818# CONFIG_NCPFS_NFS_NS is not set
819# CONFIG_NCPFS_OS2_NS is not set
820# CONFIG_NCPFS_SMALLDOS is not set
821CONFIG_NCPFS_NLS=y
822# CONFIG_NCPFS_EXTRAS is not set
823CONFIG_CODA_FS=m 944CONFIG_CODA_FS=m
824# CONFIG_CODA_FS_OLD_API is not set 945# CONFIG_CODA_FS_OLD_API is not set
825# CONFIG_AFS_FS is not set 946# CONFIG_AFS_FS is not set
@@ -829,10 +950,6 @@ CONFIG_CODA_FS=m
829# 950#
830# CONFIG_PARTITION_ADVANCED is not set 951# CONFIG_PARTITION_ADVANCED is not set
831CONFIG_MSDOS_PARTITION=y 952CONFIG_MSDOS_PARTITION=y
832
833#
834# Native Language Support
835#
836CONFIG_NLS=y 953CONFIG_NLS=y
837CONFIG_NLS_DEFAULT="iso8859-1" 954CONFIG_NLS_DEFAULT="iso8859-1"
838CONFIG_NLS_CODEPAGE_437=y 955CONFIG_NLS_CODEPAGE_437=y
@@ -873,35 +990,42 @@ CONFIG_NLS_ISO8859_15=m
873CONFIG_NLS_KOI8_R=m 990CONFIG_NLS_KOI8_R=m
874CONFIG_NLS_KOI8_U=m 991CONFIG_NLS_KOI8_U=m
875CONFIG_NLS_UTF8=m 992CONFIG_NLS_UTF8=m
993CONFIG_DLM=m
994# CONFIG_DLM_DEBUG is not set
876 995
877# 996#
878# Kernel hacking 997# Kernel hacking
879# 998#
880# CONFIG_PRINTK_TIME is not set 999# CONFIG_PRINTK_TIME is not set
881CONFIG_DEBUG_KERNEL=y 1000CONFIG_ENABLE_WARN_DEPRECATED=y
1001CONFIG_ENABLE_MUST_CHECK=y
882CONFIG_MAGIC_SYSRQ=y 1002CONFIG_MAGIC_SYSRQ=y
883CONFIG_LOG_BUF_SHIFT=16 1003# CONFIG_UNUSED_SYMBOLS is not set
884# CONFIG_SCHEDSTATS is not set
885# CONFIG_DEBUG_SLAB is not set
886# CONFIG_DEBUG_SPINLOCK is not set
887# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
888# CONFIG_DEBUG_KOBJECT is not set
889CONFIG_DEBUG_BUGVERBOSE=y
890# CONFIG_DEBUG_INFO is not set
891# CONFIG_DEBUG_FS is not set 1004# CONFIG_DEBUG_FS is not set
892# CONFIG_FRAME_POINTER is not set 1005# CONFIG_HEADERS_CHECK is not set
1006# CONFIG_DEBUG_KERNEL is not set
1007CONFIG_DEBUG_BUGVERBOSE=y
1008# CONFIG_SAMPLES is not set
893 1009
894# 1010#
895# Security options 1011# Security options
896# 1012#
897# CONFIG_KEYS is not set 1013# CONFIG_KEYS is not set
898# CONFIG_SECURITY is not set 1014# CONFIG_SECURITY is not set
899 1015# CONFIG_SECURITY_FILE_CAPABILITIES is not set
900# 1016CONFIG_XOR_BLOCKS=m
901# Cryptographic options 1017CONFIG_ASYNC_CORE=m
902# 1018CONFIG_ASYNC_MEMCPY=m
1019CONFIG_ASYNC_XOR=m
903CONFIG_CRYPTO=y 1020CONFIG_CRYPTO=y
1021CONFIG_CRYPTO_ALGAPI=y
1022CONFIG_CRYPTO_AEAD=m
1023CONFIG_CRYPTO_BLKCIPHER=y
1024CONFIG_CRYPTO_SEQIV=m
1025CONFIG_CRYPTO_HASH=y
1026CONFIG_CRYPTO_MANAGER=y
904CONFIG_CRYPTO_HMAC=y 1027CONFIG_CRYPTO_HMAC=y
1028CONFIG_CRYPTO_XCBC=m
905CONFIG_CRYPTO_NULL=m 1029CONFIG_CRYPTO_NULL=m
906CONFIG_CRYPTO_MD4=m 1030CONFIG_CRYPTO_MD4=m
907CONFIG_CRYPTO_MD5=y 1031CONFIG_CRYPTO_MD5=y
@@ -910,9 +1034,21 @@ CONFIG_CRYPTO_SHA256=m
910CONFIG_CRYPTO_SHA512=m 1034CONFIG_CRYPTO_SHA512=m
911CONFIG_CRYPTO_WP512=m 1035CONFIG_CRYPTO_WP512=m
912CONFIG_CRYPTO_TGR192=m 1036CONFIG_CRYPTO_TGR192=m
1037CONFIG_CRYPTO_GF128MUL=m
1038CONFIG_CRYPTO_ECB=m
1039CONFIG_CRYPTO_CBC=y
1040CONFIG_CRYPTO_PCBC=m
1041CONFIG_CRYPTO_LRW=m
1042CONFIG_CRYPTO_XTS=m
1043CONFIG_CRYPTO_CTR=m
1044CONFIG_CRYPTO_GCM=m
1045CONFIG_CRYPTO_CCM=m
1046CONFIG_CRYPTO_CRYPTD=m
913CONFIG_CRYPTO_DES=y 1047CONFIG_CRYPTO_DES=y
1048CONFIG_CRYPTO_FCRYPT=m
914CONFIG_CRYPTO_BLOWFISH=m 1049CONFIG_CRYPTO_BLOWFISH=m
915CONFIG_CRYPTO_TWOFISH=m 1050CONFIG_CRYPTO_TWOFISH=m
1051CONFIG_CRYPTO_TWOFISH_COMMON=m
916CONFIG_CRYPTO_SERPENT=m 1052CONFIG_CRYPTO_SERPENT=m
917CONFIG_CRYPTO_AES=m 1053CONFIG_CRYPTO_AES=m
918CONFIG_CRYPTO_CAST5=m 1054CONFIG_CRYPTO_CAST5=m
@@ -921,20 +1057,35 @@ CONFIG_CRYPTO_TEA=m
921CONFIG_CRYPTO_ARC4=m 1057CONFIG_CRYPTO_ARC4=m
922CONFIG_CRYPTO_KHAZAD=m 1058CONFIG_CRYPTO_KHAZAD=m
923CONFIG_CRYPTO_ANUBIS=m 1059CONFIG_CRYPTO_ANUBIS=m
1060CONFIG_CRYPTO_SEED=m
1061CONFIG_CRYPTO_SALSA20=m
924CONFIG_CRYPTO_DEFLATE=m 1062CONFIG_CRYPTO_DEFLATE=m
925CONFIG_CRYPTO_MICHAEL_MIC=m 1063CONFIG_CRYPTO_MICHAEL_MIC=m
926CONFIG_CRYPTO_CRC32C=m 1064CONFIG_CRYPTO_CRC32C=m
1065CONFIG_CRYPTO_CAMELLIA=m
927CONFIG_CRYPTO_TEST=m 1066CONFIG_CRYPTO_TEST=m
928 1067CONFIG_CRYPTO_AUTHENC=m
929# 1068CONFIG_CRYPTO_LZO=m
930# Hardware crypto devices 1069# CONFIG_CRYPTO_HW is not set
931#
932 1070
933# 1071#
934# Library routines 1072# Library routines
935# 1073#
1074CONFIG_BITREVERSE=y
936CONFIG_CRC_CCITT=m 1075CONFIG_CRC_CCITT=m
1076CONFIG_CRC16=m
1077# CONFIG_CRC_ITU_T is not set
937CONFIG_CRC32=y 1078CONFIG_CRC32=y
1079# CONFIG_CRC7 is not set
938CONFIG_LIBCRC32C=m 1080CONFIG_LIBCRC32C=m
939CONFIG_ZLIB_INFLATE=y 1081CONFIG_ZLIB_INFLATE=y
940CONFIG_ZLIB_DEFLATE=m 1082CONFIG_ZLIB_DEFLATE=m
1083CONFIG_LZO_COMPRESS=m
1084CONFIG_LZO_DECOMPRESS=m
1085CONFIG_TEXTSEARCH=y
1086CONFIG_TEXTSEARCH_KMP=m
1087CONFIG_TEXTSEARCH_BM=m
1088CONFIG_TEXTSEARCH_FSM=m
1089CONFIG_PLIST=y
1090CONFIG_HAS_IOMEM=y
1091CONFIG_HAS_DMA=y
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index af903b5c570..bd2b9c4927c 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:35:02 2005 4# Wed Apr 2 20:46:22 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16CONFIG_NO_DMA=y
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-sun3" 27CONFIG_LOCALVERSION="-sun3"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -69,10 +117,24 @@ CONFIG_SUN3=y
69# 117#
70CONFIG_M68020=y 118CONFIG_M68020=y
71CONFIG_MMU_SUN3=y 119CONFIG_MMU_SUN3=y
72CONFIG_M68KFPU_EMU=y 120# CONFIG_M68KFPU_EMU is not set
73CONFIG_M68KFPU_EMU_EXTRAPREC=y
74# CONFIG_M68KFPU_EMU_ONLY is not set
75# CONFIG_ADVANCED is not set 121# CONFIG_ADVANCED is not set
122CONFIG_SINGLE_MEMORY_CHUNK=y
123# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
124CONFIG_SELECT_MEMORY_MODEL=y
125CONFIG_FLATMEM_MANUAL=y
126# CONFIG_DISCONTIGMEM_MANUAL is not set
127# CONFIG_SPARSEMEM_MANUAL is not set
128CONFIG_FLATMEM=y
129CONFIG_FLAT_NODE_MEM_MAP=y
130CONFIG_NEED_MULTIPLE_NODES=y
131# CONFIG_SPARSEMEM_STATIC is not set
132# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_RESOURCES_64BIT is not set
135CONFIG_ZONE_DMA_FLAG=1
136CONFIG_BOUNCE=y
137CONFIG_VIRT_TO_BUS=y
76 138
77# 139#
78# General setup 140# General setup
@@ -81,134 +143,11 @@ CONFIG_BINFMT_ELF=y
81CONFIG_BINFMT_AOUT=m 143CONFIG_BINFMT_AOUT=m
82CONFIG_BINFMT_MISC=m 144CONFIG_BINFMT_MISC=m
83CONFIG_PROC_HARDWARE=y 145CONFIG_PROC_HARDWARE=y
146CONFIG_ZONE_DMA=y
147# CONFIG_ARCH_SUPPORTS_MSI is not set
84 148
85# 149#
86# Device Drivers 150# Networking
87#
88
89#
90# Generic Driver Options
91#
92CONFIG_STANDALONE=y
93CONFIG_PREVENT_FIRMWARE_BUILD=y
94CONFIG_FW_LOADER=m
95# CONFIG_DEBUG_DRIVER is not set
96
97#
98# Memory Technology Devices (MTD)
99#
100# CONFIG_MTD is not set
101
102#
103# Parallel port support
104#
105# CONFIG_PARPORT is not set
106
107#
108# Plug and Play support
109#
110
111#
112# Block devices
113#
114# CONFIG_BLK_DEV_COW_COMMON is not set
115CONFIG_BLK_DEV_LOOP=y
116CONFIG_BLK_DEV_CRYPTOLOOP=m
117CONFIG_BLK_DEV_NBD=m
118CONFIG_BLK_DEV_RAM=y
119CONFIG_BLK_DEV_RAM_COUNT=16
120CONFIG_BLK_DEV_RAM_SIZE=4096
121CONFIG_BLK_DEV_INITRD=y
122CONFIG_INITRAMFS_SOURCE=""
123CONFIG_CDROM_PKTCDVD=m
124CONFIG_CDROM_PKTCDVD_BUFFERS=8
125# CONFIG_CDROM_PKTCDVD_WCACHE is not set
126
127#
128# IO Schedulers
129#
130CONFIG_IOSCHED_NOOP=y
131CONFIG_IOSCHED_AS=y
132CONFIG_IOSCHED_DEADLINE=y
133CONFIG_IOSCHED_CFQ=y
134CONFIG_ATA_OVER_ETH=m
135
136#
137# ATA/ATAPI/MFM/RLL support
138#
139# CONFIG_IDE is not set
140
141#
142# SCSI device support
143#
144CONFIG_SCSI=y
145CONFIG_SCSI_PROC_FS=y
146
147#
148# SCSI support type (disk, tape, CD-ROM)
149#
150CONFIG_BLK_DEV_SD=y
151CONFIG_CHR_DEV_ST=m
152# CONFIG_CHR_DEV_OSST is not set
153CONFIG_BLK_DEV_SR=y
154CONFIG_BLK_DEV_SR_VENDOR=y
155CONFIG_CHR_DEV_SG=m
156
157#
158# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
159#
160# CONFIG_SCSI_MULTI_LUN is not set
161CONFIG_SCSI_CONSTANTS=y
162# CONFIG_SCSI_LOGGING is not set
163
164#
165# SCSI Transport Attributes
166#
167# CONFIG_SCSI_SPI_ATTRS is not set
168# CONFIG_SCSI_FC_ATTRS is not set
169# CONFIG_SCSI_ISCSI_ATTRS is not set
170
171#
172# SCSI low-level drivers
173#
174# CONFIG_SCSI_SATA is not set
175# CONFIG_SCSI_DEBUG is not set
176
177#
178# Multi-device support (RAID and LVM)
179#
180CONFIG_MD=y
181CONFIG_BLK_DEV_MD=m
182CONFIG_MD_LINEAR=m
183CONFIG_MD_RAID0=m
184CONFIG_MD_RAID1=m
185# CONFIG_MD_RAID10 is not set
186CONFIG_MD_RAID5=m
187CONFIG_MD_RAID6=m
188CONFIG_MD_MULTIPATH=m
189# CONFIG_MD_FAULTY is not set
190CONFIG_BLK_DEV_DM=m
191CONFIG_DM_CRYPT=m
192CONFIG_DM_SNAPSHOT=m
193CONFIG_DM_MIRROR=m
194CONFIG_DM_ZERO=m
195CONFIG_DM_MULTIPATH=m
196CONFIG_DM_MULTIPATH_EMC=m
197
198#
199# Fusion MPT device support
200#
201
202#
203# IEEE 1394 (FireWire) support
204#
205
206#
207# I2O device support
208#
209
210#
211# Networking support
212# 151#
213CONFIG_NET=y 152CONFIG_NET=y
214 153
@@ -218,10 +157,17 @@ CONFIG_NET=y
218CONFIG_PACKET=y 157CONFIG_PACKET=y
219# CONFIG_PACKET_MMAP is not set 158# CONFIG_PACKET_MMAP is not set
220CONFIG_UNIX=y 159CONFIG_UNIX=y
160CONFIG_XFRM=y
161# CONFIG_XFRM_USER is not set
162# CONFIG_XFRM_SUB_POLICY is not set
163CONFIG_XFRM_MIGRATE=y
164# CONFIG_XFRM_STATISTICS is not set
221CONFIG_NET_KEY=y 165CONFIG_NET_KEY=y
166CONFIG_NET_KEY_MIGRATE=y
222CONFIG_INET=y 167CONFIG_INET=y
223# CONFIG_IP_MULTICAST is not set 168# CONFIG_IP_MULTICAST is not set
224# CONFIG_IP_ADVANCED_ROUTER is not set 169# CONFIG_IP_ADVANCED_ROUTER is not set
170CONFIG_IP_FIB_HASH=y
225CONFIG_IP_PNP=y 171CONFIG_IP_PNP=y
226CONFIG_IP_PNP_DHCP=y 172CONFIG_IP_PNP_DHCP=y
227CONFIG_IP_PNP_BOOTP=y 173CONFIG_IP_PNP_BOOTP=y
@@ -233,145 +179,199 @@ CONFIG_SYN_COOKIES=y
233CONFIG_INET_AH=m 179CONFIG_INET_AH=m
234CONFIG_INET_ESP=m 180CONFIG_INET_ESP=m
235CONFIG_INET_IPCOMP=m 181CONFIG_INET_IPCOMP=m
182CONFIG_INET_XFRM_TUNNEL=m
236CONFIG_INET_TUNNEL=m 183CONFIG_INET_TUNNEL=m
237CONFIG_IP_TCPDIAG=m 184CONFIG_INET_XFRM_MODE_TRANSPORT=m
238CONFIG_IP_TCPDIAG_IPV6=y 185CONFIG_INET_XFRM_MODE_TUNNEL=m
239 186CONFIG_INET_XFRM_MODE_BEET=m
240# 187CONFIG_INET_LRO=m
241# IP: Virtual Server Configuration 188CONFIG_INET_DIAG=m
242# 189CONFIG_INET_TCP_DIAG=m
190# CONFIG_TCP_CONG_ADVANCED is not set
191CONFIG_TCP_CONG_CUBIC=y
192CONFIG_DEFAULT_TCP_CONG="cubic"
193# CONFIG_TCP_MD5SIG is not set
243# CONFIG_IP_VS is not set 194# CONFIG_IP_VS is not set
244CONFIG_IPV6=m 195CONFIG_IPV6=m
245CONFIG_IPV6_PRIVACY=y 196CONFIG_IPV6_PRIVACY=y
197CONFIG_IPV6_ROUTER_PREF=y
198CONFIG_IPV6_ROUTE_INFO=y
199# CONFIG_IPV6_OPTIMISTIC_DAD is not set
246CONFIG_INET6_AH=m 200CONFIG_INET6_AH=m
247CONFIG_INET6_ESP=m 201CONFIG_INET6_ESP=m
248CONFIG_INET6_IPCOMP=m 202CONFIG_INET6_IPCOMP=m
203# CONFIG_IPV6_MIP6 is not set
204CONFIG_INET6_XFRM_TUNNEL=m
249CONFIG_INET6_TUNNEL=m 205CONFIG_INET6_TUNNEL=m
206CONFIG_INET6_XFRM_MODE_TRANSPORT=m
207CONFIG_INET6_XFRM_MODE_TUNNEL=m
208CONFIG_INET6_XFRM_MODE_BEET=m
209CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
210CONFIG_IPV6_SIT=m
250CONFIG_IPV6_TUNNEL=m 211CONFIG_IPV6_TUNNEL=m
212# CONFIG_IPV6_MULTIPLE_TABLES is not set
213# CONFIG_NETWORK_SECMARK is not set
251CONFIG_NETFILTER=y 214CONFIG_NETFILTER=y
252# CONFIG_NETFILTER_DEBUG is not set 215# CONFIG_NETFILTER_DEBUG is not set
216CONFIG_NETFILTER_ADVANCED=y
217
218#
219# Core Netfilter Configuration
220#
221CONFIG_NETFILTER_NETLINK=m
222CONFIG_NETFILTER_NETLINK_QUEUE=m
223CONFIG_NETFILTER_NETLINK_LOG=m
224CONFIG_NF_CONNTRACK=m
225CONFIG_NF_CT_ACCT=y
226CONFIG_NF_CONNTRACK_MARK=y
227# CONFIG_NF_CONNTRACK_EVENTS is not set
228CONFIG_NF_CT_PROTO_GRE=m
229CONFIG_NF_CT_PROTO_SCTP=m
230CONFIG_NF_CT_PROTO_UDPLITE=m
231CONFIG_NF_CONNTRACK_AMANDA=m
232CONFIG_NF_CONNTRACK_FTP=m
233CONFIG_NF_CONNTRACK_H323=m
234CONFIG_NF_CONNTRACK_IRC=m
235CONFIG_NF_CONNTRACK_NETBIOS_NS=m
236CONFIG_NF_CONNTRACK_PPTP=m
237CONFIG_NF_CONNTRACK_SANE=m
238CONFIG_NF_CONNTRACK_SIP=m
239CONFIG_NF_CONNTRACK_TFTP=m
240# CONFIG_NF_CT_NETLINK is not set
241CONFIG_NETFILTER_XTABLES=m
242CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
243CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
244CONFIG_NETFILTER_XT_TARGET_DSCP=m
245CONFIG_NETFILTER_XT_TARGET_MARK=m
246CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
247CONFIG_NETFILTER_XT_TARGET_NFLOG=m
248CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
249CONFIG_NETFILTER_XT_TARGET_RATEEST=m
250CONFIG_NETFILTER_XT_TARGET_TRACE=m
251CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
252CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
253CONFIG_NETFILTER_XT_MATCH_COMMENT=m
254CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
255CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
256CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
257CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
258CONFIG_NETFILTER_XT_MATCH_DCCP=m
259CONFIG_NETFILTER_XT_MATCH_DSCP=m
260CONFIG_NETFILTER_XT_MATCH_ESP=m
261CONFIG_NETFILTER_XT_MATCH_HELPER=m
262CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
263CONFIG_NETFILTER_XT_MATCH_LENGTH=m
264CONFIG_NETFILTER_XT_MATCH_LIMIT=m
265CONFIG_NETFILTER_XT_MATCH_MAC=m
266CONFIG_NETFILTER_XT_MATCH_MARK=m
267CONFIG_NETFILTER_XT_MATCH_OWNER=m
268CONFIG_NETFILTER_XT_MATCH_POLICY=m
269CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
270CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
271CONFIG_NETFILTER_XT_MATCH_QUOTA=m
272CONFIG_NETFILTER_XT_MATCH_RATEEST=m
273CONFIG_NETFILTER_XT_MATCH_REALM=m
274CONFIG_NETFILTER_XT_MATCH_SCTP=m
275CONFIG_NETFILTER_XT_MATCH_STATE=m
276CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
277CONFIG_NETFILTER_XT_MATCH_STRING=m
278CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
279CONFIG_NETFILTER_XT_MATCH_TIME=m
280CONFIG_NETFILTER_XT_MATCH_U32=m
281CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
253 282
254# 283#
255# IP: Netfilter Configuration 284# IP: Netfilter Configuration
256# 285#
257CONFIG_IP_NF_CONNTRACK=m 286CONFIG_NF_CONNTRACK_IPV4=m
258# CONFIG_IP_NF_CT_ACCT is not set 287CONFIG_NF_CONNTRACK_PROC_COMPAT=y
259CONFIG_IP_NF_CONNTRACK_MARK=y
260# CONFIG_IP_NF_CT_PROTO_SCTP is not set
261CONFIG_IP_NF_FTP=m
262CONFIG_IP_NF_IRC=m
263CONFIG_IP_NF_TFTP=m
264CONFIG_IP_NF_AMANDA=m
265CONFIG_IP_NF_QUEUE=m 288CONFIG_IP_NF_QUEUE=m
266CONFIG_IP_NF_IPTABLES=m 289CONFIG_IP_NF_IPTABLES=m
267CONFIG_IP_NF_MATCH_LIMIT=m
268CONFIG_IP_NF_MATCH_IPRANGE=m
269CONFIG_IP_NF_MATCH_MAC=m
270CONFIG_IP_NF_MATCH_PKTTYPE=m
271CONFIG_IP_NF_MATCH_MARK=m
272CONFIG_IP_NF_MATCH_MULTIPORT=m
273CONFIG_IP_NF_MATCH_TOS=m
274CONFIG_IP_NF_MATCH_RECENT=m 290CONFIG_IP_NF_MATCH_RECENT=m
275CONFIG_IP_NF_MATCH_ECN=m 291CONFIG_IP_NF_MATCH_ECN=m
276CONFIG_IP_NF_MATCH_DSCP=m 292CONFIG_IP_NF_MATCH_AH=m
277CONFIG_IP_NF_MATCH_AH_ESP=m
278CONFIG_IP_NF_MATCH_LENGTH=m
279CONFIG_IP_NF_MATCH_TTL=m 293CONFIG_IP_NF_MATCH_TTL=m
280CONFIG_IP_NF_MATCH_TCPMSS=m
281CONFIG_IP_NF_MATCH_HELPER=m
282CONFIG_IP_NF_MATCH_STATE=m
283CONFIG_IP_NF_MATCH_CONNTRACK=m
284CONFIG_IP_NF_MATCH_OWNER=m
285CONFIG_IP_NF_MATCH_ADDRTYPE=m 294CONFIG_IP_NF_MATCH_ADDRTYPE=m
286CONFIG_IP_NF_MATCH_REALM=m
287# CONFIG_IP_NF_MATCH_SCTP is not set
288# CONFIG_IP_NF_MATCH_COMMENT is not set
289CONFIG_IP_NF_MATCH_CONNMARK=m
290CONFIG_IP_NF_MATCH_HASHLIMIT=m
291CONFIG_IP_NF_FILTER=m 295CONFIG_IP_NF_FILTER=m
292CONFIG_IP_NF_TARGET_REJECT=m 296CONFIG_IP_NF_TARGET_REJECT=m
293CONFIG_IP_NF_TARGET_LOG=m 297CONFIG_IP_NF_TARGET_LOG=m
294CONFIG_IP_NF_TARGET_ULOG=m 298CONFIG_IP_NF_TARGET_ULOG=m
295CONFIG_IP_NF_TARGET_TCPMSS=m 299CONFIG_NF_NAT=m
296CONFIG_IP_NF_NAT=m 300CONFIG_NF_NAT_NEEDED=y
297CONFIG_IP_NF_NAT_NEEDED=y
298CONFIG_IP_NF_TARGET_MASQUERADE=m 301CONFIG_IP_NF_TARGET_MASQUERADE=m
299CONFIG_IP_NF_TARGET_REDIRECT=m 302CONFIG_IP_NF_TARGET_REDIRECT=m
300CONFIG_IP_NF_TARGET_NETMAP=m 303CONFIG_IP_NF_TARGET_NETMAP=m
301CONFIG_IP_NF_TARGET_SAME=m 304CONFIG_NF_NAT_SNMP_BASIC=m
302CONFIG_IP_NF_NAT_SNMP_BASIC=m 305CONFIG_NF_NAT_PROTO_GRE=m
303CONFIG_IP_NF_NAT_IRC=m 306CONFIG_NF_NAT_FTP=m
304CONFIG_IP_NF_NAT_FTP=m 307CONFIG_NF_NAT_IRC=m
305CONFIG_IP_NF_NAT_TFTP=m 308CONFIG_NF_NAT_TFTP=m
306CONFIG_IP_NF_NAT_AMANDA=m 309CONFIG_NF_NAT_AMANDA=m
310CONFIG_NF_NAT_PPTP=m
311CONFIG_NF_NAT_H323=m
312CONFIG_NF_NAT_SIP=m
307CONFIG_IP_NF_MANGLE=m 313CONFIG_IP_NF_MANGLE=m
308CONFIG_IP_NF_TARGET_TOS=m
309CONFIG_IP_NF_TARGET_ECN=m 314CONFIG_IP_NF_TARGET_ECN=m
310CONFIG_IP_NF_TARGET_DSCP=m 315CONFIG_IP_NF_TARGET_TTL=m
311CONFIG_IP_NF_TARGET_MARK=m 316CONFIG_IP_NF_TARGET_CLUSTERIP=m
312CONFIG_IP_NF_TARGET_CLASSIFY=m
313CONFIG_IP_NF_TARGET_CONNMARK=m
314# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
315CONFIG_IP_NF_RAW=m 317CONFIG_IP_NF_RAW=m
316CONFIG_IP_NF_TARGET_NOTRACK=m
317CONFIG_IP_NF_ARPTABLES=m 318CONFIG_IP_NF_ARPTABLES=m
318CONFIG_IP_NF_ARPFILTER=m 319CONFIG_IP_NF_ARPFILTER=m
319CONFIG_IP_NF_ARP_MANGLE=m 320CONFIG_IP_NF_ARP_MANGLE=m
320 321
321# 322#
322# IPv6: Netfilter Configuration (EXPERIMENTAL) 323# IPv6: Netfilter Configuration
323# 324#
325CONFIG_NF_CONNTRACK_IPV6=m
324CONFIG_IP6_NF_QUEUE=m 326CONFIG_IP6_NF_QUEUE=m
325CONFIG_IP6_NF_IPTABLES=m 327CONFIG_IP6_NF_IPTABLES=m
326CONFIG_IP6_NF_MATCH_LIMIT=m
327CONFIG_IP6_NF_MATCH_MAC=m
328CONFIG_IP6_NF_MATCH_RT=m 328CONFIG_IP6_NF_MATCH_RT=m
329CONFIG_IP6_NF_MATCH_OPTS=m 329CONFIG_IP6_NF_MATCH_OPTS=m
330CONFIG_IP6_NF_MATCH_FRAG=m 330CONFIG_IP6_NF_MATCH_FRAG=m
331CONFIG_IP6_NF_MATCH_HL=m 331CONFIG_IP6_NF_MATCH_HL=m
332CONFIG_IP6_NF_MATCH_MULTIPORT=m
333CONFIG_IP6_NF_MATCH_OWNER=m
334CONFIG_IP6_NF_MATCH_MARK=m
335CONFIG_IP6_NF_MATCH_IPV6HEADER=m 332CONFIG_IP6_NF_MATCH_IPV6HEADER=m
336CONFIG_IP6_NF_MATCH_AHESP=m 333CONFIG_IP6_NF_MATCH_AH=m
337CONFIG_IP6_NF_MATCH_LENGTH=m 334CONFIG_IP6_NF_MATCH_MH=m
338CONFIG_IP6_NF_MATCH_EUI64=m 335CONFIG_IP6_NF_MATCH_EUI64=m
339CONFIG_IP6_NF_FILTER=m 336CONFIG_IP6_NF_FILTER=m
340CONFIG_IP6_NF_TARGET_LOG=m 337CONFIG_IP6_NF_TARGET_LOG=m
338CONFIG_IP6_NF_TARGET_REJECT=m
341CONFIG_IP6_NF_MANGLE=m 339CONFIG_IP6_NF_MANGLE=m
342CONFIG_IP6_NF_TARGET_MARK=m 340CONFIG_IP6_NF_TARGET_HL=m
343CONFIG_IP6_NF_RAW=m 341CONFIG_IP6_NF_RAW=m
344CONFIG_XFRM=y 342CONFIG_IP_DCCP=m
345# CONFIG_XFRM_USER is not set 343CONFIG_INET_DCCP_DIAG=m
344CONFIG_IP_DCCP_ACKVEC=y
346 345
347# 346#
348# SCTP Configuration (EXPERIMENTAL) 347# DCCP CCIDs Configuration (EXPERIMENTAL)
349# 348#
349CONFIG_IP_DCCP_CCID2=m
350# CONFIG_IP_DCCP_CCID2_DEBUG is not set
351CONFIG_IP_DCCP_CCID3=m
352# CONFIG_IP_DCCP_CCID3_DEBUG is not set
353CONFIG_IP_DCCP_CCID3_RTO=100
354CONFIG_IP_DCCP_TFRC_LIB=m
350CONFIG_IP_SCTP=m 355CONFIG_IP_SCTP=m
351# CONFIG_SCTP_DBG_MSG is not set 356# CONFIG_SCTP_DBG_MSG is not set
352# CONFIG_SCTP_DBG_OBJCNT is not set 357# CONFIG_SCTP_DBG_OBJCNT is not set
353# CONFIG_SCTP_HMAC_NONE is not set 358# CONFIG_SCTP_HMAC_NONE is not set
354# CONFIG_SCTP_HMAC_SHA1 is not set 359# CONFIG_SCTP_HMAC_SHA1 is not set
355CONFIG_SCTP_HMAC_MD5=y 360CONFIG_SCTP_HMAC_MD5=y
361# CONFIG_TIPC is not set
356# CONFIG_ATM is not set 362# CONFIG_ATM is not set
357# CONFIG_BRIDGE is not set 363# CONFIG_BRIDGE is not set
358# CONFIG_VLAN_8021Q is not set 364# CONFIG_VLAN_8021Q is not set
359# CONFIG_DECNET is not set 365# CONFIG_DECNET is not set
360CONFIG_LLC=m 366CONFIG_LLC=m
361# CONFIG_LLC2 is not set 367# CONFIG_LLC2 is not set
362CONFIG_IPX=m 368# CONFIG_IPX is not set
363# CONFIG_IPX_INTERN is not set
364CONFIG_ATALK=m 369CONFIG_ATALK=m
365# CONFIG_DEV_APPLETALK is not set 370# CONFIG_DEV_APPLETALK is not set
366# CONFIG_X25 is not set 371# CONFIG_X25 is not set
367# CONFIG_LAPB is not set 372# CONFIG_LAPB is not set
368# CONFIG_NET_DIVERT is not set
369# CONFIG_ECONET is not set 373# CONFIG_ECONET is not set
370# CONFIG_WAN_ROUTER is not set 374# CONFIG_WAN_ROUTER is not set
371
372#
373# QoS and/or fair queueing
374#
375# CONFIG_NET_SCHED is not set 375# CONFIG_NET_SCHED is not set
376CONFIG_NET_CLS_ROUTE=y 376CONFIG_NET_CLS_ROUTE=y
377 377
@@ -379,47 +379,156 @@ CONFIG_NET_CLS_ROUTE=y
379# Network testing 379# Network testing
380# 380#
381# CONFIG_NET_PKTGEN is not set 381# CONFIG_NET_PKTGEN is not set
382CONFIG_NETPOLL=y
383# CONFIG_NETPOLL_RX is not set
384# CONFIG_NETPOLL_TRAP is not set
385CONFIG_NET_POLL_CONTROLLER=y
386# CONFIG_HAMRADIO is not set 382# CONFIG_HAMRADIO is not set
383# CONFIG_CAN is not set
387# CONFIG_IRDA is not set 384# CONFIG_IRDA is not set
388# CONFIG_BT is not set 385# CONFIG_BT is not set
389CONFIG_NETDEVICES=y 386# CONFIG_AF_RXRPC is not set
390CONFIG_DUMMY=m
391# CONFIG_BONDING is not set
392CONFIG_EQUALIZER=m
393# CONFIG_TUN is not set
394 387
395# 388#
396# Ethernet (10 or 100Mbit) 389# Wireless
397# 390#
398CONFIG_NET_ETHERNET=y 391# CONFIG_CFG80211 is not set
399CONFIG_MII=m 392CONFIG_WIRELESS_EXT=y
400CONFIG_SUN3LANCE=y 393# CONFIG_MAC80211 is not set
401CONFIG_SUN3_82586=y 394CONFIG_IEEE80211=m
395# CONFIG_IEEE80211_DEBUG is not set
396CONFIG_IEEE80211_CRYPT_WEP=m
397CONFIG_IEEE80211_CRYPT_CCMP=m
398CONFIG_IEEE80211_CRYPT_TKIP=m
399CONFIG_IEEE80211_SOFTMAC=m
400# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
401# CONFIG_RFKILL is not set
402# CONFIG_NET_9P is not set
402 403
403# 404#
404# Ethernet (1000 Mbit) 405# Device Drivers
405# 406#
406 407
407# 408#
408# Ethernet (10000 Mbit) 409# Generic Driver Options
409# 410#
411CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
412CONFIG_STANDALONE=y
413CONFIG_PREVENT_FIRMWARE_BUILD=y
414CONFIG_FW_LOADER=m
415# CONFIG_SYS_HYPERVISOR is not set
416CONFIG_CONNECTOR=m
417# CONFIG_MTD is not set
418# CONFIG_PARPORT is not set
419CONFIG_BLK_DEV=y
420# CONFIG_BLK_DEV_COW_COMMON is not set
421CONFIG_BLK_DEV_LOOP=y
422CONFIG_BLK_DEV_CRYPTOLOOP=m
423CONFIG_BLK_DEV_NBD=m
424CONFIG_BLK_DEV_RAM=y
425CONFIG_BLK_DEV_RAM_COUNT=16
426CONFIG_BLK_DEV_RAM_SIZE=4096
427# CONFIG_BLK_DEV_XIP is not set
428CONFIG_CDROM_PKTCDVD=m
429CONFIG_CDROM_PKTCDVD_BUFFERS=8
430# CONFIG_CDROM_PKTCDVD_WCACHE is not set
431CONFIG_ATA_OVER_ETH=m
432CONFIG_MISC_DEVICES=y
433# CONFIG_EEPROM_93CX6 is not set
434# CONFIG_ENCLOSURE_SERVICES is not set
435CONFIG_HAVE_IDE=y
436# CONFIG_IDE is not set
410 437
411# 438#
412# Token Ring devices 439# SCSI device support
413# 440#
441CONFIG_RAID_ATTRS=m
442CONFIG_SCSI=y
443# CONFIG_SCSI_DMA is not set
444CONFIG_SCSI_TGT=m
445# CONFIG_SCSI_NETLINK is not set
446CONFIG_SCSI_PROC_FS=y
414 447
415# 448#
416# Wireless LAN (non-hamradio) 449# SCSI support type (disk, tape, CD-ROM)
417# 450#
418# CONFIG_NET_RADIO is not set 451CONFIG_BLK_DEV_SD=y
452CONFIG_CHR_DEV_ST=m
453CONFIG_CHR_DEV_OSST=m
454CONFIG_BLK_DEV_SR=y
455CONFIG_BLK_DEV_SR_VENDOR=y
456CONFIG_CHR_DEV_SG=m
457# CONFIG_CHR_DEV_SCH is not set
419 458
420# 459#
421# Wan interfaces 460# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
422# 461#
462# CONFIG_SCSI_MULTI_LUN is not set
463CONFIG_SCSI_CONSTANTS=y
464# CONFIG_SCSI_LOGGING is not set
465# CONFIG_SCSI_SCAN_ASYNC is not set
466CONFIG_SCSI_WAIT_SCAN=m
467
468#
469# SCSI Transports
470#
471CONFIG_SCSI_SPI_ATTRS=y
472# CONFIG_SCSI_FC_ATTRS is not set
473CONFIG_SCSI_ISCSI_ATTRS=m
474CONFIG_SCSI_SAS_ATTRS=m
475CONFIG_SCSI_SAS_LIBSAS=m
476CONFIG_SCSI_SAS_HOST_SMP=y
477# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
478CONFIG_SCSI_SRP_ATTRS=m
479CONFIG_SCSI_SRP_TGT_ATTRS=y
480CONFIG_SCSI_LOWLEVEL=y
481CONFIG_ISCSI_TCP=m
482# CONFIG_SCSI_DEBUG is not set
483CONFIG_SUN3_SCSI=y
484CONFIG_MD=y
485CONFIG_BLK_DEV_MD=m
486CONFIG_MD_LINEAR=m
487CONFIG_MD_RAID0=m
488CONFIG_MD_RAID1=m
489# CONFIG_MD_RAID10 is not set
490CONFIG_MD_RAID456=m
491CONFIG_MD_RAID5_RESHAPE=y
492CONFIG_MD_MULTIPATH=m
493# CONFIG_MD_FAULTY is not set
494CONFIG_BLK_DEV_DM=m
495# CONFIG_DM_DEBUG is not set
496CONFIG_DM_CRYPT=m
497CONFIG_DM_SNAPSHOT=m
498CONFIG_DM_MIRROR=m
499CONFIG_DM_ZERO=m
500CONFIG_DM_MULTIPATH=m
501CONFIG_DM_MULTIPATH_EMC=m
502CONFIG_DM_MULTIPATH_RDAC=m
503CONFIG_DM_MULTIPATH_HP=m
504# CONFIG_DM_DELAY is not set
505CONFIG_DM_UEVENT=y
506CONFIG_NETDEVICES=y
507# CONFIG_NETDEVICES_MULTIQUEUE is not set
508CONFIG_DUMMY=m
509# CONFIG_BONDING is not set
510CONFIG_MACVLAN=m
511CONFIG_EQUALIZER=m
512# CONFIG_TUN is not set
513CONFIG_VETH=m
514# CONFIG_PHYLIB is not set
515CONFIG_NET_ETHERNET=y
516# CONFIG_MII is not set
517CONFIG_SUN3LANCE=y
518CONFIG_SUN3_82586=y
519# CONFIG_IBM_NEW_EMAC_ZMII is not set
520# CONFIG_IBM_NEW_EMAC_RGMII is not set
521# CONFIG_IBM_NEW_EMAC_TAH is not set
522# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
523# CONFIG_B44 is not set
524# CONFIG_NETDEV_1000 is not set
525# CONFIG_NETDEV_10000 is not set
526
527#
528# Wireless LAN
529#
530# CONFIG_WLAN_PRE80211 is not set
531# CONFIG_WLAN_80211 is not set
423# CONFIG_WAN is not set 532# CONFIG_WAN is not set
424CONFIG_PPP=m 533CONFIG_PPP=m
425# CONFIG_PPP_MULTILINK is not set 534# CONFIG_PPP_MULTILINK is not set
@@ -428,28 +537,28 @@ CONFIG_PPP_ASYNC=m
428CONFIG_PPP_SYNC_TTY=m 537CONFIG_PPP_SYNC_TTY=m
429CONFIG_PPP_DEFLATE=m 538CONFIG_PPP_DEFLATE=m
430CONFIG_PPP_BSDCOMP=m 539CONFIG_PPP_BSDCOMP=m
540CONFIG_PPP_MPPE=m
431CONFIG_PPPOE=m 541CONFIG_PPPOE=m
542CONFIG_PPPOL2TP=m
432CONFIG_SLIP=m 543CONFIG_SLIP=m
433CONFIG_SLIP_COMPRESSED=y 544CONFIG_SLIP_COMPRESSED=y
545CONFIG_SLHC=m
434CONFIG_SLIP_SMART=y 546CONFIG_SLIP_SMART=y
435CONFIG_SLIP_MODE_SLIP6=y 547CONFIG_SLIP_MODE_SLIP6=y
436CONFIG_SHAPER=m
437CONFIG_NETCONSOLE=m 548CONFIG_NETCONSOLE=m
438 549CONFIG_NETCONSOLE_DYNAMIC=y
439# 550CONFIG_NETPOLL=y
440# ISDN subsystem 551# CONFIG_NETPOLL_TRAP is not set
441# 552CONFIG_NET_POLL_CONTROLLER=y
442# CONFIG_ISDN is not set 553# CONFIG_ISDN is not set
443
444#
445# Telephony Support
446#
447# CONFIG_PHONE is not set 554# CONFIG_PHONE is not set
448 555
449# 556#
450# Input device support 557# Input device support
451# 558#
452CONFIG_INPUT=y 559CONFIG_INPUT=y
560CONFIG_INPUT_FF_MEMLESS=m
561# CONFIG_INPUT_POLLDEV is not set
453 562
454# 563#
455# Userland interfaces 564# Userland interfaces
@@ -459,7 +568,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
459CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 568CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
460CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 569CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
461# CONFIG_INPUT_JOYDEV is not set 570# CONFIG_INPUT_JOYDEV is not set
462# CONFIG_INPUT_TSDEV is not set
463# CONFIG_INPUT_EVDEV is not set 571# CONFIG_INPUT_EVDEV is not set
464# CONFIG_INPUT_EVBUG is not set 572# CONFIG_INPUT_EVBUG is not set
465 573
@@ -472,11 +580,19 @@ CONFIG_KEYBOARD_SUNKBD=y
472# CONFIG_KEYBOARD_LKKBD is not set 580# CONFIG_KEYBOARD_LKKBD is not set
473# CONFIG_KEYBOARD_XTKBD is not set 581# CONFIG_KEYBOARD_XTKBD is not set
474# CONFIG_KEYBOARD_NEWTON is not set 582# CONFIG_KEYBOARD_NEWTON is not set
583# CONFIG_KEYBOARD_STOWAWAY is not set
475CONFIG_INPUT_MOUSE=y 584CONFIG_INPUT_MOUSE=y
476CONFIG_MOUSE_PS2=m 585CONFIG_MOUSE_PS2=m
586CONFIG_MOUSE_PS2_ALPS=y
587CONFIG_MOUSE_PS2_LOGIPS2PP=y
588CONFIG_MOUSE_PS2_SYNAPTICS=y
589CONFIG_MOUSE_PS2_LIFEBOOK=y
590CONFIG_MOUSE_PS2_TRACKPOINT=y
591# CONFIG_MOUSE_PS2_TOUCHKIT is not set
477CONFIG_MOUSE_SERIAL=m 592CONFIG_MOUSE_SERIAL=m
478# CONFIG_MOUSE_VSXXXAA is not set 593# CONFIG_MOUSE_VSXXXAA is not set
479# CONFIG_INPUT_JOYSTICK is not set 594# CONFIG_INPUT_JOYSTICK is not set
595# CONFIG_INPUT_TABLET is not set
480# CONFIG_INPUT_TOUCHSCREEN is not set 596# CONFIG_INPUT_TOUCHSCREEN is not set
481# CONFIG_INPUT_MISC is not set 597# CONFIG_INPUT_MISC is not set
482 598
@@ -484,7 +600,7 @@ CONFIG_MOUSE_SERIAL=m
484# Hardware I/O ports 600# Hardware I/O ports
485# 601#
486CONFIG_SERIO=y 602CONFIG_SERIO=y
487CONFIG_SERIO_SERPORT=m 603# CONFIG_SERIO_SERPORT is not set
488CONFIG_SERIO_LIBPS2=m 604CONFIG_SERIO_LIBPS2=m
489# CONFIG_SERIO_RAW is not set 605# CONFIG_SERIO_RAW is not set
490# CONFIG_GAMEPORT is not set 606# CONFIG_GAMEPORT is not set
@@ -495,6 +611,7 @@ CONFIG_SERIO_LIBPS2=m
495CONFIG_VT=y 611CONFIG_VT=y
496CONFIG_VT_CONSOLE=y 612CONFIG_VT_CONSOLE=y
497CONFIG_HW_CONSOLE=y 613CONFIG_HW_CONSOLE=y
614CONFIG_VT_HW_CONSOLE_BINDING=y
498# CONFIG_SERIAL_NONSTANDARD is not set 615# CONFIG_SERIAL_NONSTANDARD is not set
499 616
500# 617#
@@ -508,112 +625,113 @@ CONFIG_HW_CONSOLE=y
508CONFIG_UNIX98_PTYS=y 625CONFIG_UNIX98_PTYS=y
509CONFIG_LEGACY_PTYS=y 626CONFIG_LEGACY_PTYS=y
510CONFIG_LEGACY_PTY_COUNT=256 627CONFIG_LEGACY_PTY_COUNT=256
511
512#
513# IPMI
514#
515# CONFIG_IPMI_HANDLER is not set 628# CONFIG_IPMI_HANDLER is not set
516 629# CONFIG_HW_RANDOM is not set
517# 630CONFIG_GEN_RTC=m
518# Watchdog Cards
519#
520# CONFIG_WATCHDOG is not set
521CONFIG_GEN_RTC=y
522CONFIG_GEN_RTC_X=y 631CONFIG_GEN_RTC_X=y
523# CONFIG_DTLK is not set
524# CONFIG_R3964 is not set 632# CONFIG_R3964 is not set
525
526#
527# Ftape, the floppy tape device driver
528#
529# CONFIG_DRM is not set
530# CONFIG_RAW_DRIVER is not set 633# CONFIG_RAW_DRIVER is not set
531 634# CONFIG_TCG_TPM is not set
532#
533# TPM devices
534#
535
536#
537# I2C support
538#
539# CONFIG_I2C is not set 635# CONFIG_I2C is not set
540 636
541# 637#
542# Dallas's 1-wire bus 638# SPI support
543# 639#
640# CONFIG_SPI is not set
641# CONFIG_SPI_MASTER is not set
544# CONFIG_W1 is not set 642# CONFIG_W1 is not set
643# CONFIG_POWER_SUPPLY is not set
644# CONFIG_HWMON is not set
645# CONFIG_THERMAL is not set
646# CONFIG_WATCHDOG is not set
545 647
546# 648#
547# Misc devices 649# Sonics Silicon Backplane
548# 650#
651CONFIG_SSB_POSSIBLE=y
652# CONFIG_SSB is not set
549 653
550# 654#
551# Multimedia devices 655# Multifunction device drivers
552# 656#
553# CONFIG_VIDEO_DEV is not set 657# CONFIG_MFD_SM501 is not set
554 658
555# 659#
556# Digital Video Broadcasting Devices 660# Multimedia devices
557# 661#
558# CONFIG_DVB is not set 662# CONFIG_VIDEO_DEV is not set
663# CONFIG_DVB_CORE is not set
664# CONFIG_DAB is not set
559 665
560# 666#
561# Graphics support 667# Graphics support
562# 668#
669# CONFIG_VGASTATE is not set
670# CONFIG_VIDEO_OUTPUT_CONTROL is not set
563CONFIG_FB=y 671CONFIG_FB=y
672# CONFIG_FIRMWARE_EDID is not set
673# CONFIG_FB_DDC is not set
564# CONFIG_FB_CFB_FILLRECT is not set 674# CONFIG_FB_CFB_FILLRECT is not set
565# CONFIG_FB_CFB_COPYAREA is not set 675# CONFIG_FB_CFB_COPYAREA is not set
566# CONFIG_FB_CFB_IMAGEBLIT is not set 676# CONFIG_FB_CFB_IMAGEBLIT is not set
567# CONFIG_FB_SOFT_CURSOR is not set 677# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
678# CONFIG_FB_SYS_FILLRECT is not set
679# CONFIG_FB_SYS_COPYAREA is not set
680# CONFIG_FB_SYS_IMAGEBLIT is not set
681# CONFIG_FB_SYS_FOPS is not set
682CONFIG_FB_DEFERRED_IO=y
683# CONFIG_FB_SVGALIB is not set
568# CONFIG_FB_MACMODES is not set 684# CONFIG_FB_MACMODES is not set
569CONFIG_FB_MODE_HELPERS=y 685# CONFIG_FB_BACKLIGHT is not set
686# CONFIG_FB_MODE_HELPERS is not set
570# CONFIG_FB_TILEBLITTING is not set 687# CONFIG_FB_TILEBLITTING is not set
688
689#
690# Frame buffer hardware drivers
691#
692# CONFIG_FB_UVESA is not set
571# CONFIG_FB_S1D13XXX is not set 693# CONFIG_FB_S1D13XXX is not set
572# CONFIG_FB_VIRTUAL is not set 694# CONFIG_FB_VIRTUAL is not set
695# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
696
697#
698# Display device support
699#
700# CONFIG_DISPLAY_SUPPORT is not set
573 701
574# 702#
575# Console display driver support 703# Console display driver support
576# 704#
577CONFIG_DUMMY_CONSOLE=y 705CONFIG_DUMMY_CONSOLE=y
578CONFIG_FRAMEBUFFER_CONSOLE=y 706CONFIG_FRAMEBUFFER_CONSOLE=y
707# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
708# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
579# CONFIG_FONTS is not set 709# CONFIG_FONTS is not set
580CONFIG_FONT_8x8=y 710CONFIG_FONT_8x8=y
581CONFIG_FONT_8x16=y 711CONFIG_FONT_8x16=y
582
583#
584# Logo configuration
585#
586CONFIG_LOGO=y 712CONFIG_LOGO=y
587CONFIG_LOGO_LINUX_MONO=y 713CONFIG_LOGO_LINUX_MONO=y
588CONFIG_LOGO_LINUX_VGA16=y 714CONFIG_LOGO_LINUX_VGA16=y
589CONFIG_LOGO_LINUX_CLUT224=y 715CONFIG_LOGO_LINUX_CLUT224=y
590# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
591 716
592# 717#
593# Sound 718# Sound
594# 719#
595# CONFIG_SOUND is not set 720# CONFIG_SOUND is not set
596 721CONFIG_HID_SUPPORT=y
597# 722CONFIG_HID=m
598# USB support 723# CONFIG_HID_DEBUG is not set
599# 724CONFIG_HIDRAW=y
600# CONFIG_USB_ARCH_HAS_HCD is not set 725# CONFIG_USB_SUPPORT is not set
601# CONFIG_USB_ARCH_HAS_OHCI is not set
602
603#
604# USB Gadget Support
605#
606# CONFIG_USB_GADGET is not set
607
608#
609# MMC/SD Card support
610#
611# CONFIG_MMC is not set 726# CONFIG_MMC is not set
727# CONFIG_MEMSTICK is not set
728# CONFIG_NEW_LEDS is not set
729# CONFIG_RTC_CLASS is not set
612 730
613# 731#
614# InfiniBand support 732# Userspace I/O
615# 733#
616# CONFIG_INFINIBAND is not set 734# CONFIG_UIO is not set
617 735
618# 736#
619# Character devices 737# Character devices
@@ -624,10 +742,11 @@ CONFIG_LOGO_LINUX_CLUT224=y
624# 742#
625CONFIG_EXT2_FS=y 743CONFIG_EXT2_FS=y
626# CONFIG_EXT2_FS_XATTR is not set 744# CONFIG_EXT2_FS_XATTR is not set
745# CONFIG_EXT2_FS_XIP is not set
627CONFIG_EXT3_FS=y 746CONFIG_EXT3_FS=y
628# CONFIG_EXT3_FS_XATTR is not set 747# CONFIG_EXT3_FS_XATTR is not set
748# CONFIG_EXT4DEV_FS is not set
629CONFIG_JBD=y 749CONFIG_JBD=y
630# CONFIG_JBD_DEBUG is not set
631CONFIG_REISERFS_FS=m 750CONFIG_REISERFS_FS=m
632# CONFIG_REISERFS_CHECK is not set 751# CONFIG_REISERFS_CHECK is not set
633# CONFIG_REISERFS_PROC_INFO is not set 752# CONFIG_REISERFS_PROC_INFO is not set
@@ -638,25 +757,29 @@ CONFIG_JFS_FS=m
638# CONFIG_JFS_DEBUG is not set 757# CONFIG_JFS_DEBUG is not set
639# CONFIG_JFS_STATISTICS is not set 758# CONFIG_JFS_STATISTICS is not set
640CONFIG_FS_POSIX_ACL=y 759CONFIG_FS_POSIX_ACL=y
641
642#
643# XFS support
644#
645CONFIG_XFS_FS=m 760CONFIG_XFS_FS=m
646CONFIG_XFS_EXPORT=y
647# CONFIG_XFS_RT is not set
648# CONFIG_XFS_QUOTA is not set 761# CONFIG_XFS_QUOTA is not set
649# CONFIG_XFS_SECURITY is not set 762# CONFIG_XFS_SECURITY is not set
650# CONFIG_XFS_POSIX_ACL is not set 763# CONFIG_XFS_POSIX_ACL is not set
651CONFIG_MINIX_FS=y 764# CONFIG_XFS_RT is not set
652# CONFIG_ROMFS_FS is not set 765CONFIG_GFS2_FS=m
766CONFIG_GFS2_FS_LOCKING_NOLOCK=m
767CONFIG_GFS2_FS_LOCKING_DLM=m
768CONFIG_OCFS2_FS=m
769# CONFIG_OCFS2_DEBUG_MASKLOG is not set
770# CONFIG_OCFS2_DEBUG_FS is not set
771CONFIG_DNOTIFY=y
772CONFIG_INOTIFY=y
773CONFIG_INOTIFY_USER=y
653CONFIG_QUOTA=y 774CONFIG_QUOTA=y
775CONFIG_QUOTA_NETLINK_INTERFACE=y
776# CONFIG_PRINT_QUOTA_WARNING is not set
654# CONFIG_QFMT_V1 is not set 777# CONFIG_QFMT_V1 is not set
655# CONFIG_QFMT_V2 is not set 778# CONFIG_QFMT_V2 is not set
656CONFIG_QUOTACTL=y 779CONFIG_QUOTACTL=y
657CONFIG_DNOTIFY=y
658CONFIG_AUTOFS_FS=m 780CONFIG_AUTOFS_FS=m
659CONFIG_AUTOFS4_FS=m 781CONFIG_AUTOFS4_FS=m
782CONFIG_FUSE_FS=m
660 783
661# 784#
662# CD-ROM/DVD Filesystems 785# CD-ROM/DVD Filesystems
@@ -664,7 +787,6 @@ CONFIG_AUTOFS4_FS=m
664CONFIG_ISO9660_FS=y 787CONFIG_ISO9660_FS=y
665CONFIG_JOLIET=y 788CONFIG_JOLIET=y
666CONFIG_ZISOFS=y 789CONFIG_ZISOFS=y
667CONFIG_ZISOFS_FS=y
668CONFIG_UDF_FS=m 790CONFIG_UDF_FS=m
669CONFIG_UDF_NLS=y 791CONFIG_UDF_NLS=y
670 792
@@ -683,15 +805,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
683# 805#
684CONFIG_PROC_FS=y 806CONFIG_PROC_FS=y
685CONFIG_PROC_KCORE=y 807CONFIG_PROC_KCORE=y
808CONFIG_PROC_SYSCTL=y
686CONFIG_SYSFS=y 809CONFIG_SYSFS=y
687CONFIG_DEVFS_FS=y
688CONFIG_DEVFS_MOUNT=y
689# CONFIG_DEVFS_DEBUG is not set
690# CONFIG_DEVPTS_FS_XATTR is not set
691CONFIG_TMPFS=y 810CONFIG_TMPFS=y
692# CONFIG_TMPFS_XATTR is not set 811# CONFIG_TMPFS_POSIX_ACL is not set
693# CONFIG_HUGETLB_PAGE is not set 812# CONFIG_HUGETLB_PAGE is not set
694CONFIG_RAMFS=y 813CONFIG_CONFIGFS_FS=m
695 814
696# 815#
697# Miscellaneous filesystems 816# Miscellaneous filesystems
@@ -705,44 +824,40 @@ CONFIG_HFSPLUS_FS=m
705# CONFIG_EFS_FS is not set 824# CONFIG_EFS_FS is not set
706CONFIG_CRAMFS=m 825CONFIG_CRAMFS=m
707# CONFIG_VXFS_FS is not set 826# CONFIG_VXFS_FS is not set
827CONFIG_MINIX_FS=y
708CONFIG_HPFS_FS=m 828CONFIG_HPFS_FS=m
709# CONFIG_QNX4FS_FS is not set 829# CONFIG_QNX4FS_FS is not set
830# CONFIG_ROMFS_FS is not set
710CONFIG_SYSV_FS=m 831CONFIG_SYSV_FS=m
711CONFIG_UFS_FS=m 832CONFIG_UFS_FS=m
712CONFIG_UFS_FS_WRITE=y 833# CONFIG_UFS_FS_WRITE is not set
713 834# CONFIG_UFS_DEBUG is not set
714# 835CONFIG_NETWORK_FILESYSTEMS=y
715# Network File Systems
716#
717CONFIG_NFS_FS=y 836CONFIG_NFS_FS=y
718CONFIG_NFS_V3=y 837CONFIG_NFS_V3=y
838# CONFIG_NFS_V3_ACL is not set
719CONFIG_NFS_V4=y 839CONFIG_NFS_V4=y
720# CONFIG_NFS_DIRECTIO is not set 840# CONFIG_NFS_DIRECTIO is not set
721CONFIG_NFSD=m 841CONFIG_NFSD=m
722CONFIG_NFSD_V3=y 842CONFIG_NFSD_V3=y
723CONFIG_NFSD_V4=y 843# CONFIG_NFSD_V3_ACL is not set
844# CONFIG_NFSD_V4 is not set
724CONFIG_NFSD_TCP=y 845CONFIG_NFSD_TCP=y
725CONFIG_ROOT_NFS=y 846CONFIG_ROOT_NFS=y
726CONFIG_LOCKD=y 847CONFIG_LOCKD=y
727CONFIG_LOCKD_V4=y 848CONFIG_LOCKD_V4=y
728CONFIG_EXPORTFS=m 849CONFIG_EXPORTFS=m
850CONFIG_NFS_COMMON=y
729CONFIG_SUNRPC=y 851CONFIG_SUNRPC=y
730CONFIG_SUNRPC_GSS=y 852CONFIG_SUNRPC_GSS=y
853CONFIG_SUNRPC_BIND34=y
731CONFIG_RPCSEC_GSS_KRB5=y 854CONFIG_RPCSEC_GSS_KRB5=y
732# CONFIG_RPCSEC_GSS_SPKM3 is not set 855# CONFIG_RPCSEC_GSS_SPKM3 is not set
733CONFIG_SMB_FS=m 856CONFIG_SMB_FS=m
734CONFIG_SMB_NLS_DEFAULT=y 857CONFIG_SMB_NLS_DEFAULT=y
735CONFIG_SMB_NLS_REMOTE="cp437" 858CONFIG_SMB_NLS_REMOTE="cp437"
736# CONFIG_CIFS is not set 859# CONFIG_CIFS is not set
737CONFIG_NCP_FS=m 860# CONFIG_NCP_FS is not set
738# CONFIG_NCPFS_PACKET_SIGNING is not set
739# CONFIG_NCPFS_IOCTL_LOCKING is not set
740# CONFIG_NCPFS_STRONG is not set
741# CONFIG_NCPFS_NFS_NS is not set
742# CONFIG_NCPFS_OS2_NS is not set
743# CONFIG_NCPFS_SMALLDOS is not set
744CONFIG_NCPFS_NLS=y
745# CONFIG_NCPFS_EXTRAS is not set
746CONFIG_CODA_FS=m 861CONFIG_CODA_FS=m
747# CONFIG_CODA_FS_OLD_API is not set 862# CONFIG_CODA_FS_OLD_API is not set
748# CONFIG_AFS_FS is not set 863# CONFIG_AFS_FS is not set
@@ -753,10 +868,6 @@ CONFIG_CODA_FS=m
753# CONFIG_PARTITION_ADVANCED is not set 868# CONFIG_PARTITION_ADVANCED is not set
754CONFIG_MSDOS_PARTITION=y 869CONFIG_MSDOS_PARTITION=y
755CONFIG_SUN_PARTITION=y 870CONFIG_SUN_PARTITION=y
756
757#
758# Native Language Support
759#
760CONFIG_NLS=y 871CONFIG_NLS=y
761CONFIG_NLS_DEFAULT="iso8859-1" 872CONFIG_NLS_DEFAULT="iso8859-1"
762CONFIG_NLS_CODEPAGE_437=y 873CONFIG_NLS_CODEPAGE_437=y
@@ -797,35 +908,42 @@ CONFIG_NLS_ISO8859_15=m
797CONFIG_NLS_KOI8_R=m 908CONFIG_NLS_KOI8_R=m
798CONFIG_NLS_KOI8_U=m 909CONFIG_NLS_KOI8_U=m
799CONFIG_NLS_UTF8=m 910CONFIG_NLS_UTF8=m
911CONFIG_DLM=m
912# CONFIG_DLM_DEBUG is not set
800 913
801# 914#
802# Kernel hacking 915# Kernel hacking
803# 916#
804# CONFIG_PRINTK_TIME is not set 917# CONFIG_PRINTK_TIME is not set
805CONFIG_DEBUG_KERNEL=y 918CONFIG_ENABLE_WARN_DEPRECATED=y
919CONFIG_ENABLE_MUST_CHECK=y
806CONFIG_MAGIC_SYSRQ=y 920CONFIG_MAGIC_SYSRQ=y
807CONFIG_LOG_BUF_SHIFT=16 921# CONFIG_UNUSED_SYMBOLS is not set
808# CONFIG_SCHEDSTATS is not set
809# CONFIG_DEBUG_SLAB is not set
810# CONFIG_DEBUG_SPINLOCK is not set
811# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
812# CONFIG_DEBUG_KOBJECT is not set
813CONFIG_DEBUG_BUGVERBOSE=y
814# CONFIG_DEBUG_INFO is not set
815# CONFIG_DEBUG_FS is not set 922# CONFIG_DEBUG_FS is not set
816# CONFIG_FRAME_POINTER is not set 923# CONFIG_HEADERS_CHECK is not set
924# CONFIG_DEBUG_KERNEL is not set
925CONFIG_DEBUG_BUGVERBOSE=y
926# CONFIG_SAMPLES is not set
817 927
818# 928#
819# Security options 929# Security options
820# 930#
821# CONFIG_KEYS is not set 931# CONFIG_KEYS is not set
822# CONFIG_SECURITY is not set 932# CONFIG_SECURITY is not set
823 933# CONFIG_SECURITY_FILE_CAPABILITIES is not set
824# 934CONFIG_XOR_BLOCKS=m
825# Cryptographic options 935CONFIG_ASYNC_CORE=m
826# 936CONFIG_ASYNC_MEMCPY=m
937CONFIG_ASYNC_XOR=m
827CONFIG_CRYPTO=y 938CONFIG_CRYPTO=y
939CONFIG_CRYPTO_ALGAPI=y
940CONFIG_CRYPTO_AEAD=m
941CONFIG_CRYPTO_BLKCIPHER=y
942CONFIG_CRYPTO_SEQIV=m
943CONFIG_CRYPTO_HASH=y
944CONFIG_CRYPTO_MANAGER=y
828CONFIG_CRYPTO_HMAC=y 945CONFIG_CRYPTO_HMAC=y
946CONFIG_CRYPTO_XCBC=m
829CONFIG_CRYPTO_NULL=m 947CONFIG_CRYPTO_NULL=m
830CONFIG_CRYPTO_MD4=m 948CONFIG_CRYPTO_MD4=m
831CONFIG_CRYPTO_MD5=y 949CONFIG_CRYPTO_MD5=y
@@ -834,9 +952,21 @@ CONFIG_CRYPTO_SHA256=m
834CONFIG_CRYPTO_SHA512=m 952CONFIG_CRYPTO_SHA512=m
835CONFIG_CRYPTO_WP512=m 953CONFIG_CRYPTO_WP512=m
836CONFIG_CRYPTO_TGR192=m 954CONFIG_CRYPTO_TGR192=m
955CONFIG_CRYPTO_GF128MUL=m
956CONFIG_CRYPTO_ECB=m
957CONFIG_CRYPTO_CBC=y
958CONFIG_CRYPTO_PCBC=m
959CONFIG_CRYPTO_LRW=m
960CONFIG_CRYPTO_XTS=m
961CONFIG_CRYPTO_CTR=m
962CONFIG_CRYPTO_GCM=m
963CONFIG_CRYPTO_CCM=m
964CONFIG_CRYPTO_CRYPTD=m
837CONFIG_CRYPTO_DES=y 965CONFIG_CRYPTO_DES=y
966CONFIG_CRYPTO_FCRYPT=m
838CONFIG_CRYPTO_BLOWFISH=m 967CONFIG_CRYPTO_BLOWFISH=m
839CONFIG_CRYPTO_TWOFISH=m 968CONFIG_CRYPTO_TWOFISH=m
969CONFIG_CRYPTO_TWOFISH_COMMON=m
840CONFIG_CRYPTO_SERPENT=m 970CONFIG_CRYPTO_SERPENT=m
841CONFIG_CRYPTO_AES=m 971CONFIG_CRYPTO_AES=m
842CONFIG_CRYPTO_CAST5=m 972CONFIG_CRYPTO_CAST5=m
@@ -845,20 +975,34 @@ CONFIG_CRYPTO_TEA=m
845CONFIG_CRYPTO_ARC4=m 975CONFIG_CRYPTO_ARC4=m
846CONFIG_CRYPTO_KHAZAD=m 976CONFIG_CRYPTO_KHAZAD=m
847CONFIG_CRYPTO_ANUBIS=m 977CONFIG_CRYPTO_ANUBIS=m
978CONFIG_CRYPTO_SEED=m
979CONFIG_CRYPTO_SALSA20=m
848CONFIG_CRYPTO_DEFLATE=m 980CONFIG_CRYPTO_DEFLATE=m
849CONFIG_CRYPTO_MICHAEL_MIC=m 981CONFIG_CRYPTO_MICHAEL_MIC=m
850CONFIG_CRYPTO_CRC32C=m 982CONFIG_CRYPTO_CRC32C=m
983CONFIG_CRYPTO_CAMELLIA=m
851CONFIG_CRYPTO_TEST=m 984CONFIG_CRYPTO_TEST=m
852 985CONFIG_CRYPTO_AUTHENC=m
853# 986CONFIG_CRYPTO_LZO=m
854# Hardware crypto devices 987# CONFIG_CRYPTO_HW is not set
855#
856 988
857# 989#
858# Library routines 990# Library routines
859# 991#
992CONFIG_BITREVERSE=y
860CONFIG_CRC_CCITT=m 993CONFIG_CRC_CCITT=m
994CONFIG_CRC16=m
995# CONFIG_CRC_ITU_T is not set
861CONFIG_CRC32=y 996CONFIG_CRC32=y
997# CONFIG_CRC7 is not set
862CONFIG_LIBCRC32C=m 998CONFIG_LIBCRC32C=m
863CONFIG_ZLIB_INFLATE=y 999CONFIG_ZLIB_INFLATE=y
864CONFIG_ZLIB_DEFLATE=m 1000CONFIG_ZLIB_DEFLATE=m
1001CONFIG_LZO_COMPRESS=m
1002CONFIG_LZO_DECOMPRESS=m
1003CONFIG_TEXTSEARCH=y
1004CONFIG_TEXTSEARCH_KMP=m
1005CONFIG_TEXTSEARCH_BM=m
1006CONFIG_TEXTSEARCH_FSM=m
1007CONFIG_PLIST=y
1008CONFIG_HAS_IOMEM=y
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index 997143b7928..f18154f1ef1 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -1,63 +1,111 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k 3# Linux kernel version: 2.6.25-rc8
4# Tue Jun 7 20:35:06 2005 4# Wed Apr 2 20:46:23 2008
5# 5#
6CONFIG_M68K=y 6CONFIG_M68K=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9# CONFIG_ARCH_HAS_ILOG2_U32 is not set
10# CONFIG_ARCH_HAS_ILOG2_U64 is not set
11CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_TIME_LOW_RES=y
14CONFIG_GENERIC_IOMAP=y
15CONFIG_NO_IOPORT=y
16# CONFIG_NO_DMA is not set
17CONFIG_ARCH_SUPPORTS_AOUT=y
18CONFIG_HZ=100
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
11 20
12# 21#
13# Code maturity level options 22# General setup
14# 23#
15CONFIG_EXPERIMENTAL=y 24CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y 25CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32 26CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION="-sun3x" 27CONFIG_LOCALVERSION="-sun3x"
28CONFIG_LOCALVERSION_AUTO=y
24CONFIG_SWAP=y 29CONFIG_SWAP=y
25CONFIG_SYSVIPC=y 30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
26CONFIG_POSIX_MQUEUE=y 32CONFIG_POSIX_MQUEUE=y
27CONFIG_BSD_PROCESS_ACCT=y 33CONFIG_BSD_PROCESS_ACCT=y
28# CONFIG_BSD_PROCESS_ACCT_V3 is not set 34# CONFIG_BSD_PROCESS_ACCT_V3 is not set
29CONFIG_SYSCTL=y 35# CONFIG_TASKSTATS is not set
30CONFIG_AUDIT=y 36# CONFIG_AUDIT is not set
31CONFIG_HOTPLUG=y
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set 37# CONFIG_IKCONFIG is not set
38CONFIG_LOG_BUF_SHIFT=14
39# CONFIG_CGROUPS is not set
40# CONFIG_GROUP_SCHED is not set
41# CONFIG_SYSFS_DEPRECATED_V2 is not set
42CONFIG_RELAY=y
43CONFIG_NAMESPACES=y
44# CONFIG_UTS_NS is not set
45# CONFIG_IPC_NS is not set
46# CONFIG_USER_NS is not set
47# CONFIG_PID_NS is not set
48CONFIG_BLK_DEV_INITRD=y
49CONFIG_INITRAMFS_SOURCE=""
50# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
51CONFIG_SYSCTL=y
34# CONFIG_EMBEDDED is not set 52# CONFIG_EMBEDDED is not set
53CONFIG_UID16=y
54CONFIG_SYSCTL_SYSCALL=y
35CONFIG_KALLSYMS=y 55CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set 56# CONFIG_KALLSYMS_EXTRA_PASS is not set
57CONFIG_HOTPLUG=y
38CONFIG_PRINTK=y 58CONFIG_PRINTK=y
39CONFIG_BUG=y 59CONFIG_BUG=y
60CONFIG_ELF_CORE=y
61# CONFIG_COMPAT_BRK is not set
40CONFIG_BASE_FULL=y 62CONFIG_BASE_FULL=y
41CONFIG_FUTEX=y 63CONFIG_FUTEX=y
64CONFIG_ANON_INODES=y
42CONFIG_EPOLL=y 65CONFIG_EPOLL=y
66CONFIG_SIGNALFD=y
67CONFIG_TIMERFD=y
68CONFIG_EVENTFD=y
43CONFIG_SHMEM=y 69CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 70CONFIG_VM_EVENT_COUNTERS=y
45CONFIG_CC_ALIGN_LABELS=0 71CONFIG_SLAB=y
46CONFIG_CC_ALIGN_LOOPS=0 72# CONFIG_SLUB is not set
47CONFIG_CC_ALIGN_JUMPS=0 73# CONFIG_SLOB is not set
74# CONFIG_PROFILING is not set
75# CONFIG_MARKERS is not set
76# CONFIG_HAVE_OPROFILE is not set
77# CONFIG_HAVE_KPROBES is not set
78# CONFIG_HAVE_KRETPROBES is not set
79CONFIG_PROC_PAGE_MONITOR=y
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
48# CONFIG_TINY_SHMEM is not set 82# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 83CONFIG_BASE_SMALL=0
50
51#
52# Loadable module support
53#
54CONFIG_MODULES=y 84CONFIG_MODULES=y
55CONFIG_MODULE_UNLOAD=y 85CONFIG_MODULE_UNLOAD=y
56# CONFIG_MODULE_FORCE_UNLOAD is not set 86# CONFIG_MODULE_FORCE_UNLOAD is not set
57CONFIG_OBSOLETE_MODPARM=y
58# CONFIG_MODVERSIONS is not set 87# CONFIG_MODVERSIONS is not set
59# CONFIG_MODULE_SRCVERSION_ALL is not set 88# CONFIG_MODULE_SRCVERSION_ALL is not set
60CONFIG_KMOD=y 89CONFIG_KMOD=y
90CONFIG_BLOCK=y
91# CONFIG_LBD is not set
92# CONFIG_BLK_DEV_IO_TRACE is not set
93# CONFIG_LSF is not set
94CONFIG_BLK_DEV_BSG=y
95
96#
97# IO Schedulers
98#
99CONFIG_IOSCHED_NOOP=y
100CONFIG_IOSCHED_AS=y
101CONFIG_IOSCHED_DEADLINE=y
102CONFIG_IOSCHED_CFQ=y
103CONFIG_DEFAULT_AS=y
104# CONFIG_DEFAULT_DEADLINE is not set
105# CONFIG_DEFAULT_CFQ is not set
106# CONFIG_DEFAULT_NOOP is not set
107CONFIG_DEFAULT_IOSCHED="anticipatory"
108CONFIG_CLASSIC_RCU=y
61 109
62# 110#
63# Platform dependent setup 111# Platform dependent setup
@@ -80,10 +128,24 @@ CONFIG_M68030=y
80# CONFIG_M68040 is not set 128# CONFIG_M68040 is not set
81# CONFIG_M68060 is not set 129# CONFIG_M68060 is not set
82CONFIG_MMU_MOTOROLA=y 130CONFIG_MMU_MOTOROLA=y
83CONFIG_M68KFPU_EMU=y 131# CONFIG_M68KFPU_EMU is not set
84CONFIG_M68KFPU_EMU_EXTRAPREC=y
85# CONFIG_M68KFPU_EMU_ONLY is not set
86# CONFIG_ADVANCED is not set 132# CONFIG_ADVANCED is not set
133CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
134CONFIG_NODES_SHIFT=3
135CONFIG_SELECT_MEMORY_MODEL=y
136# CONFIG_FLATMEM_MANUAL is not set
137CONFIG_DISCONTIGMEM_MANUAL=y
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_DISCONTIGMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141CONFIG_NEED_MULTIPLE_NODES=y
142# CONFIG_SPARSEMEM_STATIC is not set
143# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
144CONFIG_SPLIT_PTLOCK_CPUS=4
145# CONFIG_RESOURCES_64BIT is not set
146CONFIG_ZONE_DMA_FLAG=1
147CONFIG_BOUNCE=y
148CONFIG_VIRT_TO_BUS=y
87 149
88# 150#
89# General setup 151# General setup
@@ -92,135 +154,11 @@ CONFIG_BINFMT_ELF=y
92CONFIG_BINFMT_AOUT=m 154CONFIG_BINFMT_AOUT=m
93CONFIG_BINFMT_MISC=m 155CONFIG_BINFMT_MISC=m
94CONFIG_PROC_HARDWARE=y 156CONFIG_PROC_HARDWARE=y
157CONFIG_ZONE_DMA=y
158# CONFIG_ARCH_SUPPORTS_MSI is not set
95 159
96# 160#
97# Device Drivers 161# Networking
98#
99
100#
101# Generic Driver Options
102#
103CONFIG_STANDALONE=y
104CONFIG_PREVENT_FIRMWARE_BUILD=y
105CONFIG_FW_LOADER=m
106# CONFIG_DEBUG_DRIVER is not set
107
108#
109# Memory Technology Devices (MTD)
110#
111# CONFIG_MTD is not set
112
113#
114# Parallel port support
115#
116# CONFIG_PARPORT is not set
117
118#
119# Plug and Play support
120#
121
122#
123# Block devices
124#
125# CONFIG_BLK_DEV_COW_COMMON is not set
126CONFIG_BLK_DEV_LOOP=y
127CONFIG_BLK_DEV_CRYPTOLOOP=m
128CONFIG_BLK_DEV_NBD=m
129CONFIG_BLK_DEV_RAM=y
130CONFIG_BLK_DEV_RAM_COUNT=16
131CONFIG_BLK_DEV_RAM_SIZE=4096
132CONFIG_BLK_DEV_INITRD=y
133CONFIG_INITRAMFS_SOURCE=""
134CONFIG_CDROM_PKTCDVD=m
135CONFIG_CDROM_PKTCDVD_BUFFERS=8
136# CONFIG_CDROM_PKTCDVD_WCACHE is not set
137
138#
139# IO Schedulers
140#
141CONFIG_IOSCHED_NOOP=y
142CONFIG_IOSCHED_AS=y
143CONFIG_IOSCHED_DEADLINE=y
144CONFIG_IOSCHED_CFQ=y
145CONFIG_ATA_OVER_ETH=m
146
147#
148# ATA/ATAPI/MFM/RLL support
149#
150# CONFIG_IDE is not set
151
152#
153# SCSI device support
154#
155CONFIG_SCSI=y
156CONFIG_SCSI_PROC_FS=y
157
158#
159# SCSI support type (disk, tape, CD-ROM)
160#
161CONFIG_BLK_DEV_SD=y
162CONFIG_CHR_DEV_ST=m
163# CONFIG_CHR_DEV_OSST is not set
164CONFIG_BLK_DEV_SR=y
165CONFIG_BLK_DEV_SR_VENDOR=y
166CONFIG_CHR_DEV_SG=m
167
168#
169# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
170#
171# CONFIG_SCSI_MULTI_LUN is not set
172CONFIG_SCSI_CONSTANTS=y
173# CONFIG_SCSI_LOGGING is not set
174
175#
176# SCSI Transport Attributes
177#
178# CONFIG_SCSI_SPI_ATTRS is not set
179# CONFIG_SCSI_FC_ATTRS is not set
180# CONFIG_SCSI_ISCSI_ATTRS is not set
181
182#
183# SCSI low-level drivers
184#
185# CONFIG_SCSI_SATA is not set
186# CONFIG_SCSI_DEBUG is not set
187CONFIG_SUN3X_ESP=y
188
189#
190# Multi-device support (RAID and LVM)
191#
192CONFIG_MD=y
193CONFIG_BLK_DEV_MD=m
194CONFIG_MD_LINEAR=m
195CONFIG_MD_RAID0=m
196CONFIG_MD_RAID1=m
197# CONFIG_MD_RAID10 is not set
198CONFIG_MD_RAID5=m
199CONFIG_MD_RAID6=m
200CONFIG_MD_MULTIPATH=m
201# CONFIG_MD_FAULTY is not set
202CONFIG_BLK_DEV_DM=m
203CONFIG_DM_CRYPT=m
204CONFIG_DM_SNAPSHOT=m
205CONFIG_DM_MIRROR=m
206CONFIG_DM_ZERO=m
207CONFIG_DM_MULTIPATH=m
208CONFIG_DM_MULTIPATH_EMC=m
209
210#
211# Fusion MPT device support
212#
213
214#
215# IEEE 1394 (FireWire) support
216#
217
218#
219# I2O device support
220#
221
222#
223# Networking support
224# 162#
225CONFIG_NET=y 163CONFIG_NET=y
226 164
@@ -230,10 +168,17 @@ CONFIG_NET=y
230CONFIG_PACKET=y 168CONFIG_PACKET=y
231# CONFIG_PACKET_MMAP is not set 169# CONFIG_PACKET_MMAP is not set
232CONFIG_UNIX=y 170CONFIG_UNIX=y
171CONFIG_XFRM=y
172# CONFIG_XFRM_USER is not set
173# CONFIG_XFRM_SUB_POLICY is not set
174CONFIG_XFRM_MIGRATE=y
175# CONFIG_XFRM_STATISTICS is not set
233CONFIG_NET_KEY=y 176CONFIG_NET_KEY=y
177CONFIG_NET_KEY_MIGRATE=y
234CONFIG_INET=y 178CONFIG_INET=y
235# CONFIG_IP_MULTICAST is not set 179# CONFIG_IP_MULTICAST is not set
236# CONFIG_IP_ADVANCED_ROUTER is not set 180# CONFIG_IP_ADVANCED_ROUTER is not set
181CONFIG_IP_FIB_HASH=y
237CONFIG_IP_PNP=y 182CONFIG_IP_PNP=y
238CONFIG_IP_PNP_DHCP=y 183CONFIG_IP_PNP_DHCP=y
239CONFIG_IP_PNP_BOOTP=y 184CONFIG_IP_PNP_BOOTP=y
@@ -245,145 +190,199 @@ CONFIG_SYN_COOKIES=y
245CONFIG_INET_AH=m 190CONFIG_INET_AH=m
246CONFIG_INET_ESP=m 191CONFIG_INET_ESP=m
247CONFIG_INET_IPCOMP=m 192CONFIG_INET_IPCOMP=m
193CONFIG_INET_XFRM_TUNNEL=m
248CONFIG_INET_TUNNEL=m 194CONFIG_INET_TUNNEL=m
249CONFIG_IP_TCPDIAG=m 195CONFIG_INET_XFRM_MODE_TRANSPORT=m
250CONFIG_IP_TCPDIAG_IPV6=y 196CONFIG_INET_XFRM_MODE_TUNNEL=m
251 197CONFIG_INET_XFRM_MODE_BEET=m
252# 198CONFIG_INET_LRO=m
253# IP: Virtual Server Configuration 199CONFIG_INET_DIAG=m
254# 200CONFIG_INET_TCP_DIAG=m
201# CONFIG_TCP_CONG_ADVANCED is not set
202CONFIG_TCP_CONG_CUBIC=y
203CONFIG_DEFAULT_TCP_CONG="cubic"
204# CONFIG_TCP_MD5SIG is not set
255# CONFIG_IP_VS is not set 205# CONFIG_IP_VS is not set
256CONFIG_IPV6=m 206CONFIG_IPV6=m
257CONFIG_IPV6_PRIVACY=y 207CONFIG_IPV6_PRIVACY=y
208CONFIG_IPV6_ROUTER_PREF=y
209CONFIG_IPV6_ROUTE_INFO=y
210# CONFIG_IPV6_OPTIMISTIC_DAD is not set
258CONFIG_INET6_AH=m 211CONFIG_INET6_AH=m
259CONFIG_INET6_ESP=m 212CONFIG_INET6_ESP=m
260CONFIG_INET6_IPCOMP=m 213CONFIG_INET6_IPCOMP=m
214# CONFIG_IPV6_MIP6 is not set
215CONFIG_INET6_XFRM_TUNNEL=m
261CONFIG_INET6_TUNNEL=m 216CONFIG_INET6_TUNNEL=m
217CONFIG_INET6_XFRM_MODE_TRANSPORT=m
218CONFIG_INET6_XFRM_MODE_TUNNEL=m
219CONFIG_INET6_XFRM_MODE_BEET=m
220CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
221CONFIG_IPV6_SIT=m
262CONFIG_IPV6_TUNNEL=m 222CONFIG_IPV6_TUNNEL=m
223# CONFIG_IPV6_MULTIPLE_TABLES is not set
224# CONFIG_NETWORK_SECMARK is not set
263CONFIG_NETFILTER=y 225CONFIG_NETFILTER=y
264# CONFIG_NETFILTER_DEBUG is not set 226# CONFIG_NETFILTER_DEBUG is not set
227CONFIG_NETFILTER_ADVANCED=y
228
229#
230# Core Netfilter Configuration
231#
232CONFIG_NETFILTER_NETLINK=m
233CONFIG_NETFILTER_NETLINK_QUEUE=m
234CONFIG_NETFILTER_NETLINK_LOG=m
235CONFIG_NF_CONNTRACK=m
236CONFIG_NF_CT_ACCT=y
237CONFIG_NF_CONNTRACK_MARK=y
238# CONFIG_NF_CONNTRACK_EVENTS is not set
239CONFIG_NF_CT_PROTO_GRE=m
240CONFIG_NF_CT_PROTO_SCTP=m
241CONFIG_NF_CT_PROTO_UDPLITE=m
242CONFIG_NF_CONNTRACK_AMANDA=m
243CONFIG_NF_CONNTRACK_FTP=m
244CONFIG_NF_CONNTRACK_H323=m
245CONFIG_NF_CONNTRACK_IRC=m
246CONFIG_NF_CONNTRACK_NETBIOS_NS=m
247CONFIG_NF_CONNTRACK_PPTP=m
248CONFIG_NF_CONNTRACK_SANE=m
249CONFIG_NF_CONNTRACK_SIP=m
250CONFIG_NF_CONNTRACK_TFTP=m
251# CONFIG_NF_CT_NETLINK is not set
252CONFIG_NETFILTER_XTABLES=m
253CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
254CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
255CONFIG_NETFILTER_XT_TARGET_DSCP=m
256CONFIG_NETFILTER_XT_TARGET_MARK=m
257CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
258CONFIG_NETFILTER_XT_TARGET_NFLOG=m
259CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
260CONFIG_NETFILTER_XT_TARGET_RATEEST=m
261CONFIG_NETFILTER_XT_TARGET_TRACE=m
262CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
263CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
264CONFIG_NETFILTER_XT_MATCH_COMMENT=m
265CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
266CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
267CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
268CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
269CONFIG_NETFILTER_XT_MATCH_DCCP=m
270CONFIG_NETFILTER_XT_MATCH_DSCP=m
271CONFIG_NETFILTER_XT_MATCH_ESP=m
272CONFIG_NETFILTER_XT_MATCH_HELPER=m
273CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
274CONFIG_NETFILTER_XT_MATCH_LENGTH=m
275CONFIG_NETFILTER_XT_MATCH_LIMIT=m
276CONFIG_NETFILTER_XT_MATCH_MAC=m
277CONFIG_NETFILTER_XT_MATCH_MARK=m
278CONFIG_NETFILTER_XT_MATCH_OWNER=m
279CONFIG_NETFILTER_XT_MATCH_POLICY=m
280CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
281CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
282CONFIG_NETFILTER_XT_MATCH_QUOTA=m
283CONFIG_NETFILTER_XT_MATCH_RATEEST=m
284CONFIG_NETFILTER_XT_MATCH_REALM=m
285CONFIG_NETFILTER_XT_MATCH_SCTP=m
286CONFIG_NETFILTER_XT_MATCH_STATE=m
287CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
288CONFIG_NETFILTER_XT_MATCH_STRING=m
289CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
290CONFIG_NETFILTER_XT_MATCH_TIME=m
291CONFIG_NETFILTER_XT_MATCH_U32=m
292CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
265 293
266# 294#
267# IP: Netfilter Configuration 295# IP: Netfilter Configuration
268# 296#
269CONFIG_IP_NF_CONNTRACK=m 297CONFIG_NF_CONNTRACK_IPV4=m
270# CONFIG_IP_NF_CT_ACCT is not set 298CONFIG_NF_CONNTRACK_PROC_COMPAT=y
271CONFIG_IP_NF_CONNTRACK_MARK=y
272# CONFIG_IP_NF_CT_PROTO_SCTP is not set
273CONFIG_IP_NF_FTP=m
274CONFIG_IP_NF_IRC=m
275CONFIG_IP_NF_TFTP=m
276CONFIG_IP_NF_AMANDA=m
277CONFIG_IP_NF_QUEUE=m 299CONFIG_IP_NF_QUEUE=m
278CONFIG_IP_NF_IPTABLES=m 300CONFIG_IP_NF_IPTABLES=m
279CONFIG_IP_NF_MATCH_LIMIT=m
280CONFIG_IP_NF_MATCH_IPRANGE=m
281CONFIG_IP_NF_MATCH_MAC=m
282CONFIG_IP_NF_MATCH_PKTTYPE=m
283CONFIG_IP_NF_MATCH_MARK=m
284CONFIG_IP_NF_MATCH_MULTIPORT=m
285CONFIG_IP_NF_MATCH_TOS=m
286CONFIG_IP_NF_MATCH_RECENT=m 301CONFIG_IP_NF_MATCH_RECENT=m
287CONFIG_IP_NF_MATCH_ECN=m 302CONFIG_IP_NF_MATCH_ECN=m
288CONFIG_IP_NF_MATCH_DSCP=m 303CONFIG_IP_NF_MATCH_AH=m
289CONFIG_IP_NF_MATCH_AH_ESP=m
290CONFIG_IP_NF_MATCH_LENGTH=m
291CONFIG_IP_NF_MATCH_TTL=m 304CONFIG_IP_NF_MATCH_TTL=m
292CONFIG_IP_NF_MATCH_TCPMSS=m
293CONFIG_IP_NF_MATCH_HELPER=m
294CONFIG_IP_NF_MATCH_STATE=m
295CONFIG_IP_NF_MATCH_CONNTRACK=m
296CONFIG_IP_NF_MATCH_OWNER=m
297CONFIG_IP_NF_MATCH_ADDRTYPE=m 305CONFIG_IP_NF_MATCH_ADDRTYPE=m
298CONFIG_IP_NF_MATCH_REALM=m
299# CONFIG_IP_NF_MATCH_SCTP is not set
300# CONFIG_IP_NF_MATCH_COMMENT is not set
301CONFIG_IP_NF_MATCH_CONNMARK=m
302CONFIG_IP_NF_MATCH_HASHLIMIT=m
303CONFIG_IP_NF_FILTER=m 306CONFIG_IP_NF_FILTER=m
304CONFIG_IP_NF_TARGET_REJECT=m 307CONFIG_IP_NF_TARGET_REJECT=m
305CONFIG_IP_NF_TARGET_LOG=m 308CONFIG_IP_NF_TARGET_LOG=m
306CONFIG_IP_NF_TARGET_ULOG=m 309CONFIG_IP_NF_TARGET_ULOG=m
307CONFIG_IP_NF_TARGET_TCPMSS=m 310CONFIG_NF_NAT=m
308CONFIG_IP_NF_NAT=m 311CONFIG_NF_NAT_NEEDED=y
309CONFIG_IP_NF_NAT_NEEDED=y
310CONFIG_IP_NF_TARGET_MASQUERADE=m 312CONFIG_IP_NF_TARGET_MASQUERADE=m
311CONFIG_IP_NF_TARGET_REDIRECT=m 313CONFIG_IP_NF_TARGET_REDIRECT=m
312CONFIG_IP_NF_TARGET_NETMAP=m 314CONFIG_IP_NF_TARGET_NETMAP=m
313CONFIG_IP_NF_TARGET_SAME=m 315CONFIG_NF_NAT_SNMP_BASIC=m
314CONFIG_IP_NF_NAT_SNMP_BASIC=m 316CONFIG_NF_NAT_PROTO_GRE=m
315CONFIG_IP_NF_NAT_IRC=m 317CONFIG_NF_NAT_FTP=m
316CONFIG_IP_NF_NAT_FTP=m 318CONFIG_NF_NAT_IRC=m
317CONFIG_IP_NF_NAT_TFTP=m 319CONFIG_NF_NAT_TFTP=m
318CONFIG_IP_NF_NAT_AMANDA=m 320CONFIG_NF_NAT_AMANDA=m
321CONFIG_NF_NAT_PPTP=m
322CONFIG_NF_NAT_H323=m
323CONFIG_NF_NAT_SIP=m
319CONFIG_IP_NF_MANGLE=m 324CONFIG_IP_NF_MANGLE=m
320CONFIG_IP_NF_TARGET_TOS=m
321CONFIG_IP_NF_TARGET_ECN=m 325CONFIG_IP_NF_TARGET_ECN=m
322CONFIG_IP_NF_TARGET_DSCP=m 326CONFIG_IP_NF_TARGET_TTL=m
323CONFIG_IP_NF_TARGET_MARK=m 327CONFIG_IP_NF_TARGET_CLUSTERIP=m
324CONFIG_IP_NF_TARGET_CLASSIFY=m
325CONFIG_IP_NF_TARGET_CONNMARK=m
326# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
327CONFIG_IP_NF_RAW=m 328CONFIG_IP_NF_RAW=m
328CONFIG_IP_NF_TARGET_NOTRACK=m
329CONFIG_IP_NF_ARPTABLES=m 329CONFIG_IP_NF_ARPTABLES=m
330CONFIG_IP_NF_ARPFILTER=m 330CONFIG_IP_NF_ARPFILTER=m
331CONFIG_IP_NF_ARP_MANGLE=m 331CONFIG_IP_NF_ARP_MANGLE=m
332 332
333# 333#
334# IPv6: Netfilter Configuration (EXPERIMENTAL) 334# IPv6: Netfilter Configuration
335# 335#
336CONFIG_NF_CONNTRACK_IPV6=m
336CONFIG_IP6_NF_QUEUE=m 337CONFIG_IP6_NF_QUEUE=m
337CONFIG_IP6_NF_IPTABLES=m 338CONFIG_IP6_NF_IPTABLES=m
338CONFIG_IP6_NF_MATCH_LIMIT=m
339CONFIG_IP6_NF_MATCH_MAC=m
340CONFIG_IP6_NF_MATCH_RT=m 339CONFIG_IP6_NF_MATCH_RT=m
341CONFIG_IP6_NF_MATCH_OPTS=m 340CONFIG_IP6_NF_MATCH_OPTS=m
342CONFIG_IP6_NF_MATCH_FRAG=m 341CONFIG_IP6_NF_MATCH_FRAG=m
343CONFIG_IP6_NF_MATCH_HL=m 342CONFIG_IP6_NF_MATCH_HL=m
344CONFIG_IP6_NF_MATCH_MULTIPORT=m
345CONFIG_IP6_NF_MATCH_OWNER=m
346CONFIG_IP6_NF_MATCH_MARK=m
347CONFIG_IP6_NF_MATCH_IPV6HEADER=m 343CONFIG_IP6_NF_MATCH_IPV6HEADER=m
348CONFIG_IP6_NF_MATCH_AHESP=m 344CONFIG_IP6_NF_MATCH_AH=m
349CONFIG_IP6_NF_MATCH_LENGTH=m 345CONFIG_IP6_NF_MATCH_MH=m
350CONFIG_IP6_NF_MATCH_EUI64=m 346CONFIG_IP6_NF_MATCH_EUI64=m
351CONFIG_IP6_NF_FILTER=m 347CONFIG_IP6_NF_FILTER=m
352CONFIG_IP6_NF_TARGET_LOG=m 348CONFIG_IP6_NF_TARGET_LOG=m
349CONFIG_IP6_NF_TARGET_REJECT=m
353CONFIG_IP6_NF_MANGLE=m 350CONFIG_IP6_NF_MANGLE=m
354CONFIG_IP6_NF_TARGET_MARK=m 351CONFIG_IP6_NF_TARGET_HL=m
355CONFIG_IP6_NF_RAW=m 352CONFIG_IP6_NF_RAW=m
356CONFIG_XFRM=y 353CONFIG_IP_DCCP=m
357# CONFIG_XFRM_USER is not set 354CONFIG_INET_DCCP_DIAG=m
355CONFIG_IP_DCCP_ACKVEC=y
358 356
359# 357#
360# SCTP Configuration (EXPERIMENTAL) 358# DCCP CCIDs Configuration (EXPERIMENTAL)
361# 359#
360CONFIG_IP_DCCP_CCID2=m
361# CONFIG_IP_DCCP_CCID2_DEBUG is not set
362CONFIG_IP_DCCP_CCID3=m
363# CONFIG_IP_DCCP_CCID3_DEBUG is not set
364CONFIG_IP_DCCP_CCID3_RTO=100
365CONFIG_IP_DCCP_TFRC_LIB=m
362CONFIG_IP_SCTP=m 366CONFIG_IP_SCTP=m
363# CONFIG_SCTP_DBG_MSG is not set 367# CONFIG_SCTP_DBG_MSG is not set
364# CONFIG_SCTP_DBG_OBJCNT is not set 368# CONFIG_SCTP_DBG_OBJCNT is not set
365# CONFIG_SCTP_HMAC_NONE is not set 369# CONFIG_SCTP_HMAC_NONE is not set
366# CONFIG_SCTP_HMAC_SHA1 is not set 370# CONFIG_SCTP_HMAC_SHA1 is not set
367CONFIG_SCTP_HMAC_MD5=y 371CONFIG_SCTP_HMAC_MD5=y
372# CONFIG_TIPC is not set
368# CONFIG_ATM is not set 373# CONFIG_ATM is not set
369# CONFIG_BRIDGE is not set 374# CONFIG_BRIDGE is not set
370# CONFIG_VLAN_8021Q is not set 375# CONFIG_VLAN_8021Q is not set
371# CONFIG_DECNET is not set 376# CONFIG_DECNET is not set
372CONFIG_LLC=m 377CONFIG_LLC=m
373# CONFIG_LLC2 is not set 378# CONFIG_LLC2 is not set
374CONFIG_IPX=m 379# CONFIG_IPX is not set
375# CONFIG_IPX_INTERN is not set
376CONFIG_ATALK=m 380CONFIG_ATALK=m
377# CONFIG_DEV_APPLETALK is not set 381# CONFIG_DEV_APPLETALK is not set
378# CONFIG_X25 is not set 382# CONFIG_X25 is not set
379# CONFIG_LAPB is not set 383# CONFIG_LAPB is not set
380# CONFIG_NET_DIVERT is not set
381# CONFIG_ECONET is not set 384# CONFIG_ECONET is not set
382# CONFIG_WAN_ROUTER is not set 385# CONFIG_WAN_ROUTER is not set
383
384#
385# QoS and/or fair queueing
386#
387# CONFIG_NET_SCHED is not set 386# CONFIG_NET_SCHED is not set
388CONFIG_NET_CLS_ROUTE=y 387CONFIG_NET_CLS_ROUTE=y
389 388
@@ -391,46 +390,155 @@ CONFIG_NET_CLS_ROUTE=y
391# Network testing 390# Network testing
392# 391#
393# CONFIG_NET_PKTGEN is not set 392# CONFIG_NET_PKTGEN is not set
394CONFIG_NETPOLL=y
395# CONFIG_NETPOLL_RX is not set
396# CONFIG_NETPOLL_TRAP is not set
397CONFIG_NET_POLL_CONTROLLER=y
398# CONFIG_HAMRADIO is not set 393# CONFIG_HAMRADIO is not set
394# CONFIG_CAN is not set
399# CONFIG_IRDA is not set 395# CONFIG_IRDA is not set
400# CONFIG_BT is not set 396# CONFIG_BT is not set
401CONFIG_NETDEVICES=y 397# CONFIG_AF_RXRPC is not set
402CONFIG_DUMMY=m
403# CONFIG_BONDING is not set
404CONFIG_EQUALIZER=m
405# CONFIG_TUN is not set
406 398
407# 399#
408# Ethernet (10 or 100Mbit) 400# Wireless
409# 401#
410CONFIG_NET_ETHERNET=y 402# CONFIG_CFG80211 is not set
411CONFIG_MII=m 403CONFIG_WIRELESS_EXT=y
412CONFIG_SUN3LANCE=y 404# CONFIG_MAC80211 is not set
405CONFIG_IEEE80211=m
406# CONFIG_IEEE80211_DEBUG is not set
407CONFIG_IEEE80211_CRYPT_WEP=m
408CONFIG_IEEE80211_CRYPT_CCMP=m
409CONFIG_IEEE80211_CRYPT_TKIP=m
410CONFIG_IEEE80211_SOFTMAC=m
411# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
412# CONFIG_RFKILL is not set
413# CONFIG_NET_9P is not set
413 414
414# 415#
415# Ethernet (1000 Mbit) 416# Device Drivers
416# 417#
417 418
418# 419#
419# Ethernet (10000 Mbit) 420# Generic Driver Options
420# 421#
422CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
423CONFIG_STANDALONE=y
424CONFIG_PREVENT_FIRMWARE_BUILD=y
425CONFIG_FW_LOADER=m
426# CONFIG_SYS_HYPERVISOR is not set
427CONFIG_CONNECTOR=m
428# CONFIG_MTD is not set
429# CONFIG_PARPORT is not set
430CONFIG_BLK_DEV=y
431# CONFIG_BLK_DEV_COW_COMMON is not set
432CONFIG_BLK_DEV_LOOP=y
433CONFIG_BLK_DEV_CRYPTOLOOP=m
434CONFIG_BLK_DEV_NBD=m
435CONFIG_BLK_DEV_RAM=y
436CONFIG_BLK_DEV_RAM_COUNT=16
437CONFIG_BLK_DEV_RAM_SIZE=4096
438# CONFIG_BLK_DEV_XIP is not set
439CONFIG_CDROM_PKTCDVD=m
440CONFIG_CDROM_PKTCDVD_BUFFERS=8
441# CONFIG_CDROM_PKTCDVD_WCACHE is not set
442CONFIG_ATA_OVER_ETH=m
443CONFIG_MISC_DEVICES=y
444# CONFIG_EEPROM_93CX6 is not set
445# CONFIG_ENCLOSURE_SERVICES is not set
446CONFIG_HAVE_IDE=y
447# CONFIG_IDE is not set
421 448
422# 449#
423# Token Ring devices 450# SCSI device support
424# 451#
452CONFIG_RAID_ATTRS=m
453CONFIG_SCSI=y
454CONFIG_SCSI_DMA=y
455CONFIG_SCSI_TGT=m
456# CONFIG_SCSI_NETLINK is not set
457CONFIG_SCSI_PROC_FS=y
425 458
426# 459#
427# Wireless LAN (non-hamradio) 460# SCSI support type (disk, tape, CD-ROM)
428# 461#
429# CONFIG_NET_RADIO is not set 462CONFIG_BLK_DEV_SD=y
463CONFIG_CHR_DEV_ST=m
464CONFIG_CHR_DEV_OSST=m
465CONFIG_BLK_DEV_SR=y
466CONFIG_BLK_DEV_SR_VENDOR=y
467CONFIG_CHR_DEV_SG=m
468# CONFIG_CHR_DEV_SCH is not set
430 469
431# 470#
432# Wan interfaces 471# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
433# 472#
473# CONFIG_SCSI_MULTI_LUN is not set
474CONFIG_SCSI_CONSTANTS=y
475# CONFIG_SCSI_LOGGING is not set
476# CONFIG_SCSI_SCAN_ASYNC is not set
477CONFIG_SCSI_WAIT_SCAN=m
478
479#
480# SCSI Transports
481#
482CONFIG_SCSI_SPI_ATTRS=y
483# CONFIG_SCSI_FC_ATTRS is not set
484CONFIG_SCSI_ISCSI_ATTRS=m
485CONFIG_SCSI_SAS_ATTRS=m
486CONFIG_SCSI_SAS_LIBSAS=m
487CONFIG_SCSI_SAS_HOST_SMP=y
488# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
489CONFIG_SCSI_SRP_ATTRS=m
490CONFIG_SCSI_SRP_TGT_ATTRS=y
491CONFIG_SCSI_LOWLEVEL=y
492CONFIG_ISCSI_TCP=m
493# CONFIG_SCSI_DEBUG is not set
494CONFIG_SUN3X_ESP=y
495CONFIG_MD=y
496CONFIG_BLK_DEV_MD=m
497CONFIG_MD_LINEAR=m
498CONFIG_MD_RAID0=m
499CONFIG_MD_RAID1=m
500# CONFIG_MD_RAID10 is not set
501CONFIG_MD_RAID456=m
502CONFIG_MD_RAID5_RESHAPE=y
503CONFIG_MD_MULTIPATH=m
504# CONFIG_MD_FAULTY is not set
505CONFIG_BLK_DEV_DM=m
506# CONFIG_DM_DEBUG is not set
507CONFIG_DM_CRYPT=m
508CONFIG_DM_SNAPSHOT=m
509CONFIG_DM_MIRROR=m
510CONFIG_DM_ZERO=m
511CONFIG_DM_MULTIPATH=m
512CONFIG_DM_MULTIPATH_EMC=m
513CONFIG_DM_MULTIPATH_RDAC=m
514CONFIG_DM_MULTIPATH_HP=m
515# CONFIG_DM_DELAY is not set
516CONFIG_DM_UEVENT=y
517CONFIG_NETDEVICES=y
518# CONFIG_NETDEVICES_MULTIQUEUE is not set
519CONFIG_DUMMY=m
520# CONFIG_BONDING is not set
521CONFIG_MACVLAN=m
522CONFIG_EQUALIZER=m
523# CONFIG_TUN is not set
524CONFIG_VETH=m
525# CONFIG_PHYLIB is not set
526CONFIG_NET_ETHERNET=y
527# CONFIG_MII is not set
528CONFIG_SUN3LANCE=y
529# CONFIG_IBM_NEW_EMAC_ZMII is not set
530# CONFIG_IBM_NEW_EMAC_RGMII is not set
531# CONFIG_IBM_NEW_EMAC_TAH is not set
532# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
533# CONFIG_B44 is not set
534# CONFIG_NETDEV_1000 is not set
535# CONFIG_NETDEV_10000 is not set
536
537#
538# Wireless LAN
539#
540# CONFIG_WLAN_PRE80211 is not set
541# CONFIG_WLAN_80211 is not set
434# CONFIG_WAN is not set 542# CONFIG_WAN is not set
435CONFIG_PPP=m 543CONFIG_PPP=m
436# CONFIG_PPP_MULTILINK is not set 544# CONFIG_PPP_MULTILINK is not set
@@ -439,28 +547,28 @@ CONFIG_PPP_ASYNC=m
439CONFIG_PPP_SYNC_TTY=m 547CONFIG_PPP_SYNC_TTY=m
440CONFIG_PPP_DEFLATE=m 548CONFIG_PPP_DEFLATE=m
441CONFIG_PPP_BSDCOMP=m 549CONFIG_PPP_BSDCOMP=m
550CONFIG_PPP_MPPE=m
442CONFIG_PPPOE=m 551CONFIG_PPPOE=m
552CONFIG_PPPOL2TP=m
443CONFIG_SLIP=m 553CONFIG_SLIP=m
444CONFIG_SLIP_COMPRESSED=y 554CONFIG_SLIP_COMPRESSED=y
555CONFIG_SLHC=m
445CONFIG_SLIP_SMART=y 556CONFIG_SLIP_SMART=y
446CONFIG_SLIP_MODE_SLIP6=y 557CONFIG_SLIP_MODE_SLIP6=y
447CONFIG_SHAPER=m
448CONFIG_NETCONSOLE=m 558CONFIG_NETCONSOLE=m
449 559CONFIG_NETCONSOLE_DYNAMIC=y
450# 560CONFIG_NETPOLL=y
451# ISDN subsystem 561# CONFIG_NETPOLL_TRAP is not set
452# 562CONFIG_NET_POLL_CONTROLLER=y
453# CONFIG_ISDN is not set 563# CONFIG_ISDN is not set
454
455#
456# Telephony Support
457#
458# CONFIG_PHONE is not set 564# CONFIG_PHONE is not set
459 565
460# 566#
461# Input device support 567# Input device support
462# 568#
463CONFIG_INPUT=y 569CONFIG_INPUT=y
570CONFIG_INPUT_FF_MEMLESS=m
571# CONFIG_INPUT_POLLDEV is not set
464 572
465# 573#
466# Userland interfaces 574# Userland interfaces
@@ -470,7 +578,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
470CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 578CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
471CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 579CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
472# CONFIG_INPUT_JOYDEV is not set 580# CONFIG_INPUT_JOYDEV is not set
473# CONFIG_INPUT_TSDEV is not set
474# CONFIG_INPUT_EVDEV is not set 581# CONFIG_INPUT_EVDEV is not set
475# CONFIG_INPUT_EVBUG is not set 582# CONFIG_INPUT_EVBUG is not set
476 583
@@ -483,11 +590,19 @@ CONFIG_KEYBOARD_SUNKBD=y
483# CONFIG_KEYBOARD_LKKBD is not set 590# CONFIG_KEYBOARD_LKKBD is not set
484# CONFIG_KEYBOARD_XTKBD is not set 591# CONFIG_KEYBOARD_XTKBD is not set
485# CONFIG_KEYBOARD_NEWTON is not set 592# CONFIG_KEYBOARD_NEWTON is not set
593# CONFIG_KEYBOARD_STOWAWAY is not set
486CONFIG_INPUT_MOUSE=y 594CONFIG_INPUT_MOUSE=y
487CONFIG_MOUSE_PS2=m 595CONFIG_MOUSE_PS2=m
596CONFIG_MOUSE_PS2_ALPS=y
597CONFIG_MOUSE_PS2_LOGIPS2PP=y
598CONFIG_MOUSE_PS2_SYNAPTICS=y
599CONFIG_MOUSE_PS2_LIFEBOOK=y
600CONFIG_MOUSE_PS2_TRACKPOINT=y
601# CONFIG_MOUSE_PS2_TOUCHKIT is not set
488CONFIG_MOUSE_SERIAL=m 602CONFIG_MOUSE_SERIAL=m
489# CONFIG_MOUSE_VSXXXAA is not set 603# CONFIG_MOUSE_VSXXXAA is not set
490# CONFIG_INPUT_JOYSTICK is not set 604# CONFIG_INPUT_JOYSTICK is not set
605# CONFIG_INPUT_TABLET is not set
491# CONFIG_INPUT_TOUCHSCREEN is not set 606# CONFIG_INPUT_TOUCHSCREEN is not set
492# CONFIG_INPUT_MISC is not set 607# CONFIG_INPUT_MISC is not set
493 608
@@ -495,7 +610,7 @@ CONFIG_MOUSE_SERIAL=m
495# Hardware I/O ports 610# Hardware I/O ports
496# 611#
497CONFIG_SERIO=y 612CONFIG_SERIO=y
498CONFIG_SERIO_SERPORT=m 613# CONFIG_SERIO_SERPORT is not set
499CONFIG_SERIO_LIBPS2=m 614CONFIG_SERIO_LIBPS2=m
500# CONFIG_SERIO_RAW is not set 615# CONFIG_SERIO_RAW is not set
501# CONFIG_GAMEPORT is not set 616# CONFIG_GAMEPORT is not set
@@ -506,6 +621,7 @@ CONFIG_SERIO_LIBPS2=m
506CONFIG_VT=y 621CONFIG_VT=y
507CONFIG_VT_CONSOLE=y 622CONFIG_VT_CONSOLE=y
508CONFIG_HW_CONSOLE=y 623CONFIG_HW_CONSOLE=y
624CONFIG_VT_HW_CONSOLE_BINDING=y
509# CONFIG_SERIAL_NONSTANDARD is not set 625# CONFIG_SERIAL_NONSTANDARD is not set
510 626
511# 627#
@@ -519,112 +635,113 @@ CONFIG_HW_CONSOLE=y
519CONFIG_UNIX98_PTYS=y 635CONFIG_UNIX98_PTYS=y
520CONFIG_LEGACY_PTYS=y 636CONFIG_LEGACY_PTYS=y
521CONFIG_LEGACY_PTY_COUNT=256 637CONFIG_LEGACY_PTY_COUNT=256
522
523#
524# IPMI
525#
526# CONFIG_IPMI_HANDLER is not set 638# CONFIG_IPMI_HANDLER is not set
527 639# CONFIG_HW_RANDOM is not set
528# 640CONFIG_GEN_RTC=m
529# Watchdog Cards
530#
531# CONFIG_WATCHDOG is not set
532CONFIG_GEN_RTC=y
533CONFIG_GEN_RTC_X=y 641CONFIG_GEN_RTC_X=y
534# CONFIG_DTLK is not set
535# CONFIG_R3964 is not set 642# CONFIG_R3964 is not set
536
537#
538# Ftape, the floppy tape device driver
539#
540# CONFIG_DRM is not set
541# CONFIG_RAW_DRIVER is not set 643# CONFIG_RAW_DRIVER is not set
542 644# CONFIG_TCG_TPM is not set
543#
544# TPM devices
545#
546
547#
548# I2C support
549#
550# CONFIG_I2C is not set 645# CONFIG_I2C is not set
551 646
552# 647#
553# Dallas's 1-wire bus 648# SPI support
554# 649#
650# CONFIG_SPI is not set
651# CONFIG_SPI_MASTER is not set
555# CONFIG_W1 is not set 652# CONFIG_W1 is not set
653# CONFIG_POWER_SUPPLY is not set
654# CONFIG_HWMON is not set
655# CONFIG_THERMAL is not set
656# CONFIG_WATCHDOG is not set
556 657
557# 658#
558# Misc devices 659# Sonics Silicon Backplane
559# 660#
661CONFIG_SSB_POSSIBLE=y
662# CONFIG_SSB is not set
560 663
561# 664#
562# Multimedia devices 665# Multifunction device drivers
563# 666#
564# CONFIG_VIDEO_DEV is not set 667# CONFIG_MFD_SM501 is not set
565 668
566# 669#
567# Digital Video Broadcasting Devices 670# Multimedia devices
568# 671#
569# CONFIG_DVB is not set 672# CONFIG_VIDEO_DEV is not set
673# CONFIG_DVB_CORE is not set
674# CONFIG_DAB is not set
570 675
571# 676#
572# Graphics support 677# Graphics support
573# 678#
679# CONFIG_VGASTATE is not set
680# CONFIG_VIDEO_OUTPUT_CONTROL is not set
574CONFIG_FB=y 681CONFIG_FB=y
682# CONFIG_FIRMWARE_EDID is not set
683# CONFIG_FB_DDC is not set
575# CONFIG_FB_CFB_FILLRECT is not set 684# CONFIG_FB_CFB_FILLRECT is not set
576# CONFIG_FB_CFB_COPYAREA is not set 685# CONFIG_FB_CFB_COPYAREA is not set
577# CONFIG_FB_CFB_IMAGEBLIT is not set 686# CONFIG_FB_CFB_IMAGEBLIT is not set
578# CONFIG_FB_SOFT_CURSOR is not set 687# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
688# CONFIG_FB_SYS_FILLRECT is not set
689# CONFIG_FB_SYS_COPYAREA is not set
690# CONFIG_FB_SYS_IMAGEBLIT is not set
691# CONFIG_FB_SYS_FOPS is not set
692CONFIG_FB_DEFERRED_IO=y
693# CONFIG_FB_SVGALIB is not set
579# CONFIG_FB_MACMODES is not set 694# CONFIG_FB_MACMODES is not set
580CONFIG_FB_MODE_HELPERS=y 695# CONFIG_FB_BACKLIGHT is not set
696# CONFIG_FB_MODE_HELPERS is not set
581# CONFIG_FB_TILEBLITTING is not set 697# CONFIG_FB_TILEBLITTING is not set
698
699#
700# Frame buffer hardware drivers
701#
702# CONFIG_FB_UVESA is not set
582# CONFIG_FB_S1D13XXX is not set 703# CONFIG_FB_S1D13XXX is not set
583# CONFIG_FB_VIRTUAL is not set 704# CONFIG_FB_VIRTUAL is not set
705# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
706
707#
708# Display device support
709#
710# CONFIG_DISPLAY_SUPPORT is not set
584 711
585# 712#
586# Console display driver support 713# Console display driver support
587# 714#
588CONFIG_DUMMY_CONSOLE=y 715CONFIG_DUMMY_CONSOLE=y
589CONFIG_FRAMEBUFFER_CONSOLE=y 716CONFIG_FRAMEBUFFER_CONSOLE=y
717# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
718# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
590# CONFIG_FONTS is not set 719# CONFIG_FONTS is not set
591CONFIG_FONT_8x8=y 720CONFIG_FONT_8x8=y
592CONFIG_FONT_8x16=y 721CONFIG_FONT_8x16=y
593
594#
595# Logo configuration
596#
597CONFIG_LOGO=y 722CONFIG_LOGO=y
598CONFIG_LOGO_LINUX_MONO=y 723CONFIG_LOGO_LINUX_MONO=y
599CONFIG_LOGO_LINUX_VGA16=y 724CONFIG_LOGO_LINUX_VGA16=y
600CONFIG_LOGO_LINUX_CLUT224=y 725CONFIG_LOGO_LINUX_CLUT224=y
601# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
602 726
603# 727#
604# Sound 728# Sound
605# 729#
606# CONFIG_SOUND is not set 730# CONFIG_SOUND is not set
607 731CONFIG_HID_SUPPORT=y
608# 732CONFIG_HID=m
609# USB support 733# CONFIG_HID_DEBUG is not set
610# 734CONFIG_HIDRAW=y
611# CONFIG_USB_ARCH_HAS_HCD is not set 735# CONFIG_USB_SUPPORT is not set
612# CONFIG_USB_ARCH_HAS_OHCI is not set
613
614#
615# USB Gadget Support
616#
617# CONFIG_USB_GADGET is not set
618
619#
620# MMC/SD Card support
621#
622# CONFIG_MMC is not set 736# CONFIG_MMC is not set
737# CONFIG_MEMSTICK is not set
738# CONFIG_NEW_LEDS is not set
739# CONFIG_RTC_CLASS is not set
623 740
624# 741#
625# InfiniBand support 742# Userspace I/O
626# 743#
627# CONFIG_INFINIBAND is not set 744# CONFIG_UIO is not set
628 745
629# 746#
630# Character devices 747# Character devices
@@ -635,10 +752,11 @@ CONFIG_LOGO_LINUX_CLUT224=y
635# 752#
636CONFIG_EXT2_FS=y 753CONFIG_EXT2_FS=y
637# CONFIG_EXT2_FS_XATTR is not set 754# CONFIG_EXT2_FS_XATTR is not set
755# CONFIG_EXT2_FS_XIP is not set
638CONFIG_EXT3_FS=y 756CONFIG_EXT3_FS=y
639# CONFIG_EXT3_FS_XATTR is not set 757# CONFIG_EXT3_FS_XATTR is not set
758# CONFIG_EXT4DEV_FS is not set
640CONFIG_JBD=y 759CONFIG_JBD=y
641# CONFIG_JBD_DEBUG is not set
642CONFIG_REISERFS_FS=m 760CONFIG_REISERFS_FS=m
643# CONFIG_REISERFS_CHECK is not set 761# CONFIG_REISERFS_CHECK is not set
644# CONFIG_REISERFS_PROC_INFO is not set 762# CONFIG_REISERFS_PROC_INFO is not set
@@ -649,25 +767,29 @@ CONFIG_JFS_FS=m
649# CONFIG_JFS_DEBUG is not set 767# CONFIG_JFS_DEBUG is not set
650# CONFIG_JFS_STATISTICS is not set 768# CONFIG_JFS_STATISTICS is not set
651CONFIG_FS_POSIX_ACL=y 769CONFIG_FS_POSIX_ACL=y
652
653#
654# XFS support
655#
656CONFIG_XFS_FS=m 770CONFIG_XFS_FS=m
657CONFIG_XFS_EXPORT=y
658# CONFIG_XFS_RT is not set
659# CONFIG_XFS_QUOTA is not set 771# CONFIG_XFS_QUOTA is not set
660# CONFIG_XFS_SECURITY is not set 772# CONFIG_XFS_SECURITY is not set
661# CONFIG_XFS_POSIX_ACL is not set 773# CONFIG_XFS_POSIX_ACL is not set
662CONFIG_MINIX_FS=y 774# CONFIG_XFS_RT is not set
663# CONFIG_ROMFS_FS is not set 775CONFIG_GFS2_FS=m
776CONFIG_GFS2_FS_LOCKING_NOLOCK=m
777CONFIG_GFS2_FS_LOCKING_DLM=m
778CONFIG_OCFS2_FS=m
779# CONFIG_OCFS2_DEBUG_MASKLOG is not set
780# CONFIG_OCFS2_DEBUG_FS is not set
781CONFIG_DNOTIFY=y
782CONFIG_INOTIFY=y
783CONFIG_INOTIFY_USER=y
664CONFIG_QUOTA=y 784CONFIG_QUOTA=y
785CONFIG_QUOTA_NETLINK_INTERFACE=y
786# CONFIG_PRINT_QUOTA_WARNING is not set
665# CONFIG_QFMT_V1 is not set 787# CONFIG_QFMT_V1 is not set
666# CONFIG_QFMT_V2 is not set 788# CONFIG_QFMT_V2 is not set
667CONFIG_QUOTACTL=y 789CONFIG_QUOTACTL=y
668CONFIG_DNOTIFY=y
669CONFIG_AUTOFS_FS=m 790CONFIG_AUTOFS_FS=m
670CONFIG_AUTOFS4_FS=m 791CONFIG_AUTOFS4_FS=m
792CONFIG_FUSE_FS=m
671 793
672# 794#
673# CD-ROM/DVD Filesystems 795# CD-ROM/DVD Filesystems
@@ -675,7 +797,6 @@ CONFIG_AUTOFS4_FS=m
675CONFIG_ISO9660_FS=y 797CONFIG_ISO9660_FS=y
676CONFIG_JOLIET=y 798CONFIG_JOLIET=y
677CONFIG_ZISOFS=y 799CONFIG_ZISOFS=y
678CONFIG_ZISOFS_FS=y
679CONFIG_UDF_FS=m 800CONFIG_UDF_FS=m
680CONFIG_UDF_NLS=y 801CONFIG_UDF_NLS=y
681 802
@@ -694,15 +815,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
694# 815#
695CONFIG_PROC_FS=y 816CONFIG_PROC_FS=y
696CONFIG_PROC_KCORE=y 817CONFIG_PROC_KCORE=y
818CONFIG_PROC_SYSCTL=y
697CONFIG_SYSFS=y 819CONFIG_SYSFS=y
698CONFIG_DEVFS_FS=y
699CONFIG_DEVFS_MOUNT=y
700# CONFIG_DEVFS_DEBUG is not set
701# CONFIG_DEVPTS_FS_XATTR is not set
702CONFIG_TMPFS=y 820CONFIG_TMPFS=y
703# CONFIG_TMPFS_XATTR is not set 821# CONFIG_TMPFS_POSIX_ACL is not set
704# CONFIG_HUGETLB_PAGE is not set 822# CONFIG_HUGETLB_PAGE is not set
705CONFIG_RAMFS=y 823CONFIG_CONFIGFS_FS=m
706 824
707# 825#
708# Miscellaneous filesystems 826# Miscellaneous filesystems
@@ -716,44 +834,40 @@ CONFIG_HFSPLUS_FS=m
716# CONFIG_EFS_FS is not set 834# CONFIG_EFS_FS is not set
717CONFIG_CRAMFS=m 835CONFIG_CRAMFS=m
718# CONFIG_VXFS_FS is not set 836# CONFIG_VXFS_FS is not set
837CONFIG_MINIX_FS=y
719CONFIG_HPFS_FS=m 838CONFIG_HPFS_FS=m
720# CONFIG_QNX4FS_FS is not set 839# CONFIG_QNX4FS_FS is not set
840# CONFIG_ROMFS_FS is not set
721CONFIG_SYSV_FS=m 841CONFIG_SYSV_FS=m
722CONFIG_UFS_FS=m 842CONFIG_UFS_FS=m
723CONFIG_UFS_FS_WRITE=y 843# CONFIG_UFS_FS_WRITE is not set
724 844# CONFIG_UFS_DEBUG is not set
725# 845CONFIG_NETWORK_FILESYSTEMS=y
726# Network File Systems
727#
728CONFIG_NFS_FS=y 846CONFIG_NFS_FS=y
729CONFIG_NFS_V3=y 847CONFIG_NFS_V3=y
848# CONFIG_NFS_V3_ACL is not set
730CONFIG_NFS_V4=y 849CONFIG_NFS_V4=y
731# CONFIG_NFS_DIRECTIO is not set 850# CONFIG_NFS_DIRECTIO is not set
732CONFIG_NFSD=m 851CONFIG_NFSD=m
733CONFIG_NFSD_V3=y 852CONFIG_NFSD_V3=y
734CONFIG_NFSD_V4=y 853# CONFIG_NFSD_V3_ACL is not set
854# CONFIG_NFSD_V4 is not set
735CONFIG_NFSD_TCP=y 855CONFIG_NFSD_TCP=y
736CONFIG_ROOT_NFS=y 856CONFIG_ROOT_NFS=y
737CONFIG_LOCKD=y 857CONFIG_LOCKD=y
738CONFIG_LOCKD_V4=y 858CONFIG_LOCKD_V4=y
739CONFIG_EXPORTFS=m 859CONFIG_EXPORTFS=m
860CONFIG_NFS_COMMON=y
740CONFIG_SUNRPC=y 861CONFIG_SUNRPC=y
741CONFIG_SUNRPC_GSS=y 862CONFIG_SUNRPC_GSS=y
863CONFIG_SUNRPC_BIND34=y
742CONFIG_RPCSEC_GSS_KRB5=y 864CONFIG_RPCSEC_GSS_KRB5=y
743# CONFIG_RPCSEC_GSS_SPKM3 is not set 865# CONFIG_RPCSEC_GSS_SPKM3 is not set
744CONFIG_SMB_FS=m 866CONFIG_SMB_FS=m
745CONFIG_SMB_NLS_DEFAULT=y 867CONFIG_SMB_NLS_DEFAULT=y
746CONFIG_SMB_NLS_REMOTE="cp437" 868CONFIG_SMB_NLS_REMOTE="cp437"
747# CONFIG_CIFS is not set 869# CONFIG_CIFS is not set
748CONFIG_NCP_FS=m 870# CONFIG_NCP_FS is not set
749# CONFIG_NCPFS_PACKET_SIGNING is not set
750# CONFIG_NCPFS_IOCTL_LOCKING is not set
751# CONFIG_NCPFS_STRONG is not set
752# CONFIG_NCPFS_NFS_NS is not set
753# CONFIG_NCPFS_OS2_NS is not set
754# CONFIG_NCPFS_SMALLDOS is not set
755CONFIG_NCPFS_NLS=y
756# CONFIG_NCPFS_EXTRAS is not set
757CONFIG_CODA_FS=m 871CONFIG_CODA_FS=m
758# CONFIG_CODA_FS_OLD_API is not set 872# CONFIG_CODA_FS_OLD_API is not set
759# CONFIG_AFS_FS is not set 873# CONFIG_AFS_FS is not set
@@ -764,10 +878,6 @@ CONFIG_CODA_FS=m
764# CONFIG_PARTITION_ADVANCED is not set 878# CONFIG_PARTITION_ADVANCED is not set
765CONFIG_MSDOS_PARTITION=y 879CONFIG_MSDOS_PARTITION=y
766CONFIG_SUN_PARTITION=y 880CONFIG_SUN_PARTITION=y
767
768#
769# Native Language Support
770#
771CONFIG_NLS=y 881CONFIG_NLS=y
772CONFIG_NLS_DEFAULT="iso8859-1" 882CONFIG_NLS_DEFAULT="iso8859-1"
773CONFIG_NLS_CODEPAGE_437=y 883CONFIG_NLS_CODEPAGE_437=y
@@ -808,35 +918,42 @@ CONFIG_NLS_ISO8859_15=m
808CONFIG_NLS_KOI8_R=m 918CONFIG_NLS_KOI8_R=m
809CONFIG_NLS_KOI8_U=m 919CONFIG_NLS_KOI8_U=m
810CONFIG_NLS_UTF8=m 920CONFIG_NLS_UTF8=m
921CONFIG_DLM=m
922# CONFIG_DLM_DEBUG is not set
811 923
812# 924#
813# Kernel hacking 925# Kernel hacking
814# 926#
815# CONFIG_PRINTK_TIME is not set 927# CONFIG_PRINTK_TIME is not set
816CONFIG_DEBUG_KERNEL=y 928CONFIG_ENABLE_WARN_DEPRECATED=y
929CONFIG_ENABLE_MUST_CHECK=y
817CONFIG_MAGIC_SYSRQ=y 930CONFIG_MAGIC_SYSRQ=y
818CONFIG_LOG_BUF_SHIFT=16 931# CONFIG_UNUSED_SYMBOLS is not set
819# CONFIG_SCHEDSTATS is not set
820# CONFIG_DEBUG_SLAB is not set
821# CONFIG_DEBUG_SPINLOCK is not set
822# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
823# CONFIG_DEBUG_KOBJECT is not set
824CONFIG_DEBUG_BUGVERBOSE=y
825# CONFIG_DEBUG_INFO is not set
826# CONFIG_DEBUG_FS is not set 932# CONFIG_DEBUG_FS is not set
827# CONFIG_FRAME_POINTER is not set 933# CONFIG_HEADERS_CHECK is not set
934# CONFIG_DEBUG_KERNEL is not set
935CONFIG_DEBUG_BUGVERBOSE=y
936# CONFIG_SAMPLES is not set
828 937
829# 938#
830# Security options 939# Security options
831# 940#
832# CONFIG_KEYS is not set 941# CONFIG_KEYS is not set
833# CONFIG_SECURITY is not set 942# CONFIG_SECURITY is not set
834 943# CONFIG_SECURITY_FILE_CAPABILITIES is not set
835# 944CONFIG_XOR_BLOCKS=m
836# Cryptographic options 945CONFIG_ASYNC_CORE=m
837# 946CONFIG_ASYNC_MEMCPY=m
947CONFIG_ASYNC_XOR=m
838CONFIG_CRYPTO=y 948CONFIG_CRYPTO=y
949CONFIG_CRYPTO_ALGAPI=y
950CONFIG_CRYPTO_AEAD=m
951CONFIG_CRYPTO_BLKCIPHER=y
952CONFIG_CRYPTO_SEQIV=m
953CONFIG_CRYPTO_HASH=y
954CONFIG_CRYPTO_MANAGER=y
839CONFIG_CRYPTO_HMAC=y 955CONFIG_CRYPTO_HMAC=y
956CONFIG_CRYPTO_XCBC=m
840CONFIG_CRYPTO_NULL=m 957CONFIG_CRYPTO_NULL=m
841CONFIG_CRYPTO_MD4=m 958CONFIG_CRYPTO_MD4=m
842CONFIG_CRYPTO_MD5=y 959CONFIG_CRYPTO_MD5=y
@@ -845,9 +962,21 @@ CONFIG_CRYPTO_SHA256=m
845CONFIG_CRYPTO_SHA512=m 962CONFIG_CRYPTO_SHA512=m
846CONFIG_CRYPTO_WP512=m 963CONFIG_CRYPTO_WP512=m
847CONFIG_CRYPTO_TGR192=m 964CONFIG_CRYPTO_TGR192=m
965CONFIG_CRYPTO_GF128MUL=m
966CONFIG_CRYPTO_ECB=m
967CONFIG_CRYPTO_CBC=y
968CONFIG_CRYPTO_PCBC=m
969CONFIG_CRYPTO_LRW=m
970CONFIG_CRYPTO_XTS=m
971CONFIG_CRYPTO_CTR=m
972CONFIG_CRYPTO_GCM=m
973CONFIG_CRYPTO_CCM=m
974CONFIG_CRYPTO_CRYPTD=m
848CONFIG_CRYPTO_DES=y 975CONFIG_CRYPTO_DES=y
976CONFIG_CRYPTO_FCRYPT=m
849CONFIG_CRYPTO_BLOWFISH=m 977CONFIG_CRYPTO_BLOWFISH=m
850CONFIG_CRYPTO_TWOFISH=m 978CONFIG_CRYPTO_TWOFISH=m
979CONFIG_CRYPTO_TWOFISH_COMMON=m
851CONFIG_CRYPTO_SERPENT=m 980CONFIG_CRYPTO_SERPENT=m
852CONFIG_CRYPTO_AES=m 981CONFIG_CRYPTO_AES=m
853CONFIG_CRYPTO_CAST5=m 982CONFIG_CRYPTO_CAST5=m
@@ -856,20 +985,35 @@ CONFIG_CRYPTO_TEA=m
856CONFIG_CRYPTO_ARC4=m 985CONFIG_CRYPTO_ARC4=m
857CONFIG_CRYPTO_KHAZAD=m 986CONFIG_CRYPTO_KHAZAD=m
858CONFIG_CRYPTO_ANUBIS=m 987CONFIG_CRYPTO_ANUBIS=m
988CONFIG_CRYPTO_SEED=m
989CONFIG_CRYPTO_SALSA20=m
859CONFIG_CRYPTO_DEFLATE=m 990CONFIG_CRYPTO_DEFLATE=m
860CONFIG_CRYPTO_MICHAEL_MIC=m 991CONFIG_CRYPTO_MICHAEL_MIC=m
861CONFIG_CRYPTO_CRC32C=m 992CONFIG_CRYPTO_CRC32C=m
993CONFIG_CRYPTO_CAMELLIA=m
862CONFIG_CRYPTO_TEST=m 994CONFIG_CRYPTO_TEST=m
863 995CONFIG_CRYPTO_AUTHENC=m
864# 996CONFIG_CRYPTO_LZO=m
865# Hardware crypto devices 997# CONFIG_CRYPTO_HW is not set
866#
867 998
868# 999#
869# Library routines 1000# Library routines
870# 1001#
1002CONFIG_BITREVERSE=y
871CONFIG_CRC_CCITT=m 1003CONFIG_CRC_CCITT=m
1004CONFIG_CRC16=m
1005# CONFIG_CRC_ITU_T is not set
872CONFIG_CRC32=y 1006CONFIG_CRC32=y
1007# CONFIG_CRC7 is not set
873CONFIG_LIBCRC32C=m 1008CONFIG_LIBCRC32C=m
874CONFIG_ZLIB_INFLATE=y 1009CONFIG_ZLIB_INFLATE=y
875CONFIG_ZLIB_DEFLATE=m 1010CONFIG_ZLIB_DEFLATE=m
1011CONFIG_LZO_COMPRESS=m
1012CONFIG_LZO_DECOMPRESS=m
1013CONFIG_TEXTSEARCH=y
1014CONFIG_TEXTSEARCH_KMP=m
1015CONFIG_TEXTSEARCH_BM=m
1016CONFIG_TEXTSEARCH_FSM=m
1017CONFIG_PLIST=y
1018CONFIG_HAS_IOMEM=y
1019CONFIG_HAS_DMA=y
diff --git a/arch/m68k/defconfig b/arch/m68k/defconfig
deleted file mode 100644
index 7d935e48a9a..00000000000
--- a/arch/m68k/defconfig
+++ /dev/null
@@ -1,657 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc6-m68k
4# Tue Jun 7 20:34:17 2005
5#
6CONFIG_M68K=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11
12#
13# Code maturity level options
14#
15CONFIG_EXPERIMENTAL=y
16CONFIG_CLEAN_COMPILE=y
17CONFIG_BROKEN_ON_SMP=y
18CONFIG_INIT_ENV_ARG_LIMIT=32
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27# CONFIG_BSD_PROCESS_ACCT is not set
28CONFIG_SYSCTL=y
29# CONFIG_AUDIT is not set
30# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y
32# CONFIG_IKCONFIG is not set
33# CONFIG_EMBEDDED is not set
34CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
39CONFIG_FUTEX=y
40CONFIG_EPOLL=y
41CONFIG_SHMEM=y
42CONFIG_CC_ALIGN_FUNCTIONS=0
43CONFIG_CC_ALIGN_LABELS=0
44CONFIG_CC_ALIGN_LOOPS=0
45CONFIG_CC_ALIGN_JUMPS=0
46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
48
49#
50# Loadable module support
51#
52# CONFIG_MODULES is not set
53
54#
55# Platform dependent setup
56#
57# CONFIG_SUN3 is not set
58CONFIG_AMIGA=y
59# CONFIG_ATARI is not set
60# CONFIG_MAC is not set
61# CONFIG_APOLLO is not set
62# CONFIG_VME is not set
63# CONFIG_HP300 is not set
64# CONFIG_SUN3X is not set
65# CONFIG_Q40 is not set
66
67#
68# Processor type
69#
70CONFIG_M68020=y
71CONFIG_M68030=y
72CONFIG_M68040=y
73# CONFIG_M68060 is not set
74CONFIG_MMU_MOTOROLA=y
75# CONFIG_M68KFPU_EMU is not set
76# CONFIG_ADVANCED is not set
77
78#
79# General setup
80#
81CONFIG_BINFMT_ELF=y
82CONFIG_BINFMT_AOUT=y
83# CONFIG_BINFMT_MISC is not set
84CONFIG_ZORRO=y
85# CONFIG_AMIGA_PCMCIA is not set
86# CONFIG_HEARTBEAT is not set
87CONFIG_PROC_HARDWARE=y
88# CONFIG_ZORRO_NAMES is not set
89
90#
91# Device Drivers
92#
93
94#
95# Generic Driver Options
96#
97CONFIG_STANDALONE=y
98CONFIG_PREVENT_FIRMWARE_BUILD=y
99# CONFIG_FW_LOADER is not set
100
101#
102# Memory Technology Devices (MTD)
103#
104# CONFIG_MTD is not set
105
106#
107# Parallel port support
108#
109# CONFIG_PARPORT is not set
110
111#
112# Plug and Play support
113#
114
115#
116# Block devices
117#
118CONFIG_AMIGA_FLOPPY=y
119# CONFIG_AMIGA_Z2RAM is not set
120# CONFIG_BLK_DEV_COW_COMMON is not set
121# CONFIG_BLK_DEV_LOOP is not set
122# CONFIG_BLK_DEV_NBD is not set
123CONFIG_BLK_DEV_RAM=y
124CONFIG_BLK_DEV_RAM_COUNT=16
125CONFIG_BLK_DEV_RAM_SIZE=4096
126CONFIG_BLK_DEV_INITRD=y
127CONFIG_INITRAMFS_SOURCE=""
128CONFIG_CDROM_PKTCDVD=y
129CONFIG_CDROM_PKTCDVD_BUFFERS=8
130# CONFIG_CDROM_PKTCDVD_WCACHE is not set
131
132#
133# IO Schedulers
134#
135CONFIG_IOSCHED_NOOP=y
136CONFIG_IOSCHED_AS=y
137CONFIG_IOSCHED_DEADLINE=y
138CONFIG_IOSCHED_CFQ=y
139# CONFIG_ATA_OVER_ETH is not set
140
141#
142# ATA/ATAPI/MFM/RLL support
143#
144# CONFIG_IDE is not set
145
146#
147# SCSI device support
148#
149CONFIG_SCSI=y
150CONFIG_SCSI_PROC_FS=y
151
152#
153# SCSI support type (disk, tape, CD-ROM)
154#
155CONFIG_BLK_DEV_SD=y
156CONFIG_CHR_DEV_ST=y
157# CONFIG_CHR_DEV_OSST is not set
158CONFIG_BLK_DEV_SR=y
159# CONFIG_BLK_DEV_SR_VENDOR is not set
160# CONFIG_CHR_DEV_SG is not set
161
162#
163# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
164#
165# CONFIG_SCSI_MULTI_LUN is not set
166CONFIG_SCSI_CONSTANTS=y
167# CONFIG_SCSI_LOGGING is not set
168
169#
170# SCSI Transport Attributes
171#
172# CONFIG_SCSI_SPI_ATTRS is not set
173# CONFIG_SCSI_FC_ATTRS is not set
174# CONFIG_SCSI_ISCSI_ATTRS is not set
175
176#
177# SCSI low-level drivers
178#
179# CONFIG_SCSI_SATA is not set
180# CONFIG_SCSI_DEBUG is not set
181CONFIG_A3000_SCSI=y
182CONFIG_A2091_SCSI=y
183CONFIG_GVP11_SCSI=y
184# CONFIG_CYBERSTORM_SCSI is not set
185# CONFIG_CYBERSTORMII_SCSI is not set
186# CONFIG_BLZ2060_SCSI is not set
187# CONFIG_BLZ1230_SCSI is not set
188# CONFIG_FASTLANE_SCSI is not set
189# CONFIG_OKTAGON_SCSI is not set
190
191#
192# Multi-device support (RAID and LVM)
193#
194# CONFIG_MD is not set
195
196#
197# Fusion MPT device support
198#
199
200#
201# IEEE 1394 (FireWire) support
202#
203
204#
205# I2O device support
206#
207
208#
209# Networking support
210#
211CONFIG_NET=y
212
213#
214# Networking options
215#
216CONFIG_PACKET=y
217# CONFIG_PACKET_MMAP is not set
218CONFIG_UNIX=y
219# CONFIG_NET_KEY is not set
220CONFIG_INET=y
221# CONFIG_IP_MULTICAST is not set
222# CONFIG_IP_ADVANCED_ROUTER is not set
223# CONFIG_IP_PNP is not set
224# CONFIG_NET_IPIP is not set
225# CONFIG_NET_IPGRE is not set
226# CONFIG_ARPD is not set
227# CONFIG_SYN_COOKIES is not set
228# CONFIG_INET_AH is not set
229# CONFIG_INET_ESP is not set
230# CONFIG_INET_IPCOMP is not set
231# CONFIG_INET_TUNNEL is not set
232CONFIG_IP_TCPDIAG=y
233# CONFIG_IP_TCPDIAG_IPV6 is not set
234# CONFIG_IPV6 is not set
235# CONFIG_NETFILTER is not set
236
237#
238# SCTP Configuration (EXPERIMENTAL)
239#
240# CONFIG_IP_SCTP is not set
241# CONFIG_ATM is not set
242# CONFIG_BRIDGE is not set
243# CONFIG_VLAN_8021Q is not set
244# CONFIG_DECNET is not set
245# CONFIG_LLC2 is not set
246# CONFIG_IPX is not set
247# CONFIG_ATALK is not set
248# CONFIG_X25 is not set
249# CONFIG_LAPB is not set
250# CONFIG_NET_DIVERT is not set
251# CONFIG_ECONET is not set
252# CONFIG_WAN_ROUTER is not set
253
254#
255# QoS and/or fair queueing
256#
257# CONFIG_NET_SCHED is not set
258# CONFIG_NET_CLS_ROUTE is not set
259
260#
261# Network testing
262#
263# CONFIG_NET_PKTGEN is not set
264# CONFIG_NETPOLL is not set
265# CONFIG_NET_POLL_CONTROLLER is not set
266# CONFIG_HAMRADIO is not set
267# CONFIG_IRDA is not set
268# CONFIG_BT is not set
269CONFIG_NETDEVICES=y
270# CONFIG_DUMMY is not set
271# CONFIG_BONDING is not set
272# CONFIG_EQUALIZER is not set
273# CONFIG_TUN is not set
274
275#
276# Ethernet (10 or 100Mbit)
277#
278# CONFIG_NET_ETHERNET is not set
279
280#
281# Ethernet (1000 Mbit)
282#
283
284#
285# Ethernet (10000 Mbit)
286#
287
288#
289# Token Ring devices
290#
291
292#
293# Wireless LAN (non-hamradio)
294#
295# CONFIG_NET_RADIO is not set
296
297#
298# Wan interfaces
299#
300# CONFIG_WAN is not set
301# CONFIG_PPP is not set
302# CONFIG_SLIP is not set
303# CONFIG_SHAPER is not set
304# CONFIG_NETCONSOLE is not set
305
306#
307# ISDN subsystem
308#
309# CONFIG_ISDN is not set
310
311#
312# Telephony Support
313#
314# CONFIG_PHONE is not set
315
316#
317# Input device support
318#
319CONFIG_INPUT=y
320
321#
322# Userland interfaces
323#
324CONFIG_INPUT_MOUSEDEV=y
325CONFIG_INPUT_MOUSEDEV_PSAUX=y
326CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
327CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
328# CONFIG_INPUT_JOYDEV is not set
329# CONFIG_INPUT_TSDEV is not set
330# CONFIG_INPUT_EVDEV is not set
331# CONFIG_INPUT_EVBUG is not set
332
333#
334# Input Device Drivers
335#
336CONFIG_INPUT_KEYBOARD=y
337CONFIG_KEYBOARD_ATKBD=y
338# CONFIG_KEYBOARD_SUNKBD is not set
339# CONFIG_KEYBOARD_LKKBD is not set
340# CONFIG_KEYBOARD_XTKBD is not set
341# CONFIG_KEYBOARD_NEWTON is not set
342# CONFIG_KEYBOARD_AMIGA is not set
343CONFIG_INPUT_MOUSE=y
344CONFIG_MOUSE_PS2=y
345# CONFIG_MOUSE_SERIAL is not set
346# CONFIG_MOUSE_AMIGA is not set
347# CONFIG_MOUSE_VSXXXAA is not set
348# CONFIG_INPUT_JOYSTICK is not set
349# CONFIG_INPUT_TOUCHSCREEN is not set
350# CONFIG_INPUT_MISC is not set
351
352#
353# Hardware I/O ports
354#
355CONFIG_SERIO=y
356CONFIG_SERIO_SERPORT=y
357CONFIG_SERIO_LIBPS2=y
358# CONFIG_SERIO_RAW is not set
359# CONFIG_GAMEPORT is not set
360
361#
362# Character devices
363#
364CONFIG_VT=y
365CONFIG_VT_CONSOLE=y
366CONFIG_HW_CONSOLE=y
367# CONFIG_SERIAL_NONSTANDARD is not set
368# CONFIG_A2232 is not set
369
370#
371# Serial drivers
372#
373# CONFIG_SERIAL_8250 is not set
374
375#
376# Non-8250 serial port support
377#
378CONFIG_UNIX98_PTYS=y
379CONFIG_LEGACY_PTYS=y
380CONFIG_LEGACY_PTY_COUNT=256
381
382#
383# IPMI
384#
385# CONFIG_IPMI_HANDLER is not set
386
387#
388# Watchdog Cards
389#
390# CONFIG_WATCHDOG is not set
391# CONFIG_GEN_RTC is not set
392# CONFIG_DTLK is not set
393# CONFIG_R3964 is not set
394
395#
396# Ftape, the floppy tape device driver
397#
398# CONFIG_DRM is not set
399# CONFIG_RAW_DRIVER is not set
400
401#
402# TPM devices
403#
404
405#
406# I2C support
407#
408# CONFIG_I2C is not set
409
410#
411# Dallas's 1-wire bus
412#
413# CONFIG_W1 is not set
414
415#
416# Misc devices
417#
418
419#
420# Multimedia devices
421#
422# CONFIG_VIDEO_DEV is not set
423
424#
425# Digital Video Broadcasting Devices
426#
427# CONFIG_DVB is not set
428
429#
430# Graphics support
431#
432CONFIG_FB=y
433# CONFIG_FB_CFB_FILLRECT is not set
434# CONFIG_FB_CFB_COPYAREA is not set
435# CONFIG_FB_CFB_IMAGEBLIT is not set
436CONFIG_FB_SOFT_CURSOR=y
437# CONFIG_FB_MACMODES is not set
438CONFIG_FB_MODE_HELPERS=y
439# CONFIG_FB_TILEBLITTING is not set
440# CONFIG_FB_CIRRUS is not set
441CONFIG_FB_AMIGA=y
442CONFIG_FB_AMIGA_OCS=y
443CONFIG_FB_AMIGA_ECS=y
444CONFIG_FB_AMIGA_AGA=y
445# CONFIG_FB_FM2 is not set
446# CONFIG_FB_S1D13XXX is not set
447# CONFIG_FB_VIRTUAL is not set
448
449#
450# Console display driver support
451#
452CONFIG_DUMMY_CONSOLE=y
453# CONFIG_FRAMEBUFFER_CONSOLE is not set
454
455#
456# Logo configuration
457#
458# CONFIG_LOGO is not set
459# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
460
461#
462# Sound
463#
464# CONFIG_SOUND is not set
465
466#
467# USB support
468#
469# CONFIG_USB_ARCH_HAS_HCD is not set
470# CONFIG_USB_ARCH_HAS_OHCI is not set
471
472#
473# USB Gadget Support
474#
475# CONFIG_USB_GADGET is not set
476
477#
478# MMC/SD Card support
479#
480# CONFIG_MMC is not set
481
482#
483# InfiniBand support
484#
485# CONFIG_INFINIBAND is not set
486
487#
488# Character devices
489#
490CONFIG_AMIGA_BUILTIN_SERIAL=y
491# CONFIG_MULTIFACE_III_TTY is not set
492# CONFIG_GVPIOEXT is not set
493# CONFIG_SERIAL_CONSOLE is not set
494
495#
496# File systems
497#
498CONFIG_EXT2_FS=y
499# CONFIG_EXT2_FS_XATTR is not set
500# CONFIG_EXT3_FS is not set
501# CONFIG_JBD is not set
502# CONFIG_REISERFS_FS is not set
503# CONFIG_JFS_FS is not set
504
505#
506# XFS support
507#
508# CONFIG_XFS_FS is not set
509CONFIG_MINIX_FS=y
510# CONFIG_ROMFS_FS is not set
511# CONFIG_QUOTA is not set
512CONFIG_DNOTIFY=y
513# CONFIG_AUTOFS_FS is not set
514# CONFIG_AUTOFS4_FS is not set
515
516#
517# CD-ROM/DVD Filesystems
518#
519# CONFIG_ISO9660_FS is not set
520# CONFIG_UDF_FS is not set
521
522#
523# DOS/FAT/NT Filesystems
524#
525CONFIG_FAT_FS=y
526CONFIG_MSDOS_FS=y
527# CONFIG_VFAT_FS is not set
528CONFIG_FAT_DEFAULT_CODEPAGE=437
529# CONFIG_NTFS_FS is not set
530
531#
532# Pseudo filesystems
533#
534CONFIG_PROC_FS=y
535CONFIG_PROC_KCORE=y
536CONFIG_SYSFS=y
537# CONFIG_DEVFS_FS is not set
538# CONFIG_DEVPTS_FS_XATTR is not set
539# CONFIG_TMPFS is not set
540# CONFIG_HUGETLB_PAGE is not set
541CONFIG_RAMFS=y
542
543#
544# Miscellaneous filesystems
545#
546# CONFIG_ADFS_FS is not set
547# CONFIG_AFFS_FS is not set
548# CONFIG_HFS_FS is not set
549# CONFIG_HFSPLUS_FS is not set
550# CONFIG_BEFS_FS is not set
551# CONFIG_BFS_FS is not set
552# CONFIG_EFS_FS is not set
553# CONFIG_CRAMFS is not set
554# CONFIG_VXFS_FS is not set
555# CONFIG_HPFS_FS is not set
556# CONFIG_QNX4FS_FS is not set
557# CONFIG_SYSV_FS is not set
558# CONFIG_UFS_FS is not set
559
560#
561# Network File Systems
562#
563CONFIG_NFS_FS=y
564# CONFIG_NFS_V3 is not set
565# CONFIG_NFS_V4 is not set
566# CONFIG_NFS_DIRECTIO is not set
567# CONFIG_NFSD is not set
568CONFIG_LOCKD=y
569CONFIG_SUNRPC=y
570# CONFIG_RPCSEC_GSS_KRB5 is not set
571# CONFIG_RPCSEC_GSS_SPKM3 is not set
572# CONFIG_SMB_FS is not set
573# CONFIG_CIFS is not set
574# CONFIG_NCP_FS is not set
575# CONFIG_CODA_FS is not set
576# CONFIG_AFS_FS is not set
577
578#
579# Partition Types
580#
581# CONFIG_PARTITION_ADVANCED is not set
582CONFIG_AMIGA_PARTITION=y
583CONFIG_MSDOS_PARTITION=y
584
585#
586# Native Language Support
587#
588CONFIG_NLS=y
589CONFIG_NLS_DEFAULT="iso8859-1"
590CONFIG_NLS_CODEPAGE_437=y
591# CONFIG_NLS_CODEPAGE_737 is not set
592# CONFIG_NLS_CODEPAGE_775 is not set
593# CONFIG_NLS_CODEPAGE_850 is not set
594# CONFIG_NLS_CODEPAGE_852 is not set
595# CONFIG_NLS_CODEPAGE_855 is not set
596# CONFIG_NLS_CODEPAGE_857 is not set
597# CONFIG_NLS_CODEPAGE_860 is not set
598# CONFIG_NLS_CODEPAGE_861 is not set
599# CONFIG_NLS_CODEPAGE_862 is not set
600# CONFIG_NLS_CODEPAGE_863 is not set
601# CONFIG_NLS_CODEPAGE_864 is not set
602# CONFIG_NLS_CODEPAGE_865 is not set
603# CONFIG_NLS_CODEPAGE_866 is not set
604# CONFIG_NLS_CODEPAGE_869 is not set
605# CONFIG_NLS_CODEPAGE_936 is not set
606# CONFIG_NLS_CODEPAGE_950 is not set
607# CONFIG_NLS_CODEPAGE_932 is not set
608# CONFIG_NLS_CODEPAGE_949 is not set
609# CONFIG_NLS_CODEPAGE_874 is not set
610# CONFIG_NLS_ISO8859_8 is not set
611# CONFIG_NLS_CODEPAGE_1250 is not set
612# CONFIG_NLS_CODEPAGE_1251 is not set
613# CONFIG_NLS_ASCII is not set
614# CONFIG_NLS_ISO8859_1 is not set
615# CONFIG_NLS_ISO8859_2 is not set
616# CONFIG_NLS_ISO8859_3 is not set
617# CONFIG_NLS_ISO8859_4 is not set
618# CONFIG_NLS_ISO8859_5 is not set
619# CONFIG_NLS_ISO8859_6 is not set
620# CONFIG_NLS_ISO8859_7 is not set
621# CONFIG_NLS_ISO8859_9 is not set
622# CONFIG_NLS_ISO8859_13 is not set
623# CONFIG_NLS_ISO8859_14 is not set
624# CONFIG_NLS_ISO8859_15 is not set
625# CONFIG_NLS_KOI8_R is not set
626# CONFIG_NLS_KOI8_U is not set
627# CONFIG_NLS_UTF8 is not set
628
629#
630# Kernel hacking
631#
632# CONFIG_PRINTK_TIME is not set
633# CONFIG_DEBUG_KERNEL is not set
634CONFIG_LOG_BUF_SHIFT=14
635CONFIG_DEBUG_BUGVERBOSE=y
636
637#
638# Security options
639#
640# CONFIG_KEYS is not set
641# CONFIG_SECURITY is not set
642
643#
644# Cryptographic options
645#
646# CONFIG_CRYPTO is not set
647
648#
649# Hardware crypto devices
650#
651
652#
653# Library routines
654#
655# CONFIG_CRC_CCITT is not set
656CONFIG_CRC32=y
657# CONFIG_LIBCRC32C is not set
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 72097dacabd..1c62381f5c2 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -482,10 +482,13 @@ endif
482# be 16kb aligned or the handling of the current variable will break. 482# be 16kb aligned or the handling of the current variable will break.
483# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys 483# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
484# 484#
485#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o 485ifdef CONFIG_SGI_IP28
486 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n)
487 $(error gcc doesn't support needed option -mr10k-cache-barrier=1)
488 endif
489endif
486core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ 490core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
487cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28 491cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
488#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28
489load-$(CONFIG_SGI_IP28) += 0xa800000020004000 492load-$(CONFIG_SGI_IP28) += 0xa800000020004000
490 493
491# 494#
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
index d8df5fdb045..5c0d35d6e22 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/au1000/common/cputable.c
@@ -22,24 +22,24 @@ struct cpu_spec* cur_cpu_spec[NR_CPUS];
22/* With some thought, we can probably use the mask to reduce the 22/* With some thought, we can probably use the mask to reduce the
23 * size of the table. 23 * size of the table.
24 */ 24 */
25struct cpu_spec cpu_specs[] = { 25struct cpu_spec cpu_specs[] = {
26 { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 }, 26 { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
27 { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 }, 27 { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
28 { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 }, 28 { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
29 { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 }, 29 { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
30 { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 }, 30 { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
31 { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 }, 31 { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
32 { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 }, 32 { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
33 { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 }, 33 { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
34 { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 }, 34 { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
35 { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 }, 35 { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
36 { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 }, 36 { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 }, 37 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 }, 38 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 }, 39 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
40 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 }, 40 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
41 { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 }, 41 { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
42 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 }, 42 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
43}; 43};
44 44
45void 45void
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index d885e3848ec..9e4ab80caab 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -57,7 +57,7 @@ void __init plat_mem_setup(void)
57{ 57{
58 struct cpu_spec *sp; 58 struct cpu_spec *sp;
59 char *argptr; 59 char *argptr;
60 unsigned long prid, cpupll, bclk = 1; 60 unsigned long prid, cpufreq, bclk = 1;
61 61
62 set_cpuspec(); 62 set_cpuspec();
63 sp = cur_cpu_spec[0]; 63 sp = cur_cpu_spec[0];
@@ -65,8 +65,15 @@ void __init plat_mem_setup(void)
65 board_setup(); /* board specific setup */ 65 board_setup(); /* board specific setup */
66 66
67 prid = read_c0_prid(); 67 prid = read_c0_prid();
68 cpupll = (au_readl(0xB1900060) & 0x3F) * 12; 68 if (sp->cpu_pll_wo)
69 printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll); 69#ifdef CONFIG_SOC_AU1000_FREQUENCY
70 cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
71#else
72 cpufreq = 396;
73#endif
74 else
75 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
76 printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
70 77
71 bclk = sp->cpu_bclk; 78 bclk = sp->cpu_bclk;
72 if (bclk) 79 if (bclk)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index f113b512d7b..e122bbc6cd8 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -209,18 +209,22 @@ unsigned long cal_r4koff(void)
209 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 209 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
210 au_writel(0, SYS_TOYWRITE); 210 au_writel(0, SYS_TOYWRITE);
211 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 211 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
212 } else
213 no_au1xxx_32khz = 1;
212 214
213 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 215 /*
214 AU1000_SRC_CLK; 216 * On early Au1000, sys_cpupll was write-only. Since these
215 } 217 * silicon versions of Au1000 are not sold by AMD, we don't bend
216 else { 218 * over backwards trying to determine the frequency.
217 /* The 32KHz oscillator isn't running, so assume there 219 */
218 * isn't one and grab the processor speed from the PLL. 220 if (cur_cpu_spec[0]->cpu_pll_wo)
219 * NOTE: some old silicon doesn't allow reading the PLL. 221#ifdef CONFIG_SOC_AU1000_FREQUENCY
220 */ 222 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
223#else
224 cpu_speed = 396000000;
225#endif
226 else
221 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; 227 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
222 no_au1xxx_32khz = 1;
223 }
224 mips_hpt_frequency = cpu_speed; 228 mips_hpt_frequency = cpu_speed;
225 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) 229 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
226 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); 230 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index a9237f41933..b2e413e597a 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -33,11 +33,10 @@
33#include <asm/cpu.h> 33#include <asm/cpu.h>
34#include <asm/bootinfo.h> 34#include <asm/bootinfo.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <asm/keyboard.h>
37#include <asm/mipsregs.h> 36#include <asm/mipsregs.h>
38#include <asm/reboot.h> 37#include <asm/reboot.h>
39#include <asm/pgtable.h> 38#include <asm/pgtable.h>
40#include <asm/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
41 40
42void board_reset(void) 41void board_reset(void)
43{ 42{
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c
index 389349295d7..a343da13433 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/au1000/xxs1500/irqmap.c
@@ -45,7 +45,7 @@
45#include <asm/io.h> 45#include <asm/io.h>
46#include <asm/mipsregs.h> 46#include <asm/mipsregs.h>
47#include <asm/system.h> 47#include <asm/system.h>
48#include <asm/au1000.h> 48#include <asm/mach-au1x00/au1000.h>
49 49
50struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 50struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0}, 51 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index abf70d74e9d..3b42cea2e40 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -1,58 +1,48 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.25-rc7
4# Tue Feb 20 21:47:22 2007 4# Mon Mar 31 08:11:19 2008
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set 12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
26# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
29# CONFIG_MIPS_ATLAS is not set 19# CONFIG_MIPS_ATLAS is not set
30# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
31# CONFIG_MIPS_SEAD is not set 21# CONFIG_MIPS_SEAD is not set
32# CONFIG_WR_PPMC is not set
33# CONFIG_MIPS_SIM is not set 22# CONFIG_MIPS_SIM is not set
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 23# CONFIG_MARKEINS is not set
35# CONFIG_MIPS_XXS1500 is not set 24# CONFIG_MACH_VR41XX is not set
36# CONFIG_PNX8550_JBS is not set 25# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 26# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 27# CONFIG_PMC_MSP is not set
39# CONFIG_PMC_YOSEMITE is not set 28# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_MARKEINS is not set
41# CONFIG_SGI_IP22 is not set 29# CONFIG_SGI_IP22 is not set
42# CONFIG_SGI_IP27 is not set 30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
43# CONFIG_SGI_IP32 is not set 32# CONFIG_SGI_IP32 is not set
44CONFIG_SIBYTE_BIGSUR=y
45# CONFIG_SIBYTE_SWARM is not set
46# CONFIG_SIBYTE_SENTOSA is not set
47# CONFIG_SIBYTE_RHONE is not set
48# CONFIG_SIBYTE_CARMEL is not set
49# CONFIG_SIBYTE_LITTLESUR is not set
50# CONFIG_SIBYTE_CRHINE is not set 33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_CRHONE is not set 35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40CONFIG_SIBYTE_BIGSUR=y
52# CONFIG_SNI_RM is not set 41# CONFIG_SNI_RM is not set
53# CONFIG_TOSHIBA_JMR3927 is not set 42# CONFIG_TOSHIBA_JMR3927 is not set
54# CONFIG_TOSHIBA_RBTX4927 is not set 43# CONFIG_TOSHIBA_RBTX4927 is not set
55# CONFIG_TOSHIBA_RBTX4938 is not set 44# CONFIG_TOSHIBA_RBTX4938 is not set
45# CONFIG_WR_PPMC is not set
56CONFIG_SIBYTE_BCM1x80=y 46CONFIG_SIBYTE_BCM1x80=y
57CONFIG_SIBYTE_SB1xxx_SOC=y 47CONFIG_SIBYTE_SB1xxx_SOC=y
58# CONFIG_CPU_SB1_PASS_1 is not set 48# CONFIG_CPU_SB1_PASS_1 is not set
@@ -68,9 +58,11 @@ CONFIG_SIBYTE_CFE=y
68# CONFIG_SIBYTE_CFE_CONSOLE is not set 58# CONFIG_SIBYTE_CFE_CONSOLE is not set
69# CONFIG_SIBYTE_BUS_WATCHER is not set 59# CONFIG_SIBYTE_BUS_WATCHER is not set
70# CONFIG_SIBYTE_TBPROF is not set 60# CONFIG_SIBYTE_TBPROF is not set
61CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y
71CONFIG_RWSEM_GENERIC_SPINLOCK=y 62CONFIG_RWSEM_GENERIC_SPINLOCK=y
72# CONFIG_ARCH_HAS_ILOG2_U32 is not set 63# CONFIG_ARCH_HAS_ILOG2_U32 is not set
73# CONFIG_ARCH_HAS_ILOG2_U64 is not set 64# CONFIG_ARCH_HAS_ILOG2_U64 is not set
65CONFIG_ARCH_SUPPORTS_OPROFILE=y
74CONFIG_GENERIC_FIND_NEXT_BIT=y 66CONFIG_GENERIC_FIND_NEXT_BIT=y
75CONFIG_GENERIC_HWEIGHT=y 67CONFIG_GENERIC_HWEIGHT=y
76CONFIG_GENERIC_CALIBRATE_DELAY=y 68CONFIG_GENERIC_CALIBRATE_DELAY=y
@@ -81,11 +73,17 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
81# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 73# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
82CONFIG_CEVT_BCM1480=y 74CONFIG_CEVT_BCM1480=y
83CONFIG_CSRC_BCM1480=y 75CONFIG_CSRC_BCM1480=y
76CONFIG_CFE=y
84CONFIG_DMA_COHERENT=y 77CONFIG_DMA_COHERENT=y
78CONFIG_EARLY_PRINTK=y
79CONFIG_SYS_HAS_EARLY_PRINTK=y
80# CONFIG_HOTPLUG_CPU is not set
81# CONFIG_NO_IOPORT is not set
85CONFIG_CPU_BIG_ENDIAN=y 82CONFIG_CPU_BIG_ENDIAN=y
86# CONFIG_CPU_LITTLE_ENDIAN is not set 83# CONFIG_CPU_LITTLE_ENDIAN is not set
87CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 84CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
88CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 85CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
86CONFIG_IRQ_CPU=y
89CONFIG_SWAP_IO_SPACE=y 87CONFIG_SWAP_IO_SPACE=y
90CONFIG_BOOT_ELF32=y 88CONFIG_BOOT_ELF32=y
91CONFIG_MIPS_L1_CACHE_SHIFT=5 89CONFIG_MIPS_L1_CACHE_SHIFT=5
@@ -93,10 +91,6 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
93# 91#
94# CPU selection 92# CPU selection
95# 93#
96CONFIG_TICK_ONESHOT=y
97CONFIG_NO_HZ=y
98CONFIG_HIGH_RES_TIMERS=y
99CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
100# CONFIG_CPU_LOONGSON2 is not set 94# CONFIG_CPU_LOONGSON2 is not set
101# CONFIG_CPU_MIPS32_R1 is not set 95# CONFIG_CPU_MIPS32_R1 is not set
102# CONFIG_CPU_MIPS32_R2 is not set 96# CONFIG_CPU_MIPS32_R2 is not set
@@ -137,14 +131,15 @@ CONFIG_PAGE_SIZE_4KB=y
137CONFIG_MIPS_MT_DISABLED=y 131CONFIG_MIPS_MT_DISABLED=y
138# CONFIG_MIPS_MT_SMP is not set 132# CONFIG_MIPS_MT_SMP is not set
139# CONFIG_MIPS_MT_SMTC is not set 133# CONFIG_MIPS_MT_SMTC is not set
140# CONFIG_MIPS_VPE_LOADER is not set
141CONFIG_CPU_HAS_LLSC=y 134CONFIG_CPU_HAS_LLSC=y
142CONFIG_CPU_HAS_SYNC=y 135CONFIG_CPU_HAS_SYNC=y
143CONFIG_GENERIC_HARDIRQS=y 136CONFIG_GENERIC_HARDIRQS=y
144CONFIG_GENERIC_IRQ_PROBE=y 137CONFIG_GENERIC_IRQ_PROBE=y
145CONFIG_IRQ_PER_CPU=y 138CONFIG_IRQ_PER_CPU=y
146CONFIG_CPU_SUPPORTS_HIGHMEM=y 139CONFIG_CPU_SUPPORTS_HIGHMEM=y
140CONFIG_SYS_SUPPORTS_HIGHMEM=y
147CONFIG_ARCH_FLATMEM_ENABLE=y 141CONFIG_ARCH_FLATMEM_ENABLE=y
142CONFIG_ARCH_POPULATES_NODE_MAP=y
148CONFIG_SELECT_MEMORY_MODEL=y 143CONFIG_SELECT_MEMORY_MODEL=y
149CONFIG_FLATMEM_MANUAL=y 144CONFIG_FLATMEM_MANUAL=y
150# CONFIG_DISCONTIGMEM_MANUAL is not set 145# CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -152,13 +147,19 @@ CONFIG_FLATMEM_MANUAL=y
152CONFIG_FLATMEM=y 147CONFIG_FLATMEM=y
153CONFIG_FLAT_NODE_MEM_MAP=y 148CONFIG_FLAT_NODE_MEM_MAP=y
154# CONFIG_SPARSEMEM_STATIC is not set 149# CONFIG_SPARSEMEM_STATIC is not set
150# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
155CONFIG_SPLIT_PTLOCK_CPUS=4 151CONFIG_SPLIT_PTLOCK_CPUS=4
156CONFIG_RESOURCES_64BIT=y 152CONFIG_RESOURCES_64BIT=y
157CONFIG_ZONE_DMA_FLAG=1 153CONFIG_ZONE_DMA_FLAG=0
154CONFIG_VIRT_TO_BUS=y
158CONFIG_SMP=y 155CONFIG_SMP=y
159CONFIG_SYS_SUPPORTS_SMP=y 156CONFIG_SYS_SUPPORTS_SMP=y
160CONFIG_NR_CPUS_DEFAULT_4=y 157CONFIG_NR_CPUS_DEFAULT_4=y
161CONFIG_NR_CPUS=4 158CONFIG_NR_CPUS=4
159CONFIG_TICK_ONESHOT=y
160CONFIG_NO_HZ=y
161CONFIG_HIGH_RES_TIMERS=y
162CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
162# CONFIG_HZ_48 is not set 163# CONFIG_HZ_48 is not set
163# CONFIG_HZ_100 is not set 164# CONFIG_HZ_100 is not set
164# CONFIG_HZ_128 is not set 165# CONFIG_HZ_128 is not set
@@ -171,38 +172,45 @@ CONFIG_HZ=1000
171CONFIG_PREEMPT_NONE=y 172CONFIG_PREEMPT_NONE=y
172# CONFIG_PREEMPT_VOLUNTARY is not set 173# CONFIG_PREEMPT_VOLUNTARY is not set
173# CONFIG_PREEMPT is not set 174# CONFIG_PREEMPT is not set
174# CONFIG_PREEMPT_BKL is not set
175# CONFIG_KEXEC is not set 175# CONFIG_KEXEC is not set
176CONFIG_SECCOMP=y
176CONFIG_LOCKDEP_SUPPORT=y 177CONFIG_LOCKDEP_SUPPORT=y
177CONFIG_STACKTRACE_SUPPORT=y 178CONFIG_STACKTRACE_SUPPORT=y
178CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 179CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
179 180
180# 181#
181# Code maturity level options 182# General setup
182# 183#
183CONFIG_EXPERIMENTAL=y 184CONFIG_EXPERIMENTAL=y
184CONFIG_LOCK_KERNEL=y 185CONFIG_LOCK_KERNEL=y
185CONFIG_INIT_ENV_ARG_LIMIT=32 186CONFIG_INIT_ENV_ARG_LIMIT=32
186
187#
188# General setup
189#
190CONFIG_LOCALVERSION="" 187CONFIG_LOCALVERSION=""
191CONFIG_LOCALVERSION_AUTO=y 188CONFIG_LOCALVERSION_AUTO=y
192CONFIG_SWAP=y 189CONFIG_SWAP=y
193CONFIG_SYSVIPC=y 190CONFIG_SYSVIPC=y
194# CONFIG_IPC_NS is not set
195CONFIG_SYSVIPC_SYSCTL=y 191CONFIG_SYSVIPC_SYSCTL=y
196# CONFIG_POSIX_MQUEUE is not set 192CONFIG_POSIX_MQUEUE=y
197# CONFIG_BSD_PROCESS_ACCT is not set 193CONFIG_BSD_PROCESS_ACCT=y
198# CONFIG_TASKSTATS is not set 194CONFIG_BSD_PROCESS_ACCT_V3=y
199# CONFIG_UTS_NS is not set 195CONFIG_TASKSTATS=y
200# CONFIG_AUDIT is not set 196CONFIG_TASK_DELAY_ACCT=y
197CONFIG_TASK_XACCT=y
198CONFIG_TASK_IO_ACCOUNTING=y
199CONFIG_AUDIT=y
201CONFIG_IKCONFIG=y 200CONFIG_IKCONFIG=y
202CONFIG_IKCONFIG_PROC=y 201CONFIG_IKCONFIG_PROC=y
203# CONFIG_CPUSETS is not set 202CONFIG_LOG_BUF_SHIFT=16
203# CONFIG_CGROUPS is not set
204CONFIG_GROUP_SCHED=y
205CONFIG_FAIR_GROUP_SCHED=y
206# CONFIG_RT_GROUP_SCHED is not set
207CONFIG_USER_SCHED=y
208# CONFIG_CGROUP_SCHED is not set
204CONFIG_SYSFS_DEPRECATED=y 209CONFIG_SYSFS_DEPRECATED=y
205# CONFIG_RELAY is not set 210CONFIG_SYSFS_DEPRECATED_V2=y
211CONFIG_RELAY=y
212# CONFIG_NAMESPACES is not set
213CONFIG_BLK_DEV_INITRD=y
206CONFIG_INITRAMFS_SOURCE="" 214CONFIG_INITRAMFS_SOURCE=""
207# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 215# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
208CONFIG_SYSCTL=y 216CONFIG_SYSCTL=y
@@ -211,24 +219,33 @@ CONFIG_EMBEDDED=y
211CONFIG_KALLSYMS=y 219CONFIG_KALLSYMS=y
212# CONFIG_KALLSYMS_ALL is not set 220# CONFIG_KALLSYMS_ALL is not set
213# CONFIG_KALLSYMS_EXTRA_PASS is not set 221# CONFIG_KALLSYMS_EXTRA_PASS is not set
214# CONFIG_HOTPLUG is not set 222CONFIG_HOTPLUG=y
215CONFIG_PRINTK=y 223CONFIG_PRINTK=y
216CONFIG_BUG=y 224CONFIG_BUG=y
217CONFIG_ELF_CORE=y 225CONFIG_ELF_CORE=y
226CONFIG_COMPAT_BRK=y
218CONFIG_BASE_FULL=y 227CONFIG_BASE_FULL=y
219CONFIG_FUTEX=y 228CONFIG_FUTEX=y
229CONFIG_ANON_INODES=y
220CONFIG_EPOLL=y 230CONFIG_EPOLL=y
231CONFIG_SIGNALFD=y
232CONFIG_TIMERFD=y
233CONFIG_EVENTFD=y
221CONFIG_SHMEM=y 234CONFIG_SHMEM=y
222CONFIG_SLAB=y
223CONFIG_VM_EVENT_COUNTERS=y 235CONFIG_VM_EVENT_COUNTERS=y
236CONFIG_SLAB=y
237# CONFIG_SLUB is not set
238# CONFIG_SLOB is not set
239# CONFIG_PROFILING is not set
240# CONFIG_MARKERS is not set
241CONFIG_HAVE_OPROFILE=y
242# CONFIG_HAVE_KPROBES is not set
243# CONFIG_HAVE_KRETPROBES is not set
244CONFIG_PROC_PAGE_MONITOR=y
245CONFIG_SLABINFO=y
224CONFIG_RT_MUTEXES=y 246CONFIG_RT_MUTEXES=y
225# CONFIG_TINY_SHMEM is not set 247# CONFIG_TINY_SHMEM is not set
226CONFIG_BASE_SMALL=0 248CONFIG_BASE_SMALL=0
227# CONFIG_SLOB is not set
228
229#
230# Loadable module support
231#
232CONFIG_MODULES=y 249CONFIG_MODULES=y
233CONFIG_MODULE_UNLOAD=y 250CONFIG_MODULE_UNLOAD=y
234# CONFIG_MODULE_FORCE_UNLOAD is not set 251# CONFIG_MODULE_FORCE_UNLOAD is not set
@@ -236,12 +253,10 @@ CONFIG_MODVERSIONS=y
236CONFIG_MODULE_SRCVERSION_ALL=y 253CONFIG_MODULE_SRCVERSION_ALL=y
237CONFIG_KMOD=y 254CONFIG_KMOD=y
238CONFIG_STOP_MACHINE=y 255CONFIG_STOP_MACHINE=y
239
240#
241# Block layer
242#
243CONFIG_BLOCK=y 256CONFIG_BLOCK=y
244# CONFIG_BLK_DEV_IO_TRACE is not set 257# CONFIG_BLK_DEV_IO_TRACE is not set
258# CONFIG_BLK_DEV_BSG is not set
259CONFIG_BLOCK_COMPAT=y
245 260
246# 261#
247# IO Schedulers 262# IO Schedulers
@@ -255,6 +270,7 @@ CONFIG_DEFAULT_AS=y
255# CONFIG_DEFAULT_CFQ is not set 270# CONFIG_DEFAULT_CFQ is not set
256# CONFIG_DEFAULT_NOOP is not set 271# CONFIG_DEFAULT_NOOP is not set
257CONFIG_DEFAULT_IOSCHED="anticipatory" 272CONFIG_DEFAULT_IOSCHED="anticipatory"
273CONFIG_CLASSIC_RCU=y
258 274
259# 275#
260# Bus options (PCI, PCMCIA, EISA, ISA, TC) 276# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -262,23 +278,19 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
262CONFIG_HW_HAS_PCI=y 278CONFIG_HW_HAS_PCI=y
263CONFIG_PCI=y 279CONFIG_PCI=y
264CONFIG_PCI_DOMAINS=y 280CONFIG_PCI_DOMAINS=y
281# CONFIG_ARCH_SUPPORTS_MSI is not set
282CONFIG_PCI_LEGACY=y
265CONFIG_PCI_DEBUG=y 283CONFIG_PCI_DEBUG=y
266CONFIG_MMU=y 284CONFIG_MMU=y
267 285CONFIG_ZONE_DMA32=y
268# 286# CONFIG_PCCARD is not set
269# PCCARD (PCMCIA/CardBus) support 287# CONFIG_HOTPLUG_PCI is not set
270#
271
272#
273# PCI Hotplug Support
274#
275 288
276# 289#
277# Executable file formats 290# Executable file formats
278# 291#
279CONFIG_BINFMT_ELF=y 292CONFIG_BINFMT_ELF=y
280# CONFIG_BINFMT_MISC is not set 293# CONFIG_BINFMT_MISC is not set
281# CONFIG_BUILD_ELF64 is not set
282CONFIG_MIPS32_COMPAT=y 294CONFIG_MIPS32_COMPAT=y
283CONFIG_COMPAT=y 295CONFIG_COMPAT=y
284CONFIG_SYSVIPC_COMPAT=y 296CONFIG_SYSVIPC_COMPAT=y
@@ -292,7 +304,6 @@ CONFIG_BINFMT_ELF32=y
292CONFIG_PM=y 304CONFIG_PM=y
293# CONFIG_PM_LEGACY is not set 305# CONFIG_PM_LEGACY is not set
294# CONFIG_PM_DEBUG is not set 306# CONFIG_PM_DEBUG is not set
295# CONFIG_PM_SYSFS_DEPRECATED is not set
296 307
297# 308#
298# Networking 309# Networking
@@ -302,7 +313,6 @@ CONFIG_NET=y
302# 313#
303# Networking options 314# Networking options
304# 315#
305# CONFIG_NETDEBUG is not set
306CONFIG_PACKET=y 316CONFIG_PACKET=y
307CONFIG_PACKET_MMAP=y 317CONFIG_PACKET_MMAP=y
308CONFIG_UNIX=y 318CONFIG_UNIX=y
@@ -310,10 +320,11 @@ CONFIG_XFRM=y
310CONFIG_XFRM_USER=m 320CONFIG_XFRM_USER=m
311# CONFIG_XFRM_SUB_POLICY is not set 321# CONFIG_XFRM_SUB_POLICY is not set
312CONFIG_XFRM_MIGRATE=y 322CONFIG_XFRM_MIGRATE=y
323# CONFIG_XFRM_STATISTICS is not set
313CONFIG_NET_KEY=y 324CONFIG_NET_KEY=y
314CONFIG_NET_KEY_MIGRATE=y 325CONFIG_NET_KEY_MIGRATE=y
315CONFIG_INET=y 326CONFIG_INET=y
316# CONFIG_IP_MULTICAST is not set 327CONFIG_IP_MULTICAST=y
317# CONFIG_IP_ADVANCED_ROUTER is not set 328# CONFIG_IP_ADVANCED_ROUTER is not set
318CONFIG_IP_FIB_HASH=y 329CONFIG_IP_FIB_HASH=y
319CONFIG_IP_PNP=y 330CONFIG_IP_PNP=y
@@ -322,41 +333,141 @@ CONFIG_IP_PNP_BOOTP=y
322# CONFIG_IP_PNP_RARP is not set 333# CONFIG_IP_PNP_RARP is not set
323# CONFIG_NET_IPIP is not set 334# CONFIG_NET_IPIP is not set
324# CONFIG_NET_IPGRE is not set 335# CONFIG_NET_IPGRE is not set
336CONFIG_IP_MROUTE=y
337CONFIG_IP_PIMSM_V1=y
338CONFIG_IP_PIMSM_V2=y
325# CONFIG_ARPD is not set 339# CONFIG_ARPD is not set
326# CONFIG_SYN_COOKIES is not set 340# CONFIG_SYN_COOKIES is not set
327# CONFIG_INET_AH is not set 341CONFIG_INET_AH=m
328# CONFIG_INET_ESP is not set 342CONFIG_INET_ESP=m
329# CONFIG_INET_IPCOMP is not set 343CONFIG_INET_IPCOMP=m
330# CONFIG_INET_XFRM_TUNNEL is not set 344CONFIG_INET_XFRM_TUNNEL=m
331# CONFIG_INET_TUNNEL is not set 345CONFIG_INET_TUNNEL=m
332CONFIG_INET_XFRM_MODE_TRANSPORT=m 346CONFIG_INET_XFRM_MODE_TRANSPORT=m
333CONFIG_INET_XFRM_MODE_TUNNEL=m 347CONFIG_INET_XFRM_MODE_TUNNEL=m
334CONFIG_INET_XFRM_MODE_BEET=y 348CONFIG_INET_XFRM_MODE_BEET=y
349# CONFIG_INET_LRO is not set
335CONFIG_INET_DIAG=y 350CONFIG_INET_DIAG=y
336CONFIG_INET_TCP_DIAG=y 351CONFIG_INET_TCP_DIAG=y
337# CONFIG_TCP_CONG_ADVANCED is not set 352# CONFIG_TCP_CONG_ADVANCED is not set
338CONFIG_TCP_CONG_CUBIC=y 353CONFIG_TCP_CONG_CUBIC=y
339CONFIG_DEFAULT_TCP_CONG="cubic" 354CONFIG_DEFAULT_TCP_CONG="cubic"
340CONFIG_TCP_MD5SIG=y 355CONFIG_TCP_MD5SIG=y
341# CONFIG_IPV6 is not set 356CONFIG_IP_VS=m
342# CONFIG_INET6_XFRM_TUNNEL is not set 357# CONFIG_IP_VS_DEBUG is not set
343# CONFIG_INET6_TUNNEL is not set 358CONFIG_IP_VS_TAB_BITS=12
359
360#
361# IPVS transport protocol load balancing support
362#
363CONFIG_IP_VS_PROTO_TCP=y
364CONFIG_IP_VS_PROTO_UDP=y
365CONFIG_IP_VS_PROTO_ESP=y
366CONFIG_IP_VS_PROTO_AH=y
367
368#
369# IPVS scheduler
370#
371CONFIG_IP_VS_RR=m
372CONFIG_IP_VS_WRR=m
373CONFIG_IP_VS_LC=m
374CONFIG_IP_VS_WLC=m
375CONFIG_IP_VS_LBLC=m
376CONFIG_IP_VS_LBLCR=m
377CONFIG_IP_VS_DH=m
378CONFIG_IP_VS_SH=m
379CONFIG_IP_VS_SED=m
380CONFIG_IP_VS_NQ=m
381
382#
383# IPVS application helper
384#
385CONFIG_IP_VS_FTP=m
386CONFIG_IPV6=m
387CONFIG_IPV6_PRIVACY=y
388CONFIG_IPV6_ROUTER_PREF=y
389CONFIG_IPV6_ROUTE_INFO=y
390CONFIG_IPV6_OPTIMISTIC_DAD=y
391CONFIG_INET6_AH=m
392CONFIG_INET6_ESP=m
393CONFIG_INET6_IPCOMP=m
394CONFIG_IPV6_MIP6=m
395CONFIG_INET6_XFRM_TUNNEL=m
396CONFIG_INET6_TUNNEL=m
397CONFIG_INET6_XFRM_MODE_TRANSPORT=m
398CONFIG_INET6_XFRM_MODE_TUNNEL=m
399CONFIG_INET6_XFRM_MODE_BEET=m
400CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
401CONFIG_IPV6_SIT=m
402CONFIG_IPV6_TUNNEL=m
403CONFIG_IPV6_MULTIPLE_TABLES=y
404CONFIG_IPV6_SUBTREES=y
344CONFIG_NETWORK_SECMARK=y 405CONFIG_NETWORK_SECMARK=y
345# CONFIG_NETFILTER is not set 406CONFIG_NETFILTER=y
346 407# CONFIG_NETFILTER_DEBUG is not set
347# 408# CONFIG_NETFILTER_ADVANCED is not set
348# DCCP Configuration (EXPERIMENTAL) 409
349# 410#
411# Core Netfilter Configuration
412#
413CONFIG_NETFILTER_NETLINK=m
414CONFIG_NETFILTER_NETLINK_LOG=m
415CONFIG_NF_CONNTRACK=m
416CONFIG_NF_CONNTRACK_SECMARK=y
417CONFIG_NF_CONNTRACK_FTP=m
418CONFIG_NF_CONNTRACK_IRC=m
419CONFIG_NF_CONNTRACK_SIP=m
420CONFIG_NF_CT_NETLINK=m
421CONFIG_NETFILTER_XTABLES=m
422CONFIG_NETFILTER_XT_TARGET_MARK=m
423CONFIG_NETFILTER_XT_TARGET_NFLOG=m
424CONFIG_NETFILTER_XT_TARGET_SECMARK=m
425CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
426CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
427CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
428CONFIG_NETFILTER_XT_MATCH_MARK=m
429CONFIG_NETFILTER_XT_MATCH_POLICY=m
430CONFIG_NETFILTER_XT_MATCH_STATE=m
431
432#
433# IP: Netfilter Configuration
434#
435CONFIG_NF_CONNTRACK_IPV4=m
436CONFIG_NF_CONNTRACK_PROC_COMPAT=y
437CONFIG_IP_NF_IPTABLES=m
438CONFIG_IP_NF_FILTER=m
439CONFIG_IP_NF_TARGET_REJECT=m
440CONFIG_IP_NF_TARGET_LOG=m
441CONFIG_IP_NF_TARGET_ULOG=m
442CONFIG_NF_NAT=m
443CONFIG_NF_NAT_NEEDED=y
444CONFIG_IP_NF_TARGET_MASQUERADE=m
445CONFIG_NF_NAT_FTP=m
446CONFIG_NF_NAT_IRC=m
447# CONFIG_NF_NAT_TFTP is not set
448# CONFIG_NF_NAT_AMANDA is not set
449# CONFIG_NF_NAT_PPTP is not set
450# CONFIG_NF_NAT_H323 is not set
451CONFIG_NF_NAT_SIP=m
452CONFIG_IP_NF_MANGLE=m
453
454#
455# IPv6: Netfilter Configuration
456#
457CONFIG_NF_CONNTRACK_IPV6=m
458CONFIG_IP6_NF_IPTABLES=m
459CONFIG_IP6_NF_MATCH_IPV6HEADER=m
460CONFIG_IP6_NF_FILTER=m
461CONFIG_IP6_NF_TARGET_LOG=m
462CONFIG_IP6_NF_TARGET_REJECT=m
463CONFIG_IP6_NF_MANGLE=m
350# CONFIG_IP_DCCP is not set 464# CONFIG_IP_DCCP is not set
351 465CONFIG_IP_SCTP=m
352# 466# CONFIG_SCTP_DBG_MSG is not set
353# SCTP Configuration (EXPERIMENTAL) 467# CONFIG_SCTP_DBG_OBJCNT is not set
354# 468# CONFIG_SCTP_HMAC_NONE is not set
355# CONFIG_IP_SCTP is not set 469# CONFIG_SCTP_HMAC_SHA1 is not set
356 470CONFIG_SCTP_HMAC_MD5=y
357#
358# TIPC Configuration (EXPERIMENTAL)
359#
360# CONFIG_TIPC is not set 471# CONFIG_TIPC is not set
361# CONFIG_ATM is not set 472# CONFIG_ATM is not set
362# CONFIG_BRIDGE is not set 473# CONFIG_BRIDGE is not set
@@ -369,10 +480,6 @@ CONFIG_NETWORK_SECMARK=y
369# CONFIG_LAPB is not set 480# CONFIG_LAPB is not set
370# CONFIG_ECONET is not set 481# CONFIG_ECONET is not set
371# CONFIG_WAN_ROUTER is not set 482# CONFIG_WAN_ROUTER is not set
372
373#
374# QoS and/or fair queueing
375#
376# CONFIG_NET_SCHED is not set 483# CONFIG_NET_SCHED is not set
377 484
378# 485#
@@ -380,9 +487,21 @@ CONFIG_NETWORK_SECMARK=y
380# 487#
381# CONFIG_NET_PKTGEN is not set 488# CONFIG_NET_PKTGEN is not set
382# CONFIG_HAMRADIO is not set 489# CONFIG_HAMRADIO is not set
490# CONFIG_CAN is not set
383# CONFIG_IRDA is not set 491# CONFIG_IRDA is not set
384# CONFIG_BT is not set 492# CONFIG_BT is not set
493# CONFIG_AF_RXRPC is not set
494CONFIG_FIB_RULES=y
495
496#
497# Wireless
498#
499# CONFIG_CFG80211 is not set
500# CONFIG_WIRELESS_EXT is not set
501# CONFIG_MAC80211 is not set
385# CONFIG_IEEE80211 is not set 502# CONFIG_IEEE80211 is not set
503# CONFIG_RFKILL is not set
504# CONFIG_NET_9P is not set
386 505
387# 506#
388# Device Drivers 507# Device Drivers
@@ -391,85 +510,70 @@ CONFIG_NETWORK_SECMARK=y
391# 510#
392# Generic Driver Options 511# Generic Driver Options
393# 512#
513CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
394CONFIG_STANDALONE=y 514CONFIG_STANDALONE=y
395CONFIG_PREVENT_FIRMWARE_BUILD=y 515CONFIG_PREVENT_FIRMWARE_BUILD=y
516CONFIG_FW_LOADER=m
396# CONFIG_DEBUG_DRIVER is not set 517# CONFIG_DEBUG_DRIVER is not set
397# CONFIG_DEBUG_DEVRES is not set 518# CONFIG_DEBUG_DEVRES is not set
398# CONFIG_SYS_HYPERVISOR is not set 519# CONFIG_SYS_HYPERVISOR is not set
399
400#
401# Connector - unified userspace <-> kernelspace linker
402#
403# CONFIG_CONNECTOR is not set 520# CONFIG_CONNECTOR is not set
404
405#
406# Memory Technology Devices (MTD)
407#
408# CONFIG_MTD is not set 521# CONFIG_MTD is not set
409
410#
411# Parallel port support
412#
413# CONFIG_PARPORT is not set 522# CONFIG_PARPORT is not set
414 523CONFIG_BLK_DEV=y
415#
416# Plug and Play support
417#
418# CONFIG_PNPACPI is not set
419
420#
421# Block devices
422#
423# CONFIG_BLK_CPQ_DA is not set 524# CONFIG_BLK_CPQ_DA is not set
424# CONFIG_BLK_CPQ_CISS_DA is not set 525# CONFIG_BLK_CPQ_CISS_DA is not set
425# CONFIG_BLK_DEV_DAC960 is not set 526# CONFIG_BLK_DEV_DAC960 is not set
426# CONFIG_BLK_DEV_UMEM is not set 527# CONFIG_BLK_DEV_UMEM is not set
427# CONFIG_BLK_DEV_COW_COMMON is not set 528# CONFIG_BLK_DEV_COW_COMMON is not set
428CONFIG_BLK_DEV_LOOP=m 529CONFIG_BLK_DEV_LOOP=m
429# CONFIG_BLK_DEV_CRYPTOLOOP is not set 530CONFIG_BLK_DEV_CRYPTOLOOP=m
430CONFIG_BLK_DEV_NBD=m 531CONFIG_BLK_DEV_NBD=m
431# CONFIG_BLK_DEV_SX8 is not set 532# CONFIG_BLK_DEV_SX8 is not set
432# CONFIG_BLK_DEV_RAM is not set 533# CONFIG_BLK_DEV_RAM is not set
433CONFIG_BLK_DEV_INITRD=y
434# CONFIG_CDROM_PKTCDVD is not set 534# CONFIG_CDROM_PKTCDVD is not set
435# CONFIG_ATA_OVER_ETH is not set 535# CONFIG_ATA_OVER_ETH is not set
436 536CONFIG_MISC_DEVICES=y
437# 537# CONFIG_PHANTOM is not set
438# Misc devices 538# CONFIG_EEPROM_93CX6 is not set
439#
440CONFIG_SGI_IOC4=m 539CONFIG_SGI_IOC4=m
441# CONFIG_TIFM_CORE is not set 540# CONFIG_TIFM_CORE is not set
442 541# CONFIG_ENCLOSURE_SERVICES is not set
443# 542CONFIG_HAVE_IDE=y
444# ATA/ATAPI/MFM/RLL support
445#
446CONFIG_IDE=y 543CONFIG_IDE=y
447CONFIG_IDE_MAX_HWIFS=4 544CONFIG_IDE_MAX_HWIFS=4
448CONFIG_BLK_DEV_IDE=y 545CONFIG_BLK_DEV_IDE=y
449 546
450# 547#
451# Please see Documentation/ide.txt for help/info on IDE drives 548# Please see Documentation/ide/ide.txt for help/info on IDE drives
452# 549#
453# CONFIG_BLK_DEV_IDE_SATA is not set 550# CONFIG_BLK_DEV_IDE_SATA is not set
454CONFIG_BLK_DEV_IDEDISK=y 551CONFIG_BLK_DEV_IDEDISK=y
455# CONFIG_IDEDISK_MULTI_MODE is not set 552# CONFIG_IDEDISK_MULTI_MODE is not set
456CONFIG_BLK_DEV_IDECD=y 553CONFIG_BLK_DEV_IDECD=y
554CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
457CONFIG_BLK_DEV_IDETAPE=y 555CONFIG_BLK_DEV_IDETAPE=y
458CONFIG_BLK_DEV_IDEFLOPPY=y 556CONFIG_BLK_DEV_IDEFLOPPY=y
557# CONFIG_BLK_DEV_IDESCSI is not set
459# CONFIG_IDE_TASK_IOCTL is not set 558# CONFIG_IDE_TASK_IOCTL is not set
559CONFIG_IDE_PROC_FS=y
460 560
461# 561#
462# IDE chipset support/bugfixes 562# IDE chipset support/bugfixes
463# 563#
464CONFIG_IDE_GENERIC=y 564CONFIG_IDE_GENERIC=y
565# CONFIG_BLK_DEV_PLATFORM is not set
566CONFIG_BLK_DEV_IDEDMA_SFF=y
567
568#
569# PCI IDE chipsets support
570#
465CONFIG_BLK_DEV_IDEPCI=y 571CONFIG_BLK_DEV_IDEPCI=y
466# CONFIG_IDEPCI_SHARE_IRQ is not set 572CONFIG_IDEPCI_PCIBUS_ORDER=y
467# CONFIG_BLK_DEV_OFFBOARD is not set 573# CONFIG_BLK_DEV_OFFBOARD is not set
468CONFIG_BLK_DEV_GENERIC=y 574CONFIG_BLK_DEV_GENERIC=y
469# CONFIG_BLK_DEV_OPTI621 is not set 575# CONFIG_BLK_DEV_OPTI621 is not set
470CONFIG_BLK_DEV_IDEDMA_PCI=y 576CONFIG_BLK_DEV_IDEDMA_PCI=y
471# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
472# CONFIG_IDEDMA_PCI_AUTO is not set
473# CONFIG_BLK_DEV_AEC62XX is not set 577# CONFIG_BLK_DEV_AEC62XX is not set
474# CONFIG_BLK_DEV_ALI15X3 is not set 578# CONFIG_BLK_DEV_ALI15X3 is not set
475# CONFIG_BLK_DEV_AMD74XX is not set 579# CONFIG_BLK_DEV_AMD74XX is not set
@@ -495,87 +599,196 @@ CONFIG_BLK_DEV_IT8213=m
495# CONFIG_BLK_DEV_VIA82CXXX is not set 599# CONFIG_BLK_DEV_VIA82CXXX is not set
496CONFIG_BLK_DEV_TC86C001=m 600CONFIG_BLK_DEV_TC86C001=m
497# CONFIG_BLK_DEV_IDE_SWARM is not set 601# CONFIG_BLK_DEV_IDE_SWARM is not set
498# CONFIG_IDE_ARM is not set
499CONFIG_BLK_DEV_IDEDMA=y 602CONFIG_BLK_DEV_IDEDMA=y
500# CONFIG_IDEDMA_IVB is not set 603CONFIG_IDE_ARCH_OBSOLETE_INIT=y
501# CONFIG_IDEDMA_AUTO is not set
502# CONFIG_BLK_DEV_HD is not set 604# CONFIG_BLK_DEV_HD is not set
503 605
504# 606#
505# SCSI device support 607# SCSI device support
506# 608#
507# CONFIG_RAID_ATTRS is not set 609# CONFIG_RAID_ATTRS is not set
508# CONFIG_SCSI is not set 610CONFIG_SCSI=y
611CONFIG_SCSI_DMA=y
612# CONFIG_SCSI_TGT is not set
509# CONFIG_SCSI_NETLINK is not set 613# CONFIG_SCSI_NETLINK is not set
510 614CONFIG_SCSI_PROC_FS=y
511# 615
512# Serial ATA (prod) and Parallel ATA (experimental) drivers 616#
513# 617# SCSI support type (disk, tape, CD-ROM)
514# CONFIG_ATA is not set 618#
515 619CONFIG_BLK_DEV_SD=y
516# 620# CONFIG_CHR_DEV_ST is not set
517# Multi-device support (RAID and LVM) 621# CONFIG_CHR_DEV_OSST is not set
518# 622# CONFIG_BLK_DEV_SR is not set
623# CONFIG_CHR_DEV_SG is not set
624# CONFIG_CHR_DEV_SCH is not set
625
626#
627# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
628#
629# CONFIG_SCSI_MULTI_LUN is not set
630# CONFIG_SCSI_CONSTANTS is not set
631# CONFIG_SCSI_LOGGING is not set
632# CONFIG_SCSI_SCAN_ASYNC is not set
633CONFIG_SCSI_WAIT_SCAN=m
634
635#
636# SCSI Transports
637#
638# CONFIG_SCSI_SPI_ATTRS is not set
639# CONFIG_SCSI_FC_ATTRS is not set
640# CONFIG_SCSI_ISCSI_ATTRS is not set
641# CONFIG_SCSI_SAS_LIBSAS is not set
642# CONFIG_SCSI_SRP_ATTRS is not set
643CONFIG_SCSI_LOWLEVEL=y
644# CONFIG_ISCSI_TCP is not set
645# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
646# CONFIG_SCSI_3W_9XXX is not set
647# CONFIG_SCSI_ACARD is not set
648# CONFIG_SCSI_AACRAID is not set
649# CONFIG_SCSI_AIC7XXX is not set
650# CONFIG_SCSI_AIC7XXX_OLD is not set
651# CONFIG_SCSI_AIC79XX is not set
652# CONFIG_SCSI_AIC94XX is not set
653# CONFIG_SCSI_ADVANSYS is not set
654# CONFIG_SCSI_ARCMSR is not set
655# CONFIG_MEGARAID_NEWGEN is not set
656# CONFIG_MEGARAID_LEGACY is not set
657# CONFIG_MEGARAID_SAS is not set
658# CONFIG_SCSI_HPTIOP is not set
659# CONFIG_SCSI_DMX3191D is not set
660# CONFIG_SCSI_FUTURE_DOMAIN is not set
661# CONFIG_SCSI_IPS is not set
662# CONFIG_SCSI_INITIO is not set
663# CONFIG_SCSI_INIA100 is not set
664# CONFIG_SCSI_MVSAS is not set
665# CONFIG_SCSI_STEX is not set
666# CONFIG_SCSI_SYM53C8XX_2 is not set
667# CONFIG_SCSI_IPR is not set
668# CONFIG_SCSI_QLOGIC_1280 is not set
669# CONFIG_SCSI_QLA_FC is not set
670# CONFIG_SCSI_QLA_ISCSI is not set
671# CONFIG_SCSI_LPFC is not set
672# CONFIG_SCSI_DC395x is not set
673# CONFIG_SCSI_DC390T is not set
674# CONFIG_SCSI_DEBUG is not set
675# CONFIG_SCSI_SRP is not set
676CONFIG_ATA=y
677# CONFIG_ATA_NONSTANDARD is not set
678# CONFIG_SATA_AHCI is not set
679# CONFIG_SATA_SVW is not set
680# CONFIG_ATA_PIIX is not set
681# CONFIG_SATA_MV is not set
682# CONFIG_SATA_NV is not set
683# CONFIG_PDC_ADMA is not set
684# CONFIG_SATA_QSTOR is not set
685# CONFIG_SATA_PROMISE is not set
686# CONFIG_SATA_SX4 is not set
687# CONFIG_SATA_SIL is not set
688CONFIG_SATA_SIL24=y
689# CONFIG_SATA_SIS is not set
690# CONFIG_SATA_ULI is not set
691# CONFIG_SATA_VIA is not set
692# CONFIG_SATA_VITESSE is not set
693# CONFIG_SATA_INIC162X is not set
694# CONFIG_PATA_ALI is not set
695# CONFIG_PATA_AMD is not set
696# CONFIG_PATA_ARTOP is not set
697# CONFIG_PATA_ATIIXP is not set
698# CONFIG_PATA_CMD640_PCI is not set
699# CONFIG_PATA_CMD64X is not set
700# CONFIG_PATA_CS5520 is not set
701# CONFIG_PATA_CS5530 is not set
702# CONFIG_PATA_CYPRESS is not set
703# CONFIG_PATA_EFAR is not set
704# CONFIG_ATA_GENERIC is not set
705# CONFIG_PATA_HPT366 is not set
706# CONFIG_PATA_HPT37X is not set
707# CONFIG_PATA_HPT3X2N is not set
708# CONFIG_PATA_HPT3X3 is not set
709# CONFIG_PATA_IT821X is not set
710# CONFIG_PATA_IT8213 is not set
711# CONFIG_PATA_JMICRON is not set
712# CONFIG_PATA_TRIFLEX is not set
713# CONFIG_PATA_MARVELL is not set
714# CONFIG_PATA_MPIIX is not set
715# CONFIG_PATA_OLDPIIX is not set
716# CONFIG_PATA_NETCELL is not set
717# CONFIG_PATA_NINJA32 is not set
718# CONFIG_PATA_NS87410 is not set
719# CONFIG_PATA_NS87415 is not set
720# CONFIG_PATA_OPTI is not set
721# CONFIG_PATA_OPTIDMA is not set
722# CONFIG_PATA_PDC_OLD is not set
723# CONFIG_PATA_RADISYS is not set
724# CONFIG_PATA_RZ1000 is not set
725# CONFIG_PATA_SC1200 is not set
726# CONFIG_PATA_SERVERWORKS is not set
727# CONFIG_PATA_PDC2027X is not set
728CONFIG_PATA_SIL680=y
729# CONFIG_PATA_SIS is not set
730# CONFIG_PATA_VIA is not set
731# CONFIG_PATA_WINBOND is not set
732# CONFIG_PATA_PLATFORM is not set
519# CONFIG_MD is not set 733# CONFIG_MD is not set
520
521#
522# Fusion MPT device support
523#
524# CONFIG_FUSION is not set 734# CONFIG_FUSION is not set
525 735
526# 736#
527# IEEE 1394 (FireWire) support 737# IEEE 1394 (FireWire) support
528# 738#
739# CONFIG_FIREWIRE is not set
529# CONFIG_IEEE1394 is not set 740# CONFIG_IEEE1394 is not set
530
531#
532# I2O device support
533#
534# CONFIG_I2O is not set 741# CONFIG_I2O is not set
535
536#
537# Network device support
538#
539CONFIG_NETDEVICES=y 742CONFIG_NETDEVICES=y
743# CONFIG_NETDEVICES_MULTIQUEUE is not set
540# CONFIG_DUMMY is not set 744# CONFIG_DUMMY is not set
541# CONFIG_BONDING is not set 745# CONFIG_BONDING is not set
746# CONFIG_MACVLAN is not set
542# CONFIG_EQUALIZER is not set 747# CONFIG_EQUALIZER is not set
543# CONFIG_TUN is not set 748# CONFIG_TUN is not set
544 749# CONFIG_VETH is not set
545#
546# ARCnet devices
547#
548# CONFIG_ARCNET is not set 750# CONFIG_ARCNET is not set
549 751CONFIG_PHYLIB=y
550# 752
551# PHY device support 753#
552# 754# MII PHY device drivers
553# CONFIG_PHYLIB is not set 755#
554 756# CONFIG_MARVELL_PHY is not set
555# 757# CONFIG_DAVICOM_PHY is not set
556# Ethernet (10 or 100Mbit) 758# CONFIG_QSEMI_PHY is not set
557# 759# CONFIG_LXT_PHY is not set
760# CONFIG_CICADA_PHY is not set
761# CONFIG_VITESSE_PHY is not set
762# CONFIG_SMSC_PHY is not set
763# CONFIG_BROADCOM_PHY is not set
764# CONFIG_ICPLUS_PHY is not set
765# CONFIG_REALTEK_PHY is not set
766# CONFIG_FIXED_PHY is not set
767# CONFIG_MDIO_BITBANG is not set
558CONFIG_NET_ETHERNET=y 768CONFIG_NET_ETHERNET=y
559CONFIG_MII=y 769CONFIG_MII=y
770# CONFIG_AX88796 is not set
560# CONFIG_HAPPYMEAL is not set 771# CONFIG_HAPPYMEAL is not set
561# CONFIG_SUNGEM is not set 772# CONFIG_SUNGEM is not set
562# CONFIG_CASSINI is not set 773# CONFIG_CASSINI is not set
563# CONFIG_NET_VENDOR_3COM is not set 774# CONFIG_NET_VENDOR_3COM is not set
564# CONFIG_DM9000 is not set 775# CONFIG_DM9000 is not set
565
566#
567# Tulip family network device support
568#
569# CONFIG_NET_TULIP is not set 776# CONFIG_NET_TULIP is not set
570# CONFIG_HP100 is not set 777# CONFIG_HP100 is not set
778# CONFIG_IBM_NEW_EMAC_ZMII is not set
779# CONFIG_IBM_NEW_EMAC_RGMII is not set
780# CONFIG_IBM_NEW_EMAC_TAH is not set
781# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
571# CONFIG_NET_PCI is not set 782# CONFIG_NET_PCI is not set
572 783# CONFIG_B44 is not set
573# 784CONFIG_NETDEV_1000=y
574# Ethernet (1000 Mbit)
575#
576# CONFIG_ACENIC is not set 785# CONFIG_ACENIC is not set
577# CONFIG_DL2K is not set 786# CONFIG_DL2K is not set
578# CONFIG_E1000 is not set 787# CONFIG_E1000 is not set
788# CONFIG_E1000E is not set
789# CONFIG_E1000E_ENABLED is not set
790# CONFIG_IP1000 is not set
791# CONFIG_IGB is not set
579# CONFIG_NS83820 is not set 792# CONFIG_NS83820 is not set
580# CONFIG_HAMACHI is not set 793# CONFIG_HAMACHI is not set
581# CONFIG_YELLOWFIN is not set 794# CONFIG_YELLOWFIN is not set
@@ -585,52 +798,53 @@ CONFIG_SB1250_MAC=y
585# CONFIG_SKGE is not set 798# CONFIG_SKGE is not set
586# CONFIG_SKY2 is not set 799# CONFIG_SKY2 is not set
587# CONFIG_SK98LIN is not set 800# CONFIG_SK98LIN is not set
801# CONFIG_VIA_VELOCITY is not set
588# CONFIG_TIGON3 is not set 802# CONFIG_TIGON3 is not set
589# CONFIG_BNX2 is not set 803# CONFIG_BNX2 is not set
590# CONFIG_QLA3XXX is not set 804# CONFIG_QLA3XXX is not set
591# CONFIG_ATL1 is not set 805# CONFIG_ATL1 is not set
592 806CONFIG_NETDEV_10000=y
593#
594# Ethernet (10000 Mbit)
595#
596# CONFIG_CHELSIO_T1 is not set 807# CONFIG_CHELSIO_T1 is not set
597CONFIG_CHELSIO_T3=m 808CONFIG_CHELSIO_T3=m
809# CONFIG_IXGBE is not set
598# CONFIG_IXGB is not set 810# CONFIG_IXGB is not set
599# CONFIG_S2IO is not set 811# CONFIG_S2IO is not set
600# CONFIG_MYRI10GE is not set 812# CONFIG_MYRI10GE is not set
601CONFIG_NETXEN_NIC=m 813CONFIG_NETXEN_NIC=m
602 814# CONFIG_NIU is not set
603# 815# CONFIG_MLX4_CORE is not set
604# Token Ring devices 816# CONFIG_TEHUTI is not set
605# 817# CONFIG_BNX2X is not set
606# CONFIG_TR is not set 818# CONFIG_TR is not set
607 819
608# 820#
609# Wireless LAN (non-hamradio) 821# Wireless LAN
610#
611# CONFIG_NET_RADIO is not set
612
613#
614# Wan interfaces
615# 822#
823# CONFIG_WLAN_PRE80211 is not set
824# CONFIG_WLAN_80211 is not set
616# CONFIG_WAN is not set 825# CONFIG_WAN is not set
617# CONFIG_FDDI is not set 826# CONFIG_FDDI is not set
618# CONFIG_HIPPI is not set 827# CONFIG_HIPPI is not set
619# CONFIG_PPP is not set 828CONFIG_PPP=m
620# CONFIG_SLIP is not set 829CONFIG_PPP_MULTILINK=y
621# CONFIG_SHAPER is not set 830CONFIG_PPP_FILTER=y
831CONFIG_PPP_ASYNC=m
832CONFIG_PPP_SYNC_TTY=m
833CONFIG_PPP_DEFLATE=m
834CONFIG_PPP_BSDCOMP=m
835CONFIG_PPP_MPPE=m
836CONFIG_PPPOE=m
837CONFIG_PPPOL2TP=m
838CONFIG_SLIP=m
839CONFIG_SLIP_COMPRESSED=y
840CONFIG_SLHC=m
841CONFIG_SLIP_SMART=y
842CONFIG_SLIP_MODE_SLIP6=y
843# CONFIG_NET_FC is not set
622# CONFIG_NETCONSOLE is not set 844# CONFIG_NETCONSOLE is not set
623# CONFIG_NETPOLL is not set 845# CONFIG_NETPOLL is not set
624# CONFIG_NET_POLL_CONTROLLER is not set 846# CONFIG_NET_POLL_CONTROLLER is not set
625
626#
627# ISDN subsystem
628#
629# CONFIG_ISDN is not set 847# CONFIG_ISDN is not set
630
631#
632# Telephony Support
633#
634# CONFIG_PHONE is not set 848# CONFIG_PHONE is not set
635 849
636# 850#
@@ -660,17 +874,16 @@ CONFIG_SERIAL_NONSTANDARD=y
660# CONFIG_DIGIEPCA is not set 874# CONFIG_DIGIEPCA is not set
661# CONFIG_MOXA_INTELLIO is not set 875# CONFIG_MOXA_INTELLIO is not set
662# CONFIG_MOXA_SMARTIO is not set 876# CONFIG_MOXA_SMARTIO is not set
663CONFIG_MOXA_SMARTIO_NEW=m
664# CONFIG_ISI is not set 877# CONFIG_ISI is not set
665# CONFIG_SYNCLINKMP is not set 878# CONFIG_SYNCLINKMP is not set
666# CONFIG_SYNCLINK_GT is not set 879# CONFIG_SYNCLINK_GT is not set
667# CONFIG_N_HDLC is not set 880# CONFIG_N_HDLC is not set
881# CONFIG_RISCOM8 is not set
668# CONFIG_SPECIALIX is not set 882# CONFIG_SPECIALIX is not set
669# CONFIG_SX is not set 883# CONFIG_SX is not set
670# CONFIG_RIO is not set 884# CONFIG_RIO is not set
671# CONFIG_STALDRV is not set 885# CONFIG_STALDRV is not set
672CONFIG_SERIAL_SB1250_DUART=y 886# CONFIG_NOZOMI is not set
673CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
674 887
675# 888#
676# Serial drivers 889# Serial drivers
@@ -680,39 +893,24 @@ CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
680# 893#
681# Non-8250 serial port support 894# Non-8250 serial port support
682# 895#
896CONFIG_SERIAL_SB1250_DUART=y
897CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
898CONFIG_SERIAL_CORE=y
899CONFIG_SERIAL_CORE_CONSOLE=y
683# CONFIG_SERIAL_JSM is not set 900# CONFIG_SERIAL_JSM is not set
684CONFIG_UNIX98_PTYS=y 901CONFIG_UNIX98_PTYS=y
685CONFIG_LEGACY_PTYS=y 902CONFIG_LEGACY_PTYS=y
686CONFIG_LEGACY_PTY_COUNT=256 903CONFIG_LEGACY_PTY_COUNT=256
687
688#
689# IPMI
690#
691# CONFIG_IPMI_HANDLER is not set 904# CONFIG_IPMI_HANDLER is not set
692
693#
694# Watchdog Cards
695#
696# CONFIG_WATCHDOG is not set
697# CONFIG_HW_RANDOM is not set 905# CONFIG_HW_RANDOM is not set
698# CONFIG_RTC is not set 906# CONFIG_RTC is not set
699CONFIG_GEN_RTC=y
700# CONFIG_GEN_RTC_X is not set
701# CONFIG_DTLK is not set
702# CONFIG_R3964 is not set 907# CONFIG_R3964 is not set
703# CONFIG_APPLICOM is not set 908# CONFIG_APPLICOM is not set
704# CONFIG_DRM is not set
705# CONFIG_RAW_DRIVER is not set 909# CONFIG_RAW_DRIVER is not set
706
707#
708# TPM devices
709#
710# CONFIG_TCG_TPM is not set 910# CONFIG_TCG_TPM is not set
711 911CONFIG_DEVPORT=y
712#
713# I2C support
714#
715CONFIG_I2C=y 912CONFIG_I2C=y
913CONFIG_I2C_BOARDINFO=y
716CONFIG_I2C_CHARDEV=y 914CONFIG_I2C_CHARDEV=y
717 915
718# 916#
@@ -736,29 +934,30 @@ CONFIG_I2C_CHARDEV=y
736# CONFIG_I2C_NFORCE2 is not set 934# CONFIG_I2C_NFORCE2 is not set
737# CONFIG_I2C_OCORES is not set 935# CONFIG_I2C_OCORES is not set
738# CONFIG_I2C_PARPORT_LIGHT is not set 936# CONFIG_I2C_PARPORT_LIGHT is not set
739# CONFIG_I2C_PASEMI is not set
740# CONFIG_I2C_PROSAVAGE is not set 937# CONFIG_I2C_PROSAVAGE is not set
741# CONFIG_I2C_SAVAGE4 is not set 938# CONFIG_I2C_SAVAGE4 is not set
742CONFIG_I2C_SIBYTE=y 939CONFIG_I2C_SIBYTE=y
940# CONFIG_I2C_SIMTEC is not set
743# CONFIG_I2C_SIS5595 is not set 941# CONFIG_I2C_SIS5595 is not set
744# CONFIG_I2C_SIS630 is not set 942# CONFIG_I2C_SIS630 is not set
745# CONFIG_I2C_SIS96X is not set 943# CONFIG_I2C_SIS96X is not set
944# CONFIG_I2C_TAOS_EVM is not set
746# CONFIG_I2C_STUB is not set 945# CONFIG_I2C_STUB is not set
747# CONFIG_I2C_VIA is not set 946# CONFIG_I2C_VIA is not set
748# CONFIG_I2C_VIAPRO is not set 947# CONFIG_I2C_VIAPRO is not set
749# CONFIG_I2C_VOODOO3 is not set 948# CONFIG_I2C_VOODOO3 is not set
750# CONFIG_I2C_PCA_ISA is not set
751 949
752# 950#
753# Miscellaneous I2C Chip support 951# Miscellaneous I2C Chip support
754# 952#
755CONFIG_SENSORS_DS1337=y 953# CONFIG_DS1682 is not set
756CONFIG_SENSORS_DS1374=y
757CONFIG_SENSORS_EEPROM=y 954CONFIG_SENSORS_EEPROM=y
758CONFIG_SENSORS_PCF8574=y 955CONFIG_SENSORS_PCF8574=y
759CONFIG_SENSORS_PCA9539=y 956# CONFIG_PCF8575 is not set
760CONFIG_SENSORS_PCF8591=y 957CONFIG_SENSORS_PCF8591=y
958# CONFIG_TPS65010 is not set
761CONFIG_SENSORS_MAX6875=y 959CONFIG_SENSORS_MAX6875=y
960# CONFIG_SENSORS_TSL2550 is not set
762CONFIG_I2C_DEBUG_CORE=y 961CONFIG_I2C_DEBUG_CORE=y
763CONFIG_I2C_DEBUG_ALGO=y 962CONFIG_I2C_DEBUG_ALGO=y
764CONFIG_I2C_DEBUG_BUS=y 963CONFIG_I2C_DEBUG_BUS=y
@@ -769,43 +968,49 @@ CONFIG_I2C_DEBUG_CHIP=y
769# 968#
770# CONFIG_SPI is not set 969# CONFIG_SPI is not set
771# CONFIG_SPI_MASTER is not set 970# CONFIG_SPI_MASTER is not set
971# CONFIG_W1 is not set
972# CONFIG_POWER_SUPPLY is not set
973# CONFIG_HWMON is not set
974# CONFIG_THERMAL is not set
975# CONFIG_WATCHDOG is not set
772 976
773# 977#
774# Dallas's 1-wire bus 978# Sonics Silicon Backplane
775# 979#
776# CONFIG_W1 is not set 980CONFIG_SSB_POSSIBLE=y
981# CONFIG_SSB is not set
777 982
778# 983#
779# Hardware Monitoring support 984# Multifunction device drivers
780# 985#
781# CONFIG_HWMON is not set 986# CONFIG_MFD_SM501 is not set
782# CONFIG_HWMON_VID is not set
783 987
784# 988#
785# Multimedia devices 989# Multimedia devices
786# 990#
787# CONFIG_VIDEO_DEV is not set 991# CONFIG_VIDEO_DEV is not set
788 992# CONFIG_DVB_CORE is not set
789# 993# CONFIG_DAB is not set
790# Digital Video Broadcasting Devices
791#
792# CONFIG_DVB is not set
793 994
794# 995#
795# Graphics support 996# Graphics support
796# 997#
797# CONFIG_FIRMWARE_EDID is not set 998# CONFIG_DRM is not set
999# CONFIG_VGASTATE is not set
1000# CONFIG_VIDEO_OUTPUT_CONTROL is not set
798# CONFIG_FB is not set 1001# CONFIG_FB is not set
799# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1002# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
800 1003
801# 1004#
802# Sound 1005# Display device support
803# 1006#
804# CONFIG_SOUND is not set 1007# CONFIG_DISPLAY_SUPPORT is not set
805 1008
806# 1009#
807# USB support 1010# Sound
808# 1011#
1012# CONFIG_SOUND is not set
1013CONFIG_USB_SUPPORT=y
809CONFIG_USB_ARCH_HAS_HCD=y 1014CONFIG_USB_ARCH_HAS_HCD=y
810CONFIG_USB_ARCH_HAS_OHCI=y 1015CONFIG_USB_ARCH_HAS_OHCI=y
811CONFIG_USB_ARCH_HAS_EHCI=y 1016CONFIG_USB_ARCH_HAS_EHCI=y
@@ -814,104 +1019,73 @@ CONFIG_USB_ARCH_HAS_EHCI=y
814# 1019#
815# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1020# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
816# 1021#
817
818#
819# USB Gadget Support
820#
821# CONFIG_USB_GADGET is not set 1022# CONFIG_USB_GADGET is not set
822
823#
824# MMC/SD Card support
825#
826# CONFIG_MMC is not set 1023# CONFIG_MMC is not set
827 1024# CONFIG_MEMSTICK is not set
828#
829# LED devices
830#
831# CONFIG_NEW_LEDS is not set 1025# CONFIG_NEW_LEDS is not set
832
833#
834# LED drivers
835#
836
837#
838# LED Triggers
839#
840
841#
842# InfiniBand support
843#
844# CONFIG_INFINIBAND is not set 1026# CONFIG_INFINIBAND is not set
845 1027CONFIG_RTC_LIB=y
846#
847# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
848#
849
850#
851# Real Time Clock
852#
853# CONFIG_RTC_CLASS is not set 1028# CONFIG_RTC_CLASS is not set
854 1029
855# 1030#
856# DMA Engine support 1031# Userspace I/O
857#
858# CONFIG_DMA_ENGINE is not set
859
860#
861# DMA Clients
862#
863
864#
865# DMA Devices
866#
867
868#
869# Auxiliary Display support
870#
871
872#
873# Virtualization
874# 1032#
1033# CONFIG_UIO is not set
875 1034
876# 1035#
877# File systems 1036# File systems
878# 1037#
879CONFIG_EXT2_FS=y 1038CONFIG_EXT2_FS=m
880CONFIG_EXT2_FS_XATTR=y 1039CONFIG_EXT2_FS_XATTR=y
881CONFIG_EXT2_FS_POSIX_ACL=y 1040# CONFIG_EXT2_FS_POSIX_ACL is not set
882CONFIG_EXT2_FS_SECURITY=y 1041# CONFIG_EXT2_FS_SECURITY is not set
883# CONFIG_EXT2_FS_XIP is not set 1042# CONFIG_EXT2_FS_XIP is not set
884# CONFIG_EXT3_FS is not set 1043CONFIG_EXT3_FS=y
1044CONFIG_EXT3_FS_XATTR=y
1045# CONFIG_EXT3_FS_POSIX_ACL is not set
1046# CONFIG_EXT3_FS_SECURITY is not set
885# CONFIG_EXT4DEV_FS is not set 1047# CONFIG_EXT4DEV_FS is not set
1048CONFIG_JBD=y
886CONFIG_FS_MBCACHE=y 1049CONFIG_FS_MBCACHE=y
887# CONFIG_REISERFS_FS is not set 1050# CONFIG_REISERFS_FS is not set
888# CONFIG_JFS_FS is not set 1051# CONFIG_JFS_FS is not set
889CONFIG_FS_POSIX_ACL=y 1052# CONFIG_FS_POSIX_ACL is not set
890# CONFIG_XFS_FS is not set 1053# CONFIG_XFS_FS is not set
891# CONFIG_GFS2_FS is not set 1054# CONFIG_GFS2_FS is not set
892# CONFIG_OCFS2_FS is not set 1055# CONFIG_OCFS2_FS is not set
893# CONFIG_MINIX_FS is not set 1056CONFIG_DNOTIFY=y
894# CONFIG_ROMFS_FS is not set
895CONFIG_INOTIFY=y 1057CONFIG_INOTIFY=y
896CONFIG_INOTIFY_USER=y 1058CONFIG_INOTIFY_USER=y
897# CONFIG_QUOTA is not set 1059CONFIG_QUOTA=y
898CONFIG_DNOTIFY=y 1060CONFIG_QUOTA_NETLINK_INTERFACE=y
899# CONFIG_AUTOFS_FS is not set 1061# CONFIG_PRINT_QUOTA_WARNING is not set
900# CONFIG_AUTOFS4_FS is not set 1062# CONFIG_QFMT_V1 is not set
901# CONFIG_FUSE_FS is not set 1063CONFIG_QFMT_V2=m
1064CONFIG_QUOTACTL=y
1065CONFIG_AUTOFS_FS=m
1066CONFIG_AUTOFS4_FS=m
1067CONFIG_FUSE_FS=m
902 1068
903# 1069#
904# CD-ROM/DVD Filesystems 1070# CD-ROM/DVD Filesystems
905# 1071#
906# CONFIG_ISO9660_FS is not set 1072CONFIG_ISO9660_FS=m
907# CONFIG_UDF_FS is not set 1073CONFIG_JOLIET=y
1074CONFIG_ZISOFS=y
1075CONFIG_UDF_FS=m
1076CONFIG_UDF_NLS=y
908 1077
909# 1078#
910# DOS/FAT/NT Filesystems 1079# DOS/FAT/NT Filesystems
911# 1080#
912# CONFIG_MSDOS_FS is not set 1081CONFIG_FAT_FS=m
913# CONFIG_VFAT_FS is not set 1082CONFIG_MSDOS_FS=m
914# CONFIG_NTFS_FS is not set 1083CONFIG_VFAT_FS=m
1084CONFIG_FAT_DEFAULT_CODEPAGE=437
1085CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1086CONFIG_NTFS_FS=m
1087# CONFIG_NTFS_DEBUG is not set
1088CONFIG_NTFS_RW=y
915 1089
916# 1090#
917# Pseudo filesystems 1091# Pseudo filesystems
@@ -923,7 +1097,6 @@ CONFIG_SYSFS=y
923CONFIG_TMPFS=y 1097CONFIG_TMPFS=y
924# CONFIG_TMPFS_POSIX_ACL is not set 1098# CONFIG_TMPFS_POSIX_ACL is not set
925# CONFIG_HUGETLB_PAGE is not set 1099# CONFIG_HUGETLB_PAGE is not set
926CONFIG_RAMFS=y
927CONFIG_CONFIGFS_FS=m 1100CONFIG_CONFIGFS_FS=m
928 1101
929# 1102#
@@ -939,14 +1112,13 @@ CONFIG_CONFIGFS_FS=m
939# CONFIG_EFS_FS is not set 1112# CONFIG_EFS_FS is not set
940# CONFIG_CRAMFS is not set 1113# CONFIG_CRAMFS is not set
941# CONFIG_VXFS_FS is not set 1114# CONFIG_VXFS_FS is not set
1115# CONFIG_MINIX_FS is not set
942# CONFIG_HPFS_FS is not set 1116# CONFIG_HPFS_FS is not set
943# CONFIG_QNX4FS_FS is not set 1117# CONFIG_QNX4FS_FS is not set
1118# CONFIG_ROMFS_FS is not set
944# CONFIG_SYSV_FS is not set 1119# CONFIG_SYSV_FS is not set
945# CONFIG_UFS_FS is not set 1120# CONFIG_UFS_FS is not set
946 1121CONFIG_NETWORK_FILESYSTEMS=y
947#
948# Network File Systems
949#
950CONFIG_NFS_FS=y 1122CONFIG_NFS_FS=y
951CONFIG_NFS_V3=y 1123CONFIG_NFS_V3=y
952# CONFIG_NFS_V3_ACL is not set 1124# CONFIG_NFS_V3_ACL is not set
@@ -958,6 +1130,7 @@ CONFIG_LOCKD=y
958CONFIG_LOCKD_V4=y 1130CONFIG_LOCKD_V4=y
959CONFIG_NFS_COMMON=y 1131CONFIG_NFS_COMMON=y
960CONFIG_SUNRPC=y 1132CONFIG_SUNRPC=y
1133# CONFIG_SUNRPC_BIND34 is not set
961# CONFIG_RPCSEC_GSS_KRB5 is not set 1134# CONFIG_RPCSEC_GSS_KRB5 is not set
962# CONFIG_RPCSEC_GSS_SPKM3 is not set 1135# CONFIG_RPCSEC_GSS_SPKM3 is not set
963# CONFIG_SMB_FS is not set 1136# CONFIG_SMB_FS is not set
@@ -965,37 +1138,61 @@ CONFIG_SUNRPC=y
965# CONFIG_NCP_FS is not set 1138# CONFIG_NCP_FS is not set
966# CONFIG_CODA_FS is not set 1139# CONFIG_CODA_FS is not set
967# CONFIG_AFS_FS is not set 1140# CONFIG_AFS_FS is not set
968# CONFIG_9P_FS is not set
969 1141
970# 1142#
971# Partition Types 1143# Partition Types
972# 1144#
973# CONFIG_PARTITION_ADVANCED is not set 1145# CONFIG_PARTITION_ADVANCED is not set
974CONFIG_MSDOS_PARTITION=y 1146CONFIG_MSDOS_PARTITION=y
975 1147CONFIG_NLS=m
976# 1148CONFIG_NLS_DEFAULT="iso8859-1"
977# Native Language Support 1149CONFIG_NLS_CODEPAGE_437=m
978# 1150CONFIG_NLS_CODEPAGE_737=m
979# CONFIG_NLS is not set 1151CONFIG_NLS_CODEPAGE_775=m
980 1152CONFIG_NLS_CODEPAGE_850=m
981# 1153CONFIG_NLS_CODEPAGE_852=m
982# Distributed Lock Manager 1154CONFIG_NLS_CODEPAGE_855=m
983# 1155CONFIG_NLS_CODEPAGE_857=m
1156CONFIG_NLS_CODEPAGE_860=m
1157CONFIG_NLS_CODEPAGE_861=m
1158CONFIG_NLS_CODEPAGE_862=m
1159CONFIG_NLS_CODEPAGE_863=m
1160CONFIG_NLS_CODEPAGE_864=m
1161CONFIG_NLS_CODEPAGE_865=m
1162CONFIG_NLS_CODEPAGE_866=m
1163CONFIG_NLS_CODEPAGE_869=m
1164CONFIG_NLS_CODEPAGE_936=m
1165CONFIG_NLS_CODEPAGE_950=m
1166CONFIG_NLS_CODEPAGE_932=m
1167CONFIG_NLS_CODEPAGE_949=m
1168CONFIG_NLS_CODEPAGE_874=m
1169CONFIG_NLS_ISO8859_8=m
1170CONFIG_NLS_CODEPAGE_1250=m
1171CONFIG_NLS_CODEPAGE_1251=m
1172CONFIG_NLS_ASCII=m
1173CONFIG_NLS_ISO8859_1=m
1174CONFIG_NLS_ISO8859_2=m
1175CONFIG_NLS_ISO8859_3=m
1176CONFIG_NLS_ISO8859_4=m
1177CONFIG_NLS_ISO8859_5=m
1178CONFIG_NLS_ISO8859_6=m
1179CONFIG_NLS_ISO8859_7=m
1180CONFIG_NLS_ISO8859_9=m
1181CONFIG_NLS_ISO8859_13=m
1182CONFIG_NLS_ISO8859_14=m
1183CONFIG_NLS_ISO8859_15=m
1184CONFIG_NLS_KOI8_R=m
1185CONFIG_NLS_KOI8_U=m
1186CONFIG_NLS_UTF8=m
984CONFIG_DLM=m 1187CONFIG_DLM=m
985CONFIG_DLM_TCP=y
986# CONFIG_DLM_SCTP is not set
987# CONFIG_DLM_DEBUG is not set 1188# CONFIG_DLM_DEBUG is not set
988 1189
989# 1190#
990# Profiling support
991#
992# CONFIG_PROFILING is not set
993
994#
995# Kernel hacking 1191# Kernel hacking
996# 1192#
997CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1193CONFIG_TRACE_IRQFLAGS_SUPPORT=y
998# CONFIG_PRINTK_TIME is not set 1194# CONFIG_PRINTK_TIME is not set
1195CONFIG_ENABLE_WARN_DEPRECATED=y
999CONFIG_ENABLE_MUST_CHECK=y 1196CONFIG_ENABLE_MUST_CHECK=y
1000CONFIG_MAGIC_SYSRQ=y 1197CONFIG_MAGIC_SYSRQ=y
1001# CONFIG_UNUSED_SYMBOLS is not set 1198# CONFIG_UNUSED_SYMBOLS is not set
@@ -1003,8 +1200,8 @@ CONFIG_MAGIC_SYSRQ=y
1003# CONFIG_HEADERS_CHECK is not set 1200# CONFIG_HEADERS_CHECK is not set
1004CONFIG_DEBUG_KERNEL=y 1201CONFIG_DEBUG_KERNEL=y
1005# CONFIG_DEBUG_SHIRQ is not set 1202# CONFIG_DEBUG_SHIRQ is not set
1006CONFIG_LOG_BUF_SHIFT=16
1007CONFIG_DETECT_SOFTLOCKUP=y 1203CONFIG_DETECT_SOFTLOCKUP=y
1204CONFIG_SCHED_DEBUG=y
1008# CONFIG_SCHEDSTATS is not set 1205# CONFIG_SCHEDSTATS is not set
1009# CONFIG_TIMER_STATS is not set 1206# CONFIG_TIMER_STATS is not set
1010# CONFIG_DEBUG_SLAB is not set 1207# CONFIG_DEBUG_SLAB is not set
@@ -1014,15 +1211,19 @@ CONFIG_DETECT_SOFTLOCKUP=y
1014CONFIG_DEBUG_MUTEXES=y 1211CONFIG_DEBUG_MUTEXES=y
1015# CONFIG_DEBUG_LOCK_ALLOC is not set 1212# CONFIG_DEBUG_LOCK_ALLOC is not set
1016# CONFIG_PROVE_LOCKING is not set 1213# CONFIG_PROVE_LOCKING is not set
1214# CONFIG_LOCK_STAT is not set
1017# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1215# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1018# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1216# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1019# CONFIG_DEBUG_KOBJECT is not set 1217# CONFIG_DEBUG_KOBJECT is not set
1020# CONFIG_DEBUG_INFO is not set 1218# CONFIG_DEBUG_INFO is not set
1021# CONFIG_DEBUG_VM is not set 1219# CONFIG_DEBUG_VM is not set
1022# CONFIG_DEBUG_LIST is not set 1220# CONFIG_DEBUG_LIST is not set
1023CONFIG_FORCED_INLINING=y 1221# CONFIG_DEBUG_SG is not set
1222# CONFIG_BOOT_PRINTK_DELAY is not set
1024# CONFIG_RCU_TORTURE_TEST is not set 1223# CONFIG_RCU_TORTURE_TEST is not set
1025CONFIG_CROSSCOMPILE=y 1224# CONFIG_BACKTRACE_SELF_TEST is not set
1225# CONFIG_FAULT_INJECTION is not set
1226# CONFIG_SAMPLES is not set
1026CONFIG_CMDLINE="" 1227CONFIG_CMDLINE=""
1027# CONFIG_DEBUG_STACK_USAGE is not set 1228# CONFIG_DEBUG_STACK_USAGE is not set
1028# CONFIG_SB1XXX_CORELIS is not set 1229# CONFIG_SB1XXX_CORELIS is not set
@@ -1034,23 +1235,22 @@ CONFIG_CMDLINE=""
1034CONFIG_KEYS=y 1235CONFIG_KEYS=y
1035CONFIG_KEYS_DEBUG_PROC_KEYS=y 1236CONFIG_KEYS_DEBUG_PROC_KEYS=y
1036# CONFIG_SECURITY is not set 1237# CONFIG_SECURITY is not set
1037 1238# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1038#
1039# Cryptographic options
1040#
1041CONFIG_CRYPTO=y 1239CONFIG_CRYPTO=y
1042CONFIG_CRYPTO_ALGAPI=y 1240CONFIG_CRYPTO_ALGAPI=y
1043CONFIG_CRYPTO_BLKCIPHER=m 1241CONFIG_CRYPTO_AEAD=m
1242CONFIG_CRYPTO_BLKCIPHER=y
1243CONFIG_CRYPTO_SEQIV=m
1044CONFIG_CRYPTO_HASH=y 1244CONFIG_CRYPTO_HASH=y
1045CONFIG_CRYPTO_MANAGER=y 1245CONFIG_CRYPTO_MANAGER=y
1046CONFIG_CRYPTO_HMAC=y 1246CONFIG_CRYPTO_HMAC=y
1047CONFIG_CRYPTO_XCBC=m 1247CONFIG_CRYPTO_XCBC=m
1048CONFIG_CRYPTO_NULL=y 1248CONFIG_CRYPTO_NULL=y
1049CONFIG_CRYPTO_MD4=y 1249CONFIG_CRYPTO_MD4=m
1050CONFIG_CRYPTO_MD5=y 1250CONFIG_CRYPTO_MD5=y
1051CONFIG_CRYPTO_SHA1=y 1251CONFIG_CRYPTO_SHA1=m
1052CONFIG_CRYPTO_SHA256=y 1252CONFIG_CRYPTO_SHA256=m
1053CONFIG_CRYPTO_SHA512=y 1253CONFIG_CRYPTO_SHA512=m
1054CONFIG_CRYPTO_WP512=m 1254CONFIG_CRYPTO_WP512=m
1055CONFIG_CRYPTO_TGR192=m 1255CONFIG_CRYPTO_TGR192=m
1056CONFIG_CRYPTO_GF128MUL=m 1256CONFIG_CRYPTO_GF128MUL=m
@@ -1058,39 +1258,50 @@ CONFIG_CRYPTO_ECB=m
1058CONFIG_CRYPTO_CBC=m 1258CONFIG_CRYPTO_CBC=m
1059CONFIG_CRYPTO_PCBC=m 1259CONFIG_CRYPTO_PCBC=m
1060CONFIG_CRYPTO_LRW=m 1260CONFIG_CRYPTO_LRW=m
1061CONFIG_CRYPTO_DES=y 1261CONFIG_CRYPTO_XTS=m
1262CONFIG_CRYPTO_CTR=m
1263CONFIG_CRYPTO_GCM=m
1264CONFIG_CRYPTO_CCM=m
1265# CONFIG_CRYPTO_CRYPTD is not set
1266CONFIG_CRYPTO_DES=m
1062CONFIG_CRYPTO_FCRYPT=m 1267CONFIG_CRYPTO_FCRYPT=m
1063CONFIG_CRYPTO_BLOWFISH=y 1268CONFIG_CRYPTO_BLOWFISH=m
1064CONFIG_CRYPTO_TWOFISH=y 1269CONFIG_CRYPTO_TWOFISH=m
1065CONFIG_CRYPTO_TWOFISH_COMMON=y 1270CONFIG_CRYPTO_TWOFISH_COMMON=m
1066CONFIG_CRYPTO_SERPENT=y 1271CONFIG_CRYPTO_SERPENT=m
1067CONFIG_CRYPTO_AES=m 1272CONFIG_CRYPTO_AES=m
1068# CONFIG_CRYPTO_CAST5 is not set 1273CONFIG_CRYPTO_CAST5=m
1069# CONFIG_CRYPTO_CAST6 is not set 1274CONFIG_CRYPTO_CAST6=m
1070CONFIG_CRYPTO_TEA=m 1275CONFIG_CRYPTO_TEA=m
1071# CONFIG_CRYPTO_ARC4 is not set 1276CONFIG_CRYPTO_ARC4=m
1072CONFIG_CRYPTO_KHAZAD=m 1277CONFIG_CRYPTO_KHAZAD=m
1073CONFIG_CRYPTO_ANUBIS=m 1278CONFIG_CRYPTO_ANUBIS=m
1074CONFIG_CRYPTO_DEFLATE=y 1279CONFIG_CRYPTO_SEED=m
1075CONFIG_CRYPTO_MICHAEL_MIC=y 1280CONFIG_CRYPTO_SALSA20=m
1281CONFIG_CRYPTO_DEFLATE=m
1282CONFIG_CRYPTO_MICHAEL_MIC=m
1076# CONFIG_CRYPTO_CRC32C is not set 1283# CONFIG_CRYPTO_CRC32C is not set
1077CONFIG_CRYPTO_CAMELLIA=m 1284CONFIG_CRYPTO_CAMELLIA=m
1078# CONFIG_CRYPTO_TEST is not set 1285# CONFIG_CRYPTO_TEST is not set
1079 1286CONFIG_CRYPTO_AUTHENC=m
1080# 1287# CONFIG_CRYPTO_LZO is not set
1081# Hardware crypto devices 1288CONFIG_CRYPTO_HW=y
1082# 1289# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1083 1290
1084# 1291#
1085# Library routines 1292# Library routines
1086# 1293#
1087CONFIG_BITREVERSE=y 1294CONFIG_BITREVERSE=y
1088# CONFIG_CRC_CCITT is not set 1295CONFIG_CRC_CCITT=m
1089# CONFIG_CRC16 is not set 1296# CONFIG_CRC16 is not set
1297# CONFIG_CRC_ITU_T is not set
1090CONFIG_CRC32=y 1298CONFIG_CRC32=y
1091# CONFIG_LIBCRC32C is not set 1299# CONFIG_CRC7 is not set
1092CONFIG_ZLIB_INFLATE=y 1300CONFIG_LIBCRC32C=m
1093CONFIG_ZLIB_DEFLATE=y 1301CONFIG_AUDIT_GENERIC=y
1302CONFIG_ZLIB_INFLATE=m
1303CONFIG_ZLIB_DEFLATE=m
1094CONFIG_PLIST=y 1304CONFIG_PLIST=y
1095CONFIG_HAS_IOMEM=y 1305CONFIG_HAS_IOMEM=y
1096CONFIG_HAS_IOPORT=y 1306CONFIG_HAS_IOPORT=y
1307CONFIG_HAS_DMA=y
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index 3191afa29ad..25f4eab8ea9 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -139,7 +139,6 @@
139#include <asm/system.h> 139#include <asm/system.h>
140#include <asm/gdb-stub.h> 140#include <asm/gdb-stub.h>
141#include <asm/inst.h> 141#include <asm/inst.h>
142#include <asm/smp.h>
143 142
144/* 143/*
145 * external low-level support routines 144 * external low-level support routines
@@ -656,6 +655,7 @@ void set_async_breakpoint(unsigned long *epc)
656 *epc = (unsigned long)async_breakpoint; 655 *epc = (unsigned long)async_breakpoint;
657} 656}
658 657
658#ifdef CONFIG_SMP
659static void kgdb_wait(void *arg) 659static void kgdb_wait(void *arg)
660{ 660{
661 unsigned flags; 661 unsigned flags;
@@ -668,6 +668,7 @@ static void kgdb_wait(void *arg)
668 668
669 local_irq_restore(flags); 669 local_irq_restore(flags);
670} 670}
671#endif
671 672
672/* 673/*
673 * GDB stub needs to call kgdb_wait on all processor with interrupts 674 * GDB stub needs to call kgdb_wait on all processor with interrupts
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index fc4aa07b6d3..38fa1a194bf 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -15,6 +15,7 @@
15#include <asm/time.h> 15#include <asm/time.h>
16 16
17DEFINE_SPINLOCK(i8253_lock); 17DEFINE_SPINLOCK(i8253_lock);
18EXPORT_SYMBOL(i8253_lock);
18 19
19/* 20/*
20 * Initialize the PIT timer. 21 * Initialize the PIT timer.
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9f85d4cecc5..b45a7093ca2 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -157,6 +157,6 @@ void __init time_init(void)
157{ 157{
158 plat_time_init(); 158 plat_time_init();
159 159
160 if (mips_clockevent_init() || !cpu_has_mfc0_count_bug()) 160 if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
161 init_mips_clocksource(); 161 init_mips_clocksource();
162} 162}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index eed2dc4273e..39804c584ed 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -262,13 +262,21 @@ void dump_mtregs(void)
262/* Find some VPE program space */ 262/* Find some VPE program space */
263static void *alloc_progmem(unsigned long len) 263static void *alloc_progmem(unsigned long len)
264{ 264{
265 void *addr;
266
265#ifdef CONFIG_MIPS_VPE_LOADER_TOM 267#ifdef CONFIG_MIPS_VPE_LOADER_TOM
266 /* this means you must tell linux to use less memory than you physically have */ 268 /*
267 return pfn_to_kaddr(max_pfn); 269 * This means you must tell Linux to use less memory than you
270 * physically have, for example by passing a mem= boot argument.
271 */
272 addr = pfn_to_kaddr(max_pfn);
273 memset(addr, 0, len);
268#else 274#else
269 // simple grab some mem for now 275 /* simple grab some mem for now */
270 return kmalloc(len, GFP_KERNEL); 276 addr = kzalloc(len, GFP_KERNEL);
271#endif 277#endif
278
279 return addr;
272} 280}
273 281
274static void release_progmem(void *ptr) 282static void release_progmem(void *ptr)
@@ -884,9 +892,10 @@ static int vpe_elfload(struct vpe * v)
884 } 892 }
885 893
886 v->load_addr = alloc_progmem(mod.core_size); 894 v->load_addr = alloc_progmem(mod.core_size);
887 memset(v->load_addr, 0, mod.core_size); 895 if (!v->load_addr)
896 return -ENOMEM;
888 897
889 printk("VPE loader: loading to %p\n", v->load_addr); 898 pr_info("VPE loader: loading to %p\n", v->load_addr);
890 899
891 if (relocate) { 900 if (relocate) {
892 for (i = 0; i < hdr->e_shnum; i++) { 901 for (i = 0; i < hdr->e_shnum; i++) {
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6496925b5e2..77aefb4ebed 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -361,6 +361,16 @@ static inline int has_valid_asid(const struct mm_struct *mm)
361#endif 361#endif
362} 362}
363 363
364static void r4k__flush_cache_vmap(void)
365{
366 r4k_blast_dcache();
367}
368
369static void r4k__flush_cache_vunmap(void)
370{
371 r4k_blast_dcache();
372}
373
364static inline void local_r4k_flush_cache_range(void * args) 374static inline void local_r4k_flush_cache_range(void * args)
365{ 375{
366 struct vm_area_struct *vma = args; 376 struct vm_area_struct *vma = args;
@@ -1281,6 +1291,10 @@ void __cpuinit r4k_cache_init(void)
1281 PAGE_SIZE - 1); 1291 PAGE_SIZE - 1);
1282 else 1292 else
1283 shm_align_mask = PAGE_SIZE-1; 1293 shm_align_mask = PAGE_SIZE-1;
1294
1295 __flush_cache_vmap = r4k__flush_cache_vmap;
1296 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1297
1284 flush_cache_all = cache_noop; 1298 flush_cache_all = cache_noop;
1285 __flush_cache_all = r4k___flush_cache_all; 1299 __flush_cache_all = r4k___flush_cache_all;
1286 flush_cache_mm = r4k_flush_cache_mm; 1300 flush_cache_mm = r4k_flush_cache_mm;
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index b09d56981d5..a9f7f1f5e9b 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -122,6 +122,16 @@ static inline void tx39_blast_icache(void)
122 local_irq_restore(flags); 122 local_irq_restore(flags);
123} 123}
124 124
125static void tx39__flush_cache_vmap(void)
126{
127 tx39_blast_dcache();
128}
129
130static void tx39__flush_cache_vunmap(void)
131{
132 tx39_blast_dcache();
133}
134
125static inline void tx39_flush_cache_all(void) 135static inline void tx39_flush_cache_all(void)
126{ 136{
127 if (!cpu_has_dc_aliases) 137 if (!cpu_has_dc_aliases)
@@ -344,6 +354,8 @@ void __cpuinit tx39_cache_init(void)
344 switch (current_cpu_type()) { 354 switch (current_cpu_type()) {
345 case CPU_TX3912: 355 case CPU_TX3912:
346 /* TX39/H core (writethru direct-map cache) */ 356 /* TX39/H core (writethru direct-map cache) */
357 __flush_cache_vmap = tx39__flush_cache_vmap;
358 __flush_cache_vunmap = tx39__flush_cache_vunmap;
347 flush_cache_all = tx39h_flush_icache_all; 359 flush_cache_all = tx39h_flush_icache_all;
348 __flush_cache_all = tx39h_flush_icache_all; 360 __flush_cache_all = tx39h_flush_icache_all;
349 flush_cache_mm = (void *) tx39h_flush_icache_all; 361 flush_cache_mm = (void *) tx39h_flush_icache_all;
@@ -369,6 +381,9 @@ void __cpuinit tx39_cache_init(void)
369 write_c0_wired(0); /* set 8 on reset... */ 381 write_c0_wired(0); /* set 8 on reset... */
370 /* board-dependent init code may set WBON */ 382 /* board-dependent init code may set WBON */
371 383
384 __flush_cache_vmap = tx39__flush_cache_vmap;
385 __flush_cache_vunmap = tx39__flush_cache_vunmap;
386
372 flush_cache_all = tx39_flush_cache_all; 387 flush_cache_all = tx39_flush_cache_all;
373 __flush_cache_all = tx39___flush_cache_all; 388 __flush_cache_all = tx39___flush_cache_all;
374 flush_cache_mm = tx39_flush_cache_mm; 389 flush_cache_mm = tx39_flush_cache_mm;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 51ab1faa027..f5903679ee6 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -30,6 +30,9 @@ void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
30 unsigned long pfn); 30 unsigned long pfn);
31void (*flush_icache_range)(unsigned long start, unsigned long end); 31void (*flush_icache_range)(unsigned long start, unsigned long end);
32 32
33void (*__flush_cache_vmap)(void);
34void (*__flush_cache_vunmap)(void);
35
33/* MIPS specific cache operations */ 36/* MIPS specific cache operations */
34void (*flush_cache_sigtramp)(unsigned long addr); 37void (*flush_cache_sigtramp)(unsigned long addr);
35void (*local_flush_data_cache_page)(void * addr); 38void (*local_flush_data_cache_page)(void * addr);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 3a93d4ce270..382738ca8a0 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -307,6 +307,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
307 case CPU_R12000: 307 case CPU_R12000:
308 case CPU_R14000: 308 case CPU_R14000:
309 case CPU_4KC: 309 case CPU_4KC:
310 case CPU_4KEC:
310 case CPU_SB1: 311 case CPU_SB1:
311 case CPU_SB1A: 312 case CPU_SB1A:
312 case CPU_4KSC: 313 case CPU_4KSC:
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index ab68c4318a3..87e2c8f54e2 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -185,8 +185,8 @@ static struct resource bcm1480_mem_resource = {
185 185
186static struct resource bcm1480_io_resource = { 186static struct resource bcm1480_io_resource = {
187 .name = "BCM1480 PCI I/O", 187 .name = "BCM1480 PCI I/O",
188 .start = 0x2c000000UL, 188 .start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
189 .end = 0x2dffffffUL, 189 .end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
190 .flags = IORESOURCE_IO, 190 .flags = IORESOURCE_IO,
191}; 191};
192 192
@@ -194,6 +194,7 @@ struct pci_controller bcm1480_controller = {
194 .pci_ops = &bcm1480_pci_ops, 194 .pci_ops = &bcm1480_pci_ops,
195 .mem_resource = &bcm1480_mem_resource, 195 .mem_resource = &bcm1480_mem_resource,
196 .io_resource = &bcm1480_io_resource, 196 .io_resource = &bcm1480_io_resource,
197 .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
197}; 198};
198 199
199 200
@@ -251,6 +252,7 @@ static int __init bcm1480_pcibios_init(void)
251 252
252 bcm1480_controller.io_map_base = (unsigned long) 253 bcm1480_controller.io_map_base = (unsigned long)
253 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536); 254 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
255 bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
254 set_io_port_base(bcm1480_controller.io_map_base); 256 set_io_port_base(bcm1480_controller.io_map_base);
255 isa_slot_offset = (unsigned long) 257 isa_slot_offset = (unsigned long)
256 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); 258 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index 005e7fecab0..f54f45412b0 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -180,8 +180,8 @@ static struct resource bcm1480ht_mem_resource = {
180 180
181static struct resource bcm1480ht_io_resource = { 181static struct resource bcm1480ht_io_resource = {
182 .name = "BCM1480 HT I/O", 182 .name = "BCM1480 HT I/O",
183 .start = 0x00000000UL, 183 .start = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
184 .end = 0x01ffffffUL, 184 .end = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
185 .flags = IORESOURCE_IO, 185 .flags = IORESOURCE_IO,
186}; 186};
187 187
@@ -191,29 +191,22 @@ struct pci_controller bcm1480ht_controller = {
191 .io_resource = &bcm1480ht_io_resource, 191 .io_resource = &bcm1480ht_io_resource,
192 .index = 1, 192 .index = 1,
193 .get_busno = bcm1480ht_pcibios_get_busno, 193 .get_busno = bcm1480ht_pcibios_get_busno,
194 .io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
194}; 195};
195 196
196static int __init bcm1480ht_pcibios_init(void) 197static int __init bcm1480ht_pcibios_init(void)
197{ 198{
198 uint32_t cmdreg;
199
200 ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024); 199 ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
201 200
202 /* 201 /* CFE doesn't always init all HT paths, so we always scan */
203 * See if the PCI bus has been configured by the firmware.
204 */
205 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
206 PCI_COMMAND));
207 if (!(cmdreg & PCI_COMMAND_MASTER)) {
208 printk("HT: Skipping HT probe. Bus is not initialized.\n");
209 iounmap(ht_cfg_space);
210 return 1; /* XXX */
211 }
212 bcm1480ht_bus_status |= PCI_BUS_ENABLED; 202 bcm1480ht_bus_status |= PCI_BUS_ENABLED;
213 203
214 ht_eoi_space = (unsigned long) 204 ht_eoi_space = (unsigned long)
215 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES, 205 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
216 4 * 1024 * 1024); 206 4 * 1024 * 1024);
207 bcm1480ht_controller.io_map_base = (unsigned long)
208 ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
209 bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
217 210
218 register_pci_controller(&bcm1480ht_controller); 211 register_pci_controller(&bcm1480ht_controller);
219 212
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 30737eafe68..c6ca6319e4f 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -212,13 +212,30 @@
212 ethernet@3000 { 212 ethernet@3000 {
213 device_type = "network"; 213 device_type = "network";
214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
215 reg = <3000 800>; 215 reg = <3000 400>;
216 local-mac-address = [ 00 00 00 00 00 00 ]; 216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <2 5 0>; 217 interrupts = <2 5 0>;
218 interrupt-parent = <&mpc5200_pic>; 218 interrupt-parent = <&mpc5200_pic>;
219 phy-handle = <&phy0>;
220 };
221
222 mdio@3000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
226 reg = <3000 400>; // fec range, since we need to setup fec interrupts
227 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
228 interrupt-parent = <&mpc5200_pic>;
229
230 phy0: ethernet-phy@0 {
231 device_type = "ethernet-phy";
232 reg = <0>;
233 };
219 }; 234 };
220 235
221 i2c@3d40 { 236 i2c@3d40 {
237 #address-cells = <1>;
238 #size-cells = <0>;
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 239 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <3d40 40>; 240 reg = <3d40 40>;
224 interrupts = <2 10 0>; 241 interrupts = <2 10 0>;
@@ -231,4 +248,22 @@
231 reg = <8000 4000>; 248 reg = <8000 4000>;
232 }; 249 };
233 }; 250 };
251
252 lpb {
253 model = "fsl,lpb";
254 compatible = "fsl,lpb";
255 #address-cells = <2>;
256 #size-cells = <1>;
257 ranges = <0 0 fc000000 2000000>;
258
259 // 16-bit flash device at LocalPlus Bus CS0
260 flash@0,0 {
261 compatible = "cfi-flash";
262 reg = <0 0 2000000>;
263 bank-width = <2>;
264 device-width = <2>;
265 #size-cells = <1>;
266 #address-cells = <1>;
267 };
268 };
234}; 269};
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 0d701c1bf53..09b4e16154d 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -258,6 +258,21 @@
258 local-mac-address = [ 00 00 00 00 00 00 ]; 258 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupts = <2 5 0>; 259 interrupts = <2 5 0>;
260 interrupt-parent = <&mpc5200_pic>; 260 interrupt-parent = <&mpc5200_pic>;
261 phy-handle = <&phy0>;
262 };
263
264 mdio@3000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,mpc5200-mdio";
268 reg = <3000 400>; // fec range, since we need to setup fec interrupts
269 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
270 interrupt-parent = <&mpc5200_pic>;
271
272 phy0:ethernet-phy@1 {
273 device_type = "ethernet-phy";
274 reg = <1>;
275 };
261 }; 276 };
262 277
263 ata@3a00 { 278 ata@3a00 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 76951ab038e..2b0dde058f8 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -148,7 +148,6 @@
148 interrupt-parent = <&mpc5200_pic>; 148 interrupt-parent = <&mpc5200_pic>;
149 }; 149 };
150 150
151
152 spi@f00 { 151 spi@f00 {
153 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 152 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
154 reg = <f00 20>; 153 reg = <f00 20>;
@@ -209,10 +208,25 @@
209 ethernet@3000 { 208 ethernet@3000 {
210 device_type = "network"; 209 device_type = "network";
211 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
212 reg = <3000 800>; 211 reg = <3000 400>;
213 local-mac-address = [ 00 00 00 00 00 00 ]; 212 local-mac-address = [ 00 00 00 00 00 00 ];
214 interrupts = <2 5 0>; 213 interrupts = <2 5 0>;
215 interrupt-parent = <&mpc5200_pic>; 214 interrupt-parent = <&mpc5200_pic>;
215 phy-handle = <&phy0>;
216 };
217
218 mdio@3000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <3000 400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 interrupt-parent = <&mpc5200_pic>;
225
226 phy0: ethernet-phy@2 {
227 device_type = "ethernet-phy";
228 reg = <2>;
229 };
216 }; 230 };
217 231
218 ata@3a00 { 232 ata@3a00 {
@@ -223,11 +237,19 @@
223 }; 237 };
224 238
225 i2c@3d40 { 239 i2c@3d40 {
240 #address-cells = <1>;
241 #size-cells = <0>;
226 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 242 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
227 reg = <3d40 40>; 243 reg = <3d40 40>;
228 interrupts = <2 10 0>; 244 interrupts = <2 10 0>;
229 interrupt-parent = <&mpc5200_pic>; 245 interrupt-parent = <&mpc5200_pic>;
230 fsl5200-clocking; 246 fsl5200-clocking;
247
248 rtc@68 {
249 device_type = "rtc";
250 compatible = "dallas,ds1339";
251 reg = <68>;
252 };
231 }; 253 };
232 254
233 sram@8000 { 255 sram@8000 {
@@ -240,7 +262,8 @@
240 compatible = "fsl,lpb"; 262 compatible = "fsl,lpb";
241 #address-cells = <2>; 263 #address-cells = <2>;
242 #size-cells = <1>; 264 #size-cells = <1>;
243 ranges = <1 0 50000000 00010000 265 ranges = <0 0 ff000000 01000000
266 1 0 50000000 00010000
244 2 0 50010000 00010000 267 2 0 50010000 00010000
245 3 0 50020000 00010000>; 268 3 0 50020000 00010000>;
246 269
@@ -271,31 +294,15 @@
271 compatible = "promess,pro_module_dio"; 294 compatible = "promess,pro_module_dio";
272 reg = <3 800 2>; 295 reg = <3 800 2>;
273 }; 296 };
274 };
275 297
276 pci@f0000d00 { 298 // 16-bit flash device at LocalPlus Bus CS0
277 #interrupt-cells = <1>; 299 flash@0,0 {
278 #size-cells = <2>; 300 compatible = "cfi-flash";
279 #address-cells = <3>; 301 reg = <0 0 01000000>;
280 device_type = "pci"; 302 bank-width = <2>;
281 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 303 device-width = <2>;
282 reg = <f0000d00 100>; 304 #size-cells = <1>;
283 interrupt-map-mask = <f800 0 0 7>; 305 #address-cells = <1>;
284 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 306 };
285 c000 0 0 2 &mpc5200_pic 1 1 3
286 c000 0 0 3 &mpc5200_pic 1 2 3
287 c000 0 0 4 &mpc5200_pic 1 3 3
288
289 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
290 c800 0 0 2 &mpc5200_pic 1 2 3
291 c800 0 0 3 &mpc5200_pic 1 3 3
292 c800 0 0 4 &mpc5200_pic 0 0 3>;
293 clock-frequency = <0>; // From boot loader
294 interrupts = <2 8 0 2 9 0 2 a 0>;
295 interrupt-parent = <&mpc5200_pic>;
296 bus-range = <0 0>;
297 ranges = <42000000 0 80000000 80000000 0 20000000
298 02000000 0 a0000000 a0000000 0 10000000
299 01000000 0 00000000 b0000000 0 01000000>;
300 }; 307 };
301}; 308};
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 49c05e97386..eac8e1b5949 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -255,14 +255,14 @@
255 }; 255 };
256 256
257 sata@18000 { 257 sata@18000 {
258 compatible = "fsl,mpc8379-sata"; 258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
259 reg = <0x18000 0x1000>; 259 reg = <0x18000 0x1000>;
260 interrupts = <44 0x8>; 260 interrupts = <44 0x8>;
261 interrupt-parent = <&ipic>; 261 interrupt-parent = <&ipic>;
262 }; 262 };
263 263
264 sata@19000 { 264 sata@19000 {
265 compatible = "fsl,mpc8379-sata"; 265 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
266 reg = <0x19000 0x1000>; 266 reg = <0x19000 0x1000>;
267 interrupts = <45 0x8>; 267 interrupts = <45 0x8>;
268 interrupt-parent = <&ipic>; 268 interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 440aa4dfab0..5bc09ad016f 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -143,7 +143,6 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 { 146 usb@23000 {
148 compatible = "fsl-usb2-dr"; 147 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>; 148 reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
151 #size-cells = <0>; 150 #size-cells = <0>;
152 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>;
153 interrupts = <38 0x8>; 152 interrupts = <38 0x8>;
154 phy_type = "utmi"; 153 phy_type = "ulpi";
155 }; 154 };
156 155
157 mdio@24520 { 156 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 92711534b17..711f9a30f9a 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -143,7 +143,6 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 { 146 usb@23000 {
148 compatible = "fsl-usb2-dr"; 147 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>; 148 reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
151 #size-cells = <0>; 150 #size-cells = <0>;
152 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>;
153 interrupts = <38 0x8>; 152 interrupts = <38 0x8>;
154 phy_type = "utmi"; 153 phy_type = "ulpi";
155 }; 154 };
156 155
157 mdio@24520 { 156 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index fdb4a9255b2..6f78a9fd982 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -255,28 +255,28 @@
255 }; 255 };
256 256
257 sata@18000 { 257 sata@18000 {
258 compatible = "fsl,mpc8379-sata"; 258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
259 reg = <0x18000 0x1000>; 259 reg = <0x18000 0x1000>;
260 interrupts = <44 0x8>; 260 interrupts = <44 0x8>;
261 interrupt-parent = <&ipic>; 261 interrupt-parent = <&ipic>;
262 }; 262 };
263 263
264 sata@19000 { 264 sata@19000 {
265 compatible = "fsl,mpc8379-sata"; 265 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
266 reg = <0x19000 0x1000>; 266 reg = <0x19000 0x1000>;
267 interrupts = <45 0x8>; 267 interrupts = <45 0x8>;
268 interrupt-parent = <&ipic>; 268 interrupt-parent = <&ipic>;
269 }; 269 };
270 270
271 sata@1a000 { 271 sata@1a000 {
272 compatible = "fsl,mpc8379-sata"; 272 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
273 reg = <0x1a000 0x1000>; 273 reg = <0x1a000 0x1000>;
274 interrupts = <46 0x8>; 274 interrupts = <46 0x8>;
275 interrupt-parent = <&ipic>; 275 interrupt-parent = <&ipic>;
276 }; 276 };
277 277
278 sata@1b000 { 278 sata@1b000 {
279 compatible = "fsl,mpc8379-sata"; 279 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
280 reg = <0x1b000 0x1000>; 280 reg = <0x1b000 0x1000>;
281 interrupts = <47 0x8>; 281 interrupts = <47 0x8>;
282 interrupt-parent = <&ipic>; 282 interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 0dda2fc558f..c11ceb7d329 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -143,7 +143,6 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 { 146 usb@23000 {
148 compatible = "fsl-usb2-dr"; 147 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>; 148 reg = <0x23000 0x1000>;
@@ -151,7 +150,7 @@
151 #size-cells = <0>; 150 #size-cells = <0>;
152 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>;
153 interrupts = <38 0x8>; 152 interrupts = <38 0x8>;
154 phy_type = "utmi"; 153 phy_type = "ulpi";
155 }; 154 };
156 155
157 mdio@24520 { 156 mdio@24520 {
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index c86464f007d..65bcea6a017 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -127,10 +127,25 @@
127 ethernet@3000 { 127 ethernet@3000 {
128 device_type = "network"; 128 device_type = "network";
129 compatible = "fsl,mpc5200-fec"; 129 compatible = "fsl,mpc5200-fec";
130 reg = <3000 800>; 130 reg = <3000 400>;
131 local-mac-address = [ 00 00 00 00 00 00 ]; 131 local-mac-address = [ 00 00 00 00 00 00 ];
132 interrupts = <2 5 0>; 132 interrupts = <2 5 0>;
133 interrupt-parent = <&mpc5200_pic>; 133 interrupt-parent = <&mpc5200_pic>;
134 phy-handle = <&phy0>;
135 };
136
137 mdio@3000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
141 reg = <3000 400>; // fec range, since we need to setup fec interrupts
142 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
143 interrupt-parent = <&mpc5200_pic>;
144
145 phy0: ethernet-phy@0 {
146 device_type = "ethernet-phy";
147 reg = <0>;
148 };
134 }; 149 };
135 150
136 ata@3a00 { 151 ata@3a00 {
@@ -141,11 +156,19 @@
141 }; 156 };
142 157
143 i2c@3d40 { 158 i2c@3d40 {
159 #address-cells = <1>;
160 #size-cells = <0>;
144 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 161 compatible = "fsl,mpc5200-i2c","fsl-i2c";
145 reg = <3d40 40>; 162 reg = <3d40 40>;
146 interrupts = <2 10 0>; 163 interrupts = <2 10 0>;
147 interrupt-parent = <&mpc5200_pic>; 164 interrupt-parent = <&mpc5200_pic>;
148 fsl5200-clocking; 165 fsl5200-clocking;
166
167 rtc@68 {
168 device_type = "rtc";
169 compatible = "dallas,ds1307";
170 reg = <68>;
171 };
149 }; 172 };
150 173
151 sram@8000 { 174 sram@8000 {
@@ -154,6 +177,23 @@
154 }; 177 };
155 }; 178 };
156 179
180 lpb {
181 model = "fsl,lpb";
182 compatible = "fsl,lpb";
183 #address-cells = <2>;
184 #size-cells = <1>;
185 ranges = <0 0 fc000000 02000000>;
186
187 flash@0,0 {
188 compatible = "cfi-flash";
189 reg = <0 0 02000000>;
190 bank-width = <4>;
191 device-width = <2>;
192 #size-cells = <1>;
193 #address-cells = <1>;
194 };
195 };
196
157 pci@f0000d00 { 197 pci@f0000d00 {
158 #interrupt-cells = <1>; 198 #interrupt-cells = <1>;
159 #size-cells = <2>; 199 #size-cells = <2>;
diff --git a/arch/powerpc/configs/mpc832x_mds_defconfig b/arch/powerpc/configs/mpc832x_mds_defconfig
index 79d228f84c5..50cceda8994 100644
--- a/arch/powerpc/configs/mpc832x_mds_defconfig
+++ b/arch/powerpc/configs/mpc832x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:16 2008 4# Mon Mar 31 11:36:51 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -628,8 +628,7 @@ CONFIG_LEGACY_PTY_COUNT=256
628# CONFIG_IPMI_HANDLER is not set 628# CONFIG_IPMI_HANDLER is not set
629CONFIG_HW_RANDOM=y 629CONFIG_HW_RANDOM=y
630# CONFIG_NVRAM is not set 630# CONFIG_NVRAM is not set
631CONFIG_GEN_RTC=y 631# CONFIG_GEN_RTC is not set
632# CONFIG_GEN_RTC_X is not set
633# CONFIG_R3964 is not set 632# CONFIG_R3964 is not set
634# CONFIG_APPLICOM is not set 633# CONFIG_APPLICOM is not set
635# CONFIG_RAW_DRIVER is not set 634# CONFIG_RAW_DRIVER is not set
@@ -824,10 +823,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
824# CONFIG_EDAC is not set 823# CONFIG_EDAC is not set
825CONFIG_RTC_LIB=y 824CONFIG_RTC_LIB=y
826CONFIG_RTC_CLASS=y 825CONFIG_RTC_CLASS=y
827
828#
829# Conflicting RTC option has been selected, check GEN_RTC and RTC
830#
831CONFIG_RTC_HCTOSYS=y 826CONFIG_RTC_HCTOSYS=y
832CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 827CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
833# CONFIG_RTC_DEBUG is not set 828# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc834x_mds_defconfig b/arch/powerpc/configs/mpc834x_mds_defconfig
index 9360144942f..b4e82c0e2be 100644
--- a/arch/powerpc/configs/mpc834x_mds_defconfig
+++ b/arch/powerpc/configs/mpc834x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:20 2008 4# Mon Mar 31 11:36:56 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -571,8 +571,7 @@ CONFIG_LEGACY_PTY_COUNT=256
571# CONFIG_IPMI_HANDLER is not set 571# CONFIG_IPMI_HANDLER is not set
572# CONFIG_HW_RANDOM is not set 572# CONFIG_HW_RANDOM is not set
573# CONFIG_NVRAM is not set 573# CONFIG_NVRAM is not set
574CONFIG_GEN_RTC=y 574# CONFIG_GEN_RTC is not set
575# CONFIG_GEN_RTC_X is not set
576# CONFIG_R3964 is not set 575# CONFIG_R3964 is not set
577# CONFIG_APPLICOM is not set 576# CONFIG_APPLICOM is not set
578# CONFIG_RAW_DRIVER is not set 577# CONFIG_RAW_DRIVER is not set
@@ -767,10 +766,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
767# CONFIG_EDAC is not set 766# CONFIG_EDAC is not set
768CONFIG_RTC_LIB=y 767CONFIG_RTC_LIB=y
769CONFIG_RTC_CLASS=y 768CONFIG_RTC_CLASS=y
770
771#
772# Conflicting RTC option has been selected, check GEN_RTC and RTC
773#
774CONFIG_RTC_HCTOSYS=y 769CONFIG_RTC_HCTOSYS=y
775CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 770CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
776# CONFIG_RTC_DEBUG is not set 771# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc836x_mds_defconfig b/arch/powerpc/configs/mpc836x_mds_defconfig
index 7c8b06046d5..d50a96eddcd 100644
--- a/arch/powerpc/configs/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/mpc836x_mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:21 2008 4# Mon Mar 31 11:36:57 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -626,8 +626,7 @@ CONFIG_LEGACY_PTY_COUNT=256
626# CONFIG_IPMI_HANDLER is not set 626# CONFIG_IPMI_HANDLER is not set
627CONFIG_HW_RANDOM=y 627CONFIG_HW_RANDOM=y
628# CONFIG_NVRAM is not set 628# CONFIG_NVRAM is not set
629CONFIG_GEN_RTC=y 629# CONFIG_GEN_RTC is not set
630# CONFIG_GEN_RTC_X is not set
631# CONFIG_R3964 is not set 630# CONFIG_R3964 is not set
632# CONFIG_APPLICOM is not set 631# CONFIG_APPLICOM is not set
633# CONFIG_RAW_DRIVER is not set 632# CONFIG_RAW_DRIVER is not set
@@ -822,10 +821,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
822# CONFIG_EDAC is not set 821# CONFIG_EDAC is not set
823CONFIG_RTC_LIB=y 822CONFIG_RTC_LIB=y
824CONFIG_RTC_CLASS=y 823CONFIG_RTC_CLASS=y
825
826#
827# Conflicting RTC option has been selected, check GEN_RTC and RTC
828#
829CONFIG_RTC_HCTOSYS=y 824CONFIG_RTC_HCTOSYS=y
830CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 825CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
831# CONFIG_RTC_DEBUG is not set 826# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc837x_rdb_defconfig b/arch/powerpc/configs/mpc837x_rdb_defconfig
index 44093a0eaf8..a6331769d88 100644
--- a/arch/powerpc/configs/mpc837x_rdb_defconfig
+++ b/arch/powerpc/configs/mpc837x_rdb_defconfig
@@ -684,7 +684,29 @@ CONFIG_USB_SUPPORT=y
684CONFIG_USB_ARCH_HAS_HCD=y 684CONFIG_USB_ARCH_HAS_HCD=y
685# CONFIG_USB_ARCH_HAS_OHCI is not set 685# CONFIG_USB_ARCH_HAS_OHCI is not set
686CONFIG_USB_ARCH_HAS_EHCI=y 686CONFIG_USB_ARCH_HAS_EHCI=y
687# CONFIG_USB is not set 687CONFIG_USB=y
688# CONFIG_USB_DEBUG is not set
689# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
690
691#
692# Miscellaneous USB options
693#
694# CONFIG_USB_DEVICEFS is not set
695CONFIG_USB_DEVICE_CLASS=y
696# CONFIG_USB_DYNAMIC_MINORS is not set
697# CONFIG_USB_OTG is not set
698
699#
700# USB Host Controller Drivers
701#
702CONFIG_USB_EHCI_HCD=y
703CONFIG_USB_EHCI_ROOT_HUB_TT=y
704# CONFIG_USB_EHCI_TT_NEWSCHED is not set
705CONFIG_USB_EHCI_FSL=y
706CONFIG_USB_EHCI_HCD_PPC_OF=y
707# CONFIG_USB_ISP116X_HCD is not set
708# CONFIG_USB_SL811_HCD is not set
709# CONFIG_USB_R8A66597_HCD is not set
688 710
689# 711#
690# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 712# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 1f6cf68e89f..029d2dab7de 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -690,7 +690,29 @@ CONFIG_USB_SUPPORT=y
690CONFIG_USB_ARCH_HAS_HCD=y 690CONFIG_USB_ARCH_HAS_HCD=y
691# CONFIG_USB_ARCH_HAS_OHCI is not set 691# CONFIG_USB_ARCH_HAS_OHCI is not set
692CONFIG_USB_ARCH_HAS_EHCI=y 692CONFIG_USB_ARCH_HAS_EHCI=y
693# CONFIG_USB is not set 693CONFIG_USB=y
694# CONFIG_USB_DEBUG is not set
695# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
696
697#
698# Miscellaneous USB options
699#
700# CONFIG_USB_DEVICEFS is not set
701CONFIG_USB_DEVICE_CLASS=y
702# CONFIG_USB_DYNAMIC_MINORS is not set
703# CONFIG_USB_OTG is not set
704
705#
706# USB Host Controller Drivers
707#
708CONFIG_USB_EHCI_HCD=y
709CONFIG_USB_EHCI_ROOT_HUB_TT=y
710# CONFIG_USB_EHCI_TT_NEWSCHED is not set
711CONFIG_USB_EHCI_FSL=y
712CONFIG_USB_EHCI_HCD_PPC_OF=y
713# CONFIG_USB_ISP116X_HCD is not set
714# CONFIG_USB_SL811_HCD is not set
715# CONFIG_USB_R8A66597_HCD is not set
694 716
695# 717#
696# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 718# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
diff --git a/arch/powerpc/configs/mpc8544_ds_defconfig b/arch/powerpc/configs/mpc8544_ds_defconfig
index c75b6aee76d..418bcdb5f91 100644
--- a/arch/powerpc/configs/mpc8544_ds_defconfig
+++ b/arch/powerpc/configs/mpc8544_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:26 2008 4# Mon Mar 31 11:37:03 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -742,8 +742,7 @@ CONFIG_LEGACY_PTY_COUNT=256
742# CONFIG_IPMI_HANDLER is not set 742# CONFIG_IPMI_HANDLER is not set
743# CONFIG_HW_RANDOM is not set 743# CONFIG_HW_RANDOM is not set
744CONFIG_NVRAM=y 744CONFIG_NVRAM=y
745CONFIG_GEN_RTC=y 745# CONFIG_GEN_RTC is not set
746CONFIG_GEN_RTC_X=y
747# CONFIG_R3964 is not set 746# CONFIG_R3964 is not set
748# CONFIG_APPLICOM is not set 747# CONFIG_APPLICOM is not set
749# CONFIG_RAW_DRIVER is not set 748# CONFIG_RAW_DRIVER is not set
@@ -1209,10 +1208,6 @@ CONFIG_USB_MON=y
1209# CONFIG_EDAC is not set 1208# CONFIG_EDAC is not set
1210CONFIG_RTC_LIB=y 1209CONFIG_RTC_LIB=y
1211CONFIG_RTC_CLASS=y 1210CONFIG_RTC_CLASS=y
1212
1213#
1214# Conflicting RTC option has been selected, check GEN_RTC and RTC
1215#
1216CONFIG_RTC_HCTOSYS=y 1211CONFIG_RTC_HCTOSYS=y
1217CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1212CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1218# CONFIG_RTC_DEBUG is not set 1213# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8568mds_defconfig b/arch/powerpc/configs/mpc8568mds_defconfig
index e7da4b96cde..2b866b38560 100644
--- a/arch/powerpc/configs/mpc8568mds_defconfig
+++ b/arch/powerpc/configs/mpc8568mds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:28 2008 4# Mon Mar 31 11:37:05 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -629,8 +629,7 @@ CONFIG_LEGACY_PTY_COUNT=256
629# CONFIG_IPMI_HANDLER is not set 629# CONFIG_IPMI_HANDLER is not set
630CONFIG_HW_RANDOM=y 630CONFIG_HW_RANDOM=y
631# CONFIG_NVRAM is not set 631# CONFIG_NVRAM is not set
632CONFIG_GEN_RTC=y 632# CONFIG_GEN_RTC is not set
633# CONFIG_GEN_RTC_X is not set
634# CONFIG_R3964 is not set 633# CONFIG_R3964 is not set
635# CONFIG_APPLICOM is not set 634# CONFIG_APPLICOM is not set
636# CONFIG_RAW_DRIVER is not set 635# CONFIG_RAW_DRIVER is not set
@@ -825,10 +824,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
825# CONFIG_EDAC is not set 824# CONFIG_EDAC is not set
826CONFIG_RTC_LIB=y 825CONFIG_RTC_LIB=y
827CONFIG_RTC_CLASS=y 826CONFIG_RTC_CLASS=y
828
829#
830# Conflicting RTC option has been selected, check GEN_RTC and RTC
831#
832CONFIG_RTC_HCTOSYS=y 827CONFIG_RTC_HCTOSYS=y
833CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 828CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
834# CONFIG_RTC_DEBUG is not set 829# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8572_ds_defconfig b/arch/powerpc/configs/mpc8572_ds_defconfig
index 460afe99c65..53aa6f3173a 100644
--- a/arch/powerpc/configs/mpc8572_ds_defconfig
+++ b/arch/powerpc/configs/mpc8572_ds_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:29 2008 4# Mon Mar 31 11:37:06 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -742,8 +742,7 @@ CONFIG_LEGACY_PTY_COUNT=256
742# CONFIG_IPMI_HANDLER is not set 742# CONFIG_IPMI_HANDLER is not set
743# CONFIG_HW_RANDOM is not set 743# CONFIG_HW_RANDOM is not set
744CONFIG_NVRAM=y 744CONFIG_NVRAM=y
745CONFIG_GEN_RTC=y 745# CONFIG_GEN_RTC is not set
746CONFIG_GEN_RTC_X=y
747# CONFIG_R3964 is not set 746# CONFIG_R3964 is not set
748# CONFIG_APPLICOM is not set 747# CONFIG_APPLICOM is not set
749# CONFIG_RAW_DRIVER is not set 748# CONFIG_RAW_DRIVER is not set
@@ -1209,10 +1208,6 @@ CONFIG_USB_MON=y
1209# CONFIG_EDAC is not set 1208# CONFIG_EDAC is not set
1210CONFIG_RTC_LIB=y 1209CONFIG_RTC_LIB=y
1211CONFIG_RTC_CLASS=y 1210CONFIG_RTC_CLASS=y
1212
1213#
1214# Conflicting RTC option has been selected, check GEN_RTC and RTC
1215#
1216CONFIG_RTC_HCTOSYS=y 1211CONFIG_RTC_HCTOSYS=y
1217CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1212CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1218# CONFIG_RTC_DEBUG is not set 1213# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 615e4c1bf73..2075722911b 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:31 2008 4# Mon Mar 31 11:37:08 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -750,8 +750,7 @@ CONFIG_LEGACY_PTY_COUNT=256
750# CONFIG_IPMI_HANDLER is not set 750# CONFIG_IPMI_HANDLER is not set
751# CONFIG_HW_RANDOM is not set 751# CONFIG_HW_RANDOM is not set
752CONFIG_NVRAM=y 752CONFIG_NVRAM=y
753CONFIG_GEN_RTC=y 753# CONFIG_GEN_RTC is not set
754CONFIG_GEN_RTC_X=y
755# CONFIG_R3964 is not set 754# CONFIG_R3964 is not set
756# CONFIG_APPLICOM is not set 755# CONFIG_APPLICOM is not set
757# CONFIG_RAW_DRIVER is not set 756# CONFIG_RAW_DRIVER is not set
@@ -1217,10 +1216,6 @@ CONFIG_USB_MON=y
1217# CONFIG_EDAC is not set 1216# CONFIG_EDAC is not set
1218CONFIG_RTC_LIB=y 1217CONFIG_RTC_LIB=y
1219CONFIG_RTC_CLASS=y 1218CONFIG_RTC_CLASS=y
1220
1221#
1222# Conflicting RTC option has been selected, check GEN_RTC and RTC
1223#
1224CONFIG_RTC_HCTOSYS=y 1219CONFIG_RTC_HCTOSYS=y
1225CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1220CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1226# CONFIG_RTC_DEBUG is not set 1221# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/mpc8641_hpcn_defconfig b/arch/powerpc/configs/mpc8641_hpcn_defconfig
index 994e7681796..d01dcdb70bd 100644
--- a/arch/powerpc/configs/mpc8641_hpcn_defconfig
+++ b/arch/powerpc/configs/mpc8641_hpcn_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:34 2008 4# Mon Mar 31 11:37:11 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -736,8 +736,7 @@ CONFIG_LEGACY_PTY_COUNT=256
736# CONFIG_IPMI_HANDLER is not set 736# CONFIG_IPMI_HANDLER is not set
737# CONFIG_HW_RANDOM is not set 737# CONFIG_HW_RANDOM is not set
738CONFIG_NVRAM=y 738CONFIG_NVRAM=y
739CONFIG_GEN_RTC=y 739# CONFIG_GEN_RTC is not set
740CONFIG_GEN_RTC_X=y
741# CONFIG_R3964 is not set 740# CONFIG_R3964 is not set
742# CONFIG_APPLICOM is not set 741# CONFIG_APPLICOM is not set
743# CONFIG_RAW_DRIVER is not set 742# CONFIG_RAW_DRIVER is not set
@@ -1203,10 +1202,6 @@ CONFIG_USB_MON=y
1203# CONFIG_EDAC is not set 1202# CONFIG_EDAC is not set
1204CONFIG_RTC_LIB=y 1203CONFIG_RTC_LIB=y
1205CONFIG_RTC_CLASS=y 1204CONFIG_RTC_CLASS=y
1206
1207#
1208# Conflicting RTC option has been selected, check GEN_RTC and RTC
1209#
1210CONFIG_RTC_HCTOSYS=y 1205CONFIG_RTC_HCTOSYS=y
1211CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1206CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1212# CONFIG_RTC_DEBUG is not set 1207# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig
index 797f0dfebde..09f306248f2 100644
--- a/arch/powerpc/configs/pasemi_defconfig
+++ b/arch/powerpc/configs/pasemi_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc6 3# Linux kernel version: 2.6.25-rc6
4# Tue Jan 15 10:26:10 2008 4# Tue Mar 25 10:25:48 2008
5# 5#
6CONFIG_PPC64=y 6CONFIG_PPC64=y
7 7
@@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y
27CONFIG_GENERIC_TIME_VSYSCALL=y 27CONFIG_GENERIC_TIME_VSYSCALL=y
28CONFIG_GENERIC_CLOCKEVENTS=y 28CONFIG_GENERIC_CLOCKEVENTS=y
29CONFIG_GENERIC_HARDIRQS=y 29CONFIG_GENERIC_HARDIRQS=y
30CONFIG_HAVE_SETUP_PER_CPU_AREA=y
30CONFIG_IRQ_PER_CPU=y 31CONFIG_IRQ_PER_CPU=y
31CONFIG_RWSEM_XCHGADD_ALGORITHM=y 32CONFIG_RWSEM_XCHGADD_ALGORITHM=y
32CONFIG_ARCH_HAS_ILOG2_U32=y 33CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -67,17 +68,19 @@ CONFIG_SYSVIPC_SYSCTL=y
67# CONFIG_POSIX_MQUEUE is not set 68# CONFIG_POSIX_MQUEUE is not set
68# CONFIG_BSD_PROCESS_ACCT is not set 69# CONFIG_BSD_PROCESS_ACCT is not set
69# CONFIG_TASKSTATS is not set 70# CONFIG_TASKSTATS is not set
70# CONFIG_USER_NS is not set
71# CONFIG_PID_NS is not set
72# CONFIG_AUDIT is not set 71# CONFIG_AUDIT is not set
73# CONFIG_IKCONFIG is not set 72# CONFIG_IKCONFIG is not set
74CONFIG_LOG_BUF_SHIFT=17 73CONFIG_LOG_BUF_SHIFT=17
75# CONFIG_CGROUPS is not set 74# CONFIG_CGROUPS is not set
76CONFIG_FAIR_GROUP_SCHED=y 75# CONFIG_GROUP_SCHED is not set
77CONFIG_FAIR_USER_SCHED=y
78# CONFIG_FAIR_CGROUP_SCHED is not set
79CONFIG_SYSFS_DEPRECATED=y 76CONFIG_SYSFS_DEPRECATED=y
77CONFIG_SYSFS_DEPRECATED_V2=y
80# CONFIG_RELAY is not set 78# CONFIG_RELAY is not set
79CONFIG_NAMESPACES=y
80# CONFIG_UTS_NS is not set
81# CONFIG_IPC_NS is not set
82# CONFIG_USER_NS is not set
83# CONFIG_PID_NS is not set
81CONFIG_BLK_DEV_INITRD=y 84CONFIG_BLK_DEV_INITRD=y
82CONFIG_INITRAMFS_SOURCE="" 85CONFIG_INITRAMFS_SOURCE=""
83# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 86# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -91,11 +94,13 @@ CONFIG_HOTPLUG=y
91CONFIG_PRINTK=y 94CONFIG_PRINTK=y
92CONFIG_BUG=y 95CONFIG_BUG=y
93CONFIG_ELF_CORE=y 96CONFIG_ELF_CORE=y
97CONFIG_COMPAT_BRK=y
94CONFIG_BASE_FULL=y 98CONFIG_BASE_FULL=y
95CONFIG_FUTEX=y 99CONFIG_FUTEX=y
96CONFIG_ANON_INODES=y 100CONFIG_ANON_INODES=y
97CONFIG_EPOLL=y 101CONFIG_EPOLL=y
98CONFIG_SIGNALFD=y 102CONFIG_SIGNALFD=y
103CONFIG_TIMERFD=y
99CONFIG_EVENTFD=y 104CONFIG_EVENTFD=y
100CONFIG_SHMEM=y 105CONFIG_SHMEM=y
101CONFIG_VM_EVENT_COUNTERS=y 106CONFIG_VM_EVENT_COUNTERS=y
@@ -103,6 +108,15 @@ CONFIG_SLUB_DEBUG=y
103# CONFIG_SLAB is not set 108# CONFIG_SLAB is not set
104CONFIG_SLUB=y 109CONFIG_SLUB=y
105# CONFIG_SLOB is not set 110# CONFIG_SLOB is not set
111CONFIG_PROFILING=y
112# CONFIG_MARKERS is not set
113CONFIG_OPROFILE=y
114CONFIG_HAVE_OPROFILE=y
115# CONFIG_KPROBES is not set
116CONFIG_HAVE_KPROBES=y
117CONFIG_HAVE_KRETPROBES=y
118CONFIG_PROC_PAGE_MONITOR=y
119CONFIG_SLABINFO=y
106CONFIG_RT_MUTEXES=y 120CONFIG_RT_MUTEXES=y
107# CONFIG_TINY_SHMEM is not set 121# CONFIG_TINY_SHMEM is not set
108CONFIG_BASE_SMALL=0 122CONFIG_BASE_SMALL=0
@@ -130,6 +144,7 @@ CONFIG_DEFAULT_AS=y
130# CONFIG_DEFAULT_CFQ is not set 144# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set 145# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory" 146CONFIG_DEFAULT_IOSCHED="anticipatory"
147CONFIG_CLASSIC_RCU=y
133 148
134# 149#
135# Platform support 150# Platform support
@@ -140,8 +155,8 @@ CONFIG_PPC_MULTIPLATFORM=y
140# CONFIG_PPC_86xx is not set 155# CONFIG_PPC_86xx is not set
141# CONFIG_PPC_PSERIES is not set 156# CONFIG_PPC_PSERIES is not set
142# CONFIG_PPC_ISERIES is not set 157# CONFIG_PPC_ISERIES is not set
143# CONFIG_PPC_MPC52xx is not set 158# CONFIG_PPC_MPC512x is not set
144# CONFIG_PPC_MPC5200 is not set 159# CONFIG_PPC_MPC5121 is not set
145# CONFIG_PPC_PMAC is not set 160# CONFIG_PPC_PMAC is not set
146# CONFIG_PPC_MAPLE is not set 161# CONFIG_PPC_MAPLE is not set
147CONFIG_PPC_PASEMI=y 162CONFIG_PPC_PASEMI=y
@@ -159,6 +174,7 @@ CONFIG_PPC_PASEMI_MDIO=y
159# CONFIG_PPC_IBM_CELL_BLADE is not set 174# CONFIG_PPC_IBM_CELL_BLADE is not set
160# CONFIG_PQ2ADS is not set 175# CONFIG_PQ2ADS is not set
161CONFIG_PPC_NATIVE=y 176CONFIG_PPC_NATIVE=y
177# CONFIG_IPIC is not set
162CONFIG_MPIC=y 178CONFIG_MPIC=y
163# CONFIG_MPIC_WEIRD is not set 179# CONFIG_MPIC_WEIRD is not set
164# CONFIG_PPC_I8259 is not set 180# CONFIG_PPC_I8259 is not set
@@ -189,7 +205,6 @@ CONFIG_CPU_FREQ_GOV_ONDEMAND=y
189# CPU Frequency drivers 205# CPU Frequency drivers
190# 206#
191CONFIG_PPC_PASEMI_CPUFREQ=y 207CONFIG_PPC_PASEMI_CPUFREQ=y
192# CONFIG_CPM2 is not set
193# CONFIG_FSL_ULI1575 is not set 208# CONFIG_FSL_ULI1575 is not set
194 209
195# 210#
@@ -204,16 +219,20 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
204# CONFIG_HZ_300 is not set 219# CONFIG_HZ_300 is not set
205CONFIG_HZ_1000=y 220CONFIG_HZ_1000=y
206CONFIG_HZ=1000 221CONFIG_HZ=1000
222# CONFIG_SCHED_HRTICK is not set
207CONFIG_PREEMPT_NONE=y 223CONFIG_PREEMPT_NONE=y
208# CONFIG_PREEMPT_VOLUNTARY is not set 224# CONFIG_PREEMPT_VOLUNTARY is not set
209# CONFIG_PREEMPT is not set 225# CONFIG_PREEMPT is not set
210# CONFIG_PREEMPT_BKL is not set
211CONFIG_BINFMT_ELF=y 226CONFIG_BINFMT_ELF=y
227CONFIG_COMPAT_BINFMT_ELF=y
212# CONFIG_BINFMT_MISC is not set 228# CONFIG_BINFMT_MISC is not set
213CONFIG_FORCE_MAX_ZONEORDER=9 229CONFIG_FORCE_MAX_ZONEORDER=9
214CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y 230CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
215CONFIG_IOMMU_VMERGE=y 231CONFIG_IOMMU_VMERGE=y
232CONFIG_IOMMU_HELPER=y
216CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 233CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
234CONFIG_ARCH_HAS_WALK_MEMORY=y
235CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
217# CONFIG_KEXEC is not set 236# CONFIG_KEXEC is not set
218# CONFIG_CRASH_DUMP is not set 237# CONFIG_CRASH_DUMP is not set
219# CONFIG_IRQ_ALL_CPUS is not set 238# CONFIG_IRQ_ALL_CPUS is not set
@@ -236,12 +255,12 @@ CONFIG_ZONE_DMA_FLAG=1
236CONFIG_BOUNCE=y 255CONFIG_BOUNCE=y
237CONFIG_PPC_HAS_HASH_64K=y 256CONFIG_PPC_HAS_HASH_64K=y
238CONFIG_PPC_64K_PAGES=y 257CONFIG_PPC_64K_PAGES=y
258# CONFIG_PPC_SUBPAGE_PROT is not set
239# CONFIG_SCHED_SMT is not set 259# CONFIG_SCHED_SMT is not set
240CONFIG_PROC_DEVICETREE=y 260CONFIG_PROC_DEVICETREE=y
241# CONFIG_CMDLINE_BOOL is not set 261# CONFIG_CMDLINE_BOOL is not set
242# CONFIG_PM is not set 262# CONFIG_PM is not set
243# CONFIG_SECCOMP is not set 263# CONFIG_SECCOMP is not set
244# CONFIG_WANT_DEVICE_TREE is not set
245CONFIG_ISA_DMA_API=y 264CONFIG_ISA_DMA_API=y
246 265
247# 266#
@@ -290,6 +309,7 @@ CONFIG_XFRM=y
290CONFIG_XFRM_USER=y 309CONFIG_XFRM_USER=y
291# CONFIG_XFRM_SUB_POLICY is not set 310# CONFIG_XFRM_SUB_POLICY is not set
292# CONFIG_XFRM_MIGRATE is not set 311# CONFIG_XFRM_MIGRATE is not set
312# CONFIG_XFRM_STATISTICS is not set
293CONFIG_NET_KEY=y 313CONFIG_NET_KEY=y
294# CONFIG_NET_KEY_MIGRATE is not set 314# CONFIG_NET_KEY_MIGRATE is not set
295CONFIG_INET=y 315CONFIG_INET=y
@@ -346,6 +366,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
346# 366#
347# CONFIG_NET_PKTGEN is not set 367# CONFIG_NET_PKTGEN is not set
348# CONFIG_HAMRADIO is not set 368# CONFIG_HAMRADIO is not set
369# CONFIG_CAN is not set
349# CONFIG_IRDA is not set 370# CONFIG_IRDA is not set
350# CONFIG_BT is not set 371# CONFIG_BT is not set
351# CONFIG_AF_RXRPC is not set 372# CONFIG_AF_RXRPC is not set
@@ -441,8 +462,10 @@ CONFIG_MTD_NAND=y
441CONFIG_MTD_NAND_IDS=y 462CONFIG_MTD_NAND_IDS=y
442# CONFIG_MTD_NAND_DISKONCHIP is not set 463# CONFIG_MTD_NAND_DISKONCHIP is not set
443# CONFIG_MTD_NAND_CAFE is not set 464# CONFIG_MTD_NAND_CAFE is not set
465CONFIG_MTD_NAND_PASEMI=y
444# CONFIG_MTD_NAND_PLATFORM is not set 466# CONFIG_MTD_NAND_PLATFORM is not set
445# CONFIG_MTD_ALAUDA is not set 467# CONFIG_MTD_ALAUDA is not set
468# CONFIG_MTD_NAND_FSL_ELBC is not set
446# CONFIG_MTD_ONENAND is not set 469# CONFIG_MTD_ONENAND is not set
447 470
448# 471#
@@ -465,7 +488,7 @@ CONFIG_BLK_DEV_LOOP=y
465CONFIG_BLK_DEV_RAM=y 488CONFIG_BLK_DEV_RAM=y
466CONFIG_BLK_DEV_RAM_COUNT=16 489CONFIG_BLK_DEV_RAM_COUNT=16
467CONFIG_BLK_DEV_RAM_SIZE=16384 490CONFIG_BLK_DEV_RAM_SIZE=16384
468CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 491# CONFIG_BLK_DEV_XIP is not set
469# CONFIG_CDROM_PKTCDVD is not set 492# CONFIG_CDROM_PKTCDVD is not set
470# CONFIG_ATA_OVER_ETH is not set 493# CONFIG_ATA_OVER_ETH is not set
471CONFIG_MISC_DEVICES=y 494CONFIG_MISC_DEVICES=y
@@ -473,11 +496,13 @@ CONFIG_MISC_DEVICES=y
473# CONFIG_EEPROM_93CX6 is not set 496# CONFIG_EEPROM_93CX6 is not set
474# CONFIG_SGI_IOC4 is not set 497# CONFIG_SGI_IOC4 is not set
475# CONFIG_TIFM_CORE is not set 498# CONFIG_TIFM_CORE is not set
499# CONFIG_ENCLOSURE_SERVICES is not set
500CONFIG_HAVE_IDE=y
476CONFIG_IDE=y 501CONFIG_IDE=y
477CONFIG_BLK_DEV_IDE=y 502CONFIG_BLK_DEV_IDE=y
478 503
479# 504#
480# Please see Documentation/ide.txt for help/info on IDE drives 505# Please see Documentation/ide/ide.txt for help/info on IDE drives
481# 506#
482# CONFIG_BLK_DEV_IDE_SATA is not set 507# CONFIG_BLK_DEV_IDE_SATA is not set
483CONFIG_BLK_DEV_IDEDISK=y 508CONFIG_BLK_DEV_IDEDISK=y
@@ -485,6 +510,7 @@ CONFIG_IDEDISK_MULTI_MODE=y
485# CONFIG_BLK_DEV_IDECS is not set 510# CONFIG_BLK_DEV_IDECS is not set
486# CONFIG_BLK_DEV_DELKIN is not set 511# CONFIG_BLK_DEV_DELKIN is not set
487CONFIG_BLK_DEV_IDECD=y 512CONFIG_BLK_DEV_IDECD=y
513CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
488# CONFIG_BLK_DEV_IDETAPE is not set 514# CONFIG_BLK_DEV_IDETAPE is not set
489# CONFIG_BLK_DEV_IDEFLOPPY is not set 515# CONFIG_BLK_DEV_IDEFLOPPY is not set
490CONFIG_BLK_DEV_IDESCSI=y 516CONFIG_BLK_DEV_IDESCSI=y
@@ -500,7 +526,6 @@ CONFIG_IDE_PROC_FS=y
500# 526#
501# PCI IDE chipsets support 527# PCI IDE chipsets support
502# 528#
503# CONFIG_IDEPCI_PCIBUS_ORDER is not set
504# CONFIG_BLK_DEV_GENERIC is not set 529# CONFIG_BLK_DEV_GENERIC is not set
505# CONFIG_BLK_DEV_OPTI621 is not set 530# CONFIG_BLK_DEV_OPTI621 is not set
506# CONFIG_BLK_DEV_AEC62XX is not set 531# CONFIG_BLK_DEV_AEC62XX is not set
@@ -528,7 +553,6 @@ CONFIG_IDE_PROC_FS=y
528# CONFIG_BLK_DEV_TRM290 is not set 553# CONFIG_BLK_DEV_TRM290 is not set
529# CONFIG_BLK_DEV_VIA82CXXX is not set 554# CONFIG_BLK_DEV_VIA82CXXX is not set
530# CONFIG_BLK_DEV_TC86C001 is not set 555# CONFIG_BLK_DEV_TC86C001 is not set
531# CONFIG_IDE_ARM is not set
532# CONFIG_BLK_DEV_IDEDMA is not set 556# CONFIG_BLK_DEV_IDEDMA is not set
533CONFIG_IDE_ARCH_OBSOLETE_INIT=y 557CONFIG_IDE_ARCH_OBSOLETE_INIT=y
534# CONFIG_BLK_DEV_HD is not set 558# CONFIG_BLK_DEV_HD is not set
@@ -593,6 +617,7 @@ CONFIG_SCSI_LOWLEVEL=y
593# CONFIG_SCSI_IPS is not set 617# CONFIG_SCSI_IPS is not set
594# CONFIG_SCSI_INITIO is not set 618# CONFIG_SCSI_INITIO is not set
595# CONFIG_SCSI_INIA100 is not set 619# CONFIG_SCSI_INIA100 is not set
620# CONFIG_SCSI_MVSAS is not set
596# CONFIG_SCSI_STEX is not set 621# CONFIG_SCSI_STEX is not set
597# CONFIG_SCSI_SYM53C8XX_2 is not set 622# CONFIG_SCSI_SYM53C8XX_2 is not set
598# CONFIG_SCSI_IPR is not set 623# CONFIG_SCSI_IPR is not set
@@ -646,6 +671,7 @@ CONFIG_ATA_GENERIC=y
646# CONFIG_PATA_MPIIX is not set 671# CONFIG_PATA_MPIIX is not set
647# CONFIG_PATA_OLDPIIX is not set 672# CONFIG_PATA_OLDPIIX is not set
648# CONFIG_PATA_NETCELL is not set 673# CONFIG_PATA_NETCELL is not set
674# CONFIG_PATA_NINJA32 is not set
649# CONFIG_PATA_NS87410 is not set 675# CONFIG_PATA_NS87410 is not set
650# CONFIG_PATA_NS87415 is not set 676# CONFIG_PATA_NS87415 is not set
651# CONFIG_PATA_OPTI is not set 677# CONFIG_PATA_OPTI is not set
@@ -699,7 +725,6 @@ CONFIG_DUMMY=y
699# CONFIG_EQUALIZER is not set 725# CONFIG_EQUALIZER is not set
700# CONFIG_TUN is not set 726# CONFIG_TUN is not set
701# CONFIG_VETH is not set 727# CONFIG_VETH is not set
702# CONFIG_IP1000 is not set
703# CONFIG_ARCNET is not set 728# CONFIG_ARCNET is not set
704CONFIG_PHYLIB=y 729CONFIG_PHYLIB=y
705 730
@@ -715,6 +740,7 @@ CONFIG_MARVELL_PHY=y
715# CONFIG_SMSC_PHY is not set 740# CONFIG_SMSC_PHY is not set
716# CONFIG_BROADCOM_PHY is not set 741# CONFIG_BROADCOM_PHY is not set
717# CONFIG_ICPLUS_PHY is not set 742# CONFIG_ICPLUS_PHY is not set
743# CONFIG_REALTEK_PHY is not set
718# CONFIG_FIXED_PHY is not set 744# CONFIG_FIXED_PHY is not set
719# CONFIG_MDIO_BITBANG is not set 745# CONFIG_MDIO_BITBANG is not set
720CONFIG_NET_ETHERNET=y 746CONFIG_NET_ETHERNET=y
@@ -742,6 +768,7 @@ CONFIG_NET_PCI=y
742# CONFIG_NE2K_PCI is not set 768# CONFIG_NE2K_PCI is not set
743# CONFIG_8139CP is not set 769# CONFIG_8139CP is not set
744# CONFIG_8139TOO is not set 770# CONFIG_8139TOO is not set
771# CONFIG_R6040 is not set
745# CONFIG_SIS900 is not set 772# CONFIG_SIS900 is not set
746# CONFIG_EPIC100 is not set 773# CONFIG_EPIC100 is not set
747# CONFIG_SUNDANCE is not set 774# CONFIG_SUNDANCE is not set
@@ -754,6 +781,9 @@ CONFIG_E1000=y
754CONFIG_E1000_NAPI=y 781CONFIG_E1000_NAPI=y
755# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 782# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
756# CONFIG_E1000E is not set 783# CONFIG_E1000E is not set
784# CONFIG_E1000E_ENABLED is not set
785# CONFIG_IP1000 is not set
786# CONFIG_IGB is not set
757# CONFIG_NS83820 is not set 787# CONFIG_NS83820 is not set
758# CONFIG_HAMACHI is not set 788# CONFIG_HAMACHI is not set
759# CONFIG_YELLOWFIN is not set 789# CONFIG_YELLOWFIN is not set
@@ -779,6 +809,7 @@ CONFIG_NETDEV_10000=y
779CONFIG_PASEMI_MAC=y 809CONFIG_PASEMI_MAC=y
780# CONFIG_MLX4_CORE is not set 810# CONFIG_MLX4_CORE is not set
781# CONFIG_TEHUTI is not set 811# CONFIG_TEHUTI is not set
812# CONFIG_BNX2X is not set
782# CONFIG_TR is not set 813# CONFIG_TR is not set
783 814
784# 815#
@@ -802,7 +833,6 @@ CONFIG_PASEMI_MAC=y
802# CONFIG_PPP is not set 833# CONFIG_PPP is not set
803# CONFIG_SLIP is not set 834# CONFIG_SLIP is not set
804# CONFIG_NET_FC is not set 835# CONFIG_NET_FC is not set
805# CONFIG_SHAPER is not set
806# CONFIG_NETCONSOLE is not set 836# CONFIG_NETCONSOLE is not set
807# CONFIG_NETPOLL is not set 837# CONFIG_NETPOLL is not set
808# CONFIG_NET_POLL_CONTROLLER is not set 838# CONFIG_NET_POLL_CONTROLLER is not set
@@ -861,6 +891,7 @@ CONFIG_VT_CONSOLE=y
861CONFIG_HW_CONSOLE=y 891CONFIG_HW_CONSOLE=y
862# CONFIG_VT_HW_CONSOLE_BINDING is not set 892# CONFIG_VT_HW_CONSOLE_BINDING is not set
863# CONFIG_SERIAL_NONSTANDARD is not set 893# CONFIG_SERIAL_NONSTANDARD is not set
894# CONFIG_NOZOMI is not set
864 895
865# 896#
866# Serial drivers 897# Serial drivers
@@ -886,8 +917,7 @@ CONFIG_LEGACY_PTY_COUNT=4
886# CONFIG_IPMI_HANDLER is not set 917# CONFIG_IPMI_HANDLER is not set
887CONFIG_HW_RANDOM=y 918CONFIG_HW_RANDOM=y
888CONFIG_HW_RANDOM_PASEMI=y 919CONFIG_HW_RANDOM_PASEMI=y
889CONFIG_GEN_RTC=y 920# CONFIG_GEN_RTC is not set
890CONFIG_GEN_RTC_X=y
891# CONFIG_R3964 is not set 921# CONFIG_R3964 is not set
892# CONFIG_APPLICOM is not set 922# CONFIG_APPLICOM is not set
893 923
@@ -897,6 +927,7 @@ CONFIG_GEN_RTC_X=y
897# CONFIG_SYNCLINK_CS is not set 927# CONFIG_SYNCLINK_CS is not set
898# CONFIG_CARDMAN_4000 is not set 928# CONFIG_CARDMAN_4000 is not set
899# CONFIG_CARDMAN_4040 is not set 929# CONFIG_CARDMAN_4040 is not set
930# CONFIG_IPWIRELESS is not set
900CONFIG_RAW_DRIVER=y 931CONFIG_RAW_DRIVER=y
901CONFIG_MAX_RAW_DEVS=256 932CONFIG_MAX_RAW_DEVS=256
902# CONFIG_HANGCHECK_TIMER is not set 933# CONFIG_HANGCHECK_TIMER is not set
@@ -944,13 +975,12 @@ CONFIG_I2C_PASEMI=y
944# 975#
945# Miscellaneous I2C Chip support 976# Miscellaneous I2C Chip support
946# 977#
947# CONFIG_SENSORS_DS1337 is not set
948# CONFIG_SENSORS_DS1374 is not set
949# CONFIG_DS1682 is not set 978# CONFIG_DS1682 is not set
950CONFIG_SENSORS_EEPROM=y 979CONFIG_SENSORS_EEPROM=y
951# CONFIG_SENSORS_PCF8574 is not set 980# CONFIG_SENSORS_PCF8574 is not set
952# CONFIG_SENSORS_PCA9539 is not set 981# CONFIG_PCF8575 is not set
953# CONFIG_SENSORS_PCF8591 is not set 982# CONFIG_SENSORS_PCF8591 is not set
983# CONFIG_TPS65010 is not set
954# CONFIG_SENSORS_MAX6875 is not set 984# CONFIG_SENSORS_MAX6875 is not set
955# CONFIG_SENSORS_TSL2550 is not set 985# CONFIG_SENSORS_TSL2550 is not set
956# CONFIG_I2C_DEBUG_CORE is not set 986# CONFIG_I2C_DEBUG_CORE is not set
@@ -975,6 +1005,7 @@ CONFIG_HWMON_VID=y
975# CONFIG_SENSORS_ADM1031 is not set 1005# CONFIG_SENSORS_ADM1031 is not set
976# CONFIG_SENSORS_ADM9240 is not set 1006# CONFIG_SENSORS_ADM9240 is not set
977# CONFIG_SENSORS_ADT7470 is not set 1007# CONFIG_SENSORS_ADT7470 is not set
1008# CONFIG_SENSORS_ADT7473 is not set
978# CONFIG_SENSORS_ATXP1 is not set 1009# CONFIG_SENSORS_ATXP1 is not set
979# CONFIG_SENSORS_DS1621 is not set 1010# CONFIG_SENSORS_DS1621 is not set
980# CONFIG_SENSORS_I5K_AMB is not set 1011# CONFIG_SENSORS_I5K_AMB is not set
@@ -1004,6 +1035,7 @@ CONFIG_SENSORS_LM90=y
1004# CONFIG_SENSORS_SMSC47M1 is not set 1035# CONFIG_SENSORS_SMSC47M1 is not set
1005# CONFIG_SENSORS_SMSC47M192 is not set 1036# CONFIG_SENSORS_SMSC47M192 is not set
1006# CONFIG_SENSORS_SMSC47B397 is not set 1037# CONFIG_SENSORS_SMSC47B397 is not set
1038# CONFIG_SENSORS_ADS7828 is not set
1007# CONFIG_SENSORS_THMC50 is not set 1039# CONFIG_SENSORS_THMC50 is not set
1008# CONFIG_SENSORS_VIA686A is not set 1040# CONFIG_SENSORS_VIA686A is not set
1009# CONFIG_SENSORS_VT1211 is not set 1041# CONFIG_SENSORS_VT1211 is not set
@@ -1013,9 +1045,11 @@ CONFIG_SENSORS_LM90=y
1013# CONFIG_SENSORS_W83792D is not set 1045# CONFIG_SENSORS_W83792D is not set
1014# CONFIG_SENSORS_W83793 is not set 1046# CONFIG_SENSORS_W83793 is not set
1015# CONFIG_SENSORS_W83L785TS is not set 1047# CONFIG_SENSORS_W83L785TS is not set
1048# CONFIG_SENSORS_W83L786NG is not set
1016# CONFIG_SENSORS_W83627HF is not set 1049# CONFIG_SENSORS_W83627HF is not set
1017# CONFIG_SENSORS_W83627EHF is not set 1050# CONFIG_SENSORS_W83627EHF is not set
1018# CONFIG_HWMON_DEBUG_CHIP is not set 1051# CONFIG_HWMON_DEBUG_CHIP is not set
1052# CONFIG_THERMAL is not set
1019# CONFIG_WATCHDOG is not set 1053# CONFIG_WATCHDOG is not set
1020 1054
1021# 1055#
@@ -1183,6 +1217,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
1183# CONFIG_SND_BT87X is not set 1217# CONFIG_SND_BT87X is not set
1184# CONFIG_SND_CA0106 is not set 1218# CONFIG_SND_CA0106 is not set
1185# CONFIG_SND_CMIPCI is not set 1219# CONFIG_SND_CMIPCI is not set
1220# CONFIG_SND_OXYGEN is not set
1186# CONFIG_SND_CS4281 is not set 1221# CONFIG_SND_CS4281 is not set
1187# CONFIG_SND_CS46XX is not set 1222# CONFIG_SND_CS46XX is not set
1188# CONFIG_SND_CS5530 is not set 1223# CONFIG_SND_CS5530 is not set
@@ -1208,6 +1243,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
1208# CONFIG_SND_HDA_INTEL is not set 1243# CONFIG_SND_HDA_INTEL is not set
1209# CONFIG_SND_HDSP is not set 1244# CONFIG_SND_HDSP is not set
1210# CONFIG_SND_HDSPM is not set 1245# CONFIG_SND_HDSPM is not set
1246# CONFIG_SND_HIFIER is not set
1211# CONFIG_SND_ICE1712 is not set 1247# CONFIG_SND_ICE1712 is not set
1212# CONFIG_SND_ICE1724 is not set 1248# CONFIG_SND_ICE1724 is not set
1213# CONFIG_SND_INTEL8X0 is not set 1249# CONFIG_SND_INTEL8X0 is not set
@@ -1225,6 +1261,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
1225# CONFIG_SND_TRIDENT is not set 1261# CONFIG_SND_TRIDENT is not set
1226# CONFIG_SND_VIA82XX is not set 1262# CONFIG_SND_VIA82XX is not set
1227# CONFIG_SND_VIA82XX_MODEM is not set 1263# CONFIG_SND_VIA82XX_MODEM is not set
1264# CONFIG_SND_VIRTUOSO is not set
1228# CONFIG_SND_VX222 is not set 1265# CONFIG_SND_VX222 is not set
1229# CONFIG_SND_YMFPCI is not set 1266# CONFIG_SND_YMFPCI is not set
1230 1267
@@ -1259,6 +1296,10 @@ CONFIG_SND_USB_USX2Y=y
1259# 1296#
1260 1297
1261# 1298#
1299# ALSA SoC audio for Freescale SOCs
1300#
1301
1302#
1262# Open Sound System 1303# Open Sound System
1263# 1304#
1264# CONFIG_SOUND_PRIME is not set 1305# CONFIG_SOUND_PRIME is not set
@@ -1280,6 +1321,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
1280CONFIG_USB_ARCH_HAS_EHCI=y 1321CONFIG_USB_ARCH_HAS_EHCI=y
1281CONFIG_USB=y 1322CONFIG_USB=y
1282# CONFIG_USB_DEBUG is not set 1323# CONFIG_USB_DEBUG is not set
1324# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1283 1325
1284# 1326#
1285# Miscellaneous USB options 1327# Miscellaneous USB options
@@ -1293,17 +1335,14 @@ CONFIG_USB_DEVICEFS=y
1293# USB Host Controller Drivers 1335# USB Host Controller Drivers
1294# 1336#
1295CONFIG_USB_EHCI_HCD=y 1337CONFIG_USB_EHCI_HCD=y
1296# CONFIG_USB_EHCI_SPLIT_ISO is not set
1297# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1338# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1298# CONFIG_USB_EHCI_TT_NEWSCHED is not set 1339# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1340CONFIG_USB_EHCI_HCD_PPC_OF=y
1299# CONFIG_USB_ISP116X_HCD is not set 1341# CONFIG_USB_ISP116X_HCD is not set
1300CONFIG_USB_OHCI_HCD=y 1342CONFIG_USB_OHCI_HCD=y
1301CONFIG_USB_OHCI_HCD_PPC_OF=y 1343# CONFIG_USB_OHCI_HCD_PPC_OF is not set
1302CONFIG_USB_OHCI_HCD_PPC_OF_BE=y 1344# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1303# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set 1345# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1304CONFIG_USB_OHCI_HCD_PCI=y
1305CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
1306CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
1307CONFIG_USB_OHCI_LITTLE_ENDIAN=y 1346CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1308CONFIG_USB_UHCI_HCD=y 1347CONFIG_USB_UHCI_HCD=y
1309CONFIG_USB_SL811_HCD=y 1348CONFIG_USB_SL811_HCD=y
@@ -1348,10 +1387,6 @@ CONFIG_USB_LIBUSUAL=y
1348# 1387#
1349# USB port drivers 1388# USB port drivers
1350# 1389#
1351
1352#
1353# USB Serial Converter support
1354#
1355# CONFIG_USB_SERIAL is not set 1390# CONFIG_USB_SERIAL is not set
1356 1391
1357# 1392#
@@ -1377,16 +1412,9 @@ CONFIG_USB_LIBUSUAL=y
1377# CONFIG_USB_TRANCEVIBRATOR is not set 1412# CONFIG_USB_TRANCEVIBRATOR is not set
1378# CONFIG_USB_IOWARRIOR is not set 1413# CONFIG_USB_IOWARRIOR is not set
1379# CONFIG_USB_TEST is not set 1414# CONFIG_USB_TEST is not set
1380
1381#
1382# USB DSL modem support
1383#
1384
1385#
1386# USB Gadget Support
1387#
1388# CONFIG_USB_GADGET is not set 1415# CONFIG_USB_GADGET is not set
1389# CONFIG_MMC is not set 1416# CONFIG_MMC is not set
1417# CONFIG_MEMSTICK is not set
1390# CONFIG_NEW_LEDS is not set 1418# CONFIG_NEW_LEDS is not set
1391# CONFIG_INFINIBAND is not set 1419# CONFIG_INFINIBAND is not set
1392CONFIG_EDAC=y 1420CONFIG_EDAC=y
@@ -1425,6 +1453,7 @@ CONFIG_RTC_DRV_DS1307=y
1425# CONFIG_RTC_DRV_PCF8563 is not set 1453# CONFIG_RTC_DRV_PCF8563 is not set
1426# CONFIG_RTC_DRV_PCF8583 is not set 1454# CONFIG_RTC_DRV_PCF8583 is not set
1427# CONFIG_RTC_DRV_M41T80 is not set 1455# CONFIG_RTC_DRV_M41T80 is not set
1456# CONFIG_RTC_DRV_S35390A is not set
1428 1457
1429# 1458#
1430# SPI RTC drivers 1459# SPI RTC drivers
@@ -1434,9 +1463,10 @@ CONFIG_RTC_DRV_DS1307=y
1434# Platform RTC drivers 1463# Platform RTC drivers
1435# 1464#
1436# CONFIG_RTC_DRV_CMOS is not set 1465# CONFIG_RTC_DRV_CMOS is not set
1466# CONFIG_RTC_DRV_DS1511 is not set
1437# CONFIG_RTC_DRV_DS1553 is not set 1467# CONFIG_RTC_DRV_DS1553 is not set
1438# CONFIG_RTC_DRV_STK17TA8 is not set
1439# CONFIG_RTC_DRV_DS1742 is not set 1468# CONFIG_RTC_DRV_DS1742 is not set
1469# CONFIG_RTC_DRV_STK17TA8 is not set
1440# CONFIG_RTC_DRV_M48T86 is not set 1470# CONFIG_RTC_DRV_M48T86 is not set
1441# CONFIG_RTC_DRV_M48T59 is not set 1471# CONFIG_RTC_DRV_M48T59 is not set
1442# CONFIG_RTC_DRV_V3020 is not set 1472# CONFIG_RTC_DRV_V3020 is not set
@@ -1444,6 +1474,7 @@ CONFIG_RTC_DRV_DS1307=y
1444# 1474#
1445# on-CPU RTC drivers 1475# on-CPU RTC drivers
1446# 1476#
1477# CONFIG_DMADEVICES is not set
1447 1478
1448# 1479#
1449# Userspace I/O 1480# Userspace I/O
@@ -1471,12 +1502,10 @@ CONFIG_FS_POSIX_ACL=y
1471# CONFIG_XFS_FS is not set 1502# CONFIG_XFS_FS is not set
1472# CONFIG_GFS2_FS is not set 1503# CONFIG_GFS2_FS is not set
1473# CONFIG_OCFS2_FS is not set 1504# CONFIG_OCFS2_FS is not set
1474# CONFIG_MINIX_FS is not set 1505CONFIG_DNOTIFY=y
1475# CONFIG_ROMFS_FS is not set
1476CONFIG_INOTIFY=y 1506CONFIG_INOTIFY=y
1477CONFIG_INOTIFY_USER=y 1507CONFIG_INOTIFY_USER=y
1478# CONFIG_QUOTA is not set 1508# CONFIG_QUOTA is not set
1479CONFIG_DNOTIFY=y
1480CONFIG_AUTOFS_FS=y 1509CONFIG_AUTOFS_FS=y
1481CONFIG_AUTOFS4_FS=y 1510CONFIG_AUTOFS4_FS=y
1482# CONFIG_FUSE_FS is not set 1511# CONFIG_FUSE_FS is not set
@@ -1536,8 +1565,10 @@ CONFIG_JFFS2_RTIME=y
1536# CONFIG_JFFS2_RUBIN is not set 1565# CONFIG_JFFS2_RUBIN is not set
1537# CONFIG_CRAMFS is not set 1566# CONFIG_CRAMFS is not set
1538# CONFIG_VXFS_FS is not set 1567# CONFIG_VXFS_FS is not set
1568# CONFIG_MINIX_FS is not set
1539# CONFIG_HPFS_FS is not set 1569# CONFIG_HPFS_FS is not set
1540# CONFIG_QNX4FS_FS is not set 1570# CONFIG_QNX4FS_FS is not set
1571# CONFIG_ROMFS_FS is not set
1541# CONFIG_SYSV_FS is not set 1572# CONFIG_SYSV_FS is not set
1542# CONFIG_UFS_FS is not set 1573# CONFIG_UFS_FS is not set
1543CONFIG_NETWORK_FILESYSTEMS=y 1574CONFIG_NETWORK_FILESYSTEMS=y
@@ -1629,7 +1660,6 @@ CONFIG_NLS_ISO8859_1=y
1629# CONFIG_NLS_KOI8_U is not set 1660# CONFIG_NLS_KOI8_U is not set
1630# CONFIG_NLS_UTF8 is not set 1661# CONFIG_NLS_UTF8 is not set
1631# CONFIG_DLM is not set 1662# CONFIG_DLM is not set
1632# CONFIG_UCC_SLOW is not set
1633 1663
1634# 1664#
1635# Library routines 1665# Library routines
@@ -1647,11 +1677,6 @@ CONFIG_PLIST=y
1647CONFIG_HAS_IOMEM=y 1677CONFIG_HAS_IOMEM=y
1648CONFIG_HAS_IOPORT=y 1678CONFIG_HAS_IOPORT=y
1649CONFIG_HAS_DMA=y 1679CONFIG_HAS_DMA=y
1650CONFIG_INSTRUMENTATION=y
1651CONFIG_PROFILING=y
1652CONFIG_OPROFILE=y
1653# CONFIG_KPROBES is not set
1654# CONFIG_MARKERS is not set
1655 1680
1656# 1681#
1657# Kernel hacking 1682# Kernel hacking
@@ -1670,6 +1695,7 @@ CONFIG_DETECT_SOFTLOCKUP=y
1670# CONFIG_SCHEDSTATS is not set 1695# CONFIG_SCHEDSTATS is not set
1671# CONFIG_TIMER_STATS is not set 1696# CONFIG_TIMER_STATS is not set
1672# CONFIG_SLUB_DEBUG_ON is not set 1697# CONFIG_SLUB_DEBUG_ON is not set
1698# CONFIG_SLUB_STATS is not set
1673# CONFIG_DEBUG_RT_MUTEXES is not set 1699# CONFIG_DEBUG_RT_MUTEXES is not set
1674# CONFIG_RT_MUTEX_TESTER is not set 1700# CONFIG_RT_MUTEX_TESTER is not set
1675# CONFIG_DEBUG_SPINLOCK is not set 1701# CONFIG_DEBUG_SPINLOCK is not set
@@ -1682,9 +1708,9 @@ CONFIG_DEBUG_BUGVERBOSE=y
1682# CONFIG_DEBUG_VM is not set 1708# CONFIG_DEBUG_VM is not set
1683# CONFIG_DEBUG_LIST is not set 1709# CONFIG_DEBUG_LIST is not set
1684# CONFIG_DEBUG_SG is not set 1710# CONFIG_DEBUG_SG is not set
1685# CONFIG_FORCED_INLINING is not set
1686# CONFIG_BOOT_PRINTK_DELAY is not set 1711# CONFIG_BOOT_PRINTK_DELAY is not set
1687# CONFIG_RCU_TORTURE_TEST is not set 1712# CONFIG_RCU_TORTURE_TEST is not set
1713# CONFIG_BACKTRACE_SELF_TEST is not set
1688# CONFIG_FAULT_INJECTION is not set 1714# CONFIG_FAULT_INJECTION is not set
1689# CONFIG_SAMPLES is not set 1715# CONFIG_SAMPLES is not set
1690# CONFIG_DEBUG_STACKOVERFLOW is not set 1716# CONFIG_DEBUG_STACKOVERFLOW is not set
@@ -1710,7 +1736,9 @@ CONFIG_ASYNC_MEMCPY=y
1710CONFIG_ASYNC_XOR=y 1736CONFIG_ASYNC_XOR=y
1711CONFIG_CRYPTO=y 1737CONFIG_CRYPTO=y
1712CONFIG_CRYPTO_ALGAPI=y 1738CONFIG_CRYPTO_ALGAPI=y
1739CONFIG_CRYPTO_AEAD=y
1713CONFIG_CRYPTO_BLKCIPHER=y 1740CONFIG_CRYPTO_BLKCIPHER=y
1741# CONFIG_CRYPTO_SEQIV is not set
1714CONFIG_CRYPTO_HASH=y 1742CONFIG_CRYPTO_HASH=y
1715CONFIG_CRYPTO_MANAGER=y 1743CONFIG_CRYPTO_MANAGER=y
1716CONFIG_CRYPTO_HMAC=y 1744CONFIG_CRYPTO_HMAC=y
@@ -1729,6 +1757,9 @@ CONFIG_CRYPTO_CBC=y
1729# CONFIG_CRYPTO_PCBC is not set 1757# CONFIG_CRYPTO_PCBC is not set
1730# CONFIG_CRYPTO_LRW is not set 1758# CONFIG_CRYPTO_LRW is not set
1731# CONFIG_CRYPTO_XTS is not set 1759# CONFIG_CRYPTO_XTS is not set
1760# CONFIG_CRYPTO_CTR is not set
1761# CONFIG_CRYPTO_GCM is not set
1762# CONFIG_CRYPTO_CCM is not set
1732# CONFIG_CRYPTO_CRYPTD is not set 1763# CONFIG_CRYPTO_CRYPTD is not set
1733CONFIG_CRYPTO_DES=y 1764CONFIG_CRYPTO_DES=y
1734# CONFIG_CRYPTO_FCRYPT is not set 1765# CONFIG_CRYPTO_FCRYPT is not set
@@ -1743,11 +1774,14 @@ CONFIG_CRYPTO_AES=y
1743# CONFIG_CRYPTO_KHAZAD is not set 1774# CONFIG_CRYPTO_KHAZAD is not set
1744# CONFIG_CRYPTO_ANUBIS is not set 1775# CONFIG_CRYPTO_ANUBIS is not set
1745# CONFIG_CRYPTO_SEED is not set 1776# CONFIG_CRYPTO_SEED is not set
1777# CONFIG_CRYPTO_SALSA20 is not set
1746# CONFIG_CRYPTO_DEFLATE is not set 1778# CONFIG_CRYPTO_DEFLATE is not set
1747# CONFIG_CRYPTO_MICHAEL_MIC is not set 1779# CONFIG_CRYPTO_MICHAEL_MIC is not set
1748# CONFIG_CRYPTO_CRC32C is not set 1780# CONFIG_CRYPTO_CRC32C is not set
1749# CONFIG_CRYPTO_CAMELLIA is not set 1781# CONFIG_CRYPTO_CAMELLIA is not set
1750# CONFIG_CRYPTO_TEST is not set 1782# CONFIG_CRYPTO_TEST is not set
1751# CONFIG_CRYPTO_AUTHENC is not set 1783CONFIG_CRYPTO_AUTHENC=y
1784# CONFIG_CRYPTO_LZO is not set
1752CONFIG_CRYPTO_HW=y 1785CONFIG_CRYPTO_HW=y
1786# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1753# CONFIG_PPC_CLOCK is not set 1787# CONFIG_PPC_CLOCK is not set
diff --git a/arch/powerpc/configs/prpmc2800_defconfig b/arch/powerpc/configs/prpmc2800_defconfig
index f53d55bbdd7..f9121685f11 100644
--- a/arch/powerpc/configs/prpmc2800_defconfig
+++ b/arch/powerpc/configs/prpmc2800_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:37 2008 4# Mon Mar 31 11:37:15 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -855,8 +855,7 @@ CONFIG_LEGACY_PTY_COUNT=256
855# CONFIG_IPMI_HANDLER is not set 855# CONFIG_IPMI_HANDLER is not set
856# CONFIG_HW_RANDOM is not set 856# CONFIG_HW_RANDOM is not set
857# CONFIG_NVRAM is not set 857# CONFIG_NVRAM is not set
858CONFIG_GEN_RTC=y 858# CONFIG_GEN_RTC is not set
859# CONFIG_GEN_RTC_X is not set
860# CONFIG_R3964 is not set 859# CONFIG_R3964 is not set
861# CONFIG_APPLICOM is not set 860# CONFIG_APPLICOM is not set
862# CONFIG_RAW_DRIVER is not set 861# CONFIG_RAW_DRIVER is not set
@@ -1129,10 +1128,6 @@ CONFIG_USB_MON=y
1129# CONFIG_EDAC is not set 1128# CONFIG_EDAC is not set
1130CONFIG_RTC_LIB=y 1129CONFIG_RTC_LIB=y
1131CONFIG_RTC_CLASS=y 1130CONFIG_RTC_CLASS=y
1132
1133#
1134# Conflicting RTC option has been selected, check GEN_RTC and RTC
1135#
1136CONFIG_RTC_HCTOSYS=y 1131CONFIG_RTC_HCTOSYS=y
1137CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1132CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1138# CONFIG_RTC_DEBUG is not set 1133# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig
index 8fc85747a0a..fdbfd39a3ac 100644
--- a/arch/powerpc/configs/storcenter_defconfig
+++ b/arch/powerpc/configs/storcenter_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc6 3# Linux kernel version: 2.6.25-rc7
4# Mon Mar 24 08:48:41 2008 4# Mon Mar 31 11:37:19 2008
5# 5#
6# CONFIG_PPC64 is not set 6# CONFIG_PPC64 is not set
7 7
@@ -717,8 +717,7 @@ CONFIG_LEGACY_PTY_COUNT=256
717# CONFIG_IPMI_HANDLER is not set 717# CONFIG_IPMI_HANDLER is not set
718CONFIG_HW_RANDOM=m 718CONFIG_HW_RANDOM=m
719CONFIG_NVRAM=y 719CONFIG_NVRAM=y
720CONFIG_GEN_RTC=y 720# CONFIG_GEN_RTC is not set
721# CONFIG_GEN_RTC_X is not set
722# CONFIG_R3964 is not set 721# CONFIG_R3964 is not set
723# CONFIG_APPLICOM is not set 722# CONFIG_APPLICOM is not set
724# CONFIG_RAW_DRIVER is not set 723# CONFIG_RAW_DRIVER is not set
@@ -931,10 +930,6 @@ CONFIG_USB_STORAGE=y
931# CONFIG_EDAC is not set 930# CONFIG_EDAC is not set
932CONFIG_RTC_LIB=y 931CONFIG_RTC_LIB=y
933CONFIG_RTC_CLASS=y 932CONFIG_RTC_CLASS=y
934
935#
936# Conflicting RTC option has been selected, check GEN_RTC and RTC
937#
938CONFIG_RTC_HCTOSYS=y 933CONFIG_RTC_HCTOSYS=y
939CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 934CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
940# CONFIG_RTC_DEBUG is not set 935# CONFIG_RTC_DEBUG is not set
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 11b4f6d9ffc..d3aee08e681 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -1387,12 +1387,14 @@ __secondary_start:
1387#ifdef CONFIG_PPC_ISERIES 1387#ifdef CONFIG_PPC_ISERIES
1388BEGIN_FW_FTR_SECTION 1388BEGIN_FW_FTR_SECTION
1389 ori r4,r4,MSR_EE 1389 ori r4,r4,MSR_EE
1390 li r8,1
1391 stb r8,PACAHARDIRQEN(r13)
1390END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1392END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1391#endif 1393#endif
1392BEGIN_FW_FTR_SECTION 1394BEGIN_FW_FTR_SECTION
1393 stb r7,PACASOFTIRQEN(r13)
1394 stb r7,PACAHARDIRQEN(r13) 1395 stb r7,PACAHARDIRQEN(r13)
1395END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 1396END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1397 stb r7,PACASOFTIRQEN(r13)
1396 1398
1397 mtspr SPRN_SRR0,r3 1399 mtspr SPRN_SRR0,r3
1398 mtspr SPRN_SRR1,r4 1400 mtspr SPRN_SRR1,r4
@@ -1520,15 +1522,14 @@ _INIT_GLOBAL(start_here_common)
1520#ifdef CONFIG_PPC_ISERIES 1522#ifdef CONFIG_PPC_ISERIES
1521BEGIN_FW_FTR_SECTION 1523BEGIN_FW_FTR_SECTION
1522 mfmsr r5 1524 mfmsr r5
1523 ori r5,r5,MSR_EE /* Hard Enabled */ 1525 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
1524 mtmsrd r5 1526 mtmsrd r5
1527 li r5,1
1525END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 1528END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1526#endif 1529#endif
1527BEGIN_FW_FTR_SECTION 1530 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
1528 stb r5,PACAHARDIRQEN(r13)
1529END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1530 1531
1531 bl .start_kernel 1532 bl .start_kernel
1532 1533
1533 /* Not reached */ 1534 /* Not reached */
1534 BUG_OPCODE 1535 BUG_OPCODE
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index b0e5deb4274..292163f5b39 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -143,7 +143,6 @@ void local_irq_restore(unsigned long en)
143 */ 143 */
144 if (local_paca->lppaca_ptr->int_dword.any_int) 144 if (local_paca->lppaca_ptr->int_dword.any_int)
145 iseries_handle_interrupts(); 145 iseries_handle_interrupts();
146 return;
147 } 146 }
148 147
149 /* 148 /*
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 59311ec0d42..4ec60552150 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -241,8 +241,12 @@ void discard_lazy_cpu_state(void)
241} 241}
242#endif /* CONFIG_SMP */ 242#endif /* CONFIG_SMP */
243 243
244static DEFINE_PER_CPU(unsigned long, current_dabr);
245
244int set_dabr(unsigned long dabr) 246int set_dabr(unsigned long dabr)
245{ 247{
248 __get_cpu_var(current_dabr) = dabr;
249
246#ifdef CONFIG_PPC_MERGE /* XXX for now */ 250#ifdef CONFIG_PPC_MERGE /* XXX for now */
247 if (ppc_md.set_dabr) 251 if (ppc_md.set_dabr)
248 return ppc_md.set_dabr(dabr); 252 return ppc_md.set_dabr(dabr);
@@ -259,8 +263,6 @@ int set_dabr(unsigned long dabr)
259DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); 263DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
260#endif 264#endif
261 265
262static DEFINE_PER_CPU(unsigned long, current_dabr);
263
264struct task_struct *__switch_to(struct task_struct *prev, 266struct task_struct *__switch_to(struct task_struct *prev,
265 struct task_struct *new) 267 struct task_struct *new)
266{ 268{
@@ -325,10 +327,8 @@ struct task_struct *__switch_to(struct task_struct *prev,
325 327
326#endif /* CONFIG_SMP */ 328#endif /* CONFIG_SMP */
327 329
328 if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr)) { 330 if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
329 set_dabr(new->thread.dabr); 331 set_dabr(new->thread.dabr);
330 __get_cpu_var(current_dabr) = new->thread.dabr;
331 }
332 332
333 new_thread = &new->thread; 333 new_thread = &new->thread;
334 old_thread = &current->thread; 334 old_thread = &current->thread;
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index f2276593f41..538baf46f15 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -356,7 +356,7 @@ static int rtas_excl_open(struct inode *inode, struct file *file)
356 356
357 /* Enforce exclusive open with use count of PDE */ 357 /* Enforce exclusive open with use count of PDE */
358 spin_lock(&flash_file_open_lock); 358 spin_lock(&flash_file_open_lock);
359 if (atomic_read(&dp->count) > 1) { 359 if (atomic_read(&dp->count) > 2) {
360 spin_unlock(&flash_file_open_lock); 360 spin_unlock(&flash_file_open_lock);
361 return -EBUSY; 361 return -EBUSY;
362 } 362 }
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 7f830a4888d..e10d76a860d 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -44,6 +44,9 @@ mmu_hash_lock:
44#ifdef CONFIG_SMP 44#ifdef CONFIG_SMP
45 .text 45 .text
46_GLOBAL(hash_page_sync) 46_GLOBAL(hash_page_sync)
47 mfmsr r10
48 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
49 mtmsr r0
47 lis r8,mmu_hash_lock@h 50 lis r8,mmu_hash_lock@h
48 ori r8,r8,mmu_hash_lock@l 51 ori r8,r8,mmu_hash_lock@l
49 lis r0,0x0fff 52 lis r0,0x0fff
@@ -60,8 +63,9 @@ _GLOBAL(hash_page_sync)
60 eieio 63 eieio
61 li r0,0 64 li r0,0
62 stw r0,0(r8) 65 stw r0,0(r8)
63 blr 66 mtmsr r10
64#endif 67 blr
68#endif /* CONFIG_SMP */
65 69
66/* 70/*
67 * Load a PTE into the hash table, if possible. 71 * Load a PTE into the hash table, if possible.
diff --git a/arch/powerpc/oprofile/cell/vma_map.c b/arch/powerpc/oprofile/cell/vma_map.c
index 76ec1d16aef..9a932177e70 100644
--- a/arch/powerpc/oprofile/cell/vma_map.c
+++ b/arch/powerpc/oprofile/cell/vma_map.c
@@ -92,7 +92,7 @@ vma_map_add(struct vma_to_fileoffset_map *map, unsigned int vma,
92 * A pointer to the first vma_map in the generated list 92 * A pointer to the first vma_map in the generated list
93 * of vma_maps is returned. */ 93 * of vma_maps is returned. */
94struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu, 94struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
95 unsigned long spu_elf_start) 95 unsigned long __spu_elf_start)
96{ 96{
97 static const unsigned char expected[EI_PAD] = { 97 static const unsigned char expected[EI_PAD] = {
98 [EI_MAG0] = ELFMAG0, 98 [EI_MAG0] = ELFMAG0,
@@ -107,9 +107,11 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
107 107
108 int grd_val; 108 int grd_val;
109 struct vma_to_fileoffset_map *map = NULL; 109 struct vma_to_fileoffset_map *map = NULL;
110 void __user *spu_elf_start = (void __user *)__spu_elf_start;
110 struct spu_overlay_info ovly; 111 struct spu_overlay_info ovly;
111 unsigned int overlay_tbl_offset = -1; 112 unsigned int overlay_tbl_offset = -1;
112 unsigned long phdr_start, shdr_start; 113 Elf32_Phdr __user *phdr_start;
114 Elf32_Shdr __user *shdr_start;
113 Elf32_Ehdr ehdr; 115 Elf32_Ehdr ehdr;
114 Elf32_Phdr phdr; 116 Elf32_Phdr phdr;
115 Elf32_Shdr shdr, shdr_str; 117 Elf32_Shdr shdr, shdr_str;
@@ -121,12 +123,12 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
121 unsigned int ovly_buf_table_sym = 0; 123 unsigned int ovly_buf_table_sym = 0;
122 unsigned int ovly_table_end_sym = 0; 124 unsigned int ovly_table_end_sym = 0;
123 unsigned int ovly_buf_table_end_sym = 0; 125 unsigned int ovly_buf_table_end_sym = 0;
124 unsigned long ovly_table; 126 struct spu_overlay_info __user *ovly_table;
125 unsigned int n_ovlys; 127 unsigned int n_ovlys;
126 128
127 /* Get and validate ELF header. */ 129 /* Get and validate ELF header. */
128 130
129 if (copy_from_user(&ehdr, (void *) spu_elf_start, sizeof (ehdr))) 131 if (copy_from_user(&ehdr, spu_elf_start, sizeof (ehdr)))
130 goto fail; 132 goto fail;
131 133
132 if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) { 134 if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) {
@@ -152,9 +154,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
152 154
153 /* Traverse program headers. */ 155 /* Traverse program headers. */
154 for (i = 0; i < ehdr.e_phnum; i++) { 156 for (i = 0; i < ehdr.e_phnum; i++) {
155 if (copy_from_user(&phdr, 157 if (copy_from_user(&phdr, phdr_start + i, sizeof(phdr)))
156 (void *) (phdr_start + i * sizeof(phdr)),
157 sizeof(phdr)))
158 goto fail; 158 goto fail;
159 159
160 if (phdr.p_type != PT_LOAD) 160 if (phdr.p_type != PT_LOAD)
@@ -171,9 +171,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
171 pr_debug("SPU_PROF: Created non-overlay maps\n"); 171 pr_debug("SPU_PROF: Created non-overlay maps\n");
172 /* Traverse section table and search for overlay-related symbols. */ 172 /* Traverse section table and search for overlay-related symbols. */
173 for (i = 0; i < ehdr.e_shnum; i++) { 173 for (i = 0; i < ehdr.e_shnum; i++) {
174 if (copy_from_user(&shdr, 174 if (copy_from_user(&shdr, shdr_start + i, sizeof(shdr)))
175 (void *) (shdr_start + i * sizeof(shdr)),
176 sizeof(shdr)))
177 goto fail; 175 goto fail;
178 176
179 if (shdr.sh_type != SHT_SYMTAB) 177 if (shdr.sh_type != SHT_SYMTAB)
@@ -182,8 +180,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
182 continue; 180 continue;
183 181
184 if (copy_from_user(&shdr_str, 182 if (copy_from_user(&shdr_str,
185 (void *) (shdr_start + shdr.sh_link * 183 shdr_start + shdr.sh_link,
186 sizeof(shdr)),
187 sizeof(shdr))) 184 sizeof(shdr)))
188 goto fail; 185 goto fail;
189 186
@@ -191,15 +188,15 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
191 goto fail;; 188 goto fail;;
192 189
193 for (j = 0; j < shdr.sh_size / sizeof (sym); j++) { 190 for (j = 0; j < shdr.sh_size / sizeof (sym); j++) {
194 if (copy_from_user(&sym, (void *) (spu_elf_start + 191 if (copy_from_user(&sym, spu_elf_start +
195 shdr.sh_offset + j * 192 shdr.sh_offset +
196 sizeof (sym)), 193 j * sizeof (sym),
197 sizeof (sym))) 194 sizeof (sym)))
198 goto fail; 195 goto fail;
199 196
200 if (copy_from_user(name, (void *) 197 if (copy_from_user(name,
201 (spu_elf_start + shdr_str.sh_offset + 198 spu_elf_start + shdr_str.sh_offset +
202 sym.st_name), 199 sym.st_name,
203 20)) 200 20))
204 goto fail; 201 goto fail;
205 202
@@ -245,9 +242,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
245 242
246 /* Traverse overlay table. */ 243 /* Traverse overlay table. */
247 for (i = 0; i < n_ovlys; i++) { 244 for (i = 0; i < n_ovlys; i++) {
248 if (copy_from_user(&ovly, (void *) 245 if (copy_from_user(&ovly, ovly_table + i, sizeof (ovly)))
249 (ovly_table + i * sizeof (ovly)),
250 sizeof (ovly)))
251 goto fail; 246 goto fail;
252 247
253 /* The ovly.vma/size/offset arguments are analogous to the same 248 /* The ovly.vma/size/offset arguments are analogous to the same
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index ca52b587166..a977f200db8 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -763,7 +763,7 @@ void xics_request_IPIs(void)
763} 763}
764#endif /* CONFIG_SMP */ 764#endif /* CONFIG_SMP */
765 765
766void xics_teardown_cpu() 766void xics_teardown_cpu(void)
767{ 767{
768 int cpu = smp_processor_id(); 768 int cpu = smp_processor_id();
769 769
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 7be71123212..dd066bb1d56 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -240,6 +240,7 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
240 case CPM_CLK_SCC1: 240 case CPM_CLK_SCC1:
241 reg = &im_cpmux->cmx_scr; 241 reg = &im_cpmux->cmx_scr;
242 shift = 24; 242 shift = 24;
243 break;
243 case CPM_CLK_SCC2: 244 case CPM_CLK_SCC2:
244 reg = &im_cpmux->cmx_scr; 245 reg = &im_cpmux->cmx_scr;
245 shift = 16; 246 shift = 16;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 12720489e45..8d2cd1de572 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -72,9 +72,6 @@ config SYS_SUPPORTS_NUMA
72config SYS_SUPPORTS_PCI 72config SYS_SUPPORTS_PCI
73 bool 73 bool
74 74
75config ARCH_MAY_HAVE_PC_FDC
76 bool
77
78config STACKTRACE_SUPPORT 75config STACKTRACE_SUPPORT
79 def_bool y 76 def_bool y
80 77
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 3dda24daa0a..89b408620dc 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -44,7 +44,7 @@ KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \
44 44
45quiet_cmd_uimage = UIMAGE $@ 45quiet_cmd_uimage = UIMAGE $@
46 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \ 46 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
47 -C none -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \ 47 -C gzip -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
48 -n 'Linux-$(KERNELRELEASE)' -d $< $@ 48 -n 'Linux-$(KERNELRELEASE)' -d $< $@
49 49
50$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE 50$(obj)/uImage: $(obj)/vmlinux.bin.gz FORCE
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index ff99562456f..5627c0b3ffa 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -13,6 +13,7 @@
13#include <linux/signal.h> 13#include <linux/signal.h>
14#include <asm/processor.h> 14#include <asm/processor.h>
15#include <asm/io.h> 15#include <asm/io.h>
16#include <asm/fpu.h>
16 17
17/* The PR (precision) bit in the FP Status Register must be clear when 18/* The PR (precision) bit in the FP Status Register must be clear when
18 * an frchg instruction is executed, otherwise the instruction is undefined. 19 * an frchg instruction is executed, otherwise the instruction is undefined.
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 817f9939cda..8020796139f 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -16,6 +16,7 @@
16#include <asm/cpu/fpu.h> 16#include <asm/cpu/fpu.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/system.h> 18#include <asm/system.h>
19#include <asm/fpu.h>
19 20
20/* The PR (precision) bit in the FP Status Register must be clear when 21/* The PR (precision) bit in the FP Status Register must be clear when
21 * an frchg instruction is executed, otherwise the instruction is undefined. 22 * an frchg instruction is executed, otherwise the instruction is undefined.
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index 30b76a94abf..dd4f51ffb50 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -17,6 +17,7 @@
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/user.h> 18#include <asm/user.h>
19#include <asm/io.h> 19#include <asm/io.h>
20#include <asm/fpu.h>
20 21
21/* 22/*
22 * Initially load the FPU with signalling NANS. This bit pattern 23 * Initially load the FPU with signalling NANS. This bit pattern
diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c
index 4a8a4083ff0..1db7ce0f25d 100644
--- a/arch/sh/kernel/dump_task.c
+++ b/arch/sh/kernel/dump_task.c
@@ -1,5 +1,6 @@
1#include <linux/elfcore.h> 1#include <linux/elfcore.h>
2#include <linux/sched.h> 2#include <linux/sched.h>
3#include <asm/fpu.h>
3 4
4/* 5/*
5 * Capture the user space registers if the task is not running (in user space) 6 * Capture the user space registers if the task is not running (in user space)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 9ab1926b9d1..b98e37a1f54 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -25,6 +25,7 @@
25#include <asm/pgalloc.h> 25#include <asm/pgalloc.h>
26#include <asm/system.h> 26#include <asm/system.h>
27#include <asm/ubc.h> 27#include <asm/ubc.h>
28#include <asm/fpu.h>
28 29
29static int hlt_counter; 30static int hlt_counter;
30int ubc_usercnt = 0; 31int ubc_usercnt = 0;
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index f6b5fbfe75c..f311551d9a0 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -29,6 +29,7 @@
29#include <asm/uaccess.h> 29#include <asm/uaccess.h>
30#include <asm/pgtable.h> 30#include <asm/pgtable.h>
31#include <asm/cacheflush.h> 31#include <asm/cacheflush.h>
32#include <asm/fpu.h>
32 33
33#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 34#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
34 35
diff --git a/arch/sparc/kernel/ptrace.c b/arch/sparc/kernel/ptrace.c
index 5b54f11f4e5..7f44ae69b29 100644
--- a/arch/sparc/kernel/ptrace.c
+++ b/arch/sparc/kernel/ptrace.c
@@ -325,7 +325,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
325 const struct user_regset_view *view; 325 const struct user_regset_view *view;
326 int ret; 326 int ret;
327 327
328 view = task_user_regset_view(child); 328 view = task_user_regset_view(current);
329 329
330 switch(request) { 330 switch(request) {
331 case PTRACE_GETREGS: { 331 case PTRACE_GETREGS: {
diff --git a/arch/sparc64/defconfig b/arch/sparc64/defconfig
index 250958d1e3c..9d4bd222949 100644
--- a/arch/sparc64/defconfig
+++ b/arch/sparc64/defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25-rc1 3# Linux kernel version: 2.6.25-rc3
4# Sun Feb 17 22:44:12 2008 4# Wed Mar 26 04:33:35 2008
5# 5#
6CONFIG_SPARC=y 6CONFIG_SPARC=y
7CONFIG_SPARC64=y 7CONFIG_SPARC64=y
@@ -55,9 +55,11 @@ CONFIG_POSIX_MQUEUE=y
55# CONFIG_IKCONFIG is not set 55# CONFIG_IKCONFIG is not set
56CONFIG_LOG_BUF_SHIFT=18 56CONFIG_LOG_BUF_SHIFT=18
57# CONFIG_CGROUPS is not set 57# CONFIG_CGROUPS is not set
58CONFIG_GROUP_SCHED=y
58CONFIG_FAIR_GROUP_SCHED=y 59CONFIG_FAIR_GROUP_SCHED=y
59CONFIG_FAIR_USER_SCHED=y 60CONFIG_RT_GROUP_SCHED=y
60# CONFIG_FAIR_CGROUP_SCHED is not set 61CONFIG_USER_SCHED=y
62# CONFIG_CGROUP_SCHED is not set
61CONFIG_SYSFS_DEPRECATED=y 63CONFIG_SYSFS_DEPRECATED=y
62CONFIG_RELAY=y 64CONFIG_RELAY=y
63CONFIG_NAMESPACES=y 65CONFIG_NAMESPACES=y
@@ -482,6 +484,7 @@ CONFIG_SCSI_LOWLEVEL=y
482# CONFIG_SCSI_IPS is not set 484# CONFIG_SCSI_IPS is not set
483# CONFIG_SCSI_INITIO is not set 485# CONFIG_SCSI_INITIO is not set
484# CONFIG_SCSI_INIA100 is not set 486# CONFIG_SCSI_INIA100 is not set
487# CONFIG_SCSI_MVSAS is not set
485# CONFIG_SCSI_STEX is not set 488# CONFIG_SCSI_STEX is not set
486# CONFIG_SCSI_SYM53C8XX_2 is not set 489# CONFIG_SCSI_SYM53C8XX_2 is not set
487# CONFIG_SCSI_QLOGIC_1280 is not set 490# CONFIG_SCSI_QLOGIC_1280 is not set
@@ -810,6 +813,7 @@ CONFIG_HWMON=y
810# CONFIG_SENSORS_ADM1031 is not set 813# CONFIG_SENSORS_ADM1031 is not set
811# CONFIG_SENSORS_ADM9240 is not set 814# CONFIG_SENSORS_ADM9240 is not set
812# CONFIG_SENSORS_ADT7470 is not set 815# CONFIG_SENSORS_ADT7470 is not set
816# CONFIG_SENSORS_ADT7473 is not set
813# CONFIG_SENSORS_ATXP1 is not set 817# CONFIG_SENSORS_ATXP1 is not set
814# CONFIG_SENSORS_DS1621 is not set 818# CONFIG_SENSORS_DS1621 is not set
815# CONFIG_SENSORS_I5K_AMB is not set 819# CONFIG_SENSORS_I5K_AMB is not set
diff --git a/arch/sparc64/kernel/cpu.c b/arch/sparc64/kernel/cpu.c
index dd5d28e3d79..0097c08dc60 100644
--- a/arch/sparc64/kernel/cpu.c
+++ b/arch/sparc64/kernel/cpu.c
@@ -15,6 +15,8 @@
15#include <asm/spitfire.h> 15#include <asm/spitfire.h>
16#include <asm/oplib.h> 16#include <asm/oplib.h>
17 17
18#include "entry.h"
19
18DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; 20DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
19 21
20struct cpu_iu_info { 22struct cpu_iu_info {
@@ -65,8 +67,6 @@ static struct cpu_iu_info linux_sparc_chips[] = {
65char *sparc_cpu_type; 67char *sparc_cpu_type;
66char *sparc_fpu_type; 68char *sparc_fpu_type;
67 69
68unsigned int fsr_storage;
69
70static void __init sun4v_cpu_probe(void) 70static void __init sun4v_cpu_probe(void)
71{ 71{
72 switch (sun4v_chip_type) { 72 switch (sun4v_chip_type) {
@@ -94,8 +94,10 @@ void __init cpu_probe(void)
94 unsigned long ver, fpu_vers, manuf, impl, fprs; 94 unsigned long ver, fpu_vers, manuf, impl, fprs;
95 int i; 95 int i;
96 96
97 if (tlb_type == hypervisor) 97 if (tlb_type == hypervisor) {
98 return sun4v_cpu_probe(); 98 sun4v_cpu_probe();
99 return;
100 }
99 101
100 fprs = fprs_read(); 102 fprs = fprs_read();
101 fprs_write(FPRS_FEF); 103 fprs_write(FPRS_FEF);
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index 6be4d2d2904..49eca4b1cf2 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -1705,6 +1705,36 @@ __flushw_user:
17052: retl 17052: retl
1706 nop 1706 nop
1707 1707
1708 /* Flush %fp and %i7 to the stack for all register
1709 * windows active inside of the cpu. This allows
1710 * show_stack_trace() to avoid using an expensive
1711 * 'flushw'.
1712 */
1713 .globl stack_trace_flush
1714 .type stack_trace_flush,#function
1715stack_trace_flush:
1716 rdpr %pstate, %o0
1717 wrpr %o0, PSTATE_IE, %pstate
1718
1719 rdpr %cwp, %g1
1720 rdpr %canrestore, %g2
1721 sub %g1, 1, %g3
1722
17231: brz,pn %g2, 2f
1724 sub %g2, 1, %g2
1725 wrpr %g3, %cwp
1726 stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
1727 stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
1728 ba,pt %xcc, 1b
1729 sub %g3, 1, %g3
1730
17312: wrpr %g1, %cwp
1732 wrpr %o0, %pstate
1733
1734 retl
1735 nop
1736 .size stack_trace_flush,.-stack_trace_flush
1737
1708#ifdef CONFIG_SMP 1738#ifdef CONFIG_SMP
1709 .globl hard_smp_processor_id 1739 .globl hard_smp_processor_id
1710hard_smp_processor_id: 1740hard_smp_processor_id:
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h
new file mode 100644
index 00000000000..4a91e9c6d31
--- /dev/null
+++ b/arch/sparc64/kernel/entry.h
@@ -0,0 +1,196 @@
1#ifndef _ENTRY_H
2#define _ENTRY_H
3
4#include <linux/kernel.h>
5#include <linux/types.h>
6#include <linux/init.h>
7
8extern char *sparc_cpu_type;
9extern char *sparc_fpu_type;
10
11extern void __init per_cpu_patch(void);
12extern void __init sun4v_patch(void);
13extern void __init boot_cpu_id_too_large(int cpu);
14extern unsigned int dcache_parity_tl1_occurred;
15extern unsigned int icache_parity_tl1_occurred;
16
17extern asmlinkage void update_perfctrs(void);
18extern asmlinkage void sparc_breakpoint(struct pt_regs *regs);
19extern void timer_interrupt(int irq, struct pt_regs *regs);
20
21extern void do_notify_resume(struct pt_regs *regs,
22 unsigned long orig_i0,
23 int restart_syscall,
24 unsigned long thread_info_flags);
25
26extern asmlinkage void syscall_trace(struct pt_regs *regs,
27 int syscall_exit_p);
28
29extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
30
31extern void do_fpe_common(struct pt_regs *regs);
32extern void do_fpieee(struct pt_regs *regs);
33extern void do_fpother(struct pt_regs *regs);
34extern void do_tof(struct pt_regs *regs);
35extern void do_div0(struct pt_regs *regs);
36extern void do_illegal_instruction(struct pt_regs *regs);
37extern void mem_address_unaligned(struct pt_regs *regs,
38 unsigned long sfar,
39 unsigned long sfsr);
40extern void sun4v_do_mna(struct pt_regs *regs,
41 unsigned long addr,
42 unsigned long type_ctx);
43extern void do_privop(struct pt_regs *regs);
44extern void do_privact(struct pt_regs *regs);
45extern void do_cee(struct pt_regs *regs);
46extern void do_cee_tl1(struct pt_regs *regs);
47extern void do_dae_tl1(struct pt_regs *regs);
48extern void do_iae_tl1(struct pt_regs *regs);
49extern void do_div0_tl1(struct pt_regs *regs);
50extern void do_fpdis_tl1(struct pt_regs *regs);
51extern void do_fpieee_tl1(struct pt_regs *regs);
52extern void do_fpother_tl1(struct pt_regs *regs);
53extern void do_ill_tl1(struct pt_regs *regs);
54extern void do_irq_tl1(struct pt_regs *regs);
55extern void do_lddfmna_tl1(struct pt_regs *regs);
56extern void do_stdfmna_tl1(struct pt_regs *regs);
57extern void do_paw(struct pt_regs *regs);
58extern void do_paw_tl1(struct pt_regs *regs);
59extern void do_vaw(struct pt_regs *regs);
60extern void do_vaw_tl1(struct pt_regs *regs);
61extern void do_tof_tl1(struct pt_regs *regs);
62extern void do_getpsr(struct pt_regs *regs);
63
64extern void spitfire_insn_access_exception(struct pt_regs *regs,
65 unsigned long sfsr,
66 unsigned long sfar);
67extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
68 unsigned long sfsr,
69 unsigned long sfar);
70extern void spitfire_data_access_exception(struct pt_regs *regs,
71 unsigned long sfsr,
72 unsigned long sfar);
73extern void spitfire_data_access_exception_tl1(struct pt_regs *regs,
74 unsigned long sfsr,
75 unsigned long sfar);
76extern void spitfire_access_error(struct pt_regs *regs,
77 unsigned long status_encoded,
78 unsigned long afar);
79
80extern void cheetah_fecc_handler(struct pt_regs *regs,
81 unsigned long afsr,
82 unsigned long afar);
83extern void cheetah_cee_handler(struct pt_regs *regs,
84 unsigned long afsr,
85 unsigned long afar);
86extern void cheetah_deferred_handler(struct pt_regs *regs,
87 unsigned long afsr,
88 unsigned long afar);
89extern void cheetah_plus_parity_error(int type, struct pt_regs *regs);
90
91extern void sun4v_insn_access_exception(struct pt_regs *regs,
92 unsigned long addr,
93 unsigned long type_ctx);
94extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
95 unsigned long addr,
96 unsigned long type_ctx);
97extern void sun4v_data_access_exception(struct pt_regs *regs,
98 unsigned long addr,
99 unsigned long type_ctx);
100extern void sun4v_data_access_exception_tl1(struct pt_regs *regs,
101 unsigned long addr,
102 unsigned long type_ctx);
103extern void sun4v_resum_error(struct pt_regs *regs,
104 unsigned long offset);
105extern void sun4v_resum_overflow(struct pt_regs *regs);
106extern void sun4v_nonresum_error(struct pt_regs *regs,
107 unsigned long offset);
108extern void sun4v_nonresum_overflow(struct pt_regs *regs);
109
110extern unsigned long sun4v_err_itlb_vaddr;
111extern unsigned long sun4v_err_itlb_ctx;
112extern unsigned long sun4v_err_itlb_pte;
113extern unsigned long sun4v_err_itlb_error;
114
115extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
116
117extern unsigned long sun4v_err_dtlb_vaddr;
118extern unsigned long sun4v_err_dtlb_ctx;
119extern unsigned long sun4v_err_dtlb_pte;
120extern unsigned long sun4v_err_dtlb_error;
121
122extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
123extern void hypervisor_tlbop_error(unsigned long err,
124 unsigned long op);
125extern void hypervisor_tlbop_error_xcall(unsigned long err,
126 unsigned long op);
127
128/* WARNING: The error trap handlers in assembly know the precise
129 * layout of the following structure.
130 *
131 * C-level handlers in traps.c use this information to log the
132 * error and then determine how to recover (if possible).
133 */
134struct cheetah_err_info {
135/*0x00*/u64 afsr;
136/*0x08*/u64 afar;
137
138 /* D-cache state */
139/*0x10*/u64 dcache_data[4]; /* The actual data */
140/*0x30*/u64 dcache_index; /* D-cache index */
141/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
142/*0x40*/u64 dcache_utag; /* D-cache microtag */
143/*0x48*/u64 dcache_stag; /* D-cache snooptag */
144
145 /* I-cache state */
146/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
147/*0x90*/u64 icache_index; /* I-cache index */
148/*0x98*/u64 icache_tag; /* I-cache phys tag */
149/*0xa0*/u64 icache_utag; /* I-cache microtag */
150/*0xa8*/u64 icache_stag; /* I-cache snooptag */
151/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
152/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
153
154 /* E-cache state */
155/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
156/*0xe0*/u64 ecache_index; /* E-cache index */
157/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
158
159/*0xf0*/u64 __pad[32 - 30];
160};
161#define CHAFSR_INVALID ((u64)-1L)
162
163/* This is allocated at boot time based upon the largest hardware
164 * cpu ID in the system. We allocate two entries per cpu, one for
165 * TL==0 logging and one for TL >= 1 logging.
166 */
167extern struct cheetah_err_info *cheetah_error_log;
168
169/* UPA nodes send interrupt packet to UltraSparc with first data reg
170 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
171 * delivered. We must translate this into a non-vector IRQ so we can
172 * set the softint on this cpu.
173 *
174 * To make processing these packets efficient and race free we use
175 * an array of irq buckets below. The interrupt vector handler in
176 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
177 *
178 * If you make changes to ino_bucket, please update hand coded assembler
179 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
180 */
181struct ino_bucket {
182/*0x00*/unsigned long __irq_chain_pa;
183
184 /* Virtual interrupt number assigned to this INO. */
185/*0x08*/unsigned int __virt_irq;
186/*0x0c*/unsigned int __pad;
187};
188
189extern struct ino_bucket *ivector_table;
190extern unsigned long ivector_table_pa;
191
192extern void handler_irq(int irq, struct pt_regs *regs);
193extern void init_irqwork_curcpu(void);
194extern void __cpuinit sun4v_register_mondo_queues(int this_cpu);
195
196#endif /* _ENTRY_H */
diff --git a/arch/sparc64/kernel/iommu.c b/arch/sparc64/kernel/iommu.c
index fbaab3497bf..756fa24eeef 100644
--- a/arch/sparc64/kernel/iommu.c
+++ b/arch/sparc64/kernel/iommu.c
@@ -516,9 +516,11 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
516 unsigned long flags, handle, prot, ctx; 516 unsigned long flags, handle, prot, ctx;
517 dma_addr_t dma_next = 0, dma_addr; 517 dma_addr_t dma_next = 0, dma_addr;
518 unsigned int max_seg_size; 518 unsigned int max_seg_size;
519 unsigned long seg_boundary_size;
519 int outcount, incount, i; 520 int outcount, incount, i;
520 struct strbuf *strbuf; 521 struct strbuf *strbuf;
521 struct iommu *iommu; 522 struct iommu *iommu;
523 unsigned long base_shift;
522 524
523 BUG_ON(direction == DMA_NONE); 525 BUG_ON(direction == DMA_NONE);
524 526
@@ -549,8 +551,11 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
549 outs->dma_length = 0; 551 outs->dma_length = 0;
550 552
551 max_seg_size = dma_get_max_seg_size(dev); 553 max_seg_size = dma_get_max_seg_size(dev);
554 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
555 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
556 base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
552 for_each_sg(sglist, s, nelems, i) { 557 for_each_sg(sglist, s, nelems, i) {
553 unsigned long paddr, npages, entry, slen; 558 unsigned long paddr, npages, entry, out_entry = 0, slen;
554 iopte_t *base; 559 iopte_t *base;
555 560
556 slen = s->length; 561 slen = s->length;
@@ -593,7 +598,9 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
593 * - allocated dma_addr isn't contiguous to previous allocation 598 * - allocated dma_addr isn't contiguous to previous allocation
594 */ 599 */
595 if ((dma_addr != dma_next) || 600 if ((dma_addr != dma_next) ||
596 (outs->dma_length + s->length > max_seg_size)) { 601 (outs->dma_length + s->length > max_seg_size) ||
602 (is_span_boundary(out_entry, base_shift,
603 seg_boundary_size, outs, s))) {
597 /* Can't merge: create a new segment */ 604 /* Can't merge: create a new segment */
598 segstart = s; 605 segstart = s;
599 outcount++; 606 outcount++;
@@ -607,6 +614,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
607 /* This is a new segment, fill entries */ 614 /* This is a new segment, fill entries */
608 outs->dma_address = dma_addr; 615 outs->dma_address = dma_addr;
609 outs->dma_length = slen; 616 outs->dma_length = slen;
617 out_entry = entry;
610 } 618 }
611 619
612 /* Calculate next page pointer for contiguous check */ 620 /* Calculate next page pointer for contiguous check */
@@ -626,7 +634,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
626iommu_map_failed: 634iommu_map_failed:
627 for_each_sg(sglist, s, nelems, i) { 635 for_each_sg(sglist, s, nelems, i) {
628 if (s->dma_length != 0) { 636 if (s->dma_length != 0) {
629 unsigned long vaddr, npages, entry, i; 637 unsigned long vaddr, npages, entry, j;
630 iopte_t *base; 638 iopte_t *base;
631 639
632 vaddr = s->dma_address & IO_PAGE_MASK; 640 vaddr = s->dma_address & IO_PAGE_MASK;
@@ -637,8 +645,8 @@ iommu_map_failed:
637 >> IO_PAGE_SHIFT; 645 >> IO_PAGE_SHIFT;
638 base = iommu->page_table + entry; 646 base = iommu->page_table + entry;
639 647
640 for (i = 0; i < npages; i++) 648 for (j = 0; j < npages; j++)
641 iopte_make_dummy(iommu, base + i); 649 iopte_make_dummy(iommu, base + j);
642 650
643 s->dma_address = DMA_ERROR_CODE; 651 s->dma_address = DMA_ERROR_CODE;
644 s->dma_length = 0; 652 s->dma_length = 0;
@@ -803,7 +811,7 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
803 spin_unlock_irqrestore(&iommu->lock, flags); 811 spin_unlock_irqrestore(&iommu->lock, flags);
804} 812}
805 813
806const struct dma_ops sun4u_dma_ops = { 814static const struct dma_ops sun4u_dma_ops = {
807 .alloc_coherent = dma_4u_alloc_coherent, 815 .alloc_coherent = dma_4u_alloc_coherent,
808 .free_coherent = dma_4u_free_coherent, 816 .free_coherent = dma_4u_free_coherent,
809 .map_single = dma_4u_map_single, 817 .map_single = dma_4u_map_single,
diff --git a/arch/sparc64/kernel/iommu_common.h b/arch/sparc64/kernel/iommu_common.h
index 0713bd58499..f3575a614fa 100644
--- a/arch/sparc64/kernel/iommu_common.h
+++ b/arch/sparc64/kernel/iommu_common.h
@@ -12,6 +12,7 @@
12#include <linux/mm.h> 12#include <linux/mm.h>
13#include <linux/scatterlist.h> 13#include <linux/scatterlist.h>
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/iommu-helper.h>
15 16
16#include <asm/iommu.h> 17#include <asm/iommu.h>
17#include <asm/scatterlist.h> 18#include <asm/scatterlist.h>
@@ -45,17 +46,16 @@ static inline unsigned long iommu_num_pages(unsigned long vaddr,
45 return npages; 46 return npages;
46} 47}
47 48
48static inline unsigned long calc_npages(struct scatterlist *sglist, int nelems) 49static inline int is_span_boundary(unsigned long entry,
50 unsigned long shift,
51 unsigned long boundary_size,
52 struct scatterlist *outs,
53 struct scatterlist *sg)
49{ 54{
50 unsigned long i, npages = 0; 55 unsigned long paddr = SG_ENT_PHYS_ADDRESS(outs);
51 struct scatterlist *sg; 56 int nr = iommu_num_pages(paddr, outs->dma_length + sg->length);
52 57
53 for_each_sg(sglist, sg, nelems, i) { 58 return iommu_is_span_boundary(entry, nr, shift, boundary_size);
54 unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg);
55 npages += iommu_num_pages(paddr, sg->length);
56 }
57
58 return npages;
59} 59}
60 60
61extern unsigned long iommu_range_alloc(struct device *dev, 61extern unsigned long iommu_range_alloc(struct device *dev,
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 5ec06c8c7fe..eb88bd6e674 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -44,27 +44,10 @@
44#include <asm/hypervisor.h> 44#include <asm/hypervisor.h>
45#include <asm/cacheflush.h> 45#include <asm/cacheflush.h>
46 46
47/* UPA nodes send interrupt packet to UltraSparc with first data reg 47#include "entry.h"
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
51 *
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 *
56 * If you make changes to ino_bucket, please update hand coded assembler
57 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
58 */
59struct ino_bucket {
60/*0x00*/unsigned long __irq_chain_pa;
61
62 /* Virtual interrupt number assigned to this INO. */
63/*0x08*/unsigned int __virt_irq;
64/*0x0c*/unsigned int __pad;
65};
66 48
67#define NUM_IVECS (IMAP_INR + 1) 49#define NUM_IVECS (IMAP_INR + 1)
50
68struct ino_bucket *ivector_table; 51struct ino_bucket *ivector_table;
69unsigned long ivector_table_pa; 52unsigned long ivector_table_pa;
70 53
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ddca6c6c0b4..01839706bd5 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -335,8 +335,10 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
335 unsigned long flags, handle, prot; 335 unsigned long flags, handle, prot;
336 dma_addr_t dma_next = 0, dma_addr; 336 dma_addr_t dma_next = 0, dma_addr;
337 unsigned int max_seg_size; 337 unsigned int max_seg_size;
338 unsigned long seg_boundary_size;
338 int outcount, incount, i; 339 int outcount, incount, i;
339 struct iommu *iommu; 340 struct iommu *iommu;
341 unsigned long base_shift;
340 long err; 342 long err;
341 343
342 BUG_ON(direction == DMA_NONE); 344 BUG_ON(direction == DMA_NONE);
@@ -362,8 +364,11 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
362 iommu_batch_start(dev, prot, ~0UL); 364 iommu_batch_start(dev, prot, ~0UL);
363 365
364 max_seg_size = dma_get_max_seg_size(dev); 366 max_seg_size = dma_get_max_seg_size(dev);
367 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
368 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
369 base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
365 for_each_sg(sglist, s, nelems, i) { 370 for_each_sg(sglist, s, nelems, i) {
366 unsigned long paddr, npages, entry, slen; 371 unsigned long paddr, npages, entry, out_entry = 0, slen;
367 372
368 slen = s->length; 373 slen = s->length;
369 /* Sanity check */ 374 /* Sanity check */
@@ -406,7 +411,9 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
406 * - allocated dma_addr isn't contiguous to previous allocation 411 * - allocated dma_addr isn't contiguous to previous allocation
407 */ 412 */
408 if ((dma_addr != dma_next) || 413 if ((dma_addr != dma_next) ||
409 (outs->dma_length + s->length > max_seg_size)) { 414 (outs->dma_length + s->length > max_seg_size) ||
415 (is_span_boundary(out_entry, base_shift,
416 seg_boundary_size, outs, s))) {
410 /* Can't merge: create a new segment */ 417 /* Can't merge: create a new segment */
411 segstart = s; 418 segstart = s;
412 outcount++; 419 outcount++;
@@ -420,6 +427,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
420 /* This is a new segment, fill entries */ 427 /* This is a new segment, fill entries */
421 outs->dma_address = dma_addr; 428 outs->dma_address = dma_addr;
422 outs->dma_length = slen; 429 outs->dma_length = slen;
430 out_entry = entry;
423 } 431 }
424 432
425 /* Calculate next page pointer for contiguous check */ 433 /* Calculate next page pointer for contiguous check */
diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
index 9a1ba1fe859..e9fc0aa2da3 100644
--- a/arch/sparc64/kernel/ptrace.c
+++ b/arch/sparc64/kernel/ptrace.c
@@ -35,6 +35,9 @@
35#include <asm/spitfire.h> 35#include <asm/spitfire.h>
36#include <asm/page.h> 36#include <asm/page.h>
37#include <asm/cpudata.h> 37#include <asm/cpudata.h>
38#include <asm/cacheflush.h>
39
40#include "entry.h"
38 41
39/* #define ALLOW_INIT_TRACING */ 42/* #define ALLOW_INIT_TRACING */
40 43
@@ -67,6 +70,8 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
67 if (tlb_type == hypervisor) 70 if (tlb_type == hypervisor)
68 return; 71 return;
69 72
73 preempt_disable();
74
70#ifdef DCACHE_ALIASING_POSSIBLE 75#ifdef DCACHE_ALIASING_POSSIBLE
71 /* If bit 13 of the kernel address we used to access the 76 /* If bit 13 of the kernel address we used to access the
72 * user page is the same as the virtual address that page 77 * user page is the same as the virtual address that page
@@ -105,6 +110,87 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
105 for (; start < end; start += icache_line_size) 110 for (; start < end; start += icache_line_size)
106 flushi(start); 111 flushi(start);
107 } 112 }
113
114 preempt_enable();
115}
116
117static int get_from_target(struct task_struct *target, unsigned long uaddr,
118 void *kbuf, int len)
119{
120 if (target == current) {
121 if (copy_from_user(kbuf, (void __user *) uaddr, len))
122 return -EFAULT;
123 } else {
124 int len2 = access_process_vm(target, uaddr, kbuf, len, 0);
125 if (len2 != len)
126 return -EFAULT;
127 }
128 return 0;
129}
130
131static int set_to_target(struct task_struct *target, unsigned long uaddr,
132 void *kbuf, int len)
133{
134 if (target == current) {
135 if (copy_to_user((void __user *) uaddr, kbuf, len))
136 return -EFAULT;
137 } else {
138 int len2 = access_process_vm(target, uaddr, kbuf, len, 1);
139 if (len2 != len)
140 return -EFAULT;
141 }
142 return 0;
143}
144
145static int regwindow64_get(struct task_struct *target,
146 const struct pt_regs *regs,
147 struct reg_window *wbuf)
148{
149 unsigned long rw_addr = regs->u_regs[UREG_I6];
150
151 if (test_tsk_thread_flag(current, TIF_32BIT)) {
152 struct reg_window32 win32;
153 int i;
154
155 if (get_from_target(target, rw_addr, &win32, sizeof(win32)))
156 return -EFAULT;
157 for (i = 0; i < 8; i++)
158 wbuf->locals[i] = win32.locals[i];
159 for (i = 0; i < 8; i++)
160 wbuf->ins[i] = win32.ins[i];
161 } else {
162 rw_addr += STACK_BIAS;
163 if (get_from_target(target, rw_addr, wbuf, sizeof(*wbuf)))
164 return -EFAULT;
165 }
166
167 return 0;
168}
169
170static int regwindow64_set(struct task_struct *target,
171 const struct pt_regs *regs,
172 struct reg_window *wbuf)
173{
174 unsigned long rw_addr = regs->u_regs[UREG_I6];
175
176 if (test_tsk_thread_flag(current, TIF_32BIT)) {
177 struct reg_window32 win32;
178 int i;
179
180 for (i = 0; i < 8; i++)
181 win32.locals[i] = wbuf->locals[i];
182 for (i = 0; i < 8; i++)
183 win32.ins[i] = wbuf->ins[i];
184
185 if (set_to_target(target, rw_addr, &win32, sizeof(win32)))
186 return -EFAULT;
187 } else {
188 rw_addr += STACK_BIAS;
189 if (set_to_target(target, rw_addr, wbuf, sizeof(*wbuf)))
190 return -EFAULT;
191 }
192
193 return 0;
108} 194}
109 195
110enum sparc_regset { 196enum sparc_regset {
@@ -126,16 +212,13 @@ static int genregs64_get(struct task_struct *target,
126 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 212 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
127 regs->u_regs, 213 regs->u_regs,
128 0, 16 * sizeof(u64)); 214 0, 16 * sizeof(u64));
129 if (!ret) { 215 if (!ret && count && pos < (32 * sizeof(u64))) {
130 unsigned long __user *reg_window = (unsigned long __user *) 216 struct reg_window window;
131 (regs->u_regs[UREG_I6] + STACK_BIAS);
132 unsigned long window[16];
133 217
134 if (copy_from_user(window, reg_window, sizeof(window))) 218 if (regwindow64_get(target, regs, &window))
135 return -EFAULT; 219 return -EFAULT;
136
137 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 220 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
138 window, 221 &window,
139 16 * sizeof(u64), 222 16 * sizeof(u64),
140 32 * sizeof(u64)); 223 32 * sizeof(u64));
141 } 224 }
@@ -157,10 +240,11 @@ static int genregs64_get(struct task_struct *target,
157 36 * sizeof(u64)); 240 36 * sizeof(u64));
158 } 241 }
159 242
160 if (!ret) 243 if (!ret) {
161 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, 244 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
162 36 * sizeof(u64), -1); 245 36 * sizeof(u64), -1);
163 246
247 }
164 return ret; 248 return ret;
165} 249}
166 250
@@ -178,20 +262,19 @@ static int genregs64_set(struct task_struct *target,
178 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 262 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
179 regs->u_regs, 263 regs->u_regs,
180 0, 16 * sizeof(u64)); 264 0, 16 * sizeof(u64));
181 if (!ret && count > 0) { 265 if (!ret && count && pos < (32 * sizeof(u64))) {
182 unsigned long __user *reg_window = (unsigned long __user *) 266 struct reg_window window;
183 (regs->u_regs[UREG_I6] + STACK_BIAS);
184 unsigned long window[16];
185 267
186 if (copy_from_user(window, reg_window, sizeof(window))) 268 if (regwindow64_get(target, regs, &window))
187 return -EFAULT; 269 return -EFAULT;
188 270
189 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 271 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
190 window, 272 &window,
191 16 * sizeof(u64), 273 16 * sizeof(u64),
192 32 * sizeof(u64)); 274 32 * sizeof(u64));
275
193 if (!ret && 276 if (!ret &&
194 copy_to_user(reg_window, window, sizeof(window))) 277 regwindow64_set(target, regs, &window))
195 return -EFAULT; 278 return -EFAULT;
196 } 279 }
197 280
@@ -382,6 +465,7 @@ static const struct user_regset_view user_sparc64_view = {
382 .regsets = sparc64_regsets, .n = ARRAY_SIZE(sparc64_regsets) 465 .regsets = sparc64_regsets, .n = ARRAY_SIZE(sparc64_regsets)
383}; 466};
384 467
468#ifdef CONFIG_COMPAT
385static int genregs32_get(struct task_struct *target, 469static int genregs32_get(struct task_struct *target,
386 const struct user_regset *regset, 470 const struct user_regset *regset,
387 unsigned int pos, unsigned int count, 471 unsigned int pos, unsigned int count,
@@ -404,9 +488,22 @@ static int genregs32_get(struct task_struct *target,
404 *k++ = regs->u_regs[pos++]; 488 *k++ = regs->u_regs[pos++];
405 489
406 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6]; 490 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
407 for (; count > 0 && pos < 32; count--) { 491 if (target == current) {
408 if (get_user(*k++, &reg_window[pos++])) 492 for (; count > 0 && pos < 32; count--) {
409 return -EFAULT; 493 if (get_user(*k++, &reg_window[pos++]))
494 return -EFAULT;
495 }
496 } else {
497 for (; count > 0 && pos < 32; count--) {
498 if (access_process_vm(target,
499 (unsigned long)
500 &reg_window[pos],
501 k, sizeof(*k), 0)
502 != sizeof(*k))
503 return -EFAULT;
504 k++;
505 pos++;
506 }
410 } 507 }
411 } else { 508 } else {
412 for (; count > 0 && pos < 16; count--) { 509 for (; count > 0 && pos < 16; count--) {
@@ -415,10 +512,28 @@ static int genregs32_get(struct task_struct *target,
415 } 512 }
416 513
417 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6]; 514 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
418 for (; count > 0 && pos < 32; count--) { 515 if (target == current) {
419 if (get_user(reg, &reg_window[pos++]) || 516 for (; count > 0 && pos < 32; count--) {
420 put_user(reg, u++)) 517 if (get_user(reg, &reg_window[pos++]) ||
421 return -EFAULT; 518 put_user(reg, u++))
519 return -EFAULT;
520 }
521 } else {
522 for (; count > 0 && pos < 32; count--) {
523 if (access_process_vm(target,
524 (unsigned long)
525 &reg_window[pos],
526 &reg, sizeof(reg), 0)
527 != sizeof(reg))
528 return -EFAULT;
529 if (access_process_vm(target,
530 (unsigned long) u,
531 &reg, sizeof(reg), 1)
532 != sizeof(reg))
533 return -EFAULT;
534 pos++;
535 u++;
536 }
422 } 537 }
423 } 538 }
424 while (count > 0) { 539 while (count > 0) {
@@ -480,9 +595,23 @@ static int genregs32_set(struct task_struct *target,
480 regs->u_regs[pos++] = *k++; 595 regs->u_regs[pos++] = *k++;
481 596
482 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6]; 597 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
483 for (; count > 0 && pos < 32; count--) { 598 if (target == current) {
484 if (put_user(*k++, &reg_window[pos++])) 599 for (; count > 0 && pos < 32; count--) {
485 return -EFAULT; 600 if (put_user(*k++, &reg_window[pos++]))
601 return -EFAULT;
602 }
603 } else {
604 for (; count > 0 && pos < 32; count--) {
605 if (access_process_vm(target,
606 (unsigned long)
607 &reg_window[pos],
608 (void *) k,
609 sizeof(*k), 1)
610 != sizeof(*k))
611 return -EFAULT;
612 k++;
613 pos++;
614 }
486 } 615 }
487 } else { 616 } else {
488 for (; count > 0 && pos < 16; count--) { 617 for (; count > 0 && pos < 16; count--) {
@@ -492,10 +621,29 @@ static int genregs32_set(struct task_struct *target,
492 } 621 }
493 622
494 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6]; 623 reg_window = (compat_ulong_t __user *) regs->u_regs[UREG_I6];
495 for (; count > 0 && pos < 32; count--) { 624 if (target == current) {
496 if (get_user(reg, u++) || 625 for (; count > 0 && pos < 32; count--) {
497 put_user(reg, &reg_window[pos++])) 626 if (get_user(reg, u++) ||
498 return -EFAULT; 627 put_user(reg, &reg_window[pos++]))
628 return -EFAULT;
629 }
630 } else {
631 for (; count > 0 && pos < 32; count--) {
632 if (access_process_vm(target,
633 (unsigned long)
634 u,
635 &reg, sizeof(reg), 0)
636 != sizeof(reg))
637 return -EFAULT;
638 if (access_process_vm(target,
639 (unsigned long)
640 &reg_window[pos],
641 &reg, sizeof(reg), 1)
642 != sizeof(reg))
643 return -EFAULT;
644 pos++;
645 u++;
646 }
499 } 647 }
500 } 648 }
501 while (count > 0) { 649 while (count > 0) {
@@ -676,14 +824,18 @@ static const struct user_regset_view user_sparc32_view = {
676 .name = "sparc", .e_machine = EM_SPARC, 824 .name = "sparc", .e_machine = EM_SPARC,
677 .regsets = sparc32_regsets, .n = ARRAY_SIZE(sparc32_regsets) 825 .regsets = sparc32_regsets, .n = ARRAY_SIZE(sparc32_regsets)
678}; 826};
827#endif /* CONFIG_COMPAT */
679 828
680const struct user_regset_view *task_user_regset_view(struct task_struct *task) 829const struct user_regset_view *task_user_regset_view(struct task_struct *task)
681{ 830{
831#ifdef CONFIG_COMPAT
682 if (test_tsk_thread_flag(task, TIF_32BIT)) 832 if (test_tsk_thread_flag(task, TIF_32BIT))
683 return &user_sparc32_view; 833 return &user_sparc32_view;
834#endif
684 return &user_sparc64_view; 835 return &user_sparc64_view;
685} 836}
686 837
838#ifdef CONFIG_COMPAT
687struct compat_fps { 839struct compat_fps {
688 unsigned int regs[32]; 840 unsigned int regs[32];
689 unsigned int fsr; 841 unsigned int fsr;
@@ -699,7 +851,7 @@ struct compat_fps {
699long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 851long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
700 compat_ulong_t caddr, compat_ulong_t cdata) 852 compat_ulong_t caddr, compat_ulong_t cdata)
701{ 853{
702 const struct user_regset_view *view = task_user_regset_view(child); 854 const struct user_regset_view *view = task_user_regset_view(current);
703 compat_ulong_t caddr2 = task_pt_regs(current)->u_regs[UREG_I4]; 855 compat_ulong_t caddr2 = task_pt_regs(current)->u_regs[UREG_I4];
704 struct pt_regs32 __user *pregs; 856 struct pt_regs32 __user *pregs;
705 struct compat_fps __user *fps; 857 struct compat_fps __user *fps;
@@ -798,6 +950,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
798 950
799 return ret; 951 return ret;
800} 952}
953#endif /* CONFIG_COMPAT */
801 954
802struct fps { 955struct fps {
803 unsigned int regs[64]; 956 unsigned int regs[64];
@@ -806,12 +959,15 @@ struct fps {
806 959
807long arch_ptrace(struct task_struct *child, long request, long addr, long data) 960long arch_ptrace(struct task_struct *child, long request, long addr, long data)
808{ 961{
809 const struct user_regset_view *view = task_user_regset_view(child); 962 const struct user_regset_view *view = task_user_regset_view(current);
810 struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
811 unsigned long addr2 = task_pt_regs(current)->u_regs[UREG_I4]; 963 unsigned long addr2 = task_pt_regs(current)->u_regs[UREG_I4];
812 struct fps __user *fps = (struct fps __user *) addr; 964 struct pt_regs __user *pregs;
965 struct fps __user *fps;
813 int ret; 966 int ret;
814 967
968 pregs = (struct pt_regs __user *) (unsigned long) addr;
969 fps = (struct fps __user *) (unsigned long) addr;
970
815 switch (request) { 971 switch (request) {
816 case PTRACE_PEEKUSR: 972 case PTRACE_PEEKUSR:
817 ret = (addr != 0) ? -EIO : 0; 973 ret = (addr != 0) ? -EIO : 0;
diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index d036dbe7286..6acb4c51cfe 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -51,6 +51,8 @@
51#include <net/ipconfig.h> 51#include <net/ipconfig.h>
52#endif 52#endif
53 53
54#include "entry.h"
55
54/* Used to synchronize accesses to NatSemi SUPER I/O chip configure 56/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
55 * operations in asm/ns87303.h 57 * operations in asm/ns87303.h
56 */ 58 */
@@ -335,9 +337,6 @@ void __init setup_arch(char **cmdline_p)
335 337
336/* BUFFER is PAGE_SIZE bytes long. */ 338/* BUFFER is PAGE_SIZE bytes long. */
337 339
338extern char *sparc_cpu_type;
339extern char *sparc_fpu_type;
340
341extern void smp_info(struct seq_file *); 340extern void smp_info(struct seq_file *);
342extern void smp_bogo(struct seq_file *); 341extern void smp_bogo(struct seq_file *);
343extern void mmu_info(struct seq_file *); 342extern void mmu_info(struct seq_file *);
diff --git a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
index fb13775b368..9d51956e8e2 100644
--- a/arch/sparc64/kernel/signal.c
+++ b/arch/sparc64/kernel/signal.c
@@ -32,6 +32,9 @@
32#include <asm/siginfo.h> 32#include <asm/siginfo.h>
33#include <asm/visasm.h> 33#include <asm/visasm.h>
34 34
35#include "entry.h"
36#include "systbls.h"
37
35#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 38#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
36 39
37/* {set, get}context() needed for 64-bit SparcLinux userland. */ 40/* {set, get}context() needed for 64-bit SparcLinux userland. */
@@ -354,7 +357,7 @@ static int invalid_frame_pointer(void __user *fp, int fplen)
354static inline int 357static inline int
355save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu) 358save_fpu_state(struct pt_regs *regs, __siginfo_fpu_t __user *fpu)
356{ 359{
357 unsigned long *fpregs = (unsigned long *)(regs+1); 360 unsigned long *fpregs = current_thread_info()->fpregs;
358 unsigned long fprs; 361 unsigned long fprs;
359 int err = 0; 362 int err = 0;
360 363
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 5a1126b363a..59f020d69d4 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -1,6 +1,6 @@
1/* smp.c: Sparc64 SMP support. 1/* smp.c: Sparc64 SMP support.
2 * 2 *
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) 3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#include <linux/module.h> 6#include <linux/module.h>
@@ -30,6 +30,7 @@
30#include <asm/cpudata.h> 30#include <asm/cpudata.h>
31#include <asm/hvtramp.h> 31#include <asm/hvtramp.h>
32#include <asm/io.h> 32#include <asm/io.h>
33#include <asm/timer.h>
33 34
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/irq_regs.h> 36#include <asm/irq_regs.h>
diff --git a/arch/sparc64/kernel/stacktrace.c b/arch/sparc64/kernel/stacktrace.c
index 47f92a59be1..84d39e873e8 100644
--- a/arch/sparc64/kernel/stacktrace.c
+++ b/arch/sparc64/kernel/stacktrace.c
@@ -2,13 +2,15 @@
2#include <linux/stacktrace.h> 2#include <linux/stacktrace.h>
3#include <linux/thread_info.h> 3#include <linux/thread_info.h>
4#include <asm/ptrace.h> 4#include <asm/ptrace.h>
5#include <asm/stacktrace.h>
5 6
6void save_stack_trace(struct stack_trace *trace) 7void save_stack_trace(struct stack_trace *trace)
7{ 8{
8 unsigned long ksp, fp, thread_base; 9 unsigned long ksp, fp, thread_base;
9 struct thread_info *tp = task_thread_info(current); 10 struct thread_info *tp = task_thread_info(current);
10 11
11 flushw_all(); 12 stack_trace_flush();
13
12 __asm__ __volatile__( 14 __asm__ __volatile__(
13 "mov %%fp, %0" 15 "mov %%fp, %0"
14 : "=r" (ksp) 16 : "=r" (ksp)
diff --git a/arch/sparc64/kernel/sys_sparc.c b/arch/sparc64/kernel/sys_sparc.c
index 134d801579f..f952745d0f3 100644
--- a/arch/sparc64/kernel/sys_sparc.c
+++ b/arch/sparc64/kernel/sys_sparc.c
@@ -1,5 +1,4 @@
1/* $Id: sys_sparc.c,v 1.57 2002/02/09 19:49:30 davem Exp $ 1/* linux/arch/sparc64/kernel/sys_sparc.c
2 * linux/arch/sparc64/kernel/sys_sparc.c
3 * 2 *
4 * This file contains various random system calls that 3 * This file contains various random system calls that
5 * have a non-standard calling sequence on the Linux/sparc 4 * have a non-standard calling sequence on the Linux/sparc
@@ -30,6 +29,9 @@
30#include <asm/perfctr.h> 29#include <asm/perfctr.h>
31#include <asm/unistd.h> 30#include <asm/unistd.h>
32 31
32#include "entry.h"
33#include "systbls.h"
34
33/* #define DEBUG_UNIMP_SYSCALL */ 35/* #define DEBUG_UNIMP_SYSCALL */
34 36
35asmlinkage unsigned long sys_getpagesize(void) 37asmlinkage unsigned long sys_getpagesize(void)
@@ -445,7 +447,8 @@ asmlinkage long sys_ipc(unsigned int call, int first, unsigned long second,
445 goto out; 447 goto out;
446 case SEMTIMEDOP: 448 case SEMTIMEDOP:
447 err = sys_semtimedop(first, ptr, (unsigned)second, 449 err = sys_semtimedop(first, ptr, (unsigned)second,
448 (const struct timespec __user *) fifth); 450 (const struct timespec __user *)
451 (unsigned long) fifth);
449 goto out; 452 goto out;
450 case SEMGET: 453 case SEMGET:
451 err = sys_semget(first, (int)second, (int)third); 454 err = sys_semget(first, (int)second, (int)third);
@@ -788,7 +791,7 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
788 } else { 791 } else {
789 if ((utrap_handler_t)current_thread_info()->utraps[type] != new_p && 792 if ((utrap_handler_t)current_thread_info()->utraps[type] != new_p &&
790 current_thread_info()->utraps[0] > 1) { 793 current_thread_info()->utraps[0] > 1) {
791 long *p = current_thread_info()->utraps; 794 unsigned long *p = current_thread_info()->utraps;
792 795
793 current_thread_info()->utraps = 796 current_thread_info()->utraps =
794 kmalloc((UT_TRAP_INSTRUCTION_31+1)*sizeof(long), 797 kmalloc((UT_TRAP_INSTRUCTION_31+1)*sizeof(long),
@@ -816,7 +819,8 @@ asmlinkage long sys_utrap_install(utrap_entry_t type,
816 return 0; 819 return 0;
817} 820}
818 821
819long sparc_memory_ordering(unsigned long model, struct pt_regs *regs) 822asmlinkage long sparc_memory_ordering(unsigned long model,
823 struct pt_regs *regs)
820{ 824{
821 if (model >= 3) 825 if (model >= 3)
822 return -EINVAL; 826 return -EINVAL;
diff --git a/arch/sparc64/kernel/systbls.h b/arch/sparc64/kernel/systbls.h
new file mode 100644
index 00000000000..8a0d20a35d0
--- /dev/null
+++ b/arch/sparc64/kernel/systbls.h
@@ -0,0 +1,53 @@
1#ifndef _SYSTBLS_H
2#define _SYSTBLS_H
3
4#include <linux/kernel.h>
5#include <linux/types.h>
6#include <linux/utsname.h>
7#include <asm/utrap.h>
8#include <asm/signal.h>
9
10extern asmlinkage unsigned long sys_getpagesize(void);
11extern asmlinkage unsigned long sparc_brk(unsigned long brk);
12extern asmlinkage long sparc_pipe(struct pt_regs *regs);
13extern asmlinkage long sys_ipc(unsigned int call, int first,
14 unsigned long second,
15 unsigned long third,
16 void __user *ptr, long fifth);
17extern asmlinkage long sparc64_newuname(struct new_utsname __user *name);
18extern asmlinkage long sparc64_personality(unsigned long personality);
19extern asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
20 unsigned long prot, unsigned long flags,
21 unsigned long fd, unsigned long off);
22extern asmlinkage long sys64_munmap(unsigned long addr, size_t len);
23extern asmlinkage unsigned long sys64_mremap(unsigned long addr,
24 unsigned long old_len,
25 unsigned long new_len,
26 unsigned long flags,
27 unsigned long new_addr);
28extern asmlinkage unsigned long c_sys_nis_syscall(struct pt_regs *regs);
29extern asmlinkage long sys_getdomainname(char __user *name, int len);
30extern asmlinkage long solaris_syscall(struct pt_regs *regs);
31extern asmlinkage long sunos_syscall(struct pt_regs *regs);
32extern asmlinkage long sys_utrap_install(utrap_entry_t type,
33 utrap_handler_t new_p,
34 utrap_handler_t new_d,
35 utrap_handler_t __user *old_p,
36 utrap_handler_t __user *old_d);
37extern asmlinkage long sparc_memory_ordering(unsigned long model,
38 struct pt_regs *regs);
39extern asmlinkage long sys_rt_sigaction(int sig,
40 const struct sigaction __user *act,
41 struct sigaction __user *oact,
42 void __user *restorer,
43 size_t sigsetsize);
44extern asmlinkage long sys_perfctr(int opcode, unsigned long arg0,
45 unsigned long arg1, unsigned long arg2);
46
47extern asmlinkage void sparc64_set_context(struct pt_regs *regs);
48extern asmlinkage void sparc64_get_context(struct pt_regs *regs);
49extern asmlinkage long sys_sigpause(unsigned int set);
50extern asmlinkage long sys_sigsuspend(old_sigset_t set);
51extern void do_rt_sigreturn(struct pt_regs *regs);
52
53#endif /* _SYSTBLS_H */
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index d204f1ab1d4..e5d238970c7 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -1,7 +1,6 @@
1/* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $ 1/* time.c: UltraSparc timer and TOD clock support.
2 * time.c: UltraSparc timer and TOD clock support.
3 * 2 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) 3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * 5 *
7 * Based largely on code which is: 6 * Based largely on code which is:
@@ -48,6 +47,8 @@
48#include <asm/uaccess.h> 47#include <asm/uaccess.h>
49#include <asm/irq_regs.h> 48#include <asm/irq_regs.h>
50 49
50#include "entry.h"
51
51DEFINE_SPINLOCK(mostek_lock); 52DEFINE_SPINLOCK(mostek_lock);
52DEFINE_SPINLOCK(rtc_lock); 53DEFINE_SPINLOCK(rtc_lock);
53void __iomem *mstk48t02_regs = NULL; 54void __iomem *mstk48t02_regs = NULL;
@@ -508,6 +509,37 @@ static int __init has_low_battery(void)
508 return (data1 == data2); /* Was the write blocked? */ 509 return (data1 == data2); /* Was the write blocked? */
509} 510}
510 511
512static void __init mostek_set_system_time(void __iomem *mregs)
513{
514 unsigned int year, mon, day, hour, min, sec;
515 u8 tmp;
516
517 spin_lock_irq(&mostek_lock);
518
519 /* Traditional Mostek chip. */
520 tmp = mostek_read(mregs + MOSTEK_CREG);
521 tmp |= MSTK_CREG_READ;
522 mostek_write(mregs + MOSTEK_CREG, tmp);
523
524 sec = MSTK_REG_SEC(mregs);
525 min = MSTK_REG_MIN(mregs);
526 hour = MSTK_REG_HOUR(mregs);
527 day = MSTK_REG_DOM(mregs);
528 mon = MSTK_REG_MONTH(mregs);
529 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
530
531 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
532 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
533 set_normalized_timespec(&wall_to_monotonic,
534 -xtime.tv_sec, -xtime.tv_nsec);
535
536 tmp = mostek_read(mregs + MOSTEK_CREG);
537 tmp &= ~MSTK_CREG_READ;
538 mostek_write(mregs + MOSTEK_CREG, tmp);
539
540 spin_unlock_irq(&mostek_lock);
541}
542
511/* Probe for the real time clock chip. */ 543/* Probe for the real time clock chip. */
512static void __init set_system_time(void) 544static void __init set_system_time(void)
513{ 545{
@@ -520,7 +552,6 @@ static void __init set_system_time(void)
520 unsigned long dregs = 0UL; 552 unsigned long dregs = 0UL;
521 void __iomem *bregs = 0UL; 553 void __iomem *bregs = 0UL;
522#endif 554#endif
523 u8 tmp;
524 555
525 if (!mregs && !dregs && !bregs) { 556 if (!mregs && !dregs && !bregs) {
526 prom_printf("Something wrong, clock regs not mapped yet.\n"); 557 prom_printf("Something wrong, clock regs not mapped yet.\n");
@@ -528,20 +559,11 @@ static void __init set_system_time(void)
528 } 559 }
529 560
530 if (mregs) { 561 if (mregs) {
531 spin_lock_irq(&mostek_lock); 562 mostek_set_system_time(mregs);
532 563 return;
533 /* Traditional Mostek chip. */ 564 }
534 tmp = mostek_read(mregs + MOSTEK_CREG);
535 tmp |= MSTK_CREG_READ;
536 mostek_write(mregs + MOSTEK_CREG, tmp);
537 565
538 sec = MSTK_REG_SEC(mregs); 566 if (bregs) {
539 min = MSTK_REG_MIN(mregs);
540 hour = MSTK_REG_HOUR(mregs);
541 day = MSTK_REG_DOM(mregs);
542 mon = MSTK_REG_MONTH(mregs);
543 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
544 } else if (bregs) {
545 unsigned char val = readb(bregs + 0x0e); 567 unsigned char val = readb(bregs + 0x0e);
546 unsigned int century; 568 unsigned int century;
547 569
@@ -596,14 +618,6 @@ static void __init set_system_time(void)
596 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); 618 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
597 set_normalized_timespec(&wall_to_monotonic, 619 set_normalized_timespec(&wall_to_monotonic,
598 -xtime.tv_sec, -xtime.tv_nsec); 620 -xtime.tv_sec, -xtime.tv_nsec);
599
600 if (mregs) {
601 tmp = mostek_read(mregs + MOSTEK_CREG);
602 tmp &= ~MSTK_CREG_READ;
603 mostek_write(mregs + MOSTEK_CREG, tmp);
604
605 spin_unlock_irq(&mostek_lock);
606 }
607} 621}
608 622
609/* davem suggests we keep this within the 4M locked kernel image */ 623/* davem suggests we keep this within the 4M locked kernel image */
@@ -1027,7 +1041,7 @@ void __init time_init(void)
1027 setup_clockevent_multiplier(clock); 1041 setup_clockevent_multiplier(clock);
1028 1042
1029 sparc64_clockevent.max_delta_ns = 1043 sparc64_clockevent.max_delta_ns =
1030 clockevent_delta2ns(0x7fffffffffffffff, &sparc64_clockevent); 1044 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
1031 sparc64_clockevent.min_delta_ns = 1045 sparc64_clockevent.min_delta_ns =
1032 clockevent_delta2ns(0xF, &sparc64_clockevent); 1046 clockevent_delta2ns(0xF, &sparc64_clockevent);
1033 1047
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 007f5317c0d..96da847023f 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -42,6 +42,7 @@
42#endif 42#endif
43#include <asm/prom.h> 43#include <asm/prom.h>
44 44
45#include "entry.h"
45 46
46/* When an irrecoverable trap occurs at tl > 0, the trap entry 47/* When an irrecoverable trap occurs at tl > 0, the trap entry
47 * code logs the trap state registers at every level in the trap 48 * code logs the trap state registers at every level in the trap
@@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
77 } 78 }
78} 79}
79 80
80void do_call_debug(struct pt_regs *regs)
81{
82 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
83}
84
85void bad_trap(struct pt_regs *regs, long lvl) 81void bad_trap(struct pt_regs *regs, long lvl)
86{ 82{
87 char buffer[32]; 83 char buffer[32];
@@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase;
550static unsigned long ecache_flush_linesize; 546static unsigned long ecache_flush_linesize;
551static unsigned long ecache_flush_size; 547static unsigned long ecache_flush_size;
552 548
553/* WARNING: The error trap handlers in assembly know the precise
554 * layout of the following structure.
555 *
556 * C-level handlers below use this information to log the error
557 * and then determine how to recover (if possible).
558 */
559struct cheetah_err_info {
560/*0x00*/u64 afsr;
561/*0x08*/u64 afar;
562
563 /* D-cache state */
564/*0x10*/u64 dcache_data[4]; /* The actual data */
565/*0x30*/u64 dcache_index; /* D-cache index */
566/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
567/*0x40*/u64 dcache_utag; /* D-cache microtag */
568/*0x48*/u64 dcache_stag; /* D-cache snooptag */
569
570 /* I-cache state */
571/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
572/*0x90*/u64 icache_index; /* I-cache index */
573/*0x98*/u64 icache_tag; /* I-cache phys tag */
574/*0xa0*/u64 icache_utag; /* I-cache microtag */
575/*0xa8*/u64 icache_stag; /* I-cache snooptag */
576/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
577/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
578
579 /* E-cache state */
580/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
581/*0xe0*/u64 ecache_index; /* E-cache index */
582/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
583
584/*0xf0*/u64 __pad[32 - 30];
585};
586#define CHAFSR_INVALID ((u64)-1L)
587
588/* This table is ordered in priority of errors and matches the 549/* This table is ordered in priority of errors and matches the
589 * AFAR overwrite policy as well. 550 * AFAR overwrite policy as well.
590 */ 551 */
@@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = {
758static struct afsr_error_table *cheetah_error_table; 719static struct afsr_error_table *cheetah_error_table;
759static unsigned long cheetah_afsr_errors; 720static unsigned long cheetah_afsr_errors;
760 721
761/* This is allocated at boot time based upon the largest hardware
762 * cpu ID in the system. We allocate two entries per cpu, one for
763 * TL==0 logging and one for TL >= 1 logging.
764 */
765struct cheetah_err_info *cheetah_error_log; 722struct cheetah_err_info *cheetah_error_log;
766 723
767static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr) 724static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
@@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs)
2102 force_sig_info(SIGFPE, &info, current); 2059 force_sig_info(SIGFPE, &info, current);
2103} 2060}
2104 2061
2105void instruction_dump (unsigned int *pc) 2062static void instruction_dump(unsigned int *pc)
2106{ 2063{
2107 int i; 2064 int i;
2108 2065
@@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc)
2115 printk("\n"); 2072 printk("\n");
2116} 2073}
2117 2074
2118static void user_instruction_dump (unsigned int __user *pc) 2075static void user_instruction_dump(unsigned int __user *pc)
2119{ 2076{
2120 int i; 2077 int i;
2121 unsigned int buf[9]; 2078 unsigned int buf[9];
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 466fd6cffac..f37078d9640 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -46,6 +46,7 @@
46#include <asm/prom.h> 46#include <asm/prom.h>
47#include <asm/sstate.h> 47#include <asm/sstate.h>
48#include <asm/mdesc.h> 48#include <asm/mdesc.h>
49#include <asm/cpudata.h>
49 50
50#define MAX_PHYS_ADDRESS (1UL << 42UL) 51#define MAX_PHYS_ADDRESS (1UL << 42UL)
51#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL) 52#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
@@ -1273,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void)
1273 1274
1274/* paging_init() sets up the page tables */ 1275/* paging_init() sets up the page tables */
1275 1276
1276extern void cheetah_ecache_flush_init(void);
1277extern void sun4v_patch_tlb_handlers(void);
1278
1279extern void cpu_probe(void);
1280extern void central_probe(void); 1277extern void central_probe(void);
1281 1278
1282static unsigned long last_valid_pfn; 1279static unsigned long last_valid_pfn;
diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c
index 3f10fc921b0..ae24919cba7 100644
--- a/arch/sparc64/mm/tlb.c
+++ b/arch/sparc64/mm/tlb.c
@@ -23,9 +23,7 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) = { 0, };
23 23
24void flush_tlb_pending(void) 24void flush_tlb_pending(void)
25{ 25{
26 struct mmu_gather *mp = &__get_cpu_var(mmu_gathers); 26 struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
27
28 preempt_disable();
29 27
30 if (mp->tlb_nr) { 28 if (mp->tlb_nr) {
31 flush_tsb_user(mp); 29 flush_tsb_user(mp);
@@ -42,7 +40,7 @@ void flush_tlb_pending(void)
42 mp->tlb_nr = 0; 40 mp->tlb_nr = 0;
43 } 41 }
44 42
45 preempt_enable(); 43 put_cpu_var(mmu_gathers);
46} 44}
47 45
48void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig) 46void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 1e8f41a9951..1d43bdfc20c 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -256,11 +256,7 @@ static struct net_device_stats *uml_net_get_stats(struct net_device *dev)
256 256
257static void uml_net_set_multicast_list(struct net_device *dev) 257static void uml_net_set_multicast_list(struct net_device *dev)
258{ 258{
259 if (dev->flags & IFF_PROMISC) 259 return;
260 return;
261 else if (dev->mc_count)
262 dev->flags |= IFF_ALLMULTI;
263 else dev->flags &= ~IFF_ALLMULTI;
264} 260}
265 261
266static void uml_net_tx_timeout(struct net_device *dev) 262static void uml_net_tx_timeout(struct net_device *dev)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 45d79ea890a..5fed98ca0e1 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -65,7 +65,8 @@ __setup("noreplace-paravirt", setup_noreplace_paravirt);
65 get them easily into strings. */ 65 get them easily into strings. */
66asm("\t.section .rodata, \"a\"\nintelnops: " 66asm("\t.section .rodata, \"a\"\nintelnops: "
67 GENERIC_NOP1 GENERIC_NOP2 GENERIC_NOP3 GENERIC_NOP4 GENERIC_NOP5 GENERIC_NOP6 67 GENERIC_NOP1 GENERIC_NOP2 GENERIC_NOP3 GENERIC_NOP4 GENERIC_NOP5 GENERIC_NOP6
68 GENERIC_NOP7 GENERIC_NOP8); 68 GENERIC_NOP7 GENERIC_NOP8
69 "\t.previous");
69extern const unsigned char intelnops[]; 70extern const unsigned char intelnops[];
70static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = { 71static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
71 NULL, 72 NULL,
@@ -83,7 +84,8 @@ static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
83#ifdef K8_NOP1 84#ifdef K8_NOP1
84asm("\t.section .rodata, \"a\"\nk8nops: " 85asm("\t.section .rodata, \"a\"\nk8nops: "
85 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6 86 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
86 K8_NOP7 K8_NOP8); 87 K8_NOP7 K8_NOP8
88 "\t.previous");
87extern const unsigned char k8nops[]; 89extern const unsigned char k8nops[];
88static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = { 90static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
89 NULL, 91 NULL,
@@ -101,7 +103,8 @@ static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
101#ifdef K7_NOP1 103#ifdef K7_NOP1
102asm("\t.section .rodata, \"a\"\nk7nops: " 104asm("\t.section .rodata, \"a\"\nk7nops: "
103 K7_NOP1 K7_NOP2 K7_NOP3 K7_NOP4 K7_NOP5 K7_NOP6 105 K7_NOP1 K7_NOP2 K7_NOP3 K7_NOP4 K7_NOP5 K7_NOP6
104 K7_NOP7 K7_NOP8); 106 K7_NOP7 K7_NOP8
107 "\t.previous");
105extern const unsigned char k7nops[]; 108extern const unsigned char k7nops[];
106static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = { 109static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
107 NULL, 110 NULL,
@@ -119,7 +122,8 @@ static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
119#ifdef P6_NOP1 122#ifdef P6_NOP1
120asm("\t.section .rodata, \"a\"\np6nops: " 123asm("\t.section .rodata, \"a\"\np6nops: "
121 P6_NOP1 P6_NOP2 P6_NOP3 P6_NOP4 P6_NOP5 P6_NOP6 124 P6_NOP1 P6_NOP2 P6_NOP3 P6_NOP4 P6_NOP5 P6_NOP6
122 P6_NOP7 P6_NOP8); 125 P6_NOP7 P6_NOP8
126 "\t.previous");
123extern const unsigned char p6nops[]; 127extern const unsigned char p6nops[];
124static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = { 128static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
125 NULL, 129 NULL,
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 027e5c003b1..170d2f5523b 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -143,14 +143,6 @@ static void __init check_config(void)
143#endif 143#endif
144 144
145/* 145/*
146 * If we configured ourselves for a TSC, we'd better have one!
147 */
148#ifdef CONFIG_X86_TSC
149 if (!cpu_has_tsc)
150 panic("Kernel compiled for Pentium+, requires TSC feature!");
151#endif
152
153/*
154 * If we were told we had a good local APIC, check for buggy Pentia, 146 * If we were told we had a good local APIC, check for buggy Pentia,
155 * i.e. all B steppings and the C2 stepping of P54C when using their 147 * i.e. all B steppings and the C2 stepping of P54C when using their
156 * integrated APIC (see 11AP erratum in "Pentium Processor 148 * integrated APIC (see 11AP erratum in "Pentium Processor
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
index f2b5a621d27..8a85c93bd62 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-smi.c
@@ -63,7 +63,7 @@ static struct cpufreq_frequency_table speedstep_freqs[] = {
63 */ 63 */
64static int speedstep_smi_ownership (void) 64static int speedstep_smi_ownership (void)
65{ 65{
66 u32 command, result, magic; 66 u32 command, result, magic, dummy;
67 u32 function = GET_SPEEDSTEP_OWNER; 67 u32 function = GET_SPEEDSTEP_OWNER;
68 unsigned char magic_data[] = "Copyright (c) 1999 Intel Corporation"; 68 unsigned char magic_data[] = "Copyright (c) 1999 Intel Corporation";
69 69
@@ -73,8 +73,11 @@ static int speedstep_smi_ownership (void)
73 dprintk("trying to obtain ownership with command %x at port %x\n", command, smi_port); 73 dprintk("trying to obtain ownership with command %x at port %x\n", command, smi_port);
74 74
75 __asm__ __volatile__( 75 __asm__ __volatile__(
76 "push %%ebp\n"
76 "out %%al, (%%dx)\n" 77 "out %%al, (%%dx)\n"
77 : "=D" (result) 78 "pop %%ebp\n"
79 : "=D" (result), "=a" (dummy), "=b" (dummy), "=c" (dummy), "=d" (dummy),
80 "=S" (dummy)
78 : "a" (command), "b" (function), "c" (0), "d" (smi_port), 81 : "a" (command), "b" (function), "c" (0), "d" (smi_port),
79 "D" (0), "S" (magic) 82 "D" (0), "S" (magic)
80 : "memory" 83 : "memory"
@@ -96,7 +99,7 @@ static int speedstep_smi_ownership (void)
96 */ 99 */
97static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high) 100static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
98{ 101{
99 u32 command, result = 0, edi, high_mhz, low_mhz; 102 u32 command, result = 0, edi, high_mhz, low_mhz, dummy;
100 u32 state=0; 103 u32 state=0;
101 u32 function = GET_SPEEDSTEP_FREQS; 104 u32 function = GET_SPEEDSTEP_FREQS;
102 105
@@ -109,10 +112,12 @@ static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
109 112
110 dprintk("trying to determine frequencies with command %x at port %x\n", command, smi_port); 113 dprintk("trying to determine frequencies with command %x at port %x\n", command, smi_port);
111 114
112 __asm__ __volatile__("movl $0, %%edi\n" 115 __asm__ __volatile__(
116 "push %%ebp\n"
113 "out %%al, (%%dx)\n" 117 "out %%al, (%%dx)\n"
114 : "=a" (result), "=b" (high_mhz), "=c" (low_mhz), "=d" (state), "=D" (edi) 118 "pop %%ebp"
115 : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0) 119 : "=a" (result), "=b" (high_mhz), "=c" (low_mhz), "=d" (state), "=D" (edi), "=S" (dummy)
120 : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0), "D" (0)
116 ); 121 );
117 122
118 dprintk("result %x, low_freq %u, high_freq %u\n", result, low_mhz, high_mhz); 123 dprintk("result %x, low_freq %u, high_freq %u\n", result, low_mhz, high_mhz);
@@ -135,16 +140,18 @@ static int speedstep_smi_get_freqs (unsigned int *low, unsigned int *high)
135static int speedstep_get_state (void) 140static int speedstep_get_state (void)
136{ 141{
137 u32 function=GET_SPEEDSTEP_STATE; 142 u32 function=GET_SPEEDSTEP_STATE;
138 u32 result, state, edi, command; 143 u32 result, state, edi, command, dummy;
139 144
140 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff); 145 command = (smi_sig & 0xffffff00) | (smi_cmd & 0xff);
141 146
142 dprintk("trying to determine current setting with command %x at port %x\n", command, smi_port); 147 dprintk("trying to determine current setting with command %x at port %x\n", command, smi_port);
143 148
144 __asm__ __volatile__("movl $0, %%edi\n" 149 __asm__ __volatile__(
150 "push %%ebp\n"
145 "out %%al, (%%dx)\n" 151 "out %%al, (%%dx)\n"
146 : "=a" (result), "=b" (state), "=D" (edi) 152 "pop %%ebp\n"
147 : "a" (command), "b" (function), "c" (0), "d" (smi_port), "S" (0) 153 : "=a" (result), "=b" (state), "=D" (edi), "=c" (dummy), "=d" (dummy), "=S" (dummy)
154 : "a" (command), "b" (function), "c" (0), "d" (smi_port), "S" (0), "D" (0)
148 ); 155 );
149 156
150 dprintk("state is %x, result is %x\n", state, result); 157 dprintk("state is %x, result is %x\n", state, result);
@@ -160,7 +167,7 @@ static int speedstep_get_state (void)
160 */ 167 */
161static void speedstep_set_state (unsigned int state) 168static void speedstep_set_state (unsigned int state)
162{ 169{
163 unsigned int result = 0, command, new_state; 170 unsigned int result = 0, command, new_state, dummy;
164 unsigned long flags; 171 unsigned long flags;
165 unsigned int function=SET_SPEEDSTEP_STATE; 172 unsigned int function=SET_SPEEDSTEP_STATE;
166 unsigned int retry = 0; 173 unsigned int retry = 0;
@@ -182,10 +189,12 @@ static void speedstep_set_state (unsigned int state)
182 } 189 }
183 retry++; 190 retry++;
184 __asm__ __volatile__( 191 __asm__ __volatile__(
185 "movl $0, %%edi\n" 192 "push %%ebp\n"
186 "out %%al, (%%dx)\n" 193 "out %%al, (%%dx)\n"
187 : "=b" (new_state), "=D" (result) 194 "pop %%ebp"
188 : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0) 195 : "=b" (new_state), "=D" (result), "=c" (dummy), "=a" (dummy),
196 "=d" (dummy), "=S" (dummy)
197 : "a" (command), "b" (function), "c" (state), "d" (smi_port), "S" (0), "D" (0)
189 ); 198 );
190 } while ((new_state != state) && (retry <= SMI_TRIES)); 199 } while ((new_state != state) && (retry <= SMI_TRIES));
191 200
@@ -195,7 +204,7 @@ static void speedstep_set_state (unsigned int state)
195 if (new_state == state) { 204 if (new_state == state) {
196 dprintk("change to %u MHz succeeded after %u tries with result %u\n", (speedstep_freqs[new_state].frequency / 1000), retry, result); 205 dprintk("change to %u MHz succeeded after %u tries with result %u\n", (speedstep_freqs[new_state].frequency / 1000), retry, result);
197 } else { 206 } else {
198 printk(KERN_ERR "cpufreq: change failed with new_state %u and result %u\n", new_state, result); 207 printk(KERN_ERR "cpufreq: change to state %u failed with new_state %u and result %u\n", state, new_state, result);
199 } 208 }
200 209
201 return; 210 return;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 103d61a59b1..3e18db4cefe 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -176,12 +176,13 @@ static inline void k8_enable_fixed_iorrs(void)
176} 176}
177 177
178/** 178/**
179 * Checks and updates an fixed-range MTRR if it differs from the value it 179 * set_fixed_range - checks & updates a fixed-range MTRR if it differs from the value it should have
180 * should have. If K8 extentions are wanted, update the K8 SYSCFG MSR also. 180 * @msr: MSR address of the MTTR which should be checked and updated
181 * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information 181 * @changed: pointer which indicates whether the MTRR needed to be changed
182 * \param msr MSR address of the MTTR which should be checked and updated 182 * @msrwords: pointer to the MSR values which the MSR should have
183 * \param changed pointer which indicates whether the MTRR needed to be changed 183 *
184 * \param msrwords pointer to the MSR values which the MSR should have 184 * If K8 extentions are wanted, update the K8 SYSCFG MSR also.
185 * See AMD publication no. 24593, chapter 7.8.1, page 233 for more information.
185 */ 186 */
186static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 187static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
187{ 188{
@@ -199,12 +200,15 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
199 } 200 }
200} 201}
201 202
203/**
204 * generic_get_free_region - Get a free MTRR.
205 * @base: The starting (base) address of the region.
206 * @size: The size (in bytes) of the region.
207 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
208 *
209 * Returns: The index of the region on success, else negative on error.
210 */
202int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 211int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
203/* [SUMMARY] Get a free MTRR.
204 <base> The starting (base) address of the region.
205 <size> The size (in bytes) of the region.
206 [RETURNS] The index of the region on success, else -1 on error.
207*/
208{ 212{
209 int i, max; 213 int i, max;
210 mtrr_type ltype; 214 mtrr_type ltype;
@@ -249,8 +253,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
249} 253}
250 254
251/** 255/**
252 * Checks and updates the fixed-range MTRRs if they differ from the saved set 256 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they differ from the saved set
253 * \param frs pointer to fixed-range MTRR values, saved by get_fixed_ranges() 257 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
254 */ 258 */
255static int set_fixed_ranges(mtrr_type * frs) 259static int set_fixed_ranges(mtrr_type * frs)
256{ 260{
@@ -294,13 +298,13 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
294 298
295static u32 deftype_lo, deftype_hi; 299static u32 deftype_lo, deftype_hi;
296 300
301/**
302 * set_mtrr_state - Set the MTRR state for this CPU.
303 *
304 * NOTE: The CPU must already be in a safe state for MTRR changes.
305 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
306 */
297static unsigned long set_mtrr_state(void) 307static unsigned long set_mtrr_state(void)
298/* [SUMMARY] Set the MTRR state for this CPU.
299 <state> The MTRR state information to read.
300 <ctxt> Some relevant CPU context.
301 [NOTE] The CPU must already be in a safe state for MTRR changes.
302 [RETURNS] 0 if no changes made, else a mask indication what was changed.
303*/
304{ 308{
305 unsigned int i; 309 unsigned int i;
306 unsigned long change_mask = 0; 310 unsigned long change_mask = 0;
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 9b838324b81..b943e10ad81 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -652,9 +652,6 @@ static void probe_nmi_watchdog(void)
652 wd_ops = &p6_wd_ops; 652 wd_ops = &p6_wd_ops;
653 break; 653 break;
654 case 15: 654 case 15:
655 if (boot_cpu_data.x86_model > 0x4)
656 return;
657
658 wd_ops = &p4_wd_ops; 655 wd_ops = &p4_wd_ops;
659 break; 656 break;
660 default: 657 default:
@@ -670,8 +667,10 @@ int lapic_watchdog_init(unsigned nmi_hz)
670{ 667{
671 if (!wd_ops) { 668 if (!wd_ops) {
672 probe_nmi_watchdog(); 669 probe_nmi_watchdog();
673 if (!wd_ops) 670 if (!wd_ops) {
671 printk(KERN_INFO "NMI watchdog: CPU not supported\n");
674 return -1; 672 return -1;
673 }
675 674
676 if (!wd_ops->reserve()) { 675 if (!wd_ops->reserve()) {
677 printk(KERN_ERR 676 printk(KERN_ERR
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 235fd6c7750..36652ea1a26 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -133,13 +133,16 @@ static void hpet_reserve_platform_timers(unsigned long id)
133#ifdef CONFIG_HPET_EMULATE_RTC 133#ifdef CONFIG_HPET_EMULATE_RTC
134 hpet_reserve_timer(&hd, 1); 134 hpet_reserve_timer(&hd, 1);
135#endif 135#endif
136
136 hd.hd_irq[0] = HPET_LEGACY_8254; 137 hd.hd_irq[0] = HPET_LEGACY_8254;
137 hd.hd_irq[1] = HPET_LEGACY_RTC; 138 hd.hd_irq[1] = HPET_LEGACY_RTC;
138 139
139 for (i = 2; i < nrtimers; timer++, i++) 140 for (i = 2; i < nrtimers; timer++, i++)
140 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> 141 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
141 Tn_INT_ROUTE_CNF_SHIFT; 142 Tn_INT_ROUTE_CNF_SHIFT;
143
142 hpet_alloc(&hd); 144 hpet_alloc(&hd);
145
143} 146}
144#else 147#else
145static void hpet_reserve_platform_timers(unsigned long id) { } 148static void hpet_reserve_platform_timers(unsigned long id) { }
diff --git a/arch/x86/kernel/io_delay.c b/arch/x86/kernel/io_delay.c
index c706a306155..5921e5f0a64 100644
--- a/arch/x86/kernel/io_delay.c
+++ b/arch/x86/kernel/io_delay.c
@@ -78,6 +78,14 @@ static struct dmi_system_id __initdata io_delay_0xed_port_dmi_table[] = {
78 }, 78 },
79 { 79 {
80 .callback = dmi_io_delay_0xed_port, 80 .callback = dmi_io_delay_0xed_port,
81 .ident = "HP Pavilion dv6000",
82 .matches = {
83 DMI_MATCH(DMI_BOARD_VENDOR, "Quanta"),
84 DMI_MATCH(DMI_BOARD_NAME, "30B8")
85 }
86 },
87 {
88 .callback = dmi_io_delay_0xed_port,
81 .ident = "HP Pavilion tx1000", 89 .ident = "HP Pavilion tx1000",
82 .matches = { 90 .matches = {
83 DMI_MATCH(DMI_BOARD_VENDOR, "Quanta"), 91 DMI_MATCH(DMI_BOARD_VENDOR, "Quanta"),
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 236d2f8f7dd..576a03db451 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -233,6 +233,7 @@ NORET_TYPE void machine_kexec(struct kimage *image)
233 233
234void arch_crash_save_vmcoreinfo(void) 234void arch_crash_save_vmcoreinfo(void)
235{ 235{
236 VMCOREINFO_SYMBOL(phys_base);
236 VMCOREINFO_SYMBOL(init_level4_pgt); 237 VMCOREINFO_SYMBOL(init_level4_pgt);
237 238
238#ifdef CONFIG_NUMA 239#ifdef CONFIG_NUMA
diff --git a/arch/x86/kernel/mfgpt_32.c b/arch/x86/kernel/mfgpt_32.c
index 027fc067b39..b402c0f3f19 100644
--- a/arch/x86/kernel/mfgpt_32.c
+++ b/arch/x86/kernel/mfgpt_32.c
@@ -30,6 +30,7 @@
30 30
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/module.h>
33#include <asm/geode.h> 34#include <asm/geode.h>
34 35
35static struct mfgpt_timer_t { 36static struct mfgpt_timer_t {
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index faf3229f8fb..700e4647dd3 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -615,8 +615,8 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
615 615
616 nommu: 616 nommu:
617 /* Should not happen anymore */ 617 /* Should not happen anymore */
618 printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n" 618 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
619 KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n"); 619 KERN_WARNING "falling back to iommu=soft.\n");
620 return -1; 620 return -1;
621} 621}
622 622
@@ -692,9 +692,9 @@ void __init gart_iommu_init(void)
692 !gart_iommu_aperture || 692 !gart_iommu_aperture ||
693 (no_agp && init_k8_gatt(&info) < 0)) { 693 (no_agp && init_k8_gatt(&info) < 0)) {
694 if (end_pfn > MAX_DMA32_PFN) { 694 if (end_pfn > MAX_DMA32_PFN) {
695 printk(KERN_ERR "WARNING more than 4GB of memory " 695 printk(KERN_WARNING "More than 4GB of memory "
696 "but GART IOMMU not available.\n" 696 "but GART IOMMU not available.\n"
697 KERN_ERR "WARNING 32bit PCI may malfunction.\n"); 697 KERN_WARNING "falling back to iommu=soft.\n");
698 } 698 }
699 return; 699 return;
700 } 700 }
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index be3c7a299f0..43930e73f65 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -82,7 +82,6 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
82 */ 82 */
83void (*pm_idle)(void); 83void (*pm_idle)(void);
84EXPORT_SYMBOL(pm_idle); 84EXPORT_SYMBOL(pm_idle);
85static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
86 85
87void disable_hlt(void) 86void disable_hlt(void)
88{ 87{
@@ -190,9 +189,6 @@ void cpu_idle(void)
190 while (!need_resched()) { 189 while (!need_resched()) {
191 void (*idle)(void); 190 void (*idle)(void);
192 191
193 if (__get_cpu_var(cpu_idle_state))
194 __get_cpu_var(cpu_idle_state) = 0;
195
196 check_pgt_cache(); 192 check_pgt_cache();
197 rmb(); 193 rmb();
198 idle = pm_idle; 194 idle = pm_idle;
@@ -220,40 +216,19 @@ static void do_nothing(void *unused)
220{ 216{
221} 217}
222 218
219/*
220 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
221 * pm_idle and update to new pm_idle value. Required while changing pm_idle
222 * handler on SMP systems.
223 *
224 * Caller must have changed pm_idle to the new value before the call. Old
225 * pm_idle value will not be used by any CPU after the return of this function.
226 */
223void cpu_idle_wait(void) 227void cpu_idle_wait(void)
224{ 228{
225 unsigned int cpu, this_cpu = get_cpu(); 229 smp_mb();
226 cpumask_t map, tmp = current->cpus_allowed; 230 /* kick all the CPUs so that they exit out of pm_idle */
227 231 smp_call_function(do_nothing, NULL, 0, 1);
228 set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
229 put_cpu();
230
231 cpus_clear(map);
232 for_each_online_cpu(cpu) {
233 per_cpu(cpu_idle_state, cpu) = 1;
234 cpu_set(cpu, map);
235 }
236
237 __get_cpu_var(cpu_idle_state) = 0;
238
239 wmb();
240 do {
241 ssleep(1);
242 for_each_online_cpu(cpu) {
243 if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
244 cpu_clear(cpu, map);
245 }
246 cpus_and(map, map, cpu_online_map);
247 /*
248 * We waited 1 sec, if a CPU still did not call idle
249 * it may be because it is in idle and not waking up
250 * because it has nothing to do.
251 * Give all the remaining CPUS a kick.
252 */
253 smp_call_function_mask(map, do_nothing, NULL, 0);
254 } while (!cpus_empty(map));
255
256 set_cpus_allowed(current, tmp);
257} 232}
258EXPORT_SYMBOL_GPL(cpu_idle_wait); 233EXPORT_SYMBOL_GPL(cpu_idle_wait);
259 234
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 3baf9b9f4c8..46c4c546b49 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -63,7 +63,6 @@ EXPORT_SYMBOL(boot_option_idle_override);
63 */ 63 */
64void (*pm_idle)(void); 64void (*pm_idle)(void);
65EXPORT_SYMBOL(pm_idle); 65EXPORT_SYMBOL(pm_idle);
66static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
67 66
68static ATOMIC_NOTIFIER_HEAD(idle_notifier); 67static ATOMIC_NOTIFIER_HEAD(idle_notifier);
69 68
@@ -173,9 +172,6 @@ void cpu_idle(void)
173 while (!need_resched()) { 172 while (!need_resched()) {
174 void (*idle)(void); 173 void (*idle)(void);
175 174
176 if (__get_cpu_var(cpu_idle_state))
177 __get_cpu_var(cpu_idle_state) = 0;
178
179 rmb(); 175 rmb();
180 idle = pm_idle; 176 idle = pm_idle;
181 if (!idle) 177 if (!idle)
@@ -207,40 +203,19 @@ static void do_nothing(void *unused)
207{ 203{
208} 204}
209 205
206/*
207 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
208 * pm_idle and update to new pm_idle value. Required while changing pm_idle
209 * handler on SMP systems.
210 *
211 * Caller must have changed pm_idle to the new value before the call. Old
212 * pm_idle value will not be used by any CPU after the return of this function.
213 */
210void cpu_idle_wait(void) 214void cpu_idle_wait(void)
211{ 215{
212 unsigned int cpu, this_cpu = get_cpu(); 216 smp_mb();
213 cpumask_t map, tmp = current->cpus_allowed; 217 /* kick all the CPUs so that they exit out of pm_idle */
214 218 smp_call_function(do_nothing, NULL, 0, 1);
215 set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
216 put_cpu();
217
218 cpus_clear(map);
219 for_each_online_cpu(cpu) {
220 per_cpu(cpu_idle_state, cpu) = 1;
221 cpu_set(cpu, map);
222 }
223
224 __get_cpu_var(cpu_idle_state) = 0;
225
226 wmb();
227 do {
228 ssleep(1);
229 for_each_online_cpu(cpu) {
230 if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
231 cpu_clear(cpu, map);
232 }
233 cpus_and(map, map, cpu_online_map);
234 /*
235 * We waited 1 sec, if a CPU still did not call idle
236 * it may be because it is in idle and not waking up
237 * because it has nothing to do.
238 * Give all the remaining CPUS a kick.
239 */
240 smp_call_function_mask(map, do_nothing, 0, 0);
241 } while (!cpus_empty(map));
242
243 set_cpus_allowed(current, tmp);
244} 219}
245EXPORT_SYMBOL_GPL(cpu_idle_wait); 220EXPORT_SYMBOL_GPL(cpu_idle_wait);
246 221
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index d5904eef1d3..eb92ccbb350 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -600,21 +600,6 @@ static int ptrace_bts_read_record(struct task_struct *child,
600 return sizeof(ret); 600 return sizeof(ret);
601} 601}
602 602
603static int ptrace_bts_write_record(struct task_struct *child,
604 const struct bts_struct *in)
605{
606 int retval;
607
608 if (!child->thread.ds_area_msr)
609 return -ENXIO;
610
611 retval = ds_write_bts((void *)child->thread.ds_area_msr, in);
612 if (retval)
613 return retval;
614
615 return sizeof(*in);
616}
617
618static int ptrace_bts_clear(struct task_struct *child) 603static int ptrace_bts_clear(struct task_struct *child)
619{ 604{
620 if (!child->thread.ds_area_msr) 605 if (!child->thread.ds_area_msr)
@@ -657,75 +642,6 @@ static int ptrace_bts_drain(struct task_struct *child,
657 return end; 642 return end;
658} 643}
659 644
660static int ptrace_bts_realloc(struct task_struct *child,
661 int size, int reduce_size)
662{
663 unsigned long rlim, vm;
664 int ret, old_size;
665
666 if (size < 0)
667 return -EINVAL;
668
669 old_size = ds_get_bts_size((void *)child->thread.ds_area_msr);
670 if (old_size < 0)
671 return old_size;
672
673 ret = ds_free((void **)&child->thread.ds_area_msr);
674 if (ret < 0)
675 goto out;
676
677 size >>= PAGE_SHIFT;
678 old_size >>= PAGE_SHIFT;
679
680 current->mm->total_vm -= old_size;
681 current->mm->locked_vm -= old_size;
682
683 if (size == 0)
684 goto out;
685
686 rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
687 vm = current->mm->total_vm + size;
688 if (rlim < vm) {
689 ret = -ENOMEM;
690
691 if (!reduce_size)
692 goto out;
693
694 size = rlim - current->mm->total_vm;
695 if (size <= 0)
696 goto out;
697 }
698
699 rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
700 vm = current->mm->locked_vm + size;
701 if (rlim < vm) {
702 ret = -ENOMEM;
703
704 if (!reduce_size)
705 goto out;
706
707 size = rlim - current->mm->locked_vm;
708 if (size <= 0)
709 goto out;
710 }
711
712 ret = ds_allocate((void **)&child->thread.ds_area_msr,
713 size << PAGE_SHIFT);
714 if (ret < 0)
715 goto out;
716
717 current->mm->total_vm += size;
718 current->mm->locked_vm += size;
719
720out:
721 if (child->thread.ds_area_msr)
722 set_tsk_thread_flag(child, TIF_DS_AREA_MSR);
723 else
724 clear_tsk_thread_flag(child, TIF_DS_AREA_MSR);
725
726 return ret;
727}
728
729static int ptrace_bts_config(struct task_struct *child, 645static int ptrace_bts_config(struct task_struct *child,
730 long cfg_size, 646 long cfg_size,
731 const struct ptrace_bts_config __user *ucfg) 647 const struct ptrace_bts_config __user *ucfg)
@@ -828,6 +744,91 @@ static int ptrace_bts_status(struct task_struct *child,
828 return sizeof(cfg); 744 return sizeof(cfg);
829} 745}
830 746
747
748static int ptrace_bts_write_record(struct task_struct *child,
749 const struct bts_struct *in)
750{
751 int retval;
752
753 if (!child->thread.ds_area_msr)
754 return -ENXIO;
755
756 retval = ds_write_bts((void *)child->thread.ds_area_msr, in);
757 if (retval)
758 return retval;
759
760 return sizeof(*in);
761}
762
763static int ptrace_bts_realloc(struct task_struct *child,
764 int size, int reduce_size)
765{
766 unsigned long rlim, vm;
767 int ret, old_size;
768
769 if (size < 0)
770 return -EINVAL;
771
772 old_size = ds_get_bts_size((void *)child->thread.ds_area_msr);
773 if (old_size < 0)
774 return old_size;
775
776 ret = ds_free((void **)&child->thread.ds_area_msr);
777 if (ret < 0)
778 goto out;
779
780 size >>= PAGE_SHIFT;
781 old_size >>= PAGE_SHIFT;
782
783 current->mm->total_vm -= old_size;
784 current->mm->locked_vm -= old_size;
785
786 if (size == 0)
787 goto out;
788
789 rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
790 vm = current->mm->total_vm + size;
791 if (rlim < vm) {
792 ret = -ENOMEM;
793
794 if (!reduce_size)
795 goto out;
796
797 size = rlim - current->mm->total_vm;
798 if (size <= 0)
799 goto out;
800 }
801
802 rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
803 vm = current->mm->locked_vm + size;
804 if (rlim < vm) {
805 ret = -ENOMEM;
806
807 if (!reduce_size)
808 goto out;
809
810 size = rlim - current->mm->locked_vm;
811 if (size <= 0)
812 goto out;
813 }
814
815 ret = ds_allocate((void **)&child->thread.ds_area_msr,
816 size << PAGE_SHIFT);
817 if (ret < 0)
818 goto out;
819
820 current->mm->total_vm += size;
821 current->mm->locked_vm += size;
822
823out:
824 if (child->thread.ds_area_msr)
825 set_tsk_thread_flag(child, TIF_DS_AREA_MSR);
826 else
827 clear_tsk_thread_flag(child, TIF_DS_AREA_MSR);
828
829 return ret;
830}
831
831void ptrace_bts_take_timestamp(struct task_struct *tsk, 832void ptrace_bts_take_timestamp(struct task_struct *tsk,
832 enum bts_qualifier qualifier) 833 enum bts_qualifier qualifier)
833{ 834{
diff --git a/arch/x86/kernel/setup_32.c b/arch/x86/kernel/setup_32.c
index a1d7071a51c..2b3e5d45176 100644
--- a/arch/x86/kernel/setup_32.c
+++ b/arch/x86/kernel/setup_32.c
@@ -406,8 +406,6 @@ static unsigned long __init setup_memory(void)
406 */ 406 */
407 min_low_pfn = PFN_UP(init_pg_tables_end); 407 min_low_pfn = PFN_UP(init_pg_tables_end);
408 408
409 find_max_pfn();
410
411 max_low_pfn = find_max_low_pfn(); 409 max_low_pfn = find_max_low_pfn();
412 410
413#ifdef CONFIG_HIGHMEM 411#ifdef CONFIG_HIGHMEM
@@ -764,12 +762,13 @@ void __init setup_arch(char **cmdline_p)
764 if (efi_enabled) 762 if (efi_enabled)
765 efi_init(); 763 efi_init();
766 764
767 max_low_pfn = setup_memory();
768
769 /* update e820 for memory not covered by WB MTRRs */ 765 /* update e820 for memory not covered by WB MTRRs */
766 find_max_pfn();
770 mtrr_bp_init(); 767 mtrr_bp_init();
771 if (mtrr_trim_uncached_memory(max_pfn)) 768 if (mtrr_trim_uncached_memory(max_pfn))
772 max_low_pfn = setup_memory(); 769 find_max_pfn();
770
771 max_low_pfn = setup_memory();
773 772
774#ifdef CONFIG_VMI 773#ifdef CONFIG_VMI
775 /* 774 /*
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 7637dc91c79..f4f7ecfb898 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -801,7 +801,7 @@ static void __cpuinit srat_detect_node(void)
801 /* Don't do the funky fallback heuristics the AMD version employs 801 /* Don't do the funky fallback heuristics the AMD version employs
802 for now. */ 802 for now. */
803 node = apicid_to_node[apicid]; 803 node = apicid_to_node[apicid];
804 if (node == NUMA_NO_NODE) 804 if (node == NUMA_NO_NODE || !node_online(node))
805 node = first_node(node_online_map); 805 node = first_node(node_online_map);
806 numa_set_node(cpu, node); 806 numa_set_node(cpu, node);
807 807
diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c
index 9d406cdc847..071ff479823 100644
--- a/arch/x86/kernel/step.c
+++ b/arch/x86/kernel/step.c
@@ -140,6 +140,9 @@ static int enable_single_step(struct task_struct *child)
140 */ 140 */
141static void write_debugctlmsr(struct task_struct *child, unsigned long val) 141static void write_debugctlmsr(struct task_struct *child, unsigned long val)
142{ 142{
143 if (child->thread.debugctlmsr == val)
144 return;
145
143 child->thread.debugctlmsr = val; 146 child->thread.debugctlmsr = val;
144 147
145 if (child != current) 148 if (child != current)
@@ -165,11 +168,11 @@ static void enable_step(struct task_struct *child, bool block)
165 write_debugctlmsr(child, 168 write_debugctlmsr(child,
166 child->thread.debugctlmsr | DEBUGCTLMSR_BTF); 169 child->thread.debugctlmsr | DEBUGCTLMSR_BTF);
167 } else { 170 } else {
168 write_debugctlmsr(child, 171 write_debugctlmsr(child,
169 child->thread.debugctlmsr & ~DEBUGCTLMSR_BTF); 172 child->thread.debugctlmsr & ~DEBUGCTLMSR_BTF);
170 173
171 if (!child->thread.debugctlmsr) 174 if (!child->thread.debugctlmsr)
172 clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR); 175 clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
173 } 176 }
174} 177}
175 178
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index 022bcaa3b42..ab6bf375a30 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -92,7 +92,7 @@ int do_set_thread_area(struct task_struct *p, int idx,
92asmlinkage int sys_set_thread_area(struct user_desc __user *u_info) 92asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)
93{ 93{
94 int ret = do_set_thread_area(current, -1, u_info, 1); 94 int ret = do_set_thread_area(current, -1, u_info, 1);
95 prevent_tail_call(ret); 95 asmlinkage_protect(1, ret, u_info);
96 return ret; 96 return ret;
97} 97}
98 98
@@ -142,7 +142,7 @@ int do_get_thread_area(struct task_struct *p, int idx,
142asmlinkage int sys_get_thread_area(struct user_desc __user *u_info) 142asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
143{ 143{
144 int ret = do_get_thread_area(current, -1, u_info); 144 int ret = do_get_thread_area(current, -1, u_info);
145 prevent_tail_call(ret); 145 asmlinkage_protect(1, ret, u_info);
146 return ret; 146 return ret;
147} 147}
148 148
diff --git a/arch/x86/kernel/tsc_32.c b/arch/x86/kernel/tsc_32.c
index f14cfd9d1f9..c2241e04ea5 100644
--- a/arch/x86/kernel/tsc_32.c
+++ b/arch/x86/kernel/tsc_32.c
@@ -256,9 +256,7 @@ time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
256 ref_freq, freq->new); 256 ref_freq, freq->new);
257 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) { 257 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
258 tsc_khz = cpu_khz; 258 tsc_khz = cpu_khz;
259 preempt_disable(); 259 set_cyc2ns_scale(cpu_khz, freq->cpu);
260 set_cyc2ns_scale(cpu_khz, smp_processor_id());
261 preempt_enable();
262 /* 260 /*
263 * TSC based sched_clock turns 261 * TSC based sched_clock turns
264 * to junk w/ cpufreq 262 * to junk w/ cpufreq
diff --git a/arch/x86/kernel/tsc_64.c b/arch/x86/kernel/tsc_64.c
index 947554ddabb..d3bebaaad84 100644
--- a/arch/x86/kernel/tsc_64.c
+++ b/arch/x86/kernel/tsc_64.c
@@ -148,9 +148,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
148 mark_tsc_unstable("cpufreq changes"); 148 mark_tsc_unstable("cpufreq changes");
149 } 149 }
150 150
151 preempt_disable(); 151 set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
152 set_cyc2ns_scale(tsc_khz_ref, smp_processor_id());
153 preempt_enable();
154 152
155 return 0; 153 return 0;
156} 154}
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index a104c532ff7..3335b4595ef 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -10,21 +10,19 @@
10 * (such as the example in Documentation/lguest/lguest.c) is called the 10 * (such as the example in Documentation/lguest/lguest.c) is called the
11 * Launcher. 11 * Launcher.
12 * 12 *
13 * Secondly, we only run specially modified Guests, not normal kernels. When 13 * Secondly, we only run specially modified Guests, not normal kernels: setting
14 * you set CONFIG_LGUEST to 'y' or 'm', this automatically sets 14 * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows
15 * CONFIG_LGUEST_GUEST=y, which compiles this file into the kernel so it knows 15 * how to be a Guest at boot time. This means that you can use the same kernel
16 * how to be a Guest. This means that you can use the same kernel you boot 16 * you boot normally (ie. as a Host) as a Guest.
17 * normally (ie. as a Host) as a Guest.
18 * 17 *
19 * These Guests know that they cannot do privileged operations, such as disable 18 * These Guests know that they cannot do privileged operations, such as disable
20 * interrupts, and that they have to ask the Host to do such things explicitly. 19 * interrupts, and that they have to ask the Host to do such things explicitly.
21 * This file consists of all the replacements for such low-level native 20 * This file consists of all the replacements for such low-level native
22 * hardware operations: these special Guest versions call the Host. 21 * hardware operations: these special Guest versions call the Host.
23 * 22 *
24 * So how does the kernel know it's a Guest? The Guest starts at a special 23 * So how does the kernel know it's a Guest? We'll see that later, but let's
25 * entry point marked with a magic string, which sets up a few things then 24 * just say that we end up here where we replace the native functions various
26 * calls here. We replace the native functions various "paravirt" structures 25 * "paravirt" structures with our Guest versions, then boot like normal. :*/
27 * with our Guest versions, then boot like normal. :*/
28 26
29/* 27/*
30 * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation. 28 * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation.
@@ -134,7 +132,7 @@ static void async_hcall(unsigned long call, unsigned long arg1,
134 * lguest_leave_lazy_mode(). 132 * lguest_leave_lazy_mode().
135 * 133 *
136 * So, when we're in lazy mode, we call async_hcall() to store the call for 134 * So, when we're in lazy mode, we call async_hcall() to store the call for
137 * future processing. */ 135 * future processing: */
138static void lazy_hcall(unsigned long call, 136static void lazy_hcall(unsigned long call,
139 unsigned long arg1, 137 unsigned long arg1,
140 unsigned long arg2, 138 unsigned long arg2,
@@ -147,7 +145,7 @@ static void lazy_hcall(unsigned long call,
147} 145}
148 146
149/* When lazy mode is turned off reset the per-cpu lazy mode variable and then 147/* When lazy mode is turned off reset the per-cpu lazy mode variable and then
150 * issue a hypercall to flush any stored calls. */ 148 * issue the do-nothing hypercall to flush any stored calls. */
151static void lguest_leave_lazy_mode(void) 149static void lguest_leave_lazy_mode(void)
152{ 150{
153 paravirt_leave_lazy(paravirt_get_lazy_mode()); 151 paravirt_leave_lazy(paravirt_get_lazy_mode());
@@ -164,7 +162,7 @@ static void lguest_leave_lazy_mode(void)
164 * 162 *
165 * So instead we keep an "irq_enabled" field inside our "struct lguest_data", 163 * So instead we keep an "irq_enabled" field inside our "struct lguest_data",
166 * which the Guest can update with a single instruction. The Host knows to 164 * which the Guest can update with a single instruction. The Host knows to
167 * check there when it wants to deliver an interrupt. 165 * check there before it tries to deliver an interrupt.
168 */ 166 */
169 167
170/* save_flags() is expected to return the processor state (ie. "flags"). The 168/* save_flags() is expected to return the processor state (ie. "flags"). The
@@ -196,10 +194,15 @@ static void irq_enable(void)
196/*M:003 Note that we don't check for outstanding interrupts when we re-enable 194/*M:003 Note that we don't check for outstanding interrupts when we re-enable
197 * them (or when we unmask an interrupt). This seems to work for the moment, 195 * them (or when we unmask an interrupt). This seems to work for the moment,
198 * since interrupts are rare and we'll just get the interrupt on the next timer 196 * since interrupts are rare and we'll just get the interrupt on the next timer
199 * tick, but when we turn on CONFIG_NO_HZ, we should revisit this. One way 197 * tick, but now we can run with CONFIG_NO_HZ, we should revisit this. One way
200 * would be to put the "irq_enabled" field in a page by itself, and have the 198 * would be to put the "irq_enabled" field in a page by itself, and have the
201 * Host write-protect it when an interrupt comes in when irqs are disabled. 199 * Host write-protect it when an interrupt comes in when irqs are disabled.
202 * There will then be a page fault as soon as interrupts are re-enabled. :*/ 200 * There will then be a page fault as soon as interrupts are re-enabled.
201 *
202 * A better method is to implement soft interrupt disable generally for x86:
203 * instead of disabling interrupts, we set a flag. If an interrupt does come
204 * in, we then disable them for real. This is uncommon, so we could simply use
205 * a hypercall for interrupt control and not worry about efficiency. :*/
203 206
204/*G:034 207/*G:034
205 * The Interrupt Descriptor Table (IDT). 208 * The Interrupt Descriptor Table (IDT).
@@ -212,6 +215,10 @@ static void irq_enable(void)
212static void lguest_write_idt_entry(gate_desc *dt, 215static void lguest_write_idt_entry(gate_desc *dt,
213 int entrynum, const gate_desc *g) 216 int entrynum, const gate_desc *g)
214{ 217{
218 /* The gate_desc structure is 8 bytes long: we hand it to the Host in
219 * two 32-bit chunks. The whole 32-bit kernel used to hand descriptors
220 * around like this; typesafety wasn't a big concern in Linux's early
221 * years. */
215 u32 *desc = (u32 *)g; 222 u32 *desc = (u32 *)g;
216 /* Keep the local copy up to date. */ 223 /* Keep the local copy up to date. */
217 native_write_idt_entry(dt, entrynum, g); 224 native_write_idt_entry(dt, entrynum, g);
@@ -243,7 +250,8 @@ static void lguest_load_idt(const struct desc_ptr *desc)
243 * 250 *
244 * This is the opposite of the IDT code where we have a LOAD_IDT_ENTRY 251 * This is the opposite of the IDT code where we have a LOAD_IDT_ENTRY
245 * hypercall and use that repeatedly to load a new IDT. I don't think it 252 * hypercall and use that repeatedly to load a new IDT. I don't think it
246 * really matters, but wouldn't it be nice if they were the same? 253 * really matters, but wouldn't it be nice if they were the same? Wouldn't
254 * it be even better if you were the one to send the patch to fix it?
247 */ 255 */
248static void lguest_load_gdt(const struct desc_ptr *desc) 256static void lguest_load_gdt(const struct desc_ptr *desc)
249{ 257{
@@ -298,9 +306,9 @@ static void lguest_load_tr_desc(void)
298 306
299/* The "cpuid" instruction is a way of querying both the CPU identity 307/* The "cpuid" instruction is a way of querying both the CPU identity
300 * (manufacturer, model, etc) and its features. It was introduced before the 308 * (manufacturer, model, etc) and its features. It was introduced before the
301 * Pentium in 1993 and keeps getting extended by both Intel and AMD. As you 309 * Pentium in 1993 and keeps getting extended by both Intel, AMD and others.
302 * might imagine, after a decade and a half this treatment, it is now a giant 310 * As you might imagine, after a decade and a half this treatment, it is now a
303 * ball of hair. Its entry in the current Intel manual runs to 28 pages. 311 * giant ball of hair. Its entry in the current Intel manual runs to 28 pages.
304 * 312 *
305 * This instruction even it has its own Wikipedia entry. The Wikipedia entry 313 * This instruction even it has its own Wikipedia entry. The Wikipedia entry
306 * has been translated into 4 languages. I am not making this up! 314 * has been translated into 4 languages. I am not making this up!
@@ -594,17 +602,17 @@ static unsigned long lguest_get_wallclock(void)
594 return lguest_data.time.tv_sec; 602 return lguest_data.time.tv_sec;
595} 603}
596 604
597/* The TSC is a Time Stamp Counter. The Host tells us what speed it runs at, 605/* The TSC is an Intel thing called the Time Stamp Counter. The Host tells us
598 * or 0 if it's unusable as a reliable clock source. This matches what we want 606 * what speed it runs at, or 0 if it's unusable as a reliable clock source.
599 * here: if we return 0 from this function, the x86 TSC clock will not register 607 * This matches what we want here: if we return 0 from this function, the x86
600 * itself. */ 608 * TSC clock will give up and not register itself. */
601static unsigned long lguest_cpu_khz(void) 609static unsigned long lguest_cpu_khz(void)
602{ 610{
603 return lguest_data.tsc_khz; 611 return lguest_data.tsc_khz;
604} 612}
605 613
606/* If we can't use the TSC, the kernel falls back to our "lguest_clock", where 614/* If we can't use the TSC, the kernel falls back to our lower-priority
607 * we read the time value given to us by the Host. */ 615 * "lguest_clock", where we read the time value given to us by the Host. */
608static cycle_t lguest_clock_read(void) 616static cycle_t lguest_clock_read(void)
609{ 617{
610 unsigned long sec, nsec; 618 unsigned long sec, nsec;
@@ -648,12 +656,16 @@ static struct clocksource lguest_clock = {
648static int lguest_clockevent_set_next_event(unsigned long delta, 656static int lguest_clockevent_set_next_event(unsigned long delta,
649 struct clock_event_device *evt) 657 struct clock_event_device *evt)
650{ 658{
659 /* FIXME: I don't think this can ever happen, but James tells me he had
660 * to put this code in. Maybe we should remove it now. Anyone? */
651 if (delta < LG_CLOCK_MIN_DELTA) { 661 if (delta < LG_CLOCK_MIN_DELTA) {
652 if (printk_ratelimit()) 662 if (printk_ratelimit())
653 printk(KERN_DEBUG "%s: small delta %lu ns\n", 663 printk(KERN_DEBUG "%s: small delta %lu ns\n",
654 __FUNCTION__, delta); 664 __FUNCTION__, delta);
655 return -ETIME; 665 return -ETIME;
656 } 666 }
667
668 /* Please wake us this far in the future. */
657 hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0); 669 hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0);
658 return 0; 670 return 0;
659} 671}
@@ -738,7 +750,7 @@ static void lguest_time_init(void)
738 * will not tolerate us trying to use that), the stack pointer, and the number 750 * will not tolerate us trying to use that), the stack pointer, and the number
739 * of pages in the stack. */ 751 * of pages in the stack. */
740static void lguest_load_sp0(struct tss_struct *tss, 752static void lguest_load_sp0(struct tss_struct *tss,
741 struct thread_struct *thread) 753 struct thread_struct *thread)
742{ 754{
743 lazy_hcall(LHCALL_SET_STACK, __KERNEL_DS|0x1, thread->sp0, 755 lazy_hcall(LHCALL_SET_STACK, __KERNEL_DS|0x1, thread->sp0,
744 THREAD_SIZE/PAGE_SIZE); 756 THREAD_SIZE/PAGE_SIZE);
@@ -786,9 +798,8 @@ static void lguest_safe_halt(void)
786 hcall(LHCALL_HALT, 0, 0, 0); 798 hcall(LHCALL_HALT, 0, 0, 0);
787} 799}
788 800
789/* Perhaps CRASH isn't the best name for this hypercall, but we use it to get a 801/* The SHUTDOWN hypercall takes a string to describe what's happening, and
790 * message out when we're crashing as well as elegant termination like powering 802 * an argument which says whether this to restart (reboot) the Guest or not.
791 * off.
792 * 803 *
793 * Note that the Host always prefers that the Guest speak in physical addresses 804 * Note that the Host always prefers that the Guest speak in physical addresses
794 * rather than virtual addresses, so we use __pa() here. */ 805 * rather than virtual addresses, so we use __pa() here. */
@@ -816,8 +827,9 @@ static struct notifier_block paniced = {
816/* Setting up memory is fairly easy. */ 827/* Setting up memory is fairly easy. */
817static __init char *lguest_memory_setup(void) 828static __init char *lguest_memory_setup(void)
818{ 829{
819 /* We do this here and not earlier because lockcheck barfs if we do it 830 /* We do this here and not earlier because lockcheck used to barf if we
820 * before start_kernel() */ 831 * did it before start_kernel(). I think we fixed that, so it'd be
832 * nice to move it back to lguest_init. Patch welcome... */
821 atomic_notifier_chain_register(&panic_notifier_list, &paniced); 833 atomic_notifier_chain_register(&panic_notifier_list, &paniced);
822 834
823 /* The Linux bootloader header contains an "e820" memory map: the 835 /* The Linux bootloader header contains an "e820" memory map: the
@@ -850,12 +862,19 @@ static __init int early_put_chars(u32 vtermno, const char *buf, int count)
850 return len; 862 return len;
851} 863}
852 864
865/* Rebooting also tells the Host we're finished, but the RESTART flag tells the
866 * Launcher to reboot us. */
867static void lguest_restart(char *reason)
868{
869 hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0);
870}
871
853/*G:050 872/*G:050
854 * Patching (Powerfully Placating Performance Pedants) 873 * Patching (Powerfully Placating Performance Pedants)
855 * 874 *
856 * We have already seen that pv_ops structures let us replace simple 875 * We have already seen that pv_ops structures let us replace simple native
857 * native instructions with calls to the appropriate back end all throughout 876 * instructions with calls to the appropriate back end all throughout the
858 * the kernel. This allows the same kernel to run as a Guest and as a native 877 * kernel. This allows the same kernel to run as a Guest and as a native
859 * kernel, but it's slow because of all the indirect branches. 878 * kernel, but it's slow because of all the indirect branches.
860 * 879 *
861 * Remember that David Wheeler quote about "Any problem in computer science can 880 * Remember that David Wheeler quote about "Any problem in computer science can
@@ -908,14 +927,9 @@ static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf,
908 return insn_len; 927 return insn_len;
909} 928}
910 929
911static void lguest_restart(char *reason) 930/*G:030 Once we get to lguest_init(), we know we're a Guest. The various
912{ 931 * pv_ops structures in the kernel provide points for (almost) every routine we
913 hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0); 932 * have to override to avoid privileged instructions. */
914}
915
916/*G:030 Once we get to lguest_init(), we know we're a Guest. The pv_ops
917 * structures in the kernel provide points for (almost) every routine we have
918 * to override to avoid privileged instructions. */
919__init void lguest_init(void) 933__init void lguest_init(void)
920{ 934{
921 /* We're under lguest, paravirt is enabled, and we're running at 935 /* We're under lguest, paravirt is enabled, and we're running at
@@ -1003,9 +1017,9 @@ __init void lguest_init(void)
1003 * the normal data segment to get through booting. */ 1017 * the normal data segment to get through booting. */
1004 asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory"); 1018 asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory");
1005 1019
1006 /* The Host uses the top of the Guest's virtual address space for the 1020 /* The Host<->Guest Switcher lives at the top of our address space, and
1007 * Host<->Guest Switcher, and it tells us how big that is in 1021 * the Host told us how big it is when we made LGUEST_INIT hypercall:
1008 * lguest_data.reserve_mem, set up on the LGUEST_INIT hypercall. */ 1022 * it put the answer in lguest_data.reserve_mem */
1009 reserve_top_address(lguest_data.reserve_mem); 1023 reserve_top_address(lguest_data.reserve_mem);
1010 1024
1011 /* If we don't initialize the lock dependency checker now, it crashes 1025 /* If we don't initialize the lock dependency checker now, it crashes
@@ -1027,6 +1041,7 @@ __init void lguest_init(void)
1027 /* Math is always hard! */ 1041 /* Math is always hard! */
1028 new_cpu_data.hard_math = 1; 1042 new_cpu_data.hard_math = 1;
1029 1043
1044 /* We don't have features. We have puppies! Puppies! */
1030#ifdef CONFIG_X86_MCE 1045#ifdef CONFIG_X86_MCE
1031 mce_disabled = 1; 1046 mce_disabled = 1;
1032#endif 1047#endif
@@ -1044,10 +1059,11 @@ __init void lguest_init(void)
1044 virtio_cons_early_init(early_put_chars); 1059 virtio_cons_early_init(early_put_chars);
1045 1060
1046 /* Last of all, we set the power management poweroff hook to point to 1061 /* Last of all, we set the power management poweroff hook to point to
1047 * the Guest routine to power off. */ 1062 * the Guest routine to power off, and the reboot hook to our restart
1063 * routine. */
1048 pm_power_off = lguest_power_off; 1064 pm_power_off = lguest_power_off;
1049
1050 machine_ops.restart = lguest_restart; 1065 machine_ops.restart = lguest_restart;
1066
1051 /* Now we're set up, call start_kernel() in init/main.c and we proceed 1067 /* Now we're set up, call start_kernel() in init/main.c and we proceed
1052 * to boot as normal. It never returns. */ 1068 * to boot as normal. It never returns. */
1053 start_kernel(); 1069 start_kernel();
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S
index 95b6fbcded6..5c7cef34c9e 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/i386_head.S
@@ -5,13 +5,20 @@
5#include <asm/thread_info.h> 5#include <asm/thread_info.h>
6#include <asm/processor-flags.h> 6#include <asm/processor-flags.h>
7 7
8/*G:020 This is where we begin: head.S notes that the boot header's platform 8/*G:020 Our story starts with the kernel booting into startup_32 in
9 * type field is "1" (lguest), so calls us here. 9 * arch/x86/kernel/head_32.S. It expects a boot header, which is created by
10 * the bootloader (the Launcher in our case).
11 *
12 * The startup_32 function does very little: it clears the uninitialized global
13 * C variables which we expect to be zero (ie. BSS) and then copies the boot
14 * header and kernel command line somewhere safe. Finally it checks the
15 * 'hardware_subarch' field. This was introduced in 2.6.24 for lguest and Xen:
16 * if it's set to '1' (lguest's assigned number), then it calls us here.
10 * 17 *
11 * WARNING: be very careful here! We're running at addresses equal to physical 18 * WARNING: be very careful here! We're running at addresses equal to physical
12 * addesses (around 0), not above PAGE_OFFSET as most code expectes 19 * addesses (around 0), not above PAGE_OFFSET as most code expectes
13 * (eg. 0xC0000000). Jumps are relative, so they're OK, but we can't touch any 20 * (eg. 0xC0000000). Jumps are relative, so they're OK, but we can't touch any
14 * data. 21 * data without remembering to subtract __PAGE_OFFSET!
15 * 22 *
16 * The .section line puts this code in .init.text so it will be discarded after 23 * The .section line puts this code in .init.text so it will be discarded after
17 * boot. */ 24 * boot. */
@@ -24,7 +31,7 @@ ENTRY(lguest_entry)
24 int $LGUEST_TRAP_ENTRY 31 int $LGUEST_TRAP_ENTRY
25 32
26 /* The Host put the toplevel pagetable in lguest_data.pgdir. The movsl 33 /* The Host put the toplevel pagetable in lguest_data.pgdir. The movsl
27 * instruction uses %esi implicitly as the source for the copy we' 34 * instruction uses %esi implicitly as the source for the copy we're
28 * about to do. */ 35 * about to do. */
29 movl lguest_data - __PAGE_OFFSET + LGUEST_DATA_pgdir, %esi 36 movl lguest_data - __PAGE_OFFSET + LGUEST_DATA_pgdir, %esi
30 37
diff --git a/arch/x86/mach-rdc321x/gpio.c b/arch/x86/mach-rdc321x/gpio.c
index 031269163bd..247f33d3a40 100644
--- a/arch/x86/mach-rdc321x/gpio.c
+++ b/arch/x86/mach-rdc321x/gpio.c
@@ -1,91 +1,194 @@
1/* 1/*
2 * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org> 2 * GPIO support for RDC SoC R3210/R8610
3 * RDC321x architecture specific GPIO support 3 *
4 * Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
4 * 20 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */ 21 */
10 22
11#include <linux/autoconf.h> 23
12#include <linux/init.h> 24#include <linux/spinlock.h>
13#include <linux/io.h> 25#include <linux/io.h>
14#include <linux/types.h> 26#include <linux/types.h>
15#include <linux/module.h> 27#include <linux/module.h>
16#include <linux/delay.h>
17 28
29#include <asm/gpio.h>
18#include <asm/mach-rdc321x/rdc321x_defs.h> 30#include <asm/mach-rdc321x/rdc321x_defs.h>
19 31
20static inline int rdc_gpio_is_valid(unsigned gpio) 32
33/* spin lock to protect our private copy of GPIO data register plus
34 the access to PCI conf registers. */
35static DEFINE_SPINLOCK(gpio_lock);
36
37/* copy of GPIO data registers */
38static u32 gpio_data_reg1;
39static u32 gpio_data_reg2;
40
41static u32 gpio_request_data[2];
42
43
44static inline void rdc321x_conf_write(unsigned addr, u32 value)
21{ 45{
22 return (gpio <= RDC_MAX_GPIO); 46 outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
47 outl(value, RDC3210_CFGREG_DATA);
23} 48}
24 49
25static unsigned int rdc_gpio_read(unsigned gpio) 50static inline void rdc321x_conf_or(unsigned addr, u32 value)
26{ 51{
27 unsigned int val; 52 outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
28 53 value |= inl(RDC3210_CFGREG_DATA);
29 val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x84:0x48)); 54 outl(value, RDC3210_CFGREG_DATA);
30 outl(val, RDC3210_CFGREG_ADDR);
31 udelay(10);
32 val = inl(RDC3210_CFGREG_DATA);
33 val |= (0x1 << (gpio & 0x1F));
34 outl(val, RDC3210_CFGREG_DATA);
35 udelay(10);
36 val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x88:0x4C));
37 outl(val, RDC3210_CFGREG_ADDR);
38 udelay(10);
39 val = inl(RDC3210_CFGREG_DATA);
40
41 return val;
42} 55}
43 56
44static void rdc_gpio_write(unsigned int val) 57static inline u32 rdc321x_conf_read(unsigned addr)
45{ 58{
46 if (val) { 59 outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
47 outl(val, RDC3210_CFGREG_DATA); 60
48 udelay(10); 61 return inl(RDC3210_CFGREG_DATA);
49 }
50} 62}
51 63
52int rdc_gpio_get_value(unsigned gpio) 64/* configure pin as GPIO */
65static void rdc321x_configure_gpio(unsigned gpio)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&gpio_lock, flags);
70 rdc321x_conf_or(gpio < 32
71 ? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2,
72 1 << (gpio & 0x1f));
73 spin_unlock_irqrestore(&gpio_lock, flags);
74}
75
76/* initially setup the 2 copies of the gpio data registers.
77 This function must be called by the platform setup code. */
78void __init rdc321x_gpio_setup()
79{
80 /* this might not be, what others (BIOS, bootloader, etc.)
81 wrote to these registers before, but it's a good guess. Still
82 better than just using 0xffffffff. */
83
84 gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
85 gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
86}
87
88/* determine, if gpio number is valid */
89static inline int rdc321x_is_gpio(unsigned gpio)
90{
91 return gpio <= RDC321X_MAX_GPIO;
92}
93
94/* request GPIO */
95int rdc_gpio_request(unsigned gpio, const char *label)
53{ 96{
54 if (rdc_gpio_is_valid(gpio)) 97 unsigned long flags;
55 return (int)rdc_gpio_read(gpio); 98
56 else 99 if (!rdc321x_is_gpio(gpio))
57 return -EINVAL; 100 return -EINVAL;
101
102 spin_lock_irqsave(&gpio_lock, flags);
103 if (gpio_request_data[(gpio & 0x20) ? 1 : 0] & (1 << (gpio & 0x1f)))
104 goto inuse;
105 gpio_request_data[(gpio & 0x20) ? 1 : 0] |= (1 << (gpio & 0x1f));
106 spin_unlock_irqrestore(&gpio_lock, flags);
107
108 return 0;
109inuse:
110 spin_unlock_irqrestore(&gpio_lock, flags);
111 return -EINVAL;
58} 112}
59EXPORT_SYMBOL(rdc_gpio_get_value); 113EXPORT_SYMBOL(rdc_gpio_request);
60 114
61void rdc_gpio_set_value(unsigned gpio, int value) 115/* release previously-claimed GPIO */
116void rdc_gpio_free(unsigned gpio)
62{ 117{
63 unsigned int val; 118 unsigned long flags;
64 119
65 if (!rdc_gpio_is_valid(gpio)) 120 if (!rdc321x_is_gpio(gpio))
66 return; 121 return;
67 122
68 val = rdc_gpio_read(gpio); 123 spin_lock_irqsave(&gpio_lock, flags);
124 gpio_request_data[(gpio & 0x20) ? 1 : 0] &= ~(1 << (gpio & 0x1f));
125 spin_unlock_irqrestore(&gpio_lock, flags);
126}
127EXPORT_SYMBOL(rdc_gpio_free);
128
129/* read GPIO pin */
130int rdc_gpio_get_value(unsigned gpio)
131{
132 u32 reg;
133 unsigned long flags;
134
135 spin_lock_irqsave(&gpio_lock, flags);
136 reg = rdc321x_conf_read(gpio < 32
137 ? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2);
138 spin_unlock_irqrestore(&gpio_lock, flags);
69 139
70 if (value) 140 return (1 << (gpio & 0x1f)) & reg ? 1 : 0;
71 val &= ~(0x1 << (gpio & 0x1F)); 141}
72 else 142EXPORT_SYMBOL(rdc_gpio_get_value);
73 val |= (0x1 << (gpio & 0x1F));
74 143
75 rdc_gpio_write(val); 144/* set GPIO pin to value */
145void rdc_gpio_set_value(unsigned gpio, int value)
146{
147 unsigned long flags;
148 u32 reg;
149
150 reg = 1 << (gpio & 0x1f);
151 if (gpio < 32) {
152 spin_lock_irqsave(&gpio_lock, flags);
153 if (value)
154 gpio_data_reg1 |= reg;
155 else
156 gpio_data_reg1 &= ~reg;
157 rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1);
158 spin_unlock_irqrestore(&gpio_lock, flags);
159 } else {
160 spin_lock_irqsave(&gpio_lock, flags);
161 if (value)
162 gpio_data_reg2 |= reg;
163 else
164 gpio_data_reg2 &= ~reg;
165 rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2);
166 spin_unlock_irqrestore(&gpio_lock, flags);
167 }
76} 168}
77EXPORT_SYMBOL(rdc_gpio_set_value); 169EXPORT_SYMBOL(rdc_gpio_set_value);
78 170
171/* configure GPIO pin as input */
79int rdc_gpio_direction_input(unsigned gpio) 172int rdc_gpio_direction_input(unsigned gpio)
80{ 173{
174 if (!rdc321x_is_gpio(gpio))
175 return -EINVAL;
176
177 rdc321x_configure_gpio(gpio);
178
81 return 0; 179 return 0;
82} 180}
83EXPORT_SYMBOL(rdc_gpio_direction_input); 181EXPORT_SYMBOL(rdc_gpio_direction_input);
84 182
183/* configure GPIO pin as output and set value */
85int rdc_gpio_direction_output(unsigned gpio, int value) 184int rdc_gpio_direction_output(unsigned gpio, int value)
86{ 185{
186 if (!rdc321x_is_gpio(gpio))
187 return -EINVAL;
188
189 gpio_set_value(gpio, value);
190 rdc321x_configure_gpio(gpio);
191
87 return 0; 192 return 0;
88} 193}
89EXPORT_SYMBOL(rdc_gpio_direction_output); 194EXPORT_SYMBOL(rdc_gpio_direction_output);
90
91
diff --git a/arch/x86/mach-rdc321x/platform.c b/arch/x86/mach-rdc321x/platform.c
index dda6024a586..a037041817c 100644
--- a/arch/x86/mach-rdc321x/platform.c
+++ b/arch/x86/mach-rdc321x/platform.c
@@ -62,6 +62,8 @@ static struct platform_device *rdc321x_devs[] = {
62 62
63static int __init rdc_board_setup(void) 63static int __init rdc_board_setup(void)
64{ 64{
65 rdc321x_gpio_setup();
66
65 return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs)); 67 return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs));
66} 68}
67 69
diff --git a/arch/x86/mm/discontig_32.c b/arch/x86/mm/discontig_32.c
index c394ca0720b..8e25e06ff73 100644
--- a/arch/x86/mm/discontig_32.c
+++ b/arch/x86/mm/discontig_32.c
@@ -324,7 +324,6 @@ unsigned long __init setup_memory(void)
324 * this space and use it to adjust the boundary between ZONE_NORMAL 324 * this space and use it to adjust the boundary between ZONE_NORMAL
325 * and ZONE_HIGHMEM. 325 * and ZONE_HIGHMEM.
326 */ 326 */
327 find_max_pfn();
328 get_memcfg_numa(); 327 get_memcfg_numa();
329 328
330 kva_pages = calculate_numa_remap_pages(); 329 kva_pages = calculate_numa_remap_pages();
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index fdc667422df..ec08d838985 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -91,12 +91,10 @@ static int is_prefetch(struct pt_regs *regs, unsigned long addr,
91 int prefetch = 0; 91 int prefetch = 0;
92 unsigned char *max_instr; 92 unsigned char *max_instr;
93 93
94#ifdef CONFIG_X86_32 94 /*
95 if (!(__supported_pte_mask & _PAGE_NX)) 95 * If it was a exec (instruction fetch) fault on NX page, then
96 return 0; 96 * do not ignore the fault:
97#endif 97 */
98
99 /* If it was a exec fault on NX page, ignore */
100 if (error_code & PF_INSTR) 98 if (error_code & PF_INSTR)
101 return 0; 99 return 0;
102 100
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 3d936f23270..9cf33d3ee5b 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -73,15 +73,15 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
73{ 73{
74 enum fixed_addresses idx; 74 enum fixed_addresses idx;
75 unsigned long vaddr; 75 unsigned long vaddr;
76 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
77
78 debug_kmap_atomic_prot(type);
79 76
77 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
80 pagefault_disable(); 78 pagefault_disable();
81 79
82 if (!PageHighMem(page)) 80 if (!PageHighMem(page))
83 return page_address(page); 81 return page_address(page);
84 82
83 debug_kmap_atomic_prot(type);
84
85 idx = type + KM_TYPE_NR*smp_processor_id(); 85 idx = type + KM_TYPE_NR*smp_processor_id();
86 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 86 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
87 BUG_ON(!pte_none(*(kmap_pte-idx))); 87 BUG_ON(!pte_none(*(kmap_pte-idx)));
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index 4fbafb4bc2f..0b3d567e686 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -178,7 +178,7 @@ follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
178 178
179 page = &pte_page(*pte)[vpfn % (HPAGE_SIZE/PAGE_SIZE)]; 179 page = &pte_page(*pte)[vpfn % (HPAGE_SIZE/PAGE_SIZE)];
180 180
181 WARN_ON(!PageCompound(page)); 181 WARN_ON(!PageHead(page));
182 182
183 return page; 183 return page;
184} 184}
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 4afaba0ed72..794895c6dcc 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -137,7 +137,11 @@ static void __iomem *__ioremap(resource_size_t phys_addr, unsigned long size,
137 switch (mode) { 137 switch (mode) {
138 case IOR_MODE_UNCACHED: 138 case IOR_MODE_UNCACHED:
139 default: 139 default:
140 prot = PAGE_KERNEL_NOCACHE; 140 /*
141 * FIXME: we will use UC MINUS for now, as video fb drivers
142 * depend on it. Upcoming ioremap_wc() will fix this behavior.
143 */
144 prot = PAGE_KERNEL_UC_MINUS;
141 break; 145 break;
142 case IOR_MODE_CACHED: 146 case IOR_MODE_CACHED:
143 prot = PAGE_KERNEL; 147 prot = PAGE_KERNEL;
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 14e48b5a94b..7b79f6be4e7 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -771,7 +771,7 @@ static inline int change_page_attr_clear(unsigned long addr, int numpages,
771int set_memory_uc(unsigned long addr, int numpages) 771int set_memory_uc(unsigned long addr, int numpages)
772{ 772{
773 return change_page_attr_set(addr, numpages, 773 return change_page_attr_set(addr, numpages,
774 __pgprot(_PAGE_PCD | _PAGE_PWT)); 774 __pgprot(_PAGE_PCD));
775} 775}
776EXPORT_SYMBOL(set_memory_uc); 776EXPORT_SYMBOL(set_memory_uc);
777 777
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 8b9ee27805f..27ee26aedf9 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -95,7 +95,7 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&dummy_shared_info;
95 * 95 *
96 * 0: not available, 1: available 96 * 0: not available, 1: available
97 */ 97 */
98static int have_vcpu_info_placement = 0; 98static int have_vcpu_info_placement = 1;
99 99
100static void __init xen_vcpu_setup(int cpu) 100static void __init xen_vcpu_setup(int cpu)
101{ 101{
@@ -103,6 +103,7 @@ static void __init xen_vcpu_setup(int cpu)
103 int err; 103 int err;
104 struct vcpu_info *vcpup; 104 struct vcpu_info *vcpup;
105 105
106 BUG_ON(HYPERVISOR_shared_info == &dummy_shared_info);
106 per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; 107 per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
107 108
108 if (!have_vcpu_info_placement) 109 if (!have_vcpu_info_placement)
@@ -666,10 +667,10 @@ static void xen_release_pt_init(u32 pfn)
666 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn))); 667 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
667} 668}
668 669
669static void pin_pagetable_pfn(unsigned level, unsigned long pfn) 670static void pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
670{ 671{
671 struct mmuext_op op; 672 struct mmuext_op op;
672 op.cmd = level; 673 op.cmd = cmd;
673 op.arg1.mfn = pfn_to_mfn(pfn); 674 op.arg1.mfn = pfn_to_mfn(pfn);
674 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF)) 675 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF))
675 BUG(); 676 BUG();
@@ -686,7 +687,8 @@ static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
686 687
687 if (!PageHighMem(page)) { 688 if (!PageHighMem(page)) {
688 make_lowmem_page_readonly(__va(PFN_PHYS(pfn))); 689 make_lowmem_page_readonly(__va(PFN_PHYS(pfn)));
689 pin_pagetable_pfn(level, pfn); 690 if (level == PT_PTE)
691 pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
690 } else 692 } else
691 /* make sure there are no stray mappings of 693 /* make sure there are no stray mappings of
692 this page */ 694 this page */
@@ -696,27 +698,39 @@ static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
696 698
697static void xen_alloc_pt(struct mm_struct *mm, u32 pfn) 699static void xen_alloc_pt(struct mm_struct *mm, u32 pfn)
698{ 700{
699 xen_alloc_ptpage(mm, pfn, MMUEXT_PIN_L1_TABLE); 701 xen_alloc_ptpage(mm, pfn, PT_PTE);
700} 702}
701 703
702static void xen_alloc_pd(struct mm_struct *mm, u32 pfn) 704static void xen_alloc_pd(struct mm_struct *mm, u32 pfn)
703{ 705{
704 xen_alloc_ptpage(mm, pfn, MMUEXT_PIN_L2_TABLE); 706 xen_alloc_ptpage(mm, pfn, PT_PMD);
705} 707}
706 708
707/* This should never happen until we're OK to use struct page */ 709/* This should never happen until we're OK to use struct page */
708static void xen_release_pt(u32 pfn) 710static void xen_release_ptpage(u32 pfn, unsigned level)
709{ 711{
710 struct page *page = pfn_to_page(pfn); 712 struct page *page = pfn_to_page(pfn);
711 713
712 if (PagePinned(page)) { 714 if (PagePinned(page)) {
713 if (!PageHighMem(page)) { 715 if (!PageHighMem(page)) {
714 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn); 716 if (level == PT_PTE)
717 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
715 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn))); 718 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
716 } 719 }
720 ClearPagePinned(page);
717 } 721 }
718} 722}
719 723
724static void xen_release_pt(u32 pfn)
725{
726 xen_release_ptpage(pfn, PT_PTE);
727}
728
729static void xen_release_pd(u32 pfn)
730{
731 xen_release_ptpage(pfn, PT_PMD);
732}
733
720#ifdef CONFIG_HIGHPTE 734#ifdef CONFIG_HIGHPTE
721static void *xen_kmap_atomic_pte(struct page *page, enum km_type type) 735static void *xen_kmap_atomic_pte(struct page *page, enum km_type type)
722{ 736{
@@ -805,33 +819,43 @@ static __init void xen_pagetable_setup_start(pgd_t *base)
805 PFN_DOWN(__pa(xen_start_info->pt_base))); 819 PFN_DOWN(__pa(xen_start_info->pt_base)));
806} 820}
807 821
808static __init void xen_pagetable_setup_done(pgd_t *base) 822static __init void setup_shared_info(void)
809{ 823{
810 /* This will work as long as patching hasn't happened yet
811 (which it hasn't) */
812 pv_mmu_ops.alloc_pt = xen_alloc_pt;
813 pv_mmu_ops.alloc_pd = xen_alloc_pd;
814 pv_mmu_ops.release_pt = xen_release_pt;
815 pv_mmu_ops.release_pd = xen_release_pt;
816 pv_mmu_ops.set_pte = xen_set_pte;
817
818 if (!xen_feature(XENFEAT_auto_translated_physmap)) { 824 if (!xen_feature(XENFEAT_auto_translated_physmap)) {
825 unsigned long addr = fix_to_virt(FIX_PARAVIRT_BOOTMAP);
826
819 /* 827 /*
820 * Create a mapping for the shared info page. 828 * Create a mapping for the shared info page.
821 * Should be set_fixmap(), but shared_info is a machine 829 * Should be set_fixmap(), but shared_info is a machine
822 * address with no corresponding pseudo-phys address. 830 * address with no corresponding pseudo-phys address.
823 */ 831 */
824 set_pte_mfn(fix_to_virt(FIX_PARAVIRT_BOOTMAP), 832 set_pte_mfn(addr,
825 PFN_DOWN(xen_start_info->shared_info), 833 PFN_DOWN(xen_start_info->shared_info),
826 PAGE_KERNEL); 834 PAGE_KERNEL);
827 835
828 HYPERVISOR_shared_info = 836 HYPERVISOR_shared_info = (struct shared_info *)addr;
829 (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
830
831 } else 837 } else
832 HYPERVISOR_shared_info = 838 HYPERVISOR_shared_info =
833 (struct shared_info *)__va(xen_start_info->shared_info); 839 (struct shared_info *)__va(xen_start_info->shared_info);
834 840
841#ifndef CONFIG_SMP
842 /* In UP this is as good a place as any to set up shared info */
843 xen_setup_vcpu_info_placement();
844#endif
845}
846
847static __init void xen_pagetable_setup_done(pgd_t *base)
848{
849 /* This will work as long as patching hasn't happened yet
850 (which it hasn't) */
851 pv_mmu_ops.alloc_pt = xen_alloc_pt;
852 pv_mmu_ops.alloc_pd = xen_alloc_pd;
853 pv_mmu_ops.release_pt = xen_release_pt;
854 pv_mmu_ops.release_pd = xen_release_pd;
855 pv_mmu_ops.set_pte = xen_set_pte;
856
857 setup_shared_info();
858
835 /* Actually pin the pagetable down, but we can't set PG_pinned 859 /* Actually pin the pagetable down, but we can't set PG_pinned
836 yet because the page structures don't exist yet. */ 860 yet because the page structures don't exist yet. */
837 { 861 {
@@ -1182,15 +1206,9 @@ asmlinkage void __init xen_start_kernel(void)
1182 x86_write_percpu(xen_cr3, __pa(pgd)); 1206 x86_write_percpu(xen_cr3, __pa(pgd));
1183 x86_write_percpu(xen_current_cr3, __pa(pgd)); 1207 x86_write_percpu(xen_current_cr3, __pa(pgd));
1184 1208
1185#ifdef CONFIG_SMP
1186 /* Don't do the full vcpu_info placement stuff until we have a 1209 /* Don't do the full vcpu_info placement stuff until we have a
1187 possible map. */ 1210 possible map and a non-dummy shared_info. */
1188 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; 1211 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
1189#else
1190 /* May as well do it now, since there's no good time to call
1191 it later on UP. */
1192 xen_setup_vcpu_info_placement();
1193#endif
1194 1212
1195 pv_info.kernel_rpl = 1; 1213 pv_info.kernel_rpl = 1;
1196 if (xen_feature(XENFEAT_supervisor_mode_kernel)) 1214 if (xen_feature(XENFEAT_supervisor_mode_kernel))
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 0144395448a..2a054ef2a3d 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -310,13 +310,6 @@ pgd_t xen_make_pgd(unsigned long pgd)
310} 310}
311#endif /* CONFIG_X86_PAE */ 311#endif /* CONFIG_X86_PAE */
312 312
313enum pt_level {
314 PT_PGD,
315 PT_PUD,
316 PT_PMD,
317 PT_PTE
318};
319
320/* 313/*
321 (Yet another) pagetable walker. This one is intended for pinning a 314 (Yet another) pagetable walker. This one is intended for pinning a
322 pagetable. This means that it walks a pagetable and calls the 315 pagetable. This means that it walks a pagetable and calls the
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index c9ff27f3ac3..b5e189b1519 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -3,6 +3,13 @@
3#include <linux/linkage.h> 3#include <linux/linkage.h>
4#include <asm/page.h> 4#include <asm/page.h>
5 5
6enum pt_level {
7 PT_PGD,
8 PT_PUD,
9 PT_PMD,
10 PT_PTE
11};
12
6/* 13/*
7 * Page-directory addresses above 4GB do not fit into architectural %cr3. 14 * Page-directory addresses above 4GB do not fit into architectural %cr3.
8 * When accessing %cr3, or equivalent field in vcpu_guest_context, guests 15 * When accessing %cr3, or equivalent field in vcpu_guest_context, guests
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 1a43b60c0c6..6b7190449d0 100644
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -33,12 +33,17 @@
33 events, then enter the hypervisor to get them handled. 33 events, then enter the hypervisor to get them handled.
34 */ 34 */
35ENTRY(xen_irq_enable_direct) 35ENTRY(xen_irq_enable_direct)
36 /* Clear mask and test pending */ 36 /* Unmask events */
37 andw $0x00ff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending 37 movb $0, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
38
38 /* Preempt here doesn't matter because that will deal with 39 /* Preempt here doesn't matter because that will deal with
39 any pending interrupts. The pending check may end up being 40 any pending interrupts. The pending check may end up being
40 run on the wrong CPU, but that doesn't hurt. */ 41 run on the wrong CPU, but that doesn't hurt. */
42
43 /* Test for pending */
44 testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
41 jz 1f 45 jz 1f
46
422: call check_events 472: call check_events
431: 481:
44ENDPATCH(xen_irq_enable_direct) 49ENDPATCH(xen_irq_enable_direct)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 11:23:03 -0400