diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 08:45:41 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 09:56:34 -0500 |
commit | 9cf945cbef42a4524b6a58486bd8bfb96640e97f (patch) | |
tree | 777e8ead1904e7158901493b0c22314c2550dbfb /arch | |
parent | 84ab80616b0eb5fac4d1970f10ea1b3cf75280e1 (diff) |
i.MX27: Add USB control register access support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-mxc/ehci.c | 47 |
1 files changed, 46 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 586b55dc2ab..816a9cc60e5 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c | |||
@@ -41,7 +41,7 @@ | |||
41 | int mxc_set_usbcontrol(int port, unsigned int flags) | 41 | int mxc_set_usbcontrol(int port, unsigned int flags) |
42 | { | 42 | { |
43 | unsigned int v; | 43 | unsigned int v; |
44 | 44 | #ifdef CONFIG_ARCH_MX3 | |
45 | if (cpu_is_mx31()) { | 45 | if (cpu_is_mx31()) { |
46 | v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + | 46 | v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + |
47 | USBCTRL_OTGBASE_OFFSET)); | 47 | USBCTRL_OTGBASE_OFFSET)); |
@@ -85,7 +85,52 @@ int mxc_set_usbcontrol(int port, unsigned int flags) | |||
85 | USBCTRL_OTGBASE_OFFSET)); | 85 | USBCTRL_OTGBASE_OFFSET)); |
86 | return 0; | 86 | return 0; |
87 | } | 87 | } |
88 | #endif /* CONFIG_ARCH_MX3 */ | ||
89 | #ifdef CONFIG_MACH_MX27 | ||
90 | if (cpu_is_mx27()) { | ||
91 | /* On i.MX27 we can use the i.MX31 USBCTRL bits, they | ||
92 | * are identical | ||
93 | */ | ||
94 | v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + | ||
95 | USBCTRL_OTGBASE_OFFSET)); | ||
96 | switch (port) { | ||
97 | case 0: /* OTG port */ | ||
98 | v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); | ||
99 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | ||
100 | << MX31_OTG_SIC_SHIFT; | ||
101 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | ||
102 | v |= MX31_OTG_PM_BIT; | ||
103 | break; | ||
104 | case 1: /* H1 port */ | ||
105 | v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); | ||
106 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | ||
107 | << MX31_H1_SIC_SHIFT; | ||
108 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | ||
109 | v |= MX31_H1_PM_BIT; | ||
110 | |||
111 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | ||
112 | v |= MX31_H1_DT_BIT; | ||
88 | 113 | ||
114 | break; | ||
115 | case 2: /* H2 port */ | ||
116 | v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); | ||
117 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | ||
118 | << MX31_H2_SIC_SHIFT; | ||
119 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | ||
120 | v |= MX31_H2_PM_BIT; | ||
121 | |||
122 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | ||
123 | v |= MX31_H2_DT_BIT; | ||
124 | |||
125 | break; | ||
126 | default: | ||
127 | return -EINVAL; | ||
128 | } | ||
129 | writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + | ||
130 | USBCTRL_OTGBASE_OFFSET)); | ||
131 | return 0; | ||
132 | } | ||
133 | #endif /* CONFIG_MACH_MX27 */ | ||
89 | printk(KERN_WARNING | 134 | printk(KERN_WARNING |
90 | "%s() unable to setup USBCONTROL for this CPU\n", __func__); | 135 | "%s() unable to setup USBCONTROL for this CPU\n", __func__); |
91 | return -EINVAL; | 136 | return -EINVAL; |