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authorKumar Gala <galak@kernel.crashing.org>2011-11-04 01:48:57 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:38 -0500
commit941d71c7361815c02e2b2831bbb9f06a504a3d24 (patch)
tree973976fa32a26369b7fcb59f5aa89a5a29875bc6 /arch
parent7f9ce7143efe1231d66a5c91e57fce55fce6728e (diff)
powerpc/85xx: Rework P2020RDB device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & * etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts63
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts141
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts107
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi355
4 files changed, 22 insertions, 644 deletions
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f3021..fd4271296f8 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,7 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020RDB"; 15 model = "fsl,P2020RDB";
@@ -29,7 +29,8 @@
29 device_type = "memory"; 29 device_type = "memory";
30 }; 30 };
31 31
32 localbus@ffe05000 { 32 lbc: localbus@ffe05000 {
33 reg = <0 0xffe05000 0 0x1000>;
33 34
34 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -140,7 +141,9 @@
140 141
141 }; 142 };
142 143
143 soc@ffe00000 { 144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0x100000>;
146
144 i2c@3000 { 147 i2c@3000 {
145 rtc@68 { 148 rtc@68 {
146 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
@@ -148,17 +151,13 @@
148 }; 151 };
149 }; 152 };
150 153
151 spi@7000 { 154 spi@7000 {
152 155 flash@0 {
153 fsl_m25p80@0 {
154 #address-cells = <1>; 156 #address-cells = <1>;
155 #size-cells = <1>; 157 #size-cells = <1>;
156 compatible = "fsl,espi-flash"; 158 compatible = "spansion,s25sl12801";
157 reg = <0>; 159 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>; 160 spi-max-frequency = <50000000>;
161 mode = <0>;
162 161
163 partition@0 { 162 partition@0 {
164 /* 512KB for u-boot Bootloader Image */ 163 /* 512KB for u-boot Bootloader Image */
@@ -202,13 +201,11 @@
202 201
203 mdio@24520 { 202 mdio@24520 {
204 phy0: ethernet-phy@0 { 203 phy0: ethernet-phy@0 {
205 interrupt-parent = <&mpic>; 204 interrupts = <3 1 0 0>;
206 interrupts = <3 1>;
207 reg = <0x0>; 205 reg = <0x0>;
208 }; 206 };
209 phy1: ethernet-phy@1 { 207 phy1: ethernet-phy@1 {
210 interrupt-parent = <&mpic>; 208 interrupts = <3 1 0 0>;
211 interrupts = <3 1>;
212 reg = <0x1>; 209 reg = <0x1>;
213 }; 210 };
214 }; 211 };
@@ -224,11 +221,7 @@
224 status = "disabled"; 221 status = "disabled";
225 }; 222 };
226 223
227 ptp_clock@24E00 { 224 ptp_clock@24e00 {
228 compatible = "fsl,etsec-ptp";
229 reg = <0x24E00 0xB0>;
230 interrupts = <68 2 69 2 70 2>;
231 interrupt-parent = < &mpic >;
232 fsl,tclk-period = <5>; 225 fsl,tclk-period = <5>;
233 fsl,tmr-prsc = <200>; 226 fsl,tmr-prsc = <200>;
234 fsl,tmr-add = <0xCCCCCCCD>; 227 fsl,tmr-add = <0xCCCCCCCD>;
@@ -252,29 +245,18 @@
252 phy-handle = <&phy1>; 245 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id"; 246 phy-connection-type = "rgmii-id";
254 }; 247 };
255
256 }; 248 };
257 249
258 pci0: pcie@ffe08000 { 250 pci0: pcie@ffe08000 {
251 reg = <0 0xffe08000 0 0x1000>;
259 status = "disabled"; 252 status = "disabled";
260 }; 253 };
261 254
262 pci1: pcie@ffe09000 { 255 pci1: pcie@ffe09000 {
256 reg = <0 0xffe09000 0 0x1000>;
263 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 257 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
264 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 258 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
265 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 259 pcie@0 {
266 interrupt-map = <
267 /* IDSEL 0x0 */
268 0000 0x0 0x0 0x1 &mpic 0x4 0x1
269 0000 0x0 0x0 0x2 &mpic 0x5 0x1
270 0000 0x0 0x0 0x3 &mpic 0x6 0x1
271 0000 0x0 0x0 0x4 &mpic 0x7 0x1
272 >;
273 pcie@0 {
274 reg = <0x0 0x0 0x0 0x0 0x0>;
275 #size-cells = <2>;
276 #address-cells = <3>;
277 device_type = "pci";
278 ranges = <0x2000000 0x0 0xa0000000 260 ranges = <0x2000000 0x0 0xa0000000
279 0x2000000 0x0 0xa0000000 261 0x2000000 0x0 0xa0000000
280 0x0 0x20000000 262 0x0 0x20000000
@@ -286,21 +268,10 @@
286 }; 268 };
287 269
288 pci2: pcie@ffe0a000 { 270 pci2: pcie@ffe0a000 {
271 reg = <0 0xffe0a000 0 0x1000>;
289 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 272 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
290 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 273 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = <
293 /* IDSEL 0x0 */
294 0000 0x0 0x0 0x1 &mpic 0x0 0x1
295 0000 0x0 0x0 0x2 &mpic 0x1 0x1
296 0000 0x0 0x0 0x3 &mpic 0x2 0x1
297 0000 0x0 0x0 0x4 &mpic 0x3 0x1
298 >;
299 pcie@0 { 274 pcie@0 {
300 reg = <0x0 0x0 0x0 0x0 0x0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x2000000 0x0 0x80000000 275 ranges = <0x2000000 0x0 0x80000000
305 0x2000000 0x0 0x80000000 276 0x2000000 0x0 0x80000000
306 0x0 0x20000000 277 0x0 0x20000000
@@ -311,3 +282,5 @@
311 }; 282 };
312 }; 283 };
313}; 284};
285
286/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8ddddfccb..66aac864c4c 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,28 +14,16 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/include/ "p2020si.dtsi" 17/include/ "p2020rdb.dts"
18 18
19/ { 19/ {
20 model = "fsl,P2020RDB"; 20 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 22
23 aliases {
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 serial0 = &serial0;
27 pci0 = &pci0;
28 };
29
30 cpus { 23 cpus {
31 PowerPC,P2020@1 { 24 PowerPC,P2020@1 {
32 status = "disabled"; 25 status = "disabled";
33 }; 26 };
34
35 };
36
37 memory {
38 device_type = "memory";
39 }; 27 };
40 28
41 localbus@ffe05000 { 29 localbus@ffe05000 {
@@ -43,115 +31,18 @@
43 }; 31 };
44 32
45 soc@ffe00000 { 33 soc@ffe00000 {
46 i2c@3000 {
47 rtc@68 {
48 compatible = "dallas,ds1339";
49 reg = <0x68>;
50 };
51 };
52
53 serial1: serial@4600 { 34 serial1: serial@4600 {
54 status = "disabled"; 35 status = "disabled";
55 }; 36 };
56 37
57 spi@7000 {
58
59 fsl_m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "fsl,espi-flash";
63 reg = <0>;
64 linux,modalias = "fsl_m25p80";
65 modal = "s25sl128b";
66 spi-max-frequency = <50000000>;
67 mode = <0>;
68
69 partition@0 {
70 /* 512KB for u-boot Bootloader Image */
71 reg = <0x0 0x00080000>;
72 label = "SPI (RO) U-Boot Image";
73 read-only;
74 };
75
76 partition@80000 {
77 /* 512KB for DTB Image */
78 reg = <0x00080000 0x00080000>;
79 label = "SPI (RO) DTB Image";
80 read-only;
81 };
82
83 partition@100000 {
84 /* 4MB for Linux Kernel Image */
85 reg = <0x00100000 0x00400000>;
86 label = "SPI (RO) Linux Kernel Image";
87 read-only;
88 };
89
90 partition@500000 {
91 /* 4MB for Compressed RFS Image */
92 reg = <0x00500000 0x00400000>;
93 label = "SPI (RO) Compressed RFS Image";
94 read-only;
95 };
96
97 partition@900000 {
98 /* 7MB for JFFS2 based RFS */
99 reg = <0x00900000 0x00700000>;
100 label = "SPI (RW) JFFS2 RFS";
101 };
102 };
103 };
104
105 dma@c300 { 38 dma@c300 {
106 status = "disabled"; 39 status = "disabled";
107 }; 40 };
108 41
109 usb@22000 {
110 phy_type = "ulpi";
111 };
112
113 mdio@24520 {
114
115 phy0: ethernet-phy@0 {
116 interrupt-parent = <&mpic>;
117 interrupts = <3 1>;
118 reg = <0x0>;
119 };
120 phy1: ethernet-phy@1 {
121 interrupt-parent = <&mpic>;
122 interrupts = <3 1>;
123 reg = <0x1>;
124 };
125 };
126
127 mdio@25520 {
128 tbi0: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 { 42 enet0: ethernet@24000 {
139 status = "disabled"; 43 status = "disabled";
140 }; 44 };
141 45
142 enet1: ethernet@25000 {
143 tbi-handle = <&tbi0>;
144 phy-handle = <&phy0>;
145 phy-connection-type = "sgmii";
146
147 };
148
149 enet2: ethernet@26000 {
150 phy-handle = <&phy1>;
151 phy-connection-type = "rgmii-id";
152 };
153
154
155 mpic: pic@40000 { 46 mpic: pic@40000 {
156 protected-sources = < 47 protected-sources = <
157 42 76 77 78 79 /* serial1 , dma2 */ 48 42 76 77 78 79 /* serial1 , dma2 */
@@ -164,40 +55,12 @@
164 msi@41600 { 55 msi@41600 {
165 status = "disabled"; 56 status = "disabled";
166 }; 57 };
167
168
169 }; 58 };
170 59
171 pci0: pcie@ffe08000 { 60 pci0: pcie@ffe08000 {
172 status = "disabled"; 61 status = "disabled";
173 }; 62 };
174 63
175 pci1: pcie@ffe09000 {
176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
179 interrupt-map = <
180 /* IDSEL 0x0 */
181 0000 0x0 0x0 0x1 &mpic 0x4 0x1
182 0000 0x0 0x0 0x2 &mpic 0x5 0x1
183 0000 0x0 0x0 0x3 &mpic 0x6 0x1
184 0000 0x0 0x0 0x4 &mpic 0x7 0x1
185 >;
186 pcie@0 {
187 reg = <0x0 0x0 0x0 0x0 0x0>;
188 #size-cells = <2>;
189 #address-cells = <3>;
190 device_type = "pci";
191 ranges = <0x2000000 0x0 0xa0000000
192 0x2000000 0x0 0xa0000000
193 0x0 0x20000000
194
195 0x1000000 0x0 0x0
196 0x1000000 0x0 0x0
197 0x0 0x100000>;
198 };
199 };
200
201 pci2: pcie@ffe0a000 { 64 pci2: pcie@ffe0a000 {
202 status = "disabled"; 65 status = "disabled";
203 }; 66 };
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 261c34ba45e..9bd8ef493dd 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,28 +15,18 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/include/ "p2020si.dtsi" 18/include/ "p2020rdb.dts"
19 19
20/ { 20/ {
21 model = "fsl,P2020RDB"; 21 model = "fsl,P2020RDB";
22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
23 23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 pci1 = &pci1;
28 };
29
30 cpus { 24 cpus {
31 PowerPC,P2020@0 { 25 PowerPC,P2020@0 {
32 status = "disabled"; 26 status = "disabled";
33 }; 27 };
34 }; 28 };
35 29
36 memory {
37 device_type = "memory";
38 };
39
40 localbus@ffe05000 { 30 localbus@ffe05000 {
41 status = "disabled"; 31 status = "disabled";
42 }; 32 };
@@ -70,55 +60,10 @@
70 status = "disabled"; 60 status = "disabled";
71 }; 61 };
72 62
73 dma@c300 {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 compatible = "fsl,eloplus-dma";
77 reg = <0xc300 0x4>;
78 ranges = <0x0 0xc100 0x200>;
79 cell-index = <1>;
80 dma-channel@0 {
81 compatible = "fsl,eloplus-dma-channel";
82 reg = <0x0 0x80>;
83 cell-index = <0>;
84 interrupt-parent = <&mpic>;
85 interrupts = <76 2>;
86 };
87 dma-channel@80 {
88 compatible = "fsl,eloplus-dma-channel";
89 reg = <0x80 0x80>;
90 cell-index = <1>;
91 interrupt-parent = <&mpic>;
92 interrupts = <77 2>;
93 };
94 dma-channel@100 {
95 compatible = "fsl,eloplus-dma-channel";
96 reg = <0x100 0x80>;
97 cell-index = <2>;
98 interrupt-parent = <&mpic>;
99 interrupts = <78 2>;
100 };
101 dma-channel@180 {
102 compatible = "fsl,eloplus-dma-channel";
103 reg = <0x180 0x80>;
104 cell-index = <3>;
105 interrupt-parent = <&mpic>;
106 interrupts = <79 2>;
107 };
108 };
109
110 gpio: gpio-controller@f000 { 63 gpio: gpio-controller@f000 {
111 status = "disabled"; 64 status = "disabled";
112 }; 65 };
113 66
114 L2: l2-cache-controller@20000 {
115 compatible = "fsl,p2020-l2-cache-controller";
116 reg = <0x20000 0x1000>;
117 cache-line-size = <32>; // 32 bytes
118 cache-size = <0x80000>; // L2,512K
119 interrupt-parent = <&mpic>;
120 };
121
122 dma@21300 { 67 dma@21300 {
123 status = "disabled"; 68 status = "disabled";
124 }; 69 };
@@ -139,12 +84,6 @@
139 status = "disabled"; 84 status = "disabled";
140 }; 85 };
141 86
142 enet0: ethernet@24000 {
143 fixed-link = <1 1 1000 0 0>;
144 phy-connection-type = "rgmii-id";
145
146 };
147
148 enet1: ethernet@25000 { 87 enet1: ethernet@25000 {
149 status = "disabled"; 88 status = "disabled";
150 }; 89 };
@@ -170,22 +109,6 @@
170 >; 109 >;
171 }; 110 };
172 111
173 msi@41600 {
174 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
175 reg = <0x41600 0x80>;
176 msi-available-ranges = <0 0x100>;
177 interrupts = <
178 0xe0 0
179 0xe1 0
180 0xe2 0
181 0xe3 0
182 0xe4 0
183 0xe5 0
184 0xe6 0
185 0xe7 0>;
186 interrupt-parent = <&mpic>;
187 };
188
189 global-utilities@e0000 { //global utilities block 112 global-utilities@e0000 { //global utilities block
190 status = "disabled"; 113 status = "disabled";
191 }; 114 };
@@ -199,30 +122,4 @@
199 pci1: pcie@ffe09000 { 122 pci1: pcie@ffe09000 {
200 status = "disabled"; 123 status = "disabled";
201 }; 124 };
202
203 pci2: pcie@ffe0a000 {
204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
206 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
207 interrupt-map = <
208 /* IDSEL 0x0 */
209 0000 0x0 0x0 0x1 &mpic 0x0 0x1
210 0000 0x0 0x0 0x2 &mpic 0x1 0x1
211 0000 0x0 0x0 0x3 &mpic 0x2 0x1
212 0000 0x0 0x0 0x4 &mpic 0x3 0x1
213 >;
214 pcie@0 {
215 reg = <0x0 0x0 0x0 0x0 0x0>;
216 #size-cells = <2>;
217 #address-cells = <3>;
218 device_type = "pci";
219 ranges = <0x2000000 0x0 0x80000000
220 0x2000000 0x0 0x80000000
221 0x0 0x20000000
222
223 0x1000000 0x0 0x0
224 0x1000000 0x0 0x0
225 0x0 0x100000>;
226 };
227 };
228}; 125};
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
deleted file mode 100644
index 37f7194186c..00000000000
--- a/arch/powerpc/boot/dts/p2020si.dtsi
+++ /dev/null
@@ -1,355 +0,0 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,P2020@0 {
24 device_type = "cpu";
25 reg = <0x0>;
26 next-level-cache = <&L2>;
27 };
28
29 PowerPC,P2020@1 {
30 device_type = "cpu";
31 reg = <0x1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 localbus@ffe05000 {
37 #address-cells = <2>;
38 #size-cells = <1>;
39 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
40 reg = <0 0xffe05000 0 0x1000>;
41 interrupts = <19 2 0 0>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2 0 0>;
62 };
63
64 memory-controller@2000 {
65 compatible = "fsl,p2020-memory-controller";
66 reg = <0x2000 0x1000>;
67 interrupts = <18 2 0 0>;
68 };
69
70 i2c@3000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 cell-index = <0>;
74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>;
76 interrupts = <43 2 0 0>;
77 dfsrr;
78 };
79
80 i2c@3100 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 cell-index = <1>;
84 compatible = "fsl-i2c";
85 reg = <0x3100 0x100>;
86 interrupts = <43 2 0 0>;
87 dfsrr;
88 };
89
90 serial0: serial@4500 {
91 cell-index = <0>;
92 device_type = "serial";
93 compatible = "ns16550";
94 reg = <0x4500 0x100>;
95 clock-frequency = <0>;
96 interrupts = <42 2 0 0>;
97 };
98
99 serial1: serial@4600 {
100 cell-index = <1>;
101 device_type = "serial";
102 compatible = "ns16550";
103 reg = <0x4600 0x100>;
104 clock-frequency = <0>;
105 interrupts = <42 2 0 0>;
106 };
107
108 spi@7000 {
109 cell-index = <0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,espi";
113 reg = <0x7000 0x1000>;
114 interrupts = <59 0x2 0 0>;
115 mode = "cpu";
116 };
117
118 dma@c300 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,eloplus-dma";
122 reg = <0xc300 0x4>;
123 ranges = <0x0 0xc100 0x200>;
124 cell-index = <1>;
125 dma-channel@0 {
126 compatible = "fsl,eloplus-dma-channel";
127 reg = <0x0 0x80>;
128 cell-index = <0>;
129 interrupts = <76 2 0 0>;
130 };
131 dma-channel@80 {
132 compatible = "fsl,eloplus-dma-channel";
133 reg = <0x80 0x80>;
134 cell-index = <1>;
135 interrupts = <77 2 0 0>;
136 };
137 dma-channel@100 {
138 compatible = "fsl,eloplus-dma-channel";
139 reg = <0x100 0x80>;
140 cell-index = <2>;
141 interrupts = <78 2 0 0>;
142 };
143 dma-channel@180 {
144 compatible = "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupts = <79 2 0 0>;
148 };
149 };
150
151 gpio: gpio-controller@f000 {
152 #gpio-cells = <2>;
153 compatible = "fsl,mpc8572-gpio";
154 reg = <0xf000 0x100>;
155 interrupts = <47 0x2 0 0>;
156 gpio-controller;
157 };
158
159 L2: l2-cache-controller@20000 {
160 compatible = "fsl,p2020-l2-cache-controller";
161 reg = <0x20000 0x1000>;
162 cache-line-size = <32>; // 32 bytes
163 cache-size = <0x80000>; // L2,512K
164 interrupts = <16 2 0 0>;
165 };
166
167 dma@21300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,eloplus-dma";
171 reg = <0x21300 0x4>;
172 ranges = <0x0 0x21100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,eloplus-dma-channel";
176 reg = <0x0 0x80>;
177 cell-index = <0>;
178 interrupts = <20 2 0 0>;
179 };
180 dma-channel@80 {
181 compatible = "fsl,eloplus-dma-channel";
182 reg = <0x80 0x80>;
183 cell-index = <1>;
184 interrupts = <21 2 0 0>;
185 };
186 dma-channel@100 {
187 compatible = "fsl,eloplus-dma-channel";
188 reg = <0x100 0x80>;
189 cell-index = <2>;
190 interrupts = <22 2 0 0>;
191 };
192 dma-channel@180 {
193 compatible = "fsl,eloplus-dma-channel";
194 reg = <0x180 0x80>;
195 cell-index = <3>;
196 interrupts = <23 2 0 0>;
197 };
198 };
199
200 usb@22000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl-usb2-dr";
204 reg = <0x22000 0x1000>;
205 interrupts = <28 0x2 0 0>;
206 };
207
208 mdio@24520 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,gianfar-mdio";
212 reg = <0x24520 0x20>;
213 };
214
215 mdio@25520 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "fsl,gianfar-tbi";
219 reg = <0x26520 0x20>;
220 };
221
222 mdio@26520 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,gianfar-tbi";
226 reg = <0x520 0x20>;
227 };
228
229 enet0: ethernet@24000 {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 cell-index = <0>;
233 device_type = "network";
234 model = "eTSEC";
235 compatible = "gianfar";
236 reg = <0x24000 0x1000>;
237 ranges = <0x0 0x24000 0x1000>;
238 local-mac-address = [ 00 00 00 00 00 00 ];
239 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
240 };
241
242 enet1: ethernet@25000 {
243 #address-cells = <1>;
244 #size-cells = <1>;
245 cell-index = <1>;
246 device_type = "network";
247 model = "eTSEC";
248 compatible = "gianfar";
249 reg = <0x25000 0x1000>;
250 ranges = <0x0 0x25000 0x1000>;
251 local-mac-address = [ 00 00 00 00 00 00 ];
252 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
253
254 };
255
256 enet2: ethernet@26000 {
257 #address-cells = <1>;
258 #size-cells = <1>;
259 cell-index = <2>;
260 device_type = "network";
261 model = "eTSEC";
262 compatible = "gianfar";
263 reg = <0x26000 0x1000>;
264 ranges = <0x0 0x26000 0x1000>;
265 local-mac-address = [ 00 00 00 00 00 00 ];
266 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
267
268 };
269
270 sdhci@2e000 {
271 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
272 reg = <0x2e000 0x1000>;
273 interrupts = <72 0x2 0 0>;
274 /* Filled in by U-Boot */
275 clock-frequency = <0>;
276 };
277
278 crypto@30000 {
279 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
280 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
281 reg = <0x30000 0x10000>;
282 interrupts = <45 2 0 0 58 2 0 0>;
283 fsl,num-channels = <4>;
284 fsl,channel-fifo-len = <24>;
285 fsl,exec-units-mask = <0xbfe>;
286 fsl,descriptor-types-mask = <0x3ab0ebf>;
287 };
288
289 mpic: pic@40000 {
290 interrupt-controller;
291 #address-cells = <0>;
292 #interrupt-cells = <2>;
293 reg = <0x40000 0x40000>;
294 compatible = "chrp,open-pic";
295 device_type = "open-pic";
296 };
297
298 msi@41600 {
299 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
300 reg = <0x41600 0x80>;
301 msi-available-ranges = <0 0x100>;
302 interrupts = <
303 0xe0 0 0 0
304 0xe1 0 0 0
305 0xe2 0 0 0
306 0xe3 0 0 0
307 0xe4 0 0 0
308 0xe5 0 0 0
309 0xe6 0 0 0
310 0xe7 0 0 0>;
311 };
312
313 global-utilities@e0000 { //global utilities block
314 compatible = "fsl,p2020-guts";
315 reg = <0xe0000 0x1000>;
316 fsl,has-rstcr;
317 };
318 };
319
320 pci0: pcie@ffe08000 {
321 compatible = "fsl,mpc8548-pcie";
322 device_type = "pci";
323 #interrupt-cells = <1>;
324 #size-cells = <2>;
325 #address-cells = <3>;
326 reg = <0 0xffe08000 0 0x1000>;
327 bus-range = <0 255>;
328 clock-frequency = <33333333>;
329 interrupts = <24 2 0 0>;
330 };
331
332 pci1: pcie@ffe09000 {
333 compatible = "fsl,mpc8548-pcie";
334 device_type = "pci";
335 #interrupt-cells = <1>;
336 #size-cells = <2>;
337 #address-cells = <3>;
338 reg = <0 0xffe09000 0 0x1000>;
339 bus-range = <0 255>;
340 clock-frequency = <33333333>;
341 interrupts = <25 2 0 0>;
342 };
343
344 pci2: pcie@ffe0a000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe0a000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupts = <26 2 0 0>;
354 };
355};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 05:37:38 -0400