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authorBen Dooks <ben-linux@fluff.org>2010-05-03 04:19:49 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-05 20:32:13 -0400
commit7ced5eab39809539e8fc7f3fb561bd3001d535e7 (patch)
tree67e1a351198da8f33f20e34228becc231af3ae44 /arch
parent1ec7269fd8b05044f2cb4059b679e053d57460f5 (diff)
ARM: S3C24XX: Add extended GPIO used on S3C2443 and beyond
Add the GPIO banks that are used on the S3C2443 and above to the list of available GPIOS. Currently we do not have any limit on the SoC GPIO, so these are being registered whether the SoC has them or not. It is currently up to the user not to try and use them. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h12
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h17
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpioj.h4
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c41
4 files changed, 69 insertions, 5 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 2edbb9c88ab..f3182ff847c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -34,6 +34,10 @@
34#define S3C2410_GPIO_F_NR (32) 34#define S3C2410_GPIO_F_NR (32)
35#define S3C2410_GPIO_G_NR (32) 35#define S3C2410_GPIO_G_NR (32)
36#define S3C2410_GPIO_H_NR (32) 36#define S3C2410_GPIO_H_NR (32)
37#define S3C2410_GPIO_J_NR (32) /* technically 16. */
38#define S3C2410_GPIO_K_NR (32) /* technically 16. */
39#define S3C2410_GPIO_L_NR (32) /* technically 15. */
40#define S3C2410_GPIO_M_NR (32) /* technically 2. */
37 41
38#if CONFIG_S3C_GPIO_SPACE != 0 42#if CONFIG_S3C_GPIO_SPACE != 0
39#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment 43#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
@@ -53,6 +57,10 @@ enum s3c_gpio_number {
53 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), 57 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
54 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), 58 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
55 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), 59 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
60 S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
61 S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
62 S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
63 S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
56}; 64};
57 65
58#endif /* __ASSEMBLY__ */ 66#endif /* __ASSEMBLY__ */
@@ -67,6 +75,10 @@ enum s3c_gpio_number {
67#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) 75#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) 76#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) 77#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
78#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
79#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
80#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
81#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
70 82
71/* compatibility until drivers can be modified */ 83/* compatibility until drivers can be modified */
72 84
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index fd672f330bf..821b966bf05 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -639,6 +639,23 @@
639 * for the 2412/2413 from the 2410/2440/2442 639 * for the 2412/2413 from the 2410/2440/2442
640*/ 640*/
641 641
642/* S3C2443 and above */
643#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
644#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
645#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
646
647#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
648#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
649#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
650
651#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
652#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
653#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
654
655#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
656#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
657#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
658
642/* miscellaneous control */ 659/* miscellaneous control */
643#define S3C2400_MISCCR S3C2410_GPIOREG(0x54) 660#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
644#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 661#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
index 1202ca5e99f..de463bc17b5 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -24,10 +24,6 @@
24 24
25#define S3C2440_GPIO_BANKJ (416) 25#define S3C2440_GPIO_BANKJ (416)
26 26
27#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0)
28#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
29#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
30
31#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) 27#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
32#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) 28#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
33#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) 29#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 376b061804c..e8c0e8a247b 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/gpiolib.c 1/* linux/arch/arm/plat-s3c24xx/gpiolib.c
2 * 2 *
3 * Copyright (c) 2008 Simtec Electronics 3 * Copyright (c) 2008-2010 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
@@ -172,8 +172,47 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
172 .ngpio = 11, 172 .ngpio = 11,
173 }, 173 },
174 }, 174 },
175 /* GPIOS for the S3C2443 and later devices. */
176 {
177 .base = S3C2440_GPJCON,
178 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
179 .chip = {
180 .base = S3C2410_GPJ(0),
181 .owner = THIS_MODULE,
182 .label = "GPIOJ",
183 .ngpio = 16,
184 },
185 }, {
186 .base = S3C2443_GPKCON,
187 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
188 .chip = {
189 .base = S3C2410_GPK(0),
190 .owner = THIS_MODULE,
191 .label = "GPIOK",
192 .ngpio = 16,
193 },
194 }, {
195 .base = S3C2443_GPLCON,
196 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
197 .chip = {
198 .base = S3C2410_GPL(0),
199 .owner = THIS_MODULE,
200 .label = "GPIOL",
201 .ngpio = 15,
202 },
203 }, {
204 .base = S3C2443_GPMCON,
205 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
206 .chip = {
207 .base = S3C2410_GPM(0),
208 .owner = THIS_MODULE,
209 .label = "GPIOM",
210 .ngpio = 2,
211 },
212 },
175}; 213};
176 214
215
177static __init int s3c24xx_gpiolib_init(void) 216static __init int s3c24xx_gpiolib_init(void)
178{ 217{
179 struct s3c_gpio_chip *chip = s3c24xx_gpios; 218 struct s3c_gpio_chip *chip = s3c24xx_gpios;