diff options
author | Will Deacon <will.deacon@arm.com> | 2011-11-15 08:25:04 -0500 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2011-12-06 09:04:14 -0500 |
commit | 1a4baafa7d203da1cceb302c2df38f0fea1c17a1 (patch) | |
tree | f64d1b22be6f3255ccb73470a9799890972bd670 /arch | |
parent | e6eadc67873d5f363c864cd7723104e7d47dcb44 (diff) |
ARM: proc-*.S: place cpu_reset functions into .idmap.text section
The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.
This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.
Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mm/proc-arm1020.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm1020e.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm1022.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm1026.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm6_7.S | 4 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm720.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm740.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm7tdmi.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm920.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm922.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm925.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm926.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm940.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm946.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm9tdmi.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-fa526.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-feroceon.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-mohawk.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-sa110.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 3 | ||||
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 3 |
24 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 67469665d47..234951345eb 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S | |||
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020_proc_fin) | |||
95 | * loc: location to jump to for soft reset | 95 | * loc: location to jump to for soft reset |
96 | */ | 96 | */ |
97 | .align 5 | 97 | .align 5 |
98 | .pushsection .idmap.text, "ax" | ||
98 | ENTRY(cpu_arm1020_reset) | 99 | ENTRY(cpu_arm1020_reset) |
99 | mov ip, #0 | 100 | mov ip, #0 |
100 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 101 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020_reset) | |||
107 | bic ip, ip, #0x1100 @ ...i...s........ | 108 | bic ip, ip, #0x1100 @ ...i...s........ |
108 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 109 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
109 | mov pc, r0 | 110 | mov pc, r0 |
111 | ENDPROC(cpu_arm1020_reset) | ||
112 | .popsection | ||
110 | 113 | ||
111 | /* | 114 | /* |
112 | * cpu_arm1020_do_idle() | 115 | * cpu_arm1020_do_idle() |
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 4251421c0ed..c244b06caac 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S | |||
@@ -95,6 +95,7 @@ ENTRY(cpu_arm1020e_proc_fin) | |||
95 | * loc: location to jump to for soft reset | 95 | * loc: location to jump to for soft reset |
96 | */ | 96 | */ |
97 | .align 5 | 97 | .align 5 |
98 | .pushsection .idmap.text, "ax" | ||
98 | ENTRY(cpu_arm1020e_reset) | 99 | ENTRY(cpu_arm1020e_reset) |
99 | mov ip, #0 | 100 | mov ip, #0 |
100 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 101 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -107,6 +108,8 @@ ENTRY(cpu_arm1020e_reset) | |||
107 | bic ip, ip, #0x1100 @ ...i...s........ | 108 | bic ip, ip, #0x1100 @ ...i...s........ |
108 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 109 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
109 | mov pc, r0 | 110 | mov pc, r0 |
111 | ENDPROC(cpu_arm1020e_reset) | ||
112 | .popsection | ||
110 | 113 | ||
111 | /* | 114 | /* |
112 | * cpu_arm1020e_do_idle() | 115 | * cpu_arm1020e_do_idle() |
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index d283cf3d06e..38fe22efd18 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S | |||
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1022_proc_fin) | |||
84 | * loc: location to jump to for soft reset | 84 | * loc: location to jump to for soft reset |
85 | */ | 85 | */ |
86 | .align 5 | 86 | .align 5 |
87 | .pushsection .idmap.text, "ax" | ||
87 | ENTRY(cpu_arm1022_reset) | 88 | ENTRY(cpu_arm1022_reset) |
88 | mov ip, #0 | 89 | mov ip, #0 |
89 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 90 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1022_reset) | |||
96 | bic ip, ip, #0x1100 @ ...i...s........ | 97 | bic ip, ip, #0x1100 @ ...i...s........ |
97 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 98 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
98 | mov pc, r0 | 99 | mov pc, r0 |
100 | ENDPROC(cpu_arm1022_reset) | ||
101 | .popsection | ||
99 | 102 | ||
100 | /* | 103 | /* |
101 | * cpu_arm1022_do_idle() | 104 | * cpu_arm1022_do_idle() |
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 678a1ceafed..3eb9c3c26c7 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S | |||
@@ -84,6 +84,7 @@ ENTRY(cpu_arm1026_proc_fin) | |||
84 | * loc: location to jump to for soft reset | 84 | * loc: location to jump to for soft reset |
85 | */ | 85 | */ |
86 | .align 5 | 86 | .align 5 |
87 | .pushsection .idmap.text, "ax" | ||
87 | ENTRY(cpu_arm1026_reset) | 88 | ENTRY(cpu_arm1026_reset) |
88 | mov ip, #0 | 89 | mov ip, #0 |
89 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 90 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -96,6 +97,8 @@ ENTRY(cpu_arm1026_reset) | |||
96 | bic ip, ip, #0x1100 @ ...i...s........ | 97 | bic ip, ip, #0x1100 @ ...i...s........ |
97 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 98 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
98 | mov pc, r0 | 99 | mov pc, r0 |
100 | ENDPROC(cpu_arm1026_reset) | ||
101 | .popsection | ||
99 | 102 | ||
100 | /* | 103 | /* |
101 | * cpu_arm1026_do_idle() | 104 | * cpu_arm1026_do_idle() |
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index e5b974cddac..4fbeb5b8e6c 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S | |||
@@ -225,6 +225,7 @@ ENTRY(cpu_arm7_set_pte_ext) | |||
225 | * Params : r0 = address to jump to | 225 | * Params : r0 = address to jump to |
226 | * Notes : This sets up everything for a reset | 226 | * Notes : This sets up everything for a reset |
227 | */ | 227 | */ |
228 | .pushsection .idmap.text, "ax" | ||
228 | ENTRY(cpu_arm6_reset) | 229 | ENTRY(cpu_arm6_reset) |
229 | ENTRY(cpu_arm7_reset) | 230 | ENTRY(cpu_arm7_reset) |
230 | mov r1, #0 | 231 | mov r1, #0 |
@@ -235,6 +236,9 @@ ENTRY(cpu_arm7_reset) | |||
235 | mov r1, #0x30 | 236 | mov r1, #0x30 |
236 | mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc | 237 | mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc |
237 | mov pc, r0 | 238 | mov pc, r0 |
239 | ENDPROC(cpu_arm6_reset) | ||
240 | ENDPROC(cpu_arm7_reset) | ||
241 | .popsection | ||
238 | 242 | ||
239 | __CPUINIT | 243 | __CPUINIT |
240 | 244 | ||
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 55f4e290665..0ac908c7ade 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S | |||
@@ -101,6 +101,7 @@ ENTRY(cpu_arm720_set_pte_ext) | |||
101 | * Params : r0 = address to jump to | 101 | * Params : r0 = address to jump to |
102 | * Notes : This sets up everything for a reset | 102 | * Notes : This sets up everything for a reset |
103 | */ | 103 | */ |
104 | .pushsection .idmap.text, "ax" | ||
104 | ENTRY(cpu_arm720_reset) | 105 | ENTRY(cpu_arm720_reset) |
105 | mov ip, #0 | 106 | mov ip, #0 |
106 | mcr p15, 0, ip, c7, c7, 0 @ invalidate cache | 107 | mcr p15, 0, ip, c7, c7, 0 @ invalidate cache |
@@ -112,6 +113,8 @@ ENTRY(cpu_arm720_reset) | |||
112 | bic ip, ip, #0x2100 @ ..v....s........ | 113 | bic ip, ip, #0x2100 @ ..v....s........ |
113 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 114 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
114 | mov pc, r0 | 115 | mov pc, r0 |
116 | ENDPROC(cpu_arm720_reset) | ||
117 | .popsection | ||
115 | 118 | ||
116 | __CPUINIT | 119 | __CPUINIT |
117 | 120 | ||
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 4506be3adda..dc5de5d53f2 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S | |||
@@ -49,6 +49,7 @@ ENTRY(cpu_arm740_proc_fin) | |||
49 | * Params : r0 = address to jump to | 49 | * Params : r0 = address to jump to |
50 | * Notes : This sets up everything for a reset | 50 | * Notes : This sets up everything for a reset |
51 | */ | 51 | */ |
52 | .pushsection .idmap.text, "ax" | ||
52 | ENTRY(cpu_arm740_reset) | 53 | ENTRY(cpu_arm740_reset) |
53 | mov ip, #0 | 54 | mov ip, #0 |
54 | mcr p15, 0, ip, c7, c0, 0 @ invalidate cache | 55 | mcr p15, 0, ip, c7, c0, 0 @ invalidate cache |
@@ -56,6 +57,8 @@ ENTRY(cpu_arm740_reset) | |||
56 | bic ip, ip, #0x0000000c @ ............wc.. | 57 | bic ip, ip, #0x0000000c @ ............wc.. |
57 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 58 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
58 | mov pc, r0 | 59 | mov pc, r0 |
60 | ENDPROC(cpu_arm740_reset) | ||
61 | .popsection | ||
59 | 62 | ||
60 | __CPUINIT | 63 | __CPUINIT |
61 | 64 | ||
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 7e0e1fe4ed4..6ddea3e464b 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S | |||
@@ -45,8 +45,11 @@ ENTRY(cpu_arm7tdmi_proc_fin) | |||
45 | * Params : loc(r0) address to jump to | 45 | * Params : loc(r0) address to jump to |
46 | * Purpose : Sets up everything for a reset and jump to the location for soft reset. | 46 | * Purpose : Sets up everything for a reset and jump to the location for soft reset. |
47 | */ | 47 | */ |
48 | .pushsection .idmap.text, "ax" | ||
48 | ENTRY(cpu_arm7tdmi_reset) | 49 | ENTRY(cpu_arm7tdmi_reset) |
49 | mov pc, r0 | 50 | mov pc, r0 |
51 | ENDPROC(cpu_arm7tdmi_reset) | ||
52 | .popsection | ||
50 | 53 | ||
51 | __CPUINIT | 54 | __CPUINIT |
52 | 55 | ||
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 88fb3d9e064..cb941ae95f6 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S | |||
@@ -85,6 +85,7 @@ ENTRY(cpu_arm920_proc_fin) | |||
85 | * loc: location to jump to for soft reset | 85 | * loc: location to jump to for soft reset |
86 | */ | 86 | */ |
87 | .align 5 | 87 | .align 5 |
88 | .pushsection .idmap.text, "ax" | ||
88 | ENTRY(cpu_arm920_reset) | 89 | ENTRY(cpu_arm920_reset) |
89 | mov ip, #0 | 90 | mov ip, #0 |
90 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 91 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -97,6 +98,8 @@ ENTRY(cpu_arm920_reset) | |||
97 | bic ip, ip, #0x1100 @ ...i...s........ | 98 | bic ip, ip, #0x1100 @ ...i...s........ |
98 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 99 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
99 | mov pc, r0 | 100 | mov pc, r0 |
101 | ENDPROC(cpu_arm920_reset) | ||
102 | .popsection | ||
100 | 103 | ||
101 | /* | 104 | /* |
102 | * cpu_arm920_do_idle() | 105 | * cpu_arm920_do_idle() |
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 490e1883385..4ec0e074dd5 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S | |||
@@ -87,6 +87,7 @@ ENTRY(cpu_arm922_proc_fin) | |||
87 | * loc: location to jump to for soft reset | 87 | * loc: location to jump to for soft reset |
88 | */ | 88 | */ |
89 | .align 5 | 89 | .align 5 |
90 | .pushsection .idmap.text, "ax" | ||
90 | ENTRY(cpu_arm922_reset) | 91 | ENTRY(cpu_arm922_reset) |
91 | mov ip, #0 | 92 | mov ip, #0 |
92 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 93 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -99,6 +100,8 @@ ENTRY(cpu_arm922_reset) | |||
99 | bic ip, ip, #0x1100 @ ...i...s........ | 100 | bic ip, ip, #0x1100 @ ...i...s........ |
100 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 101 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
101 | mov pc, r0 | 102 | mov pc, r0 |
103 | ENDPROC(cpu_arm922_reset) | ||
104 | .popsection | ||
102 | 105 | ||
103 | /* | 106 | /* |
104 | * cpu_arm922_do_idle() | 107 | * cpu_arm922_do_idle() |
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 51d494be057..9dccd9a365b 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S | |||
@@ -108,6 +108,7 @@ ENTRY(cpu_arm925_proc_fin) | |||
108 | * loc: location to jump to for soft reset | 108 | * loc: location to jump to for soft reset |
109 | */ | 109 | */ |
110 | .align 5 | 110 | .align 5 |
111 | .pushsection .idmap.text, "ax" | ||
111 | ENTRY(cpu_arm925_reset) | 112 | ENTRY(cpu_arm925_reset) |
112 | /* Send software reset to MPU and DSP */ | 113 | /* Send software reset to MPU and DSP */ |
113 | mov ip, #0xff000000 | 114 | mov ip, #0xff000000 |
@@ -115,6 +116,8 @@ ENTRY(cpu_arm925_reset) | |||
115 | orr ip, ip, #0x0000ce00 | 116 | orr ip, ip, #0x0000ce00 |
116 | mov r4, #1 | 117 | mov r4, #1 |
117 | strh r4, [ip, #0x10] | 118 | strh r4, [ip, #0x10] |
119 | ENDPROC(cpu_arm925_reset) | ||
120 | .popsection | ||
118 | 121 | ||
119 | mov ip, #0 | 122 | mov ip, #0 |
120 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 123 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 9f8fd91f918..820259b81a1 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S | |||
@@ -77,6 +77,7 @@ ENTRY(cpu_arm926_proc_fin) | |||
77 | * loc: location to jump to for soft reset | 77 | * loc: location to jump to for soft reset |
78 | */ | 78 | */ |
79 | .align 5 | 79 | .align 5 |
80 | .pushsection .idmap.text, "ax" | ||
80 | ENTRY(cpu_arm926_reset) | 81 | ENTRY(cpu_arm926_reset) |
81 | mov ip, #0 | 82 | mov ip, #0 |
82 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 83 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -89,6 +90,8 @@ ENTRY(cpu_arm926_reset) | |||
89 | bic ip, ip, #0x1100 @ ...i...s........ | 90 | bic ip, ip, #0x1100 @ ...i...s........ |
90 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 91 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
91 | mov pc, r0 | 92 | mov pc, r0 |
93 | ENDPROC(cpu_arm926_reset) | ||
94 | .popsection | ||
92 | 95 | ||
93 | /* | 96 | /* |
94 | * cpu_arm926_do_idle() | 97 | * cpu_arm926_do_idle() |
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index ac750d50615..9fdc0a17097 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S | |||
@@ -48,6 +48,7 @@ ENTRY(cpu_arm940_proc_fin) | |||
48 | * Params : r0 = address to jump to | 48 | * Params : r0 = address to jump to |
49 | * Notes : This sets up everything for a reset | 49 | * Notes : This sets up everything for a reset |
50 | */ | 50 | */ |
51 | .pushsection .idmap.text, "ax" | ||
51 | ENTRY(cpu_arm940_reset) | 52 | ENTRY(cpu_arm940_reset) |
52 | mov ip, #0 | 53 | mov ip, #0 |
53 | mcr p15, 0, ip, c7, c5, 0 @ flush I cache | 54 | mcr p15, 0, ip, c7, c5, 0 @ flush I cache |
@@ -58,6 +59,8 @@ ENTRY(cpu_arm940_reset) | |||
58 | bic ip, ip, #0x00001000 @ i-cache | 59 | bic ip, ip, #0x00001000 @ i-cache |
59 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 60 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
60 | mov pc, r0 | 61 | mov pc, r0 |
62 | ENDPROC(cpu_arm940_reset) | ||
63 | .popsection | ||
61 | 64 | ||
62 | /* | 65 | /* |
63 | * cpu_arm940_do_idle() | 66 | * cpu_arm940_do_idle() |
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 683af3a182b..f684cfedcca 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S | |||
@@ -55,6 +55,7 @@ ENTRY(cpu_arm946_proc_fin) | |||
55 | * Params : r0 = address to jump to | 55 | * Params : r0 = address to jump to |
56 | * Notes : This sets up everything for a reset | 56 | * Notes : This sets up everything for a reset |
57 | */ | 57 | */ |
58 | .pushsection .idmap.text, "ax" | ||
58 | ENTRY(cpu_arm946_reset) | 59 | ENTRY(cpu_arm946_reset) |
59 | mov ip, #0 | 60 | mov ip, #0 |
60 | mcr p15, 0, ip, c7, c5, 0 @ flush I cache | 61 | mcr p15, 0, ip, c7, c5, 0 @ flush I cache |
@@ -65,6 +66,8 @@ ENTRY(cpu_arm946_reset) | |||
65 | bic ip, ip, #0x00001000 @ i-cache | 66 | bic ip, ip, #0x00001000 @ i-cache |
66 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 67 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
67 | mov pc, r0 | 68 | mov pc, r0 |
69 | ENDPROC(cpu_arm946_reset) | ||
70 | .popsection | ||
68 | 71 | ||
69 | /* | 72 | /* |
70 | * cpu_arm946_do_idle() | 73 | * cpu_arm946_do_idle() |
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 2120f9e2af7..8881391dfb9 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S | |||
@@ -45,8 +45,11 @@ ENTRY(cpu_arm9tdmi_proc_fin) | |||
45 | * Params : loc(r0) address to jump to | 45 | * Params : loc(r0) address to jump to |
46 | * Purpose : Sets up everything for a reset and jump to the location for soft reset. | 46 | * Purpose : Sets up everything for a reset and jump to the location for soft reset. |
47 | */ | 47 | */ |
48 | .pushsection .idmap.text, "ax" | ||
48 | ENTRY(cpu_arm9tdmi_reset) | 49 | ENTRY(cpu_arm9tdmi_reset) |
49 | mov pc, r0 | 50 | mov pc, r0 |
51 | ENDPROC(cpu_arm9tdmi_reset) | ||
52 | .popsection | ||
50 | 53 | ||
51 | __CPUINIT | 54 | __CPUINIT |
52 | 55 | ||
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index 4c7a5710472..272558a133a 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S | |||
@@ -57,6 +57,7 @@ ENTRY(cpu_fa526_proc_fin) | |||
57 | * loc: location to jump to for soft reset | 57 | * loc: location to jump to for soft reset |
58 | */ | 58 | */ |
59 | .align 4 | 59 | .align 4 |
60 | .pushsection .idmap.text, "ax" | ||
60 | ENTRY(cpu_fa526_reset) | 61 | ENTRY(cpu_fa526_reset) |
61 | /* TODO: Use CP8 if possible... */ | 62 | /* TODO: Use CP8 if possible... */ |
62 | mov ip, #0 | 63 | mov ip, #0 |
@@ -73,6 +74,8 @@ ENTRY(cpu_fa526_reset) | |||
73 | nop | 74 | nop |
74 | nop | 75 | nop |
75 | mov pc, r0 | 76 | mov pc, r0 |
77 | ENDPROC(cpu_fa526_reset) | ||
78 | .popsection | ||
76 | 79 | ||
77 | /* | 80 | /* |
78 | * cpu_fa526_do_idle() | 81 | * cpu_fa526_do_idle() |
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 8a6c2f78c1c..ba3c500584a 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
@@ -98,6 +98,7 @@ ENTRY(cpu_feroceon_proc_fin) | |||
98 | * loc: location to jump to for soft reset | 98 | * loc: location to jump to for soft reset |
99 | */ | 99 | */ |
100 | .align 5 | 100 | .align 5 |
101 | .pushsection .idmap.text, "ax" | ||
101 | ENTRY(cpu_feroceon_reset) | 102 | ENTRY(cpu_feroceon_reset) |
102 | mov ip, #0 | 103 | mov ip, #0 |
103 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 104 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -110,6 +111,8 @@ ENTRY(cpu_feroceon_reset) | |||
110 | bic ip, ip, #0x1100 @ ...i...s........ | 111 | bic ip, ip, #0x1100 @ ...i...s........ |
111 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 112 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
112 | mov pc, r0 | 113 | mov pc, r0 |
114 | ENDPROC(cpu_feroceon_reset) | ||
115 | .popsection | ||
113 | 116 | ||
114 | /* | 117 | /* |
115 | * cpu_feroceon_do_idle() | 118 | * cpu_feroceon_do_idle() |
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index db52b0fb14a..cdfedc5b8ad 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S | |||
@@ -69,6 +69,7 @@ ENTRY(cpu_mohawk_proc_fin) | |||
69 | * (same as arm926) | 69 | * (same as arm926) |
70 | */ | 70 | */ |
71 | .align 5 | 71 | .align 5 |
72 | .pushsection .idmap.text, "ax" | ||
72 | ENTRY(cpu_mohawk_reset) | 73 | ENTRY(cpu_mohawk_reset) |
73 | mov ip, #0 | 74 | mov ip, #0 |
74 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 75 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -79,6 +80,8 @@ ENTRY(cpu_mohawk_reset) | |||
79 | bic ip, ip, #0x1100 @ ...i...s........ | 80 | bic ip, ip, #0x1100 @ ...i...s........ |
80 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 81 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
81 | mov pc, r0 | 82 | mov pc, r0 |
83 | ENDPROC(cpu_mohawk_reset) | ||
84 | .popsection | ||
82 | 85 | ||
83 | /* | 86 | /* |
84 | * cpu_mohawk_do_idle() | 87 | * cpu_mohawk_do_idle() |
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index d50ada26edd..775d70fba93 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S | |||
@@ -62,6 +62,7 @@ ENTRY(cpu_sa110_proc_fin) | |||
62 | * loc: location to jump to for soft reset | 62 | * loc: location to jump to for soft reset |
63 | */ | 63 | */ |
64 | .align 5 | 64 | .align 5 |
65 | .pushsection .idmap.text, "ax" | ||
65 | ENTRY(cpu_sa110_reset) | 66 | ENTRY(cpu_sa110_reset) |
66 | mov ip, #0 | 67 | mov ip, #0 |
67 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 68 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -74,6 +75,8 @@ ENTRY(cpu_sa110_reset) | |||
74 | bic ip, ip, #0x1100 @ ...i...s........ | 75 | bic ip, ip, #0x1100 @ ...i...s........ |
75 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 76 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
76 | mov pc, r0 | 77 | mov pc, r0 |
78 | ENDPROC(cpu_sa110_reset) | ||
79 | .popsection | ||
77 | 80 | ||
78 | /* | 81 | /* |
79 | * cpu_sa110_do_idle(type) | 82 | * cpu_sa110_do_idle(type) |
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 7d91545d089..3aa0da11fd8 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S | |||
@@ -70,6 +70,7 @@ ENTRY(cpu_sa1100_proc_fin) | |||
70 | * loc: location to jump to for soft reset | 70 | * loc: location to jump to for soft reset |
71 | */ | 71 | */ |
72 | .align 5 | 72 | .align 5 |
73 | .pushsection .idmap.text, "ax" | ||
73 | ENTRY(cpu_sa1100_reset) | 74 | ENTRY(cpu_sa1100_reset) |
74 | mov ip, #0 | 75 | mov ip, #0 |
75 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | 76 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
@@ -82,6 +83,8 @@ ENTRY(cpu_sa1100_reset) | |||
82 | bic ip, ip, #0x1100 @ ...i...s........ | 83 | bic ip, ip, #0x1100 @ ...i...s........ |
83 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | 84 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
84 | mov pc, r0 | 85 | mov pc, r0 |
86 | ENDPROC(cpu_sa1100_reset) | ||
87 | .popsection | ||
85 | 88 | ||
86 | /* | 89 | /* |
87 | * cpu_sa1100_do_idle(type) | 90 | * cpu_sa1100_do_idle(type) |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index d061d2fa550..5900cd520e8 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
@@ -55,6 +55,7 @@ ENTRY(cpu_v6_proc_fin) | |||
55 | * - loc - location to jump to for soft reset | 55 | * - loc - location to jump to for soft reset |
56 | */ | 56 | */ |
57 | .align 5 | 57 | .align 5 |
58 | .pushsection .idmap.text, "ax" | ||
58 | ENTRY(cpu_v6_reset) | 59 | ENTRY(cpu_v6_reset) |
59 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register | 60 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
60 | bic r1, r1, #0x1 @ ...............m | 61 | bic r1, r1, #0x1 @ ...............m |
@@ -62,6 +63,8 @@ ENTRY(cpu_v6_reset) | |||
62 | mov r1, #0 | 63 | mov r1, #0 |
63 | mcr p15, 0, r1, c7, c5, 4 @ ISB | 64 | mcr p15, 0, r1, c7, c5, 4 @ ISB |
64 | mov pc, r0 | 65 | mov pc, r0 |
66 | ENDPROC(cpu_v6_reset) | ||
67 | .popsection | ||
65 | 68 | ||
66 | /* | 69 | /* |
67 | * cpu_v6_do_idle() | 70 | * cpu_v6_do_idle() |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c559ac3814..66a185f018a 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -63,6 +63,7 @@ ENDPROC(cpu_v7_proc_fin) | |||
63 | * caches disabled. | 63 | * caches disabled. |
64 | */ | 64 | */ |
65 | .align 5 | 65 | .align 5 |
66 | .pushsection .idmap.text, "ax" | ||
66 | ENTRY(cpu_v7_reset) | 67 | ENTRY(cpu_v7_reset) |
67 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register | 68 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
68 | bic r1, r1, #0x1 @ ...............m | 69 | bic r1, r1, #0x1 @ ...............m |
@@ -71,6 +72,7 @@ ENTRY(cpu_v7_reset) | |||
71 | isb | 72 | isb |
72 | mov pc, r0 | 73 | mov pc, r0 |
73 | ENDPROC(cpu_v7_reset) | 74 | ENDPROC(cpu_v7_reset) |
75 | .popsection | ||
74 | 76 | ||
75 | /* | 77 | /* |
76 | * cpu_v7_do_idle() | 78 | * cpu_v7_do_idle() |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index abf0507a08a..b0d57869da2 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -105,6 +105,7 @@ ENTRY(cpu_xsc3_proc_fin) | |||
105 | * loc: location to jump to for soft reset | 105 | * loc: location to jump to for soft reset |
106 | */ | 106 | */ |
107 | .align 5 | 107 | .align 5 |
108 | .pushsection .idmap.text, "ax" | ||
108 | ENTRY(cpu_xsc3_reset) | 109 | ENTRY(cpu_xsc3_reset) |
109 | mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE | 110 | mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE |
110 | msr cpsr_c, r1 @ reset CPSR | 111 | msr cpsr_c, r1 @ reset CPSR |
@@ -119,6 +120,8 @@ ENTRY(cpu_xsc3_reset) | |||
119 | @ already containing those two last instructions to survive. | 120 | @ already containing those two last instructions to survive. |
120 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs | 121 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs |
121 | mov pc, r0 | 122 | mov pc, r0 |
123 | ENDPROC(cpu_xsc3_reset) | ||
124 | .popsection | ||
122 | 125 | ||
123 | /* | 126 | /* |
124 | * cpu_xsc3_do_idle() | 127 | * cpu_xsc3_do_idle() |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 3277904beba..4ffebaa595e 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -142,6 +142,7 @@ ENTRY(cpu_xscale_proc_fin) | |||
142 | * Beware PXA270 erratum E7. | 142 | * Beware PXA270 erratum E7. |
143 | */ | 143 | */ |
144 | .align 5 | 144 | .align 5 |
145 | .pushsection .idmap.text, "ax" | ||
145 | ENTRY(cpu_xscale_reset) | 146 | ENTRY(cpu_xscale_reset) |
146 | mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE | 147 | mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE |
147 | msr cpsr_c, r1 @ reset CPSR | 148 | msr cpsr_c, r1 @ reset CPSR |
@@ -160,6 +161,8 @@ ENTRY(cpu_xscale_reset) | |||
160 | @ already containing those two last instructions to survive. | 161 | @ already containing those two last instructions to survive. |
161 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | 162 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
162 | mov pc, r0 | 163 | mov pc, r0 |
164 | ENDPROC(cpu_xscale_reset) | ||
165 | .popsection | ||
163 | 166 | ||
164 | /* | 167 | /* |
165 | * cpu_xscale_do_idle() | 168 | * cpu_xscale_do_idle() |