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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-12 22:25:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-12 22:25:41 -0400
commit18a022de47bc11ee20d7d0f4dd72d42d2cfdc51c (patch)
tree84e178e4e475400f8e9a5c74f1e2cb35ee17fca4 /arch
parent02a650e2820e19fde8f6a49752027217fdd33d78 (diff)
parentd23b5799b608112bb799c9b0e1e11ee1da692d76 (diff)
Merge tag 'for-3.7' of git://openrisc.net/jonas/linux
Pull OpenRISC updates from Jonas Bonn: "Fixups for some corner cases, build issues, and some obvious bugs in IRQ handling. No major changes." * tag 'for-3.7' of git://openrisc.net/jonas/linux: openrisc: mask interrupts in irq_mask_ack function openrisc: fix typos in comments and warnings openrisc: PIC should act on domain-local irqs openrisc: Make cpu_relax() invoke barrier() audit: define AUDIT_ARCH_OPENRISC openrisc: delay: fix handling of counter overflow openrisc: delay: fix loops calculation for __const_udelay
Diffstat (limited to 'arch')
-rw-r--r--arch/openrisc/include/asm/processor.h2
-rw-r--r--arch/openrisc/kernel/irq.c20
-rw-r--r--arch/openrisc/kernel/ptrace.c2
-rw-r--r--arch/openrisc/lib/delay.c6
4 files changed, 16 insertions, 14 deletions
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
index 30462f1fe95..43decdbdb2e 100644
--- a/arch/openrisc/include/asm/processor.h
+++ b/arch/openrisc/include/asm/processor.h
@@ -103,7 +103,7 @@ extern unsigned long thread_saved_pc(struct task_struct *t);
103 103
104#define init_stack (init_thread_union.stack) 104#define init_stack (init_thread_union.stack)
105 105
106#define cpu_relax() do { } while (0) 106#define cpu_relax() barrier()
107 107
108#endif /* __ASSEMBLY__ */ 108#endif /* __ASSEMBLY__ */
109#endif /* __ASM_OPENRISC_PROCESSOR_H */ 109#endif /* __ASM_OPENRISC_PROCESSOR_H */
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index e935b9d8eee..8ec77bc9f1e 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -46,19 +46,19 @@ EXPORT_SYMBOL(arch_local_irq_restore);
46 46
47static void or1k_pic_mask(struct irq_data *data) 47static void or1k_pic_mask(struct irq_data *data)
48{ 48{
49 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->irq)); 49 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
50} 50}
51 51
52static void or1k_pic_unmask(struct irq_data *data) 52static void or1k_pic_unmask(struct irq_data *data)
53{ 53{
54 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->irq)); 54 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
55} 55}
56 56
57static void or1k_pic_ack(struct irq_data *data) 57static void or1k_pic_ack(struct irq_data *data)
58{ 58{
59 /* EDGE-triggered interrupts need to be ack'ed in order to clear 59 /* EDGE-triggered interrupts need to be ack'ed in order to clear
60 * the latch. 60 * the latch.
61 * LEVER-triggered interrupts do not need to be ack'ed; however, 61 * LEVEL-triggered interrupts do not need to be ack'ed; however,
62 * ack'ing the interrupt has no ill-effect and is quicker than 62 * ack'ing the interrupt has no ill-effect and is quicker than
63 * trying to figure out what type it is... 63 * trying to figure out what type it is...
64 */ 64 */
@@ -75,10 +75,10 @@ static void or1k_pic_ack(struct irq_data *data)
75 * as opposed to a 1 as mandated by the spec 75 * as opposed to a 1 as mandated by the spec
76 */ 76 */
77 77
78 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq)); 78 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
79#else 79#else
80 WARN(1, "Interrupt handling possibily broken\n"); 80 WARN(1, "Interrupt handling possibly broken\n");
81 mtspr(SPR_PICSR, (1UL << irq)); 81 mtspr(SPR_PICSR, (1UL << data->hwirq));
82#endif 82#endif
83} 83}
84 84
@@ -87,10 +87,12 @@ static void or1k_pic_mask_ack(struct irq_data *data)
87 /* Comments for pic_ack apply here, too */ 87 /* Comments for pic_ack apply here, too */
88 88
89#ifdef CONFIG_OR1K_1200 89#ifdef CONFIG_OR1K_1200
90 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq)); 90 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
91 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
91#else 92#else
92 WARN(1, "Interrupt handling possibily broken\n"); 93 WARN(1, "Interrupt handling possibly broken\n");
93 mtspr(SPR_PICSR, (1UL << irq)); 94 mtspr(SPR_PICMR, (1UL << data->hwirq));
95 mtspr(SPR_PICSR, (1UL << data->hwirq));
94#endif 96#endif
95} 97}
96 98
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index e71781d24b0..71a2a0c34c6 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -187,7 +187,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
187 */ 187 */
188 ret = -1L; 188 ret = -1L;
189 189
190 audit_syscall_entry(audit_arch(), regs->gpr[11], 190 audit_syscall_entry(AUDIT_ARCH_OPENRISC, regs->gpr[11],
191 regs->gpr[3], regs->gpr[4], 191 regs->gpr[3], regs->gpr[4],
192 regs->gpr[5], regs->gpr[6]); 192 regs->gpr[5], regs->gpr[6]);
193 193
diff --git a/arch/openrisc/lib/delay.c b/arch/openrisc/lib/delay.c
index 01d9740ae6f..c330767c921 100644
--- a/arch/openrisc/lib/delay.c
+++ b/arch/openrisc/lib/delay.c
@@ -30,9 +30,9 @@ int __devinit read_current_timer(unsigned long *timer_value)
30 30
31void __delay(unsigned long cycles) 31void __delay(unsigned long cycles)
32{ 32{
33 cycles_t target = get_cycles() + cycles; 33 cycles_t start = get_cycles();
34 34
35 while (get_cycles() < target) 35 while ((get_cycles() - start) < cycles)
36 cpu_relax(); 36 cpu_relax();
37} 37}
38EXPORT_SYMBOL(__delay); 38EXPORT_SYMBOL(__delay);
@@ -41,7 +41,7 @@ inline void __const_udelay(unsigned long xloops)
41{ 41{
42 unsigned long long loops; 42 unsigned long long loops;
43 43
44 loops = xloops * loops_per_jiffy * HZ; 44 loops = (unsigned long long)xloops * loops_per_jiffy * HZ;
45 45
46 __delay(loops >> 32); 46 __delay(loops >> 32);
47} 47}