aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorMichal Simek <monstr@monstr.eu>2011-02-04 09:24:11 -0500
committerMichal Simek <monstr@monstr.eu>2011-02-07 13:13:01 -0500
commit0eb6aaf52965c14ba3ea245448c4806cfcd1d18c (patch)
tree046fba87d27c0461cd3ba897e5a0fd3b5362c3df /arch
parent1f80a67da2da4180355bc36b2691f16684b194fd (diff)
microblaze: Fix msr instruction detection
Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch')
-rw-r--r--arch/microblaze/kernel/head.S15
-rw-r--r--arch/microblaze/kernel/setup.c4
2 files changed, 9 insertions, 10 deletions
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 0db20b5abb5..778a5ce2e4f 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -62,15 +62,14 @@ real_start:
62 andi r1, r1, ~2 62 andi r1, r1, ~2
63 mts rmsr, r1 63 mts rmsr, r1
64/* 64/*
65 * Here is checking mechanism which check if Microblaze has msr instructions 65 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
66 * We load msr and compare it with previous r1 value - if is the same, 66 * if the msrclr instruction is not enabled. We use this to detect
67 * msr instructions works if not - cpu don't have them. 67 * if the opcode is available, by issuing msrclr and then testing the result.
68 * r8 == 0 - msr instructions are implemented
69 * r8 != 0 - msr instructions are not implemented
68 */ 70 */
69 /* r8=0 - I have msr instr, 1 - I don't have them */ 71 msrclr r8, 0 /* clear nothing - just read msr for test */
70 rsubi r0, r0, 1 /* set the carry bit */ 72 cmpu r8, r8, r1 /* r1 must contain msr reg content */
71 msrclr r0, 0x4 /* try to clear it */
72 /* read the carry bit, r8 will be '0' if msrclr exists */
73 addik r8, r0, 0
74 73
75/* r7 may point to an FDT, or there may be one linked in. 74/* r7 may point to an FDT, or there may be one linked in.
76 if it's in r7, we've got to save it away ASAP. 75 if it's in r7, we've got to save it away ASAP.
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index bb1558e4b28..9312fbb37ef 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
161#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 161#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
162 if (msr) 162 if (msr)
163 eprintk("!!!Your kernel has setup MSR instruction but " 163 eprintk("!!!Your kernel has setup MSR instruction but "
164 "CPU don't have it %d\n", msr); 164 "CPU don't have it %x\n", msr);
165#else 165#else
166 if (!msr) 166 if (!msr)
167 eprintk("!!!Your kernel not setup MSR instruction but " 167 eprintk("!!!Your kernel not setup MSR instruction but "
168 "CPU have it %d\n", msr); 168 "CPU have it %x\n", msr);
169#endif 169#endif
170 170
171 for (src = __ivt_start; src < __ivt_end; src++, dst++) 171 for (src = __ivt_start; src < __ivt_end; src++, dst++)