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authorLinus Torvalds <torvalds@linux-foundation.org>2011-10-26 11:30:33 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-10-26 11:30:33 -0400
commit0791e98dd1cd1833547f814188b25b6c8c711ad5 (patch)
tree7a55a18a4d10d1f8565be7399381f543362cbb32 /arch
parentedb34a4dbdfec6fd83fe907dbf4498eedc77e17e (diff)
parent141d55e6cc590293ea1378f55b9ebd38f5024bf0 (diff)
Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/irq: Standardize on CONFIG_SPARSE_IRQ=y x86, ioapic: Clean up ioapic/apic_id usage x86, ioapic: Factor out print_IO_APIC() to only print one io apic x86, ioapic: Print out irte with right ioapic index x86, ioapic: Split up setup_ioapic_entry() x86, ioapic: Pass struct irq_attr * to setup_ioapic_irq() apic, i386/bigsmp: Fix false warnings regarding logical APIC ID mismatches
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/Kconfig1
-rw-r--r--arch/x86/include/asm/apic.h2
-rw-r--r--arch/x86/include/asm/irq_vectors.h12
-rw-r--r--arch/x86/kernel/apic/bigsmp_32.c20
-rw-r--r--arch/x86/kernel/apic/io_apic.c394
-rw-r--r--arch/x86/kernel/apic/probe_32.c10
6 files changed, 219 insertions, 220 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e022f82cd0d..f49767716c7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -64,6 +64,7 @@ config X86
64 select HAVE_TEXT_POKE_SMP 64 select HAVE_TEXT_POKE_SMP
65 select HAVE_GENERIC_HARDIRQS 65 select HAVE_GENERIC_HARDIRQS
66 select HAVE_SPARSE_IRQ 66 select HAVE_SPARSE_IRQ
67 select SPARSE_IRQ
67 select GENERIC_FIND_FIRST_BIT 68 select GENERIC_FIND_FIRST_BIT
68 select GENERIC_IRQ_PROBE 69 select GENERIC_IRQ_PROBE
69 select GENERIC_PENDING_IRQ if SMP 70 select GENERIC_PENDING_IRQ if SMP
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 7b3ca8324b6..9b7273cb219 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -495,7 +495,7 @@ static inline void default_wait_for_init_deassert(atomic_t *deassert)
495 return; 495 return;
496} 496}
497 497
498extern struct apic *generic_bigsmp_probe(void); 498extern void generic_bigsmp_probe(void);
499 499
500 500
501#ifdef CONFIG_X86_LOCAL_APIC 501#ifdef CONFIG_X86_LOCAL_APIC
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 7e50f06393a..4b4448761e8 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -160,19 +160,11 @@ static inline int invalid_vm86_irq(int irq)
160#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 160#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS )
161 161
162#ifdef CONFIG_X86_IO_APIC 162#ifdef CONFIG_X86_IO_APIC
163# ifdef CONFIG_SPARSE_IRQ 163# define CPU_VECTOR_LIMIT (64 * NR_CPUS)
164# define CPU_VECTOR_LIMIT (64 * NR_CPUS) 164# define NR_IRQS \
165# define NR_IRQS \
166 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 165 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
167 (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 166 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
168 (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 167 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
169# else
170# define CPU_VECTOR_LIMIT (32 * NR_CPUS)
171# define NR_IRQS \
172 (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \
173 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
174 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
175# endif
176#else /* !CONFIG_X86_IO_APIC: */ 168#else /* !CONFIG_X86_IO_APIC: */
177# define NR_IRQS NR_IRQS_LEGACY 169# define NR_IRQS NR_IRQS_LEGACY
178#endif 170#endif
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index efd737e827f..521bead0113 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -255,12 +255,24 @@ static struct apic apic_bigsmp = {
255 .x86_32_early_logical_apicid = bigsmp_early_logical_apicid, 255 .x86_32_early_logical_apicid = bigsmp_early_logical_apicid,
256}; 256};
257 257
258struct apic * __init generic_bigsmp_probe(void) 258void __init generic_bigsmp_probe(void)
259{ 259{
260 if (probe_bigsmp()) 260 unsigned int cpu;
261 return &apic_bigsmp;
262 261
263 return NULL; 262 if (!probe_bigsmp())
263 return;
264
265 apic = &apic_bigsmp;
266
267 for_each_possible_cpu(cpu) {
268 if (early_per_cpu(x86_cpu_to_logical_apicid,
269 cpu) == BAD_APICID)
270 continue;
271 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
272 bigsmp_early_logical_apicid(cpu);
273 }
274
275 pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name);
264} 276}
265 277
266apic_driver(apic_bigsmp); 278apic_driver(apic_bigsmp);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 229e19f3eb5..3c31fa98af6 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -92,21 +92,21 @@ static struct ioapic {
92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); 92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
93} ioapics[MAX_IO_APICS]; 93} ioapics[MAX_IO_APICS];
94 94
95#define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver 95#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
96 96
97int mpc_ioapic_id(int id) 97int mpc_ioapic_id(int ioapic_idx)
98{ 98{
99 return ioapics[id].mp_config.apicid; 99 return ioapics[ioapic_idx].mp_config.apicid;
100} 100}
101 101
102unsigned int mpc_ioapic_addr(int id) 102unsigned int mpc_ioapic_addr(int ioapic_idx)
103{ 103{
104 return ioapics[id].mp_config.apicaddr; 104 return ioapics[ioapic_idx].mp_config.apicaddr;
105} 105}
106 106
107struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id) 107struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
108{ 108{
109 return &ioapics[id].gsi_config; 109 return &ioapics[ioapic_idx].gsi_config;
110} 110}
111 111
112int nr_ioapics; 112int nr_ioapics;
@@ -186,11 +186,7 @@ static struct irq_pin_list *alloc_irq_pin_list(int node)
186 186
187 187
188/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ 188/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189#ifdef CONFIG_SPARSE_IRQ
190static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; 189static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
191#else
192static struct irq_cfg irq_cfgx[NR_IRQS];
193#endif
194 190
195int __init arch_early_irq_init(void) 191int __init arch_early_irq_init(void)
196{ 192{
@@ -234,7 +230,6 @@ int __init arch_early_irq_init(void)
234 return 0; 230 return 0;
235} 231}
236 232
237#ifdef CONFIG_SPARSE_IRQ
238static struct irq_cfg *irq_cfg(unsigned int irq) 233static struct irq_cfg *irq_cfg(unsigned int irq)
239{ 234{
240 return irq_get_chip_data(irq); 235 return irq_get_chip_data(irq);
@@ -269,22 +264,6 @@ static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
269 kfree(cfg); 264 kfree(cfg);
270} 265}
271 266
272#else
273
274struct irq_cfg *irq_cfg(unsigned int irq)
275{
276 return irq < nr_irqs ? irq_cfgx + irq : NULL;
277}
278
279static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
280{
281 return irq_cfgx + irq;
282}
283
284static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
285
286#endif
287
288static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) 267static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
289{ 268{
290 int res = irq_alloc_desc_at(at, node); 269 int res = irq_alloc_desc_at(at, node);
@@ -802,13 +781,13 @@ int restore_ioapic_entries(void)
802/* 781/*
803 * Find the IRQ entry number of a certain pin. 782 * Find the IRQ entry number of a certain pin.
804 */ 783 */
805static int find_irq_entry(int apic, int pin, int type) 784static int find_irq_entry(int ioapic_idx, int pin, int type)
806{ 785{
807 int i; 786 int i;
808 787
809 for (i = 0; i < mp_irq_entries; i++) 788 for (i = 0; i < mp_irq_entries; i++)
810 if (mp_irqs[i].irqtype == type && 789 if (mp_irqs[i].irqtype == type &&
811 (mp_irqs[i].dstapic == mpc_ioapic_id(apic) || 790 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
812 mp_irqs[i].dstapic == MP_APIC_ALL) && 791 mp_irqs[i].dstapic == MP_APIC_ALL) &&
813 mp_irqs[i].dstirq == pin) 792 mp_irqs[i].dstirq == pin)
814 return i; 793 return i;
@@ -847,12 +826,13 @@ static int __init find_isa_irq_apic(int irq, int type)
847 (mp_irqs[i].srcbusirq == irq)) 826 (mp_irqs[i].srcbusirq == irq))
848 break; 827 break;
849 } 828 }
829
850 if (i < mp_irq_entries) { 830 if (i < mp_irq_entries) {
851 int apic; 831 int ioapic_idx;
852 for(apic = 0; apic < nr_ioapics; apic++) { 832
853 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic) 833 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
854 return apic; 834 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
855 } 835 return ioapic_idx;
856 } 836 }
857 837
858 return -1; 838 return -1;
@@ -1067,7 +1047,7 @@ static int pin_2_irq(int idx, int apic, int pin)
1067int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, 1047int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1068 struct io_apic_irq_attr *irq_attr) 1048 struct io_apic_irq_attr *irq_attr)
1069{ 1049{
1070 int apic, i, best_guess = -1; 1050 int ioapic_idx, i, best_guess = -1;
1071 1051
1072 apic_printk(APIC_DEBUG, 1052 apic_printk(APIC_DEBUG,
1073 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1053 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
@@ -1080,8 +1060,8 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1080 for (i = 0; i < mp_irq_entries; i++) { 1060 for (i = 0; i < mp_irq_entries; i++) {
1081 int lbus = mp_irqs[i].srcbus; 1061 int lbus = mp_irqs[i].srcbus;
1082 1062
1083 for (apic = 0; apic < nr_ioapics; apic++) 1063 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1084 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic || 1064 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1085 mp_irqs[i].dstapic == MP_APIC_ALL) 1065 mp_irqs[i].dstapic == MP_APIC_ALL)
1086 break; 1066 break;
1087 1067
@@ -1089,13 +1069,13 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1089 !mp_irqs[i].irqtype && 1069 !mp_irqs[i].irqtype &&
1090 (bus == lbus) && 1070 (bus == lbus) &&
1091 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { 1071 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1092 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); 1072 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1093 1073
1094 if (!(apic || IO_APIC_IRQ(irq))) 1074 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1095 continue; 1075 continue;
1096 1076
1097 if (pin == (mp_irqs[i].srcbusirq & 3)) { 1077 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1098 set_io_apic_irq_attr(irq_attr, apic, 1078 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1099 mp_irqs[i].dstirq, 1079 mp_irqs[i].dstirq,
1100 irq_trigger(i), 1080 irq_trigger(i),
1101 irq_polarity(i)); 1081 irq_polarity(i));
@@ -1106,7 +1086,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1106 * best-guess fuzzy result for broken mptables. 1086 * best-guess fuzzy result for broken mptables.
1107 */ 1087 */
1108 if (best_guess < 0) { 1088 if (best_guess < 0) {
1109 set_io_apic_irq_attr(irq_attr, apic, 1089 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1110 mp_irqs[i].dstirq, 1090 mp_irqs[i].dstirq,
1111 irq_trigger(i), 1091 irq_trigger(i),
1112 irq_polarity(i)); 1092 irq_polarity(i));
@@ -1344,77 +1324,100 @@ static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1344 fasteoi ? "fasteoi" : "edge"); 1324 fasteoi ? "fasteoi" : "edge");
1345} 1325}
1346 1326
1347static int setup_ioapic_entry(int apic_id, int irq, 1327
1348 struct IO_APIC_route_entry *entry, 1328static int setup_ir_ioapic_entry(int irq,
1349 unsigned int destination, int trigger, 1329 struct IR_IO_APIC_route_entry *entry,
1350 int polarity, int vector, int pin) 1330 unsigned int destination, int vector,
1331 struct io_apic_irq_attr *attr)
1351{ 1332{
1352 /* 1333 int index;
1353 * add it to the IO-APIC irq-routing table: 1334 struct irte irte;
1354 */ 1335 int ioapic_id = mpc_ioapic_id(attr->ioapic);
1355 memset(entry,0,sizeof(*entry)); 1336 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
1356 1337
1357 if (intr_remapping_enabled) { 1338 if (!iommu) {
1358 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); 1339 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
1359 struct irte irte; 1340 return -ENODEV;
1360 struct IR_IO_APIC_route_entry *ir_entry = 1341 }
1361 (struct IR_IO_APIC_route_entry *) entry;
1362 int index;
1363 1342
1364 if (!iommu) 1343 index = alloc_irte(iommu, irq, 1);
1365 panic("No mapping iommu for ioapic %d\n", apic_id); 1344 if (index < 0) {
1345 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
1346 return -ENOMEM;
1347 }
1366 1348
1367 index = alloc_irte(iommu, irq, 1); 1349 prepare_irte(&irte, vector, destination);
1368 if (index < 0)
1369 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1370 1350
1371 prepare_irte(&irte, vector, destination); 1351 /* Set source-id of interrupt request */
1352 set_ioapic_sid(&irte, ioapic_id);
1372 1353
1373 /* Set source-id of interrupt request */ 1354 modify_irte(irq, &irte);
1374 set_ioapic_sid(&irte, apic_id);
1375 1355
1376 modify_irte(irq, &irte); 1356 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1357 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1358 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1359 "Avail:%X Vector:%02X Dest:%08X "
1360 "SID:%04X SQ:%X SVT:%X)\n",
1361 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1362 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1363 irte.avail, irte.vector, irte.dest_id,
1364 irte.sid, irte.sq, irte.svt);
1365
1366 memset(entry, 0, sizeof(*entry));
1367
1368 entry->index2 = (index >> 15) & 0x1;
1369 entry->zero = 0;
1370 entry->format = 1;
1371 entry->index = (index & 0x7fff);
1372 /*
1373 * IO-APIC RTE will be configured with virtual vector.
1374 * irq handler will do the explicit EOI to the io-apic.
1375 */
1376 entry->vector = attr->ioapic_pin;
1377 entry->mask = 0; /* enable IRQ */
1378 entry->trigger = attr->trigger;
1379 entry->polarity = attr->polarity;
1377 1380
1378 ir_entry->index2 = (index >> 15) & 0x1; 1381 /* Mask level triggered irqs.
1379 ir_entry->zero = 0; 1382 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1380 ir_entry->format = 1; 1383 */
1381 ir_entry->index = (index & 0x7fff); 1384 if (attr->trigger)
1382 /* 1385 entry->mask = 1;
1383 * IO-APIC RTE will be configured with virtual vector. 1386
1384 * irq handler will do the explicit EOI to the io-apic. 1387 return 0;
1385 */ 1388}
1386 ir_entry->vector = pin;
1387
1388 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1389 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1390 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1391 "Avail:%X Vector:%02X Dest:%08X "
1392 "SID:%04X SQ:%X SVT:%X)\n",
1393 apic_id, irte.present, irte.fpd, irte.dst_mode,
1394 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1395 irte.avail, irte.vector, irte.dest_id,
1396 irte.sid, irte.sq, irte.svt);
1397 } else {
1398 entry->delivery_mode = apic->irq_delivery_mode;
1399 entry->dest_mode = apic->irq_dest_mode;
1400 entry->dest = destination;
1401 entry->vector = vector;
1402 }
1403 1389
1404 entry->mask = 0; /* enable IRQ */ 1390static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1405 entry->trigger = trigger; 1391 unsigned int destination, int vector,
1406 entry->polarity = polarity; 1392 struct io_apic_irq_attr *attr)
1393{
1394 if (intr_remapping_enabled)
1395 return setup_ir_ioapic_entry(irq,
1396 (struct IR_IO_APIC_route_entry *)entry,
1397 destination, vector, attr);
1407 1398
1408 /* Mask level triggered irqs. 1399 memset(entry, 0, sizeof(*entry));
1400
1401 entry->delivery_mode = apic->irq_delivery_mode;
1402 entry->dest_mode = apic->irq_dest_mode;
1403 entry->dest = destination;
1404 entry->vector = vector;
1405 entry->mask = 0; /* enable IRQ */
1406 entry->trigger = attr->trigger;
1407 entry->polarity = attr->polarity;
1408
1409 /*
1410 * Mask level triggered irqs.
1409 * Use IRQ_DELAYED_DISABLE for edge triggered irqs. 1411 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1410 */ 1412 */
1411 if (trigger) 1413 if (attr->trigger)
1412 entry->mask = 1; 1414 entry->mask = 1;
1415
1413 return 0; 1416 return 0;
1414} 1417}
1415 1418
1416static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, 1419static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1417 struct irq_cfg *cfg, int trigger, int polarity) 1420 struct io_apic_irq_attr *attr)
1418{ 1421{
1419 struct IO_APIC_route_entry entry; 1422 struct IO_APIC_route_entry entry;
1420 unsigned int dest; 1423 unsigned int dest;
@@ -1437,49 +1440,48 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1437 apic_printk(APIC_VERBOSE,KERN_DEBUG 1440 apic_printk(APIC_VERBOSE,KERN_DEBUG
1438 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " 1441 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1439 "IRQ %d Mode:%i Active:%i Dest:%d)\n", 1442 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1440 apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector, 1443 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1441 irq, trigger, polarity, dest); 1444 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1442
1443 1445
1444 if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry, 1446 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1445 dest, trigger, polarity, cfg->vector, pin)) { 1447 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1446 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", 1448 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1447 mpc_ioapic_id(apic_id), pin);
1448 __clear_irq_vector(irq, cfg); 1449 __clear_irq_vector(irq, cfg);
1450
1449 return; 1451 return;
1450 } 1452 }
1451 1453
1452 ioapic_register_intr(irq, cfg, trigger); 1454 ioapic_register_intr(irq, cfg, attr->trigger);
1453 if (irq < legacy_pic->nr_legacy_irqs) 1455 if (irq < legacy_pic->nr_legacy_irqs)
1454 legacy_pic->mask(irq); 1456 legacy_pic->mask(irq);
1455 1457
1456 ioapic_write_entry(apic_id, pin, entry); 1458 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1457} 1459}
1458 1460
1459static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) 1461static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1460{ 1462{
1461 if (idx != -1) 1463 if (idx != -1)
1462 return false; 1464 return false;
1463 1465
1464 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", 1466 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1465 mpc_ioapic_id(apic_id), pin); 1467 mpc_ioapic_id(ioapic_idx), pin);
1466 return true; 1468 return true;
1467} 1469}
1468 1470
1469static void __init __io_apic_setup_irqs(unsigned int apic_id) 1471static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1470{ 1472{
1471 int idx, node = cpu_to_node(0); 1473 int idx, node = cpu_to_node(0);
1472 struct io_apic_irq_attr attr; 1474 struct io_apic_irq_attr attr;
1473 unsigned int pin, irq; 1475 unsigned int pin, irq;
1474 1476
1475 for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) { 1477 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1476 idx = find_irq_entry(apic_id, pin, mp_INT); 1478 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1477 if (io_apic_pin_not_connected(idx, apic_id, pin)) 1479 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1478 continue; 1480 continue;
1479 1481
1480 irq = pin_2_irq(idx, apic_id, pin); 1482 irq = pin_2_irq(idx, ioapic_idx, pin);
1481 1483
1482 if ((apic_id > 0) && (irq > 16)) 1484 if ((ioapic_idx > 0) && (irq > 16))
1483 continue; 1485 continue;
1484 1486
1485 /* 1487 /*
@@ -1487,10 +1489,10 @@ static void __init __io_apic_setup_irqs(unsigned int apic_id)
1487 * installed and if it returns 1: 1489 * installed and if it returns 1:
1488 */ 1490 */
1489 if (apic->multi_timer_check && 1491 if (apic->multi_timer_check &&
1490 apic->multi_timer_check(apic_id, irq)) 1492 apic->multi_timer_check(ioapic_idx, irq))
1491 continue; 1493 continue;
1492 1494
1493 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), 1495 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1494 irq_polarity(idx)); 1496 irq_polarity(idx));
1495 1497
1496 io_apic_setup_irq_pin(irq, node, &attr); 1498 io_apic_setup_irq_pin(irq, node, &attr);
@@ -1499,12 +1501,12 @@ static void __init __io_apic_setup_irqs(unsigned int apic_id)
1499 1501
1500static void __init setup_IO_APIC_irqs(void) 1502static void __init setup_IO_APIC_irqs(void)
1501{ 1503{
1502 unsigned int apic_id; 1504 unsigned int ioapic_idx;
1503 1505
1504 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); 1506 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1505 1507
1506 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) 1508 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1507 __io_apic_setup_irqs(apic_id); 1509 __io_apic_setup_irqs(ioapic_idx);
1508} 1510}
1509 1511
1510/* 1512/*
@@ -1514,28 +1516,28 @@ static void __init setup_IO_APIC_irqs(void)
1514 */ 1516 */
1515void setup_IO_APIC_irq_extra(u32 gsi) 1517void setup_IO_APIC_irq_extra(u32 gsi)
1516{ 1518{
1517 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); 1519 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1518 struct io_apic_irq_attr attr; 1520 struct io_apic_irq_attr attr;
1519 1521
1520 /* 1522 /*
1521 * Convert 'gsi' to 'ioapic.pin'. 1523 * Convert 'gsi' to 'ioapic.pin'.
1522 */ 1524 */
1523 apic_id = mp_find_ioapic(gsi); 1525 ioapic_idx = mp_find_ioapic(gsi);
1524 if (apic_id < 0) 1526 if (ioapic_idx < 0)
1525 return; 1527 return;
1526 1528
1527 pin = mp_find_ioapic_pin(apic_id, gsi); 1529 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1528 idx = find_irq_entry(apic_id, pin, mp_INT); 1530 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1529 if (idx == -1) 1531 if (idx == -1)
1530 return; 1532 return;
1531 1533
1532 irq = pin_2_irq(idx, apic_id, pin); 1534 irq = pin_2_irq(idx, ioapic_idx, pin);
1533 1535
1534 /* Only handle the non legacy irqs on secondary ioapics */ 1536 /* Only handle the non legacy irqs on secondary ioapics */
1535 if (apic_id == 0 || irq < NR_IRQS_LEGACY) 1537 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1536 return; 1538 return;
1537 1539
1538 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), 1540 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1539 irq_polarity(idx)); 1541 irq_polarity(idx));
1540 1542
1541 io_apic_setup_irq_pin_once(irq, node, &attr); 1543 io_apic_setup_irq_pin_once(irq, node, &attr);
@@ -1544,8 +1546,8 @@ void setup_IO_APIC_irq_extra(u32 gsi)
1544/* 1546/*
1545 * Set up the timer pin, possibly with the 8259A-master behind. 1547 * Set up the timer pin, possibly with the 8259A-master behind.
1546 */ 1548 */
1547static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, 1549static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1548 int vector) 1550 unsigned int pin, int vector)
1549{ 1551{
1550 struct IO_APIC_route_entry entry; 1552 struct IO_APIC_route_entry entry;
1551 1553
@@ -1576,45 +1578,29 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1576 /* 1578 /*
1577 * Add it to the IO-APIC irq-routing table: 1579 * Add it to the IO-APIC irq-routing table:
1578 */ 1580 */
1579 ioapic_write_entry(apic_id, pin, entry); 1581 ioapic_write_entry(ioapic_idx, pin, entry);
1580} 1582}
1581 1583
1582 1584__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1583__apicdebuginit(void) print_IO_APIC(void)
1584{ 1585{
1585 int apic, i; 1586 int i;
1586 union IO_APIC_reg_00 reg_00; 1587 union IO_APIC_reg_00 reg_00;
1587 union IO_APIC_reg_01 reg_01; 1588 union IO_APIC_reg_01 reg_01;
1588 union IO_APIC_reg_02 reg_02; 1589 union IO_APIC_reg_02 reg_02;
1589 union IO_APIC_reg_03 reg_03; 1590 union IO_APIC_reg_03 reg_03;
1590 unsigned long flags; 1591 unsigned long flags;
1591 struct irq_cfg *cfg;
1592 unsigned int irq;
1593
1594 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1595 for (i = 0; i < nr_ioapics; i++)
1596 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1597 mpc_ioapic_id(i), ioapics[i].nr_registers);
1598
1599 /*
1600 * We are a bit conservative about what we expect. We have to
1601 * know about every hardware change ASAP.
1602 */
1603 printk(KERN_INFO "testing the IO APIC.......................\n");
1604
1605 for (apic = 0; apic < nr_ioapics; apic++) {
1606 1592
1607 raw_spin_lock_irqsave(&ioapic_lock, flags); 1593 raw_spin_lock_irqsave(&ioapic_lock, flags);
1608 reg_00.raw = io_apic_read(apic, 0); 1594 reg_00.raw = io_apic_read(ioapic_idx, 0);
1609 reg_01.raw = io_apic_read(apic, 1); 1595 reg_01.raw = io_apic_read(ioapic_idx, 1);
1610 if (reg_01.bits.version >= 0x10) 1596 if (reg_01.bits.version >= 0x10)
1611 reg_02.raw = io_apic_read(apic, 2); 1597 reg_02.raw = io_apic_read(ioapic_idx, 2);
1612 if (reg_01.bits.version >= 0x20) 1598 if (reg_01.bits.version >= 0x20)
1613 reg_03.raw = io_apic_read(apic, 3); 1599 reg_03.raw = io_apic_read(ioapic_idx, 3);
1614 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1600 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1615 1601
1616 printk("\n"); 1602 printk("\n");
1617 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic)); 1603 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1618 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); 1604 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1619 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); 1605 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1620 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1606 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
@@ -1664,7 +1650,7 @@ __apicdebuginit(void) print_IO_APIC(void)
1664 struct IO_APIC_route_entry entry; 1650 struct IO_APIC_route_entry entry;
1665 struct IR_IO_APIC_route_entry *ir_entry; 1651 struct IR_IO_APIC_route_entry *ir_entry;
1666 1652
1667 entry = ioapic_read_entry(apic, i); 1653 entry = ioapic_read_entry(ioapic_idx, i);
1668 ir_entry = (struct IR_IO_APIC_route_entry *) &entry; 1654 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1669 printk(KERN_DEBUG " %02x %04X ", 1655 printk(KERN_DEBUG " %02x %04X ",
1670 i, 1656 i,
@@ -1685,7 +1671,7 @@ __apicdebuginit(void) print_IO_APIC(void)
1685 } else { 1671 } else {
1686 struct IO_APIC_route_entry entry; 1672 struct IO_APIC_route_entry entry;
1687 1673
1688 entry = ioapic_read_entry(apic, i); 1674 entry = ioapic_read_entry(ioapic_idx, i);
1689 printk(KERN_DEBUG " %02x %02X ", 1675 printk(KERN_DEBUG " %02x %02X ",
1690 i, 1676 i,
1691 entry.dest 1677 entry.dest
@@ -1703,7 +1689,28 @@ __apicdebuginit(void) print_IO_APIC(void)
1703 ); 1689 );
1704 } 1690 }
1705 } 1691 }
1706 } 1692}
1693
1694__apicdebuginit(void) print_IO_APICs(void)
1695{
1696 int ioapic_idx;
1697 struct irq_cfg *cfg;
1698 unsigned int irq;
1699
1700 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1701 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1702 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1703 mpc_ioapic_id(ioapic_idx),
1704 ioapics[ioapic_idx].nr_registers);
1705
1706 /*
1707 * We are a bit conservative about what we expect. We have to
1708 * know about every hardware change ASAP.
1709 */
1710 printk(KERN_INFO "testing the IO APIC.......................\n");
1711
1712 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1713 print_IO_APIC(ioapic_idx);
1707 1714
1708 printk(KERN_DEBUG "IRQ to pin mappings:\n"); 1715 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1709 for_each_active_irq(irq) { 1716 for_each_active_irq(irq) {
@@ -1722,8 +1729,6 @@ __apicdebuginit(void) print_IO_APIC(void)
1722 } 1729 }
1723 1730
1724 printk(KERN_INFO ".................................... done.\n"); 1731 printk(KERN_INFO ".................................... done.\n");
1725
1726 return;
1727} 1732}
1728 1733
1729__apicdebuginit(void) print_APIC_field(int base) 1734__apicdebuginit(void) print_APIC_field(int base)
@@ -1917,7 +1922,7 @@ __apicdebuginit(int) print_ICs(void)
1917 return 0; 1922 return 0;
1918 1923
1919 print_local_APICs(show_lapic); 1924 print_local_APICs(show_lapic);
1920 print_IO_APIC(); 1925 print_IO_APICs();
1921 1926
1922 return 0; 1927 return 0;
1923} 1928}
@@ -2042,7 +2047,7 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
2042{ 2047{
2043 union IO_APIC_reg_00 reg_00; 2048 union IO_APIC_reg_00 reg_00;
2044 physid_mask_t phys_id_present_map; 2049 physid_mask_t phys_id_present_map;
2045 int apic_id; 2050 int ioapic_idx;
2046 int i; 2051 int i;
2047 unsigned char old_id; 2052 unsigned char old_id;
2048 unsigned long flags; 2053 unsigned long flags;
@@ -2056,21 +2061,20 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
2056 /* 2061 /*
2057 * Set the IOAPIC ID to the value stored in the MPC table. 2062 * Set the IOAPIC ID to the value stored in the MPC table.
2058 */ 2063 */
2059 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { 2064 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2060
2061 /* Read the register 0 value */ 2065 /* Read the register 0 value */
2062 raw_spin_lock_irqsave(&ioapic_lock, flags); 2066 raw_spin_lock_irqsave(&ioapic_lock, flags);
2063 reg_00.raw = io_apic_read(apic_id, 0); 2067 reg_00.raw = io_apic_read(ioapic_idx, 0);
2064 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2068 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2065 2069
2066 old_id = mpc_ioapic_id(apic_id); 2070 old_id = mpc_ioapic_id(ioapic_idx);
2067 2071
2068 if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) { 2072 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2069 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 2073 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2070 apic_id, mpc_ioapic_id(apic_id)); 2074 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2071 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 2075 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2072 reg_00.bits.ID); 2076 reg_00.bits.ID);
2073 ioapics[apic_id].mp_config.apicid = reg_00.bits.ID; 2077 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2074 } 2078 }
2075 2079
2076 /* 2080 /*
@@ -2079,9 +2083,9 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
2079 * 'stuck on smp_invalidate_needed IPI wait' messages. 2083 * 'stuck on smp_invalidate_needed IPI wait' messages.
2080 */ 2084 */
2081 if (apic->check_apicid_used(&phys_id_present_map, 2085 if (apic->check_apicid_used(&phys_id_present_map,
2082 mpc_ioapic_id(apic_id))) { 2086 mpc_ioapic_id(ioapic_idx))) {
2083 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 2087 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2084 apic_id, mpc_ioapic_id(apic_id)); 2088 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2085 for (i = 0; i < get_physical_broadcast(); i++) 2089 for (i = 0; i < get_physical_broadcast(); i++)
2086 if (!physid_isset(i, phys_id_present_map)) 2090 if (!physid_isset(i, phys_id_present_map))
2087 break; 2091 break;
@@ -2090,14 +2094,14 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
2090 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 2094 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2091 i); 2095 i);
2092 physid_set(i, phys_id_present_map); 2096 physid_set(i, phys_id_present_map);
2093 ioapics[apic_id].mp_config.apicid = i; 2097 ioapics[ioapic_idx].mp_config.apicid = i;
2094 } else { 2098 } else {
2095 physid_mask_t tmp; 2099 physid_mask_t tmp;
2096 apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id), 2100 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2097 &tmp); 2101 &tmp);
2098 apic_printk(APIC_VERBOSE, "Setting %d in the " 2102 apic_printk(APIC_VERBOSE, "Setting %d in the "
2099 "phys_id_present_map\n", 2103 "phys_id_present_map\n",
2100 mpc_ioapic_id(apic_id)); 2104 mpc_ioapic_id(ioapic_idx));
2101 physids_or(phys_id_present_map, phys_id_present_map, tmp); 2105 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2102 } 2106 }
2103 2107
@@ -2105,35 +2109,35 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
2105 * We need to adjust the IRQ routing table 2109 * We need to adjust the IRQ routing table
2106 * if the ID changed. 2110 * if the ID changed.
2107 */ 2111 */
2108 if (old_id != mpc_ioapic_id(apic_id)) 2112 if (old_id != mpc_ioapic_id(ioapic_idx))
2109 for (i = 0; i < mp_irq_entries; i++) 2113 for (i = 0; i < mp_irq_entries; i++)
2110 if (mp_irqs[i].dstapic == old_id) 2114 if (mp_irqs[i].dstapic == old_id)
2111 mp_irqs[i].dstapic 2115 mp_irqs[i].dstapic
2112 = mpc_ioapic_id(apic_id); 2116 = mpc_ioapic_id(ioapic_idx);
2113 2117
2114 /* 2118 /*
2115 * Update the ID register according to the right value 2119 * Update the ID register according to the right value
2116 * from the MPC table if they are different. 2120 * from the MPC table if they are different.
2117 */ 2121 */
2118 if (mpc_ioapic_id(apic_id) == reg_00.bits.ID) 2122 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2119 continue; 2123 continue;
2120 2124
2121 apic_printk(APIC_VERBOSE, KERN_INFO 2125 apic_printk(APIC_VERBOSE, KERN_INFO
2122 "...changing IO-APIC physical APIC ID to %d ...", 2126 "...changing IO-APIC physical APIC ID to %d ...",
2123 mpc_ioapic_id(apic_id)); 2127 mpc_ioapic_id(ioapic_idx));
2124 2128
2125 reg_00.bits.ID = mpc_ioapic_id(apic_id); 2129 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2126 raw_spin_lock_irqsave(&ioapic_lock, flags); 2130 raw_spin_lock_irqsave(&ioapic_lock, flags);
2127 io_apic_write(apic_id, 0, reg_00.raw); 2131 io_apic_write(ioapic_idx, 0, reg_00.raw);
2128 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2132 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2129 2133
2130 /* 2134 /*
2131 * Sanity check 2135 * Sanity check
2132 */ 2136 */
2133 raw_spin_lock_irqsave(&ioapic_lock, flags); 2137 raw_spin_lock_irqsave(&ioapic_lock, flags);
2134 reg_00.raw = io_apic_read(apic_id, 0); 2138 reg_00.raw = io_apic_read(ioapic_idx, 0);
2135 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2139 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2136 if (reg_00.bits.ID != mpc_ioapic_id(apic_id)) 2140 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2137 printk("could not set ID!\n"); 2141 printk("could not set ID!\n");
2138 else 2142 else
2139 apic_printk(APIC_VERBOSE, " ok.\n"); 2143 apic_printk(APIC_VERBOSE, " ok.\n");
@@ -3001,27 +3005,26 @@ static int __init io_apic_bug_finalize(void)
3001 3005
3002late_initcall(io_apic_bug_finalize); 3006late_initcall(io_apic_bug_finalize);
3003 3007
3004static void resume_ioapic_id(int ioapic_id) 3008static void resume_ioapic_id(int ioapic_idx)
3005{ 3009{
3006 unsigned long flags; 3010 unsigned long flags;
3007 union IO_APIC_reg_00 reg_00; 3011 union IO_APIC_reg_00 reg_00;
3008 3012
3009
3010 raw_spin_lock_irqsave(&ioapic_lock, flags); 3013 raw_spin_lock_irqsave(&ioapic_lock, flags);
3011 reg_00.raw = io_apic_read(ioapic_id, 0); 3014 reg_00.raw = io_apic_read(ioapic_idx, 0);
3012 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) { 3015 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3013 reg_00.bits.ID = mpc_ioapic_id(ioapic_id); 3016 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3014 io_apic_write(ioapic_id, 0, reg_00.raw); 3017 io_apic_write(ioapic_idx, 0, reg_00.raw);
3015 } 3018 }
3016 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3019 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3017} 3020}
3018 3021
3019static void ioapic_resume(void) 3022static void ioapic_resume(void)
3020{ 3023{
3021 int ioapic_id; 3024 int ioapic_idx;
3022 3025
3023 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) 3026 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
3024 resume_ioapic_id(ioapic_id); 3027 resume_ioapic_id(ioapic_idx);
3025 3028
3026 restore_ioapic_entries(); 3029 restore_ioapic_entries();
3027} 3030}
@@ -3558,26 +3561,25 @@ io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3558 return -EINVAL; 3561 return -EINVAL;
3559 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); 3562 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3560 if (!ret) 3563 if (!ret)
3561 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, 3564 setup_ioapic_irq(irq, cfg, attr);
3562 attr->trigger, attr->polarity);
3563 return ret; 3565 return ret;
3564} 3566}
3565 3567
3566int io_apic_setup_irq_pin_once(unsigned int irq, int node, 3568int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3567 struct io_apic_irq_attr *attr) 3569 struct io_apic_irq_attr *attr)
3568{ 3570{
3569 unsigned int id = attr->ioapic, pin = attr->ioapic_pin; 3571 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3570 int ret; 3572 int ret;
3571 3573
3572 /* Avoid redundant programming */ 3574 /* Avoid redundant programming */
3573 if (test_bit(pin, ioapics[id].pin_programmed)) { 3575 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3574 pr_debug("Pin %d-%d already programmed\n", 3576 pr_debug("Pin %d-%d already programmed\n",
3575 mpc_ioapic_id(id), pin); 3577 mpc_ioapic_id(ioapic_idx), pin);
3576 return 0; 3578 return 0;
3577 } 3579 }
3578 ret = io_apic_setup_irq_pin(irq, node, attr); 3580 ret = io_apic_setup_irq_pin(irq, node, attr);
3579 if (!ret) 3581 if (!ret)
3580 set_bit(pin, ioapics[id].pin_programmed); 3582 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3581 return ret; 3583 return ret;
3582} 3584}
3583 3585
@@ -3613,7 +3615,6 @@ int get_nr_irqs_gsi(void)
3613 return nr_irqs_gsi; 3615 return nr_irqs_gsi;
3614} 3616}
3615 3617
3616#ifdef CONFIG_SPARSE_IRQ
3617int __init arch_probe_nr_irqs(void) 3618int __init arch_probe_nr_irqs(void)
3618{ 3619{
3619 int nr; 3620 int nr;
@@ -3633,7 +3634,6 @@ int __init arch_probe_nr_irqs(void)
3633 3634
3634 return NR_IRQS_LEGACY; 3635 return NR_IRQS_LEGACY;
3635} 3636}
3636#endif
3637 3637
3638int io_apic_set_pci_routing(struct device *dev, int irq, 3638int io_apic_set_pci_routing(struct device *dev, int irq,
3639 struct io_apic_irq_attr *irq_attr) 3639 struct io_apic_irq_attr *irq_attr)
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index b5254ad044a..0787bb3412f 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -200,14 +200,8 @@ void __init default_setup_apic_routing(void)
200 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support 200 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
201 */ 201 */
202 202
203 if (!cmdline_apic && apic == &apic_default) { 203 if (!cmdline_apic && apic == &apic_default)
204 struct apic *bigsmp = generic_bigsmp_probe(); 204 generic_bigsmp_probe();
205 if (bigsmp) {
206 apic = bigsmp;
207 printk(KERN_INFO "Overriding APIC driver with %s\n",
208 apic->name);
209 }
210 }
211#endif 205#endif
212 206
213 if (apic->setup_apic_routing) 207 if (apic->setup_apic_routing)