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authorTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
committerTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
commit6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0 (patch)
treec9d7fc50a2e2147a5ca07e3096e7eeb916ad2da9 /arch/xtensa/kernel
parent0415b00d175e0d8945e6785aad21b5f157976ce0 (diff)
parent6ea0c34dac89611126455537552cffe6c7e832ad (diff)
Merge branch 'fixes-2.6.39' into for-2.6.40
Diffstat (limited to 'arch/xtensa/kernel')
-rw-r--r--arch/xtensa/kernel/irq.c106
1 files changed, 35 insertions, 71 deletions
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 87508886cbb..d77089df412 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -35,7 +35,6 @@ atomic_t irq_err_count;
35asmlinkage void do_IRQ(int irq, struct pt_regs *regs) 35asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
36{ 36{
37 struct pt_regs *old_regs = set_irq_regs(regs); 37 struct pt_regs *old_regs = set_irq_regs(regs);
38 struct irq_desc *desc = irq_desc + irq;
39 38
40 if (irq >= NR_IRQS) { 39 if (irq >= NR_IRQS) {
41 printk(KERN_EMERG "%s: cannot handle IRQ %d\n", 40 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
@@ -57,104 +56,69 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
57 sp - sizeof(struct thread_info)); 56 sp - sizeof(struct thread_info));
58 } 57 }
59#endif 58#endif
60 desc->handle_irq(irq, desc); 59 generic_handle_irq(irq);
61 60
62 irq_exit(); 61 irq_exit();
63 set_irq_regs(old_regs); 62 set_irq_regs(old_regs);
64} 63}
65 64
66/* 65int arch_show_interrupts(struct seq_file *p, int prec)
67 * Generic, controller-independent functions:
68 */
69
70int show_interrupts(struct seq_file *p, void *v)
71{ 66{
72 int i = *(loff_t *) v, j; 67 int j;
73 struct irqaction * action; 68
74 unsigned long flags; 69 seq_printf(p, "%*s: ", prec, "NMI");
75 70 for_each_online_cpu(j)
76 if (i == 0) { 71 seq_printf(p, "%10u ", nmi_count(j));
77 seq_printf(p, " "); 72 seq_putc(p, '\n');
78 for_each_online_cpu(j) 73 seq_printf(p, "%*s: ", prec, "ERR");
79 seq_printf(p, "CPU%d ",j); 74 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
80 seq_putc(p, '\n');
81 }
82
83 if (i < NR_IRQS) {
84 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
85 action = irq_desc[i].action;
86 if (!action)
87 goto skip;
88 seq_printf(p, "%3d: ",i);
89#ifndef CONFIG_SMP
90 seq_printf(p, "%10u ", kstat_irqs(i));
91#else
92 for_each_online_cpu(j)
93 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
94#endif
95 seq_printf(p, " %14s", irq_desc[i].chip->name);
96 seq_printf(p, " %s", action->name);
97
98 for (action=action->next; action; action = action->next)
99 seq_printf(p, ", %s", action->name);
100
101 seq_putc(p, '\n');
102skip:
103 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
104 } else if (i == NR_IRQS) {
105 seq_printf(p, "NMI: ");
106 for_each_online_cpu(j)
107 seq_printf(p, "%10u ", nmi_count(j));
108 seq_putc(p, '\n');
109 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
110 }
111 return 0; 75 return 0;
112} 76}
113 77
114static void xtensa_irq_mask(unsigned int irq) 78static void xtensa_irq_mask(struct irq_chip *d)
115{ 79{
116 cached_irq_mask &= ~(1 << irq); 80 cached_irq_mask &= ~(1 << d->irq);
117 set_sr (cached_irq_mask, INTENABLE); 81 set_sr (cached_irq_mask, INTENABLE);
118} 82}
119 83
120static void xtensa_irq_unmask(unsigned int irq) 84static void xtensa_irq_unmask(struct irq_chip *d)
121{ 85{
122 cached_irq_mask |= 1 << irq; 86 cached_irq_mask |= 1 << d->irq;
123 set_sr (cached_irq_mask, INTENABLE); 87 set_sr (cached_irq_mask, INTENABLE);
124} 88}
125 89
126static void xtensa_irq_enable(unsigned int irq) 90static void xtensa_irq_enable(struct irq_chip *d)
127{ 91{
128 variant_irq_enable(irq); 92 variant_irq_enable(d->irq);
129 xtensa_irq_unmask(irq); 93 xtensa_irq_unmask(d->irq);
130} 94}
131 95
132static void xtensa_irq_disable(unsigned int irq) 96static void xtensa_irq_disable(struct irq_chip *d)
133{ 97{
134 xtensa_irq_mask(irq); 98 xtensa_irq_mask(d->irq);
135 variant_irq_disable(irq); 99 variant_irq_disable(d->irq);
136} 100}
137 101
138static void xtensa_irq_ack(unsigned int irq) 102static void xtensa_irq_ack(struct irq_chip *d)
139{ 103{
140 set_sr(1 << irq, INTCLEAR); 104 set_sr(1 << d->irq, INTCLEAR);
141} 105}
142 106
143static int xtensa_irq_retrigger(unsigned int irq) 107static int xtensa_irq_retrigger(struct irq_chip *d)
144{ 108{
145 set_sr (1 << irq, INTSET); 109 set_sr (1 << d->irq, INTSET);
146 return 1; 110 return 1;
147} 111}
148 112
149 113
150static struct irq_chip xtensa_irq_chip = { 114static struct irq_chip xtensa_irq_chip = {
151 .name = "xtensa", 115 .name = "xtensa",
152 .enable = xtensa_irq_enable, 116 .irq_enable = xtensa_irq_enable,
153 .disable = xtensa_irq_disable, 117 .irq_disable = xtensa_irq_disable,
154 .mask = xtensa_irq_mask, 118 .irq_mask = xtensa_irq_mask,
155 .unmask = xtensa_irq_unmask, 119 .irq_unmask = xtensa_irq_unmask,
156 .ack = xtensa_irq_ack, 120 .irq_ack = xtensa_irq_ack,
157 .retrigger = xtensa_irq_retrigger, 121 .irq_retrigger = xtensa_irq_retrigger,
158}; 122};
159 123
160void __init init_IRQ(void) 124void __init init_IRQ(void)
@@ -165,25 +129,25 @@ void __init init_IRQ(void)
165 int mask = 1 << index; 129 int mask = 1 << index;
166 130
167 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) 131 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
168 set_irq_chip_and_handler(index, &xtensa_irq_chip, 132 irq_set_chip_and_handler(index, &xtensa_irq_chip,
169 handle_simple_irq); 133 handle_simple_irq);
170 134
171 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) 135 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
172 set_irq_chip_and_handler(index, &xtensa_irq_chip, 136 irq_set_chip_and_handler(index, &xtensa_irq_chip,
173 handle_edge_irq); 137 handle_edge_irq);
174 138
175 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) 139 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
176 set_irq_chip_and_handler(index, &xtensa_irq_chip, 140 irq_set_chip_and_handler(index, &xtensa_irq_chip,
177 handle_level_irq); 141 handle_level_irq);
178 142
179 else if (mask & XCHAL_INTTYPE_MASK_TIMER) 143 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
180 set_irq_chip_and_handler(index, &xtensa_irq_chip, 144 irq_set_chip_and_handler(index, &xtensa_irq_chip,
181 handle_edge_irq); 145 handle_edge_irq);
182 146
183 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 147 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
184 /* XCHAL_INTTYPE_MASK_NMI */ 148 /* XCHAL_INTTYPE_MASK_NMI */
185 149
186 set_irq_chip_and_handler(index, &xtensa_irq_chip, 150 irq_set_chip_and_handler(index, &xtensa_irq_chip,
187 handle_level_irq); 151 handle_level_irq);
188 } 152 }
189 153