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authorThomas Gleixner <tglx@linutronix.de>2009-04-08 06:31:24 -0400
committerH. Peter Anvin <hpa@zytor.com>2009-05-28 12:24:12 -0400
commit01c6680a547a3ee8dd170c269ea8e037b3191b71 (patch)
treed915249ccc33aa6d99d0c1b671a7fbaf219ed4be /arch/x86
parentba2d0f2b0c56d7174a0208f7c463271f39040728 (diff)
x86, mce: Cleanup MCG definitions
Decode more magic constants and turn them into symbols. [ Sort definitions bitwise, introduce MCG_EXT_CNT - HS ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/include/asm/mce.h10
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce.c5
2 files changed, 10 insertions, 5 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index b9972a6bc2a..94aedaf6327 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -8,9 +8,13 @@
8 * Machine Check support for x86 8 * Machine Check support for x86
9 */ 9 */
10 10
11#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ 11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12#define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 12#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
13#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16#define MCG_EXT_CNT_SHIFT 16
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
14 18
15#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 19#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
16#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 20#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 49c74222359..14733362741 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -569,7 +569,8 @@ static int mce_cap_init(void)
569 u64 cap; 569 u64 cap;
570 570
571 rdmsrl(MSR_IA32_MCG_CAP, cap); 571 rdmsrl(MSR_IA32_MCG_CAP, cap);
572 b = cap & 0xff; 572
573 b = cap & MCG_BANKCNT_MASK;
573 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); 574 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
574 575
575 if (b > MAX_NR_BANKS) { 576 if (b > MAX_NR_BANKS) {
@@ -590,7 +591,7 @@ static int mce_cap_init(void)
590 } 591 }
591 592
592 /* Use accurate RIP reporting if available. */ 593 /* Use accurate RIP reporting if available. */
593 if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) 594 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
594 rip_msr = MSR_IA32_MCG_EIP; 595 rip_msr = MSR_IA32_MCG_EIP;
595 596
596 return 0; 597 return 0;