Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (36 commits)
  PCI: hotplug: pciehp: Removed check for hotplug of display devices
  PCI: read memory ranges out of Broadcom CNB20LE host bridge
  PCI: Allow manual resource allocation for PCI hotplug bridges
  x86/PCI: make ACPI MCFG reserved error messages ACPI specific
  PCI hotplug: Use kmemdup
  PM/PCI: Update PCI power management documentation
  PCI: output FW warning in pci_read/write_vpd
  PCI: fix typos pci_device_dis/enable to pci_dis/enable_device in comments
  PCI quirks: disable msi on AMD rs4xx internal gfx bridges
  PCI: Disable MSI for MCP55 on P5N32-E SLI
  x86/PCI: irq and pci_ids patch for additional Intel Cougar Point DeviceIDs
  PCI: aerdrv: trivial cleanup for aerdrv_core.c
  PCI: aerdrv: trivial cleanup for aerdrv.c
  PCI: aerdrv: introduce default_downstream_reset_link
  PCI: aerdrv: rework find_aer_service
  PCI: aerdrv: remove is_downstream
  PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS
  PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC
  PCI: aerdrv: rework do_recovery
  PCI: aerdrv: rework get_e_source()
  ...

9 files changed, 140 insertions, 31 deletions

diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index b110d97fb92..a0207a7fdf3 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_X86_MRST)		+= mrst.o
 obj-y                           += common.o early.o
 obj-y                           += amd_bus.o bus_numa.o
 
+obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o
+
 ifeq ($(CONFIG_PCI_DEBUG),y)
 EXTRA_CFLAGS += -DDEBUG
 endif
diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c
new file mode 100644
index 00000000000..0846a5bbbfb
--- /dev/null
+++ b/arch/x86/pci/broadcom_bus.c
@@ -0,0 +1,101 @@
+/*
+ * Read address ranges from a Broadcom CNB20LE Host Bridge
+ *
+ * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/dmi.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <asm/pci_x86.h>
+
+#include "bus_numa.h"
+
+static void __devinit cnb20le_res(struct pci_dev *dev)
+{
+        struct pci_root_info *info;
+        struct resource res;
+        u16 word1, word2;
+        u8 fbus, lbus;
+        int i;
+
+        /*
+         * The x86_pci_root_bus_res_quirks() function already refuses to use
+         * this information if ACPI _CRS was used. Therefore, we don't bother
+         * checking if ACPI is enabled, and just generate the information
+         * for both the ACPI _CRS and no ACPI cases.
+         */
+
+        info = &pci_root_info[pci_root_num];
+        pci_root_num++;
+
+        /* read the PCI bus numbers */
+        pci_read_config_byte(dev, 0x44, &fbus);
+        pci_read_config_byte(dev, 0x45, &lbus);
+        info->bus_min = fbus;
+        info->bus_max = lbus;
+
+        /*
+         * Add the legacy IDE ports on bus 0
+         *
+         * These do not exist anywhere in the bridge registers, AFAICT. I do
+         * not have the datasheet, so this is the best I can do.
+         */
+        if (fbus == 0) {
+                update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0);
+                update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0);
+                update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0);
+                update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0);
+                update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0);
+        }
+
+        /* read the non-prefetchable memory window */
+        pci_read_config_word(dev, 0xc0, &word1);
+        pci_read_config_word(dev, 0xc2, &word2);
+        if (word1 != word2) {
+                res.start = (word1 << 16) | 0x0000;
+                res.end   = (word2 << 16) | 0xffff;
+                res.flags = IORESOURCE_MEM;
+                update_res(info, res.start, res.end, res.flags, 0);
+        }
+
+        /* read the prefetchable memory window */
+        pci_read_config_word(dev, 0xc4, &word1);
+        pci_read_config_word(dev, 0xc6, &word2);
+        if (word1 != word2) {
+                res.start = (word1 << 16) | 0x0000;
+                res.end   = (word2 << 16) | 0xffff;
+                res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+                update_res(info, res.start, res.end, res.flags, 0);
+        }
+
+        /* read the IO port window */
+        pci_read_config_word(dev, 0xd0, &word1);
+        pci_read_config_word(dev, 0xd2, &word2);
+        if (word1 != word2) {
+                res.start = word1;
+                res.end   = word2;
+                res.flags = IORESOURCE_IO;
+                update_res(info, res.start, res.end, res.flags, 0);
+        }
+
+        /* print information about this host bridge */
+        res.start = fbus;
+        res.end   = lbus;
+        res.flags = IORESOURCE_BUS;
+        dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n",
+                            pci_domain_nr(dev->bus), &res);
+
+        for (i = 0; i < info->res_num; i++)
+                dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
+                        cnb20le_res);
+
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index cf2e93869c4..215a27ae050 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -76,7 +76,7 @@ struct pci_ops pci_root_ops = {
  * This interrupt-safe spinlock protects all accesses to PCI
  * configuration space.
  */
-DEFINE_SPINLOCK(pci_config_lock);
+DEFINE_RAW_SPINLOCK(pci_config_lock);
 
 static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
 {
diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c
index 347d882b3bb..bd33620b007 100644
--- a/arch/x86/pci/direct.c
+++ b/arch/x86/pci/direct.c
@@ -27,7 +27,7 @@ static int pci_conf1_read(unsigned int seg, unsigned int bus,
                 return -EINVAL;
         }
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
 
@@ -43,7 +43,7 @@ static int pci_conf1_read(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
@@ -56,7 +56,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus,
         if ((bus > 255) || (devfn > 255) || (reg > 4095))
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
 
@@ -72,7 +72,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
@@ -108,7 +108,7 @@ static int pci_conf2_read(unsigned int seg, unsigned int bus,
         if (dev & 0x10) 
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         outb((u8)(0xF0 | (fn << 1)), 0xCF8);
         outb((u8)bus, 0xCFA);
@@ -127,7 +127,7 @@ static int pci_conf2_read(unsigned int seg, unsigned int bus,
 
         outb(0, 0xCF8);
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
@@ -147,7 +147,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus,
         if (dev & 0x10) 
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         outb((u8)(0xF0 | (fn << 1)), 0xCF8);
         outb((u8)bus, 0xCFA);
@@ -166,7 +166,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus,
 
         outb(0, 0xCF8);    
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 5d362b5ba06..9810a0f76c9 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -589,8 +589,6 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
         case PCI_DEVICE_ID_INTEL_ICH10_1:
         case PCI_DEVICE_ID_INTEL_ICH10_2:
         case PCI_DEVICE_ID_INTEL_ICH10_3:
-        case PCI_DEVICE_ID_INTEL_CPT_LPC1:
-        case PCI_DEVICE_ID_INTEL_CPT_LPC2:
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
@@ -605,6 +603,13 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
                 return 1;
         }
 
+        if ((device >= PCI_DEVICE_ID_INTEL_CPT_LPC_MIN) && 
+                (device <= PCI_DEVICE_ID_INTEL_CPT_LPC_MAX)) {
+                r->name = "PIIX/ICH";
+                r->get = pirq_piix_get;
+                r->set = pirq_piix_set;
+                return 1;
+        }
         return 0;
 }
 
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 39b9ebe8f88..a918553ebc7 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -483,16 +483,17 @@ static void __init pci_mmcfg_reject_broken(int early)
         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
                 int valid = 0;
 
-                if (!early && !acpi_disabled)
+                if (!early && !acpi_disabled) {
                         valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
 
-                if (valid)
-                        continue;
-
-                if (!early)
-                        printk(KERN_ERR FW_BUG PREFIX
-                               "MMCONFIG at %pR not reserved in "
-                               "ACPI motherboard resources\n", &cfg->res);
+                        if (valid)
+                                continue;
+                        else
+                                printk(KERN_ERR FW_BUG PREFIX
+                                       "MMCONFIG at %pR not reserved in "
+                                       "ACPI motherboard resources\n",
+                                       &cfg->res);
+                }
 
                 /* Don't try to do this check unless configuration
                    type 1 is available. how about type 2 ?*/
diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c
index 90d5fd476ed..a3d9c54792a 100644
--- a/arch/x86/pci/mmconfig_32.c
+++ b/arch/x86/pci/mmconfig_32.c
@@ -64,7 +64,7 @@ err:		*value = -1;
         if (!base)
                 goto err;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         pci_exp_set_dev_base(base, bus, devfn);
 
@@ -79,7 +79,7 @@ err:		*value = -1;
                 *value = mmio_config_readl(mmcfg_virt_addr + reg);
                 break;
         }
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
@@ -97,7 +97,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
         if (!base)
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         pci_exp_set_dev_base(base, bus, devfn);
 
@@ -112,7 +112,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
                 mmio_config_writel(mmcfg_virt_addr + reg, value);
                 break;
         }
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
index 8223738ad80..5c9e2458df4 100644
--- a/arch/x86/pci/numaq_32.c
+++ b/arch/x86/pci/numaq_32.c
@@ -37,7 +37,7 @@ static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
         if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         write_cf8(bus, devfn, reg);
 
@@ -62,7 +62,7 @@ static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
@@ -76,7 +76,7 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
         if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) 
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         write_cf8(bus, devfn, reg);
 
@@ -101,7 +101,7 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return 0;
 }
diff --git a/arch/x86/pci/pcbios.c b/arch/x86/pci/pcbios.c
index 59a225c17b8..2492d165096 100644
--- a/arch/x86/pci/pcbios.c
+++ b/arch/x86/pci/pcbios.c
@@ -162,7 +162,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus,
         if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         switch (len) {
         case 1:
@@ -213,7 +213,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return (int)((result & 0xff00) >> 8);
 }
@@ -228,7 +228,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus,
         if ((bus > 255) || (devfn > 255) || (reg > 255)) 
                 return -EINVAL;
 
-        spin_lock_irqsave(&pci_config_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
 
         switch (len) {
         case 1:
@@ -269,7 +269,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus,
                 break;
         }
 
-        spin_unlock_irqrestore(&pci_config_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         return (int)((result & 0xff00) >> 8);
 }