Patched in Tegra support.

1 files changed, 231 insertions, 3 deletions

diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index b2b94438ff0..9cbb710dc94 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -29,6 +29,8 @@
 #include "op_x86_model.h"
 #include "op_counter.h"
 
+#define NUM_COUNTERS            4
+#define NUM_COUNTERS_F15H       6
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 #define NUM_VIRT_COUNTERS       32
 #else
@@ -68,12 +70,62 @@ static struct ibs_config ibs_config;
 static struct ibs_state ibs_state;
 
 /*
+ * IBS cpuid feature detection
+ */
+
+#define IBS_CPUID_FEATURES              0x8000001b
+
+/*
+ * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
+ * bit 0 is used to indicate the existence of IBS.
+ */
+#define IBS_CAPS_AVAIL                  (1U<<0)
+#define IBS_CAPS_FETCHSAM               (1U<<1)
+#define IBS_CAPS_OPSAM                  (1U<<2)
+#define IBS_CAPS_RDWROPCNT              (1U<<3)
+#define IBS_CAPS_OPCNT                  (1U<<4)
+#define IBS_CAPS_BRNTRGT                (1U<<5)
+#define IBS_CAPS_OPCNTEXT               (1U<<6)
+
+#define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
+                                         | IBS_CAPS_FETCHSAM    \
+                                         | IBS_CAPS_OPSAM)
+
+/*
+ * IBS APIC setup
+ */
+#define IBSCTL                          0x1cc
+#define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
+#define IBSCTL_LVT_OFFSET_MASK          0x0F
+
+/*
  * IBS randomization macros
  */
 #define IBS_RANDOM_BITS                 12
 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
 
+static u32 get_ibs_caps(void)
+{
+        u32 ibs_caps;
+        unsigned int max_level;
+
+        if (!boot_cpu_has(X86_FEATURE_IBS))
+                return 0;
+
+        /* check IBS cpuid feature flags */
+        max_level = cpuid_eax(0x80000000);
+        if (max_level < IBS_CPUID_FEATURES)
+                return IBS_CAPS_DEFAULT;
+
+        ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
+        if (!(ibs_caps & IBS_CAPS_AVAIL))
+                /* cpuid flags not valid */
+                return IBS_CAPS_DEFAULT;
+
+        return ibs_caps;
+}
+
 /*
  * 16-bit Linear Feedback Shift Register (LFSR)
  *
@@ -264,6 +316,81 @@ static void op_amd_stop_ibs(void)
                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
 
+static inline int get_eilvt(int offset)
+{
+        return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
+}
+
+static inline int put_eilvt(int offset)
+{
+        return !setup_APIC_eilvt(offset, 0, 0, 1);
+}
+
+static inline int ibs_eilvt_valid(void)
+{
+        int offset;
+        u64 val;
+        int valid = 0;
+
+        preempt_disable();
+
+        rdmsrl(MSR_AMD64_IBSCTL, val);
+        offset = val & IBSCTL_LVT_OFFSET_MASK;
+
+        if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
+                pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
+                       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
+                goto out;
+        }
+
+        if (!get_eilvt(offset)) {
+                pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
+                       smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
+                goto out;
+        }
+
+        valid = 1;
+out:
+        preempt_enable();
+
+        return valid;
+}
+
+static inline int get_ibs_offset(void)
+{
+        u64 val;
+
+        rdmsrl(MSR_AMD64_IBSCTL, val);
+        if (!(val & IBSCTL_LVT_OFFSET_VALID))
+                return -EINVAL;
+
+        return val & IBSCTL_LVT_OFFSET_MASK;
+}
+
+static void setup_APIC_ibs(void)
+{
+        int offset;
+
+        offset = get_ibs_offset();
+        if (offset < 0)
+                goto failed;
+
+        if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
+                return;
+failed:
+        pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
+                smp_processor_id());
+}
+
+static void clear_APIC_ibs(void)
+{
+        int offset;
+
+        offset = get_ibs_offset();
+        if (offset >= 0)
+                setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
+}
+
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 
 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
@@ -312,7 +439,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
                         goto fail;
                 }
                 /* both registers must be reserved */
-                if (num_counters == AMD64_NUM_COUNTERS_CORE) {
+                if (num_counters == NUM_COUNTERS_F15H) {
                         msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
                         msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
                 } else {
@@ -377,6 +504,15 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
                 wrmsrl(msrs->controls[i].addr, val);
         }
+
+        if (ibs_caps)
+                setup_APIC_ibs();
+}
+
+static void op_amd_cpu_shutdown(void)
+{
+        if (ibs_caps)
+                clear_APIC_ibs();
 }
 
 static int op_amd_check_ctrs(struct pt_regs * const regs,
@@ -439,6 +575,86 @@ static void op_amd_stop(struct op_msrs const * const msrs)
         op_amd_stop_ibs();
 }
 
+static int setup_ibs_ctl(int ibs_eilvt_off)
+{
+        struct pci_dev *cpu_cfg;
+        int nodes;
+        u32 value = 0;
+
+        nodes = 0;
+        cpu_cfg = NULL;
+        do {
+                cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
+                                         PCI_DEVICE_ID_AMD_10H_NB_MISC,
+                                         cpu_cfg);
+                if (!cpu_cfg)
+                        break;
+                ++nodes;
+                pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
+                                       | IBSCTL_LVT_OFFSET_VALID);
+                pci_read_config_dword(cpu_cfg, IBSCTL, &value);
+                if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
+                        pci_dev_put(cpu_cfg);
+                        printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
+                               "IBSCTL = 0x%08x\n", value);
+                        return -EINVAL;
+                }
+        } while (1);
+
+        if (!nodes) {
+                printk(KERN_DEBUG "No CPU node configured for IBS\n");
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+/*
+ * This runs only on the current cpu. We try to find an LVT offset and
+ * setup the local APIC. For this we must disable preemption. On
+ * success we initialize all nodes with this offset. This updates then
+ * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
+ * the IBS interrupt vector is called from op_amd_setup_ctrs()/op_-
+ * amd_cpu_shutdown() using the new offset.
+ */
+static int force_ibs_eilvt_setup(void)
+{
+        int offset;
+        int ret;
+
+        preempt_disable();
+        /* find the next free available EILVT entry, skip offset 0 */
+        for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
+                if (get_eilvt(offset))
+                        break;
+        }
+        preempt_enable();
+
+        if (offset == APIC_EILVT_NR_MAX) {
+                printk(KERN_DEBUG "No EILVT entry available\n");
+                return -EBUSY;
+        }
+
+        ret = setup_ibs_ctl(offset);
+        if (ret)
+                goto out;
+
+        if (!ibs_eilvt_valid()) {
+                ret = -EFAULT;
+                goto out;
+        }
+
+        pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
+        pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
+
+        return 0;
+out:
+        preempt_disable();
+        put_eilvt(offset);
+        preempt_enable();
+        return ret;
+}
+
 /*
  * check and reserve APIC extended interrupt LVT offset for IBS if
  * available
@@ -451,6 +667,17 @@ static void init_ibs(void)
         if (!ibs_caps)
                 return;
 
+        if (ibs_eilvt_valid())
+                goto out;
+
+        if (!force_ibs_eilvt_setup())
+                goto out;
+
+        /* Failed to setup ibs */
+        ibs_caps = 0;
+        return;
+
+out:
         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
 }
 
@@ -514,9 +741,9 @@ static int op_amd_init(struct oprofile_operations *ops)
         ops->create_files = setup_ibs_files;
 
         if (boot_cpu_data.x86 == 0x15) {
-                num_counters = AMD64_NUM_COUNTERS_CORE;
+                num_counters = NUM_COUNTERS_F15H;
         } else {
-                num_counters = AMD64_NUM_COUNTERS;
+                num_counters = NUM_COUNTERS;
         }
 
         op_amd_spec.num_counters = num_counters;
@@ -533,6 +760,7 @@ struct op_x86_model_spec op_amd_spec = {
         .init                   = op_amd_init,
         .fill_in_addresses      = &op_amd_fill_in_addresses,
         .setup_ctrs             = &op_amd_setup_ctrs,
+        .cpu_down               = &op_amd_cpu_shutdown,
         .check_ctrs             = &op_amd_check_ctrs,
         .start                  = &op_amd_start,
         .stop                   = &op_amd_stop,