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authorBorislav Petkov <borislav.petkov@amd.com>2010-04-22 10:06:58 -0400
committerH. Peter Anvin <hpa@zytor.com>2010-04-22 20:17:20 -0400
commitb1ab1b4d9ab9812c77843abec79030292ef0a544 (patch)
treee0405fa695565e9cc6b3510a70168bd10bbd8f3c /arch/x86/kernel/cpu
parent6dad2a29646ce3792c40cfc52d77e9b65a7bb143 (diff)
x86, cacheinfo: Unify AMD L3 cache index disable checking
All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3 cache index disable. Concentrate the family, model, stepping checking at one place and enable the feature implicitly on upcoming Fam10h models. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/intel_cacheinfo.c17
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b3eeb66c0a5..acfb0838390 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -328,18 +328,22 @@ static unsigned int __cpuinit amd_calc_l3_indices(void)
328static void __cpuinit 328static void __cpuinit
329amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf) 329amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
330{ 330{
331 if (index < 3) 331 if (boot_cpu_data.x86 != 0x10)
332 return; 332 return;
333 333
334 if (boot_cpu_data.x86 == 0x11) 334 if (index < 3)
335 return; 335 return;
336 336
337 /* see errata #382 and #388 */ 337 /* see errata #382 and #388 */
338 if ((boot_cpu_data.x86 == 0x10) && 338 if (boot_cpu_data.x86_model < 0x8)
339 ((boot_cpu_data.x86_model < 0x8) ||
340 (boot_cpu_data.x86_mask < 0x1)))
341 return; 339 return;
342 340
341 if ((boot_cpu_data.x86_model == 0x8 ||
342 boot_cpu_data.x86_model == 0x9)
343 &&
344 boot_cpu_data.x86_mask < 0x1)
345 return;
346
343 this_leaf->can_disable = true; 347 this_leaf->can_disable = true;
344 this_leaf->l3_indices = amd_calc_l3_indices(); 348 this_leaf->l3_indices = amd_calc_l3_indices();
345} 349}
@@ -443,8 +447,7 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
443 447
444 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { 448 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
445 amd_cpuid4(index, &eax, &ebx, &ecx); 449 amd_cpuid4(index, &eax, &ebx, &ecx);
446 if (boot_cpu_data.x86 >= 0x10) 450 amd_check_l3_disable(index, this_leaf);
447 amd_check_l3_disable(index, this_leaf);
448 } else { 451 } else {
449 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); 452 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
450 } 453 }