Patched in Tegra support.

1 files changed, 155 insertions, 671 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 93b9e1181f8..f88af2c2a56 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1,36 +1,29 @@
+#ifdef CONFIG_CPU_SUP_INTEL
+
 /*
  * Per core/cpu state
  *
  * Used to coordinate shared registers between HT threads or
  * among events on a single PMU.
  */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/stddef.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-
-#include <asm/hardirq.h>
-#include <asm/apic.h>
-
-#include "perf_event.h"
+struct intel_shared_regs {
+        struct er_account       regs[EXTRA_REG_MAX];
+        int                     refcnt;         /* per-core: #HT threads */
+        unsigned                core_id;        /* per-core: core id */
+};
 
 /*
  * Intel PerfMon, used on Core and later.
  */
 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
 {
-        [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
-        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
-        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
-        [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
-        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
-        [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
-        [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
+  [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
+  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
+  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
+  [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
+  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
+  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
+  [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
 };
 
 static struct event_constraint intel_core_event_constraints[] __read_mostly =
@@ -48,7 +41,12 @@ static struct event_constraint intel_core2_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        /*
+         * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
+         * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
+         * ratio between these counters.
+         */
+        /* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
@@ -66,7 +64,7 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
@@ -88,7 +86,7 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
@@ -100,7 +98,7 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -123,7 +121,7 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
         EVENT_CONSTRAINT_END
 };
 
@@ -138,84 +136,6 @@ static u64 intel_pmu_event_map(int hw_event)
         return intel_perfmon_event_map[hw_event];
 }
 
-#define SNB_DMND_DATA_RD        (1ULL << 0)
-#define SNB_DMND_RFO            (1ULL << 1)
-#define SNB_DMND_IFETCH         (1ULL << 2)
-#define SNB_DMND_WB             (1ULL << 3)
-#define SNB_PF_DATA_RD          (1ULL << 4)
-#define SNB_PF_RFO              (1ULL << 5)
-#define SNB_PF_IFETCH           (1ULL << 6)
-#define SNB_LLC_DATA_RD         (1ULL << 7)
-#define SNB_LLC_RFO             (1ULL << 8)
-#define SNB_LLC_IFETCH          (1ULL << 9)
-#define SNB_BUS_LOCKS           (1ULL << 10)
-#define SNB_STRM_ST             (1ULL << 11)
-#define SNB_OTHER               (1ULL << 15)
-#define SNB_RESP_ANY            (1ULL << 16)
-#define SNB_NO_SUPP             (1ULL << 17)
-#define SNB_LLC_HITM            (1ULL << 18)
-#define SNB_LLC_HITE            (1ULL << 19)
-#define SNB_LLC_HITS            (1ULL << 20)
-#define SNB_LLC_HITF            (1ULL << 21)
-#define SNB_LOCAL               (1ULL << 22)
-#define SNB_REMOTE              (0xffULL << 23)
-#define SNB_SNP_NONE            (1ULL << 31)
-#define SNB_SNP_NOT_NEEDED      (1ULL << 32)
-#define SNB_SNP_MISS            (1ULL << 33)
-#define SNB_NO_FWD              (1ULL << 34)
-#define SNB_SNP_FWD             (1ULL << 35)
-#define SNB_HITM                (1ULL << 36)
-#define SNB_NON_DRAM            (1ULL << 37)
-
-#define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
-#define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
-#define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
-
-#define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
-                                 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
-                                 SNB_HITM)
-
-#define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
-#define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
-
-#define SNB_L3_ACCESS           SNB_RESP_ANY
-#define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
-
-static __initconst const u64 snb_hw_cache_extra_regs
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
-                [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
-                [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
-                [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
-        },
- },
- [ C(NODE) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
-                [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
-                [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
-                [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
-        },
- },
-};
-
 static __initconst const u64 snb_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -313,16 +233,16 @@ static __initconst const u64 snb_hw_cache_event_ids
  },
  [ C(NODE) ] = {
         [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x01b7,
-                [ C(RESULT_MISS)   ] = 0x01b7,
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
         },
         [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x01b7,
-                [ C(RESULT_MISS)   ] = 0x01b7,
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
         },
         [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x01b7,
-                [ C(RESULT_MISS)   ] = 0x01b7,
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
         },
  },
 
@@ -465,15 +385,14 @@ static __initconst const u64 westmere_hw_cache_event_ids
 #define NHM_LOCAL_DRAM          (1 << 14)
 #define NHM_NON_DRAM            (1 << 15)
 
-#define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
-#define NHM_REMOTE              (NHM_REMOTE_DRAM)
+#define NHM_ALL_DRAM            (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
 
 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 
 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
-#define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
+#define NHM_L3_MISS     (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 
 static __initconst const u64 nehalem_hw_cache_extra_regs
@@ -497,16 +416,16 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
  },
  [ C(NODE) ] = {
         [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
-                [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
+                [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
         },
         [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
-                [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
+                [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
         },
         [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
-                [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
+                [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
+                [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
         },
  },
 };
@@ -808,26 +727,13 @@ static __initconst const u64 atom_hw_cache_event_ids
  },
 };
 
-static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
-{
-        /* user explicitly requested branch sampling */
-        if (has_branch_stack(event))
-                return true;
-
-        /* implicit branch sampling to correct PEBS skid */
-        if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
-                return true;
-
-        return false;
-}
-
 static void intel_pmu_disable_all(void)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 
-        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
                 intel_pmu_disable_bts();
 
         intel_pmu_pebs_disable_all();
@@ -840,12 +746,11 @@ static void intel_pmu_enable_all(int added)
 
         intel_pmu_pebs_enable_all();
         intel_pmu_lbr_enable_all();
-        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
-                        x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
+        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 
-        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
                 struct perf_event *event =
-                        cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
+                        cpuc->events[X86_PMC_IDX_FIXED_BTS];
 
                 if (WARN_ON_ONCE(!event))
                         return;
@@ -951,7 +856,7 @@ static inline void intel_pmu_ack_status(u64 ack)
 
 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
+        int idx = hwc->idx - X86_PMC_IDX_FIXED;
         u64 ctrl_val, mask;
 
         mask = 0xfULL << (idx * 4);
@@ -964,24 +869,13 @@ static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 static void intel_pmu_disable_event(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
                 intel_pmu_disable_bts();
                 intel_pmu_drain_bts_buffer();
                 return;
         }
 
-        cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
-        cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
-
-        /*
-         * must disable before any actual event
-         * because any event may be combined with LBR
-         */
-        if (intel_pmu_needs_lbr_smpl(event))
-                intel_pmu_lbr_disable(event);
-
         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                 intel_pmu_disable_fixed(hwc);
                 return;
@@ -995,7 +889,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
 
 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
+        int idx = hwc->idx - X86_PMC_IDX_FIXED;
         u64 ctrl_val, bits, mask;
 
         /*
@@ -1027,26 +921,14 @@ static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 static void intel_pmu_enable_event(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
                 if (!__this_cpu_read(cpu_hw_events.enabled))
                         return;
 
                 intel_pmu_enable_bts(hwc->config);
                 return;
         }
-        /*
-         * must enabled before any actual event
-         * because any event may be combined with LBR
-         */
-        if (intel_pmu_needs_lbr_smpl(event))
-                intel_pmu_lbr_enable(event);
-
-        if (event->attr.exclude_host)
-                cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
-        if (event->attr.exclude_guest)
-                cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
 
         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                 intel_pmu_enable_fixed(hwc);
@@ -1063,7 +945,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
  * Save and restart an expired event. Called by NMI contexts,
  * so it has to be careful about preempting normal event ops:
  */
-int intel_pmu_save_and_restart(struct perf_event *event)
+static int intel_pmu_save_and_restart(struct perf_event *event)
 {
         x86_perf_event_update(event);
         return x86_perf_event_set_period(event);
@@ -1080,14 +962,14 @@ static void intel_pmu_reset(void)
 
         local_irq_save(flags);
 
-        pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
+        printk("clearing PMU state on CPU#%d\n", smp_processor_id());
 
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
-                wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
-                wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
+                checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
+                checking_wrmsrl(x86_pmu_event_addr(idx),  0ull);
         }
         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
-                wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
+                checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
 
         if (ds)
                 ds->bts_index = ds->bts_buffer_base;
@@ -1107,6 +989,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         u64 status;
         int handled;
 
+        perf_sample_data_init(&data, 0);
+
         cpuc = &__get_cpu_var(cpu_hw_events);
 
         /*
@@ -1160,10 +1044,7 @@ again:
                 if (!intel_pmu_save_and_restart(event))
                         continue;
 
-                perf_sample_data_init(&data, 0, event->hw.last_period);
-
-                if (has_branch_stack(event))
-                        data.br_stack = &cpuc->lbr_stack;
+                data.period = event->hw.last_period;
 
                 if (perf_event_overflow(event, &data, regs))
                         x86_pmu_stop(event, 0);
@@ -1199,33 +1080,27 @@ intel_bts_constraints(struct perf_event *event)
         return NULL;
 }
 
-static int intel_alt_er(int idx)
+static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
 {
         if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
-                return idx;
-
-        if (idx == EXTRA_REG_RSP_0)
-                return EXTRA_REG_RSP_1;
+                return false;
 
-        if (idx == EXTRA_REG_RSP_1)
-                return EXTRA_REG_RSP_0;
-
-        return idx;
-}
-
-static void intel_fixup_er(struct perf_event *event, int idx)
-{
-        event->hw.extra_reg.idx = idx;
-
-        if (idx == EXTRA_REG_RSP_0) {
-                event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
-                event->hw.config |= 0x01b7;
-                event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
-        } else if (idx == EXTRA_REG_RSP_1) {
+        if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
                 event->hw.config |= 0x01bb;
+                event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
+        } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
+                event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
+                event->hw.config |= 0x01b7;
+                event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
+                event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
         }
+
+        if (event->hw.extra_reg.idx == orig_idx)
+                return false;
+
+        return true;
 }
 
 /*
@@ -1237,24 +1112,20 @@ static void intel_fixup_er(struct perf_event *event, int idx)
  */
 static struct event_constraint *
 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
-                                   struct perf_event *event,
-                                   struct hw_perf_event_extra *reg)
+                                   struct perf_event *event)
 {
         struct event_constraint *c = &emptyconstraint;
+        struct hw_perf_event_extra *reg = &event->hw.extra_reg;
         struct er_account *era;
         unsigned long flags;
-        int idx = reg->idx;
+        int orig_idx = reg->idx;
 
-        /*
-         * reg->alloc can be set due to existing state, so for fake cpuc we
-         * need to ignore this, otherwise we might fail to allocate proper fake
-         * state for this extra reg constraint. Also see the comment below.
-         */
-        if (reg->alloc && !cpuc->is_fake)
-                return NULL; /* call x86_get_event_constraint() */
+        /* already allocated shared msr */
+        if (reg->alloc)
+                return &unconstrained;
 
 again:
-        era = &cpuc->shared_regs->regs[idx];
+        era = &cpuc->shared_regs->regs[reg->idx];
         /*
          * we use spin_lock_irqsave() to avoid lockdep issues when
          * passing a fake cpuc
@@ -1263,29 +1134,6 @@ again:
 
         if (!atomic_read(&era->ref) || era->config == reg->config) {
 
-                /*
-                 * If its a fake cpuc -- as per validate_{group,event}() we
-                 * shouldn't touch event state and we can avoid doing so
-                 * since both will only call get_event_constraints() once
-                 * on each event, this avoids the need for reg->alloc.
-                 *
-                 * Not doing the ER fixup will only result in era->reg being
-                 * wrong, but since we won't actually try and program hardware
-                 * this isn't a problem either.
-                 */
-                if (!cpuc->is_fake) {
-                        if (idx != reg->idx)
-                                intel_fixup_er(event, idx);
-
-                        /*
-                         * x86_schedule_events() can call get_event_constraints()
-                         * multiple times on events in the case of incremental
-                         * scheduling(). reg->alloc ensures we only do the ER
-                         * allocation once.
-                         */
-                        reg->alloc = 1;
-                }
-
                 /* lock in msr value */
                 era->config = reg->config;
                 era->reg = reg->reg;
@@ -1293,17 +1141,21 @@ again:
                 /* one more user */
                 atomic_inc(&era->ref);
 
+                /* no need to reallocate during incremental event scheduling */
+                reg->alloc = 1;
+
                 /*
-                 * need to call x86_get_event_constraint()
-                 * to check if associated event has constraints
+                 * All events using extra_reg are unconstrained.
+                 * Avoids calling x86_get_event_constraints()
+                 *
+                 * Must revisit if extra_reg controlling events
+                 * ever have constraints. Worst case we go through
+                 * the regular event constraint table.
                  */
-                c = NULL;
-        } else {
-                idx = intel_alt_er(idx);
-                if (idx != reg->idx) {
-                        raw_spin_unlock_irqrestore(&era->lock, flags);
-                        goto again;
-                }
+                c = &unconstrained;
+        } else if (intel_try_alt_er(event, orig_idx)) {
+                raw_spin_unlock(&era->lock);
+                goto again;
         }
         raw_spin_unlock_irqrestore(&era->lock, flags);
 
@@ -1317,14 +1169,11 @@ __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
         struct er_account *era;
 
         /*
-         * Only put constraint if extra reg was actually allocated. Also takes
-         * care of event which do not use an extra shared reg.
-         *
-         * Also, if this is a fake cpuc we shouldn't touch any event state
-         * (reg->alloc) and we don't care about leaving inconsistent cpuc state
-         * either since it'll be thrown out.
+         * only put constraint if extra reg was actually
+         * allocated. Also takes care of event which do
+         * not use an extra shared reg
          */
-        if (!reg->alloc || cpuc->is_fake)
+        if (!reg->alloc)
                 return;
 
         era = &cpuc->shared_regs->regs[reg->idx];
@@ -1340,39 +1189,12 @@ static struct event_constraint *
 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
                               struct perf_event *event)
 {
-        struct event_constraint *c = NULL, *d;
-        struct hw_perf_event_extra *xreg, *breg;
-
-        xreg = &event->hw.extra_reg;
-        if (xreg->idx != EXTRA_REG_NONE) {
-                c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
-                if (c == &emptyconstraint)
-                        return c;
-        }
-        breg = &event->hw.branch_reg;
-        if (breg->idx != EXTRA_REG_NONE) {
-                d = __intel_shared_reg_get_constraints(cpuc, event, breg);
-                if (d == &emptyconstraint) {
-                        __intel_shared_reg_put_constraints(cpuc, xreg);
-                        c = d;
-                }
-        }
-        return c;
-}
+        struct event_constraint *c = NULL;
 
-struct event_constraint *
-x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
-{
-        struct event_constraint *c;
+        if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
+                c = __intel_shared_reg_get_constraints(cpuc, event);
 
-        if (x86_pmu.event_constraints) {
-                for_each_event_constraint(c, x86_pmu.event_constraints) {
-                        if ((event->hw.config & c->cmask) == c->code)
-                                return c;
-                }
-        }
-
-        return &unconstrained;
+        return c;
 }
 
 static struct event_constraint *
@@ -1404,10 +1226,6 @@ intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
         reg = &event->hw.extra_reg;
         if (reg->idx != EXTRA_REG_NONE)
                 __intel_shared_reg_put_constraints(cpuc, reg);
-
-        reg = &event->hw.branch_reg;
-        if (reg->idx != EXTRA_REG_NONE)
-                __intel_shared_reg_put_constraints(cpuc, reg);
 }
 
 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
@@ -1416,9 +1234,15 @@ static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
         intel_put_shared_regs_event_constraints(cpuc, event);
 }
 
-static void intel_pebs_aliases_core2(struct perf_event *event)
+static int intel_pmu_hw_config(struct perf_event *event)
 {
-        if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
+        int ret = x86_pmu_hw_config(event);
+
+        if (ret)
+                return ret;
+
+        if (event->attr.precise_ip &&
+            (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
                 /*
                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
                  * (0x003c) so that we can use it with PEBS.
@@ -1437,56 +1261,11 @@ static void intel_pebs_aliases_core2(struct perf_event *event)
                  *
                  * Thereby we gain a PEBS capable cycle counter.
                  */
-                u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
-
-                alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
-                event->hw.config = alt_config;
-        }
-}
-
-static void intel_pebs_aliases_snb(struct perf_event *event)
-{
-        if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
-                /*
-                 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
-                 * (0x003c) so that we can use it with PEBS.
-                 *
-                 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
-                 * PEBS capable. However we can use UOPS_RETIRED.ALL
-                 * (0x01c2), which is a PEBS capable event, to get the same
-                 * count.
-                 *
-                 * UOPS_RETIRED.ALL counts the number of cycles that retires
-                 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
-                 * larger than the maximum number of micro-ops that can be
-                 * retired per cycle (4) and then inverting the condition, we
-                 * count all cycles that retire 16 or less micro-ops, which
-                 * is every cycle.
-                 *
-                 * Thereby we gain a PEBS capable cycle counter.
-                 */
-                u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
+                u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
 
                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
                 event->hw.config = alt_config;
         }
-}
-
-static int intel_pmu_hw_config(struct perf_event *event)
-{
-        int ret = x86_pmu_hw_config(event);
-
-        if (ret)
-                return ret;
-
-        if (event->attr.precise_ip && x86_pmu.pebs_aliases)
-                x86_pmu.pebs_aliases(event);
-
-        if (intel_pmu_needs_lbr_smpl(event)) {
-                ret = intel_pmu_setup_lbr_filter(event);
-                if (ret)
-                        return ret;
-        }
 
         if (event->attr.type != PERF_TYPE_RAW)
                 return 0;
@@ -1505,117 +1284,12 @@ static int intel_pmu_hw_config(struct perf_event *event)
         return 0;
 }
 
-struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
-{
-        if (x86_pmu.guest_get_msrs)
-                return x86_pmu.guest_get_msrs(nr);
-        *nr = 0;
-        return NULL;
-}
-EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
-
-static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
-
-        arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
-        arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
-        arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
-        /*
-         * If PMU counter has PEBS enabled it is not enough to disable counter
-         * on a guest entry since PEBS memory write can overshoot guest entry
-         * and corrupt guest memory. Disabling PEBS solves the problem.
-         */
-        arr[1].msr = MSR_IA32_PEBS_ENABLE;
-        arr[1].host = cpuc->pebs_enabled;
-        arr[1].guest = 0;
-
-        *nr = 2;
-        return arr;
-}
-
-static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
-        int idx;
-
-        for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
-                struct perf_event *event = cpuc->events[idx];
-
-                arr[idx].msr = x86_pmu_config_addr(idx);
-                arr[idx].host = arr[idx].guest = 0;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                arr[idx].host = arr[idx].guest =
-                        event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
-
-                if (event->attr.exclude_host)
-                        arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
-                else if (event->attr.exclude_guest)
-                        arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
-        }
-
-        *nr = x86_pmu.num_counters;
-        return arr;
-}
-
-static void core_pmu_enable_event(struct perf_event *event)
-{
-        if (!event->attr.exclude_host)
-                x86_pmu_enable_event(event);
-}
-
-static void core_pmu_enable_all(int added)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        int idx;
-
-        for (idx = 0; idx < x86_pmu.num_counters; idx++) {
-                struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
-
-                if (!test_bit(idx, cpuc->active_mask) ||
-                                cpuc->events[idx]->attr.exclude_host)
-                        continue;
-
-                __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
-        }
-}
-
-PMU_FORMAT_ATTR(event,  "config:0-7"    );
-PMU_FORMAT_ATTR(umask,  "config:8-15"   );
-PMU_FORMAT_ATTR(edge,   "config:18"     );
-PMU_FORMAT_ATTR(pc,     "config:19"     );
-PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
-PMU_FORMAT_ATTR(inv,    "config:23"     );
-PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
-
-static struct attribute *intel_arch_formats_attr[] = {
-        &format_attr_event.attr,
-        &format_attr_umask.attr,
-        &format_attr_edge.attr,
-        &format_attr_pc.attr,
-        &format_attr_inv.attr,
-        &format_attr_cmask.attr,
-        NULL,
-};
-
-ssize_t intel_event_sysfs_show(char *page, u64 config)
-{
-        u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
-
-        return x86_event_sysfs_show(page, config, event);
-}
-
 static __initconst const struct x86_pmu core_pmu = {
         .name                   = "core",
         .handle_irq             = x86_pmu_handle_irq,
         .disable_all            = x86_pmu_disable_all,
-        .enable_all             = core_pmu_enable_all,
-        .enable                 = core_pmu_enable_event,
+        .enable_all             = x86_pmu_enable_all,
+        .enable                 = x86_pmu_enable_event,
         .disable                = x86_pmu_disable_event,
         .hw_config              = x86_pmu_hw_config,
         .schedule_events        = x86_schedule_events,
@@ -1633,12 +1307,9 @@ static __initconst const struct x86_pmu core_pmu = {
         .get_event_constraints  = intel_get_event_constraints,
         .put_event_constraints  = intel_put_event_constraints,
         .event_constraints      = intel_core_event_constraints,
-        .guest_get_msrs         = core_guest_get_msrs,
-        .format_attrs           = intel_arch_formats_attr,
-        .events_sysfs_show      = intel_event_sysfs_show,
 };
 
-struct intel_shared_regs *allocate_shared_regs(int cpu)
+static struct intel_shared_regs *allocate_shared_regs(int cpu)
 {
         struct intel_shared_regs *regs;
         int i;
@@ -1661,7 +1332,7 @@ static int intel_pmu_cpu_prepare(int cpu)
 {
         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 
-        if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
+        if (!x86_pmu.extra_regs)
                 return NOTIFY_OK;
 
         cpuc->shared_regs = allocate_shared_regs(cpu);
@@ -1683,28 +1354,22 @@ static void intel_pmu_cpu_starting(int cpu)
          */
         intel_pmu_lbr_reset();
 
-        cpuc->lbr_sel = NULL;
-
-        if (!cpuc->shared_regs)
+        if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
                 return;
 
-        if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
-                for_each_cpu(i, topology_thread_cpumask(cpu)) {
-                        struct intel_shared_regs *pc;
+        for_each_cpu(i, topology_thread_cpumask(cpu)) {
+                struct intel_shared_regs *pc;
 
-                        pc = per_cpu(cpu_hw_events, i).shared_regs;
-                        if (pc && pc->core_id == core_id) {
-                                cpuc->kfree_on_online = cpuc->shared_regs;
-                                cpuc->shared_regs = pc;
-                                break;
-                        }
+                pc = per_cpu(cpu_hw_events, i).shared_regs;
+                if (pc && pc->core_id == core_id) {
+                        kfree(cpuc->shared_regs);
+                        cpuc->shared_regs = pc;
+                        break;
                 }
-                cpuc->shared_regs->core_id = core_id;
-                cpuc->shared_regs->refcnt++;
         }
 
-        if (x86_pmu.lbr_sel_map)
-                cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
+        cpuc->shared_regs->core_id = core_id;
+        cpuc->shared_regs->refcnt++;
 }
 
 static void intel_pmu_cpu_dying(int cpu)
@@ -1722,33 +1387,6 @@ static void intel_pmu_cpu_dying(int cpu)
         fini_debug_store_on_cpu(cpu);
 }
 
-static void intel_pmu_flush_branch_stack(void)
-{
-        /*
-         * Intel LBR does not tag entries with the
-         * PID of the current task, then we need to
-         * flush it on ctxsw
-         * For now, we simply reset it
-         */
-        if (x86_pmu.lbr_nr)
-                intel_pmu_lbr_reset();
-}
-
-PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
-
-static struct attribute *intel_arch3_formats_attr[] = {
-        &format_attr_event.attr,
-        &format_attr_umask.attr,
-        &format_attr_edge.attr,
-        &format_attr_pc.attr,
-        &format_attr_any.attr,
-        &format_attr_inv.attr,
-        &format_attr_cmask.attr,
-
-        &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
-        NULL,
-};
-
 static __initconst const struct x86_pmu intel_pmu = {
         .name                   = "Intel",
         .handle_irq             = intel_pmu_handle_irq,
@@ -1771,19 +1409,13 @@ static __initconst const struct x86_pmu intel_pmu = {
         .max_period             = (1ULL << 31) - 1,
         .get_event_constraints  = intel_get_event_constraints,
         .put_event_constraints  = intel_put_event_constraints,
-        .pebs_aliases           = intel_pebs_aliases_core2,
-
-        .format_attrs           = intel_arch3_formats_attr,
-        .events_sysfs_show      = intel_event_sysfs_show,
 
         .cpu_prepare            = intel_pmu_cpu_prepare,
         .cpu_starting           = intel_pmu_cpu_starting,
         .cpu_dying              = intel_pmu_cpu_dying,
-        .guest_get_msrs         = intel_guest_get_msrs,
-        .flush_branch_stack     = intel_pmu_flush_branch_stack,
 };
 
-static __init void intel_clovertown_quirk(void)
+static void intel_clovertown_quirks(void)
 {
         /*
          * PEBS is unreliable due to:
@@ -1804,119 +1436,23 @@ static __init void intel_clovertown_quirk(void)
          * But taken together it might just make sense to not enable PEBS on
          * these chips.
          */
-        pr_warn("PEBS disabled due to CPU errata\n");
+        printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
         x86_pmu.pebs = 0;
         x86_pmu.pebs_constraints = NULL;
 }
 
-static int intel_snb_pebs_broken(int cpu)
-{
-        u32 rev = UINT_MAX; /* default to broken for unknown models */
-
-        switch (cpu_data(cpu).x86_model) {
-        case 42: /* SNB */
-                rev = 0x28;
-                break;
-
-        case 45: /* SNB-EP */
-                switch (cpu_data(cpu).x86_mask) {
-                case 6: rev = 0x618; break;
-                case 7: rev = 0x70c; break;
-                }
-        }
-
-        return (cpu_data(cpu).microcode < rev);
-}
-
-static void intel_snb_check_microcode(void)
-{
-        int pebs_broken = 0;
-        int cpu;
-
-        get_online_cpus();
-        for_each_online_cpu(cpu) {
-                if ((pebs_broken = intel_snb_pebs_broken(cpu)))
-                        break;
-        }
-        put_online_cpus();
-
-        if (pebs_broken == x86_pmu.pebs_broken)
-                return;
-
-        /*
-         * Serialized by the microcode lock..
-         */
-        if (x86_pmu.pebs_broken) {
-                pr_info("PEBS enabled due to microcode update\n");
-                x86_pmu.pebs_broken = 0;
-        } else {
-                pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
-                x86_pmu.pebs_broken = 1;
-        }
-}
-
-static __init void intel_sandybridge_quirk(void)
-{
-        x86_pmu.check_microcode = intel_snb_check_microcode;
-        intel_snb_check_microcode();
-}
-
-static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
-        { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
-        { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
-        { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
-        { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
-        { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
-        { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
-        { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
-};
-
-static __init void intel_arch_events_quirk(void)
-{
-        int bit;
-
-        /* disable event that reported as not presend by cpuid */
-        for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
-                intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
-                pr_warn("CPUID marked event: \'%s\' unavailable\n",
-                        intel_arch_events_map[bit].name);
-        }
-}
-
-static __init void intel_nehalem_quirk(void)
-{
-        union cpuid10_ebx ebx;
-
-        ebx.full = x86_pmu.events_maskl;
-        if (ebx.split.no_branch_misses_retired) {
-                /*
-                 * Erratum AAJ80 detected, we work it around by using
-                 * the BR_MISP_EXEC.ANY event. This will over-count
-                 * branch-misses, but it's still much better than the
-                 * architectural event which is often completely bogus:
-                 */
-                intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
-                ebx.split.no_branch_misses_retired = 0;
-                x86_pmu.events_maskl = ebx.full;
-                pr_info("CPU erratum AAJ80 worked around\n");
-        }
-}
-
-__init int intel_pmu_init(void)
+static __init int intel_pmu_init(void)
 {
         union cpuid10_edx edx;
         union cpuid10_eax eax;
-        union cpuid10_ebx ebx;
-        struct event_constraint *c;
         unsigned int unused;
+        unsigned int ebx;
         int version;
 
         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
                 switch (boot_cpu_data.x86) {
                 case 0x6:
                         return p6_pmu_init();
-                case 0xb:
-                        return knc_pmu_init();
                 case 0xf:
                         return p4_pmu_init();
                 }
@@ -1927,8 +1463,8 @@ __init int intel_pmu_init(void)
          * Check whether the Architectural PerfMon supports
          * Branch Misses Retired hw_event or not.
          */
-        cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
-        if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
+        cpuid(10, &eax.full, &ebx, &unused, &edx.full);
+        if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
                 return -ENODEV;
 
         version = eax.split.version_id;
@@ -1942,11 +1478,6 @@ __init int intel_pmu_init(void)
         x86_pmu.cntval_bits             = eax.split.bit_width;
         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
 
-        x86_pmu.events_maskl            = ebx.full;
-        x86_pmu.events_mask_len         = eax.split.mask_length;
-
-        x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
-
         /*
          * Quirk: v2 perfmon does not report fixed-purpose events, so
          * assume at least 3 events:
@@ -1966,8 +1497,6 @@ __init int intel_pmu_init(void)
 
         intel_ds_init();
 
-        x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
-
         /*
          * Install the hw-cache-events table:
          */
@@ -1977,7 +1506,7 @@ __init int intel_pmu_init(void)
                 break;
 
         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
-                x86_add_quirk(intel_clovertown_quirk);
+                x86_pmu.quirks = intel_clovertown_quirks;
         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
         case 29: /* six-core 45 nm xeon "Dunnington" */
@@ -2007,19 +1536,25 @@ __init int intel_pmu_init(void)
                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
 
                 /* UOPS_ISSUED.STALLED_CYCLES */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
-                        X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
-                        X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
 
-                x86_add_quirk(intel_nehalem_quirk);
+                if (ebx & 0x40) {
+                        /*
+                         * Erratum AAJ80 detected, we work it around by using
+                         * the BR_MISP_EXEC.ANY event. This will over-count
+                         * branch-misses, but it's still much better than the
+                         * architectural event which is often completely bogus:
+                         */
+                        intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
 
+                        pr_cont("erratum AAJ80 worked around, ");
+                }
                 pr_cont("Nehalem events, ");
                 break;
 
         case 28: /* Atom */
-        case 54: /* Cedariew */
                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));
 
@@ -2047,65 +1582,34 @@ __init int intel_pmu_init(void)
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
 
                 /* UOPS_ISSUED.STALLED_CYCLES */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
-                        X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
-                        X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
 
                 pr_cont("Westmere events, ");
                 break;
 
         case 42: /* SandyBridge */
         case 45: /* SandyBridge, "Romely-EP" */
-                x86_add_quirk(intel_sandybridge_quirk);
                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));
-                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
-                       sizeof(hw_cache_extra_regs));
 
-                intel_pmu_lbr_init_snb();
+                intel_pmu_lbr_init_nhm();
 
                 x86_pmu.event_constraints = intel_snb_event_constraints;
-                x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
-                x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
+                x86_pmu.pebs_constraints = intel_snb_pebs_events;
                 x86_pmu.extra_regs = intel_snb_extra_regs;
                 /* all extra regs are per-cpu when HT is on */
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
 
                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
-                        X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
-                        X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
+                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
 
                 pr_cont("SandyBridge events, ");
                 break;
-        case 58: /* IvyBridge */
-                memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
-                       sizeof(hw_cache_event_ids));
-                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
-                       sizeof(hw_cache_extra_regs));
-
-                intel_pmu_lbr_init_snb();
-
-                x86_pmu.event_constraints = intel_snb_event_constraints;
-                x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
-                x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
-                x86_pmu.extra_regs = intel_snb_extra_regs;
-                /* all extra regs are per-cpu when HT is on */
-                x86_pmu.er_flags |= ERF_HAS_RSP_1;
-                x86_pmu.er_flags |= ERF_NO_HT_SHARING;
-
-                /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
-                intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
-                        X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
-
-                pr_cont("IvyBridge events, ");
-                break;
-
 
         default:
                 switch (x86_pmu.version) {
@@ -2122,38 +1626,18 @@ __init int intel_pmu_init(void)
                         break;
                 }
         }
+        return 0;
+}
 
-        if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
-                WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
-                     x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
-                x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
-        }
-        x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
-
-        if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
-                WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
-                     x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
-                x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
-        }
-
-        x86_pmu.intel_ctrl |=
-                ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
-
-        if (x86_pmu.event_constraints) {
-                /*
-                 * event on fixed counter2 (REF_CYCLES) only works on this
-                 * counter, so do not extend mask to generic counters
-                 */
-                for_each_event_constraint(c, x86_pmu.event_constraints) {
-                        if (c->cmask != X86_RAW_EVENT_MASK
-                            || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
-                                continue;
-                        }
-
-                        c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
-                        c->weight += x86_pmu.num_counters;
-                }
-        }
+#else /* CONFIG_CPU_SUP_INTEL */
 
+static int intel_pmu_init(void)
+{
         return 0;
 }
+
+static struct intel_shared_regs *allocate_shared_regs(int cpu)
+{
+        return NULL;
+}
+#endif /* CONFIG_CPU_SUP_INTEL */