x86, AMD, cacheinfo: Fix L3 cache index disable checks

We provide two slots to disable cache indices, and have a check to
prevent both slots to be used for the same index.

If the user disables the same index on different subcaches, both slots
will hold the same index, e.g.

  $ echo 2047 > /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_0
  $ cat /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_0
  2047
  $ echo 1050623 > /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_1
  $ cat /sys/devices/system/cpu/cpu0/cache/index3/cache_disable_1
  2047

due to the fact that the check was looking only at index bits [11:0]
and was ignoring writes to bits outside that range. The more correct
fix is to simply check whether the index is within the bounds of
[0..l3->indices].

While at it, cleanup comments and drop now-unused local macros.

Signed-off-by: Frank Arnold <frank.arnold@amd.com>
Link: http://lkml.kernel.org/r/1305553188-21061-3-git-send-email-bp@amd64.org
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

1 files changed, 4 insertions, 15 deletions

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 31590a001e2..c105c533ed9 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -453,27 +453,16 @@ int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot,
 {
         int ret = 0;
 
-#define SUBCACHE_MASK   (3UL << 20)
-#define SUBCACHE_INDEX  0xfff
-
-        /*
-         * check whether this slot is already used or
-         * the index is already disabled
-         */
+        /*  check if @slot is already used or the index is already disabled */
         ret = amd_get_l3_disable_slot(l3, slot);
         if (ret >= 0)
                 return -EINVAL;
 
-        /*
-         * check whether the other slot has disabled the
-         * same index already
-         */
-        if (index == amd_get_l3_disable_slot(l3, !slot))
+        if (index > l3->indices)
                 return -EINVAL;
 
-        /* do not allow writes outside of allowed bits */
-        if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
-            ((index & SUBCACHE_INDEX) > l3->indices))
+        /* check whether the other slot has disabled the same index already */
+        if (index == amd_get_l3_disable_slot(l3, !slot))
                 return -EINVAL;
 
         amd_l3_disable_index(l3, cpu, slot, index);