diff options
author | Kees Cook <kees.cook@canonical.com> | 2011-07-06 21:10:34 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2011-07-06 23:09:34 -0400 |
commit | 7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76 (patch) | |
tree | 9d9e9f1de8ab1306b8b9d26aadb4a7f401323e69 /arch/x86/kernel/acpi/realmode/wakeup.S | |
parent | b49c78d4827be8d7e67e5b94adac6b30a4a9ad14 (diff) |
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
Diffstat (limited to 'arch/x86/kernel/acpi/realmode/wakeup.S')
-rw-r--r-- | arch/x86/kernel/acpi/realmode/wakeup.S | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/kernel/acpi/realmode/wakeup.S b/arch/x86/kernel/acpi/realmode/wakeup.S index ead21b66311..b4fd836e405 100644 --- a/arch/x86/kernel/acpi/realmode/wakeup.S +++ b/arch/x86/kernel/acpi/realmode/wakeup.S | |||
@@ -28,6 +28,8 @@ pmode_cr3: .long 0 /* Saved %cr3 */ | |||
28 | pmode_cr4: .long 0 /* Saved %cr4 */ | 28 | pmode_cr4: .long 0 /* Saved %cr4 */ |
29 | pmode_efer: .quad 0 /* Saved EFER */ | 29 | pmode_efer: .quad 0 /* Saved EFER */ |
30 | pmode_gdt: .quad 0 | 30 | pmode_gdt: .quad 0 |
31 | pmode_misc_en: .quad 0 /* Saved MISC_ENABLE MSR */ | ||
32 | pmode_behavior: .long 0 /* Wakeup behavior flags */ | ||
31 | realmode_flags: .long 0 | 33 | realmode_flags: .long 0 |
32 | real_magic: .long 0 | 34 | real_magic: .long 0 |
33 | trampoline_segment: .word 0 | 35 | trampoline_segment: .word 0 |
@@ -91,6 +93,18 @@ wakeup_code: | |||
91 | /* Call the C code */ | 93 | /* Call the C code */ |
92 | calll main | 94 | calll main |
93 | 95 | ||
96 | /* Restore MISC_ENABLE before entering protected mode, in case | ||
97 | BIOS decided to clear XD_DISABLE during S3. */ | ||
98 | movl pmode_behavior, %eax | ||
99 | btl $WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE, %eax | ||
100 | jnc 1f | ||
101 | |||
102 | movl pmode_misc_en, %eax | ||
103 | movl pmode_misc_en + 4, %edx | ||
104 | movl $MSR_IA32_MISC_ENABLE, %ecx | ||
105 | wrmsr | ||
106 | 1: | ||
107 | |||
94 | /* Do any other stuff... */ | 108 | /* Do any other stuff... */ |
95 | 109 | ||
96 | #ifndef CONFIG_64BIT | 110 | #ifndef CONFIG_64BIT |