diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-02-26 07:02:23 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-02-26 07:02:23 -0500 |
commit | 8e818179eb9e8f9e44d8410dd2a25077d026a08e (patch) | |
tree | 7d08afd30c95c04129c20693d974a18799caeb5a /arch/x86/include | |
parent | 742bd95ba96e19b3f7196c3a0834ebc17c8ba006 (diff) | |
parent | ecc25fbd6b9e07b33895c61ddf84006b00f55d99 (diff) |
Merge branch 'x86/core' into perfcounters/core
Conflicts:
arch/x86/kernel/apic/apic.c
arch/x86/kernel/irqinit_32.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include')
29 files changed, 80 insertions, 805 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index dce1bf696cc..a6208dc7463 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h | |||
@@ -146,7 +146,7 @@ static inline u64 native_x2apic_icr_read(void) | |||
146 | return val; | 146 | return val; |
147 | } | 147 | } |
148 | 148 | ||
149 | extern int x2apic; | 149 | extern int x2apic, x2apic_phys; |
150 | extern void check_x2apic(void); | 150 | extern void check_x2apic(void); |
151 | extern void enable_x2apic(void); | 151 | extern void enable_x2apic(void); |
152 | extern void enable_IR_x2apic(void); | 152 | extern void enable_IR_x2apic(void); |
diff --git a/arch/x86/include/asm/arch_hooks.h b/arch/x86/include/asm/arch_hooks.h deleted file mode 100644 index cbd4957838a..00000000000 --- a/arch/x86/include/asm/arch_hooks.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | #ifndef _ASM_X86_ARCH_HOOKS_H | ||
2 | #define _ASM_X86_ARCH_HOOKS_H | ||
3 | |||
4 | #include <linux/interrupt.h> | ||
5 | |||
6 | /* | ||
7 | * linux/include/asm/arch_hooks.h | ||
8 | * | ||
9 | * define the architecture specific hooks | ||
10 | */ | ||
11 | |||
12 | /* these aren't arch hooks, they are generic routines | ||
13 | * that can be used by the hooks */ | ||
14 | extern void init_ISA_irqs(void); | ||
15 | extern irqreturn_t timer_interrupt(int irq, void *dev_id); | ||
16 | |||
17 | /* these are the defined hooks */ | ||
18 | extern void intr_init_hook(void); | ||
19 | extern void pre_intr_init_hook(void); | ||
20 | extern void pre_setup_arch_hook(void); | ||
21 | extern void trap_init_hook(void); | ||
22 | extern void pre_time_init_hook(void); | ||
23 | extern void time_init_hook(void); | ||
24 | extern void mca_nmi_hook(void); | ||
25 | |||
26 | #endif /* _ASM_X86_ARCH_HOOKS_H */ | ||
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 58d7091eeb1..1a99e6c092a 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h | |||
@@ -60,4 +60,8 @@ extern struct irq_chip i8259A_chip; | |||
60 | extern void mask_8259A(void); | 60 | extern void mask_8259A(void); |
61 | extern void unmask_8259A(void); | 61 | extern void unmask_8259A(void); |
62 | 62 | ||
63 | #ifdef CONFIG_X86_32 | ||
64 | extern void init_ISA_irqs(void); | ||
65 | #endif | ||
66 | |||
63 | #endif /* _ASM_X86_I8259_H */ | 67 | #endif /* _ASM_X86_I8259_H */ |
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 4f8e820cf38..683d0b4c00f 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h | |||
@@ -124,10 +124,15 @@ static inline void *phys_to_virt(phys_addr_t address) | |||
124 | 124 | ||
125 | /* | 125 | /* |
126 | * ISA I/O bus memory addresses are 1:1 with the physical address. | 126 | * ISA I/O bus memory addresses are 1:1 with the physical address. |
127 | * However, we truncate the address to unsigned int to avoid undesirable | ||
128 | * promitions in legacy drivers. | ||
127 | */ | 129 | */ |
128 | #define isa_virt_to_bus (unsigned long)virt_to_phys | 130 | static inline unsigned int isa_virt_to_bus(volatile void *address) |
129 | #define isa_page_to_bus page_to_phys | 131 | { |
130 | #define isa_bus_to_virt phys_to_virt | 132 | return (unsigned int)virt_to_phys(address); |
133 | } | ||
134 | #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) | ||
135 | #define isa_bus_to_virt phys_to_virt | ||
131 | 136 | ||
132 | /* | 137 | /* |
133 | * However PCI ones are not necessarily 1:1 and therefore these interfaces | 138 | * However PCI ones are not necessarily 1:1 and therefore these interfaces |
diff --git a/arch/x86/include/asm/iomap.h b/arch/x86/include/asm/iomap.h index c1f06289b14..bd46495ff7d 100644 --- a/arch/x86/include/asm/iomap.h +++ b/arch/x86/include/asm/iomap.h | |||
@@ -23,6 +23,12 @@ | |||
23 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
24 | #include <asm/tlbflush.h> | 24 | #include <asm/tlbflush.h> |
25 | 25 | ||
26 | int | ||
27 | reserve_io_memtype_wc(u64 base, unsigned long size, pgprot_t *prot); | ||
28 | |||
29 | void | ||
30 | free_io_memtype(u64 base, unsigned long size); | ||
31 | |||
26 | void * | 32 | void * |
27 | iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); | 33 | iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); |
28 | 34 | ||
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index b07278c55e9..8a285f356f8 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h | |||
@@ -128,7 +128,7 @@ | |||
128 | #ifndef __ASSEMBLY__ | 128 | #ifndef __ASSEMBLY__ |
129 | static inline int invalid_vm86_irq(int irq) | 129 | static inline int invalid_vm86_irq(int irq) |
130 | { | 130 | { |
131 | return irq < 3 || irq > 15; | 131 | return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; |
132 | } | 132 | } |
133 | #endif | 133 | #endif |
134 | 134 | ||
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h index d2e3bf3608a..886c9402ec4 100644 --- a/arch/x86/include/asm/kvm.h +++ b/arch/x86/include/asm/kvm.h | |||
@@ -9,6 +9,13 @@ | |||
9 | #include <linux/types.h> | 9 | #include <linux/types.h> |
10 | #include <linux/ioctl.h> | 10 | #include <linux/ioctl.h> |
11 | 11 | ||
12 | /* Select x86 specific features in <linux/kvm.h> */ | ||
13 | #define __KVM_HAVE_PIT | ||
14 | #define __KVM_HAVE_IOAPIC | ||
15 | #define __KVM_HAVE_DEVICE_ASSIGNMENT | ||
16 | #define __KVM_HAVE_MSI | ||
17 | #define __KVM_HAVE_USER_NMI | ||
18 | |||
12 | /* Architectural interrupt line count. */ | 19 | /* Architectural interrupt line count. */ |
13 | #define KVM_NR_INTERRUPTS 256 | 20 | #define KVM_NR_INTERRUPTS 256 |
14 | 21 | ||
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h index 5d98d0b68ff..9320e2a8a26 100644 --- a/arch/x86/include/asm/linkage.h +++ b/arch/x86/include/asm/linkage.h | |||
@@ -52,70 +52,14 @@ | |||
52 | 52 | ||
53 | #endif | 53 | #endif |
54 | 54 | ||
55 | #define GLOBAL(name) \ | ||
56 | .globl name; \ | ||
57 | name: | ||
58 | |||
55 | #ifdef CONFIG_X86_ALIGNMENT_16 | 59 | #ifdef CONFIG_X86_ALIGNMENT_16 |
56 | #define __ALIGN .align 16,0x90 | 60 | #define __ALIGN .align 16,0x90 |
57 | #define __ALIGN_STR ".align 16,0x90" | 61 | #define __ALIGN_STR ".align 16,0x90" |
58 | #endif | 62 | #endif |
59 | 63 | ||
60 | /* | ||
61 | * to check ENTRY_X86/END_X86 and | ||
62 | * KPROBE_ENTRY_X86/KPROBE_END_X86 | ||
63 | * unbalanced-missed-mixed appearance | ||
64 | */ | ||
65 | #define __set_entry_x86 .set ENTRY_X86_IN, 0 | ||
66 | #define __unset_entry_x86 .set ENTRY_X86_IN, 1 | ||
67 | #define __set_kprobe_x86 .set KPROBE_X86_IN, 0 | ||
68 | #define __unset_kprobe_x86 .set KPROBE_X86_IN, 1 | ||
69 | |||
70 | #define __macro_err_x86 .error "ENTRY_X86/KPROBE_X86 unbalanced,missed,mixed" | ||
71 | |||
72 | #define __check_entry_x86 \ | ||
73 | .ifdef ENTRY_X86_IN; \ | ||
74 | .ifeq ENTRY_X86_IN; \ | ||
75 | __macro_err_x86; \ | ||
76 | .abort; \ | ||
77 | .endif; \ | ||
78 | .endif | ||
79 | |||
80 | #define __check_kprobe_x86 \ | ||
81 | .ifdef KPROBE_X86_IN; \ | ||
82 | .ifeq KPROBE_X86_IN; \ | ||
83 | __macro_err_x86; \ | ||
84 | .abort; \ | ||
85 | .endif; \ | ||
86 | .endif | ||
87 | |||
88 | #define __check_entry_kprobe_x86 \ | ||
89 | __check_entry_x86; \ | ||
90 | __check_kprobe_x86 | ||
91 | |||
92 | #define ENTRY_KPROBE_FINAL_X86 __check_entry_kprobe_x86 | ||
93 | |||
94 | #define ENTRY_X86(name) \ | ||
95 | __check_entry_kprobe_x86; \ | ||
96 | __set_entry_x86; \ | ||
97 | .globl name; \ | ||
98 | __ALIGN; \ | ||
99 | name: | ||
100 | |||
101 | #define END_X86(name) \ | ||
102 | __unset_entry_x86; \ | ||
103 | __check_entry_kprobe_x86; \ | ||
104 | .size name, .-name | ||
105 | |||
106 | #define KPROBE_ENTRY_X86(name) \ | ||
107 | __check_entry_kprobe_x86; \ | ||
108 | __set_kprobe_x86; \ | ||
109 | .pushsection .kprobes.text, "ax"; \ | ||
110 | .globl name; \ | ||
111 | __ALIGN; \ | ||
112 | name: | ||
113 | |||
114 | #define KPROBE_END_X86(name) \ | ||
115 | __unset_kprobe_x86; \ | ||
116 | __check_entry_kprobe_x86; \ | ||
117 | .size name, .-name; \ | ||
118 | .popsection | ||
119 | |||
120 | #endif /* _ASM_X86_LINKAGE_H */ | 64 | #endif /* _ASM_X86_LINKAGE_H */ |
121 | 65 | ||
diff --git a/arch/x86/include/asm/mach-voyager/do_timer.h b/arch/x86/include/asm/mach-voyager/do_timer.h deleted file mode 100644 index 9e5a459fd15..00000000000 --- a/arch/x86/include/asm/mach-voyager/do_timer.h +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | /* defines for inline arch setup functions */ | ||
2 | #include <linux/clockchips.h> | ||
3 | |||
4 | #include <asm/voyager.h> | ||
5 | #include <asm/i8253.h> | ||
6 | |||
7 | /** | ||
8 | * do_timer_interrupt_hook - hook into timer tick | ||
9 | * | ||
10 | * Call the pit clock event handler. see asm/i8253.h | ||
11 | **/ | ||
12 | static inline void do_timer_interrupt_hook(void) | ||
13 | { | ||
14 | global_clock_event->event_handler(global_clock_event); | ||
15 | voyager_timer_interrupt(); | ||
16 | } | ||
17 | |||
diff --git a/arch/x86/include/asm/mach-voyager/entry_arch.h b/arch/x86/include/asm/mach-voyager/entry_arch.h deleted file mode 100644 index ae52624b593..00000000000 --- a/arch/x86/include/asm/mach-voyager/entry_arch.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* -*- mode: c; c-basic-offset: 8 -*- */ | ||
2 | |||
3 | /* Copyright (C) 2002 | ||
4 | * | ||
5 | * Author: James.Bottomley@HansenPartnership.com | ||
6 | * | ||
7 | * linux/arch/i386/voyager/entry_arch.h | ||
8 | * | ||
9 | * This file builds the VIC and QIC CPI gates | ||
10 | */ | ||
11 | |||
12 | /* initialise the voyager interrupt gates | ||
13 | * | ||
14 | * This uses the macros in irq.h to set up assembly jump gates. The | ||
15 | * calls are then redirected to the same routine with smp_ prefixed */ | ||
16 | BUILD_INTERRUPT(vic_sys_interrupt, VIC_SYS_INT) | ||
17 | BUILD_INTERRUPT(vic_cmn_interrupt, VIC_CMN_INT) | ||
18 | BUILD_INTERRUPT(vic_cpi_interrupt, VIC_CPI_LEVEL0); | ||
19 | |||
20 | /* do all the QIC interrupts */ | ||
21 | BUILD_INTERRUPT(qic_timer_interrupt, QIC_TIMER_CPI); | ||
22 | BUILD_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI); | ||
23 | BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI); | ||
24 | BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI); | ||
25 | BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI); | ||
26 | BUILD_INTERRUPT(qic_call_function_single_interrupt, QIC_CALL_FUNCTION_SINGLE_CPI); | ||
diff --git a/arch/x86/include/asm/mach-voyager/setup_arch.h b/arch/x86/include/asm/mach-voyager/setup_arch.h deleted file mode 100644 index 71729ca05cd..00000000000 --- a/arch/x86/include/asm/mach-voyager/setup_arch.h +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | #include <asm/voyager.h> | ||
2 | #include <asm/setup.h> | ||
3 | #define VOYAGER_BIOS_INFO ((struct voyager_bios_info *) \ | ||
4 | (&boot_params.apm_bios_info)) | ||
5 | |||
6 | /* Hook to call BIOS initialisation function */ | ||
7 | |||
8 | /* for voyager, pass the voyager BIOS/SUS info area to the detection | ||
9 | * routines */ | ||
10 | |||
11 | #define ARCH_SETUP voyager_detect(VOYAGER_BIOS_INFO); | ||
12 | |||
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h index 07f1af494ca..105fb90a063 100644 --- a/arch/x86/include/asm/mmzone_32.h +++ b/arch/x86/include/asm/mmzone_32.h | |||
@@ -32,8 +32,6 @@ static inline void get_memcfg_numa(void) | |||
32 | get_memcfg_numa_flat(); | 32 | get_memcfg_numa_flat(); |
33 | } | 33 | } |
34 | 34 | ||
35 | extern int early_pfn_to_nid(unsigned long pfn); | ||
36 | |||
37 | extern void resume_map_numa_kva(pgd_t *pgd); | 35 | extern void resume_map_numa_kva(pgd_t *pgd); |
38 | 36 | ||
39 | #else /* !CONFIG_NUMA */ | 37 | #else /* !CONFIG_NUMA */ |
diff --git a/arch/x86/include/asm/mmzone_64.h b/arch/x86/include/asm/mmzone_64.h index a5b3817d4b9..a29f48c2a32 100644 --- a/arch/x86/include/asm/mmzone_64.h +++ b/arch/x86/include/asm/mmzone_64.h | |||
@@ -40,8 +40,6 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr) | |||
40 | #define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \ | 40 | #define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \ |
41 | NODE_DATA(nid)->node_spanned_pages) | 41 | NODE_DATA(nid)->node_spanned_pages) |
42 | 42 | ||
43 | extern int early_pfn_to_nid(unsigned long pfn); | ||
44 | |||
45 | #ifdef CONFIG_NUMA_EMU | 43 | #ifdef CONFIG_NUMA_EMU |
46 | #define FAKE_NODE_MIN_SIZE (64 * 1024 * 1024) | 44 | #define FAKE_NODE_MIN_SIZE (64 * 1024 * 1024) |
47 | #define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) | 45 | #define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) |
diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/page_32_types.h index b5486aaf36e..f1e4a79a6e4 100644 --- a/arch/x86/include/asm/page_32_types.h +++ b/arch/x86/include/asm/page_32_types.h | |||
@@ -33,12 +33,10 @@ | |||
33 | /* 44=32+12, the limit we can fit into an unsigned long pfn */ | 33 | /* 44=32+12, the limit we can fit into an unsigned long pfn */ |
34 | #define __PHYSICAL_MASK_SHIFT 44 | 34 | #define __PHYSICAL_MASK_SHIFT 44 |
35 | #define __VIRTUAL_MASK_SHIFT 32 | 35 | #define __VIRTUAL_MASK_SHIFT 32 |
36 | #define PAGETABLE_LEVELS 3 | ||
37 | 36 | ||
38 | #else /* !CONFIG_X86_PAE */ | 37 | #else /* !CONFIG_X86_PAE */ |
39 | #define __PHYSICAL_MASK_SHIFT 32 | 38 | #define __PHYSICAL_MASK_SHIFT 32 |
40 | #define __VIRTUAL_MASK_SHIFT 32 | 39 | #define __VIRTUAL_MASK_SHIFT 32 |
41 | #define PAGETABLE_LEVELS 2 | ||
42 | #endif /* CONFIG_X86_PAE */ | 40 | #endif /* CONFIG_X86_PAE */ |
43 | 41 | ||
44 | #ifndef __ASSEMBLY__ | 42 | #ifndef __ASSEMBLY__ |
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h index bc73af3eda9..d38c91b7024 100644 --- a/arch/x86/include/asm/page_64_types.h +++ b/arch/x86/include/asm/page_64_types.h | |||
@@ -1,8 +1,6 @@ | |||
1 | #ifndef _ASM_X86_PAGE_64_DEFS_H | 1 | #ifndef _ASM_X86_PAGE_64_DEFS_H |
2 | #define _ASM_X86_PAGE_64_DEFS_H | 2 | #define _ASM_X86_PAGE_64_DEFS_H |
3 | 3 | ||
4 | #define PAGETABLE_LEVELS 4 | ||
5 | |||
6 | #define THREAD_ORDER 1 | 4 | #define THREAD_ORDER 1 |
7 | #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER) | 5 | #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER) |
8 | #define CURRENT_MASK (~(THREAD_SIZE - 1)) | 6 | #define CURRENT_MASK (~(THREAD_SIZE - 1)) |
diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h index 2c52ff76758..2d625da6603 100644 --- a/arch/x86/include/asm/page_types.h +++ b/arch/x86/include/asm/page_types.h | |||
@@ -16,12 +16,6 @@ | |||
16 | (ie, 32-bit PAE). */ | 16 | (ie, 32-bit PAE). */ |
17 | #define PHYSICAL_PAGE_MASK (((signed long)PAGE_MASK) & __PHYSICAL_MASK) | 17 | #define PHYSICAL_PAGE_MASK (((signed long)PAGE_MASK) & __PHYSICAL_MASK) |
18 | 18 | ||
19 | /* PTE_PFN_MASK extracts the PFN from a (pte|pmd|pud|pgd)val_t */ | ||
20 | #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK) | ||
21 | |||
22 | /* PTE_FLAGS_MASK extracts the flags from a (pte|pmd|pud|pgd)val_t */ | ||
23 | #define PTE_FLAGS_MASK (~PTE_PFN_MASK) | ||
24 | |||
25 | #define PMD_PAGE_SIZE (_AC(1, UL) << PMD_SHIFT) | 19 | #define PMD_PAGE_SIZE (_AC(1, UL) << PMD_SHIFT) |
26 | #define PMD_PAGE_MASK (~(PMD_PAGE_SIZE-1)) | 20 | #define PMD_PAGE_MASK (~(PMD_PAGE_SIZE-1)) |
27 | 21 | ||
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h index 9709fdff661..b0e70056838 100644 --- a/arch/x86/include/asm/pat.h +++ b/arch/x86/include/asm/pat.h | |||
@@ -15,4 +15,7 @@ extern int reserve_memtype(u64 start, u64 end, | |||
15 | unsigned long req_type, unsigned long *ret_type); | 15 | unsigned long req_type, unsigned long *ret_type); |
16 | extern int free_memtype(u64 start, u64 end); | 16 | extern int free_memtype(u64 start, u64 end); |
17 | 17 | ||
18 | extern int kernel_map_sync_memtype(u64 base, unsigned long size, | ||
19 | unsigned long flag); | ||
20 | |||
18 | #endif /* _ASM_X86_PAT_H */ | 21 | #endif /* _ASM_X86_PAT_H */ |
diff --git a/arch/x86/include/asm/pgtable-2level_types.h b/arch/x86/include/asm/pgtable-2level_types.h index 09ae67efceb..daacc23e3fb 100644 --- a/arch/x86/include/asm/pgtable-2level_types.h +++ b/arch/x86/include/asm/pgtable-2level_types.h | |||
@@ -17,6 +17,7 @@ typedef union { | |||
17 | #endif /* !__ASSEMBLY__ */ | 17 | #endif /* !__ASSEMBLY__ */ |
18 | 18 | ||
19 | #define SHARED_KERNEL_PMD 0 | 19 | #define SHARED_KERNEL_PMD 0 |
20 | #define PAGETABLE_LEVELS 2 | ||
20 | 21 | ||
21 | /* | 22 | /* |
22 | * traditional i386 two-level paging structure: | 23 | * traditional i386 two-level paging structure: |
@@ -25,6 +26,7 @@ typedef union { | |||
25 | #define PGDIR_SHIFT 22 | 26 | #define PGDIR_SHIFT 22 |
26 | #define PTRS_PER_PGD 1024 | 27 | #define PTRS_PER_PGD 1024 |
27 | 28 | ||
29 | |||
28 | /* | 30 | /* |
29 | * the i386 is two-level, so we don't really have any | 31 | * the i386 is two-level, so we don't really have any |
30 | * PMD directory physically. | 32 | * PMD directory physically. |
diff --git a/arch/x86/include/asm/pgtable-3level_types.h b/arch/x86/include/asm/pgtable-3level_types.h index bcc89625ebe..1bd5876c864 100644 --- a/arch/x86/include/asm/pgtable-3level_types.h +++ b/arch/x86/include/asm/pgtable-3level_types.h | |||
@@ -24,6 +24,8 @@ typedef union { | |||
24 | #define SHARED_KERNEL_PMD 1 | 24 | #define SHARED_KERNEL_PMD 1 |
25 | #endif | 25 | #endif |
26 | 26 | ||
27 | #define PAGETABLE_LEVELS 3 | ||
28 | |||
27 | /* | 29 | /* |
28 | * PGDIR_SHIFT determines what a top-level page table entry can map | 30 | * PGDIR_SHIFT determines what a top-level page table entry can map |
29 | */ | 31 | */ |
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 2f59135c6f2..fbf42b8e038 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h | |||
@@ -18,6 +18,7 @@ typedef struct { pteval_t pte; } pte_t; | |||
18 | #endif /* !__ASSEMBLY__ */ | 18 | #endif /* !__ASSEMBLY__ */ |
19 | 19 | ||
20 | #define SHARED_KERNEL_PMD 0 | 20 | #define SHARED_KERNEL_PMD 0 |
21 | #define PAGETABLE_LEVELS 4 | ||
21 | 22 | ||
22 | /* | 23 | /* |
23 | * PGDIR_SHIFT determines what a top-level page table entry can map | 24 | * PGDIR_SHIFT determines what a top-level page table entry can map |
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 9dafe87be2d..4d258ad76a0 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h | |||
@@ -173,6 +173,12 @@ | |||
173 | 173 | ||
174 | #include <linux/types.h> | 174 | #include <linux/types.h> |
175 | 175 | ||
176 | /* PTE_PFN_MASK extracts the PFN from a (pte|pmd|pud|pgd)val_t */ | ||
177 | #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK) | ||
178 | |||
179 | /* PTE_FLAGS_MASK extracts the flags from a (pte|pmd|pud|pgd)val_t */ | ||
180 | #define PTE_FLAGS_MASK (~PTE_PFN_MASK) | ||
181 | |||
176 | typedef struct pgprot { pgprotval_t pgprot; } pgprot_t; | 182 | typedef struct pgprot { pgprotval_t pgprot; } pgprot_t; |
177 | 183 | ||
178 | typedef struct { pgdval_t pgd; } pgd_t; | 184 | typedef struct { pgdval_t pgd; } pgd_t; |
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index dabab1a19dd..c7a98f73821 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h | |||
@@ -403,7 +403,6 @@ DECLARE_PER_CPU(unsigned long, stack_canary); | |||
403 | #endif | 403 | #endif |
404 | #endif /* X86_64 */ | 404 | #endif /* X86_64 */ |
405 | 405 | ||
406 | extern void print_cpu_info(struct cpuinfo_x86 *); | ||
407 | extern unsigned int xstate_size; | 406 | extern unsigned int xstate_size; |
408 | extern void free_thread_xstate(struct task_struct *); | 407 | extern void free_thread_xstate(struct task_struct *); |
409 | extern struct kmem_cache *task_xstate_cachep; | 408 | extern struct kmem_cache *task_xstate_cachep; |
@@ -862,6 +861,7 @@ static inline void spin_lock_prefetch(const void *x) | |||
862 | * User space process size: 3GB (default). | 861 | * User space process size: 3GB (default). |
863 | */ | 862 | */ |
864 | #define TASK_SIZE PAGE_OFFSET | 863 | #define TASK_SIZE PAGE_OFFSET |
864 | #define TASK_SIZE_MAX TASK_SIZE | ||
865 | #define STACK_TOP TASK_SIZE | 865 | #define STACK_TOP TASK_SIZE |
866 | #define STACK_TOP_MAX STACK_TOP | 866 | #define STACK_TOP_MAX STACK_TOP |
867 | 867 | ||
@@ -921,7 +921,7 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk); | |||
921 | /* | 921 | /* |
922 | * User space process size. 47bits minus one guard page. | 922 | * User space process size. 47bits minus one guard page. |
923 | */ | 923 | */ |
924 | #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE) | 924 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
925 | 925 | ||
926 | /* This decides where the kernel will search for a free chunk of vm | 926 | /* This decides where the kernel will search for a free chunk of vm |
927 | * space during mmap's. | 927 | * space during mmap's. |
@@ -930,12 +930,12 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk); | |||
930 | 0xc0000000 : 0xFFFFe000) | 930 | 0xc0000000 : 0xFFFFe000) |
931 | 931 | ||
932 | #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ | 932 | #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ |
933 | IA32_PAGE_OFFSET : TASK_SIZE64) | 933 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
934 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ | 934 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ |
935 | IA32_PAGE_OFFSET : TASK_SIZE64) | 935 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
936 | 936 | ||
937 | #define STACK_TOP TASK_SIZE | 937 | #define STACK_TOP TASK_SIZE |
938 | #define STACK_TOP_MAX TASK_SIZE64 | 938 | #define STACK_TOP_MAX TASK_SIZE_MAX |
939 | 939 | ||
940 | #define INIT_THREAD { \ | 940 | #define INIT_THREAD { \ |
941 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | 941 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ |
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 8029369cd6f..66801cb72f6 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h | |||
@@ -13,6 +13,7 @@ | |||
13 | struct mpc_cpu; | 13 | struct mpc_cpu; |
14 | struct mpc_bus; | 14 | struct mpc_bus; |
15 | struct mpc_oemtable; | 15 | struct mpc_oemtable; |
16 | |||
16 | struct x86_quirks { | 17 | struct x86_quirks { |
17 | int (*arch_pre_time_init)(void); | 18 | int (*arch_pre_time_init)(void); |
18 | int (*arch_time_init)(void); | 19 | int (*arch_time_init)(void); |
@@ -33,6 +34,14 @@ struct x86_quirks { | |||
33 | int (*update_apic)(void); | 34 | int (*update_apic)(void); |
34 | }; | 35 | }; |
35 | 36 | ||
37 | extern void x86_quirk_pre_intr_init(void); | ||
38 | extern void x86_quirk_intr_init(void); | ||
39 | |||
40 | extern void x86_quirk_trap_init(void); | ||
41 | |||
42 | extern void x86_quirk_pre_time_init(void); | ||
43 | extern void x86_quirk_time_init(void); | ||
44 | |||
36 | #endif /* __ASSEMBLY__ */ | 45 | #endif /* __ASSEMBLY__ */ |
37 | 46 | ||
38 | #ifdef __i386__ | 47 | #ifdef __i386__ |
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h index 258ef730aaa..7043408f690 100644 --- a/arch/x86/include/asm/syscalls.h +++ b/arch/x86/include/asm/syscalls.h | |||
@@ -82,7 +82,7 @@ asmlinkage long sys_iopl(unsigned int, struct pt_regs *); | |||
82 | /* kernel/signal_64.c */ | 82 | /* kernel/signal_64.c */ |
83 | asmlinkage long sys_sigaltstack(const stack_t __user *, stack_t __user *, | 83 | asmlinkage long sys_sigaltstack(const stack_t __user *, stack_t __user *, |
84 | struct pt_regs *); | 84 | struct pt_regs *); |
85 | asmlinkage long sys_rt_sigreturn(struct pt_regs *); | 85 | long sys_rt_sigreturn(struct pt_regs *); |
86 | 86 | ||
87 | /* kernel/sys_x86_64.c */ | 87 | /* kernel/sys_x86_64.c */ |
88 | asmlinkage long sys_mmap(unsigned long, unsigned long, unsigned long, | 88 | asmlinkage long sys_mmap(unsigned long, unsigned long, unsigned long, |
diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h index 2bb6a835c45..a81195eaa2b 100644 --- a/arch/x86/include/asm/timer.h +++ b/arch/x86/include/asm/timer.h | |||
@@ -3,6 +3,7 @@ | |||
3 | #include <linux/init.h> | 3 | #include <linux/init.h> |
4 | #include <linux/pm.h> | 4 | #include <linux/pm.h> |
5 | #include <linux/percpu.h> | 5 | #include <linux/percpu.h> |
6 | #include <linux/interrupt.h> | ||
6 | 7 | ||
7 | #define TICK_SIZE (tick_nsec / 1000) | 8 | #define TICK_SIZE (tick_nsec / 1000) |
8 | 9 | ||
@@ -12,6 +13,7 @@ unsigned long native_calibrate_tsc(void); | |||
12 | #ifdef CONFIG_X86_32 | 13 | #ifdef CONFIG_X86_32 |
13 | extern int timer_ack; | 14 | extern int timer_ack; |
14 | extern int recalibrate_cpu_khz(void); | 15 | extern int recalibrate_cpu_khz(void); |
16 | extern irqreturn_t timer_interrupt(int irq, void *dev_id); | ||
15 | #endif /* CONFIG_X86_32 */ | 17 | #endif /* CONFIG_X86_32 */ |
16 | 18 | ||
17 | extern int no_timer_check; | 19 | extern int no_timer_check; |
diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h index 5e06259e90e..a0ba6138697 100644 --- a/arch/x86/include/asm/uaccess_32.h +++ b/arch/x86/include/asm/uaccess_32.h | |||
@@ -157,7 +157,7 @@ __copy_from_user(void *to, const void __user *from, unsigned long n) | |||
157 | } | 157 | } |
158 | 158 | ||
159 | static __always_inline unsigned long __copy_from_user_nocache(void *to, | 159 | static __always_inline unsigned long __copy_from_user_nocache(void *to, |
160 | const void __user *from, unsigned long n) | 160 | const void __user *from, unsigned long n, unsigned long total) |
161 | { | 161 | { |
162 | might_fault(); | 162 | might_fault(); |
163 | if (__builtin_constant_p(n)) { | 163 | if (__builtin_constant_p(n)) { |
@@ -180,7 +180,7 @@ static __always_inline unsigned long __copy_from_user_nocache(void *to, | |||
180 | 180 | ||
181 | static __always_inline unsigned long | 181 | static __always_inline unsigned long |
182 | __copy_from_user_inatomic_nocache(void *to, const void __user *from, | 182 | __copy_from_user_inatomic_nocache(void *to, const void __user *from, |
183 | unsigned long n) | 183 | unsigned long n, unsigned long total) |
184 | { | 184 | { |
185 | return __copy_from_user_ll_nocache_nozero(to, from, n); | 185 | return __copy_from_user_ll_nocache_nozero(to, from, n); |
186 | } | 186 | } |
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 84210c479fc..dcaa0404cf7 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h | |||
@@ -189,17 +189,28 @@ extern long __copy_user_nocache(void *dst, const void __user *src, | |||
189 | unsigned size, int zerorest); | 189 | unsigned size, int zerorest); |
190 | 190 | ||
191 | static inline int __copy_from_user_nocache(void *dst, const void __user *src, | 191 | static inline int __copy_from_user_nocache(void *dst, const void __user *src, |
192 | unsigned size) | 192 | unsigned size, unsigned long total) |
193 | { | 193 | { |
194 | might_sleep(); | 194 | might_sleep(); |
195 | return __copy_user_nocache(dst, src, size, 1); | 195 | /* |
196 | * In practice this limit means that large file write()s | ||
197 | * which get chunked to 4K copies get handled via | ||
198 | * non-temporal stores here. Smaller writes get handled | ||
199 | * via regular __copy_from_user(): | ||
200 | */ | ||
201 | if (likely(total >= PAGE_SIZE)) | ||
202 | return __copy_user_nocache(dst, src, size, 1); | ||
203 | else | ||
204 | return __copy_from_user(dst, src, size); | ||
196 | } | 205 | } |
197 | 206 | ||
198 | static inline int __copy_from_user_inatomic_nocache(void *dst, | 207 | static inline int __copy_from_user_inatomic_nocache(void *dst, |
199 | const void __user *src, | 208 | const void __user *src, unsigned size, unsigned total) |
200 | unsigned size) | ||
201 | { | 209 | { |
202 | return __copy_user_nocache(dst, src, size, 0); | 210 | if (likely(total >= PAGE_SIZE)) |
211 | return __copy_user_nocache(dst, src, size, 0); | ||
212 | else | ||
213 | return __copy_from_user_inatomic(dst, src, size); | ||
203 | } | 214 | } |
204 | 215 | ||
205 | unsigned long | 216 | unsigned long |
diff --git a/arch/x86/include/asm/vic.h b/arch/x86/include/asm/vic.h deleted file mode 100644 index 53100f35361..00000000000 --- a/arch/x86/include/asm/vic.h +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | /* Copyright (C) 1999,2001 | ||
2 | * | ||
3 | * Author: J.E.J.Bottomley@HansenPartnership.com | ||
4 | * | ||
5 | * Standard include definitions for the NCR Voyager Interrupt Controller */ | ||
6 | |||
7 | /* The eight CPI vectors. To activate a CPI, you write a bit mask | ||
8 | * corresponding to the processor set to be interrupted into the | ||
9 | * relevant register. That set of CPUs will then be interrupted with | ||
10 | * the CPI */ | ||
11 | static const int VIC_CPI_Registers[] = | ||
12 | {0xFC00, 0xFC01, 0xFC08, 0xFC09, | ||
13 | 0xFC10, 0xFC11, 0xFC18, 0xFC19 }; | ||
14 | |||
15 | #define VIC_PROC_WHO_AM_I 0xfc29 | ||
16 | # define QUAD_IDENTIFIER 0xC0 | ||
17 | # define EIGHT_SLOT_IDENTIFIER 0xE0 | ||
18 | #define QIC_EXTENDED_PROCESSOR_SELECT 0xFC72 | ||
19 | #define VIC_CPI_BASE_REGISTER 0xFC41 | ||
20 | #define VIC_PROCESSOR_ID 0xFC21 | ||
21 | # define VIC_CPU_MASQUERADE_ENABLE 0x8 | ||
22 | |||
23 | #define VIC_CLAIM_REGISTER_0 0xFC38 | ||
24 | #define VIC_CLAIM_REGISTER_1 0xFC39 | ||
25 | #define VIC_REDIRECT_REGISTER_0 0xFC60 | ||
26 | #define VIC_REDIRECT_REGISTER_1 0xFC61 | ||
27 | #define VIC_PRIORITY_REGISTER 0xFC20 | ||
28 | |||
29 | #define VIC_PRIMARY_MC_BASE 0xFC48 | ||
30 | #define VIC_SECONDARY_MC_BASE 0xFC49 | ||
31 | |||
32 | #define QIC_PROCESSOR_ID 0xFC71 | ||
33 | # define QIC_CPUID_ENABLE 0x08 | ||
34 | |||
35 | #define QIC_VIC_CPI_BASE_REGISTER 0xFC79 | ||
36 | #define QIC_CPI_BASE_REGISTER 0xFC7A | ||
37 | |||
38 | #define QIC_MASK_REGISTER0 0xFC80 | ||
39 | /* NOTE: these are masked high, enabled low */ | ||
40 | # define QIC_PERF_TIMER 0x01 | ||
41 | # define QIC_LPE 0x02 | ||
42 | # define QIC_SYS_INT 0x04 | ||
43 | # define QIC_CMN_INT 0x08 | ||
44 | /* at the moment, just enable CMN_INT, disable SYS_INT */ | ||
45 | # define QIC_DEFAULT_MASK0 (~(QIC_CMN_INT /* | VIC_SYS_INT */)) | ||
46 | #define QIC_MASK_REGISTER1 0xFC81 | ||
47 | # define QIC_BOOT_CPI_MASK 0xFE | ||
48 | /* Enable CPI's 1-6 inclusive */ | ||
49 | # define QIC_CPI_ENABLE 0x81 | ||
50 | |||
51 | #define QIC_INTERRUPT_CLEAR0 0xFC8A | ||
52 | #define QIC_INTERRUPT_CLEAR1 0xFC8B | ||
53 | |||
54 | /* this is where we place the CPI vectors */ | ||
55 | #define VIC_DEFAULT_CPI_BASE 0xC0 | ||
56 | /* this is where we place the QIC CPI vectors */ | ||
57 | #define QIC_DEFAULT_CPI_BASE 0xD0 | ||
58 | |||
59 | #define VIC_BOOT_INTERRUPT_MASK 0xfe | ||
60 | |||
61 | extern void smp_vic_timer_interrupt(void); | ||
diff --git a/arch/x86/include/asm/voyager.h b/arch/x86/include/asm/voyager.h deleted file mode 100644 index c1635d43616..00000000000 --- a/arch/x86/include/asm/voyager.h +++ /dev/null | |||
@@ -1,571 +0,0 @@ | |||
1 | /* Copyright (C) 1999,2001 | ||
2 | * | ||
3 | * Author: J.E.J.Bottomley@HansenPartnership.com | ||
4 | * | ||
5 | * Standard include definitions for the NCR Voyager system */ | ||
6 | |||
7 | #undef VOYAGER_DEBUG | ||
8 | #undef VOYAGER_CAT_DEBUG | ||
9 | |||
10 | #ifdef VOYAGER_DEBUG | ||
11 | #define VDEBUG(x) printk x | ||
12 | #else | ||
13 | #define VDEBUG(x) | ||
14 | #endif | ||
15 | |||
16 | /* There are three levels of voyager machine: 3,4 and 5. The rule is | ||
17 | * if it's less than 3435 it's a Level 3 except for a 3360 which is | ||
18 | * a level 4. A 3435 or above is a Level 5 */ | ||
19 | #define VOYAGER_LEVEL5_AND_ABOVE 0x3435 | ||
20 | #define VOYAGER_LEVEL4 0x3360 | ||
21 | |||
22 | /* The L4 DINO ASIC */ | ||
23 | #define VOYAGER_DINO 0x43 | ||
24 | |||
25 | /* voyager ports in standard I/O space */ | ||
26 | #define VOYAGER_MC_SETUP 0x96 | ||
27 | |||
28 | |||
29 | #define VOYAGER_CAT_CONFIG_PORT 0x97 | ||
30 | # define VOYAGER_CAT_DESELECT 0xff | ||
31 | #define VOYAGER_SSPB_RELOCATION_PORT 0x98 | ||
32 | |||
33 | /* Valid CAT controller commands */ | ||
34 | /* start instruction register cycle */ | ||
35 | #define VOYAGER_CAT_IRCYC 0x01 | ||
36 | /* start data register cycle */ | ||
37 | #define VOYAGER_CAT_DRCYC 0x02 | ||
38 | /* move to execute state */ | ||
39 | #define VOYAGER_CAT_RUN 0x0F | ||
40 | /* end operation */ | ||
41 | #define VOYAGER_CAT_END 0x80 | ||
42 | /* hold in idle state */ | ||
43 | #define VOYAGER_CAT_HOLD 0x90 | ||
44 | /* single step an "intest" vector */ | ||
45 | #define VOYAGER_CAT_STEP 0xE0 | ||
46 | /* return cat controller to CLEMSON mode */ | ||
47 | #define VOYAGER_CAT_CLEMSON 0xFF | ||
48 | |||
49 | /* the default cat command header */ | ||
50 | #define VOYAGER_CAT_HEADER 0x7F | ||
51 | |||
52 | /* the range of possible CAT module ids in the system */ | ||
53 | #define VOYAGER_MIN_MODULE 0x10 | ||
54 | #define VOYAGER_MAX_MODULE 0x1f | ||
55 | |||
56 | /* The voyager registers per asic */ | ||
57 | #define VOYAGER_ASIC_ID_REG 0x00 | ||
58 | #define VOYAGER_ASIC_TYPE_REG 0x01 | ||
59 | /* the sub address registers can be made auto incrementing on reads */ | ||
60 | #define VOYAGER_AUTO_INC_REG 0x02 | ||
61 | # define VOYAGER_AUTO_INC 0x04 | ||
62 | # define VOYAGER_NO_AUTO_INC 0xfb | ||
63 | #define VOYAGER_SUBADDRDATA 0x03 | ||
64 | #define VOYAGER_SCANPATH 0x05 | ||
65 | # define VOYAGER_CONNECT_ASIC 0x01 | ||
66 | # define VOYAGER_DISCONNECT_ASIC 0xfe | ||
67 | #define VOYAGER_SUBADDRLO 0x06 | ||
68 | #define VOYAGER_SUBADDRHI 0x07 | ||
69 | #define VOYAGER_SUBMODSELECT 0x08 | ||
70 | #define VOYAGER_SUBMODPRESENT 0x09 | ||
71 | |||
72 | #define VOYAGER_SUBADDR_LO 0xff | ||
73 | #define VOYAGER_SUBADDR_HI 0xffff | ||
74 | |||
75 | /* the maximum size of a scan path -- used to form instructions */ | ||
76 | #define VOYAGER_MAX_SCAN_PATH 0x100 | ||
77 | /* the biggest possible register size (in bytes) */ | ||
78 | #define VOYAGER_MAX_REG_SIZE 4 | ||
79 | |||
80 | /* Total number of possible modules (including submodules) */ | ||
81 | #define VOYAGER_MAX_MODULES 16 | ||
82 | /* Largest number of asics per module */ | ||
83 | #define VOYAGER_MAX_ASICS_PER_MODULE 7 | ||
84 | |||
85 | /* the CAT asic of each module is always the first one */ | ||
86 | #define VOYAGER_CAT_ID 0 | ||
87 | #define VOYAGER_PSI 0x1a | ||
88 | |||
89 | /* voyager instruction operations and registers */ | ||
90 | #define VOYAGER_READ_CONFIG 0x1 | ||
91 | #define VOYAGER_WRITE_CONFIG 0x2 | ||
92 | #define VOYAGER_BYPASS 0xff | ||
93 | |||
94 | typedef struct voyager_asic { | ||
95 | __u8 asic_addr; /* ASIC address; Level 4 */ | ||
96 | __u8 asic_type; /* ASIC type */ | ||
97 | __u8 asic_id; /* ASIC id */ | ||
98 | __u8 jtag_id[4]; /* JTAG id */ | ||
99 | __u8 asic_location; /* Location within scan path; start w/ 0 */ | ||
100 | __u8 bit_location; /* Location within bit stream; start w/ 0 */ | ||
101 | __u8 ireg_length; /* Instruction register length */ | ||
102 | __u16 subaddr; /* Amount of sub address space */ | ||
103 | struct voyager_asic *next; /* Next asic in linked list */ | ||
104 | } voyager_asic_t; | ||
105 | |||
106 | typedef struct voyager_module { | ||
107 | __u8 module_addr; /* Module address */ | ||
108 | __u8 scan_path_connected; /* Scan path connected */ | ||
109 | __u16 ee_size; /* Size of the EEPROM */ | ||
110 | __u16 num_asics; /* Number of Asics */ | ||
111 | __u16 inst_bits; /* Instruction bits in the scan path */ | ||
112 | __u16 largest_reg; /* Largest register in the scan path */ | ||
113 | __u16 smallest_reg; /* Smallest register in the scan path */ | ||
114 | voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */ | ||
115 | struct voyager_module *submodule; /* Submodule pointer */ | ||
116 | struct voyager_module *next; /* Next module in linked list */ | ||
117 | } voyager_module_t; | ||
118 | |||
119 | typedef struct voyager_eeprom_hdr { | ||
120 | __u8 module_id[4]; | ||
121 | __u8 version_id; | ||
122 | __u8 config_id; | ||
123 | __u16 boundry_id; /* boundary scan id */ | ||
124 | __u16 ee_size; /* size of EEPROM */ | ||
125 | __u8 assembly[11]; /* assembly # */ | ||
126 | __u8 assembly_rev; /* assembly rev */ | ||
127 | __u8 tracer[4]; /* tracer number */ | ||
128 | __u16 assembly_cksum; /* asm checksum */ | ||
129 | __u16 power_consump; /* pwr requirements */ | ||
130 | __u16 num_asics; /* number of asics */ | ||
131 | __u16 bist_time; /* min. bist time */ | ||
132 | __u16 err_log_offset; /* error log offset */ | ||
133 | __u16 scan_path_offset;/* scan path offset */ | ||
134 | __u16 cct_offset; | ||
135 | __u16 log_length; /* length of err log */ | ||
136 | __u16 xsum_end; /* offset to end of | ||
137 | checksum */ | ||
138 | __u8 reserved[4]; | ||
139 | __u8 sflag; /* starting sentinal */ | ||
140 | __u8 part_number[13]; /* prom part number */ | ||
141 | __u8 version[10]; /* version number */ | ||
142 | __u8 signature[8]; | ||
143 | __u16 eeprom_chksum; | ||
144 | __u32 data_stamp_offset; | ||
145 | __u8 eflag ; /* ending sentinal */ | ||
146 | } __attribute__((packed)) voyager_eprom_hdr_t; | ||
147 | |||
148 | |||
149 | |||
150 | #define VOYAGER_EPROM_SIZE_OFFSET \ | ||
151 | ((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size))) | ||
152 | #define VOYAGER_XSUM_END_OFFSET 0x2a | ||
153 | |||
154 | /* the following three definitions are for internal table layouts | ||
155 | * in the module EPROMs. We really only care about the IDs and | ||
156 | * offsets */ | ||
157 | typedef struct voyager_sp_table { | ||
158 | __u8 asic_id; | ||
159 | __u8 bypass_flag; | ||
160 | __u16 asic_data_offset; | ||
161 | __u16 config_data_offset; | ||
162 | } __attribute__((packed)) voyager_sp_table_t; | ||
163 | |||
164 | typedef struct voyager_jtag_table { | ||
165 | __u8 icode[4]; | ||
166 | __u8 runbist[4]; | ||
167 | __u8 intest[4]; | ||
168 | __u8 samp_preld[4]; | ||
169 | __u8 ireg_len; | ||
170 | } __attribute__((packed)) voyager_jtt_t; | ||
171 | |||
172 | typedef struct voyager_asic_data_table { | ||
173 | __u8 jtag_id[4]; | ||
174 | __u16 length_bsr; | ||
175 | __u16 length_bist_reg; | ||
176 | __u32 bist_clk; | ||
177 | __u16 subaddr_bits; | ||
178 | __u16 seed_bits; | ||
179 | __u16 sig_bits; | ||
180 | __u16 jtag_offset; | ||
181 | } __attribute__((packed)) voyager_at_t; | ||
182 | |||
183 | /* Voyager Interrupt Controller (VIC) registers */ | ||
184 | |||
185 | /* Base to add to Cross Processor Interrupts (CPIs) when triggering | ||
186 | * the CPU IRQ line */ | ||
187 | /* register defines for the WCBICs (one per processor) */ | ||
188 | #define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */ | ||
189 | #define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */ | ||
190 | #define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */ | ||
191 | #define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */ | ||
192 | #define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */ | ||
193 | #define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */ | ||
194 | #define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */ | ||
195 | #define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */ | ||
196 | |||
197 | |||
198 | /* top of memory registers */ | ||
199 | #define VOYAGER_WCBIC_TOM_L 0x4 | ||
200 | #define VOYAGER_WCBIC_TOM_H 0x5 | ||
201 | |||
202 | /* register defines for Voyager Memory Contol (VMC) | ||
203 | * these are present on L4 machines only */ | ||
204 | #define VOYAGER_VMC1 0x81 | ||
205 | #define VOYAGER_VMC2 0x91 | ||
206 | #define VOYAGER_VMC3 0xa1 | ||
207 | #define VOYAGER_VMC4 0xb1 | ||
208 | |||
209 | /* VMC Ports */ | ||
210 | #define VOYAGER_VMC_MEMORY_SETUP 0x9 | ||
211 | # define VMC_Interleaving 0x01 | ||
212 | # define VMC_4Way 0x02 | ||
213 | # define VMC_EvenCacheLines 0x04 | ||
214 | # define VMC_HighLine 0x08 | ||
215 | # define VMC_Start0_Enable 0x20 | ||
216 | # define VMC_Start1_Enable 0x40 | ||
217 | # define VMC_Vremap 0x80 | ||
218 | #define VOYAGER_VMC_BANK_DENSITY 0xa | ||
219 | # define VMC_BANK_EMPTY 0 | ||
220 | # define VMC_BANK_4MB 1 | ||
221 | # define VMC_BANK_16MB 2 | ||
222 | # define VMC_BANK_64MB 3 | ||
223 | # define VMC_BANK0_MASK 0x03 | ||
224 | # define VMC_BANK1_MASK 0x0C | ||
225 | # define VMC_BANK2_MASK 0x30 | ||
226 | # define VMC_BANK3_MASK 0xC0 | ||
227 | |||
228 | /* Magellan Memory Controller (MMC) defines - present on L5 */ | ||
229 | #define VOYAGER_MMC_ASIC_ID 1 | ||
230 | /* the two memory modules corresponding to memory cards in the system */ | ||
231 | #define VOYAGER_MMC_MEMORY0_MODULE 0x14 | ||
232 | #define VOYAGER_MMC_MEMORY1_MODULE 0x15 | ||
233 | /* the Magellan Memory Address (MMA) defines */ | ||
234 | #define VOYAGER_MMA_ASIC_ID 2 | ||
235 | |||
236 | /* Submodule number for the Quad Baseboard */ | ||
237 | #define VOYAGER_QUAD_BASEBOARD 1 | ||
238 | |||
239 | /* ASIC defines for the Quad Baseboard */ | ||
240 | #define VOYAGER_QUAD_QDATA0 1 | ||
241 | #define VOYAGER_QUAD_QDATA1 2 | ||
242 | #define VOYAGER_QUAD_QABC 3 | ||
243 | |||
244 | /* Useful areas in extended CMOS */ | ||
245 | #define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a | ||
246 | #define VOYAGER_MEMORY_CLICKMAP 0xa23 | ||
247 | #define VOYAGER_DUMP_LOCATION 0xb1a | ||
248 | |||
249 | /* SUS In Control bit - used to tell SUS that we don't need to be | ||
250 | * babysat anymore */ | ||
251 | #define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff | ||
252 | # define VOYAGER_IN_CONTROL_FLAG 0x80 | ||
253 | |||
254 | /* Voyager PSI defines */ | ||
255 | #define VOYAGER_PSI_STATUS_REG 0x08 | ||
256 | # define PSI_DC_FAIL 0x01 | ||
257 | # define PSI_MON 0x02 | ||
258 | # define PSI_FAULT 0x04 | ||
259 | # define PSI_ALARM 0x08 | ||
260 | # define PSI_CURRENT 0x10 | ||
261 | # define PSI_DVM 0x20 | ||
262 | # define PSI_PSCFAULT 0x40 | ||
263 | # define PSI_STAT_CHG 0x80 | ||
264 | |||
265 | #define VOYAGER_PSI_SUPPLY_REG 0x8000 | ||
266 | /* read */ | ||
267 | # define PSI_FAIL_DC 0x01 | ||
268 | # define PSI_FAIL_AC 0x02 | ||
269 | # define PSI_MON_INT 0x04 | ||
270 | # define PSI_SWITCH_OFF 0x08 | ||
271 | # define PSI_HX_OFF 0x10 | ||
272 | # define PSI_SECURITY 0x20 | ||
273 | # define PSI_CMOS_BATT_LOW 0x40 | ||
274 | # define PSI_CMOS_BATT_FAIL 0x80 | ||
275 | /* write */ | ||
276 | # define PSI_CLR_SWITCH_OFF 0x13 | ||
277 | # define PSI_CLR_HX_OFF 0x14 | ||
278 | # define PSI_CLR_CMOS_BATT_FAIL 0x17 | ||
279 | |||
280 | #define VOYAGER_PSI_MASK 0x8001 | ||
281 | # define PSI_MASK_MASK 0x10 | ||
282 | |||
283 | #define VOYAGER_PSI_AC_FAIL_REG 0x8004 | ||
284 | #define AC_FAIL_STAT_CHANGE 0x80 | ||
285 | |||
286 | #define VOYAGER_PSI_GENERAL_REG 0x8007 | ||
287 | /* read */ | ||
288 | # define PSI_SWITCH_ON 0x01 | ||
289 | # define PSI_SWITCH_ENABLED 0x02 | ||
290 | # define PSI_ALARM_ENABLED 0x08 | ||
291 | # define PSI_SECURE_ENABLED 0x10 | ||
292 | # define PSI_COLD_RESET 0x20 | ||
293 | # define PSI_COLD_START 0x80 | ||
294 | /* write */ | ||
295 | # define PSI_POWER_DOWN 0x10 | ||
296 | # define PSI_SWITCH_DISABLE 0x01 | ||
297 | # define PSI_SWITCH_ENABLE 0x11 | ||
298 | # define PSI_CLEAR 0x12 | ||
299 | # define PSI_ALARM_DISABLE 0x03 | ||
300 | # define PSI_ALARM_ENABLE 0x13 | ||
301 | # define PSI_CLEAR_COLD_RESET 0x05 | ||
302 | # define PSI_SET_COLD_RESET 0x15 | ||
303 | # define PSI_CLEAR_COLD_START 0x07 | ||
304 | # define PSI_SET_COLD_START 0x17 | ||
305 | |||
306 | |||
307 | |||
308 | struct voyager_bios_info { | ||
309 | __u8 len; | ||
310 | __u8 major; | ||
311 | __u8 minor; | ||
312 | __u8 debug; | ||
313 | __u8 num_classes; | ||
314 | __u8 class_1; | ||
315 | __u8 class_2; | ||
316 | }; | ||
317 | |||
318 | /* The following structures and definitions are for the Kernel/SUS | ||
319 | * interface these are needed to find out how SUS initialised any Quad | ||
320 | * boards in the system */ | ||
321 | |||
322 | #define NUMBER_OF_MC_BUSSES 2 | ||
323 | #define SLOTS_PER_MC_BUS 8 | ||
324 | #define MAX_CPUS 16 /* 16 way CPU system */ | ||
325 | #define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */ | ||
326 | #define MAX_CACHE_LEVELS 4 /* # of cache levels supported */ | ||
327 | #define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */ | ||
328 | #define NUMBER_OF_POS_REGS 8 | ||
329 | |||
330 | typedef struct { | ||
331 | __u8 MC_Slot; | ||
332 | __u8 POS_Values[NUMBER_OF_POS_REGS]; | ||
333 | } __attribute__((packed)) MC_SlotInformation_t; | ||
334 | |||
335 | struct QuadDescription { | ||
336 | __u8 Type; /* for type 0 (DYADIC or MONADIC) all fields | ||
337 | * will be zero except for slot */ | ||
338 | __u8 StructureVersion; | ||
339 | __u32 CPI_BaseAddress; | ||
340 | __u32 LARC_BankSize; | ||
341 | __u32 LocalMemoryStateBits; | ||
342 | __u8 Slot; /* Processor slots 1 - 4 */ | ||
343 | } __attribute__((packed)); | ||
344 | |||
345 | struct ProcBoardInfo { | ||
346 | __u8 Type; | ||
347 | __u8 StructureVersion; | ||
348 | __u8 NumberOfBoards; | ||
349 | struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS]; | ||
350 | } __attribute__((packed)); | ||
351 | |||
352 | struct CacheDescription { | ||
353 | __u8 Level; | ||
354 | __u32 TotalSize; | ||
355 | __u16 LineSize; | ||
356 | __u8 Associativity; | ||
357 | __u8 CacheType; | ||
358 | __u8 WriteType; | ||
359 | __u8 Number_CPUs_SharedBy; | ||
360 | __u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS]; | ||
361 | |||
362 | } __attribute__((packed)); | ||
363 | |||
364 | struct CPU_Description { | ||
365 | __u8 CPU_HardwareId; | ||
366 | char *FRU_String; | ||
367 | __u8 NumberOfCacheLevels; | ||
368 | struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS]; | ||
369 | } __attribute__((packed)); | ||
370 | |||
371 | struct CPU_Info { | ||
372 | __u8 Type; | ||
373 | __u8 StructureVersion; | ||
374 | __u8 NumberOf_CPUs; | ||
375 | struct CPU_Description CPU_Data[MAX_CPUS]; | ||
376 | } __attribute__((packed)); | ||
377 | |||
378 | |||
379 | /* | ||
380 | * This structure will be used by SUS and the OS. | ||
381 | * The assumption about this structure is that no blank space is | ||
382 | * packed in it by our friend the compiler. | ||
383 | */ | ||
384 | typedef struct { | ||
385 | __u8 Mailbox_SUS; /* Written to by SUS to give | ||
386 | commands/response to the OS */ | ||
387 | __u8 Mailbox_OS; /* Written to by the OS to give | ||
388 | commands/response to SUS */ | ||
389 | __u8 SUS_MailboxVersion; /* Tells the OS which iteration of the | ||
390 | interface SUS supports */ | ||
391 | __u8 OS_MailboxVersion; /* Tells SUS which iteration of the | ||
392 | interface the OS supports */ | ||
393 | __u32 OS_Flags; /* Flags set by the OS as info for | ||
394 | SUS */ | ||
395 | __u32 SUS_Flags; /* Flags set by SUS as info | ||
396 | for the OS */ | ||
397 | __u32 WatchDogPeriod; /* Watchdog period (in seconds) which | ||
398 | the DP uses to see if the OS | ||
399 | is dead */ | ||
400 | __u32 WatchDogCount; /* Updated by the OS on every tic. */ | ||
401 | __u32 MemoryFor_SUS_ErrorLog; /* Flat 32 bit address which tells SUS | ||
402 | where to stuff the SUS error log | ||
403 | on a dump */ | ||
404 | MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS]; | ||
405 | /* Storage for MCA POS data */ | ||
406 | /* All new SECOND_PASS_INTERFACE fields added from this point */ | ||
407 | struct ProcBoardInfo *BoardData; | ||
408 | struct CPU_Info *CPU_Data; | ||
409 | /* All new fields must be added from this point */ | ||
410 | } Voyager_KernelSUS_Mbox_t; | ||
411 | |||
412 | /* structure for finding the right memory address to send a QIC CPI to */ | ||
413 | struct voyager_qic_cpi { | ||
414 | /* Each cache line (32 bytes) can trigger a cpi. The cpi | ||
415 | * read/write may occur anywhere in the cache line---pick the | ||
416 | * middle to be safe */ | ||
417 | struct { | ||
418 | __u32 pad1[3]; | ||
419 | __u32 cpi; | ||
420 | __u32 pad2[4]; | ||
421 | } qic_cpi[8]; | ||
422 | }; | ||
423 | |||
424 | struct voyager_status { | ||
425 | __u32 power_fail:1; | ||
426 | __u32 switch_off:1; | ||
427 | __u32 request_from_kernel:1; | ||
428 | }; | ||
429 | |||
430 | struct voyager_psi_regs { | ||
431 | __u8 cat_id; | ||
432 | __u8 cat_dev; | ||
433 | __u8 cat_control; | ||
434 | __u8 subaddr; | ||
435 | __u8 dummy4; | ||
436 | __u8 checkbit; | ||
437 | __u8 subaddr_low; | ||
438 | __u8 subaddr_high; | ||
439 | __u8 intstatus; | ||
440 | __u8 stat1; | ||
441 | __u8 stat3; | ||
442 | __u8 fault; | ||
443 | __u8 tms; | ||
444 | __u8 gen; | ||
445 | __u8 sysconf; | ||
446 | __u8 dummy15; | ||
447 | }; | ||
448 | |||
449 | struct voyager_psi_subregs { | ||
450 | __u8 supply; | ||
451 | __u8 mask; | ||
452 | __u8 present; | ||
453 | __u8 DCfail; | ||
454 | __u8 ACfail; | ||
455 | __u8 fail; | ||
456 | __u8 UPSfail; | ||
457 | __u8 genstatus; | ||
458 | }; | ||
459 | |||
460 | struct voyager_psi { | ||
461 | struct voyager_psi_regs regs; | ||
462 | struct voyager_psi_subregs subregs; | ||
463 | }; | ||
464 | |||
465 | struct voyager_SUS { | ||
466 | #define VOYAGER_DUMP_BUTTON_NMI 0x1 | ||
467 | #define VOYAGER_SUS_VALID 0x2 | ||
468 | #define VOYAGER_SYSINT_COMPLETE 0x3 | ||
469 | __u8 SUS_mbox; | ||
470 | #define VOYAGER_NO_COMMAND 0x0 | ||
471 | #define VOYAGER_IGNORE_DUMP 0x1 | ||
472 | #define VOYAGER_DO_DUMP 0x2 | ||
473 | #define VOYAGER_SYSINT_HANDSHAKE 0x3 | ||
474 | #define VOYAGER_DO_MEM_DUMP 0x4 | ||
475 | #define VOYAGER_SYSINT_WAS_RECOVERED 0x5 | ||
476 | __u8 kernel_mbox; | ||
477 | #define VOYAGER_MAILBOX_VERSION 0x10 | ||
478 | __u8 SUS_version; | ||
479 | __u8 kernel_version; | ||
480 | #define VOYAGER_OS_HAS_SYSINT 0x1 | ||
481 | #define VOYAGER_OS_IN_PROGRESS 0x2 | ||
482 | #define VOYAGER_UPDATING_WDPERIOD 0x4 | ||
483 | __u32 kernel_flags; | ||
484 | #define VOYAGER_SUS_BOOTING 0x1 | ||
485 | #define VOYAGER_SUS_IN_PROGRESS 0x2 | ||
486 | __u32 SUS_flags; | ||
487 | __u32 watchdog_period; | ||
488 | __u32 watchdog_count; | ||
489 | __u32 SUS_errorlog; | ||
490 | /* lots of system configuration stuff under here */ | ||
491 | }; | ||
492 | |||
493 | /* Variables exported by voyager_smp */ | ||
494 | extern __u32 voyager_extended_vic_processors; | ||
495 | extern __u32 voyager_allowed_boot_processors; | ||
496 | extern __u32 voyager_quad_processors; | ||
497 | extern struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS]; | ||
498 | extern struct voyager_SUS *voyager_SUS; | ||
499 | |||
500 | /* variables exported always */ | ||
501 | extern struct task_struct *voyager_thread; | ||
502 | extern int voyager_level; | ||
503 | extern struct voyager_status voyager_status; | ||
504 | |||
505 | /* functions exported by the voyager and voyager_smp modules */ | ||
506 | extern int voyager_cat_readb(__u8 module, __u8 asic, int reg); | ||
507 | extern void voyager_cat_init(void); | ||
508 | extern void voyager_detect(struct voyager_bios_info *); | ||
509 | extern void voyager_trap_init(void); | ||
510 | extern void voyager_setup_irqs(void); | ||
511 | extern int voyager_memory_detect(int region, __u32 *addr, __u32 *length); | ||
512 | extern void voyager_smp_intr_init(void); | ||
513 | extern __u8 voyager_extended_cmos_read(__u16 cmos_address); | ||
514 | extern void voyager_smp_dump(void); | ||
515 | extern void voyager_timer_interrupt(void); | ||
516 | extern void smp_local_timer_interrupt(void); | ||
517 | extern void voyager_power_off(void); | ||
518 | extern void smp_voyager_power_off(void *dummy); | ||
519 | extern void voyager_restart(void); | ||
520 | extern void voyager_cat_power_off(void); | ||
521 | extern void voyager_cat_do_common_interrupt(void); | ||
522 | extern void voyager_handle_nmi(void); | ||
523 | extern void voyager_smp_intr_init(void); | ||
524 | /* Commands for the following are */ | ||
525 | #define VOYAGER_PSI_READ 0 | ||
526 | #define VOYAGER_PSI_WRITE 1 | ||
527 | #define VOYAGER_PSI_SUBREAD 2 | ||
528 | #define VOYAGER_PSI_SUBWRITE 3 | ||
529 | extern void voyager_cat_psi(__u8, __u16, __u8 *); | ||
530 | |||
531 | /* These define the CPIs we use in linux */ | ||
532 | #define VIC_CPI_LEVEL0 0 | ||
533 | #define VIC_CPI_LEVEL1 1 | ||
534 | /* now the fake CPIs */ | ||
535 | #define VIC_TIMER_CPI 2 | ||
536 | #define VIC_INVALIDATE_CPI 3 | ||
537 | #define VIC_RESCHEDULE_CPI 4 | ||
538 | #define VIC_ENABLE_IRQ_CPI 5 | ||
539 | #define VIC_CALL_FUNCTION_CPI 6 | ||
540 | #define VIC_CALL_FUNCTION_SINGLE_CPI 7 | ||
541 | |||
542 | /* Now the QIC CPIs: Since we don't need the two initial levels, | ||
543 | * these are 2 less than the VIC CPIs */ | ||
544 | #define QIC_CPI_OFFSET 1 | ||
545 | #define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) | ||
546 | #define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) | ||
547 | #define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) | ||
548 | #define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) | ||
549 | #define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) | ||
550 | #define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET) | ||
551 | |||
552 | #define VIC_START_FAKE_CPI VIC_TIMER_CPI | ||
553 | #define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI | ||
554 | |||
555 | /* this is the SYS_INT CPI. */ | ||
556 | #define VIC_SYS_INT 8 | ||
557 | #define VIC_CMN_INT 15 | ||
558 | |||
559 | /* This is the boot CPI for alternate processors. It gets overwritten | ||
560 | * by the above once the system has activated all available processors */ | ||
561 | #define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 | ||
562 | #define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) | ||
563 | |||
564 | extern asmlinkage void vic_cpi_interrupt(void); | ||
565 | extern asmlinkage void vic_sys_interrupt(void); | ||
566 | extern asmlinkage void vic_cmn_interrupt(void); | ||
567 | extern asmlinkage void qic_timer_interrupt(void); | ||
568 | extern asmlinkage void qic_invalidate_interrupt(void); | ||
569 | extern asmlinkage void qic_reschedule_interrupt(void); | ||
570 | extern asmlinkage void qic_enable_irq_interrupt(void); | ||
571 | extern asmlinkage void qic_call_function_interrupt(void); | ||