Patched in Tegra support.

254 files changed, 3748 insertions, 8693 deletions

diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild
index 7f669853317..6fa90a845e4 100644
--- a/arch/x86/include/asm/Kbuild
+++ b/arch/x86/include/asm/Kbuild
@@ -1,7 +1,25 @@
+include include/asm-generic/Kbuild.asm
 
-
-genhdr-y += unistd_32.h
-genhdr-y += unistd_64.h
-genhdr-y += unistd_x32.h
-
-generic-y += clkdev.h
+header-y += boot.h
+header-y += bootparam.h
+header-y += debugreg.h
+header-y += e820.h
+header-y += hw_breakpoint.h
+header-y += hyperv.h
+header-y += ist.h
+header-y += ldt.h
+header-y += mce.h
+header-y += msr-index.h
+header-y += msr.h
+header-y += mtrr.h
+header-y += posix_types_32.h
+header-y += posix_types_64.h
+header-y += prctl.h
+header-y += processor-flags.h
+header-y += ptrace-abi.h
+header-y += sigcontext32.h
+header-y += ucontext.h
+header-y += unistd_32.h
+header-y += unistd_64.h
+header-y += vm86.h
+header-y += vsyscall.h
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 0c44630d178..610001d385d 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -29,7 +29,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/mpspec.h>
-#include <asm/realmode.h>
+#include <asm/trampoline.h>
 
 #define COMPILER_DEPENDENT_INT64   long long
 #define COMPILER_DEPENDENT_UINT64  unsigned long long
@@ -117,8 +117,11 @@ static inline void acpi_disable_pci(void)
 /* Low-level suspend routine. */
 extern int acpi_suspend_lowlevel(void);
 
-/* Physical address to resume after wakeup */
-#define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start))
+extern const unsigned char acpi_wakeup_code[];
+#define acpi_wakeup_address (__pa(TRAMPOLINE_SYM(acpi_wakeup_code)))
+
+/* early initialization routine */
+extern void acpi_reserve_wakeup_memory(void);
 
 /*
  * Check if the CPU can handle C2 and deeper
diff --git a/arch/x86/include/asm/alternative-asm.h b/arch/x86/include/asm/alternative-asm.h
index 372231c22a4..091508b533b 100644
--- a/arch/x86/include/asm/alternative-asm.h
+++ b/arch/x86/include/asm/alternative-asm.h
@@ -1,17 +1,14 @@
-#ifndef _ASM_X86_ALTERNATIVE_ASM_H
-#define _ASM_X86_ALTERNATIVE_ASM_H
-
 #ifdef __ASSEMBLY__
 
 #include <asm/asm.h>
 
 #ifdef CONFIG_SMP
         .macro LOCK_PREFIX
-672:    lock
-        .pushsection .smp_locks,"a"
+1:      lock
+        .section .smp_locks,"a"
         .balign 4
-        .long 672b - .
-        .popsection
+        .long 1b - .
+        .previous
         .endm
 #else
         .macro LOCK_PREFIX
@@ -27,5 +24,3 @@
 .endm
 
 #endif  /*  __ASSEMBLY__  */
-
-#endif /* _ASM_X86_ALTERNATIVE_ASM_H */
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 58ed6d96a6a..37ad100a221 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -29,10 +29,10 @@
 
 #ifdef CONFIG_SMP
 #define LOCK_PREFIX_HERE \
-                ".pushsection .smp_locks,\"a\"\n"       \
-                ".balign 4\n"                           \
-                ".long 671f - .\n" /* offset */         \
-                ".popsection\n"                         \
+                ".section .smp_locks,\"a\"\n"   \
+                ".balign 4\n"                   \
+                ".long 671f - .\n" /* offset */ \
+                ".previous\n"                   \
                 "671:"
 
 #define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "
@@ -60,7 +60,7 @@ extern void alternatives_smp_module_add(struct module *mod, char *name,
                                         void *locks, void *locks_end,
                                         void *text, void *text_end);
 extern void alternatives_smp_module_del(struct module *mod);
-extern void alternatives_enable_smp(void);
+extern void alternatives_smp_switch(int smp);
 extern int alternatives_text_reserved(void *start, void *end);
 extern bool skip_smp_alternatives;
 #else
@@ -68,61 +68,30 @@ static inline void alternatives_smp_module_add(struct module *mod, char *name,
                                                void *locks, void *locks_end,
                                                void *text, void *text_end) {}
 static inline void alternatives_smp_module_del(struct module *mod) {}
-static inline void alternatives_enable_smp(void) {}
+static inline void alternatives_smp_switch(int smp) {}
 static inline int alternatives_text_reserved(void *start, void *end)
 {
         return 0;
 }
 #endif  /* CONFIG_SMP */
 
-#define OLDINSTR(oldinstr)      "661:\n\t" oldinstr "\n662:\n"
-
-#define b_replacement(number)   "663"#number
-#define e_replacement(number)   "664"#number
-
-#define alt_slen "662b-661b"
-#define alt_rlen(number) e_replacement(number)"f-"b_replacement(number)"f"
-
-#define ALTINSTR_ENTRY(feature, number)                                       \
-        " .long 661b - .\n"                             /* label           */ \
-        " .long " b_replacement(number)"f - .\n"        /* new instruction */ \
-        " .word " __stringify(feature) "\n"             /* feature bit     */ \
-        " .byte " alt_slen "\n"                         /* source len      */ \
-        " .byte " alt_rlen(number) "\n"                 /* replacement len */
-
-#define DISCARD_ENTRY(number)                           /* rlen <= slen */    \
-        " .byte 0xff + (" alt_rlen(number) ") - (" alt_slen ")\n"
-
-#define ALTINSTR_REPLACEMENT(newinstr, feature, number) /* replacement */     \
-        b_replacement(number)":\n\t" newinstr "\n" e_replacement(number) ":\n\t"
-
 /* alternative assembly primitive: */
 #define ALTERNATIVE(oldinstr, newinstr, feature)                        \
-        OLDINSTR(oldinstr)                                              \
-        ".pushsection .altinstructions,\"a\"\n"                         \
-        ALTINSTR_ENTRY(feature, 1)                                      \
-        ".popsection\n"                                                 \
-        ".pushsection .discard,\"aw\",@progbits\n"                      \
-        DISCARD_ENTRY(1)                                                \
-        ".popsection\n"                                                 \
-        ".pushsection .altinstr_replacement, \"ax\"\n"                  \
-        ALTINSTR_REPLACEMENT(newinstr, feature, 1)                      \
-        ".popsection"
-
-#define ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, feature2)\
-        OLDINSTR(oldinstr)                                              \
-        ".pushsection .altinstructions,\"a\"\n"                         \
-        ALTINSTR_ENTRY(feature1, 1)                                     \
-        ALTINSTR_ENTRY(feature2, 2)                                     \
-        ".popsection\n"                                                 \
-        ".pushsection .discard,\"aw\",@progbits\n"                      \
-        DISCARD_ENTRY(1)                                                \
-        DISCARD_ENTRY(2)                                                \
-        ".popsection\n"                                                 \
-        ".pushsection .altinstr_replacement, \"ax\"\n"                  \
-        ALTINSTR_REPLACEMENT(newinstr1, feature1, 1)                    \
-        ALTINSTR_REPLACEMENT(newinstr2, feature2, 2)                    \
-        ".popsection"
+                                                                        \
+      "661:\n\t" oldinstr "\n662:\n"                                    \
+      ".section .altinstructions,\"a\"\n"                               \
+      "  .long 661b - .\n"                      /* label           */   \
+      "  .long 663f - .\n"                      /* new instruction */   \
+      "  .word " __stringify(feature) "\n"      /* feature bit     */   \
+      "  .byte 662b-661b\n"                     /* sourcelen       */   \
+      "  .byte 664f-663f\n"                     /* replacementlen  */   \
+      ".previous\n"                                                     \
+      ".section .discard,\"aw\",@progbits\n"                            \
+      "  .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */   \
+      ".previous\n"                                                     \
+      ".section .altinstr_replacement, \"ax\"\n"                        \
+      "663:\n\t" newinstr "\n664:\n"            /* replacement     */   \
+      ".previous"
 
 /*
  * This must be included *after* the definition of ALTERNATIVE due to
@@ -171,30 +140,11 @@ static inline int alternatives_text_reserved(void *start, void *end)
                 : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
 
 /*
- * Like alternative_call, but there are two features and respective functions.
- * If CPU has feature2, function2 is used.
- * Otherwise, if CPU has feature1, function1 is used.
- * Otherwise, old function is used.
- */
-#define alternative_call_2(oldfunc, newfunc1, feature1, newfunc2, feature2,   \
-                           output, input...)                                  \
-        asm volatile (ALTERNATIVE_2("call %P[old]", "call %P[new1]", feature1,\
-                "call %P[new2]", feature2)                                    \
-                : output : [old] "i" (oldfunc), [new1] "i" (newfunc1),        \
-                [new2] "i" (newfunc2), ## input)
-
-/*
  * use this macro(s) if you need more than one output parameter
  * in alternative_io
  */
 #define ASM_OUTPUT2(a...) a
 
-/*
- * use this macro if you need clobbers but no inputs in
- * alternative_{input,io,call}()
- */
-#define ASM_NO_INPUT_CLOBBER(clbr...) "i" (0) : clbr
-
 struct paravirt_patch_site;
 #ifdef CONFIG_PARAVIRT
 void apply_paravirt(struct paravirt_patch_site *start,
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index b3341e9cd8f..78a1eff7422 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -21,36 +21,9 @@ extern int amd_numa_init(void);
 extern int amd_get_subcaches(int);
 extern int amd_set_subcaches(int, int);
 
-struct amd_l3_cache {
-        unsigned indices;
-        u8       subcaches[4];
-};
-
-struct threshold_block {
-        unsigned int            block;
-        unsigned int            bank;
-        unsigned int            cpu;
-        u32                     address;
-        u16                     interrupt_enable;
-        bool                    interrupt_capable;
-        u16                     threshold_limit;
-        struct kobject          kobj;
-        struct list_head        miscj;
-};
-
-struct threshold_bank {
-        struct kobject          *kobj;
-        struct threshold_block  *blocks;
-
-        /* initialized to the number of CPUs on the node sharing this bank */
-        atomic_t                cpus;
-};
-
 struct amd_northbridge {
         struct pci_dev *misc;
         struct pci_dev *link;
-        struct amd_l3_cache l3_cache;
-        struct threshold_bank *bank4;
 };
 
 struct amd_northbridge_info {
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 33880342223..9b7273cb219 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -11,6 +11,7 @@
 #include <linux/atomic.h>
 #include <asm/fixmap.h>
 #include <asm/mpspec.h>
+#include <asm/system.h>
 #include <asm/msr.h>
 
 #define ARCH_APICTIMER_STOPS_ON_C3      1
@@ -48,7 +49,6 @@ extern unsigned int apic_verbosity;
 extern int local_apic_timer_c2_ok;
 
 extern int disable_apic;
-extern unsigned int lapic_timer_frequency;
 
 #ifdef CONFIG_SMP
 extern void __inquire_remote_apic(int apicid);
@@ -138,11 +138,6 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 }
 
-static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
-{
-        wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
-}
-
 static inline u32 native_apic_msr_read(u32 reg)
 {
         u64 msr;
@@ -180,7 +175,6 @@ static inline u64 native_x2apic_icr_read(void)
 }
 
 extern int x2apic_phys;
-extern int x2apic_preenabled;
 extern void check_x2apic(void);
 extern void enable_x2apic(void);
 extern void x2apic_icr_write(u32 low, u32 id);
@@ -203,9 +197,6 @@ static inline void x2apic_force_phys(void)
         x2apic_phys = 1;
 }
 #else
-static inline void disable_x2apic(void)
-{
-}
 static inline void check_x2apic(void)
 {
 }
@@ -220,7 +211,6 @@ static inline void x2apic_force_phys(void)
 {
 }
 
-#define nox2apic        0
 #define x2apic_preenabled 0
 #define x2apic_supported()      0
 #endif
@@ -292,7 +282,6 @@ struct apic {
 
         int (*probe)(void);
         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
-        int (*apic_id_valid)(int apicid);
         int (*apic_id_registered)(void);
 
         u32 irq_delivery_mode;
@@ -306,8 +295,7 @@ struct apic {
         unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
         unsigned long (*check_apicid_present)(int apicid);
 
-        void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
-                                         const struct cpumask *mask);
+        void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
         void (*init_apic_ldr)(void);
 
         void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
@@ -332,9 +320,9 @@ struct apic {
         unsigned long (*set_apic_id)(unsigned int id);
         unsigned long apic_id_mask;
 
-        int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
-                                      const struct cpumask *andmask,
-                                      unsigned int *apicid);
+        unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
+        unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
+                                               const struct cpumask *andmask);
 
         /* ipi */
         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
@@ -357,14 +345,6 @@ struct apic {
         /* apic ops */
         u32 (*read)(u32 reg);
         void (*write)(u32 reg, u32 v);
-        /*
-         * ->eoi_write() has the same signature as ->write().
-         *
-         * Drivers can support both ->eoi_write() and ->write() by passing the same
-         * callback value. Kernel can override ->eoi_write() and fall back
-         * on write for EOI.
-         */
-        void (*eoi_write)(u32 reg, u32 v);
         u64 (*icr_read)(void);
         void (*icr_write)(u32 low, u32 high);
         void (*wait_icr_idle)(void);
@@ -409,7 +389,7 @@ extern struct apic *apic;
  * to enforce the order with in them.
  */
 #define apic_driver(sym)                                        \
-        static const struct apic *__apicdrivers_##sym __used            \
+        static struct apic *__apicdrivers_##sym __used          \
         __aligned(sizeof(struct apic *))                        \
         __section(.apicdrivers) = { &sym }
 
@@ -429,7 +409,6 @@ extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 #endif
 
 #ifdef CONFIG_X86_LOCAL_APIC
-
 static inline u32 apic_read(u32 reg)
 {
         return apic->read(reg);
@@ -440,11 +419,6 @@ static inline void apic_write(u32 reg, u32 val)
         apic->write(reg, val);
 }
 
-static inline void apic_eoi(void)
-{
-        apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
-}
-
 static inline u64 apic_icr_read(void)
 {
         return apic->icr_read();
@@ -465,18 +439,14 @@ static inline u32 safe_apic_wait_icr_idle(void)
         return apic->safe_wait_icr_idle();
 }
 
-extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
-
 #else /* CONFIG_X86_LOCAL_APIC */
 
 static inline u32 apic_read(u32 reg) { return 0; }
 static inline void apic_write(u32 reg, u32 val) { }
-static inline void apic_eoi(void) { }
 static inline u64 apic_icr_read(void) { return 0; }
 static inline void apic_icr_write(u32 low, u32 high) { }
 static inline void apic_wait_icr_idle(void) { }
 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
-static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
 
 #endif /* CONFIG_X86_LOCAL_APIC */
 
@@ -486,7 +456,9 @@ static inline void ack_APIC_irq(void)
          * ack_APIC_irq() actually gets compiled as a single instruction
          * ... yummie.
          */
-        apic_eoi();
+
+        /* Docs say use 0 for future compatibility */
+        apic_write(APIC_EOI, 0);
 }
 
 static inline unsigned default_get_apic_id(unsigned long x)
@@ -541,12 +513,7 @@ static inline const struct cpumask *default_target_cpus(void)
 #endif
 }
 
-static inline const struct cpumask *online_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
-DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
+DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 
 
 static inline unsigned int read_apic_id(void)
@@ -558,11 +525,6 @@ static inline unsigned int read_apic_id(void)
         return apic->get_apic_id(reg);
 }
 
-static inline int default_apic_id_valid(int apicid)
-{
-        return (apicid < 255);
-}
-
 extern void default_setup_apic_routing(void);
 
 extern struct apic apic_noop;
@@ -595,50 +557,21 @@ static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 
 #endif
 
-static inline int
-flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                            const struct cpumask *andmask,
-                            unsigned int *apicid)
+static inline unsigned int
+default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 {
-        unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
-                                 cpumask_bits(andmask)[0] &
-                                 cpumask_bits(cpu_online_mask)[0] &
-                                 APIC_ALL_CPUS;
-
-        if (likely(cpu_mask)) {
-                *apicid = (unsigned int)cpu_mask;
-                return 0;
-        } else {
-                return -EINVAL;
-        }
+        return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
 }
 
-extern int
+static inline unsigned int
 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                               const struct cpumask *andmask,
-                               unsigned int *apicid);
-
-static inline void
-flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
-                              const struct cpumask *mask)
+                               const struct cpumask *andmask)
 {
-        /* Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
+        unsigned long mask1 = cpumask_bits(cpumask)[0];
+        unsigned long mask2 = cpumask_bits(andmask)[0];
+        unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 
-static inline void
-default_vector_allocation_domain(int cpu, struct cpumask *retmask,
-                                 const struct cpumask *mask)
-{
-        cpumask_copy(retmask, cpumask_of(cpu));
+        return (unsigned int)(mask1 & mask2 & mask3);
 }
 
 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
diff --git a/arch/x86/include/asm/apic_flat_64.h b/arch/x86/include/asm/apic_flat_64.h
deleted file mode 100644
index a2d31279644..00000000000
--- a/arch/x86/include/asm/apic_flat_64.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ASM_X86_APIC_FLAT_64_H
-#define _ASM_X86_APIC_FLAT_64_H
-
-extern void flat_init_apic_ldr(void);
-
-#endif
-
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index c46bb99d5fb..34595d5e103 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -37,7 +37,7 @@
 #define         APIC_ARBPRI_MASK        0xFFu
 #define APIC_PROCPRI    0xA0
 #define APIC_EOI        0xB0
-#define         APIC_EOI_ACK            0x0 /* Docs say 0 for future compat. */
+#define         APIC_EIO_ACK            0x0
 #define APIC_RRR        0xC0
 #define APIC_LDR        0xD0
 #define         APIC_LDR_MASK           (0xFFu << 24)
@@ -100,9 +100,7 @@
 #define         APIC_TIMER_BASE_CLKIN           0x0
 #define         APIC_TIMER_BASE_TMBASE          0x1
 #define         APIC_TIMER_BASE_DIV             0x2
-#define         APIC_LVT_TIMER_ONESHOT          (0 << 17)
 #define         APIC_LVT_TIMER_PERIODIC         (1 << 17)
-#define         APIC_LVT_TIMER_TSCDEADLINE      (2 << 17)
 #define         APIC_LVT_MASKED                 (1 << 16)
 #define         APIC_LVT_LEVEL_TRIGGER          (1 << 15)
 #define         APIC_LVT_REMOTE_IRR             (1 << 14)
@@ -144,7 +142,6 @@
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR   0x800
-#define XAPIC_ENABLE    (1UL << 11)
 #define X2APIC_ENABLE   (1UL << 10)
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/include/asm/archrandom.h b/arch/x86/include/asm/archrandom.h
deleted file mode 100644
index 0d9ec770f2f..00000000000
--- a/arch/x86/include/asm/archrandom.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the Linux kernel.
- *
- * Copyright (c) 2011, Intel Corporation
- * Authors: Fenghua Yu <fenghua.yu@intel.com>,
- *          H. Peter Anvin <hpa@linux.intel.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#ifndef ASM_X86_ARCHRANDOM_H
-#define ASM_X86_ARCHRANDOM_H
-
-#include <asm/processor.h>
-#include <asm/cpufeature.h>
-#include <asm/alternative.h>
-#include <asm/nops.h>
-
-#define RDRAND_RETRY_LOOPS      10
-
-#define RDRAND_INT      ".byte 0x0f,0xc7,0xf0"
-#ifdef CONFIG_X86_64
-# define RDRAND_LONG    ".byte 0x48,0x0f,0xc7,0xf0"
-#else
-# define RDRAND_LONG    RDRAND_INT
-#endif
-
-#ifdef CONFIG_ARCH_RANDOM
-
-#define GET_RANDOM(name, type, rdrand, nop)                     \
-static inline int name(type *v)                                 \
-{                                                               \
-        int ok;                                                 \
-        alternative_io("movl $0, %0\n\t"                        \
-                       nop,                                     \
-                       "\n1: " rdrand "\n\t"                    \
-                       "jc 2f\n\t"                              \
-                       "decl %0\n\t"                            \
-                       "jnz 1b\n\t"                             \
-                       "2:",                                    \
-                       X86_FEATURE_RDRAND,                      \
-                       ASM_OUTPUT2("=r" (ok), "=a" (*v)),       \
-                       "0" (RDRAND_RETRY_LOOPS));               \
-        return ok;                                              \
-}
-
-#ifdef CONFIG_X86_64
-
-GET_RANDOM(arch_get_random_long, unsigned long, RDRAND_LONG, ASM_NOP5);
-GET_RANDOM(arch_get_random_int, unsigned int, RDRAND_INT, ASM_NOP4);
-
-#else
-
-GET_RANDOM(arch_get_random_long, unsigned long, RDRAND_LONG, ASM_NOP3);
-GET_RANDOM(arch_get_random_int, unsigned int, RDRAND_INT, ASM_NOP3);
-
-#endif /* CONFIG_X86_64 */
-
-#endif  /* CONFIG_ARCH_RANDOM */
-
-extern void x86_init_rdrand(struct cpuinfo_x86 *c);
-
-#endif /* ASM_X86_ARCHRANDOM_H */
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index 1c2d247f65c..9412d6558c8 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -4,9 +4,11 @@
 #ifdef __ASSEMBLY__
 # define __ASM_FORM(x)  x
 # define __ASM_FORM_COMMA(x) x,
+# define __ASM_EX_SEC   .section __ex_table, "a"
 #else
 # define __ASM_FORM(x)  " " #x " "
 # define __ASM_FORM_COMMA(x) " " #x ","
+# define __ASM_EX_SEC   " .section __ex_table,\"a\"\n"
 #endif
 
 #ifdef CONFIG_X86_32
@@ -40,33 +42,17 @@
 
 /* Exception table entry */
 #ifdef __ASSEMBLY__
-# define _ASM_EXTABLE(from,to)                                  \
-        .pushsection "__ex_table","a" ;                         \
-        .balign 8 ;                                             \
-        .long (from) - . ;                                      \
-        .long (to) - . ;                                        \
-        .popsection
-
-# define _ASM_EXTABLE_EX(from,to)                               \
-        .pushsection "__ex_table","a" ;                         \
-        .balign 8 ;                                             \
-        .long (from) - . ;                                      \
-        .long (to) - . + 0x7ffffff0 ;                           \
-        .popsection
+# define _ASM_EXTABLE(from,to)      \
+        __ASM_EX_SEC ;              \
+        _ASM_ALIGN ;                \
+        _ASM_PTR from , to ;        \
+        .previous
 #else
-# define _ASM_EXTABLE(from,to)                                  \
-        " .pushsection \"__ex_table\",\"a\"\n"                  \
-        " .balign 8\n"                                          \
-        " .long (" #from ") - .\n"                              \
-        " .long (" #to ") - .\n"                                \
-        " .popsection\n"
-
-# define _ASM_EXTABLE_EX(from,to)                               \
-        " .pushsection \"__ex_table\",\"a\"\n"                  \
-        " .balign 8\n"                                          \
-        " .long (" #from ") - .\n"                              \
-        " .long (" #to ") - . + 0x7ffffff0\n"                   \
-        " .popsection\n"
+# define _ASM_EXTABLE(from,to) \
+        __ASM_EX_SEC    \
+        _ASM_ALIGN "\n" \
+        _ASM_PTR #from "," #to "\n" \
+        " .previous\n"
 #endif
 
 #endif /* _ASM_X86_ASM_H */
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 722aa3b0462..10572e309ab 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -172,7 +172,27 @@ static inline int atomic_add_negative(int i, atomic_t *v)
  */
 static inline int atomic_add_return(int i, atomic_t *v)
 {
-        return i + xadd(&v->counter, i);
+        int __i;
+#ifdef CONFIG_M386
+        unsigned long flags;
+        if (unlikely(boot_cpu_data.x86 <= 3))
+                goto no_xadd;
+#endif
+        /* Modern 486+ processor */
+        __i = i;
+        asm volatile(LOCK_PREFIX "xaddl %0, %1"
+                     : "+r" (i), "+m" (v->counter)
+                     : : "memory");
+        return i + __i;
+
+#ifdef CONFIG_M386
+no_xadd: /* Legacy 386 processor */
+        raw_local_irq_save(flags);
+        __i = atomic_read(v);
+        atomic_set(v, i + __i);
+        raw_local_irq_restore(flags);
+        return i + __i;
+#endif
 }
 
 /**
@@ -224,6 +244,30 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
         return c;
 }
 
+
+/*
+ * atomic_dec_if_positive - decrement by 1 if old value positive
+ * @v: pointer of type atomic_t
+ *
+ * The function returns the old value of *v minus 1, even if
+ * the atomic variable, v, was not decremented.
+ */
+static inline int atomic_dec_if_positive(atomic_t *v)
+{
+        int c, old, dec;
+        c = atomic_read(v);
+        for (;;) {
+                dec = c - 1;
+                if (unlikely(dec < 0))
+                        break;
+                old = atomic_cmpxchg((v), c, dec);
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return dec;
+}
+
 /**
  * atomic_inc_short - increment of a short integer
  * @v: pointer to type int
@@ -269,9 +313,9 @@ static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
 #define smp_mb__after_atomic_inc()      barrier()
 
 #ifdef CONFIG_X86_32
-# include <asm/atomic64_32.h>
+# include "atomic64_32.h"
 #else
-# include <asm/atomic64_64.h>
+# include "atomic64_64.h"
 #endif
 
 #endif /* _ASM_X86_ATOMIC_H */
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index b154de75c90..24098aafce0 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -14,56 +14,17 @@ typedef struct {
 
 #define ATOMIC64_INIT(val)      { (val) }
 
-#define __ATOMIC64_DECL(sym) void atomic64_##sym(atomic64_t *, ...)
-#ifndef ATOMIC64_EXPORT
-#define ATOMIC64_DECL_ONE __ATOMIC64_DECL
-#else
-#define ATOMIC64_DECL_ONE(sym) __ATOMIC64_DECL(sym); \
-        ATOMIC64_EXPORT(atomic64_##sym)
-#endif
-
 #ifdef CONFIG_X86_CMPXCHG64
-#define __alternative_atomic64(f, g, out, in...) \
-        asm volatile("call %P[func]" \
-                     : out : [func] "i" (atomic64_##g##_cx8), ## in)
-
-#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8)
+#define ATOMIC64_ALTERNATIVE_(f, g) "call atomic64_" #g "_cx8"
 #else
-#define __alternative_atomic64(f, g, out, in...) \
-        alternative_call(atomic64_##f##_386, atomic64_##g##_cx8, \
-                         X86_FEATURE_CX8, ASM_OUTPUT2(out), ## in)
-
-#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8); \
-        ATOMIC64_DECL_ONE(sym##_386)
-
-ATOMIC64_DECL_ONE(add_386);
-ATOMIC64_DECL_ONE(sub_386);
-ATOMIC64_DECL_ONE(inc_386);
-ATOMIC64_DECL_ONE(dec_386);
+#define ATOMIC64_ALTERNATIVE_(f, g) ALTERNATIVE("call atomic64_" #f "_386", "call atomic64_" #g "_cx8", X86_FEATURE_CX8)
 #endif
 
-#define alternative_atomic64(f, out, in...) \
-        __alternative_atomic64(f, f, ASM_OUTPUT2(out), ## in)
-
-ATOMIC64_DECL(read);
-ATOMIC64_DECL(set);
-ATOMIC64_DECL(xchg);
-ATOMIC64_DECL(add_return);
-ATOMIC64_DECL(sub_return);
-ATOMIC64_DECL(inc_return);
-ATOMIC64_DECL(dec_return);
-ATOMIC64_DECL(dec_if_positive);
-ATOMIC64_DECL(inc_not_zero);
-ATOMIC64_DECL(add_unless);
-
-#undef ATOMIC64_DECL
-#undef ATOMIC64_DECL_ONE
-#undef __ATOMIC64_DECL
-#undef ATOMIC64_EXPORT
+#define ATOMIC64_ALTERNATIVE(f) ATOMIC64_ALTERNATIVE_(f, f)
 
 /**
  * atomic64_cmpxchg - cmpxchg atomic64 variable
- * @v: pointer to type atomic64_t
+ * @p: pointer to type atomic64_t
  * @o: expected value
  * @n: new value
  *
@@ -89,16 +50,18 @@ static inline long long atomic64_xchg(atomic64_t *v, long long n)
         long long o;
         unsigned high = (unsigned)(n >> 32);
         unsigned low = (unsigned)n;
-        alternative_atomic64(xchg, "=&A" (o),
-                             "S" (v), "b" (low), "c" (high)
-                             : "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(xchg)
+                     : "=A" (o), "+b" (low), "+c" (high)
+                     : "S" (v)
+                     : "memory"
+                     );
         return o;
 }
 
 /**
  * atomic64_set - set atomic64 variable
  * @v: pointer to type atomic64_t
- * @i: value to assign
+ * @n: value to assign
  *
  * Atomically sets the value of @v to @n.
  */
@@ -106,9 +69,11 @@ static inline void atomic64_set(atomic64_t *v, long long i)
 {
         unsigned high = (unsigned)(i >> 32);
         unsigned low = (unsigned)i;
-        alternative_atomic64(set, /* no output */,
-                             "S" (v), "b" (low), "c" (high)
-                             : "eax", "edx", "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(set)
+                     : "+b" (low), "+c" (high)
+                     : "S" (v)
+                     : "eax", "edx", "memory"
+                     );
 }
 
 /**
@@ -117,10 +82,13 @@ static inline void atomic64_set(atomic64_t *v, long long i)
  *
  * Atomically reads the value of @v and returns it.
  */
-static inline long long atomic64_read(const atomic64_t *v)
+static inline long long atomic64_read(atomic64_t *v)
 {
         long long r;
-        alternative_atomic64(read, "=&A" (r), "c" (v) : "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(read)
+                     : "=A" (r), "+c" (v)
+                     : : "memory"
+                     );
         return r;
  }
 
@@ -133,9 +101,10 @@ static inline long long atomic64_read(const atomic64_t *v)
  */
 static inline long long atomic64_add_return(long long i, atomic64_t *v)
 {
-        alternative_atomic64(add_return,
-                             ASM_OUTPUT2("+A" (i), "+c" (v)),
-                             ASM_NO_INPUT_CLOBBER("memory"));
+        asm volatile(ATOMIC64_ALTERNATIVE(add_return)
+                     : "+A" (i), "+c" (v)
+                     : : "memory"
+                     );
         return i;
 }
 
@@ -144,25 +113,32 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v)
  */
 static inline long long atomic64_sub_return(long long i, atomic64_t *v)
 {
-        alternative_atomic64(sub_return,
-                             ASM_OUTPUT2("+A" (i), "+c" (v)),
-                             ASM_NO_INPUT_CLOBBER("memory"));
+        asm volatile(ATOMIC64_ALTERNATIVE(sub_return)
+                     : "+A" (i), "+c" (v)
+                     : : "memory"
+                     );
         return i;
 }
 
 static inline long long atomic64_inc_return(atomic64_t *v)
 {
         long long a;
-        alternative_atomic64(inc_return, "=&A" (a),
-                             "S" (v) : "memory", "ecx");
+        asm volatile(ATOMIC64_ALTERNATIVE(inc_return)
+                     : "=A" (a)
+                     : "S" (v)
+                     : "memory", "ecx"
+                     );
         return a;
 }
 
 static inline long long atomic64_dec_return(atomic64_t *v)
 {
         long long a;
-        alternative_atomic64(dec_return, "=&A" (a),
-                             "S" (v) : "memory", "ecx");
+        asm volatile(ATOMIC64_ALTERNATIVE(dec_return)
+                     : "=A" (a)
+                     : "S" (v)
+                     : "memory", "ecx"
+                     );
         return a;
 }
 
@@ -175,9 +151,10 @@ static inline long long atomic64_dec_return(atomic64_t *v)
  */
 static inline long long atomic64_add(long long i, atomic64_t *v)
 {
-        __alternative_atomic64(add, add_return,
-                               ASM_OUTPUT2("+A" (i), "+c" (v)),
-                               ASM_NO_INPUT_CLOBBER("memory"));
+        asm volatile(ATOMIC64_ALTERNATIVE_(add, add_return)
+                     : "+A" (i), "+c" (v)
+                     : : "memory"
+                     );
         return i;
 }
 
@@ -190,9 +167,10 @@ static inline long long atomic64_add(long long i, atomic64_t *v)
  */
 static inline long long atomic64_sub(long long i, atomic64_t *v)
 {
-        __alternative_atomic64(sub, sub_return,
-                               ASM_OUTPUT2("+A" (i), "+c" (v)),
-                               ASM_NO_INPUT_CLOBBER("memory"));
+        asm volatile(ATOMIC64_ALTERNATIVE_(sub, sub_return)
+                     : "+A" (i), "+c" (v)
+                     : : "memory"
+                     );
         return i;
 }
 
@@ -200,7 +178,7 @@ static inline long long atomic64_sub(long long i, atomic64_t *v)
  * atomic64_sub_and_test - subtract value from variable and test result
  * @i: integer value to subtract
  * @v: pointer to type atomic64_t
- *
+  *
  * Atomically subtracts @i from @v and returns
  * true if the result is zero, or false for all
  * other cases.
@@ -218,20 +196,24 @@ static inline int atomic64_sub_and_test(long long i, atomic64_t *v)
  */
 static inline void atomic64_inc(atomic64_t *v)
 {
-        __alternative_atomic64(inc, inc_return, /* no output */,
-                               "S" (v) : "memory", "eax", "ecx", "edx");
+        asm volatile(ATOMIC64_ALTERNATIVE_(inc, inc_return)
+                     : : "S" (v)
+                     : "memory", "eax", "ecx", "edx"
+                     );
 }
 
 /**
  * atomic64_dec - decrement atomic64 variable
- * @v: pointer to type atomic64_t
+ * @ptr: pointer to type atomic64_t
  *
- * Atomically decrements @v by 1.
+ * Atomically decrements @ptr by 1.
  */
 static inline void atomic64_dec(atomic64_t *v)
 {
-        __alternative_atomic64(dec, dec_return, /* no output */,
-                               "S" (v) : "memory", "eax", "ecx", "edx");
+        asm volatile(ATOMIC64_ALTERNATIVE_(dec, dec_return)
+                     : : "S" (v)
+                     : "memory", "eax", "ecx", "edx"
+                     );
 }
 
 /**
@@ -281,15 +263,15 @@ static inline int atomic64_add_negative(long long i, atomic64_t *v)
  * @u: ...unless v is equal to u.
  *
  * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if the add was done, zero otherwise.
+ * Returns the old value of @v.
  */
 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
 {
         unsigned low = (unsigned)u;
         unsigned high = (unsigned)(u >> 32);
-        alternative_atomic64(add_unless,
-                             ASM_OUTPUT2("+A" (a), "+c" (low), "+D" (high)),
-                             "S" (v) : "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(add_unless) "\n\t"
+                     : "+A" (a), "+c" (v), "+S" (low), "+D" (high)
+                     : : "memory");
         return (int)a;
 }
 
@@ -297,20 +279,26 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
 static inline int atomic64_inc_not_zero(atomic64_t *v)
 {
         int r;
-        alternative_atomic64(inc_not_zero, "=&a" (r),
-                             "S" (v) : "ecx", "edx", "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(inc_not_zero)
+                     : "=a" (r)
+                     : "S" (v)
+                     : "ecx", "edx", "memory"
+                     );
         return r;
 }
 
 static inline long long atomic64_dec_if_positive(atomic64_t *v)
 {
         long long r;
-        alternative_atomic64(dec_if_positive, "=&A" (r),
-                             "S" (v) : "ecx", "memory");
+        asm volatile(ATOMIC64_ALTERNATIVE(dec_if_positive)
+                     : "=A" (r)
+                     : "S" (v)
+                     : "ecx", "memory"
+                     );
         return r;
 }
 
-#undef alternative_atomic64
-#undef __alternative_atomic64
+#undef ATOMIC64_ALTERNATIVE
+#undef ATOMIC64_ALTERNATIVE_
 
 #endif /* _ASM_X86_ATOMIC64_32_H */
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
index 0e1cbfc8ee0..017594d403f 100644
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -170,7 +170,11 @@ static inline int atomic64_add_negative(long i, atomic64_t *v)
  */
 static inline long atomic64_add_return(long i, atomic64_t *v)
 {
-        return i + xadd(&v->counter, i);
+        long __i = i;
+        asm volatile(LOCK_PREFIX "xaddq %0, %1;"
+                     : "+r" (i), "+m" (v->counter)
+                     : : "memory");
+        return i + __i;
 }
 
 static inline long atomic64_sub_return(long i, atomic64_t *v)
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
deleted file mode 100644
index c6cd358a1ee..00000000000
--- a/arch/x86/include/asm/barrier.h
+++ /dev/null
@@ -1,116 +0,0 @@
-#ifndef _ASM_X86_BARRIER_H
-#define _ASM_X86_BARRIER_H
-
-#include <asm/alternative.h>
-#include <asm/nops.h>
-
-/*
- * Force strict CPU ordering.
- * And yes, this is required on UP too when we're talking
- * to devices.
- */
-
-#ifdef CONFIG_X86_32
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
-#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
-#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
-#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
-#else
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence" ::: "memory")
-#endif
-
-/**
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      b = 2;
- *      memory_barrier();
- *      p = &b;                         q = p;
- *                                      read_barrier_depends();
- *                                      d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      a = 2;
- *      memory_barrier();
- *      b = 3;                          y = b;
- *                                      read_barrier_depends();
- *                                      x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- **/
-
-#define read_barrier_depends()  do { } while (0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#ifdef CONFIG_X86_PPRO_FENCE
-# define smp_rmb()      rmb()
-#else
-# define smp_rmb()      barrier()
-#endif
-#ifdef CONFIG_X86_OOSTORE
-# define smp_wmb()      wmb()
-#else
-# define smp_wmb()      barrier()
-#endif
-#define smp_read_barrier_depends()      read_barrier_depends()
-#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while (0)
-#define set_mb(var, value) do { var = value; barrier(); } while (0)
-#endif
-
-/*
- * Stop RDTSC speculation. This is needed when you need to use RDTSC
- * (or get_cycles or vread that possibly accesses the TSC) in a defined
- * code region.
- *
- * (Could use an alternative three way for this if there was one.)
- */
-static __always_inline void rdtsc_barrier(void)
-{
-        alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
-        alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
-}
-
-#endif /* _ASM_X86_BARRIER_H */
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 6dfd0195bb5..1775d6e5920 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -15,8 +15,6 @@
 #include <linux/compiler.h>
 #include <asm/alternative.h>
 
-#define BIT_64(n)                       (U64_C(1) << (n))
-
 /*
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
@@ -264,13 +262,6 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
- *
- * Note: the operation is performed atomically with respect to
- * the local CPU, but not other CPUs. Portable code should not
- * rely on this behaviour.
- * KVM relies on this behaviour on x86 for modifying memory that is also
- * accessed from a hypervisor on the same CPU if running in a VM: don't change
- * this without also updating arch/x86/kernel/kvm.c
  */
 static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
@@ -355,7 +346,7 @@ static int test_bit(int nr, const volatile unsigned long *addr);
  */
 static inline unsigned long __ffs(unsigned long word)
 {
-        asm("rep; bsf %1,%0"
+        asm("bsf %1,%0"
                 : "=r" (word)
                 : "rm" (word));
         return word;
@@ -369,7 +360,7 @@ static inline unsigned long __ffs(unsigned long word)
  */
 static inline unsigned long ffz(unsigned long word)
 {
-        asm("rep; bsf %1,%0"
+        asm("bsf %1,%0"
                 : "=r" (word)
                 : "r" (~word));
         return word;
@@ -389,8 +380,6 @@ static inline unsigned long __fls(unsigned long word)
         return word;
 }
 
-#undef ADDR
-
 #ifdef __KERNEL__
 /**
  * ffs - find first set bit in word
@@ -406,24 +395,10 @@ static inline unsigned long __fls(unsigned long word)
 static inline int ffs(int x)
 {
         int r;
-
-#ifdef CONFIG_X86_64
-        /*
-         * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
-         * dest reg is undefined if x==0, but their CPU architect says its
-         * value is written to set it to the same as before, except that the
-         * top 32 bits will be cleared.
-         *
-         * We cannot do this on 32 bits because at the very least some
-         * 486 CPUs did not behave this way.
-         */
-        asm("bsfl %1,%0"
-            : "=r" (r)
-            : "rm" (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#ifdef CONFIG_X86_CMOV
         asm("bsfl %1,%0\n\t"
             "cmovzl %2,%0"
-            : "=&r" (r) : "rm" (x), "r" (-1));
+            : "=r" (r) : "rm" (x), "r" (-1));
 #else
         asm("bsfl %1,%0\n\t"
             "jnz 1f\n\t"
@@ -447,21 +422,7 @@ static inline int ffs(int x)
 static inline int fls(int x)
 {
         int r;
-
-#ifdef CONFIG_X86_64
-        /*
-         * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
-         * dest reg is undefined if x==0, but their CPU architect says its
-         * value is written to set it to the same as before, except that the
-         * top 32 bits will be cleared.
-         *
-         * We cannot do this on 32 bits because at the very least some
-         * 486 CPUs did not behave this way.
-         */
-        asm("bsrl %1,%0"
-            : "=r" (r)
-            : "rm" (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#ifdef CONFIG_X86_CMOV
         asm("bsrl %1,%0\n\t"
             "cmovzl %2,%0"
             : "=&r" (r) : "rm" (x), "rm" (-1));
@@ -473,35 +434,11 @@ static inline int fls(int x)
 #endif
         return r + 1;
 }
+#endif /* __KERNEL__ */
 
-/**
- * fls64 - find last set bit in a 64-bit word
- * @x: the word to search
- *
- * This is defined in a similar way as the libc and compiler builtin
- * ffsll, but returns the position of the most significant set bit.
- *
- * fls64(value) returns 0 if value is 0 or the position of the last
- * set bit if value is nonzero. The last (most significant) bit is
- * at position 64.
- */
-#ifdef CONFIG_X86_64
-static __always_inline int fls64(__u64 x)
-{
-        int bitpos = -1;
-        /*
-         * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
-         * dest reg is undefined if x==0, but their CPU architect says its
-         * value is written to set it to the same as before.
-         */
-        asm("bsrq %1,%q0"
-            : "+r" (bitpos)
-            : "rm" (x));
-        return bitpos + 1;
-}
-#else
-#include <asm-generic/bitops/fls64.h>
-#endif
+#undef ADDR
+
+#ifdef __KERNEL__
 
 #include <asm-generic/bitops/find.h>
 
@@ -513,6 +450,12 @@ static __always_inline int fls64(__u64 x)
 
 #include <asm-generic/bitops/const_hweight.h>
 
+#endif /* __KERNEL__ */
+
+#include <asm-generic/bitops/fls64.h>
+
+#ifdef __KERNEL__
+
 #include <asm-generic/bitops/le.h>
 
 #include <asm-generic/bitops/ext2-atomic-setbit.h>
diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h
index 4fa687a47a6..5e1a2eef3e7 100644
--- a/arch/x86/include/asm/boot.h
+++ b/arch/x86/include/asm/boot.h
@@ -1,9 +1,14 @@
 #ifndef _ASM_X86_BOOT_H
 #define _ASM_X86_BOOT_H
 
+/* Internal svga startup constants */
+#define NORMAL_VGA      0xffff          /* 80x25 mode */
+#define EXTENDED_VGA    0xfffe          /* 80x50 mode */
+#define ASK_VGA         0xfffd          /* ask for it at bootup */
+
+#ifdef __KERNEL__
 
 #include <asm/pgtable_types.h>
-#include <uapi/asm/boot.h>
 
 /* Physical address where kernel should be loaded. */
 #define LOAD_PHYSICAL_ADDR ((CONFIG_PHYSICAL_START \
@@ -14,7 +19,7 @@
 #ifdef CONFIG_X86_64
 #define MIN_KERNEL_ALIGN_LG2    PMD_SHIFT
 #else
-#define MIN_KERNEL_ALIGN_LG2    (PAGE_SHIFT + THREAD_SIZE_ORDER)
+#define MIN_KERNEL_ALIGN_LG2    (PAGE_SHIFT + THREAD_ORDER)
 #endif
 #define MIN_KERNEL_ALIGN        (_AC(1, UL) << MIN_KERNEL_ALIGN_LG2)
 
@@ -37,4 +42,6 @@
 #define BOOT_STACK_SIZE 0x1000
 #endif
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_X86_BOOT_H */
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 11e1152222d..f654d1bb17f 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -36,8 +36,4 @@ do {								\
 #endif /* !CONFIG_BUG */
 
 #include <asm-generic/bug.h>
-
-
-extern void show_regs_common(void);
-
 #endif /* _ASM_X86_BUG_H */
diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h
index 9863ee3747d..4e12668711e 100644
--- a/arch/x86/include/asm/cacheflush.h
+++ b/arch/x86/include/asm/cacheflush.h
@@ -3,7 +3,6 @@
 
 /* Caches aren't brain-dead on the intel. */
 #include <asm-generic/cacheflush.h>
-#include <asm/special_insns.h>
 
 #ifdef CONFIG_X86_PAT
 /*
diff --git a/arch/x86/include/asm/calling.h b/arch/x86/include/asm/calling.h
index 0fa67503391..a9e3a740f69 100644
--- a/arch/x86/include/asm/calling.h
+++ b/arch/x86/include/asm/calling.h
@@ -46,39 +46,41 @@ For 32-bit we have the following conventions - kernel is built with
 
 */
 
-#include <asm/dwarf2.h>
+#include "dwarf2.h"
 
 /*
- * 64-bit system call stack frame layout defines and helpers,
- * for assembly code:
+ * 64-bit system call stack frame layout defines and helpers, for
+ * assembly code (note that the seemingly unnecessary parentheses
+ * are to prevent cpp from inserting spaces in expressions that get
+ * passed to macros):
  */
 
-#define R15               0
-#define R14               8
-#define R13              16
-#define R12              24
-#define RBP              32
-#define RBX              40
+#define R15               (0)
+#define R14               (8)
+#define R13              (16)
+#define R12              (24)
+#define RBP              (32)
+#define RBX              (40)
 
 /* arguments: interrupts/non tracing syscalls only save up to here: */
-#define R11              48
-#define R10              56
-#define R9               64
-#define R8               72
-#define RAX              80
-#define RCX              88
-#define RDX              96
-#define RSI             104
-#define RDI             112
-#define ORIG_RAX        120       /* + error_code */
+#define R11              (48)
+#define R10              (56)
+#define R9               (64)
+#define R8               (72)
+#define RAX              (80)
+#define RCX              (88)
+#define RDX              (96)
+#define RSI             (104)
+#define RDI             (112)
+#define ORIG_RAX        (120)       /* + error_code */
 /* end of arguments */
 
 /* cpu exception frame or undefined in case of fast syscall: */
-#define RIP             128
-#define CS              136
-#define EFLAGS          144
-#define RSP             152
-#define SS              160
+#define RIP             (128)
+#define CS              (136)
+#define EFLAGS          (144)
+#define RSP             (152)
+#define SS              (160)
 
 #define ARGOFFSET       R11
 #define SWFRAME         ORIG_RAX
diff --git a/arch/x86/include/asm/checksum.h b/arch/x86/include/asm/checksum.h
index 5f5bb0f9736..848850fd7d6 100644
--- a/arch/x86/include/asm/checksum.h
+++ b/arch/x86/include/asm/checksum.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/checksum_32.h>
+# include "checksum_32.h"
 #else
-# include <asm/checksum_64.h>
+# include "checksum_64.h"
 #endif
diff --git a/arch/x86/include/asm/clocksource.h b/arch/x86/include/asm/clocksource.h
index 16a57f4ed64..0bdbbb3b9ce 100644
--- a/arch/x86/include/asm/clocksource.h
+++ b/arch/x86/include/asm/clocksource.h
@@ -8,7 +8,6 @@
 #define VCLOCK_NONE 0  /* No vDSO clock available.      */
 #define VCLOCK_TSC  1  /* vDSO should use vread_tsc.    */
 #define VCLOCK_HPET 2  /* vDSO should use vread_hpet.   */
-#define VCLOCK_PVCLOCK 3 /* vDSO should use vread_pvclock. */
 
 struct arch_clocksource_data {
         int vclock_mode;
diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h
index 8d871eaddb6..a460fa088d4 100644
--- a/arch/x86/include/asm/cmpxchg.h
+++ b/arch/x86/include/asm/cmpxchg.h
@@ -1,233 +1,5 @@
-#ifndef ASM_X86_CMPXCHG_H
-#define ASM_X86_CMPXCHG_H
-
-#include <linux/compiler.h>
-#include <asm/alternative.h> /* Provides LOCK_PREFIX */
-
-/*
- * Non-existant functions to indicate usage errors at link time
- * (or compile-time if the compiler implements __compiletime_error().
- */
-extern void __xchg_wrong_size(void)
-        __compiletime_error("Bad argument size for xchg");
-extern void __cmpxchg_wrong_size(void)
-        __compiletime_error("Bad argument size for cmpxchg");
-extern void __xadd_wrong_size(void)
-        __compiletime_error("Bad argument size for xadd");
-extern void __add_wrong_size(void)
-        __compiletime_error("Bad argument size for add");
-
-/*
- * Constants for operation sizes. On 32-bit, the 64-bit size it set to
- * -1 because sizeof will never return -1, thereby making those switch
- * case statements guaranteeed dead code which the compiler will
- * eliminate, and allowing the "missing symbol in the default case" to
- * indicate a usage error.
- */
-#define __X86_CASE_B    1
-#define __X86_CASE_W    2
-#define __X86_CASE_L    4
-#ifdef CONFIG_64BIT
-#define __X86_CASE_Q    8
-#else
-#define __X86_CASE_Q    -1              /* sizeof will never return -1 */
-#endif
-
-/* 
- * An exchange-type operation, which takes a value and a pointer, and
- * returns a the old value.
- */
-#define __xchg_op(ptr, arg, op, lock)                                   \
-        ({                                                              \
-                __typeof__ (*(ptr)) __ret = (arg);                      \
-                switch (sizeof(*(ptr))) {                               \
-                case __X86_CASE_B:                                      \
-                        asm volatile (lock #op "b %b0, %1\n"            \
-                                      : "+q" (__ret), "+m" (*(ptr))     \
-                                      : : "memory", "cc");              \
-                        break;                                          \
-                case __X86_CASE_W:                                      \
-                        asm volatile (lock #op "w %w0, %1\n"            \
-                                      : "+r" (__ret), "+m" (*(ptr))     \
-                                      : : "memory", "cc");              \
-                        break;                                          \
-                case __X86_CASE_L:                                      \
-                        asm volatile (lock #op "l %0, %1\n"             \
-                                      : "+r" (__ret), "+m" (*(ptr))     \
-                                      : : "memory", "cc");              \
-                        break;                                          \
-                case __X86_CASE_Q:                                      \
-                        asm volatile (lock #op "q %q0, %1\n"            \
-                                      : "+r" (__ret), "+m" (*(ptr))     \
-                                      : : "memory", "cc");              \
-                        break;                                          \
-                default:                                                \
-                        __ ## op ## _wrong_size();                      \
-                }                                                       \
-                __ret;                                                  \
-        })
-
-/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
- * Since this is generally used to protect other memory information, we
- * use "asm volatile" and "memory" clobbers to prevent gcc from moving
- * information around.
- */
-#define xchg(ptr, v)    __xchg_op((ptr), (v), xchg, "")
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-#define __raw_cmpxchg(ptr, old, new, size, lock)                        \
-({                                                                      \
-        __typeof__(*(ptr)) __ret;                                       \
-        __typeof__(*(ptr)) __old = (old);                               \
-        __typeof__(*(ptr)) __new = (new);                               \
-        switch (size) {                                                 \
-        case __X86_CASE_B:                                              \
-        {                                                               \
-                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
-                asm volatile(lock "cmpxchgb %2,%1"                      \
-                             : "=a" (__ret), "+m" (*__ptr)              \
-                             : "q" (__new), "0" (__old)                 \
-                             : "memory");                               \
-                break;                                                  \
-        }                                                               \
-        case __X86_CASE_W:                                              \
-        {                                                               \
-                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
-                asm volatile(lock "cmpxchgw %2,%1"                      \
-                             : "=a" (__ret), "+m" (*__ptr)              \
-                             : "r" (__new), "0" (__old)                 \
-                             : "memory");                               \
-                break;                                                  \
-        }                                                               \
-        case __X86_CASE_L:                                              \
-        {                                                               \
-                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
-                asm volatile(lock "cmpxchgl %2,%1"                      \
-                             : "=a" (__ret), "+m" (*__ptr)              \
-                             : "r" (__new), "0" (__old)                 \
-                             : "memory");                               \
-                break;                                                  \
-        }                                                               \
-        case __X86_CASE_Q:                                              \
-        {                                                               \
-                volatile u64 *__ptr = (volatile u64 *)(ptr);            \
-                asm volatile(lock "cmpxchgq %2,%1"                      \
-                             : "=a" (__ret), "+m" (*__ptr)              \
-                             : "r" (__new), "0" (__old)                 \
-                             : "memory");                               \
-                break;                                                  \
-        }                                                               \
-        default:                                                        \
-                __cmpxchg_wrong_size();                                 \
-        }                                                               \
-        __ret;                                                          \
-})
-
-#define __cmpxchg(ptr, old, new, size)                                  \
-        __raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
-
-#define __sync_cmpxchg(ptr, old, new, size)                             \
-        __raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
-
-#define __cmpxchg_local(ptr, old, new, size)                            \
-        __raw_cmpxchg((ptr), (old), (new), (size), "")
-
 #ifdef CONFIG_X86_32
-# include <asm/cmpxchg_32.h>
+# include "cmpxchg_32.h"
 #else
-# include <asm/cmpxchg_64.h>
-#endif
-
-#ifdef __HAVE_ARCH_CMPXCHG
-#define cmpxchg(ptr, old, new)                                          \
-        __cmpxchg(ptr, old, new, sizeof(*(ptr)))
-
-#define sync_cmpxchg(ptr, old, new)                                     \
-        __sync_cmpxchg(ptr, old, new, sizeof(*(ptr)))
-
-#define cmpxchg_local(ptr, old, new)                                    \
-        __cmpxchg_local(ptr, old, new, sizeof(*(ptr)))
+# include "cmpxchg_64.h"
 #endif
-
-/*
- * xadd() adds "inc" to "*ptr" and atomically returns the previous
- * value of "*ptr".
- *
- * xadd() is locked when multiple CPUs are online
- * xadd_sync() is always locked
- * xadd_local() is never locked
- */
-#define __xadd(ptr, inc, lock)  __xchg_op((ptr), (inc), xadd, lock)
-#define xadd(ptr, inc)          __xadd((ptr), (inc), LOCK_PREFIX)
-#define xadd_sync(ptr, inc)     __xadd((ptr), (inc), "lock; ")
-#define xadd_local(ptr, inc)    __xadd((ptr), (inc), "")
-
-#define __add(ptr, inc, lock)                                           \
-        ({                                                              \
-                __typeof__ (*(ptr)) __ret = (inc);                      \
-                switch (sizeof(*(ptr))) {                               \
-                case __X86_CASE_B:                                      \
-                        asm volatile (lock "addb %b1, %0\n"             \
-                                      : "+m" (*(ptr)) : "qi" (inc)      \
-                                      : "memory", "cc");                \
-                        break;                                          \
-                case __X86_CASE_W:                                      \
-                        asm volatile (lock "addw %w1, %0\n"             \
-                                      : "+m" (*(ptr)) : "ri" (inc)      \
-                                      : "memory", "cc");                \
-                        break;                                          \
-                case __X86_CASE_L:                                      \
-                        asm volatile (lock "addl %1, %0\n"              \
-                                      : "+m" (*(ptr)) : "ri" (inc)      \
-                                      : "memory", "cc");                \
-                        break;                                          \
-                case __X86_CASE_Q:                                      \
-                        asm volatile (lock "addq %1, %0\n"              \
-                                      : "+m" (*(ptr)) : "ri" (inc)      \
-                                      : "memory", "cc");                \
-                        break;                                          \
-                default:                                                \
-                        __add_wrong_size();                             \
-                }                                                       \
-                __ret;                                                  \
-        })
-
-/*
- * add_*() adds "inc" to "*ptr"
- *
- * __add() takes a lock prefix
- * add_smp() is locked when multiple CPUs are online
- * add_sync() is always locked
- */
-#define add_smp(ptr, inc)       __add((ptr), (inc), LOCK_PREFIX)
-#define add_sync(ptr, inc)      __add((ptr), (inc), "lock; ")
-
-#define __cmpxchg_double(pfx, p1, p2, o1, o2, n1, n2)                   \
-({                                                                      \
-        bool __ret;                                                     \
-        __typeof__(*(p1)) __old1 = (o1), __new1 = (n1);                 \
-        __typeof__(*(p2)) __old2 = (o2), __new2 = (n2);                 \
-        BUILD_BUG_ON(sizeof(*(p1)) != sizeof(long));                    \
-        BUILD_BUG_ON(sizeof(*(p2)) != sizeof(long));                    \
-        VM_BUG_ON((unsigned long)(p1) % (2 * sizeof(long)));            \
-        VM_BUG_ON((unsigned long)((p1) + 1) != (unsigned long)(p2));    \
-        asm volatile(pfx "cmpxchg%c4b %2; sete %0"                      \
-                     : "=a" (__ret), "+d" (__old2),                     \
-                       "+m" (*(p1)), "+m" (*(p2))                       \
-                     : "i" (2 * sizeof(long)), "a" (__old1),            \
-                       "b" (__new1), "c" (__new2));                     \
-        __ret;                                                          \
-})
-
-#define cmpxchg_double(p1, p2, o1, o2, n1, n2) \
-        __cmpxchg_double(LOCK_PREFIX, p1, p2, o1, o2, n1, n2)
-
-#define cmpxchg_double_local(p1, p2, o1, o2, n1, n2) \
-        __cmpxchg_double(, p1, p2, o1, o2, n1, n2)
-
-#endif  /* ASM_X86_CMPXCHG_H */
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index f8bf2eecab8..3deb7250624 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -1,11 +1,61 @@
 #ifndef _ASM_X86_CMPXCHG_32_H
 #define _ASM_X86_CMPXCHG_32_H
 
+#include <linux/bitops.h> /* for LOCK_PREFIX */
+
 /*
  * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
  *       you need to test for the feature in boot_cpu_data.
  */
 
+extern void __xchg_wrong_size(void);
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
+ * Since this is generally used to protect other memory information, we
+ * use "asm volatile" and "memory" clobbers to prevent gcc from moving
+ * information around.
+ */
+#define __xchg(x, ptr, size)                                            \
+({                                                                      \
+        __typeof(*(ptr)) __x = (x);                                     \
+        switch (size) {                                                 \
+        case 1:                                                         \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile("xchgb %0,%1"                              \
+                             : "=q" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 2:                                                         \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile("xchgw %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 4:                                                         \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile("xchgl %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        default:                                                        \
+                __xchg_wrong_size();                                    \
+        }                                                               \
+        __x;                                                            \
+})
+
+#define xchg(ptr, v)                                                    \
+        __xchg((v), (ptr), sizeof(*ptr))
+
 /*
  * CMPXCHG8B only writes to the target if we had the previous
  * value in registers, otherwise it acts as a read and gives us the
@@ -34,8 +84,74 @@ static inline void set_64bit(volatile u64 *ptr, u64 value)
                      : "memory");
 }
 
+extern void __cmpxchg_wrong_size(void);
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+#define __raw_cmpxchg(ptr, old, new, size, lock)                        \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        __typeof__(*(ptr)) __old = (old);                               \
+        __typeof__(*(ptr)) __new = (new);                               \
+        switch (size) {                                                 \
+        case 1:                                                         \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile(lock "cmpxchgb %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "q" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 2:                                                         \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile(lock "cmpxchgw %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 4:                                                         \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile(lock "cmpxchgl %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        default:                                                        \
+                __cmpxchg_wrong_size();                                 \
+        }                                                               \
+        __ret;                                                          \
+})
+
+#define __cmpxchg(ptr, old, new, size)                                  \
+        __raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
+
+#define __sync_cmpxchg(ptr, old, new, size)                             \
+        __raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
+
+#define __cmpxchg_local(ptr, old, new, size)                            \
+        __raw_cmpxchg((ptr), (old), (new), (size), "")
+
+#ifdef CONFIG_X86_CMPXCHG
 #define __HAVE_ARCH_CMPXCHG 1
 
+#define cmpxchg(ptr, old, new)                                          \
+        __cmpxchg((ptr), (old), (new), sizeof(*ptr))
+
+#define sync_cmpxchg(ptr, old, new)                                     \
+        __sync_cmpxchg((ptr), (old), (new), sizeof(*ptr))
+
+#define cmpxchg_local(ptr, old, new)                                    \
+        __cmpxchg_local((ptr), (old), (new), sizeof(*ptr))
+#endif
+
 #ifdef CONFIG_X86_CMPXCHG64
 #define cmpxchg64(ptr, o, n)                                            \
         ((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
@@ -71,6 +187,59 @@ static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
         return prev;
 }
 
+#ifndef CONFIG_X86_CMPXCHG
+/*
+ * Building a kernel capable running on 80386. It may be necessary to
+ * simulate the cmpxchg on the 80386 CPU. For that purpose we define
+ * a function for each of the sizes we support.
+ */
+
+extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
+extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
+extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
+
+static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
+                                        unsigned long new, int size)
+{
+        switch (size) {
+        case 1:
+                return cmpxchg_386_u8(ptr, old, new);
+        case 2:
+                return cmpxchg_386_u16(ptr, old, new);
+        case 4:
+                return cmpxchg_386_u32(ptr, old, new);
+        }
+        return old;
+}
+
+#define cmpxchg(ptr, o, n)                                              \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        if (likely(boot_cpu_data.x86 > 3))                              \
+                __ret = (__typeof__(*(ptr)))__cmpxchg((ptr),            \
+                                (unsigned long)(o), (unsigned long)(n), \
+                                sizeof(*(ptr)));                        \
+        else                                                            \
+                __ret = (__typeof__(*(ptr)))cmpxchg_386((ptr),          \
+                                (unsigned long)(o), (unsigned long)(n), \
+                                sizeof(*(ptr)));                        \
+        __ret;                                                          \
+})
+#define cmpxchg_local(ptr, o, n)                                        \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        if (likely(boot_cpu_data.x86 > 3))                              \
+                __ret = (__typeof__(*(ptr)))__cmpxchg_local((ptr),      \
+                                (unsigned long)(o), (unsigned long)(n), \
+                                sizeof(*(ptr)));                        \
+        else                                                            \
+                __ret = (__typeof__(*(ptr)))cmpxchg_386((ptr),          \
+                                (unsigned long)(o), (unsigned long)(n), \
+                                sizeof(*(ptr)));                        \
+        __ret;                                                          \
+})
+#endif
+
 #ifndef CONFIG_X86_CMPXCHG64
 /*
  * Building a kernel capable running on 80386 and 80486. It may be necessary
@@ -111,6 +280,52 @@ static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
 
 #endif
 
+#define cmpxchg8b(ptr, o1, o2, n1, n2)                          \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __dummy;                                 \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile(LOCK_PREFIX "cmpxchg8b %2; setz %1"        \
+                       : "=d"(__dummy), "=a" (__ret), "+m" (*ptr)\
+                       : "a" (__old1), "d"(__old2),             \
+                         "b" (__new1), "c" (__new2)             \
+                       : "memory");                             \
+        __ret; })
+
+
+#define cmpxchg8b_local(ptr, o1, o2, n1, n2)                    \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __dummy;                                 \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile("cmpxchg8b %2; setz %1"                    \
+                       : "=d"(__dummy), "=a"(__ret), "+m" (*ptr)\
+                       : "a" (__old), "d"(__old2),              \
+                         "b" (__new1), "c" (__new2),            \
+                       : "memory");                             \
+        __ret; })
+
+
+#define cmpxchg_double(ptr, o1, o2, n1, n2)                             \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 4);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 8);                            \
+        cmpxchg8b((ptr), (o1), (o2), (n1), (n2));                       \
+})
+
+#define cmpxchg_double_local(ptr, o1, o2, n1, n2)                       \
+({                                                                      \
+       BUILD_BUG_ON(sizeof(*(ptr)) != 4);                               \
+       VM_BUG_ON((unsigned long)(ptr) % 8);                             \
+       cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2));                 \
+})
+
 #define system_has_cmpxchg_double() cpu_has_cx8
 
 #endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 614be87f1a9..7cf5c0a2443 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -1,13 +1,144 @@
 #ifndef _ASM_X86_CMPXCHG_64_H
 #define _ASM_X86_CMPXCHG_64_H
 
+#include <asm/alternative.h> /* Provides LOCK_PREFIX */
+
 static inline void set_64bit(volatile u64 *ptr, u64 val)
 {
         *ptr = val;
 }
 
+extern void __xchg_wrong_size(void);
+extern void __cmpxchg_wrong_size(void);
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
+ * Since this is generally used to protect other memory information, we
+ * use "asm volatile" and "memory" clobbers to prevent gcc from moving
+ * information around.
+ */
+#define __xchg(x, ptr, size)                                            \
+({                                                                      \
+        __typeof(*(ptr)) __x = (x);                                     \
+        switch (size) {                                                 \
+        case 1:                                                         \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile("xchgb %0,%1"                              \
+                             : "=q" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 2:                                                         \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile("xchgw %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 4:                                                         \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile("xchgl %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 8:                                                         \
+        {                                                               \
+                volatile u64 *__ptr = (volatile u64 *)(ptr);            \
+                asm volatile("xchgq %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        default:                                                        \
+                __xchg_wrong_size();                                    \
+        }                                                               \
+        __x;                                                            \
+})
+
+#define xchg(ptr, v)                                                    \
+        __xchg((v), (ptr), sizeof(*ptr))
+
 #define __HAVE_ARCH_CMPXCHG 1
 
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+#define __raw_cmpxchg(ptr, old, new, size, lock)                        \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        __typeof__(*(ptr)) __old = (old);                               \
+        __typeof__(*(ptr)) __new = (new);                               \
+        switch (size) {                                                 \
+        case 1:                                                         \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile(lock "cmpxchgb %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "q" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 2:                                                         \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile(lock "cmpxchgw %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 4:                                                         \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile(lock "cmpxchgl %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        case 8:                                                         \
+        {                                                               \
+                volatile u64 *__ptr = (volatile u64 *)(ptr);            \
+                asm volatile(lock "cmpxchgq %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
+                             : "memory");                               \
+                break;                                                  \
+        }                                                               \
+        default:                                                        \
+                __cmpxchg_wrong_size();                                 \
+        }                                                               \
+        __ret;                                                          \
+})
+
+#define __cmpxchg(ptr, old, new, size)                                  \
+        __raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
+
+#define __sync_cmpxchg(ptr, old, new, size)                             \
+        __raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
+
+#define __cmpxchg_local(ptr, old, new, size)                            \
+        __raw_cmpxchg((ptr), (old), (new), (size), "")
+
+#define cmpxchg(ptr, old, new)                                          \
+        __cmpxchg((ptr), (old), (new), sizeof(*ptr))
+
+#define sync_cmpxchg(ptr, old, new)                                     \
+        __sync_cmpxchg((ptr), (old), (new), sizeof(*ptr))
+
+#define cmpxchg_local(ptr, old, new)                                    \
+        __cmpxchg_local((ptr), (old), (new), sizeof(*ptr))
+
 #define cmpxchg64(ptr, o, n)                                            \
 ({                                                                      \
         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
@@ -20,6 +151,49 @@ static inline void set_64bit(volatile u64 *ptr, u64 val)
         cmpxchg_local((ptr), (o), (n));                                 \
 })
 
+#define cmpxchg16b(ptr, o1, o2, n1, n2)                         \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __junk;                                  \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile(LOCK_PREFIX "cmpxchg16b %2;setz %1"        \
+                       : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
+                       : "b"(__new1), "c"(__new2),              \
+                         "a"(__old1), "d"(__old2));             \
+        __ret; })
+
+
+#define cmpxchg16b_local(ptr, o1, o2, n1, n2)                   \
+({                                                              \
+        char __ret;                                             \
+        __typeof__(o2) __junk;                                  \
+        __typeof__(*(ptr)) __old1 = (o1);                       \
+        __typeof__(o2) __old2 = (o2);                           \
+        __typeof__(*(ptr)) __new1 = (n1);                       \
+        __typeof__(o2) __new2 = (n2);                           \
+        asm volatile("cmpxchg16b %2;setz %1"                    \
+                       : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
+                       : "b"(__new1), "c"(__new2),              \
+                         "a"(__old1), "d"(__old2));             \
+        __ret; })
+
+#define cmpxchg_double(ptr, o1, o2, n1, n2)                             \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 16);                           \
+        cmpxchg16b((ptr), (o1), (o2), (n1), (n2));                      \
+})
+
+#define cmpxchg_double_local(ptr, o1, o2, n1, n2)                       \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        VM_BUG_ON((unsigned long)(ptr) % 16);                           \
+        cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2));                \
+})
+
 #define system_has_cmpxchg_double() cpu_has_cx16
 
 #endif /* _ASM_X86_CMPXCHG_64_H */
diff --git a/arch/x86/include/asm/compat.h b/arch/x86/include/asm/compat.h
index 59c6c401f79..1d9cd27c292 100644
--- a/arch/x86/include/asm/compat.h
+++ b/arch/x86/include/asm/compat.h
@@ -6,9 +6,7 @@
  */
 #include <linux/types.h>
 #include <linux/sched.h>
-#include <asm/processor.h>
 #include <asm/user32.h>
-#include <asm/unistd.h>
 
 #define COMPAT_USER_HZ          100
 #define COMPAT_UTS_MACHINE      "i686\0\0"
@@ -41,7 +39,6 @@ typedef s64 __attribute__((aligned(4))) compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64 __attribute__((aligned(4))) compat_u64;
-typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -111,8 +108,7 @@ struct compat_statfs {
         compat_fsid_t   f_fsid;
         int             f_namelen;      /* SunOS ignores this field. */
         int             f_frsize;
-        int             f_flags;
-        int             f_spare[4];
+        int             f_spare[5];
 };
 
 #define COMPAT_RLIM_OLD_INFINITY        0x7fffffff
@@ -125,78 +121,6 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32               compat_sigset_word;
 
-typedef union compat_sigval {
-        compat_int_t    sival_int;
-        compat_uptr_t   sival_ptr;
-} compat_sigval_t;
-
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[128/sizeof(int) - 3];
-
-                /* kill() */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;    /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                        int _overrun_incr;      /* amount to add to overrun */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGCHLD (x32 version) */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_s64 _utime;
-                        compat_s64 _stime;
-                } _sigchld_x32;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        unsigned int _addr;     /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-
-                struct {
-                        unsigned int _call_addr; /* calling insn */
-                        int _syscall;   /* triggering system call number */
-                        unsigned int _arch;     /* AUDIT_ARCH_* of syscall */
-                } _sigsys;
-        } _sifields;
-} compat_siginfo_t;
-
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -261,20 +185,7 @@ struct compat_shmid64_ds {
 /*
  * The type of struct elf_prstatus.pr_reg in compatible core dumps.
  */
-#ifdef CONFIG_X86_X32_ABI
-typedef struct user_regs_struct compat_elf_gregset_t;
-
-#define PR_REG_SIZE(S) (test_thread_flag(TIF_IA32) ? 68 : 216)
-#define PRSTATUS_SIZE(S) (test_thread_flag(TIF_IA32) ? 144 : 296)
-#define SET_PR_FPVALID(S,V) \
-  do { *(int *) (((void *) &((S)->pr_reg)) + PR_REG_SIZE(0)) = (V); } \
-  while (0)
-
-#define COMPAT_USE_64BIT_TIME \
-        (!!(task_pt_regs(current)->orig_ax & __X32_SYSCALL_BIT))
-#else
 typedef struct user_regs_struct32 compat_elf_gregset_t;
-#endif
 
 /*
  * A pointer passed in from user mode. This should not
@@ -282,6 +193,7 @@ typedef struct user_regs_struct32 compat_elf_gregset_t;
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
+typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
@@ -295,30 +207,13 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
 
 static inline void __user *arch_compat_alloc_user_space(long len)
 {
-        compat_uptr_t sp;
-
-        if (test_thread_flag(TIF_IA32)) {
-                sp = task_pt_regs(current)->sp;
-        } else {
-                /* -128 for the x32 ABI redzone */
-                sp = this_cpu_read(old_rsp) - 128;
-        }
-
-        return (void __user *)round_down(sp - len, 16);
-}
-
-static inline bool is_x32_task(void)
-{
-#ifdef CONFIG_X86_X32_ABI
-        if (task_pt_regs(current)->orig_ax & __X32_SYSCALL_BIT)
-                return true;
-#endif
-        return false;
+        struct pt_regs *regs = task_pt_regs(current);
+        return (void __user *)regs->sp - len;
 }
 
-static inline bool is_compat_task(void)
+static inline int is_compat_task(void)
 {
-        return is_ia32_task() || is_x32_task();
+        return current_thread_info()->status & TS_COMPAT;
 }
 
 #endif /* _ASM_X86_COMPAT_H */
diff --git a/arch/x86/include/asm/context_tracking.h b/arch/x86/include/asm/context_tracking.h
deleted file mode 100644
index 1616562683e..00000000000
--- a/arch/x86/include/asm/context_tracking.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASM_X86_CONTEXT_TRACKING_H
-#define _ASM_X86_CONTEXT_TRACKING_H
-
-#ifndef __ASSEMBLY__
-#include <linux/context_tracking.h>
-#include <asm/ptrace.h>
-
-static inline void exception_enter(struct pt_regs *regs)
-{
-        user_exit();
-}
-
-static inline void exception_exit(struct pt_regs *regs)
-{
-#ifdef CONFIG_CONTEXT_TRACKING
-        if (user_mode(regs))
-                user_enter();
-#endif
-}
-
-#else /* __ASSEMBLY__ */
-
-#ifdef CONFIG_CONTEXT_TRACKING
-# define SCHEDULE_USER call schedule_user
-#else
-# define SCHEDULE_USER call schedule
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 5f9a1243190..4564c8e28a3 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -28,10 +28,6 @@ struct x86_cpu {
 #ifdef CONFIG_HOTPLUG_CPU
 extern int arch_register_cpu(int num);
 extern void arch_unregister_cpu(int);
-extern void __cpuinit start_cpu0(void);
-#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
-extern int _debug_hotplug_cpu(int cpu, int action);
-#endif
 #endif
 
 DECLARE_PER_CPU(int, cpu_state);
diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h
deleted file mode 100644
index ff501e511d9..00000000000
--- a/arch/x86/include/asm/cpu_device_id.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CPU_DEVICE_ID
-#define _CPU_DEVICE_ID 1
-
-/*
- * Declare drivers belonging to specific x86 CPUs
- * Similar in spirit to pci_device_id and related PCI functions
- */
-
-#include <linux/mod_devicetable.h>
-
-extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match);
-
-#endif
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 2d9075e863a..88b23a43f34 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -4,9 +4,7 @@
 #ifndef _ASM_X86_CPUFEATURE_H
 #define _ASM_X86_CPUFEATURE_H
 
-#ifndef _ASM_X86_REQUIRED_FEATURES_H
 #include <asm/required-features.h>
-#endif
 
 #define NCAPINTS        10      /* N 32-bit words worth of info */
 
@@ -99,7 +97,6 @@
 #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
 #define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF  (3*32+28) /* APERFMPERF */
-#define X86_FEATURE_EAGER_FPU   (3*32+29) /* "eagerfpu" Non lazy FPU restore */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
@@ -117,14 +114,12 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_PDCM        (4*32+15) /* Performance Capabilities */
-#define X86_FEATURE_PCID        (4*32+17) /* Process Context Identifiers */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
 #define X86_FEATURE_XMM4_1      (4*32+19) /* "sse4_1" SSE-4.1 */
 #define X86_FEATURE_XMM4_2      (4*32+20) /* "sse4_2" SSE-4.2 */
 #define X86_FEATURE_X2APIC      (4*32+21) /* x2APIC */
 #define X86_FEATURE_MOVBE       (4*32+22) /* MOVBE instruction */
 #define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
-#define X86_FEATURE_TSC_DEADLINE_TIMER  (4*32+24) /* Tsc deadline timer */
 #define X86_FEATURE_AES         (4*32+25) /* AES instructions */
 #define X86_FEATURE_XSAVE       (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 #define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
@@ -162,7 +157,6 @@
 #define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
 #define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
 #define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
-#define X86_FEATURE_TCE         (6*32+17) /* translation cache extension */
 #define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
 #define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
 #define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
@@ -179,8 +173,7 @@
 #define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
 #define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
 #define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
-#define X86_FEATURE_DTHERM      (7*32+ 7) /* Digital Thermal Sensor */
-#define X86_FEATURE_HW_PSTATE   (7*32+ 8) /* AMD HW-PState */
+#define X86_FEATURE_DTS         (7*32+ 7) /* Digital Thermal Sensor */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -202,18 +195,8 @@
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
 #define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
-#define X86_FEATURE_TSC_ADJUST  (9*32+ 1) /* TSC adjustment MSR 0x3b */
-#define X86_FEATURE_BMI1        (9*32+ 3) /* 1st group bit manipulation extensions */
-#define X86_FEATURE_HLE         (9*32+ 4) /* Hardware Lock Elision */
-#define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
 #define X86_FEATURE_SMEP        (9*32+ 7) /* Supervisor Mode Execution Protection */
-#define X86_FEATURE_BMI2        (9*32+ 8) /* 2nd group bit manipulation extensions */
 #define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
-#define X86_FEATURE_INVPCID     (9*32+10) /* Invalidate Processor Context ID */
-#define X86_FEATURE_RTM         (9*32+11) /* Restricted Transactional Memory */
-#define X86_FEATURE_RDSEED      (9*32+18) /* The RDSEED instruction */
-#define X86_FEATURE_ADX         (9*32+19) /* The ADCX and ADOX instructions */
-#define X86_FEATURE_SMAP        (9*32+20) /* Supervisor Mode Access Prevention */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
@@ -274,9 +257,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
 #define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
 #define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
-#define cpu_has_ssse3           boot_cpu_has(X86_FEATURE_SSSE3)
 #define cpu_has_aes             boot_cpu_has(X86_FEATURE_AES)
-#define cpu_has_avx             boot_cpu_has(X86_FEATURE_AVX)
 #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
 #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
@@ -304,15 +285,17 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
 #define cpu_has_x2apic          boot_cpu_has(X86_FEATURE_X2APIC)
 #define cpu_has_xsave           boot_cpu_has(X86_FEATURE_XSAVE)
-#define cpu_has_xsaveopt        boot_cpu_has(X86_FEATURE_XSAVEOPT)
-#define cpu_has_osxsave         boot_cpu_has(X86_FEATURE_OSXSAVE)
 #define cpu_has_hypervisor      boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
 #define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
-#define cpu_has_eager_fpu       boot_cpu_has(X86_FEATURE_EAGER_FPU)
-#define cpu_has_topoext         boot_cpu_has(X86_FEATURE_TOPOEXT)
+
+#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
+# define cpu_has_invlpg         1
+#else
+# define cpu_has_invlpg         (boot_cpu_data.x86 > 3)
+#endif
 
 #ifdef CONFIG_X86_64
 
diff --git a/arch/x86/include/asm/crypto/ablk_helper.h b/arch/x86/include/asm/crypto/ablk_helper.h
deleted file mode 100644
index 4f93df50c23..00000000000
--- a/arch/x86/include/asm/crypto/ablk_helper.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Shared async block cipher helpers
- */
-
-#ifndef _CRYPTO_ABLK_HELPER_H
-#define _CRYPTO_ABLK_HELPER_H
-
-#include <linux/crypto.h>
-#include <linux/kernel.h>
-#include <crypto/cryptd.h>
-
-struct async_helper_ctx {
-        struct cryptd_ablkcipher *cryptd_tfm;
-};
-
-extern int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
-                        unsigned int key_len);
-
-extern int __ablk_encrypt(struct ablkcipher_request *req);
-
-extern int ablk_encrypt(struct ablkcipher_request *req);
-
-extern int ablk_decrypt(struct ablkcipher_request *req);
-
-extern void ablk_exit(struct crypto_tfm *tfm);
-
-extern int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name);
-
-extern int ablk_init(struct crypto_tfm *tfm);
-
-#endif /* _CRYPTO_ABLK_HELPER_H */
diff --git a/arch/x86/include/asm/crypto/aes.h b/arch/x86/include/asm/crypto/aes.h
deleted file mode 100644
index 80545a1cbe3..00000000000
--- a/arch/x86/include/asm/crypto/aes.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef ASM_X86_AES_H
-#define ASM_X86_AES_H
-
-#include <linux/crypto.h>
-#include <crypto/aes.h>
-
-void crypto_aes_encrypt_x86(struct crypto_aes_ctx *ctx, u8 *dst,
-                            const u8 *src);
-void crypto_aes_decrypt_x86(struct crypto_aes_ctx *ctx, u8 *dst,
-                            const u8 *src);
-#endif
diff --git a/arch/x86/include/asm/crypto/camellia.h b/arch/x86/include/asm/crypto/camellia.h
deleted file mode 100644
index 98038add801..00000000000
--- a/arch/x86/include/asm/crypto/camellia.h
+++ /dev/null
@@ -1,82 +0,0 @@
-#ifndef ASM_X86_CAMELLIA_H
-#define ASM_X86_CAMELLIA_H
-
-#include <linux/kernel.h>
-#include <linux/crypto.h>
-
-#define CAMELLIA_MIN_KEY_SIZE   16
-#define CAMELLIA_MAX_KEY_SIZE   32
-#define CAMELLIA_BLOCK_SIZE     16
-#define CAMELLIA_TABLE_BYTE_LEN 272
-#define CAMELLIA_PARALLEL_BLOCKS 2
-
-struct camellia_ctx {
-        u64 key_table[CAMELLIA_TABLE_BYTE_LEN / sizeof(u64)];
-        u32 key_length;
-};
-
-struct camellia_lrw_ctx {
-        struct lrw_table_ctx lrw_table;
-        struct camellia_ctx camellia_ctx;
-};
-
-struct camellia_xts_ctx {
-        struct camellia_ctx tweak_ctx;
-        struct camellia_ctx crypt_ctx;
-};
-
-extern int __camellia_setkey(struct camellia_ctx *cctx,
-                             const unsigned char *key,
-                             unsigned int key_len, u32 *flags);
-
-extern int lrw_camellia_setkey(struct crypto_tfm *tfm, const u8 *key,
-                               unsigned int keylen);
-extern void lrw_camellia_exit_tfm(struct crypto_tfm *tfm);
-
-extern int xts_camellia_setkey(struct crypto_tfm *tfm, const u8 *key,
-                               unsigned int keylen);
-
-/* regular block cipher functions */
-asmlinkage void __camellia_enc_blk(struct camellia_ctx *ctx, u8 *dst,
-                                   const u8 *src, bool xor);
-asmlinkage void camellia_dec_blk(struct camellia_ctx *ctx, u8 *dst,
-                                 const u8 *src);
-
-/* 2-way parallel cipher functions */
-asmlinkage void __camellia_enc_blk_2way(struct camellia_ctx *ctx, u8 *dst,
-                                        const u8 *src, bool xor);
-asmlinkage void camellia_dec_blk_2way(struct camellia_ctx *ctx, u8 *dst,
-                                      const u8 *src);
-
-static inline void camellia_enc_blk(struct camellia_ctx *ctx, u8 *dst,
-                                    const u8 *src)
-{
-        __camellia_enc_blk(ctx, dst, src, false);
-}
-
-static inline void camellia_enc_blk_xor(struct camellia_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        __camellia_enc_blk(ctx, dst, src, true);
-}
-
-static inline void camellia_enc_blk_2way(struct camellia_ctx *ctx, u8 *dst,
-                                         const u8 *src)
-{
-        __camellia_enc_blk_2way(ctx, dst, src, false);
-}
-
-static inline void camellia_enc_blk_xor_2way(struct camellia_ctx *ctx, u8 *dst,
-                                             const u8 *src)
-{
-        __camellia_enc_blk_2way(ctx, dst, src, true);
-}
-
-/* glue helpers */
-extern void camellia_decrypt_cbc_2way(void *ctx, u128 *dst, const u128 *src);
-extern void camellia_crypt_ctr(void *ctx, u128 *dst, const u128 *src,
-                               le128 *iv);
-extern void camellia_crypt_ctr_2way(void *ctx, u128 *dst, const u128 *src,
-                                    le128 *iv);
-
-#endif /* ASM_X86_CAMELLIA_H */
diff --git a/arch/x86/include/asm/crypto/glue_helper.h b/arch/x86/include/asm/crypto/glue_helper.h
deleted file mode 100644
index e2d65b061d2..00000000000
--- a/arch/x86/include/asm/crypto/glue_helper.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Shared glue code for 128bit block ciphers
- */
-
-#ifndef _CRYPTO_GLUE_HELPER_H
-#define _CRYPTO_GLUE_HELPER_H
-
-#include <linux/kernel.h>
-#include <linux/crypto.h>
-#include <asm/i387.h>
-#include <crypto/b128ops.h>
-
-typedef void (*common_glue_func_t)(void *ctx, u8 *dst, const u8 *src);
-typedef void (*common_glue_cbc_func_t)(void *ctx, u128 *dst, const u128 *src);
-typedef void (*common_glue_ctr_func_t)(void *ctx, u128 *dst, const u128 *src,
-                                       le128 *iv);
-
-#define GLUE_FUNC_CAST(fn) ((common_glue_func_t)(fn))
-#define GLUE_CBC_FUNC_CAST(fn) ((common_glue_cbc_func_t)(fn))
-#define GLUE_CTR_FUNC_CAST(fn) ((common_glue_ctr_func_t)(fn))
-
-struct common_glue_func_entry {
-        unsigned int num_blocks; /* number of blocks that @fn will process */
-        union {
-                common_glue_func_t ecb;
-                common_glue_cbc_func_t cbc;
-                common_glue_ctr_func_t ctr;
-        } fn_u;
-};
-
-struct common_glue_ctx {
-        unsigned int num_funcs;
-        int fpu_blocks_limit; /* -1 means fpu not needed at all */
-
-        /*
-         * First funcs entry must have largest num_blocks and last funcs entry
-         * must have num_blocks == 1!
-         */
-        struct common_glue_func_entry funcs[];
-};
-
-static inline bool glue_fpu_begin(unsigned int bsize, int fpu_blocks_limit,
-                                  struct blkcipher_desc *desc,
-                                  bool fpu_enabled, unsigned int nbytes)
-{
-        if (likely(fpu_blocks_limit < 0))
-                return false;
-
-        if (fpu_enabled)
-                return true;
-
-        /*
-         * Vector-registers are only used when chunk to be processed is large
-         * enough, so do not enable FPU until it is necessary.
-         */
-        if (nbytes < bsize * (unsigned int)fpu_blocks_limit)
-                return false;
-
-        if (desc) {
-                /* prevent sleeping if FPU is in use */
-                desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        }
-
-        kernel_fpu_begin();
-        return true;
-}
-
-static inline void glue_fpu_end(bool fpu_enabled)
-{
-        if (fpu_enabled)
-                kernel_fpu_end();
-}
-
-static inline void le128_to_be128(be128 *dst, const le128 *src)
-{
-        dst->a = cpu_to_be64(le64_to_cpu(src->a));
-        dst->b = cpu_to_be64(le64_to_cpu(src->b));
-}
-
-static inline void be128_to_le128(le128 *dst, const be128 *src)
-{
-        dst->a = cpu_to_le64(be64_to_cpu(src->a));
-        dst->b = cpu_to_le64(be64_to_cpu(src->b));
-}
-
-static inline void le128_inc(le128 *i)
-{
-        u64 a = le64_to_cpu(i->a);
-        u64 b = le64_to_cpu(i->b);
-
-        b++;
-        if (!b)
-                a++;
-
-        i->a = cpu_to_le64(a);
-        i->b = cpu_to_le64(b);
-}
-
-extern int glue_ecb_crypt_128bit(const struct common_glue_ctx *gctx,
-                                 struct blkcipher_desc *desc,
-                                 struct scatterlist *dst,
-                                 struct scatterlist *src, unsigned int nbytes);
-
-extern int glue_cbc_encrypt_128bit(const common_glue_func_t fn,
-                                   struct blkcipher_desc *desc,
-                                   struct scatterlist *dst,
-                                   struct scatterlist *src,
-                                   unsigned int nbytes);
-
-extern int glue_cbc_decrypt_128bit(const struct common_glue_ctx *gctx,
-                                   struct blkcipher_desc *desc,
-                                   struct scatterlist *dst,
-                                   struct scatterlist *src,
-                                   unsigned int nbytes);
-
-extern int glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
-                                 struct blkcipher_desc *desc,
-                                 struct scatterlist *dst,
-                                 struct scatterlist *src, unsigned int nbytes);
-
-#endif /* _CRYPTO_GLUE_HELPER_H */
diff --git a/arch/x86/include/asm/crypto/serpent-avx.h b/arch/x86/include/asm/crypto/serpent-avx.h
deleted file mode 100644
index 0da1d3e2a55..00000000000
--- a/arch/x86/include/asm/crypto/serpent-avx.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef ASM_X86_SERPENT_AVX_H
-#define ASM_X86_SERPENT_AVX_H
-
-#include <linux/crypto.h>
-#include <crypto/serpent.h>
-
-#define SERPENT_PARALLEL_BLOCKS 8
-
-asmlinkage void serpent_ecb_enc_8way_avx(struct serpent_ctx *ctx, u8 *dst,
-                                         const u8 *src);
-asmlinkage void serpent_ecb_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
-                                         const u8 *src);
-
-asmlinkage void serpent_cbc_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
-                                         const u8 *src);
-asmlinkage void serpent_ctr_8way_avx(struct serpent_ctx *ctx, u8 *dst,
-                                     const u8 *src, le128 *iv);
-
-#endif
diff --git a/arch/x86/include/asm/crypto/serpent-sse2.h b/arch/x86/include/asm/crypto/serpent-sse2.h
deleted file mode 100644
index e6e77dffbda..00000000000
--- a/arch/x86/include/asm/crypto/serpent-sse2.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef ASM_X86_SERPENT_SSE2_H
-#define ASM_X86_SERPENT_SSE2_H
-
-#include <linux/crypto.h>
-#include <crypto/serpent.h>
-
-#ifdef CONFIG_X86_32
-
-#define SERPENT_PARALLEL_BLOCKS 4
-
-asmlinkage void __serpent_enc_blk_4way(struct serpent_ctx *ctx, u8 *dst,
-                                       const u8 *src, bool xor);
-asmlinkage void serpent_dec_blk_4way(struct serpent_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-
-static inline void serpent_enc_blk_xway(struct serpent_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        __serpent_enc_blk_4way(ctx, dst, src, false);
-}
-
-static inline void serpent_enc_blk_xway_xor(struct serpent_ctx *ctx, u8 *dst,
-                                            const u8 *src)
-{
-        __serpent_enc_blk_4way(ctx, dst, src, true);
-}
-
-static inline void serpent_dec_blk_xway(struct serpent_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        serpent_dec_blk_4way(ctx, dst, src);
-}
-
-#else
-
-#define SERPENT_PARALLEL_BLOCKS 8
-
-asmlinkage void __serpent_enc_blk_8way(struct serpent_ctx *ctx, u8 *dst,
-                                       const u8 *src, bool xor);
-asmlinkage void serpent_dec_blk_8way(struct serpent_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-
-static inline void serpent_enc_blk_xway(struct serpent_ctx *ctx, u8 *dst,
-                                   const u8 *src)
-{
-        __serpent_enc_blk_8way(ctx, dst, src, false);
-}
-
-static inline void serpent_enc_blk_xway_xor(struct serpent_ctx *ctx, u8 *dst,
-                                       const u8 *src)
-{
-        __serpent_enc_blk_8way(ctx, dst, src, true);
-}
-
-static inline void serpent_dec_blk_xway(struct serpent_ctx *ctx, u8 *dst,
-                                   const u8 *src)
-{
-        serpent_dec_blk_8way(ctx, dst, src);
-}
-
-#endif
-
-#endif
diff --git a/arch/x86/include/asm/crypto/twofish.h b/arch/x86/include/asm/crypto/twofish.h
deleted file mode 100644
index 878c51ceebb..00000000000
--- a/arch/x86/include/asm/crypto/twofish.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef ASM_X86_TWOFISH_H
-#define ASM_X86_TWOFISH_H
-
-#include <linux/crypto.h>
-#include <crypto/twofish.h>
-#include <crypto/lrw.h>
-#include <crypto/b128ops.h>
-
-struct twofish_lrw_ctx {
-        struct lrw_table_ctx lrw_table;
-        struct twofish_ctx twofish_ctx;
-};
-
-struct twofish_xts_ctx {
-        struct twofish_ctx tweak_ctx;
-        struct twofish_ctx crypt_ctx;
-};
-
-/* regular block cipher functions from twofish_x86_64 module */
-asmlinkage void twofish_enc_blk(struct twofish_ctx *ctx, u8 *dst,
-                                const u8 *src);
-asmlinkage void twofish_dec_blk(struct twofish_ctx *ctx, u8 *dst,
-                                const u8 *src);
-
-/* 3-way parallel cipher functions */
-asmlinkage void __twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
-                                       const u8 *src, bool xor);
-asmlinkage void twofish_dec_blk_3way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-
-/* helpers from twofish_x86_64-3way module */
-extern void twofish_dec_blk_cbc_3way(void *ctx, u128 *dst, const u128 *src);
-extern void twofish_enc_blk_ctr(void *ctx, u128 *dst, const u128 *src,
-                                le128 *iv);
-extern void twofish_enc_blk_ctr_3way(void *ctx, u128 *dst, const u128 *src,
-                                     le128 *iv);
-
-extern int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen);
-
-extern void lrw_twofish_exit_tfm(struct crypto_tfm *tfm);
-
-extern int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen);
-
-#endif /* ASM_X86_TWOFISH_H */
diff --git a/arch/x86/include/asm/current.h b/arch/x86/include/asm/current.h
index 9476c04ee63..4d447b732d8 100644
--- a/arch/x86/include/asm/current.h
+++ b/arch/x86/include/asm/current.h
@@ -11,7 +11,7 @@ DECLARE_PER_CPU(struct task_struct *, current_task);
 
 static __always_inline struct task_struct *get_current(void)
 {
-        return this_cpu_read_stable(current_task);
+        return percpu_read_stable(current_task);
 }
 
 #define current get_current()
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 4b528a970bd..078ad0caefc 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -2,75 +2,83 @@
 #define _ASM_X86_DEBUGREG_H
 
 
-#include <linux/bug.h>
-#include <uapi/asm/debugreg.h>
+/* Indicate the register numbers for a number of the specific
+   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
+#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
+#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
 
-DECLARE_PER_CPU(unsigned long, cpu_dr7);
+#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
+#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
 
-#ifndef CONFIG_PARAVIRT
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register)                             \
-        (var) = native_get_debugreg(register)
-#define set_debugreg(value, register)                           \
-        native_set_debugreg(register, value)
+/* Define a few things for the status register.  We can use this to determine
+   which debugging register was responsible for the trap.  The other bits
+   are either reserved or not of interest to us. */
+
+/* Define reserved bits in DR6 which are always set to 1 */
+#define DR6_RESERVED    (0xFFFF0FF0)
+
+#define DR_TRAP0        (0x1)           /* db0 */
+#define DR_TRAP1        (0x2)           /* db1 */
+#define DR_TRAP2        (0x4)           /* db2 */
+#define DR_TRAP3        (0x8)           /* db3 */
+#define DR_TRAP_BITS    (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
+
+#define DR_STEP         (0x4000)        /* single-step */
+#define DR_SWITCH       (0x8000)        /* task switch */
+
+/* Now define a bunch of things for manipulating the control register.
+   The top two bytes of the control register consist of 4 fields of 4
+   bits - each field corresponds to one of the four debug registers,
+   and indicates what types of access we trap on, and how large the data
+   field is that we are looking at */
+
+#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
+#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
+
+#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
+#define DR_RW_WRITE (0x1)
+#define DR_RW_READ (0x3)
+
+#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
+#define DR_LEN_2 (0x4)
+#define DR_LEN_4 (0xC)
+#define DR_LEN_8 (0x8)
+
+/* The low byte to the control register determine which registers are
+   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
+   that the processor will reset the bit after a task switch and the other
+   is global meaning that we have to explicitly reset the bit.  With linux,
+   you can use either one, since we explicitly zero the register when we enter
+   kernel mode. */
+
+#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
+#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
+#define DR_LOCAL_ENABLE (0x1)      /* Local enable for reg 0 */
+#define DR_GLOBAL_ENABLE (0x2)     /* Global enable for reg 0 */
+#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
+
+#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
+#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
+
+/* The second byte to the control register has a few special things.
+   We can slow the instruction pipeline for instructions coming via the
+   gdt or the ldt if we want to.  I am not sure why this is an advantage */
+
+#ifdef __i386__
+#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
+#else
+#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
 #endif
 
-static inline unsigned long native_get_debugreg(int regno)
-{
-        unsigned long val = 0;  /* Damn you, gcc! */
-
-        switch (regno) {
-        case 0:
-                asm("mov %%db0, %0" :"=r" (val));
-                break;
-        case 1:
-                asm("mov %%db1, %0" :"=r" (val));
-                break;
-        case 2:
-                asm("mov %%db2, %0" :"=r" (val));
-                break;
-        case 3:
-                asm("mov %%db3, %0" :"=r" (val));
-                break;
-        case 6:
-                asm("mov %%db6, %0" :"=r" (val));
-                break;
-        case 7:
-                asm("mov %%db7, %0" :"=r" (val));
-                break;
-        default:
-                BUG();
-        }
-        return val;
-}
+#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
+#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
 
-static inline void native_set_debugreg(int regno, unsigned long value)
-{
-        switch (regno) {
-        case 0:
-                asm("mov %0, %%db0"     ::"r" (value));
-                break;
-        case 1:
-                asm("mov %0, %%db1"     ::"r" (value));
-                break;
-        case 2:
-                asm("mov %0, %%db2"     ::"r" (value));
-                break;
-        case 3:
-                asm("mov %0, %%db3"     ::"r" (value));
-                break;
-        case 6:
-                asm("mov %0, %%db6"     ::"r" (value));
-                break;
-        case 7:
-                asm("mov %0, %%db7"     ::"r" (value));
-                break;
-        default:
-                BUG();
-        }
-}
+/*
+ * HW breakpoint additions
+ */
+#ifdef __KERNEL__
+
+DECLARE_PER_CPU(unsigned long, cpu_dr7);
 
 static inline void hw_breakpoint_disable(void)
 {
@@ -93,26 +101,6 @@ extern void aout_dump_debugregs(struct user *dump);
 
 extern void hw_breakpoint_restore(void);
 
-#ifdef CONFIG_X86_64
-DECLARE_PER_CPU(int, debug_stack_usage);
-static inline void debug_stack_usage_inc(void)
-{
-        __get_cpu_var(debug_stack_usage)++;
-}
-static inline void debug_stack_usage_dec(void)
-{
-        __get_cpu_var(debug_stack_usage)--;
-}
-int is_debug_stack(unsigned long addr);
-void debug_stack_set_zero(void);
-void debug_stack_reset(void);
-#else /* !X86_64 */
-static inline int is_debug_stack(unsigned long addr) { return 0; }
-static inline void debug_stack_set_zero(void) { }
-static inline void debug_stack_reset(void) { }
-static inline void debug_stack_usage_inc(void) { }
-static inline void debug_stack_usage_dec(void) { }
-#endif /* X86_64 */
-
+#endif  /* __KERNEL__ */
 
 #endif /* _ASM_X86_DEBUGREG_H */
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 8bf1c06070d..41935fadfdf 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -6,7 +6,6 @@
 #include <asm/mmu.h>
 
 #include <linux/smp.h>
-#include <linux/percpu.h>
 
 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
 {
@@ -36,8 +35,6 @@ static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *in
 
 extern struct desc_ptr idt_descr;
 extern gate_desc idt_table[];
-extern struct desc_ptr nmi_idt_descr;
-extern gate_desc nmi_idt_table[];
 
 struct gdt_page {
         struct desc_struct gdt[GDT_ENTRIES];
@@ -310,16 +307,6 @@ static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
         desc->limit = (limit >> 16) & 0xf;
 }
 
-#ifdef CONFIG_X86_64
-static inline void set_nmi_gate(int gate, void *addr)
-{
-        gate_desc s;
-
-        pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
-        write_idt_entry(nmi_idt_table, gate, &s);
-}
-#endif
-
 static inline void _set_gate(int gate, unsigned type, void *addr,
                              unsigned dpl, unsigned ist, unsigned seg)
 {
diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h
index 03dd72957d2..63a2a03d7d5 100644
--- a/arch/x86/include/asm/device.h
+++ b/arch/x86/include/asm/device.h
@@ -2,8 +2,11 @@
 #define _ASM_X86_DEVICE_H
 
 struct dev_archdata {
-#ifdef CONFIG_X86_DEV_DMA_OPS
-        struct dma_map_ops *dma_ops;
+#ifdef CONFIG_ACPI
+        void    *acpi_handle;
+#endif
+#ifdef CONFIG_X86_64
+struct dma_map_ops *dma_ops;
 #endif
 #if defined(CONFIG_INTEL_IOMMU) || defined(CONFIG_AMD_IOMMU)
         void *iommu; /* hook for IOMMU specific extension */
diff --git a/arch/x86/include/asm/div64.h b/arch/x86/include/asm/div64.h
index ced283ac79d..9a2d644c08e 100644
--- a/arch/x86/include/asm/div64.h
+++ b/arch/x86/include/asm/div64.h
@@ -4,7 +4,6 @@
 #ifdef CONFIG_X86_32
 
 #include <linux/types.h>
-#include <linux/log2.h>
 
 /*
  * do_div() is NOT a C function. It wants to return
@@ -22,20 +21,15 @@
 ({                                                              \
         unsigned long __upper, __low, __high, __mod, __base;    \
         __base = (base);                                        \
-        if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \
-                __mod = n & (__base - 1);                       \
-                n >>= ilog2(__base);                            \
-        } else {                                                \
-                asm("" : "=a" (__low), "=d" (__high) : "A" (n));\
-                __upper = __high;                               \
-                if (__high) {                                   \
-                        __upper = __high % (__base);            \
-                        __high = __high / (__base);             \
-                }                                               \
-                asm("divl %2" : "=a" (__low), "=d" (__mod)      \
-                        : "rm" (__base), "0" (__low), "1" (__upper));   \
-                asm("" : "=A" (n) : "a" (__low), "d" (__high)); \
+        asm("":"=a" (__low), "=d" (__high) : "A" (n));          \
+        __upper = __high;                                       \
+        if (__high) {                                           \
+                __upper = __high % (__base);                    \
+                __high = __high / (__base);                     \
         }                                                       \
+        asm("divl %2":"=a" (__low), "=d" (__mod)                \
+            : "rm" (__base), "0" (__low), "1" (__upper));       \
+        asm("":"=A" (n) : "a" (__low), "d" (__high));           \
         __mod;                                                  \
 })
 
diff --git a/arch/x86/include/asm/dma-contiguous.h b/arch/x86/include/asm/dma-contiguous.h
deleted file mode 100644
index c0924165997..00000000000
--- a/arch/x86/include/asm/dma-contiguous.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef ASMX86_DMA_CONTIGUOUS_H
-#define ASMX86_DMA_CONTIGUOUS_H
-
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <asm-generic/dma-contiguous.h>
-
-static inline void
-dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { }
-
-#endif
-#endif
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index 808dae63eee..d4c419f883a 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -2,7 +2,7 @@
 #define _ASM_X86_DMA_MAPPING_H
 
 /*
- * IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
+ * IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and
  * Documentation/DMA-API.txt for documentation.
  */
 
@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/swiotlb.h>
 #include <asm-generic/dma-coherent.h>
-#include <linux/dma-contiguous.h>
 
 #ifdef CONFIG_ISA
 # define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
@@ -31,7 +30,7 @@ extern struct dma_map_ops *dma_ops;
 
 static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 {
-#ifndef CONFIG_X86_DEV_DMA_OPS
+#ifdef CONFIG_X86_32
         return dma_ops;
 #else
         if (unlikely(!dev) || !dev->archdata.dma_ops)
@@ -47,7 +46,6 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
-        debug_dma_mapping_error(dev, dma_addr);
         if (ops->mapping_error)
                 return ops->mapping_error(dev, dma_addr);
 
@@ -61,18 +59,7 @@ extern int dma_supported(struct device *hwdev, u64 mask);
 extern int dma_set_mask(struct device *dev, u64 mask);
 
 extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-                                        dma_addr_t *dma_addr, gfp_t flag,
-                                        struct dma_attrs *attrs);
-
-extern void dma_generic_free_coherent(struct device *dev, size_t size,
-                                      void *vaddr, dma_addr_t dma_addr,
-                                      struct dma_attrs *attrs);
-
-#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
-extern bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
-extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
-extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
-#else
+                                        dma_addr_t *dma_addr, gfp_t flag);
 
 static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
 {
@@ -91,7 +78,6 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
 {
         return daddr;
 }
-#endif /* CONFIG_X86_DMA_REMAP */
 
 static inline void
 dma_cache_sync(struct device *dev, void *vaddr, size_t size,
@@ -125,11 +111,9 @@ static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
        return gfp;
 }
 
-#define dma_alloc_coherent(d,s,h,f)     dma_alloc_attrs(d,s,h,f,NULL)
-
 static inline void *
-dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                gfp_t gfp, struct dma_attrs *attrs)
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
+                gfp_t gfp)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
         void *memory;
@@ -145,21 +129,18 @@ dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
         if (!is_device_dma_capable(dev))
                 return NULL;
 
-        if (!ops->alloc)
+        if (!ops->alloc_coherent)
                 return NULL;
 
-        memory = ops->alloc(dev, size, dma_handle,
-                            dma_alloc_coherent_gfp_flags(dev, gfp), attrs);
+        memory = ops->alloc_coherent(dev, size, dma_handle,
+                                     dma_alloc_coherent_gfp_flags(dev, gfp));
         debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
 
         return memory;
 }
 
-#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
-
-static inline void dma_free_attrs(struct device *dev, size_t size,
-                                  void *vaddr, dma_addr_t bus,
-                                  struct dma_attrs *attrs)
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t bus)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
 
@@ -169,8 +150,8 @@ static inline void dma_free_attrs(struct device *dev, size_t size,
                 return;
 
         debug_dma_free_coherent(dev, size, vaddr, bus);
-        if (ops->free)
-                ops->free(dev, size, vaddr, bus, attrs);
+        if (ops->free_coherent)
+                ops->free_coherent(dev, size, vaddr, bus);
 }
 
 #endif
diff --git a/arch/x86/include/asm/dwarf2.h b/arch/x86/include/asm/dwarf2.h
index f6f15986df6..32609919931 100644
--- a/arch/x86/include/asm/dwarf2.h
+++ b/arch/x86/include/asm/dwarf2.h
@@ -27,7 +27,6 @@
 #define CFI_REMEMBER_STATE      .cfi_remember_state
 #define CFI_RESTORE_STATE       .cfi_restore_state
 #define CFI_UNDEFINED           .cfi_undefined
-#define CFI_ESCAPE              .cfi_escape
 
 #ifdef CONFIG_AS_CFI_SIGNAL_FRAME
 #define CFI_SIGNAL_FRAME        .cfi_signal_frame
@@ -69,7 +68,6 @@
 #define CFI_REMEMBER_STATE      cfi_ignore
 #define CFI_RESTORE_STATE       cfi_ignore
 #define CFI_UNDEFINED           cfi_ignore
-#define CFI_ESCAPE              cfi_ignore
 #define CFI_SIGNAL_FRAME        cfi_ignore
 
 #endif
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index cccd07fa5e3..908b96957d8 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -1,14 +1,81 @@
 #ifndef _ASM_X86_E820_H
 #define _ASM_X86_E820_H
+#define E820MAP 0x2d0           /* our map */
+#define E820MAX 128             /* number of entries in E820MAP */
 
+/*
+ * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
+ * constrained space in the zeropage.  If we have more nodes than
+ * that, and if we've booted off EFI firmware, then the EFI tables
+ * passed us from the EFI firmware can list more nodes.  Size our
+ * internal memory map tables to have room for these additional
+ * nodes, based on up to three entries per node for which the
+ * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
+ * plus E820MAX, allowing space for the possible duplicate E820
+ * entries that might need room in the same arrays, prior to the
+ * call to sanitize_e820_map() to remove duplicates.  The allowance
+ * of three memory map entries per node is "enough" entries for
+ * the initial hardware platform motivating this mechanism to make
+ * use of additional EFI map entries.  Future platforms may want
+ * to allow more than three entries per node or otherwise refine
+ * this size.
+ */
+
+/*
+ * Odd: 'make headers_check' complains about numa.h if I try
+ * to collapse the next two #ifdef lines to a single line:
+ *      #if defined(__KERNEL__) && defined(CONFIG_EFI)
+ */
+#ifdef __KERNEL__
 #ifdef CONFIG_EFI
 #include <linux/numa.h>
 #define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES)
 #else   /* ! CONFIG_EFI */
 #define E820_X_MAX E820MAX
 #endif
-#include <uapi/asm/e820.h>
+#else   /* ! __KERNEL__ */
+#define E820_X_MAX E820MAX
+#endif
+
+#define E820NR  0x1e8           /* # entries in E820MAP */
+
+#define E820_RAM        1
+#define E820_RESERVED   2
+#define E820_ACPI       3
+#define E820_NVS        4
+#define E820_UNUSABLE   5
+
+/*
+ * reserved RAM used by kernel itself
+ * if CONFIG_INTEL_TXT is enabled, memory of this type will be
+ * included in the S3 integrity calculation and so should not include
+ * any memory that BIOS might alter over the S3 transition
+ */
+#define E820_RESERVED_KERN        128
+
 #ifndef __ASSEMBLY__
+#include <linux/types.h>
+struct e820entry {
+        __u64 addr;     /* start of memory segment */
+        __u64 size;     /* size of memory segment */
+        __u32 type;     /* type of memory segment */
+} __attribute__((packed));
+
+struct e820map {
+        __u32 nr_map;
+        struct e820entry map[E820_X_MAX];
+};
+
+#define ISA_START_ADDRESS       0xa0000
+#define ISA_END_ADDRESS         0x100000
+
+#define BIOS_BEGIN              0x000a0000
+#define BIOS_END                0x00100000
+
+#define BIOS_ROM_BASE           0xffe00000
+#define BIOS_ROM_END            0xffffffff
+
+#ifdef __KERNEL__
 /* see comment in arch/x86/kernel/e820.c */
 extern struct e820map e820;
 extern struct e820map e820_saved;
@@ -50,7 +117,7 @@ static inline void early_memtest(unsigned long start, unsigned long end)
 
 extern unsigned long e820_end_of_ram_pfn(void);
 extern unsigned long e820_end_of_low_ram_pfn(void);
-extern u64 early_reserve_e820(u64 sizet, u64 align);
+extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
 
 void memblock_x86_fill(void);
 void memblock_find_dma_reserve(void);
@@ -70,8 +137,13 @@ static inline bool is_ISA_range(u64 s, u64 e)
         return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS;
 }
 
+#endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
 #include <linux/ioport.h>
 
 #define HIGH_MEMORY     (1024*1024)
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_X86_E820_H */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 6e8fdf5ad11..7093e4a6a0b 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -3,8 +3,6 @@
 
 #ifdef CONFIG_X86_32
 
-#define EFI_LOADER_SIGNATURE    "EL32"
-
 extern unsigned long asmlinkage efi_call_phys(void *, ...);
 
 #define efi_call_phys0(f)               efi_call_phys(f)
@@ -35,12 +33,10 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...);
 #define efi_call_virt6(f, a1, a2, a3, a4, a5, a6)       \
         efi_call_virt(f, a1, a2, a3, a4, a5, a6)
 
-#define efi_ioremap(addr, size, type, attr)     ioremap_cache(addr, size)
+#define efi_ioremap(addr, size, type)           ioremap_cache(addr, size)
 
 #else /* !CONFIG_X86_32 */
 
-#define EFI_LOADER_SIGNATURE    "EL64"
-
 extern u64 efi_call0(void *fp);
 extern u64 efi_call1(void *fp, u64 arg1);
 extern u64 efi_call2(void *fp, u64 arg1, u64 arg2);
@@ -89,17 +85,15 @@ extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3,
                   (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6))
 
 extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size,
-                                 u32 type, u64 attribute);
+                                 u32 type);
 
 #endif /* CONFIG_X86_32 */
 
 extern int add_efi_memmap;
 extern void efi_set_executable(efi_memory_desc_t *md, bool executable);
-extern int efi_memblock_x86_reserve_range(void);
+extern void efi_memblock_x86_reserve_range(void);
 extern void efi_call_phys_prelog(void);
 extern void efi_call_phys_epilog(void);
-extern void efi_unmap_memmap(void);
-extern void efi_memory_uc(u64 addr, unsigned long size);
 
 #ifndef CONFIG_EFI
 /*
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 9c999c1674f..f2ad2163109 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -4,7 +4,6 @@
 /*
  * ELF register definitions..
  */
-#include <linux/thread_info.h>
 
 #include <asm/ptrace.h>
 #include <asm/user.h>
@@ -84,6 +83,7 @@ extern unsigned int vdso_enabled;
         (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
 
 #include <asm/processor.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_X86_32
 #include <asm/desc.h>
@@ -155,12 +155,7 @@ do {						\
 #define elf_check_arch(x)                       \
         ((x)->e_machine == EM_X86_64)
 
-#define compat_elf_check_arch(x)                \
-        (elf_check_arch_ia32(x) || (x)->e_machine == EM_X86_64)
-
-#if __USER32_DS != __USER_DS
-# error "The following code assumes __USER32_DS == __USER_DS"
-#endif
+#define compat_elf_check_arch(x)        elf_check_arch_ia32(x)
 
 static inline void elf_common_init(struct thread_struct *t,
                                    struct pt_regs *regs, const u16 ds)
@@ -183,9 +178,8 @@ static inline void elf_common_init(struct thread_struct *t,
 void start_thread_ia32(struct pt_regs *regs, u32 new_ip, u32 new_sp);
 #define compat_start_thread start_thread_ia32
 
-void set_personality_ia32(bool);
-#define COMPAT_SET_PERSONALITY(ex)                      \
-        set_personality_ia32((ex).e_machine == EM_X86_64)
+void set_personality_ia32(void);
+#define COMPAT_SET_PERSONALITY(ex) set_personality_ia32()
 
 #define COMPAT_ELF_PLATFORM                     ("i686")
 
@@ -292,7 +286,7 @@ do {									\
 #define VDSO_HIGH_BASE          0xffffe000U /* CONFIG_COMPAT_VDSO address */
 
 /* 1GB for 64bit, 8MB for 32bit */
-#define STACK_RND_MASK (test_thread_flag(TIF_ADDR32) ? 0x7ff : 0x3fffff)
+#define STACK_RND_MASK (test_thread_flag(TIF_IA32) ? 0x7ff : 0x3fffff)
 
 #define ARCH_DLINFO                                                     \
 do {                                                                    \
@@ -301,20 +295,9 @@ do {									\
                             (unsigned long)current->mm->context.vdso);  \
 } while (0)
 
-#define ARCH_DLINFO_X32                                                 \
-do {                                                                    \
-        if (vdso_enabled)                                               \
-                NEW_AUX_ENT(AT_SYSINFO_EHDR,                            \
-                            (unsigned long)current->mm->context.vdso);  \
-} while (0)
-
 #define AT_SYSINFO              32
 
-#define COMPAT_ARCH_DLINFO                                              \
-if (test_thread_flag(TIF_X32))                                          \
-        ARCH_DLINFO_X32;                                                \
-else                                                                    \
-        ARCH_DLINFO_IA32(sysctl_vsyscall32)
+#define COMPAT_ARCH_DLINFO      ARCH_DLINFO_IA32(sysctl_vsyscall32)
 
 #define COMPAT_ELF_ET_DYN_BASE  (TASK_UNMAPPED_BASE + 0x1000000)
 
@@ -330,8 +313,6 @@ struct linux_binprm;
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                        int uses_interp);
-extern int x32_setup_additional_pages(struct linux_binprm *bprm,
-                                      int uses_interp);
 
 extern int syscall32_setup_pages(struct linux_binprm *, int exstack);
 #define compat_arch_setup_additional_pages      syscall32_setup_pages
@@ -339,32 +320,4 @@ extern int syscall32_setup_pages(struct linux_binprm *, int exstack);
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
-/*
- * True on X86_32 or when emulating IA32 on X86_64
- */
-static inline int mmap_is_ia32(void)
-{
-#ifdef CONFIG_X86_32
-        return 1;
-#endif
-#ifdef CONFIG_IA32_EMULATION
-        if (test_thread_flag(TIF_ADDR32))
-                return 1;
-#endif
-        return 0;
-}
-
-/* Do not change the values. See get_align_mask() */
-enum align_flags {
-        ALIGN_VA_32     = BIT(0),
-        ALIGN_VA_64     = BIT(1),
-};
-
-struct va_alignment {
-        int flags;
-        unsigned long mask;
-} ____cacheline_aligned;
-
-extern struct va_alignment va_align;
-extern unsigned long align_vdso_addr(unsigned long);
 #endif /* _ASM_X86_ELF_H */
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index 75ce3f47d20..cc70c1c78ca 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -4,7 +4,9 @@
 enum reboot_type {
         BOOT_TRIPLE = 't',
         BOOT_KBD = 'k',
+#ifdef CONFIG_X86_32
         BOOT_BIOS = 'b',
+#endif
         BOOT_ACPI = 'a',
         BOOT_EFI = 'e',
         BOOT_CF9 = 'p',
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 40afa0005c6..0baa628e330 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -15,6 +15,15 @@ BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
 BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
 BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
 BUILD_INTERRUPT(reboot_interrupt,REBOOT_VECTOR)
+
+.irp idx,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \
+        16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+.if NUM_INVALIDATE_TLB_VECTORS > \idx
+BUILD_INTERRUPT3(invalidate_interrupt\idx,
+                 (INVALIDATE_TLB_VECTOR_START)+\idx,
+                 smp_invalidate_interrupt)
+.endif
+.endr
 #endif
 
 BUILD_INTERRUPT(x86_platform_ipi, X86_PLATFORM_IPI_VECTOR)
diff --git a/arch/x86/include/asm/exec.h b/arch/x86/include/asm/exec.h
deleted file mode 100644
index 54c2e1db274..00000000000
--- a/arch/x86/include/asm/exec.h
+++ /dev/null
@@ -1 +0,0 @@
-/* define arch_align_stack() here */
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index a09c2857106..460c74e4852 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -19,7 +19,6 @@
 #include <asm/acpi.h>
 #include <asm/apicdef.h>
 #include <asm/page.h>
-#include <asm/pvclock.h>
 #ifdef CONFIG_X86_32
 #include <linux/threads.h>
 #include <asm/kmap_types.h>
@@ -82,10 +81,6 @@ enum fixed_addresses {
         VVAR_PAGE,
         VSYSCALL_HPET,
 #endif
-#ifdef CONFIG_PARAVIRT_CLOCK
-        PVCLOCK_FIXMAP_BEGIN,
-        PVCLOCK_FIXMAP_END = PVCLOCK_FIXMAP_BEGIN+PVCLOCK_VSYSCALL_NR_PAGES-1,
-#endif
         FIX_DBGP_BASE,
         FIX_EARLYCON_MEM_BASE,
 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
@@ -122,7 +117,7 @@ enum fixed_addresses {
 #endif
         FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */
         FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
-#ifdef  CONFIG_X86_INTEL_MID
+#ifdef  CONFIG_X86_MRST
         FIX_LNW_VRTC,
 #endif
         __end_of_permanent_fixed_addresses,
diff --git a/arch/x86/include/asm/floppy.h b/arch/x86/include/asm/floppy.h
index d3d74698dce..dbe82a5c5ea 100644
--- a/arch/x86/include/asm/floppy.h
+++ b/arch/x86/include/asm/floppy.h
@@ -99,7 +99,7 @@ static irqreturn_t floppy_hardint(int irq, void *dev_id)
                 virtual_dma_residue += virtual_dma_count;
                 virtual_dma_count = 0;
 #ifdef TRACE_FLPY_INT
-                printk(KERN_DEBUG "count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
+                printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
                        virtual_dma_count, virtual_dma_residue, calls, bytes,
                        dma_wait);
                 calls = 0;
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
deleted file mode 100644
index 41ab26ea656..00000000000
--- a/arch/x86/include/asm/fpu-internal.h
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * Copyright (C) 1994 Linus Torvalds
- *
- * Pentium III FXSR, SSE support
- * General FPU state handling cleanups
- *      Gareth Hughes <gareth@valinux.com>, May 2000
- * x86-64 work by Andi Kleen 2002
- */
-
-#ifndef _FPU_INTERNAL_H
-#define _FPU_INTERNAL_H
-
-#include <linux/kernel_stat.h>
-#include <linux/regset.h>
-#include <linux/compat.h>
-#include <linux/slab.h>
-#include <asm/asm.h>
-#include <asm/cpufeature.h>
-#include <asm/processor.h>
-#include <asm/sigcontext.h>
-#include <asm/user.h>
-#include <asm/uaccess.h>
-#include <asm/xsave.h>
-#include <asm/smap.h>
-
-#ifdef CONFIG_X86_64
-# include <asm/sigcontext32.h>
-# include <asm/user32.h>
-int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                        compat_sigset_t *set, struct pt_regs *regs);
-int ia32_setup_frame(int sig, struct k_sigaction *ka,
-                     compat_sigset_t *set, struct pt_regs *regs);
-#else
-# define user_i387_ia32_struct  user_i387_struct
-# define user32_fxsr_struct     user_fxsr_struct
-# define ia32_setup_frame       __setup_frame
-# define ia32_setup_rt_frame    __setup_rt_frame
-#endif
-
-extern unsigned int mxcsr_feature_mask;
-extern void fpu_init(void);
-extern void eager_fpu_init(void);
-
-DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
-
-extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
-                              struct task_struct *tsk);
-extern void convert_to_fxsr(struct task_struct *tsk,
-                            const struct user_i387_ia32_struct *env);
-
-extern user_regset_active_fn fpregs_active, xfpregs_active;
-extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
-                                xstateregs_get;
-extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
-                                 xstateregs_set;
-
-/*
- * xstateregs_active == fpregs_active. Please refer to the comment
- * at the definition of fpregs_active.
- */
-#define xstateregs_active       fpregs_active
-
-#ifdef CONFIG_MATH_EMULATION
-# define HAVE_HWFP              (boot_cpu_data.hard_math)
-extern void finit_soft_fpu(struct i387_soft_struct *soft);
-#else
-# define HAVE_HWFP              1
-static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
-#endif
-
-static inline int is_ia32_compat_frame(void)
-{
-        return config_enabled(CONFIG_IA32_EMULATION) &&
-               test_thread_flag(TIF_IA32);
-}
-
-static inline int is_ia32_frame(void)
-{
-        return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
-}
-
-static inline int is_x32_frame(void)
-{
-        return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
-}
-
-#define X87_FSW_ES (1 << 7)     /* Exception Summary */
-
-static __always_inline __pure bool use_eager_fpu(void)
-{
-        return static_cpu_has(X86_FEATURE_EAGER_FPU);
-}
-
-static __always_inline __pure bool use_xsaveopt(void)
-{
-        return static_cpu_has(X86_FEATURE_XSAVEOPT);
-}
-
-static __always_inline __pure bool use_xsave(void)
-{
-        return static_cpu_has(X86_FEATURE_XSAVE);
-}
-
-static __always_inline __pure bool use_fxsr(void)
-{
-        return static_cpu_has(X86_FEATURE_FXSR);
-}
-
-static inline void fx_finit(struct i387_fxsave_struct *fx)
-{
-        memset(fx, 0, xstate_size);
-        fx->cwd = 0x37f;
-        fx->mxcsr = MXCSR_DEFAULT;
-}
-
-extern void __sanitize_i387_state(struct task_struct *);
-
-static inline void sanitize_i387_state(struct task_struct *tsk)
-{
-        if (!use_xsaveopt())
-                return;
-        __sanitize_i387_state(tsk);
-}
-
-#define user_insn(insn, output, input...)                               \
-({                                                                      \
-        int err;                                                        \
-        asm volatile(ASM_STAC "\n"                                      \
-                     "1:" #insn "\n\t"                                  \
-                     "2: " ASM_CLAC "\n"                                \
-                     ".section .fixup,\"ax\"\n"                         \
-                     "3:  movl $-1,%[err]\n"                            \
-                     "    jmp  2b\n"                                    \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : [err] "=r" (err), output                         \
-                     : "0"(0), input);                                  \
-        err;                                                            \
-})
-
-#define check_insn(insn, output, input...)                              \
-({                                                                      \
-        int err;                                                        \
-        asm volatile("1:" #insn "\n\t"                                  \
-                     "2:\n"                                             \
-                     ".section .fixup,\"ax\"\n"                         \
-                     "3:  movl $-1,%[err]\n"                            \
-                     "    jmp  2b\n"                                    \
-                     ".previous\n"                                      \
-                     _ASM_EXTABLE(1b, 3b)                               \
-                     : [err] "=r" (err), output                         \
-                     : "0"(0), input);                                  \
-        err;                                                            \
-})
-
-static inline int fsave_user(struct i387_fsave_struct __user *fx)
-{
-        return user_insn(fnsave %[fx]; fwait,  [fx] "=m" (*fx), "m" (*fx));
-}
-
-static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
-{
-        if (config_enabled(CONFIG_X86_32))
-                return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
-        else if (config_enabled(CONFIG_AS_FXSAVEQ))
-                return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
-
-        /* See comment in fpu_fxsave() below. */
-        return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
-}
-
-static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
-{
-        if (config_enabled(CONFIG_X86_32))
-                return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
-        else if (config_enabled(CONFIG_AS_FXSAVEQ))
-                return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
-
-        /* See comment in fpu_fxsave() below. */
-        return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
-                          "m" (*fx));
-}
-
-static inline int fxrstor_user(struct i387_fxsave_struct __user *fx)
-{
-        if (config_enabled(CONFIG_X86_32))
-                return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
-        else if (config_enabled(CONFIG_AS_FXSAVEQ))
-                return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
-
-        /* See comment in fpu_fxsave() below. */
-        return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
-                          "m" (*fx));
-}
-
-static inline int frstor_checking(struct i387_fsave_struct *fx)
-{
-        return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
-}
-
-static inline int frstor_user(struct i387_fsave_struct __user *fx)
-{
-        return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
-}
-
-static inline void fpu_fxsave(struct fpu *fpu)
-{
-        if (config_enabled(CONFIG_X86_32))
-                asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
-        else if (config_enabled(CONFIG_AS_FXSAVEQ))
-                asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
-        else {
-                /* Using "rex64; fxsave %0" is broken because, if the memory
-                 * operand uses any extended registers for addressing, a second
-                 * REX prefix will be generated (to the assembler, rex64
-                 * followed by semicolon is a separate instruction), and hence
-                 * the 64-bitness is lost.
-                 *
-                 * Using "fxsaveq %0" would be the ideal choice, but is only
-                 * supported starting with gas 2.16.
-                 *
-                 * Using, as a workaround, the properly prefixed form below
-                 * isn't accepted by any binutils version so far released,
-                 * complaining that the same type of prefix is used twice if
-                 * an extended register is needed for addressing (fix submitted
-                 * to mainline 2005-11-21).
-                 *
-                 *  asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
-                 *
-                 * This, however, we can work around by forcing the compiler to
-                 * select an addressing mode that doesn't require extended
-                 * registers.
-                 */
-                asm volatile( "rex64/fxsave (%[fx])"
-                             : "=m" (fpu->state->fxsave)
-                             : [fx] "R" (&fpu->state->fxsave));
-        }
-}
-
-/*
- * These must be called with preempt disabled. Returns
- * 'true' if the FPU state is still intact.
- */
-static inline int fpu_save_init(struct fpu *fpu)
-{
-        if (use_xsave()) {
-                fpu_xsave(fpu);
-
-                /*
-                 * xsave header may indicate the init state of the FP.
-                 */
-                if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
-                        return 1;
-        } else if (use_fxsr()) {
-                fpu_fxsave(fpu);
-        } else {
-                asm volatile("fnsave %[fx]; fwait"
-                             : [fx] "=m" (fpu->state->fsave));
-                return 0;
-        }
-
-        /*
-         * If exceptions are pending, we need to clear them so
-         * that we don't randomly get exceptions later.
-         *
-         * FIXME! Is this perhaps only true for the old-style
-         * irq13 case? Maybe we could leave the x87 state
-         * intact otherwise?
-         */
-        if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
-                asm volatile("fnclex");
-                return 0;
-        }
-        return 1;
-}
-
-static inline int __save_init_fpu(struct task_struct *tsk)
-{
-        return fpu_save_init(&tsk->thread.fpu);
-}
-
-static inline int fpu_restore_checking(struct fpu *fpu)
-{
-        if (use_xsave())
-                return fpu_xrstor_checking(&fpu->state->xsave);
-        else if (use_fxsr())
-                return fxrstor_checking(&fpu->state->fxsave);
-        else
-                return frstor_checking(&fpu->state->fsave);
-}
-
-static inline int restore_fpu_checking(struct task_struct *tsk)
-{
-        /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
-           is pending.  Clear the x87 state here by setting it to fixed
-           values. "m" is a random variable that should be in L1 */
-        alternative_input(
-                ASM_NOP8 ASM_NOP2,
-                "emms\n\t"              /* clear stack tags */
-                "fildl %P[addr]",       /* set F?P to defined value */
-                X86_FEATURE_FXSAVE_LEAK,
-                [addr] "m" (tsk->thread.fpu.has_fpu));
-
-        return fpu_restore_checking(&tsk->thread.fpu);
-}
-
-/*
- * Software FPU state helpers. Careful: these need to
- * be preemption protection *and* they need to be
- * properly paired with the CR0.TS changes!
- */
-static inline int __thread_has_fpu(struct task_struct *tsk)
-{
-        return tsk->thread.fpu.has_fpu;
-}
-
-/* Must be paired with an 'stts' after! */
-static inline void __thread_clear_has_fpu(struct task_struct *tsk)
-{
-        tsk->thread.fpu.has_fpu = 0;
-        this_cpu_write(fpu_owner_task, NULL);
-}
-
-/* Must be paired with a 'clts' before! */
-static inline void __thread_set_has_fpu(struct task_struct *tsk)
-{
-        tsk->thread.fpu.has_fpu = 1;
-        this_cpu_write(fpu_owner_task, tsk);
-}
-
-/*
- * Encapsulate the CR0.TS handling together with the
- * software flag.
- *
- * These generally need preemption protection to work,
- * do try to avoid using these on their own.
- */
-static inline void __thread_fpu_end(struct task_struct *tsk)
-{
-        __thread_clear_has_fpu(tsk);
-        if (!use_eager_fpu())
-                stts();
-}
-
-static inline void __thread_fpu_begin(struct task_struct *tsk)
-{
-        if (!use_eager_fpu())
-                clts();
-        __thread_set_has_fpu(tsk);
-}
-
-static inline void __drop_fpu(struct task_struct *tsk)
-{
-        if (__thread_has_fpu(tsk)) {
-                /* Ignore delayed exceptions from user space */
-                asm volatile("1: fwait\n"
-                             "2:\n"
-                             _ASM_EXTABLE(1b, 2b));
-                __thread_fpu_end(tsk);
-        }
-}
-
-static inline void drop_fpu(struct task_struct *tsk)
-{
-        /*
-         * Forget coprocessor state..
-         */
-        preempt_disable();
-        tsk->fpu_counter = 0;
-        __drop_fpu(tsk);
-        clear_used_math();
-        preempt_enable();
-}
-
-static inline void drop_init_fpu(struct task_struct *tsk)
-{
-        if (!use_eager_fpu())
-                drop_fpu(tsk);
-        else {
-                if (use_xsave())
-                        xrstor_state(init_xstate_buf, -1);
-                else
-                        fxrstor_checking(&init_xstate_buf->i387);
-        }
-}
-
-/*
- * FPU state switching for scheduling.
- *
- * This is a two-stage process:
- *
- *  - switch_fpu_prepare() saves the old state and
- *    sets the new state of the CR0.TS bit. This is
- *    done within the context of the old process.
- *
- *  - switch_fpu_finish() restores the new state as
- *    necessary.
- */
-typedef struct { int preload; } fpu_switch_t;
-
-/*
- * Must be run with preemption disabled: this clears the fpu_owner_task,
- * on this CPU.
- *
- * This will disable any lazy FPU state restore of the current FPU state,
- * but if the current thread owns the FPU, it will still be saved by.
- */
-static inline void __cpu_disable_lazy_restore(unsigned int cpu)
-{
-        per_cpu(fpu_owner_task, cpu) = NULL;
-}
-
-static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
-{
-        return new == this_cpu_read_stable(fpu_owner_task) &&
-                cpu == new->thread.fpu.last_cpu;
-}
-
-static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
-{
-        fpu_switch_t fpu;
-
-        /*
-         * If the task has used the math, pre-load the FPU on xsave processors
-         * or if the past 5 consecutive context-switches used math.
-         */
-        fpu.preload = tsk_used_math(new) && (use_eager_fpu() ||
-                                             new->fpu_counter > 5);
-        if (__thread_has_fpu(old)) {
-                if (!__save_init_fpu(old))
-                        cpu = ~0;
-                old->thread.fpu.last_cpu = cpu;
-                old->thread.fpu.has_fpu = 0;    /* But leave fpu_owner_task! */
-
-                /* Don't change CR0.TS if we just switch! */
-                if (fpu.preload) {
-                        new->fpu_counter++;
-                        __thread_set_has_fpu(new);
-                        prefetch(new->thread.fpu.state);
-                } else if (!use_eager_fpu())
-                        stts();
-        } else {
-                old->fpu_counter = 0;
-                old->thread.fpu.last_cpu = ~0;
-                if (fpu.preload) {
-                        new->fpu_counter++;
-                        if (!use_eager_fpu() && fpu_lazy_restore(new, cpu))
-                                fpu.preload = 0;
-                        else
-                                prefetch(new->thread.fpu.state);
-                        __thread_fpu_begin(new);
-                }
-        }
-        return fpu;
-}
-
-/*
- * By the time this gets called, we've already cleared CR0.TS and
- * given the process the FPU if we are going to preload the FPU
- * state - all we need to do is to conditionally restore the register
- * state itself.
- */
-static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
-{
-        if (fpu.preload) {
-                if (unlikely(restore_fpu_checking(new)))
-                        drop_init_fpu(new);
-        }
-}
-
-/*
- * Signal frame handlers...
- */
-extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
-extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);
-
-static inline int xstate_sigframe_size(void)
-{
-        return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
-}
-
-static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
-{
-        void __user *buf_fx = buf;
-        int size = xstate_sigframe_size();
-
-        if (ia32_frame && use_fxsr()) {
-                buf_fx = buf + sizeof(struct i387_fsave_struct);
-                size += sizeof(struct i387_fsave_struct);
-        }
-
-        return __restore_xstate_sig(buf, buf_fx, size);
-}
-
-/*
- * Need to be preemption-safe.
- *
- * NOTE! user_fpu_begin() must be used only immediately before restoring
- * it. This function does not do any save/restore on their own.
- */
-static inline void user_fpu_begin(void)
-{
-        preempt_disable();
-        if (!user_has_fpu())
-                __thread_fpu_begin(current);
-        preempt_enable();
-}
-
-static inline void __save_fpu(struct task_struct *tsk)
-{
-        if (use_xsave())
-                xsave_state(&tsk->thread.fpu.state->xsave, -1);
-        else
-                fpu_fxsave(&tsk->thread.fpu);
-}
-
-/*
- * These disable preemption on their own and are safe
- */
-static inline void save_init_fpu(struct task_struct *tsk)
-{
-        WARN_ON_ONCE(!__thread_has_fpu(tsk));
-
-        if (use_eager_fpu()) {
-                __save_fpu(tsk);
-                return;
-        }
-
-        preempt_disable();
-        __save_init_fpu(tsk);
-        __thread_fpu_end(tsk);
-        preempt_enable();
-}
-
-/*
- * i387 state interaction
- */
-static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
-{
-        if (cpu_has_fxsr) {
-                return tsk->thread.fpu.state->fxsave.cwd;
-        } else {
-                return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
-        }
-}
-
-static inline unsigned short get_fpu_swd(struct task_struct *tsk)
-{
-        if (cpu_has_fxsr) {
-                return tsk->thread.fpu.state->fxsave.swd;
-        } else {
-                return (unsigned short)tsk->thread.fpu.state->fsave.swd;
-        }
-}
-
-static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
-{
-        if (cpu_has_xmm) {
-                return tsk->thread.fpu.state->fxsave.mxcsr;
-        } else {
-                return MXCSR_DEFAULT;
-        }
-}
-
-static bool fpu_allocated(struct fpu *fpu)
-{
-        return fpu->state != NULL;
-}
-
-static inline int fpu_alloc(struct fpu *fpu)
-{
-        if (fpu_allocated(fpu))
-                return 0;
-        fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
-        if (!fpu->state)
-                return -ENOMEM;
-        WARN_ON((unsigned long)fpu->state & 15);
-        return 0;
-}
-
-static inline void fpu_free(struct fpu *fpu)
-{
-        if (fpu->state) {
-                kmem_cache_free(task_xstate_cachep, fpu->state);
-                fpu->state = NULL;
-        }
-}
-
-static inline void fpu_copy(struct task_struct *dst, struct task_struct *src)
-{
-        if (use_eager_fpu()) {
-                memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
-                __save_fpu(dst);
-        } else {
-                struct fpu *dfpu = &dst->thread.fpu;
-                struct fpu *sfpu = &src->thread.fpu;
-
-                unlazy_fpu(src);
-                memcpy(dfpu->state, sfpu->state, xstate_size);
-        }
-}
-
-static inline unsigned long
-alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
-                unsigned long *size)
-{
-        unsigned long frame_size = xstate_sigframe_size();
-
-        *buf_fx = sp = round_down(sp - frame_size, 64);
-        if (ia32_frame && use_fxsr()) {
-                frame_size += sizeof(struct i387_fsave_struct);
-                sp -= sizeof(struct i387_fsave_struct);
-        }
-
-        *size = frame_size;
-        return sp;
-}
-
-#endif
diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h
index 9a25b522d37..268c783ab1c 100644
--- a/arch/x86/include/asm/ftrace.h
+++ b/arch/x86/include/asm/ftrace.h
@@ -3,54 +3,37 @@
 
 #ifdef __ASSEMBLY__
 
-        /* skip is set if the stack was already partially adjusted */
-        .macro MCOUNT_SAVE_FRAME skip=0
-         /*
-          * We add enough stack to save all regs.
-          */
-        subq $(SS+8-\skip), %rsp
-        movq %rax, RAX(%rsp)
-        movq %rcx, RCX(%rsp)
-        movq %rdx, RDX(%rsp)
-        movq %rsi, RSI(%rsp)
-        movq %rdi, RDI(%rsp)
-        movq %r8, R8(%rsp)
-        movq %r9, R9(%rsp)
-         /* Move RIP to its proper location */
-        movq SS+8(%rsp), %rdx
-        movq %rdx, RIP(%rsp)
+        .macro MCOUNT_SAVE_FRAME
+        /* taken from glibc */
+        subq $0x38, %rsp
+        movq %rax, (%rsp)
+        movq %rcx, 8(%rsp)
+        movq %rdx, 16(%rsp)
+        movq %rsi, 24(%rsp)
+        movq %rdi, 32(%rsp)
+        movq %r8, 40(%rsp)
+        movq %r9, 48(%rsp)
         .endm
 
-        .macro MCOUNT_RESTORE_FRAME skip=0
-        movq R9(%rsp), %r9
-        movq R8(%rsp), %r8
-        movq RDI(%rsp), %rdi
-        movq RSI(%rsp), %rsi
-        movq RDX(%rsp), %rdx
-        movq RCX(%rsp), %rcx
-        movq RAX(%rsp), %rax
-        addq $(SS+8-\skip), %rsp
+        .macro MCOUNT_RESTORE_FRAME
+        movq 48(%rsp), %r9
+        movq 40(%rsp), %r8
+        movq 32(%rsp), %rdi
+        movq 24(%rsp), %rsi
+        movq 16(%rsp), %rdx
+        movq 8(%rsp), %rcx
+        movq (%rsp), %rax
+        addq $0x38, %rsp
         .endm
 
 #endif
 
 #ifdef CONFIG_FUNCTION_TRACER
-#ifdef CC_USING_FENTRY
-# define MCOUNT_ADDR            ((long)(__fentry__))
-#else
-# define MCOUNT_ADDR            ((long)(mcount))
-#endif
+#define MCOUNT_ADDR             ((long)(mcount))
 #define MCOUNT_INSN_SIZE        5 /* sizeof mcount call */
 
-#ifdef CONFIG_DYNAMIC_FTRACE
-#define ARCH_SUPPORTS_FTRACE_OPS 1
-#define ARCH_SUPPORTS_FTRACE_SAVE_REGS
-#endif
-
 #ifndef __ASSEMBLY__
 extern void mcount(void);
-extern atomic_t modifying_ftrace_code;
-extern void __fentry__(void);
 
 static inline unsigned long ftrace_call_adjust(unsigned long addr)
 {
@@ -67,8 +50,6 @@ struct dyn_arch_ftrace {
         /* No extra data needed for x86 */
 };
 
-int ftrace_int3_handler(struct pt_regs *regs);
-
 #endif /*  CONFIG_DYNAMIC_FTRACE */
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_FUNCTION_TRACER */
diff --git a/arch/x86/include/asm/futex.h b/arch/x86/include/asm/futex.h
index be27ba1e947..d09bb03653f 100644
--- a/arch/x86/include/asm/futex.h
+++ b/arch/x86/include/asm/futex.h
@@ -9,13 +9,11 @@
 #include <asm/asm.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
-#include <asm/smap.h>
+#include <asm/system.h>
 
 #define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg)     \
-        asm volatile("\t" ASM_STAC "\n"                         \
-                     "1:\t" insn "\n"                           \
-                     "2:\t" ASM_CLAC "\n"                       \
-                     "\t.section .fixup,\"ax\"\n"               \
+        asm volatile("1:\t" insn "\n"                           \
+                     "2:\t.section .fixup,\"ax\"\n"             \
                      "3:\tmov\t%3, %1\n"                        \
                      "\tjmp\t2b\n"                              \
                      "\t.previous\n"                            \
@@ -24,14 +22,12 @@
                      : "i" (-EFAULT), "0" (oparg), "1" (0))
 
 #define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg)     \
-        asm volatile("\t" ASM_STAC "\n"                         \
-                     "1:\tmovl  %2, %0\n"                       \
+        asm volatile("1:\tmovl  %2, %0\n"                       \
                      "\tmovl\t%0, %3\n"                         \
                      "\t" insn "\n"                             \
                      "2:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"     \
                      "\tjnz\t1b\n"                              \
-                     "3:\t" ASM_CLAC "\n"                       \
-                     "\t.section .fixup,\"ax\"\n"               \
+                     "3:\t.section .fixup,\"ax\"\n"             \
                      "4:\tmov\t%5, %1\n"                        \
                      "\tjmp\t3b\n"                              \
                      "\t.previous\n"                            \
@@ -55,6 +51,12 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
         if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
+#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
+        /* Real i386 machines can only support FUTEX_OP_SET */
+        if (op != FUTEX_OP_SET && boot_cpu_data.x86 == 3)
+                return -ENOSYS;
+#endif
+
         pagefault_disable();
 
         switch (op) {
@@ -112,13 +114,17 @@ static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 {
         int ret = 0;
 
+#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
+        /* Real i386 machines have no cmpxchg instruction */
+        if (boot_cpu_data.x86 == 3)
+                return -ENOSYS;
+#endif
+
         if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
-        asm volatile("\t" ASM_STAC "\n"
-                     "1:\t" LOCK_PREFIX "cmpxchgl %4, %2\n"
-                     "2:\t" ASM_CLAC "\n"
-                     "\t.section .fixup, \"ax\"\n"
+        asm volatile("1:\t" LOCK_PREFIX "cmpxchgl %4, %2\n"
+                     "2:\t.section .fixup, \"ax\"\n"
                      "3:\tmov     %3, %0\n"
                      "\tjmp     2b\n"
                      "\t.previous\n"
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index b3799d88ffc..91d915a6525 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -1,4 +1,53 @@
-#ifndef __LINUX_GPIO_H
-#warning Include linux/gpio.h instead of asm/gpio.h
-#include <linux/gpio.h>
-#endif
+/*
+ * Generic GPIO API implementation for x86.
+ *
+ * Derived from the generic GPIO API for powerpc:
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _ASM_X86_GPIO_H
+#define _ASM_X86_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_GPIOLIB
+
+/*
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return -EINVAL;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* _ASM_X86_GPIO_H */
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 81f04cee5f7..55e4de613f0 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -7,10 +7,10 @@
 typedef struct {
         unsigned int __softirq_pending;
         unsigned int __nmi_count;       /* arch dependent */
+        unsigned int irq0_irqs;
 #ifdef CONFIG_X86_LOCAL_APIC
         unsigned int apic_timer_irqs;   /* arch dependent */
         unsigned int irq_spurious_count;
-        unsigned int icr_read_retry_count;
 #endif
         unsigned int x86_platform_ipis; /* arch dependent */
         unsigned int apic_perf_irqs;
@@ -18,10 +18,6 @@ typedef struct {
 #ifdef CONFIG_SMP
         unsigned int irq_resched_count;
         unsigned int irq_call_count;
-        /*
-         * irq_tlb_count is double-counted in irq_call_count, so it must be
-         * subtracted from irq_call_count when displaying irq_call_count
-         */
         unsigned int irq_tlb_count;
 #endif
 #ifdef CONFIG_X86_THERMAL_VECTOR
@@ -39,15 +35,14 @@ DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
 
 #define __ARCH_IRQ_STAT
 
-#define inc_irq_stat(member)    this_cpu_inc(irq_stat.member)
+#define inc_irq_stat(member)    percpu_inc(irq_stat.member)
 
-#define local_softirq_pending() this_cpu_read(irq_stat.__softirq_pending)
+#define local_softirq_pending() percpu_read(irq_stat.__softirq_pending)
 
 #define __ARCH_SET_SOFTIRQ_PENDING
 
-#define set_softirq_pending(x)  \
-                this_cpu_write(irq_stat.__softirq_pending, (x))
-#define or_softirq_pending(x)   this_cpu_or(irq_stat.__softirq_pending, (x))
+#define set_softirq_pending(x)  percpu_write(irq_stat.__softirq_pending, (x))
+#define or_softirq_pending(x)   percpu_or(irq_stat.__softirq_pending, (x))
 
 extern void ack_bad_irq(unsigned int irq);
 
diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h
index 302a323b3f6..3bd04022fd0 100644
--- a/arch/x86/include/asm/highmem.h
+++ b/arch/x86/include/asm/highmem.h
@@ -61,7 +61,7 @@ void *kmap(struct page *page);
 void kunmap(struct page *page);
 
 void *kmap_atomic_prot(struct page *page, pgprot_t prot);
-void *kmap_atomic(struct page *page);
+void *__kmap_atomic(struct page *page);
 void __kunmap_atomic(void *kvaddr);
 void *kmap_atomic_pfn(unsigned long pfn);
 void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot);
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index 434e2106cc8..2c392d663dc 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -35,6 +35,8 @@
 #define HPET_ID_NUMBER_SHIFT    8
 #define HPET_ID_VENDOR_SHIFT    16
 
+#define HPET_ID_VENDOR_8086     0x8086
+
 #define HPET_CFG_ENABLE         0x001
 #define HPET_CFG_LEGACY         0x002
 #define HPET_LEGACY_8254        2
diff --git a/arch/x86/include/asm/hugetlb.h b/arch/x86/include/asm/hugetlb.h
index bdd35dbd060..439a9acc132 100644
--- a/arch/x86/include/asm/hugetlb.h
+++ b/arch/x86/include/asm/hugetlb.h
@@ -90,8 +90,4 @@ static inline void arch_release_hugepage(struct page *page)
 {
 }
 
-static inline void arch_clear_hugepage_flags(struct page *page)
-{
-}
-
 #endif /* _ASM_X86_HUGETLB_H */
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index ef1c4d2d41e..824ca07860d 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -1,8 +1,7 @@
 #ifndef _I386_HW_BREAKPOINT_H
 #define _I386_HW_BREAKPOINT_H
 
-#include <uapi/asm/hw_breakpoint.h>
-
+#ifdef  __KERNEL__
 #define __ARCH_HW_BREAKPOINT_H
 
 /*
@@ -72,4 +71,6 @@ extern int arch_bp_generic_fields(int x86_len, int x86_type,
 
 extern struct pmu perf_ops_bp;
 
+#endif  /* __KERNEL__ */
 #endif  /* _I386_HW_BREAKPOINT_H */
+
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index b518c750993..7a15153c675 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -49,7 +49,6 @@ extern const struct hypervisor_x86 *x86_hyper;
 extern const struct hypervisor_x86 x86_hyper_vmware;
 extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
 extern const struct hypervisor_x86 x86_hyper_xen_hvm;
-extern const struct hypervisor_x86 x86_hyper_kvm;
 
 static inline bool hypervisor_x2apic_available(void)
 {
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index ed8089d6909..c9e09ea0564 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -13,44 +13,324 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/sched.h>
+#include <linux/kernel_stat.h>
+#include <linux/regset.h>
 #include <linux/hardirq.h>
+#include <linux/slab.h>
+#include <asm/asm.h>
+#include <asm/cpufeature.h>
+#include <asm/processor.h>
+#include <asm/sigcontext.h>
+#include <asm/user.h>
+#include <asm/uaccess.h>
+#include <asm/xsave.h>
 
-struct pt_regs;
-struct user_i387_struct;
-
+extern unsigned int sig_xstate_size;
+extern void fpu_init(void);
+extern void mxcsr_feature_mask_init(void);
 extern int init_fpu(struct task_struct *child);
-extern void fpu_finit(struct fpu *fpu);
+extern asmlinkage void math_state_restore(void);
+extern void __math_state_restore(void);
 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
-extern void math_state_restore(void);
 
-extern bool irq_fpu_usable(void);
+extern user_regset_active_fn fpregs_active, xfpregs_active;
+extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
+                                xstateregs_get;
+extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
+                                 xstateregs_set;
 
 /*
- * Careful: __kernel_fpu_begin/end() must be called with preempt disabled
- * and they don't touch the preempt state on their own.
- * If you enable preemption after __kernel_fpu_begin(), preempt notifier
- * should call the __kernel_fpu_end() to prevent the kernel/user FPU
- * state from getting corrupted. KVM for example uses this model.
- *
- * All other cases use kernel_fpu_begin/end() which disable preemption
- * during kernel FPU usage.
+ * xstateregs_active == fpregs_active. Please refer to the comment
+ * at the definition of fpregs_active.
+ */
+#define xstateregs_active       fpregs_active
+
+extern struct _fpx_sw_bytes fx_sw_reserved;
+#ifdef CONFIG_IA32_EMULATION
+extern unsigned int sig_xstate_ia32_size;
+extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
+struct _fpstate_ia32;
+struct _xstate_ia32;
+extern int save_i387_xstate_ia32(void __user *buf);
+extern int restore_i387_xstate_ia32(void __user *buf);
+#endif
+
+#ifdef CONFIG_MATH_EMULATION
+extern void finit_soft_fpu(struct i387_soft_struct *soft);
+#else
+static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
+#endif
+
+#define X87_FSW_ES (1 << 7)     /* Exception Summary */
+
+static __always_inline __pure bool use_xsaveopt(void)
+{
+        return static_cpu_has(X86_FEATURE_XSAVEOPT);
+}
+
+static __always_inline __pure bool use_xsave(void)
+{
+        return static_cpu_has(X86_FEATURE_XSAVE);
+}
+
+static __always_inline __pure bool use_fxsr(void)
+{
+        return static_cpu_has(X86_FEATURE_FXSR);
+}
+
+extern void __sanitize_i387_state(struct task_struct *);
+
+static inline void sanitize_i387_state(struct task_struct *tsk)
+{
+        if (!use_xsaveopt())
+                return;
+        __sanitize_i387_state(tsk);
+}
+
+#ifdef CONFIG_X86_64
+static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
+{
+        int err;
+
+        /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxrstorq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : [fx] "m" (*fx), "0" (0));
+#else
+        asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : [fx] "R" (fx), "m" (*fx), "0" (0));
+#endif
+        return err;
+}
+
+static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
+{
+        int err;
+
+        /*
+         * Clear the bytes not touched by the fxsave and reserved
+         * for the SW usage.
+         */
+        err = __clear_user(&fx->sw_reserved,
+                           sizeof(struct _fpx_sw_bytes));
+        if (unlikely(err))
+                return -EFAULT;
+
+        /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxsaveq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err), [fx] "=m" (*fx)
+                     : "0" (0));
+#else
+        asm volatile("1:  rex64/fxsave (%[fx])\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err), "=m" (*fx)
+                     : [fx] "R" (fx), "0" (0));
+#endif
+        if (unlikely(err) &&
+            __clear_user(fx, sizeof(struct i387_fxsave_struct)))
+                err = -EFAULT;
+        /* No need to clear here because the caller clears USED_MATH */
+        return err;
+}
+
+static inline void fpu_fxsave(struct fpu *fpu)
+{
+        /* Using "rex64; fxsave %0" is broken because, if the memory operand
+           uses any extended registers for addressing, a second REX prefix
+           will be generated (to the assembler, rex64 followed by semicolon
+           is a separate instruction), and hence the 64-bitness is lost. */
+
+#ifdef CONFIG_AS_FXSAVEQ
+        /* Using "fxsaveq %0" would be the ideal choice, but is only supported
+           starting with gas 2.16. */
+        __asm__ __volatile__("fxsaveq %0"
+                             : "=m" (fpu->state->fxsave));
+#else
+        /* Using, as a workaround, the properly prefixed form below isn't
+           accepted by any binutils version so far released, complaining that
+           the same type of prefix is used twice if an extended register is
+           needed for addressing (fix submitted to mainline 2005-11-21).
+        asm volatile("rex64/fxsave %0"
+                     : "=m" (fpu->state->fxsave));
+           This, however, we can work around by forcing the compiler to select
+           an addressing mode that doesn't require extended registers. */
+        asm volatile("rex64/fxsave (%[fx])"
+                     : "=m" (fpu->state->fxsave)
+                     : [fx] "R" (&fpu->state->fxsave));
+#endif
+}
+
+#else  /* CONFIG_X86_32 */
+
+/* perform fxrstor iff the processor has extended states, otherwise frstor */
+static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
+{
+        /*
+         * The "nop" is needed to make the instructions the same
+         * length.
+         */
+        alternative_input(
+                "nop ; frstor %1",
+                "fxrstor %1",
+                X86_FEATURE_FXSR,
+                "m" (*fx));
+
+        return 0;
+}
+
+static inline void fpu_fxsave(struct fpu *fpu)
+{
+        asm volatile("fxsave %[fx]"
+                     : [fx] "=m" (fpu->state->fxsave));
+}
+
+#endif  /* CONFIG_X86_64 */
+
+/* We need a safe address that is cheap to find and that is already
+   in L1 during context switch. The best choices are unfortunately
+   different for UP and SMP */
+#ifdef CONFIG_SMP
+#define safe_address (__per_cpu_offset[0])
+#else
+#define safe_address (kstat_cpu(0).cpustat.user)
+#endif
+
+/*
+ * These must be called with preempt disabled
+ */
+static inline void fpu_save_init(struct fpu *fpu)
+{
+        if (use_xsave()) {
+                fpu_xsave(fpu);
+
+                /*
+                 * xsave header may indicate the init state of the FP.
+                 */
+                if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
+                        return;
+        } else if (use_fxsr()) {
+                fpu_fxsave(fpu);
+        } else {
+                asm volatile("fnsave %[fx]; fwait"
+                             : [fx] "=m" (fpu->state->fsave));
+                return;
+        }
+
+        if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES))
+                asm volatile("fnclex");
+
+        /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
+           is pending.  Clear the x87 state here by setting it to fixed
+           values. safe_address is a random variable that should be in L1 */
+        alternative_input(
+                ASM_NOP8 ASM_NOP2,
+                "emms\n\t"              /* clear stack tags */
+                "fildl %P[addr]",       /* set F?P to defined value */
+                X86_FEATURE_FXSAVE_LEAK,
+                [addr] "m" (safe_address));
+}
+
+static inline void __save_init_fpu(struct task_struct *tsk)
+{
+        fpu_save_init(&tsk->thread.fpu);
+        task_thread_info(tsk)->status &= ~TS_USEDFPU;
+}
+
+static inline int fpu_fxrstor_checking(struct fpu *fpu)
+{
+        return fxrstor_checking(&fpu->state->fxsave);
+}
+
+static inline int fpu_restore_checking(struct fpu *fpu)
+{
+        if (use_xsave())
+                return fpu_xrstor_checking(fpu);
+        else
+                return fpu_fxrstor_checking(fpu);
+}
+
+static inline int restore_fpu_checking(struct task_struct *tsk)
+{
+        return fpu_restore_checking(&tsk->thread.fpu);
+}
+
+/*
+ * Signal frame handlers...
  */
-extern void __kernel_fpu_begin(void);
-extern void __kernel_fpu_end(void);
+extern int save_i387_xstate(void __user *buf);
+extern int restore_i387_xstate(void __user *buf);
+
+static inline void __unlazy_fpu(struct task_struct *tsk)
+{
+        if (task_thread_info(tsk)->status & TS_USEDFPU) {
+                __save_init_fpu(tsk);
+                stts();
+        } else
+                tsk->fpu_counter = 0;
+}
+
+static inline void __clear_fpu(struct task_struct *tsk)
+{
+        if (task_thread_info(tsk)->status & TS_USEDFPU) {
+                /* Ignore delayed exceptions from user space */
+                asm volatile("1: fwait\n"
+                             "2:\n"
+                             _ASM_EXTABLE(1b, 2b));
+                task_thread_info(tsk)->status &= ~TS_USEDFPU;
+                stts();
+        }
+}
 
 static inline void kernel_fpu_begin(void)
 {
-        WARN_ON_ONCE(!irq_fpu_usable());
+        struct thread_info *me = current_thread_info();
         preempt_disable();
-        __kernel_fpu_begin();
+        if (me->status & TS_USEDFPU)
+                __save_init_fpu(me->task);
+        else
+                clts();
 }
 
 static inline void kernel_fpu_end(void)
 {
-        __kernel_fpu_end();
+        stts();
         preempt_enable();
 }
 
+static inline bool irq_fpu_usable(void)
+{
+        struct pt_regs *regs;
+
+        return !in_interrupt() || !(regs = get_irq_regs()) || \
+                user_mode(regs) || (read_cr0() & X86_CR0_TS);
+}
+
 /*
  * Some instructions like VIA's padlock instructions generate a spurious
  * DNA fault but don't modify SSE registers. And these instructions
@@ -83,21 +363,90 @@ static inline void irq_ts_restore(int TS_state)
 }
 
 /*
- * The question "does this thread have fpu access?"
- * is slightly racy, since preemption could come in
- * and revoke it immediately after the test.
- *
- * However, even in that very unlikely scenario,
- * we can just assume we have FPU access - typically
- * to save the FP state - we'll just take a #NM
- * fault and get the FPU access back.
+ * These disable preemption on their own and are safe
+ */
+static inline void save_init_fpu(struct task_struct *tsk)
+{
+        preempt_disable();
+        __save_init_fpu(tsk);
+        stts();
+        preempt_enable();
+}
+
+static inline void unlazy_fpu(struct task_struct *tsk)
+{
+        preempt_disable();
+        __unlazy_fpu(tsk);
+        preempt_enable();
+}
+
+static inline void clear_fpu(struct task_struct *tsk)
+{
+        preempt_disable();
+        __clear_fpu(tsk);
+        preempt_enable();
+}
+
+/*
+ * i387 state interaction
  */
-static inline int user_has_fpu(void)
+static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
+{
+        if (cpu_has_fxsr) {
+                return tsk->thread.fpu.state->fxsave.cwd;
+        } else {
+                return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
+        }
+}
+
+static inline unsigned short get_fpu_swd(struct task_struct *tsk)
+{
+        if (cpu_has_fxsr) {
+                return tsk->thread.fpu.state->fxsave.swd;
+        } else {
+                return (unsigned short)tsk->thread.fpu.state->fsave.swd;
+        }
+}
+
+static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
+{
+        if (cpu_has_xmm) {
+                return tsk->thread.fpu.state->fxsave.mxcsr;
+        } else {
+                return MXCSR_DEFAULT;
+        }
+}
+
+static bool fpu_allocated(struct fpu *fpu)
+{
+        return fpu->state != NULL;
+}
+
+static inline int fpu_alloc(struct fpu *fpu)
+{
+        if (fpu_allocated(fpu))
+                return 0;
+        fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
+        if (!fpu->state)
+                return -ENOMEM;
+        WARN_ON((unsigned long)fpu->state & 15);
+        return 0;
+}
+
+static inline void fpu_free(struct fpu *fpu)
+{
+        if (fpu->state) {
+                kmem_cache_free(task_xstate_cachep, fpu->state);
+                fpu->state = NULL;
+        }
+}
+
+static inline void fpu_copy(struct fpu *dst, struct fpu *src)
 {
-        return current->thread.fpu.has_fpu;
+        memcpy(dst->state, src->state, xstate_size);
 }
 
-extern void unlazy_fpu(struct task_struct *tsk);
+extern void fpu_finit(struct fpu *fpu);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/ia32.h b/arch/x86/include/asm/ia32.h
index 4c6da2e4bb1..1f7e6251728 100644
--- a/arch/x86/include/asm/ia32.h
+++ b/arch/x86/include/asm/ia32.h
@@ -29,23 +29,20 @@ struct old_sigaction32 {
         unsigned int sa_restorer;       /* Another 32 bit pointer */
 };
 
+typedef struct sigaltstack_ia32 {
+        unsigned int    ss_sp;
+        int             ss_flags;
+        unsigned int    ss_size;
+} stack_ia32_t;
+
 struct ucontext_ia32 {
         unsigned int      uc_flags;
         unsigned int      uc_link;
-        compat_stack_t    uc_stack;
+        stack_ia32_t      uc_stack;
         struct sigcontext_ia32 uc_mcontext;
         compat_sigset_t   uc_sigmask;   /* mask last for extensibility */
 };
 
-struct ucontext_x32 {
-        unsigned int      uc_flags;
-        unsigned int      uc_link;
-        compat_stack_t    uc_stack;
-        unsigned int      uc__pad0;     /* needed for alignment */
-        struct sigcontext uc_mcontext;  /* the 64-bit sigcontext type */
-        compat_sigset_t   uc_sigmask;   /* mask last for extensibility */
-};
-
 /* This matches struct stat64 in glibc2.2, hence the absolutely
  * insane amounts of padding around dev_t's.
  */
@@ -80,6 +77,58 @@ struct stat64 {
         unsigned long long      st_ino;
 } __attribute__((packed));
 
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_errno;
+        int si_code;
+
+        union {
+                int _pad[((128 / sizeof(int)) - 3)];
+
+                /* kill() */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;    /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                        int _overrun_incr;      /* amount to add to overrun */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        unsigned int _pid;      /* sender's pid */
+                        unsigned int _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        unsigned int _pid;      /* which child */
+                        unsigned int _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        unsigned int _addr;     /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} compat_siginfo_t;
+
 #define IA32_STACK_TOP IA32_PAGE_OFFSET
 
 #ifdef __KERNEL__
diff --git a/arch/x86/include/asm/ia32_unistd.h b/arch/x86/include/asm/ia32_unistd.h
index b0d5716ca1e..976f6ecd2ce 100644
--- a/arch/x86/include/asm/ia32_unistd.h
+++ b/arch/x86/include/asm/ia32_unistd.h
@@ -2,10 +2,17 @@
 #define _ASM_X86_IA32_UNISTD_H
 
 /*
- * This file contains the system call numbers of the ia32 compat ABI,
+ * This file contains the system call numbers of the ia32 port,
  * this is for the kernel only.
+ * Only add syscalls here where some part of the kernel needs to know
+ * the number. This should be otherwise in sync with asm-x86/unistd_32.h. -AK
  */
-#define __SYSCALL_ia32_NR(x) (x)
-#include <asm/unistd_32_ia32.h>
+
+#define __NR_ia32_restart_syscall 0
+#define __NR_ia32_exit            1
+#define __NR_ia32_read            3
+#define __NR_ia32_write           4
+#define __NR_ia32_sigreturn     119
+#define __NR_ia32_rt_sigreturn  173
 
 #endif /* _ASM_X86_IA32_UNISTD_H */
diff --git a/arch/x86/include/asm/idle.h b/arch/x86/include/asm/idle.h
index c5d1785373e..f1e4268ef3c 100644
--- a/arch/x86/include/asm/idle.h
+++ b/arch/x86/include/asm/idle.h
@@ -1,20 +1,12 @@
 #ifndef _ASM_X86_IDLE_H
 #define _ASM_X86_IDLE_H
 
-#define IDLE_START 1
-#define IDLE_END 2
-
-struct notifier_block;
-void idle_notifier_register(struct notifier_block *n);
-void idle_notifier_unregister(struct notifier_block *n);
-
 #ifdef CONFIG_X86_64
 void enter_idle(void);
 void exit_idle(void);
 #else /* !CONFIG_X86_64 */
 static inline void enter_idle(void) { }
 static inline void exit_idle(void) { }
-static inline void __exit_idle(void) { }
 #endif /* CONFIG_X86_64 */
 
 void amd_e400_remove_cpu(int cpu);
diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h
index 74a2e312e8a..205b063e3e3 100644
--- a/arch/x86/include/asm/inat.h
+++ b/arch/x86/include/asm/inat.h
@@ -97,12 +97,11 @@
 
 /* Attribute search APIs */
 extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode);
-extern int inat_get_last_prefix_id(insn_byte_t last_pfx);
 extern insn_attr_t inat_get_escape_attribute(insn_byte_t opcode,
-                                             int lpfx_id,
+                                             insn_byte_t last_pfx,
                                              insn_attr_t esc_attr);
 extern insn_attr_t inat_get_group_attribute(insn_byte_t modrm,
-                                            int lpfx_id,
+                                            insn_byte_t last_pfx,
                                             insn_attr_t esc_attr);
 extern insn_attr_t inat_get_avx_attribute(insn_byte_t opcode,
                                           insn_byte_t vex_m,
diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h
index adcc0ae73d0..8dbe353e41e 100644
--- a/arch/x86/include/asm/init.h
+++ b/arch/x86/include/asm/init.h
@@ -5,8 +5,6 @@
 extern void __init early_ioremap_page_table_range_init(void);
 #endif
 
-extern void __init zone_sizes_init(void);
-
 extern unsigned long __init
 kernel_physical_mapping_init(unsigned long start,
                              unsigned long end,
diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h
index 48eb30a8606..88c765e1641 100644
--- a/arch/x86/include/asm/insn.h
+++ b/arch/x86/include/asm/insn.h
@@ -96,6 +96,12 @@ struct insn {
 #define X86_VEX_P(vex)  ((vex) & 0x03)          /* VEX3 Byte2, VEX2 Byte1 */
 #define X86_VEX_M_MAX   0x1f                    /* VEX3.M Maximum value */
 
+/* The last prefix is needed for two-byte and three-byte opcodes */
+static inline insn_byte_t insn_last_prefix(struct insn *insn)
+{
+        return insn->prefixes.bytes[3];
+}
+
 extern void insn_init(struct insn *insn, const void *kaddr, int x86_64);
 extern void insn_get_prefixes(struct insn *insn);
 extern void insn_get_opcode(struct insn *insn);
@@ -131,13 +137,6 @@ static inline int insn_is_avx(struct insn *insn)
         return (insn->vex_prefix.value != 0);
 }
 
-/* Ensure this instruction is decoded completely */
-static inline int insn_complete(struct insn *insn)
-{
-        return insn->opcode.got && insn->modrm.got && insn->sib.got &&
-                insn->displacement.got && insn->immediate.got;
-}
-
 static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
 {
         if (insn->vex_prefix.nbytes == 2)       /* 2 bytes VEX */
@@ -154,18 +153,6 @@ static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
                 return X86_VEX_P(insn->vex_prefix.bytes[2]);
 }
 
-/* Get the last prefix id from last prefix or VEX prefix */
-static inline int insn_last_prefix_id(struct insn *insn)
-{
-        if (insn_is_avx(insn))
-                return insn_vex_p_bits(insn);   /* VEX_p is a SIMD prefix id */
-
-        if (insn->prefixes.bytes[3])
-                return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
-
-        return 0;
-}
-
 /* Offset of each field from kaddr */
 static inline int insn_offset_rex_prefix(struct insn *insn)
 {
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 925b605eb5c..29f66793cc5 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -1,17 +1,11 @@
 #ifndef _ASM_X86_INTEL_SCU_IPC_H_
 #define  _ASM_X86_INTEL_SCU_IPC_H_
 
-#include <linux/notifier.h>
+#define IPCMSG_VRTC     0xFA     /* Set vRTC device */
 
-#define IPCMSG_WARM_RESET       0xF0
-#define IPCMSG_COLD_RESET       0xF1
-#define IPCMSG_SOFT_RESET       0xF2
-#define IPCMSG_COLD_BOOT        0xF3
-
-#define IPCMSG_VRTC             0xFA     /* Set vRTC device */
-        /* Command id associated with message IPCMSG_VRTC */
-        #define IPC_CMD_VRTC_SETTIME      1 /* Set time */
-        #define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */
+/* Command id associated with message IPCMSG_VRTC */
+#define IPC_CMD_VRTC_SETTIME      1 /* Set time */
+#define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */
 
 /* Read single register */
 int intel_scu_ipc_ioread8(u16 addr, u8 *data);
@@ -50,24 +44,4 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data);
 /* Update FW version */
 int intel_scu_ipc_fw_update(u8 *buffer, u32 length);
 
-extern struct blocking_notifier_head intel_scu_notifier;
-
-static inline void intel_scu_notifier_add(struct notifier_block *nb)
-{
-        blocking_notifier_chain_register(&intel_scu_notifier, nb);
-}
-
-static inline void intel_scu_notifier_remove(struct notifier_block *nb)
-{
-        blocking_notifier_chain_unregister(&intel_scu_notifier, nb);
-}
-
-static inline int intel_scu_notifier_post(unsigned long v, void *p)
-{
-        return blocking_notifier_call_chain(&intel_scu_notifier, v, p);
-}
-
-#define         SCU_AVAILABLE           1
-#define         SCU_DOWN                2
-
 #endif
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 73d8c5398ea..690d1cc9a87 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -5,7 +5,7 @@
 #include <asm/mpspec.h>
 #include <asm/apicdef.h>
 #include <asm/irq_vectors.h>
-#include <asm/x86_init.h>
+
 /*
  * Intel IO-APIC support for SMP and UP systems.
  *
@@ -147,6 +147,7 @@ struct io_apic_irq_attr;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
                  struct io_apic_irq_attr *irq_attr);
 void setup_IO_APIC_irq_extra(u32 gsi);
+extern void ioapic_and_gsi_init(void);
 extern void ioapic_insert_resources(void);
 
 int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
@@ -175,29 +176,12 @@ extern void mp_save_irq(struct mpc_intsrc *m);
 
 extern void disable_ioapic_support(void);
 
-extern void __init native_io_apic_init_mappings(void);
-extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
-extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
-extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
-
-static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
-{
-        return x86_io_apic_ops.read(apic, reg);
-}
-
-static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
-{
-        x86_io_apic_ops.write(apic, reg, value);
-}
-static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
-{
-        x86_io_apic_ops.modify(apic, reg, value);
-}
 #else  /* !CONFIG_X86_IO_APIC */
 
 #define io_apic_assign_pci_irqs 0
 #define setup_ioapic_ids_from_mpc x86_init_noop
 static const int timer_through_8259 = 0;
+static inline void ioapic_and_gsi_init(void) { }
 static inline void ioapic_insert_resources(void) { }
 #define gsi_top (NR_IRQS_LEGACY)
 static inline int mp_find_ioapic(u32 gsi) { return 0; }
@@ -219,10 +203,6 @@ static inline int restore_ioapic_entries(void)
 
 static inline void mp_save_irq(struct mpc_intsrc *m) { };
 static inline void disable_ioapic_support(void) { }
-#define native_io_apic_init_mappings    NULL
-#define native_io_apic_read             NULL
-#define native_io_apic_write            NULL
-#define native_io_apic_modify           NULL
 #endif
 
 #endif /* _ASM_X86_IO_APIC_H */
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index 345c99cef15..dffc38ee625 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -5,6 +5,7 @@ extern struct dma_map_ops nommu_dma_ops;
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
 extern int iommu_pass_through;
+extern int iommu_group_mf;
 
 /* 10 seconds */
 #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000)
diff --git a/arch/x86/include/asm/iommu_table.h b/arch/x86/include/asm/iommu_table.h
index f42a04735a0..f229b13a5f3 100644
--- a/arch/x86/include/asm/iommu_table.h
+++ b/arch/x86/include/asm/iommu_table.h
@@ -48,7 +48,7 @@ struct iommu_table_entry {
 
 
 #define __IOMMU_INIT(_detect, _depend, _early_init, _late_init, _finish)\
-        static const struct iommu_table_entry                           \
+        static const struct iommu_table_entry const                     \
                 __iommu_entry_##_detect __used                          \
         __attribute__ ((unused, __section__(".iommu_table"),            \
                         aligned((sizeof(void *)))))     \
@@ -63,10 +63,10 @@ struct iommu_table_entry {
  * to stop detecting the other IOMMUs after yours has been detected.
  */
 #define IOMMU_INIT_POST(_detect)                                        \
-        __IOMMU_INIT(_detect, pci_swiotlb_detect_4gb,  NULL, NULL, 0)
+        __IOMMU_INIT(_detect, pci_swiotlb_detect_4gb,  0, 0, 0)
 
 #define IOMMU_INIT_POST_FINISH(detect)                                  \
-        __IOMMU_INIT(_detect, pci_swiotlb_detect_4gb,  NULL, NULL, 1)
+        __IOMMU_INIT(_detect, pci_swiotlb_detect_4gb,  0, 0, 1)
 
 /*
  * A more sophisticated version of IOMMU_INIT. This variant requires:
diff --git a/arch/x86/include/asm/irq_regs.h b/arch/x86/include/asm/irq_regs.h
index d82250b1deb..77843225b7e 100644
--- a/arch/x86/include/asm/irq_regs.h
+++ b/arch/x86/include/asm/irq_regs.h
@@ -15,7 +15,7 @@ DECLARE_PER_CPU(struct pt_regs *, irq_regs);
 
 static inline struct pt_regs *get_irq_regs(void)
 {
-        return this_cpu_read(irq_regs);
+        return percpu_read(irq_regs);
 }
 
 static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
@@ -23,7 +23,7 @@ static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
         struct pt_regs *old_regs;
 
         old_regs = get_irq_regs();
-        this_cpu_write(irq_regs, new_regs);
+        percpu_write(irq_regs, new_regs);
 
         return old_regs;
 }
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 5fb9bbbd2f1..47d99934580 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -1,101 +1,45 @@
-/*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Author: Joerg Roedel <joerg.roedel@amd.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This header file contains the interface of the interrupt remapping code to
- * the x86 interrupt management code.
- */
+#ifndef _ASM_X86_IRQ_REMAPPING_H
+#define _ASM_X86_IRQ_REMAPPING_H
 
-#ifndef __X86_IRQ_REMAPPING_H
-#define __X86_IRQ_REMAPPING_H
-
-#include <asm/io_apic.h>
+#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
 
 #ifdef CONFIG_IRQ_REMAP
-
-extern int irq_remapping_enabled;
-
-extern void setup_irq_remapping_ops(void);
-extern int irq_remapping_supported(void);
-extern int irq_remapping_prepare(void);
-extern int irq_remapping_enable(void);
-extern void irq_remapping_disable(void);
-extern int irq_remapping_reenable(int);
-extern int irq_remap_enable_fault_handling(void);
-extern int setup_ioapic_remapped_entry(int irq,
-                                       struct IO_APIC_route_entry *entry,
-                                       unsigned int destination,
-                                       int vector,
-                                       struct io_apic_irq_attr *attr);
-extern int set_remapped_irq_affinity(struct irq_data *data,
-                                     const struct cpumask *mask,
-                                     bool force);
-extern void free_remapped_irq(int irq);
-extern void compose_remapped_msi_msg(struct pci_dev *pdev,
-                                     unsigned int irq, unsigned int dest,
-                                     struct msi_msg *msg, u8 hpet_id);
-extern int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec);
-extern int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
-                                  int index, int sub_handle);
-extern int setup_hpet_msi_remapped(unsigned int irq, unsigned int id);
-
-#else  /* CONFIG_IRQ_REMAP */
-
-#define irq_remapping_enabled   0
-
-static inline void setup_irq_remapping_ops(void) { }
-static inline int irq_remapping_supported(void) { return 0; }
-static inline int irq_remapping_prepare(void) { return -ENODEV; }
-static inline int irq_remapping_enable(void) { return -ENODEV; }
-static inline void irq_remapping_disable(void) { }
-static inline int irq_remapping_reenable(int eim) { return -ENODEV; }
-static inline int irq_remap_enable_fault_handling(void) { return -ENODEV; }
-static inline int setup_ioapic_remapped_entry(int irq,
-                                              struct IO_APIC_route_entry *entry,
-                                              unsigned int destination,
-                                              int vector,
-                                              struct io_apic_irq_attr *attr)
-{
-        return -ENODEV;
-}
-static inline int set_remapped_irq_affinity(struct irq_data *data,
-                                            const struct cpumask *mask,
-                                            bool force)
+static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
+static inline void prepare_irte(struct irte *irte, int vector,
+                                unsigned int dest)
 {
-        return 0;
+        memset(irte, 0, sizeof(*irte));
+
+        irte->present = 1;
+        irte->dst_mode = apic->irq_dest_mode;
+        /*
+         * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
+         * actual level or edge trigger will be setup in the IO-APIC
+         * RTE. This will help simplify level triggered irq migration.
+         * For more details, see the comments (in io_apic.c) explainig IO-APIC
+         * irq migration in the presence of interrupt-remapping.
+        */
+        irte->trigger_mode = 0;
+        irte->dlvry_mode = apic->irq_delivery_mode;
+        irte->vector = vector;
+        irte->dest_id = IRTE_DEST(dest);
+        irte->redir_hint = 1;
 }
-static inline void free_remapped_irq(int irq) { }
-static inline void compose_remapped_msi_msg(struct pci_dev *pdev,
-                                            unsigned int irq, unsigned int dest,
-                                            struct msi_msg *msg, u8 hpet_id)
+static inline bool irq_remapped(struct irq_cfg *cfg)
 {
+        return cfg->irq_2_iommu.iommu != NULL;
 }
-static inline int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec)
+#else
+static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
 {
-        return -ENODEV;
 }
-static inline int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
-                                         int index, int sub_handle)
+static inline bool irq_remapped(struct irq_cfg *cfg)
 {
-        return -ENODEV;
+        return false;
 }
-static inline int setup_hpet_msi_remapped(unsigned int irq, unsigned int id)
+static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
 {
-        return -ENODEV;
 }
-#endif /* CONFIG_IRQ_REMAP */
+#endif
 
-#endif /* __X86_IRQ_REMAPPING_H */
+#endif  /* _ASM_X86_IRQ_REMAPPING_H */
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 1508e518c7e..7e50f06393a 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -119,6 +119,17 @@
  */
 #define LOCAL_TIMER_VECTOR              0xef
 
+/* up to 32 vectors used for spreading out TLB flushes: */
+#if NR_CPUS <= 32
+# define NUM_INVALIDATE_TLB_VECTORS     (NR_CPUS)
+#else
+# define NUM_INVALIDATE_TLB_VECTORS     (32)
+#endif
+
+#define INVALIDATE_TLB_VECTOR_END       (0xee)
+#define INVALIDATE_TLB_VECTOR_START     \
+        (INVALIDATE_TLB_VECTOR_END-NUM_INVALIDATE_TLB_VECTORS+1)
+
 #define NR_VECTORS                       256
 
 #define FPU_IRQ                           13
@@ -149,11 +160,19 @@ static inline int invalid_vm86_irq(int irq)
 #define IO_APIC_VECTOR_LIMIT            ( 32 * MAX_IO_APICS )
 
 #ifdef CONFIG_X86_IO_APIC
-# define CPU_VECTOR_LIMIT               (64 * NR_CPUS)
-# define NR_IRQS                                        \
+# ifdef CONFIG_SPARSE_IRQ
+#  define CPU_VECTOR_LIMIT              (64 * NR_CPUS)
+#  define NR_IRQS                                       \
         (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?      \
                 (NR_VECTORS + CPU_VECTOR_LIMIT)  :      \
                 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
+# else
+#  define CPU_VECTOR_LIMIT              (32 * NR_CPUS)
+#  define NR_IRQS                                       \
+        (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ?      \
+                (NR_VECTORS + CPU_VECTOR_LIMIT)  :      \
+                (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
+# endif
 #else /* !CONFIG_X86_IO_APIC: */
 # define NR_IRQS                        NR_IRQS_LEGACY
 #endif
diff --git a/arch/x86/include/asm/ist.h b/arch/x86/include/asm/ist.h
index c9803f1a203..7e5dff1de0e 100644
--- a/arch/x86/include/asm/ist.h
+++ b/arch/x86/include/asm/ist.h
@@ -1,3 +1,6 @@
+#ifndef _ASM_X86_IST_H
+#define _ASM_X86_IST_H
+
 /*
  * Include file for the interface to IST BIOS
  * Copyright 2002 Andy Grover <andrew.grover@intel.com>
@@ -12,12 +15,20 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  */
-#ifndef _ASM_X86_IST_H
-#define _ASM_X86_IST_H
 
-#include <uapi/asm/ist.h>
 
+#include <linux/types.h>
+
+struct ist_info {
+        __u32 signature;
+        __u32 command;
+        __u32 event;
+        __u32 perf_level;
+};
+
+#ifdef __KERNEL__
 
 extern struct ist_info ist_info;
 
+#endif  /* __KERNEL__ */
 #endif /* _ASM_X86_IST_H */
diff --git a/arch/x86/include/asm/jump_label.h b/arch/x86/include/asm/jump_label.h
index 3a16c1483b4..a32b18ce6ea 100644
--- a/arch/x86/include/asm/jump_label.h
+++ b/arch/x86/include/asm/jump_label.h
@@ -9,12 +9,12 @@
 
 #define JUMP_LABEL_NOP_SIZE 5
 
-#define STATIC_KEY_INITIAL_NOP ".byte 0xe9 \n\t .long 0\n\t"
+#define JUMP_LABEL_INITIAL_NOP ".byte 0xe9 \n\t .long 0\n\t"
 
-static __always_inline bool arch_static_branch(struct static_key *key)
+static __always_inline bool arch_static_branch(struct jump_label_key *key)
 {
         asm goto("1:"
-                STATIC_KEY_INITIAL_NOP
+                JUMP_LABEL_INITIAL_NOP
                 ".pushsection __jump_table,  \"aw\" \n\t"
                 _ASM_ALIGN "\n\t"
                 _ASM_PTR "1b, %l[l_yes], %c0 \n\t"
diff --git a/arch/x86/include/asm/kbdleds.h b/arch/x86/include/asm/kbdleds.h
deleted file mode 100644
index f27ac5ff597..00000000000
--- a/arch/x86/include/asm/kbdleds.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_X86_KBDLEDS_H
-#define _ASM_X86_KBDLEDS_H
-
-/*
- * Some laptops take the 789uiojklm,. keys as number pad when NumLock is on.
- * This seems a good reason to start with NumLock off. That's why on X86 we
- * ask the bios for the correct state.
- */
-
-#include <asm/setup.h>
-
-static inline int kbd_defleds(void)
-{
-        return boot_params.kbd_status & 0x20 ? (1 << VC_NUMLOCK) : 0;
-}
-
-#endif /* _ASM_X86_KBDLEDS_H */
diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h
index 2c37aadcbc3..d73f1571bde 100644
--- a/arch/x86/include/asm/kdebug.h
+++ b/arch/x86/include/asm/kdebug.h
@@ -24,6 +24,7 @@ enum die_val {
 extern void printk_address(unsigned long address, int reliable);
 extern void die(const char *, struct pt_regs *,long);
 extern int __must_check __die(const char *, struct pt_regs *, long);
+extern void show_registers(struct pt_regs *regs);
 extern void show_trace(struct task_struct *t, struct pt_regs *regs,
                        unsigned long *sp, unsigned long bp);
 extern void __show_regs(struct pt_regs *regs, int all);
diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h
index 6080d2694ba..317ff1703d0 100644
--- a/arch/x86/include/asm/kexec.h
+++ b/arch/x86/include/asm/kexec.h
@@ -163,9 +163,6 @@ struct kimage_arch {
 };
 #endif
 
-typedef void crash_vmclear_fn(void);
-extern crash_vmclear_fn __rcu *crash_vmclear_loaded_vmcss;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_X86_KEXEC_H */
diff --git a/arch/x86/include/asm/kgdb.h b/arch/x86/include/asm/kgdb.h
index 332f98c9111..77e95f54570 100644
--- a/arch/x86/include/asm/kgdb.h
+++ b/arch/x86/include/asm/kgdb.h
@@ -64,15 +64,11 @@ enum regnames {
         GDB_PS,                 /* 17 */
         GDB_CS,                 /* 18 */
         GDB_SS,                 /* 19 */
-        GDB_DS,                 /* 20 */
-        GDB_ES,                 /* 21 */
-        GDB_FS,                 /* 22 */
-        GDB_GS,                 /* 23 */
 };
 #define GDB_ORIG_AX             57
-#define DBG_MAX_REG_NUM         24
-/* 17 64 bit regs and 5 32 bit regs */
-#define NUMREGBYTES             ((17 * 8) + (5 * 4))
+#define DBG_MAX_REG_NUM         20
+/* 17 64 bit regs and 3 32 bit regs */
+#define NUMREGBYTES             ((17 * 8) + (3 * 4))
 #endif /* ! CONFIG_X86_32 */
 
 static inline void arch_kgdb_breakpoint(void)
diff --git a/arch/x86/include/asm/kprobes.h b/arch/x86/include/asm/kprobes.h
index d3ddd17405d..54788253915 100644
--- a/arch/x86/include/asm/kprobes.h
+++ b/arch/x86/include/asm/kprobes.h
@@ -27,7 +27,6 @@
 #include <asm/insn.h>
 
 #define  __ARCH_WANT_KPROBES_INSN_SLOT
-#define  ARCH_SUPPORTS_KPROBES_ON_FTRACE
 
 struct pt_regs;
 struct kprobe;
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 15f960c06ff..6040d115ef5 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -86,19 +86,6 @@ struct x86_instruction_info {
 
 struct x86_emulate_ops {
         /*
-         * read_gpr: read a general purpose register (rax - r15)
-         *
-         * @reg: gpr number.
-         */
-        ulong (*read_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg);
-        /*
-         * write_gpr: write a general purpose register (rax - r15)
-         *
-         * @reg: gpr number.
-         * @val: value to write.
-         */
-        void (*write_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val);
-        /*
          * read_std: Read bytes of standard (non-emulated/special) memory.
          *           Used for descriptor reading.
          *  @addr:  [IN ] Linear address from which to read.
@@ -189,13 +176,11 @@ struct x86_emulate_ops {
         void (*set_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
         ulong (*get_cr)(struct x86_emulate_ctxt *ctxt, int cr);
         int (*set_cr)(struct x86_emulate_ctxt *ctxt, int cr, ulong val);
-        void (*set_rflags)(struct x86_emulate_ctxt *ctxt, ulong val);
         int (*cpl)(struct x86_emulate_ctxt *ctxt);
         int (*get_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong *dest);
         int (*set_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong value);
         int (*set_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 data);
         int (*get_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 *pdata);
-        int (*read_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc, u64 *pdata);
         void (*halt)(struct x86_emulate_ctxt *ctxt);
         void (*wbinvd)(struct x86_emulate_ctxt *ctxt);
         int (*fix_hypercall)(struct x86_emulate_ctxt *ctxt);
@@ -204,18 +189,14 @@ struct x86_emulate_ops {
         int (*intercept)(struct x86_emulate_ctxt *ctxt,
                          struct x86_instruction_info *info,
                          enum x86_intercept_stage stage);
-
-        void (*get_cpuid)(struct x86_emulate_ctxt *ctxt,
-                          u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
 };
 
 typedef u32 __attribute__((vector_size(16))) sse128_t;
 
 /* Type, address-of, and value of an instruction's operand. */
 struct operand {
-        enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type;
+        enum { OP_REG, OP_MEM, OP_IMM, OP_XMM, OP_NONE } type;
         unsigned int bytes;
-        unsigned int count;
         union {
                 unsigned long orig_val;
                 u64 orig_val64;
@@ -227,15 +208,12 @@ struct operand {
                         unsigned seg;
                 } mem;
                 unsigned xmm;
-                unsigned mm;
         } addr;
         union {
                 unsigned long val;
                 u64 val64;
                 char valptr[sizeof(unsigned long) + 2];
                 sse128_t vec_val;
-                u64 mm_val;
-                void *data;
         };
 };
 
@@ -251,23 +229,14 @@ struct read_cache {
         unsigned long end;
 };
 
-/* Execution mode, passed to the emulator. */
-enum x86emul_mode {
-        X86EMUL_MODE_REAL,      /* Real mode.             */
-        X86EMUL_MODE_VM86,      /* Virtual 8086 mode.     */
-        X86EMUL_MODE_PROT16,    /* 16-bit protected mode. */
-        X86EMUL_MODE_PROT32,    /* 32-bit protected mode. */
-        X86EMUL_MODE_PROT64,    /* 64-bit (long) mode.    */
-};
-
 struct x86_emulate_ctxt {
-        const struct x86_emulate_ops *ops;
+        struct x86_emulate_ops *ops;
 
         /* Register state before/after emulation. */
         unsigned long eflags;
         unsigned long eip; /* eip before instruction emulation */
         /* Emulated execution mode, represented by an X86EMUL_MODE value. */
-        enum x86emul_mode mode;
+        int mode;
 
         /* interruptibility state, as a result of execution of STI or MOV SS */
         int interruptibility;
@@ -293,7 +262,7 @@ struct x86_emulate_ctxt {
         struct operand dst;
         bool has_seg_override;
         u8 seg_override;
-        u64 d;
+        unsigned int d;
         int (*execute)(struct x86_emulate_ctxt *ctxt);
         int (*check_perm)(struct x86_emulate_ctxt *ctxt);
         /* modrm */
@@ -304,12 +273,8 @@ struct x86_emulate_ctxt {
         u8 modrm_seg;
         bool rip_relative;
         unsigned long _eip;
-        struct operand memop;
-        u32 regs_valid;  /* bitmaps of registers in _regs[] that can be read */
-        u32 regs_dirty;  /* bitmaps of registers in _regs[] that have been written */
         /* Fields above regs are cleared together. */
-        unsigned long _regs[NR_VCPU_REGS];
-        struct operand *memopp;
+        unsigned long regs[NR_VCPU_REGS];
         struct fetch_cache fetch;
         struct read_cache io_read;
         struct read_cache mem_read;
@@ -319,18 +284,16 @@ struct x86_emulate_ctxt {
 #define REPE_PREFIX     0xf3
 #define REPNE_PREFIX    0xf2
 
-/* CPUID vendors */
-#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx 0x68747541
-#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163
-#define X86EMUL_CPUID_VENDOR_AuthenticAMD_edx 0x69746e65
-
-#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx 0x69444d41
-#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574
-#define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273
+/* Execution mode, passed to the emulator. */
+#define X86EMUL_MODE_REAL     0 /* Real mode.             */
+#define X86EMUL_MODE_VM86     1 /* Virtual 8086 mode.     */
+#define X86EMUL_MODE_PROT16   2 /* 16-bit protected mode. */
+#define X86EMUL_MODE_PROT32   4 /* 32-bit protected mode. */
+#define X86EMUL_MODE_PROT64   8 /* 64-bit (long) mode.    */
 
-#define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547
-#define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e
-#define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69
+/* any protected mode   */
+#define X86EMUL_MODE_PROT     (X86EMUL_MODE_PROT16|X86EMUL_MODE_PROT32| \
+                               X86EMUL_MODE_PROT64)
 
 enum x86_intercept_stage {
         X86_ICTP_NONE = 0,   /* Allow zero-init to not match anything */
@@ -399,17 +362,13 @@ enum x86_intercept {
 #endif
 
 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len);
-bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
 #define EMULATION_FAILED -1
 #define EMULATION_OK 0
 #define EMULATION_RESTART 1
 #define EMULATION_INTERCEPTED 2
 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);
 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
-                         u16 tss_selector, int idt_index, int reason,
+                         u16 tss_selector, int reason,
                          bool has_error_code, u32 error_code);
 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq);
-void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt);
-void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt);
-
 #endif /* _ASM_X86_KVM_X86_EMULATE_H */
diff --git a/arch/x86/include/asm/kvm_guest.h b/arch/x86/include/asm/kvm_guest.h
deleted file mode 100644
index a92b1763c41..00000000000
--- a/arch/x86/include/asm/kvm_guest.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_X86_KVM_GUEST_H
-#define _ASM_X86_KVM_GUEST_H
-
-int kvm_setup_vsyscall_timeinfo(void);
-
-#endif /* _ASM_X86_KVM_GUEST_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index dc87b65e9c3..dd51c83aa5d 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -16,28 +16,20 @@
 #include <linux/mmu_notifier.h>
 #include <linux/tracepoint.h>
 #include <linux/cpumask.h>
-#include <linux/irq_work.h>
 
 #include <linux/kvm.h>
 #include <linux/kvm_para.h>
 #include <linux/kvm_types.h>
-#include <linux/perf_event.h>
-#include <linux/pvclock_gtod.h>
-#include <linux/clocksource.h>
 
 #include <asm/pvclock-abi.h>
 #include <asm/desc.h>
 #include <asm/mtrr.h>
 #include <asm/msr-index.h>
-#include <asm/asm.h>
 
-#define KVM_MAX_VCPUS 254
-#define KVM_SOFT_MAX_VCPUS 160
+#define KVM_MAX_VCPUS 64
 #define KVM_MEMORY_SLOTS 32
 /* memory slots that does not exposed to userspace */
 #define KVM_PRIVATE_MEM_SLOTS 4
-#define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS)
-
 #define KVM_MMIO_SIZE 16
 
 #define KVM_PIO_PAGE_OFFSET 1
@@ -50,13 +42,12 @@
 
 #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
 #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
-#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL
 #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |    \
                                   0xFFFFFF0000000000ULL)
 #define CR4_RESERVED_BITS                                               \
         (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
                           | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
-                          | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
+                          | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \
                           | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
                           | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 
@@ -77,6 +68,22 @@
 #define KVM_HPAGE_MASK(x)       (~(KVM_HPAGE_SIZE(x) - 1))
 #define KVM_PAGES_PER_HPAGE(x)  (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
 
+#define DE_VECTOR 0
+#define DB_VECTOR 1
+#define BP_VECTOR 3
+#define OF_VECTOR 4
+#define BR_VECTOR 5
+#define UD_VECTOR 6
+#define NM_VECTOR 7
+#define DF_VECTOR 8
+#define TS_VECTOR 10
+#define NP_VECTOR 11
+#define SS_VECTOR 12
+#define GP_VECTOR 13
+#define PF_VECTOR 14
+#define MF_VECTOR 16
+#define MC_VECTOR 18
+
 #define SELECTOR_TI_MASK (1 << 2)
 #define SELECTOR_RPL_MASK 0x03
 
@@ -160,16 +167,6 @@ enum {
 #define DR7_FIXED_1     0x00000400
 #define DR7_VOLATILE    0xffff23ff
 
-/* apic attention bits */
-#define KVM_APIC_CHECK_VAPIC    0
-/*
- * The following bit is set with PV-EOI, unset on EOI.
- * We detect PV-EOI changes by guest by comparing
- * this bit with PV-EOI in guest memory.
- * See the implementation in apic_update_pv_eoi.
- */
-#define KVM_APIC_PV_EOI_PENDING 1
-
 /*
  * We don't want allocation failures within the mmu code, so we preallocate
  * enough memory for a single page fault in a cache.
@@ -179,6 +176,13 @@ struct kvm_mmu_memory_cache {
         void *objects[KVM_NR_MEM_OBJS];
 };
 
+#define NR_PTE_CHAIN_ENTRIES 5
+
+struct kvm_pte_chain {
+        u64 *parent_ptes[NR_PTE_CHAIN_ENTRIES];
+        struct hlist_node link;
+};
+
 /*
  * kvm_mmu_page_role, below, is defined as:
  *
@@ -223,7 +227,7 @@ struct kvm_mmu_page {
          * One bit set per slot which has memory
          * in this shadow page.
          */
-        DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM);
+        DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
         bool unsync;
         int root_count;          /* Currently serving as active root */
         unsigned int unsync_children;
@@ -234,7 +238,14 @@ struct kvm_mmu_page {
         int clear_spte_count;
 #endif
 
-        int write_flooding_count;
+        struct rcu_head rcu;
+};
+
+struct kvm_pv_mmu_op_buffer {
+        void *ptr;
+        unsigned len;
+        unsigned processed;
+        char buf[512] __aligned(sizeof(long));
 };
 
 struct kvm_pio_request {
@@ -253,7 +264,6 @@ struct kvm_mmu {
         void (*new_cr3)(struct kvm_vcpu *vcpu);
         void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
         unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
-        u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
         int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
                           bool prefault);
         void (*inject_page_fault)(struct kvm_vcpu *vcpu,
@@ -273,60 +283,15 @@ struct kvm_mmu {
         union kvm_mmu_page_role base_role;
         bool direct_map;
 
-        /*
-         * Bitmap; bit set = permission fault
-         * Byte index: page fault error code [4:1]
-         * Bit index: pte permissions in ACC_* format
-         */
-        u8 permissions[16];
-
         u64 *pae_root;
         u64 *lm_root;
         u64 rsvd_bits_mask[2][4];
 
-        /*
-         * Bitmap: bit set = last pte in walk
-         * index[0:1]: level (zero-based)
-         * index[2]: pte.ps
-         */
-        u8 last_pte_bitmap;
-
         bool nx;
 
         u64 pdptrs[4]; /* pae */
 };
 
-enum pmc_type {
-        KVM_PMC_GP = 0,
-        KVM_PMC_FIXED,
-};
-
-struct kvm_pmc {
-        enum pmc_type type;
-        u8 idx;
-        u64 counter;
-        u64 eventsel;
-        struct perf_event *perf_event;
-        struct kvm_vcpu *vcpu;
-};
-
-struct kvm_pmu {
-        unsigned nr_arch_gp_counters;
-        unsigned nr_arch_fixed_counters;
-        unsigned available_event_types;
-        u64 fixed_ctr_ctrl;
-        u64 global_ctrl;
-        u64 global_status;
-        u64 global_ovf_ctrl;
-        u64 counter_bitmask[2];
-        u64 global_ctrl_mask;
-        u8 version;
-        struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
-        struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
-        struct irq_work irq_work;
-        u64 reprogram_pmi;
-};
-
 struct kvm_vcpu_arch {
         /*
          * rip and regs accesses must go through
@@ -347,7 +312,6 @@ struct kvm_vcpu_arch {
         u64 efer;
         u64 apic_base;
         struct kvm_lapic *apic;    /* kernel irqchip context */
-        unsigned long apic_attention;
         int32_t apic_arb_prio;
         int mp_state;
         int sipi_vector;
@@ -379,10 +343,19 @@ struct kvm_vcpu_arch {
          */
         struct kvm_mmu *walk_mmu;
 
+        /* only needed in kvm_pv_mmu_op() path, but it's hot so
+         * put it here to avoid allocation */
+        struct kvm_pv_mmu_op_buffer mmu_op_buffer;
+
         struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
         struct kvm_mmu_memory_cache mmu_page_cache;
         struct kvm_mmu_memory_cache mmu_page_header_cache;
 
+        gfn_t last_pt_write_gfn;
+        int   last_pt_write_count;
+        u64  *last_pte_updated;
+        gfn_t last_pte_gfn;
+
         struct fpu guest_fpu;
         u64 xcr0;
 
@@ -414,15 +387,12 @@ struct kvm_vcpu_arch {
         struct x86_emulate_ctxt emulate_ctxt;
         bool emulate_regs_need_sync_to_vcpu;
         bool emulate_regs_need_sync_from_vcpu;
-        int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
 
         gpa_t time;
         struct pvclock_vcpu_time_info hv_clock;
         unsigned int hw_tsc_khz;
         unsigned int time_offset;
         struct page *time_page;
-        /* set guest stopped flag in pvclock flags field */
-        bool pvclock_set_guest_stopped_request;
 
         struct {
                 u64 msr_val;
@@ -434,21 +404,15 @@ struct kvm_vcpu_arch {
 
         u64 last_guest_tsc;
         u64 last_kernel_ns;
-        u64 last_host_tsc;
-        u64 tsc_offset_adjustment;
-        u64 this_tsc_nsec;
-        u64 this_tsc_write;
-        u8  this_tsc_generation;
-        bool tsc_catchup;
-        bool tsc_always_catchup;
-        s8 virtual_tsc_shift;
-        u32 virtual_tsc_mult;
+        u64 last_tsc_nsec;
+        u64 last_tsc_write;
         u32 virtual_tsc_khz;
-        s64 ia32_tsc_adjust_msr;
+        bool tsc_catchup;
+        u32  tsc_catchup_mult;
+        s8   tsc_catchup_shift;
 
-        atomic_t nmi_queued;  /* unprocessed asynchronous NMIs */
-        unsigned nmi_pending; /* NMI queued after currently running handler */
-        bool nmi_injected;    /* Trying to inject an NMI this entry */
+        bool nmi_pending;
+        bool nmi_injected;
 
         struct mtrr_state_type mtrr_state;
         u32 pat;
@@ -458,7 +422,6 @@ struct kvm_vcpu_arch {
         unsigned long dr6;
         unsigned long dr7;
         unsigned long eff_db[KVM_NR_DB_REGS];
-        unsigned long guest_debug_dr7;
 
         u64 mcg_cap;
         u64 mcg_status;
@@ -470,8 +433,6 @@ struct kvm_vcpu_arch {
         unsigned access;
         gfn_t mmio_gfn;
 
-        struct kvm_pmu pmu;
-
         /* used for guest single stepping over the given code position */
         unsigned long singlestep_rip;
 
@@ -480,9 +441,6 @@ struct kvm_vcpu_arch {
 
         cpumask_var_t wbinvd_dirty_mask;
 
-        unsigned long last_retry_eip;
-        unsigned long last_retry_addr;
-
         struct {
                 bool halted;
                 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
@@ -491,36 +449,6 @@ struct kvm_vcpu_arch {
                 u32 id;
                 bool send_user_only;
         } apf;
-
-        /* OSVW MSRs (AMD only) */
-        struct {
-                u64 length;
-                u64 status;
-        } osvw;
-
-        struct {
-                u64 msr_val;
-                struct gfn_to_hva_cache data;
-        } pv_eoi;
-};
-
-struct kvm_lpage_info {
-        int write_count;
-};
-
-struct kvm_arch_memory_slot {
-        unsigned long *rmap[KVM_NR_PAGE_SIZES];
-        struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
-};
-
-struct kvm_apic_map {
-        struct rcu_head rcu;
-        u8 ldr_bits;
-        /* fields bellow are used to decode ldr values in different modes */
-        u32 cid_shift, cid_mask, lid_mask;
-        struct kvm_lapic *phys_map[256];
-        /* first index is cluster id second is cpu id in a cluster */
-        struct kvm_lapic *logical_map[16][16];
 };
 
 struct kvm_arch {
@@ -528,6 +456,7 @@ struct kvm_arch {
         unsigned int n_requested_mmu_pages;
         unsigned int n_max_mmu_pages;
         unsigned int indirect_shadow_pages;
+        atomic_t invlpg_counter;
         struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
         /*
          * Hash table of struct kvm_mmu_page.
@@ -540,8 +469,6 @@ struct kvm_arch {
         struct kvm_ioapic *vioapic;
         struct kvm_pit *vpit;
         int vapics_in_nmi_mode;
-        struct mutex apic_map_lock;
-        struct kvm_apic_map *apic_map;
 
         unsigned int tss_addr;
         struct page *apic_access_page;
@@ -556,18 +483,8 @@ struct kvm_arch {
         s64 kvmclock_offset;
         raw_spinlock_t tsc_write_lock;
         u64 last_tsc_nsec;
+        u64 last_tsc_offset;
         u64 last_tsc_write;
-        u32 last_tsc_khz;
-        u64 cur_tsc_nsec;
-        u64 cur_tsc_write;
-        u64 cur_tsc_offset;
-        u8  cur_tsc_generation;
-        int nr_vcpus_matched_tsc;
-
-        spinlock_t pvclock_gtod_sync_lock;
-        bool use_master_clock;
-        u64 master_kernel_ns;
-        cycle_t master_cycle_now;
 
         struct kvm_xen_hvm_config xen_hvm_config;
 
@@ -575,6 +492,8 @@ struct kvm_arch {
         u64 hv_guest_os_id;
         u64 hv_hypercall;
 
+        atomic_t reader_counter;
+
         #ifdef CONFIG_KVM_MMU_AUDIT
         int audit_point;
         #endif
@@ -621,12 +540,6 @@ struct kvm_vcpu_stat {
 
 struct x86_instruction_info;
 
-struct msr_data {
-        bool host_initiated;
-        u32 index;
-        u64 data;
-};
-
 struct kvm_x86_ops {
         int (*cpu_has_kvm_support)(void);          /* __init */
         int (*disabled_by_bios)(void);             /* __init */
@@ -647,9 +560,10 @@ struct kvm_x86_ops {
         void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
         void (*vcpu_put)(struct kvm_vcpu *vcpu);
 
-        void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu);
+        void (*set_guest_debug)(struct kvm_vcpu *vcpu,
+                                struct kvm_guest_debug *dbg);
         int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
-        int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
+        int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
         u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
         void (*get_segment)(struct kvm_vcpu *vcpu,
                             struct kvm_segment *var, int seg);
@@ -702,8 +616,7 @@ struct kvm_x86_ops {
         u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
         int (*get_lpage_level)(void);
         bool (*rdtscp_supported)(void);
-        bool (*invpcid_supported)(void);
-        void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);
+        void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment);
 
         void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
 
@@ -711,18 +624,18 @@ struct kvm_x86_ops {
 
         bool (*has_wbinvd_exit)(void);
 
-        void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale);
-        u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu);
+        void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz);
         void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
 
         u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc);
-        u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc);
 
         void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2);
 
         int (*check_intercept)(struct kvm_vcpu *vcpu,
                                struct x86_instruction_info *info,
                                enum x86_intercept_stage stage);
+
+        const struct trace_print_flags *exit_reasons_str;
 };
 
 struct kvm_arch_async_pf {
@@ -734,17 +647,6 @@ struct kvm_arch_async_pf {
 
 extern struct kvm_x86_ops *kvm_x86_ops;
 
-static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
-                                           s64 adjustment)
-{
-        kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false);
-}
-
-static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
-{
-        kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true);
-}
-
 int kvm_mmu_module_init(void);
 void kvm_mmu_module_exit(void);
 
@@ -756,9 +658,6 @@ void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
 
 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot);
-void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
-                                     struct kvm_memory_slot *slot,
-                                     gfn_t gfn_offset, unsigned long mask);
 void kvm_mmu_zap_all(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
@@ -767,12 +666,12 @@ int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
 
 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
                           const void *val, int bytes);
+int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
+                  gpa_t addr, unsigned long *ret);
 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
 
 extern bool tdp_enabled;
 
-u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
-
 /* control of guest tsc rate supported? */
 extern bool kvm_has_tsc_control;
 /* minimum supported tsc_khz for guests */
@@ -789,7 +688,6 @@ enum emulation_result {
 #define EMULTYPE_NO_DECODE          (1 << 0)
 #define EMULTYPE_TRAP_UD            (1 << 1)
 #define EMULTYPE_SKIP               (1 << 2)
-#define EMULTYPE_RETRY              (1 << 3)
 int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
                             int emulation_type, void *insn, int insn_len);
 
@@ -801,7 +699,7 @@ static inline int emulate_instruction(struct kvm_vcpu *vcpu,
 
 void kvm_enable_efer_bits(u64);
 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
-int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
+int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
 
 struct x86_emulate_ctxt;
 
@@ -813,8 +711,8 @@ int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
 
-int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
-                    int reason, bool has_error_code, u32 error_code);
+int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
+                    bool has_error_code, u32 error_code);
 
 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
@@ -828,11 +726,10 @@ void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
 
 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
-int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
+int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 
 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
-bool kvm_rdpmc(struct kvm_vcpu *vcpu);
 
 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
@@ -845,20 +742,7 @@ int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
 
-static inline int __kvm_irq_line_state(unsigned long *irq_state,
-                                       int irq_source_id, int level)
-{
-        /* Logical OR for level trig interrupt */
-        if (level)
-                __set_bit(irq_source_id, irq_state);
-        else
-                __clear_bit(irq_source_id, irq_state);
-
-        return !!(*irq_state);
-}
-
-int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
-void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
+int kvm_pic_set_irq(void *opaque, int irq, int level);
 
 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
 
@@ -866,14 +750,13 @@ int fx_init(struct kvm_vcpu *vcpu);
 
 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-                       const u8 *new, int bytes);
-int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
+                       const u8 *new, int bytes,
+                       bool guest_initiated);
 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
 int kvm_mmu_load(struct kvm_vcpu *vcpu);
 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
-gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
                               struct x86_exception *exception);
 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
@@ -895,11 +778,6 @@ void kvm_disable_tdp(void);
 int complete_pio(struct kvm_vcpu *vcpu);
 bool kvm_check_iopl(struct kvm_vcpu *vcpu);
 
-static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
-{
-        return gpa;
-}
-
 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
 {
         struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
@@ -979,14 +857,15 @@ extern bool kvm_rebooting;
         __ASM_SIZE(push) " $666b \n\t"        \
         "call kvm_spurious_fault \n\t"        \
         ".popsection \n\t" \
-        _ASM_EXTABLE(666b, 667b)
+        ".pushsection __ex_table, \"a\" \n\t" \
+        _ASM_PTR " 666b, 667b \n\t" \
+        ".popsection"
 
 #define __kvm_handle_fault_on_reboot(insn)              \
         ____kvm_handle_fault_on_reboot(insn, "")
 
 #define KVM_ARCH_WANT_MMU_NOTIFIER
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
-int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end);
 int kvm_age_hva(struct kvm *kvm, unsigned long hva);
 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
@@ -1011,17 +890,4 @@ extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
 
 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
 
-int kvm_is_in_guest(void);
-
-void kvm_pmu_init(struct kvm_vcpu *vcpu);
-void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
-void kvm_pmu_reset(struct kvm_vcpu *vcpu);
-void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu);
-bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr);
-int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
-int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
-int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
-void kvm_handle_pmu_event(struct kvm_vcpu *vcpu);
-void kvm_deliver_pmi(struct kvm_vcpu *vcpu);
-
 #endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index 5ed1f16187b..734c3767cfa 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -1,27 +1,107 @@
 #ifndef _ASM_X86_KVM_PARA_H
 #define _ASM_X86_KVM_PARA_H
 
+#include <linux/types.h>
+#include <asm/hyperv.h>
+
+/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
+ * should be used to determine that a VM is running under KVM.
+ */
+#define KVM_CPUID_SIGNATURE     0x40000000
+
+/* This CPUID returns a feature bitmap in eax.  Before enabling a particular
+ * paravirtualization, the appropriate feature bit should be checked.
+ */
+#define KVM_CPUID_FEATURES      0x40000001
+#define KVM_FEATURE_CLOCKSOURCE         0
+#define KVM_FEATURE_NOP_IO_DELAY        1
+#define KVM_FEATURE_MMU_OP              2
+/* This indicates that the new set of kvmclock msrs
+ * are available. The use of 0x11 and 0x12 is deprecated
+ */
+#define KVM_FEATURE_CLOCKSOURCE2        3
+#define KVM_FEATURE_ASYNC_PF            4
+#define KVM_FEATURE_STEAL_TIME          5
+
+/* The last 8 bits are used to indicate how to interpret the flags field
+ * in pvclock structure. If no bits are set, all flags are ignored.
+ */
+#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT      24
+
+#define MSR_KVM_WALL_CLOCK  0x11
+#define MSR_KVM_SYSTEM_TIME 0x12
+
+#define KVM_MSR_ENABLED 1
+/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
+#define MSR_KVM_WALL_CLOCK_NEW  0x4b564d00
+#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
+#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
+#define MSR_KVM_STEAL_TIME  0x4b564d03
+
+struct kvm_steal_time {
+        __u64 steal;
+        __u32 version;
+        __u32 flags;
+        __u32 pad[12];
+};
+
+#define KVM_STEAL_ALIGNMENT_BITS 5
+#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
+#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
+
+#define KVM_MAX_MMU_OP_BATCH           32
+
+#define KVM_ASYNC_PF_ENABLED                    (1 << 0)
+#define KVM_ASYNC_PF_SEND_ALWAYS                (1 << 1)
+
+/* Operations for KVM_HC_MMU_OP */
+#define KVM_MMU_OP_WRITE_PTE            1
+#define KVM_MMU_OP_FLUSH_TLB            2
+#define KVM_MMU_OP_RELEASE_PT           3
+
+/* Payload for KVM_HC_MMU_OP */
+struct kvm_mmu_op_header {
+        __u32 op;
+        __u32 pad;
+};
+
+struct kvm_mmu_op_write_pte {
+        struct kvm_mmu_op_header header;
+        __u64 pte_phys;
+        __u64 pte_val;
+};
+
+struct kvm_mmu_op_flush_tlb {
+        struct kvm_mmu_op_header header;
+};
+
+struct kvm_mmu_op_release_pt {
+        struct kvm_mmu_op_header header;
+        __u64 pt_phys;
+};
+
+#define KVM_PV_REASON_PAGE_NOT_PRESENT 1
+#define KVM_PV_REASON_PAGE_READY 2
+
+struct kvm_vcpu_pv_apf_data {
+        __u32 reason;
+        __u8 pad[60];
+        __u32 enabled;
+};
+
+#ifdef __KERNEL__
 #include <asm/processor.h>
-#include <uapi/asm/kvm_para.h>
 
 extern void kvmclock_init(void);
 extern int kvm_register_clock(char *txt);
 
-#ifdef CONFIG_KVM_GUEST
-bool kvm_check_and_clear_guest_paused(void);
-#else
-static inline bool kvm_check_and_clear_guest_paused(void)
-{
-        return false;
-}
-#endif /* CONFIG_KVM_GUEST */
 
 /* This instruction is vmcall.  On non-VT architectures, it will generate a
  * trap that we will then rewrite to the appropriate instruction.
  */
 #define KVM_HYPERCALL ".byte 0x0f,0x01,0xc1"
 
-/* For KVM hypercalls, a three-byte sequence of either the vmcall or the vmmcall
+/* For KVM hypercalls, a three-byte sequence of either the vmrun or the vmmrun
  * instruction.  The hypervisor may replace it with something else but only the
  * instructions are guaranteed to be supported.
  *
@@ -90,19 +170,14 @@ static inline int kvm_para_available(void)
         unsigned int eax, ebx, ecx, edx;
         char signature[13];
 
-        if (boot_cpu_data.cpuid_level < 0)
-                return 0;       /* So we don't blow up on old processors */
-
-        if (cpu_has_hypervisor) {
-                cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx);
-                memcpy(signature + 0, &ebx, 4);
-                memcpy(signature + 4, &ecx, 4);
-                memcpy(signature + 8, &edx, 4);
-                signature[12] = 0;
+        cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx);
+        memcpy(signature + 0, &ebx, 4);
+        memcpy(signature + 4, &ecx, 4);
+        memcpy(signature + 8, &edx, 4);
+        signature[12] = 0;
 
-                if (strcmp(signature, "KVMKVMKVM") == 0)
-                        return 1;
-        }
+        if (strcmp(signature, "KVMKVMKVM") == 0)
+                return 1;
 
         return 0;
 }
@@ -133,4 +208,6 @@ static inline void kvm_disable_steal_time(void)
 }
 #endif
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_X86_KVM_PARA_H */
diff --git a/arch/x86/include/asm/local.h b/arch/x86/include/asm/local.h
index 2d89e3980cb..9cdae5d47e8 100644
--- a/arch/x86/include/asm/local.h
+++ b/arch/x86/include/asm/local.h
@@ -3,6 +3,7 @@
 
 #include <linux/percpu.h>
 
+#include <asm/system.h>
 #include <linux/atomic.h>
 #include <asm/asm.h>
 
@@ -124,11 +125,27 @@ static inline int local_add_negative(long i, local_t *l)
  */
 static inline long local_add_return(long i, local_t *l)
 {
-        long __i = i;
+        long __i;
+#ifdef CONFIG_M386
+        unsigned long flags;
+        if (unlikely(boot_cpu_data.x86 <= 3))
+                goto no_xadd;
+#endif
+        /* Modern 486+ processor */
+        __i = i;
         asm volatile(_ASM_XADD "%0, %1;"
                      : "+r" (i), "+m" (l->a.counter)
                      : : "memory");
         return i + __i;
+
+#ifdef CONFIG_M386
+no_xadd: /* Legacy 386 processor */
+        local_irq_save(flags);
+        __i = local_read(l);
+        local_set(l, i + __i);
+        local_irq_restore(flags);
+        return i + __i;
+#endif
 }
 
 static inline long local_sub_return(long i, local_t *l)
diff --git a/arch/x86/include/asm/mach_timer.h b/arch/x86/include/asm/mach_timer.h
index 88d0c3c74c1..853728519ae 100644
--- a/arch/x86/include/asm/mach_timer.h
+++ b/arch/x86/include/asm/mach_timer.h
@@ -15,7 +15,7 @@
 
 #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
 #define CALIBRATE_LATCH \
-        ((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
+        ((CLOCK_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
 
 static inline void mach_prepare_counter(void)
 {
diff --git a/arch/x86/include/asm/mach_traps.h b/arch/x86/include/asm/mach_traps.h
index a01e7ec7d23..72a8b52e7df 100644
--- a/arch/x86/include/asm/mach_traps.h
+++ b/arch/x86/include/asm/mach_traps.h
@@ -17,7 +17,7 @@
 #define NMI_REASON_CLEAR_IOCHK  0x08
 #define NMI_REASON_CLEAR_MASK   0x0f
 
-static inline unsigned char default_get_nmi_reason(void)
+static inline unsigned char get_nmi_reason(void)
 {
         return inb(NMI_REASON_PORT);
 }
diff --git a/arch/x86/include/asm/mc146818rtc.h b/arch/x86/include/asm/mc146818rtc.h
index d354fb781c5..01fdf5674e2 100644
--- a/arch/x86/include/asm/mc146818rtc.h
+++ b/arch/x86/include/asm/mc146818rtc.h
@@ -5,6 +5,7 @@
 #define _ASM_X86_MC146818RTC_H
 
 #include <asm/io.h>
+#include <asm/system.h>
 #include <asm/processor.h>
 #include <linux/mc146818rtc.h>
 
@@ -80,8 +81,8 @@ static inline unsigned char current_lock_cmos_reg(void)
 #else
 #define lock_cmos_prefix(reg) do {} while (0)
 #define lock_cmos_suffix(reg) do {} while (0)
-#define lock_cmos(reg) do { } while (0)
-#define unlock_cmos() do { } while (0)
+#define lock_cmos(reg)
+#define unlock_cmos()
 #define do_i_have_lock_cmos() 0
 #define current_lock_cmos_reg() 0
 #endif
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ecdfee60ee4..c9321f34e55 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -1,32 +1,132 @@
 #ifndef _ASM_X86_MCE_H
 #define _ASM_X86_MCE_H
 
-#include <uapi/asm/mce.h>
-
-
-struct mca_config {
-        bool dont_log_ce;
-        bool cmci_disabled;
-        bool ignore_ce;
-        bool disabled;
-        bool ser;
-        bool bios_cmci_threshold;
-        u8 banks;
-        s8 bootlog;
-        int tolerant;
-        int monarch_timeout;
-        int panic_timeout;
-        u32 rip_msr;
+#include <linux/types.h>
+#include <asm/ioctls.h>
+
+/*
+ * Machine Check support for x86
+ */
+
+/* MCG_CAP register defines */
+#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
+#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
+#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
+#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
+#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
+#define MCG_EXT_CNT_SHIFT       16
+#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
+#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
+
+/* MCG_STATUS register defines */
+#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
+#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
+#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
+
+/* MCi_STATUS register defines */
+#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
+#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
+#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
+#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
+#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
+#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
+#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
+#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
+#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
+
+/* MCi_MISC register defines */
+#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
+#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
+#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
+#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
+#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
+#define  MCI_MISC_ADDR_MEM      3       /* memory address */
+#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
+
+/* CTL2 register defines */
+#define MCI_CTL2_CMCI_EN                (1ULL << 30)
+#define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
+
+#define MCJ_CTX_MASK            3
+#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
+#define MCJ_CTX_RANDOM          0    /* inject context: random */
+#define MCJ_CTX_PROCESS         1    /* inject context: process */
+#define MCJ_CTX_IRQ             2    /* inject context: IRQ */
+#define MCJ_NMI_BROADCAST       4    /* do NMI broadcasting */
+#define MCJ_EXCEPTION           8    /* raise as exception */
+
+/* Fields are zero when not available */
+struct mce {
+        __u64 status;
+        __u64 misc;
+        __u64 addr;
+        __u64 mcgstatus;
+        __u64 ip;
+        __u64 tsc;      /* cpu time stamp counter */
+        __u64 time;     /* wall time_t when error was detected */
+        __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
+        __u8  inject_flags;     /* software inject flags */
+        __u16  pad;
+        __u32 cpuid;    /* CPUID 1 EAX */
+        __u8  cs;               /* code segment */
+        __u8  bank;     /* machine check bank */
+        __u8  cpu;      /* cpu number; obsolete; use extcpu now */
+        __u8  finished;   /* entry is valid */
+        __u32 extcpu;   /* linux cpu number that detected the error */
+        __u32 socketid; /* CPU socket ID */
+        __u32 apicid;   /* CPU initial apic ID */
+        __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
+};
+
+/*
+ * This structure contains all data related to the MCE log.  Also
+ * carries a signature to make it easier to find from external
+ * debugging tools.  Each entry is only valid when its finished flag
+ * is set.
+ */
+
+#define MCE_LOG_LEN 32
+
+struct mce_log {
+        char signature[12]; /* "MACHINECHECK" */
+        unsigned len;       /* = MCE_LOG_LEN */
+        unsigned next;
+        unsigned flags;
+        unsigned recordlen;     /* length of struct mce */
+        struct mce entry[MCE_LOG_LEN];
 };
 
-extern struct mca_config mca_cfg;
-extern void mce_register_decode_chain(struct notifier_block *nb);
-extern void mce_unregister_decode_chain(struct notifier_block *nb);
+#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
+
+#define MCE_LOG_SIGNATURE       "MACHINECHECK"
+
+#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
+#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
+#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
+
+/* Software defined banks */
+#define MCE_EXTENDED_BANK       128
+#define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
+
+#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
+#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
+#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
+#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
+#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
+#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
+#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
+#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
+
+
+#ifdef __KERNEL__
+
+extern struct atomic_notifier_head x86_mce_decoder_chain;
 
 #include <linux/percpu.h>
 #include <linux/init.h>
 #include <linux/atomic.h>
 
+extern int mce_disabled;
 extern int mce_p5_enabled;
 
 #ifdef CONFIG_X86_MCE
@@ -49,7 +149,7 @@ static inline void enable_p5_mce(void) {}
 
 void mce_setup(struct mce *m);
 void mce_log(struct mce *m);
-DECLARE_PER_CPU(struct device *, mce_device);
+DECLARE_PER_CPU(struct sys_device, mce_sysdev);
 
 /*
  * Maximum banks number.
@@ -59,6 +159,8 @@ DECLARE_PER_CPU(struct device *, mce_device);
 #define MAX_NR_BANKS 32
 
 #ifdef CONFIG_X86_MCE_INTEL
+extern int mce_cmci_disabled;
+extern int mce_ignore_ce;
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 void cmci_clear(void);
 void cmci_reenable(void);
@@ -99,10 +201,7 @@ int mce_notify_irq(void);
 void mce_notify_process(void);
 
 DECLARE_PER_CPU(struct mce, injectm);
-
-extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
-                                    const char __user *ubuf,
-                                    size_t usize, loff_t *off));
+extern struct file_operations mce_chrdev_ops;
 
 /*
  * Exception handler
@@ -144,4 +243,5 @@ struct cper_sec_mem_err;
 extern void apei_mce_report_mem_error(int corrected,
                                       struct cper_sec_mem_err *mem_err);
 
+#endif /* __KERNEL__ */
 #endif /* _ASM_X86_MCE_H */
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 43d921b4752..24215072d0e 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -15,8 +15,8 @@ struct microcode_ops {
         enum ucode_state (*request_microcode_user) (int cpu,
                                 const void __user *buf, size_t size);
 
-        enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
-                                                  bool refresh_fw);
+        enum ucode_state (*request_microcode_fw) (int cpu,
+                                struct device *device);
 
         void (*microcode_fini_cpu) (int cpu);
 
@@ -48,13 +48,17 @@ static inline struct microcode_ops * __init init_intel_microcode(void)
 
 #ifdef CONFIG_MICROCODE_AMD
 extern struct microcode_ops * __init init_amd_microcode(void);
-extern void __exit exit_amd_microcode(void);
+
+static inline void get_ucode_data(void *to, const u8 *from, size_t n)
+{
+        memcpy(to, from, n);
+}
+
 #else
 static inline struct microcode_ops * __init init_amd_microcode(void)
 {
         return NULL;
 }
-static inline void __exit exit_amd_microcode(void) {}
 #endif
 
 #endif /* _ASM_X86_MICROCODE_H */
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index cdbf3677610..69021528b43 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -25,8 +25,8 @@ void destroy_context(struct mm_struct *mm);
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 #ifdef CONFIG_SMP
-        if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
-                this_cpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
+        if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
+                percpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
 #endif
 }
 
@@ -37,8 +37,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 
         if (likely(prev != next)) {
 #ifdef CONFIG_SMP
-                this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
-                this_cpu_write(cpu_tlbstate.active_mm, next);
+                percpu_write(cpu_tlbstate.state, TLBSTATE_OK);
+                percpu_write(cpu_tlbstate.active_mm, next);
 #endif
                 cpumask_set_cpu(cpu, mm_cpumask(next));
 
@@ -56,8 +56,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         }
 #ifdef CONFIG_SMP
         else {
-                this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
-                BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
+                percpu_write(cpu_tlbstate.state, TLBSTATE_OK);
+                BUG_ON(percpu_read(cpu_tlbstate.active_mm) != next);
 
                 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) {
                         /* We were in lazy tlb mode and leave_mm disabled
diff --git a/arch/x86/include/asm/mmzone.h b/arch/x86/include/asm/mmzone.h
index d497bc425ca..64217ea16a3 100644
--- a/arch/x86/include/asm/mmzone.h
+++ b/arch/x86/include/asm/mmzone.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/mmzone_32.h>
+# include "mmzone_32.h"
 #else
-# include <asm/mmzone_64.h>
+# include "mmzone_64.h"
 #endif
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index eb05fb3b02f..55728e12147 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -61,4 +61,10 @@ static inline int pfn_valid(int pfn)
 
 #endif /* CONFIG_DISCONTIGMEM */
 
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+/* always use node 0 for bootmem on this numa platform */
+#define bootmem_arch_preferred_node(__bdata, size, align, goal, limit)  \
+        (NODE_DATA(0)->bdata)
+#endif /* CONFIG_NEED_MULTIPLE_NODES */
+
 #endif /* _ASM_X86_MMZONE_32_H */
diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h
index e3b7819caee..9eae7752ae9 100644
--- a/arch/x86/include/asm/module.h
+++ b/arch/x86/include/asm/module.h
@@ -5,6 +5,8 @@
 
 #ifdef CONFIG_X86_64
 /* X86_64 does not define MODULE_PROC_FAMILY */
+#elif defined CONFIG_M386
+#define MODULE_PROC_FAMILY "386 "
 #elif defined CONFIG_M486
 #define MODULE_PROC_FAMILY "486 "
 #elif defined CONFIG_M586
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 3e2f42a4b87..9c7d95f6174 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -40,7 +40,7 @@ extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 
 #endif /* CONFIG_X86_64 */
 
-#ifdef CONFIG_EISA
+#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
 extern int mp_bus_id_to_type[MAX_MP_BUSSES];
 #endif
 
diff --git a/arch/x86/include/asm/mpspec_def.h b/arch/x86/include/asm/mpspec_def.h
index b31f8c09827..c0a955a9a08 100644
--- a/arch/x86/include/asm/mpspec_def.h
+++ b/arch/x86/include/asm/mpspec_def.h
@@ -84,7 +84,7 @@ struct mpc_bus {
 #define BUSTYPE_EISA    "EISA"
 #define BUSTYPE_ISA     "ISA"
 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
-#define BUSTYPE_MCA     "MCA"           /* Obsolete */
+#define BUSTYPE_MCA     "MCA"
 #define BUSTYPE_VL      "VL"            /* Local bus */
 #define BUSTYPE_PCI     "PCI"
 #define BUSTYPE_PCMCIA  "PCMCIA"
@@ -169,5 +169,6 @@ enum mp_bustype {
         MP_BUS_ISA = 1,
         MP_BUS_EISA,
         MP_BUS_PCI,
+        MP_BUS_MCA,
 };
 #endif /* _ASM_X86_MPSPEC_DEF_H */
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index fc18bf3ce7c..719f00b28ff 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -26,25 +26,16 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[];
  * identified via MSRs.
  */
 enum mrst_cpu_type {
-        /* 1 was Moorestown */
-        MRST_CPU_CHIP_PENWELL = 2,
+        MRST_CPU_CHIP_LINCROFT = 1,
+        MRST_CPU_CHIP_PENWELL,
 };
 
 extern enum mrst_cpu_type __mrst_cpu_chip;
-
-#ifdef CONFIG_X86_INTEL_MID
-
 static inline enum mrst_cpu_type mrst_identify_cpu(void)
 {
         return __mrst_cpu_chip;
 }
 
-#else /* !CONFIG_X86_INTEL_MID */
-
-#define mrst_identify_cpu()    (0)
-
-#endif /* !CONFIG_X86_INTEL_MID */
-
 enum mrst_timer_options {
         MRST_TIMER_DEFAULT,
         MRST_TIMER_APBT_ONLY,
@@ -53,13 +44,6 @@ enum mrst_timer_options {
 
 extern enum mrst_timer_options mrst_timer_options;
 
-/*
- * Penwell uses spread spectrum clock, so the freq number is not exactly
- * the same as reported by MSR based on SDM.
- */
-#define PENWELL_FSB_FREQ_83SKU         83200
-#define PENWELL_FSB_FREQ_100SKU        99840
-
 #define SFI_MTMR_MAX_NUM 8
 #define SFI_MRTC_MAX    8
 
@@ -67,7 +51,7 @@ extern struct console early_mrst_console;
 extern void mrst_early_console_init(void);
 
 extern struct console early_hsu_console;
-extern void hsu_early_console_init(const char *);
+extern void hsu_early_console_init(void);
 
 extern void intel_scu_devices_create(void);
 extern void intel_scu_devices_destroy(void);
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 9264802e282..084ef95274c 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -1,10 +1,18 @@
 #ifndef _ASM_X86_MSR_H
 #define _ASM_X86_MSR_H
 
-#include <uapi/asm/msr.h>
+#include <asm/msr-index.h>
 
 #ifndef __ASSEMBLY__
 
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define X86_IOC_RDMSR_REGS      _IOWR('c', 0xA0, __u32[8])
+#define X86_IOC_WRMSR_REGS      _IOWR('c', 0xA1, __u32[8])
+
+#ifdef __KERNEL__
+
 #include <asm/asm.h>
 #include <asm/errno.h>
 #include <asm/cpumask.h>
@@ -107,8 +115,8 @@ notrace static inline int native_write_msr_safe(unsigned int msr,
 
 extern unsigned long long native_read_tsc(void);
 
-extern int rdmsr_safe_regs(u32 regs[8]);
-extern int wrmsr_safe_regs(u32 regs[8]);
+extern int native_rdmsr_safe_regs(u32 regs[8]);
+extern int native_wrmsr_safe_regs(u32 regs[8]);
 
 static __always_inline unsigned long long __native_read_tsc(void)
 {
@@ -179,6 +187,43 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         return err;
 }
 
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+        u32 gprs[8] = { 0 };
+        int err;
+
+        gprs[1] = msr;
+        gprs[7] = 0x9c5a203a;
+
+        err = native_rdmsr_safe_regs(gprs);
+
+        *p = gprs[0] | ((u64)gprs[2] << 32);
+
+        return err;
+}
+
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+        u32 gprs[8] = { 0 };
+
+        gprs[0] = (u32)val;
+        gprs[1] = msr;
+        gprs[2] = val >> 32;
+        gprs[7] = 0x9c5a203a;
+
+        return native_wrmsr_safe_regs(gprs);
+}
+
+static inline int rdmsr_safe_regs(u32 regs[8])
+{
+        return native_rdmsr_safe_regs(regs);
+}
+
+static inline int wrmsr_safe_regs(u32 regs[8])
+{
+        return native_wrmsr_safe_regs(regs);
+}
+
 #define rdtscl(low)                                             \
         ((low) = (u32)__native_read_tsc())
 
@@ -192,8 +237,6 @@ do {							\
         (high) = (u32)(_l >> 32);                       \
 } while (0)
 
-#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
-
 #define rdtscp(low, high, aux)                                  \
 do {                                                            \
         unsigned long long _val = native_read_tscp(&(aux));     \
@@ -205,7 +248,8 @@ do {                                                            \
 
 #endif  /* !CONFIG_PARAVIRT */
 
-#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),             \
+
+#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),         \
                                              (u32)((val) >> 32))
 
 #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
@@ -263,5 +307,6 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
         return wrmsr_safe_regs(regs);
 }
 #endif  /* CONFIG_SMP */
+#endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_X86_MSR_H */
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index e235582f993..4365ffdb461 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -23,8 +23,89 @@
 #ifndef _ASM_X86_MTRR_H
 #define _ASM_X86_MTRR_H
 
-#include <uapi/asm/mtrr.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/errno.h>
 
+#define MTRR_IOCTL_BASE 'M'
+
+struct mtrr_sentry {
+    unsigned long base;    /*  Base address     */
+    unsigned int size;    /*  Size of region   */
+    unsigned int type;     /*  Type of region   */
+};
+
+/* Warning: this structure has a different order from i386
+   on x86-64. The 32bit emulation code takes care of that.
+   But you need to use this for 64bit, otherwise your X server
+   will break. */
+
+#ifdef __i386__
+struct mtrr_gentry {
+    unsigned int regnum;   /*  Register number  */
+    unsigned long base;    /*  Base address     */
+    unsigned int size;    /*  Size of region   */
+    unsigned int type;     /*  Type of region   */
+};
+
+#else /* __i386__ */
+
+struct mtrr_gentry {
+    unsigned long base;    /*  Base address     */
+    unsigned int size;    /*  Size of region   */
+    unsigned int regnum;   /*  Register number  */
+    unsigned int type;     /*  Type of region   */
+};
+#endif /* !__i386__ */
+
+struct mtrr_var_range {
+        __u32 base_lo;
+        __u32 base_hi;
+        __u32 mask_lo;
+        __u32 mask_hi;
+};
+
+/* In the Intel processor's MTRR interface, the MTRR type is always held in
+   an 8 bit field: */
+typedef __u8 mtrr_type;
+
+#define MTRR_NUM_FIXED_RANGES 88
+#define MTRR_MAX_VAR_RANGES 256
+
+struct mtrr_state_type {
+        struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
+        mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
+        unsigned char enabled;
+        unsigned char have_fixed;
+        mtrr_type def_type;
+};
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+/*  These are the various ioctls  */
+#define MTRRIOC_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry)
+#define MTRRIOC_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry)
+#define MTRRIOC_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry)
+#define MTRRIOC_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
+#define MTRRIOC_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry)
+#define MTRRIOC_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry)
+#define MTRRIOC_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry)
+#define MTRRIOC_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry)
+#define MTRRIOC_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
+#define MTRRIOC_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry)
+
+/*  These are the region types  */
+#define MTRR_TYPE_UNCACHABLE 0
+#define MTRR_TYPE_WRCOMB     1
+/*#define MTRR_TYPE_         2*/
+/*#define MTRR_TYPE_         3*/
+#define MTRR_TYPE_WRTHROUGH  4
+#define MTRR_TYPE_WRPROT     5
+#define MTRR_TYPE_WRBACK     6
+#define MTRR_NUM_TYPES       7
+
+#ifdef __KERNEL__
 
 /*  The following functions are for use by other drivers  */
 # ifdef CONFIG_MTRR
@@ -119,4 +200,6 @@ struct mtrr_gentry32 {
                                  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry32)
 #endif /* CONFIG_COMPAT */
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_X86_MTRR_H */
diff --git a/arch/x86/include/asm/mutex.h b/arch/x86/include/asm/mutex.h
index 7d3a4827539..a731b9c573a 100644
--- a/arch/x86/include/asm/mutex.h
+++ b/arch/x86/include/asm/mutex.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/mutex_32.h>
+# include "mutex_32.h"
 #else
-# include <asm/mutex_64.h>
+# include "mutex_64.h"
 #endif
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index c0fa356e90d..4886a68f267 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -22,44 +22,27 @@ void arch_trigger_all_cpu_backtrace(void);
 #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
 #endif
 
-#define NMI_FLAG_FIRST  1
-
-enum {
-        NMI_LOCAL=0,
-        NMI_UNKNOWN,
-        NMI_SERR,
-        NMI_IO_CHECK,
-        NMI_MAX
-};
-
-#define NMI_DONE        0
-#define NMI_HANDLED     1
-
-typedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);
-
-struct nmiaction {
-        struct list_head        list;
-        nmi_handler_t           handler;
-        unsigned long           flags;
-        const char              *name;
-};
-
-#define register_nmi_handler(t, fn, fg, n, init...)     \
-({                                                      \
-        static struct nmiaction init fn##_na = {        \
-                .handler = (fn),                        \
-                .name = (n),                            \
-                .flags = (fg),                          \
-        };                                              \
-        __register_nmi_handler((t), &fn##_na);          \
-})
-
-int __register_nmi_handler(unsigned int, struct nmiaction *);
-
-void unregister_nmi_handler(unsigned int, const char *);
+/*
+ * Define some priorities for the nmi notifier call chain.
+ *
+ * Create a local nmi bit that has a higher priority than
+ * external nmis, because the local ones are more frequent.
+ *
+ * Also setup some default high/normal/low settings for
+ * subsystems to registers with.  Using 4 bits to separate
+ * the priorities.  This can go a lot higher if needed be.
+ */
+
+#define NMI_LOCAL_SHIFT         16      /* randomly picked */
+#define NMI_LOCAL_BIT           (1ULL << NMI_LOCAL_SHIFT)
+#define NMI_HIGH_PRIOR          (1ULL << 8)
+#define NMI_NORMAL_PRIOR        (1ULL << 4)
+#define NMI_LOW_PRIOR           (1ULL << 0)
+#define NMI_LOCAL_HIGH_PRIOR    (NMI_LOCAL_BIT | NMI_HIGH_PRIOR)
+#define NMI_LOCAL_NORMAL_PRIOR  (NMI_LOCAL_BIT | NMI_NORMAL_PRIOR)
+#define NMI_LOCAL_LOW_PRIOR     (NMI_LOCAL_BIT | NMI_LOW_PRIOR)
 
 void stop_nmi(void);
 void restart_nmi(void);
-void local_touch_nmi(void);
 
 #endif /* _ASM_X86_NMI_H */
diff --git a/arch/x86/include/asm/nops.h b/arch/x86/include/asm/nops.h
index aff2b335610..405b4032a60 100644
--- a/arch/x86/include/asm/nops.h
+++ b/arch/x86/include/asm/nops.h
@@ -87,11 +87,7 @@
 #define P6_NOP8 0x0f,0x1f,0x84,0x00,0,0,0,0
 #define P6_NOP5_ATOMIC P6_NOP5
 
-#ifdef __ASSEMBLY__
-#define _ASM_MK_NOP(x) .byte x
-#else
 #define _ASM_MK_NOP(x) ".byte " __stringify(x) "\n"
-#endif
 
 #if defined(CONFIG_MK7)
 #define ASM_NOP1 _ASM_MK_NOP(K7_NOP1)
diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h
index 49119fcea2d..bfacd2ccf65 100644
--- a/arch/x86/include/asm/numa.h
+++ b/arch/x86/include/asm/numa.h
@@ -53,9 +53,9 @@ static inline int numa_cpu_node(int cpu)
 #endif  /* CONFIG_NUMA */
 
 #ifdef CONFIG_X86_32
-# include <asm/numa_32.h>
+# include "numa_32.h"
 #else
-# include <asm/numa_64.h>
+# include "numa_64.h"
 #endif
 
 #ifdef CONFIG_NUMA
diff --git a/arch/x86/include/asm/numachip/numachip.h b/arch/x86/include/asm/numachip/numachip.h
deleted file mode 100644
index 1c6f7f6212c..00000000000
--- a/arch/x86/include/asm/numachip/numachip.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Numascale NumaConnect-specific header file
- *
- * Copyright (C) 2012 Numascale AS. All rights reserved.
- *
- * Send feedback to <support@numascale.com>
- *
- */
-
-#ifndef _ASM_X86_NUMACHIP_NUMACHIP_H
-#define _ASM_X86_NUMACHIP_NUMACHIP_H
-
-extern int __init pci_numachip_init(void);
-
-#endif /* _ASM_X86_NUMACHIP_NUMACHIP_H */
diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h
deleted file mode 100644
index 660f843df92..00000000000
--- a/arch/x86/include/asm/numachip/numachip_csr.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Numascale NumaConnect-Specific Header file
- *
- * Copyright (C) 2011 Numascale AS. All rights reserved.
- *
- * Send feedback to <support@numascale.com>
- *
- */
-
-#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
-#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
-
-#include <linux/numa.h>
-#include <linux/percpu.h>
-#include <linux/io.h>
-#include <linux/swab.h>
-#include <asm/types.h>
-#include <asm/processor.h>
-
-#define CSR_NODE_SHIFT          16
-#define CSR_NODE_BITS(p)        (((unsigned long)(p)) << CSR_NODE_SHIFT)
-#define CSR_NODE_MASK           0x0fff          /* 4K nodes */
-
-/* 32K CSR space, b15 indicates geo/non-geo */
-#define CSR_OFFSET_MASK 0x7fffUL
-
-/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
-#define NUMACHIP_GCSR_BASE      0x3fff00000000ULL
-#define NUMACHIP_GCSR_LIM       0x3fff0fffffffULL
-#define NUMACHIP_GCSR_SIZE      (NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)
-
-/*
- * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
- * when using the direct mapping on x86_64, both start and size needs to be
- * aligned with PMD_SIZE which is 2M
- */
-#define NUMACHIP_LCSR_BASE      0x3ffffe000000ULL
-#define NUMACHIP_LCSR_LIM       0x3fffffffffffULL
-#define NUMACHIP_LCSR_SIZE      (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
-
-static inline void *gcsr_address(int node, unsigned long offset)
-{
-        return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |
-                CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));
-}
-
-static inline void *lcsr_address(unsigned long offset)
-{
-        return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
-                CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
-}
-
-static inline unsigned int read_gcsr(int node, unsigned long offset)
-{
-        return swab32(readl(gcsr_address(node, offset)));
-}
-
-static inline void write_gcsr(int node, unsigned long offset, unsigned int val)
-{
-        writel(swab32(val), gcsr_address(node, offset));
-}
-
-static inline unsigned int read_lcsr(unsigned long offset)
-{
-        return swab32(readl(lcsr_address(offset)));
-}
-
-static inline void write_lcsr(unsigned long offset, unsigned int val)
-{
-        writel(swab32(val), lcsr_address(offset));
-}
-
-/* ========================================================================= */
-/*                   CSR_G0_STATE_CLEAR                                      */
-/* ========================================================================= */
-
-#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))
-union numachip_csr_g0_state_clear {
-        unsigned int v;
-        struct numachip_csr_g0_state_clear_s {
-                unsigned int _state:2;
-                unsigned int _rsvd_2_6:5;
-                unsigned int _lost:1;
-                unsigned int _rsvd_8_31:24;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G0_NODE_IDS                                         */
-/* ========================================================================= */
-
-#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
-union numachip_csr_g0_node_ids {
-        unsigned int v;
-        struct numachip_csr_g0_node_ids_s {
-                unsigned int _initialid:16;
-                unsigned int _nodeid:12;
-                unsigned int _rsvd_28_31:4;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G3_EXT_IRQ_GEN                                      */
-/* ========================================================================= */
-
-#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
-union numachip_csr_g3_ext_irq_gen {
-        unsigned int v;
-        struct numachip_csr_g3_ext_irq_gen_s {
-                unsigned int _vector:8;
-                unsigned int _msgtype:3;
-                unsigned int _index:5;
-                unsigned int _destination_apic_id:16;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G3_EXT_IRQ_STATUS                                   */
-/* ========================================================================= */
-
-#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))
-union numachip_csr_g3_ext_irq_status {
-        unsigned int v;
-        struct numachip_csr_g3_ext_irq_status_s {
-                unsigned int _result:32;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G3_EXT_IRQ_DEST                                     */
-/* ========================================================================= */
-
-#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))
-union numachip_csr_g3_ext_irq_dest {
-        unsigned int v;
-        struct numachip_csr_g3_ext_irq_dest_s {
-                unsigned int _irq:8;
-                unsigned int _rsvd_8_31:24;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G3_NC_ATT_MAP_SELECT                                */
-/* ========================================================================= */
-
-#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))
-union numachip_csr_g3_nc_att_map_select {
-        unsigned int v;
-        struct numachip_csr_g3_nc_att_map_select_s {
-                unsigned int _upper_address_bits:4;
-                unsigned int _select_ram:4;
-                unsigned int _rsvd_8_31:24;
-        } s;
-};
-
-/* ========================================================================= */
-/*                   CSR_G3_NC_ATT_MAP_SELECT_0-255                          */
-/* ========================================================================= */
-
-#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))
-
-#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
-
diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h
index 72f9adf6eca..87bdbca72f9 100644
--- a/arch/x86/include/asm/olpc.h
+++ b/arch/x86/include/asm/olpc.h
@@ -100,6 +100,25 @@ extern void olpc_xo1_pm_wakeup_clear(u16 value);
 
 extern int pci_olpc_init(void);
 
+/* EC related functions */
+
+extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
+                unsigned char *outbuf, size_t outlen);
+
+/* EC commands */
+
+#define EC_FIRMWARE_REV                 0x08
+#define EC_WRITE_SCI_MASK               0x1b
+#define EC_WAKE_UP_WLAN                 0x24
+#define EC_WLAN_LEAVE_RESET             0x25
+#define EC_READ_EB_MODE                 0x2a
+#define EC_SET_SCI_INHIBIT              0x32
+#define EC_SET_SCI_INHIBIT_RELEASE      0x34
+#define EC_WLAN_ENTER_RESET             0x35
+#define EC_WRITE_EXT_SCI_MASK           0x38
+#define EC_SCI_QUERY                    0x84
+#define EC_EXT_SCI_QUERY                0x85
+
 /* SCI source values */
 
 #define EC_SCI_SRC_EMPTY        0x00
diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/page_32_types.h
index ef17af01347..ade619ff9e2 100644
--- a/arch/x86/include/asm/page_32_types.h
+++ b/arch/x86/include/asm/page_32_types.h
@@ -15,8 +15,8 @@
  */
 #define __PAGE_OFFSET           _AC(CONFIG_PAGE_OFFSET, UL)
 
-#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_ORDER    1
+#define THREAD_SIZE     (PAGE_SIZE << THREAD_ORDER)
 
 #define STACKFAULT_STACK 0
 #define DOUBLEFAULT_STACK 1
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 320f7bb95f7..7639dbf5d22 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -1,8 +1,8 @@
 #ifndef _ASM_X86_PAGE_64_DEFS_H
 #define _ASM_X86_PAGE_64_DEFS_H
 
-#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE  (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_ORDER    1
+#define THREAD_SIZE  (PAGE_SIZE << THREAD_ORDER)
 #define CURRENT_MASK (~(THREAD_SIZE - 1))
 
 #define EXCEPTION_STACK_ORDER 0
diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h
index e21fdd10479..bce688d54c1 100644
--- a/arch/x86/include/asm/page_types.h
+++ b/arch/x86/include/asm/page_types.h
@@ -55,6 +55,7 @@ extern unsigned long init_memory_mapping(unsigned long start,
                                          unsigned long end);
 
 extern void initmem_init(void);
+extern void free_initmem(void);
 
 #endif  /* !__ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 5edd1742cfd..a7d2db9a74f 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -10,7 +10,6 @@
 #include <asm/paravirt_types.h>
 
 #ifndef __ASSEMBLY__
-#include <linux/bug.h>
 #include <linux/types.h>
 #include <linux/cpumask.h>
 
@@ -128,11 +127,21 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err)
         return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
 }
 
+static inline int paravirt_rdmsr_regs(u32 *regs)
+{
+        return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);
+}
+
 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
 {
         return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
 }
 
+static inline int paravirt_wrmsr_regs(u32 *regs)
+{
+        return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs);
+}
+
 /* These should all do BUG_ON(_err), but our headers are too tangled. */
 #define rdmsr(msr, val1, val2)                  \
 do {                                            \
@@ -166,6 +175,9 @@ do {						\
         _err;                                   \
 })
 
+#define rdmsr_safe_regs(regs)   paravirt_rdmsr_regs(regs)
+#define wrmsr_safe_regs(regs)   paravirt_wrmsr_regs(regs)
+
 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
 {
         int err;
@@ -173,6 +185,32 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         *p = paravirt_read_msr(msr, &err);
         return err;
 }
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+        u32 gprs[8] = { 0 };
+        int err;
+
+        gprs[1] = msr;
+        gprs[7] = 0x9c5a203a;
+
+        err = paravirt_rdmsr_regs(gprs);
+
+        *p = gprs[0] | ((u64)gprs[2] << 32);
+
+        return err;
+}
+
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+        u32 gprs[8] = { 0 };
+
+        gprs[0] = (u32)val;
+        gprs[1] = msr;
+        gprs[2] = val >> 32;
+        gprs[7] = 0x9c5a203a;
+
+        return paravirt_wrmsr_regs(gprs);
+}
 
 static inline u64 paravirt_read_tsc(void)
 {
@@ -192,9 +230,9 @@ static inline unsigned long long paravirt_sched_clock(void)
         return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
 }
 
-struct static_key;
-extern struct static_key paravirt_steal_enabled;
-extern struct static_key paravirt_steal_rq_enabled;
+struct jump_label_key;
+extern struct jump_label_key paravirt_steal_enabled;
+extern struct jump_label_key paravirt_steal_rq_enabled;
 
 static inline u64 paravirt_steal_clock(int cpu)
 {
@@ -213,8 +251,6 @@ do {						\
         high = _l >> 32;                        \
 } while (0)
 
-#define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
-
 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
 {
         return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
@@ -360,10 +396,9 @@ static inline void __flush_tlb_single(unsigned long addr)
 
 static inline void flush_tlb_others(const struct cpumask *cpumask,
                                     struct mm_struct *mm,
-                                    unsigned long start,
-                                    unsigned long end)
+                                    unsigned long va)
 {
-        PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end);
+        PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, cpumask, mm, va);
 }
 
 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
@@ -528,6 +563,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
                 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
 }
 
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
                               pmd_t *pmdp, pmd_t pmd)
 {
@@ -538,6 +574,7 @@ static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
                 PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp,
                             native_pmd_val(pmd));
 }
+#endif
 
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
@@ -985,8 +1022,10 @@ extern void default_banner(void);
                   call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs)          \
                  )
 
-#define GET_CR2_INTO_RAX                                \
-        call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2)
+#define GET_CR2_INTO_RCX                                \
+        call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \
+        movq %rax, %rcx;                                \
+        xorq %rax, %rax;
 
 #define PARAVIRT_ADJUST_EXCEPTION_FRAME                                 \
         PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 142236ed83a..8e8b9a4987e 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -153,7 +153,9 @@ struct pv_cpu_ops {
         /* MSR, PMC and TSR operations.
            err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
         u64 (*read_msr)(unsigned int msr, int *err);
+        int (*rdmsr_regs)(u32 *regs);
         int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
+        int (*wrmsr_regs)(u32 *regs);
 
         u64 (*read_tsc)(void);
         u64 (*read_pmc)(int counter);
@@ -248,8 +250,7 @@ struct pv_mmu_ops {
         void (*flush_tlb_single)(unsigned long addr);
         void (*flush_tlb_others)(const struct cpumask *cpus,
                                  struct mm_struct *mm,
-                                 unsigned long start,
-                                 unsigned long end);
+                                 unsigned long va);
 
         /* Hooks for allocating and freeing a pagetable top-level */
         int  (*pgd_alloc)(struct mm_struct *mm);
diff --git a/arch/x86/include/asm/parport.h b/arch/x86/include/asm/parport.h
index 0d2d3b29118..3c4ffeb467e 100644
--- a/arch/x86/include/asm/parport.h
+++ b/arch/x86/include/asm/parport.h
@@ -1,8 +1,8 @@
 #ifndef _ASM_X86_PARPORT_H
 #define _ASM_X86_PARPORT_H
 
-static int parport_pc_find_isa_ports(int autoirq, int autodma);
-static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
+static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
+static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
 {
         return parport_pc_find_isa_ports(autoirq, autodma);
 }
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index dba7805176b..d498943b906 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -112,28 +112,19 @@ static inline void x86_teardown_msi_irq(unsigned int irq)
 {
         x86_msi.teardown_msi_irq(irq);
 }
-static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
-{
-        x86_msi.restore_msi_irqs(dev, irq);
-}
 #define arch_setup_msi_irqs x86_setup_msi_irqs
 #define arch_teardown_msi_irqs x86_teardown_msi_irqs
 #define arch_teardown_msi_irq x86_teardown_msi_irq
-#define arch_restore_msi_irqs x86_restore_msi_irqs
 /* implemented in arch/x86/kernel/apic/io_apic. */
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void native_teardown_msi_irq(unsigned int irq);
-void native_restore_msi_irqs(struct pci_dev *dev, int irq);
 /* default to the implementation in drivers/lib/msi.c */
 #define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
-#define HAVE_DEFAULT_MSI_RESTORE_IRQS
 void default_teardown_msi_irqs(struct pci_dev *dev);
-void default_restore_msi_irqs(struct pci_dev *dev, int irq);
 #else
 #define native_setup_msi_irqs           NULL
 #define native_teardown_msi_irq         NULL
 #define default_teardown_msi_irqs       NULL
-#define default_restore_msi_irqs        NULL
 #endif
 
 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
@@ -141,7 +132,7 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq);
 #endif  /* __KERNEL__ */
 
 #ifdef CONFIG_X86_64
-#include <asm/pci_64.h>
+#include "pci_64.h"
 #endif
 
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
@@ -171,16 +162,4 @@ cpumask_of_pcibus(const struct pci_bus *bus)
 }
 #endif
 
-struct pci_setup_rom {
-        struct setup_data data;
-        uint16_t vendor;
-        uint16_t devid;
-        uint64_t pcilen;
-        unsigned long segment;
-        unsigned long bus;
-        unsigned long device;
-        unsigned long function;
-        uint8_t romdata[0];
-};
-
 #endif /* _ASM_X86_PCI_H */
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 747e5a38b59..704526734be 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -7,13 +7,9 @@
 #undef DEBUG
 
 #ifdef DEBUG
-#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
+#define DBG(x...) printk(x)
 #else
-#define DBG(fmt, ...)                           \
-do {                                            \
-        if (0)                                  \
-                printk(fmt, ##__VA_ARGS__);     \
-} while (0)
+#define DBG(x...)
 #endif
 
 #define PCI_PROBE_BIOS          0x0001
@@ -48,6 +44,8 @@ enum pci_bf_sort_state {
 
 /* pci-i386.c */
 
+extern unsigned int pcibios_max_latency;
+
 void pcibios_resource_survey(void);
 void pcibios_set_cache_line_size(void);
 
@@ -101,11 +99,10 @@ struct pci_raw_ops {
                                                 int reg, int len, u32 val);
 };
 
-extern const struct pci_raw_ops *raw_pci_ops;
-extern const struct pci_raw_ops *raw_pci_ext_ops;
+extern struct pci_raw_ops *raw_pci_ops;
+extern struct pci_raw_ops *raw_pci_ext_ops;
 
-extern const struct pci_raw_ops pci_mmcfg;
-extern const struct pci_raw_ops pci_direct_conf1;
+extern struct pci_raw_ops pci_direct_conf1;
 extern bool port_cf9_safe;
 
 /* arch_initcall level */
@@ -140,11 +137,6 @@ struct pci_mmcfg_region {
 
 extern int __init pci_mmcfg_arch_init(void);
 extern void __init pci_mmcfg_arch_free(void);
-extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
-extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
-extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
-                               phys_addr_t addr);
-extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
 
 extern struct list_head pci_mmcfg_list;
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 0da5200ee79..3470c9d0ebb 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -46,7 +46,7 @@
 
 #ifdef CONFIG_SMP
 #define __percpu_prefix         "%%"__stringify(__percpu_seg)":"
-#define __my_cpu_offset         this_cpu_read(this_cpu_off)
+#define __my_cpu_offset         percpu_read(this_cpu_off)
 
 /*
  * Compared to the generic __my_cpu_offset version, the following
@@ -351,15 +351,23 @@ do {									\
 })
 
 /*
- * this_cpu_read() makes gcc load the percpu variable every time it is
- * accessed while this_cpu_read_stable() allows the value to be cached.
- * this_cpu_read_stable() is more efficient and can be used if its value
+ * percpu_read() makes gcc load the percpu variable every time it is
+ * accessed while percpu_read_stable() allows the value to be cached.
+ * percpu_read_stable() is more efficient and can be used if its value
  * is guaranteed to be valid across cpus.  The current users include
  * get_current() and get_thread_info() both of which are actually
  * per-thread variables implemented as per-cpu variables and thus
  * stable for the duration of the respective task.
  */
-#define this_cpu_read_stable(var)       percpu_from_op("mov", var, "p" (&(var)))
+#define percpu_read(var)                percpu_from_op("mov", var, "m" (var))
+#define percpu_read_stable(var)         percpu_from_op("mov", var, "p" (&(var)))
+#define percpu_write(var, val)          percpu_to_op("mov", var, val)
+#define percpu_add(var, val)            percpu_add_op(var, val)
+#define percpu_sub(var, val)            percpu_add_op(var, -(val))
+#define percpu_and(var, val)            percpu_to_op("and", var, val)
+#define percpu_or(var, val)             percpu_to_op("or", var, val)
+#define percpu_xor(var, val)            percpu_to_op("xor", var, val)
+#define percpu_inc(var)         percpu_unary_op("inc", var)
 
 #define __this_cpu_read_1(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
 #define __this_cpu_read_2(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
@@ -406,6 +414,23 @@ do {									\
 #define this_cpu_xchg_2(pcp, nval)      percpu_xchg_op(pcp, nval)
 #define this_cpu_xchg_4(pcp, nval)      percpu_xchg_op(pcp, nval)
 
+#define irqsafe_cpu_add_1(pcp, val)     percpu_add_op((pcp), val)
+#define irqsafe_cpu_add_2(pcp, val)     percpu_add_op((pcp), val)
+#define irqsafe_cpu_add_4(pcp, val)     percpu_add_op((pcp), val)
+#define irqsafe_cpu_and_1(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_and_2(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_and_4(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_or_1(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_or_2(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_or_4(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_xor_1(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xor_2(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xor_4(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xchg_1(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_xchg_2(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_xchg_4(pcp, nval)   percpu_xchg_op(pcp, nval)
+
+#ifndef CONFIG_M386
 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
 #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
 #define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
@@ -420,20 +445,29 @@ do {									\
 #define this_cpu_cmpxchg_2(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 #define this_cpu_cmpxchg_4(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 
+#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#endif /* !CONFIG_M386 */
+
 #ifdef CONFIG_X86_CMPXCHG64
-#define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2)             \
+#define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)                   \
 ({                                                                      \
-        bool __ret;                                                     \
-        typeof(pcp1) __o1 = (o1), __n1 = (n1);                          \
-        typeof(pcp2) __o2 = (o2), __n2 = (n2);                          \
+        char __ret;                                                     \
+        typeof(o1) __o1 = o1;                                           \
+        typeof(o1) __n1 = n1;                                           \
+        typeof(o2) __o2 = o2;                                           \
+        typeof(o2) __n2 = n2;                                           \
+        typeof(o2) __dummy = n2;                                        \
         asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t"       \
-                    : "=a" (__ret), "+m" (pcp1), "+m" (pcp2), "+d" (__o2) \
-                    :  "b" (__n1), "c" (__n2), "a" (__o1));             \
+                    : "=a"(__ret), "=m" (pcp1), "=d"(__dummy)           \
+                    :  "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2));     \
         __ret;                                                          \
 })
 
-#define __this_cpu_cmpxchg_double_4     percpu_cmpxchg8b_double
-#define this_cpu_cmpxchg_double_4       percpu_cmpxchg8b_double
+#define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2)         percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
+#define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2)           percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
+#define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2)        percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
 #endif /* CONFIG_X86_CMPXCHG64 */
 
 /*
@@ -461,28 +495,44 @@ do {									\
 #define this_cpu_xchg_8(pcp, nval)      percpu_xchg_op(pcp, nval)
 #define this_cpu_cmpxchg_8(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 
+#define irqsafe_cpu_add_8(pcp, val)     percpu_add_op((pcp), val)
+#define irqsafe_cpu_and_8(pcp, val)     percpu_to_op("and", (pcp), val)
+#define irqsafe_cpu_or_8(pcp, val)      percpu_to_op("or", (pcp), val)
+#define irqsafe_cpu_xor_8(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xchg_8(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+
 /*
  * Pretty complex macro to generate cmpxchg16 instruction.  The instruction
  * is not supported on early AMD64 processors so we must be able to emulate
  * it in software.  The address used in the cmpxchg16 instruction must be
  * aligned to a 16 byte boundary.
  */
-#define percpu_cmpxchg16b_double(pcp1, pcp2, o1, o2, n1, n2)            \
+#ifdef CONFIG_SMP
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP3
+#else
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP2
+#endif
+#define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)                  \
 ({                                                                      \
-        bool __ret;                                                     \
-        typeof(pcp1) __o1 = (o1), __n1 = (n1);                          \
-        typeof(pcp2) __o2 = (o2), __n2 = (n2);                          \
-        alternative_io("leaq %P1,%%rsi\n\tcall this_cpu_cmpxchg16b_emu\n\t", \
-                       "cmpxchg16b " __percpu_arg(1) "\n\tsetz %0\n\t", \
+        char __ret;                                                     \
+        typeof(o1) __o1 = o1;                                           \
+        typeof(o1) __n1 = n1;                                           \
+        typeof(o2) __o2 = o2;                                           \
+        typeof(o2) __n2 = n2;                                           \
+        typeof(o2) __dummy;                                             \
+        alternative_io(CMPXCHG16B_EMU_CALL,                             \
+                       "cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t",  \
                        X86_FEATURE_CX16,                                \
-                       ASM_OUTPUT2("=a" (__ret), "+m" (pcp1),           \
-                                   "+m" (pcp2), "+d" (__o2)),           \
-                       "b" (__n1), "c" (__n2), "a" (__o1) : "rsi");     \
+                       ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)),         \
+                       "S" (&pcp1), "b"(__n1), "c"(__n2),               \
+                       "a"(__o1), "d"(__o2) : "memory");                \
         __ret;                                                          \
 })
 
-#define __this_cpu_cmpxchg_double_8     percpu_cmpxchg16b_double
-#define this_cpu_cmpxchg_double_8       percpu_cmpxchg16b_double
+#define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2)         percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
+#define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2)           percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
+#define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2)        percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
 
 #endif
 
@@ -501,11 +551,7 @@ static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr,
 {
         unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG;
 
-#ifdef CONFIG_X86_64
-        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_8(*a)) != 0;
-#else
-        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_4(*a)) != 0;
-#endif
+        return ((1UL << (nr % BITS_PER_LONG)) & percpu_read(*a)) != 0;
 }
 
 static inline int x86_this_cpu_variable_test_bit(int nr,
@@ -548,12 +594,6 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
                                 { [0 ... NR_CPUS-1] = _initvalue };     \
         __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
 
-#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue)      \
-        DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue;          \
-        __typeof__(_type) _name##_early_map[NR_CPUS] __initdata =       \
-                                { [0 ... NR_CPUS-1] = _initvalue };     \
-        __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
-
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
 
@@ -562,11 +602,6 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
         extern __typeof__(_type) *_name##_early_ptr;            \
         extern __typeof__(_type)  _name##_early_map[]
 
-#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name)         \
-        DECLARE_PER_CPU_READ_MOSTLY(_type, _name);              \
-        extern __typeof__(_type) *_name##_early_ptr;            \
-        extern __typeof__(_type)  _name##_early_map[]
-
 #define early_per_cpu_ptr(_name) (_name##_early_ptr)
 #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
 #define early_per_cpu(_name, _cpu)                              \
@@ -578,18 +613,12 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)          \
         DEFINE_PER_CPU(_type, _name) = _initvalue
 
-#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue)      \
-        DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue
-
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
 
 #define DECLARE_EARLY_PER_CPU(_type, _name)                     \
         DECLARE_PER_CPU(_type, _name)
 
-#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name)         \
-        DECLARE_PER_CPU_READ_MOSTLY(_type, _name)
-
 #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
 #define early_per_cpu_ptr(_name) NULL
 /* no early_per_cpu_map() */
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4fabcdf1cfa..094fb30817a 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -5,10 +5,11 @@
  * Performance event hw details:
  */
 
-#define INTEL_PMC_MAX_GENERIC                                  32
-#define INTEL_PMC_MAX_FIXED                                     3
-#define INTEL_PMC_IDX_FIXED                                    32
+#define X86_PMC_MAX_GENERIC                                    32
+#define X86_PMC_MAX_FIXED                                       3
 
+#define X86_PMC_IDX_GENERIC                                     0
+#define X86_PMC_IDX_FIXED                                      32
 #define X86_PMC_IDX_MAX                                        64
 
 #define MSR_ARCH_PERFMON_PERFCTR0                             0xc1
@@ -22,16 +23,12 @@
 #define ARCH_PERFMON_EVENTSEL_USR                       (1ULL << 16)
 #define ARCH_PERFMON_EVENTSEL_OS                        (1ULL << 17)
 #define ARCH_PERFMON_EVENTSEL_EDGE                      (1ULL << 18)
-#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL               (1ULL << 19)
 #define ARCH_PERFMON_EVENTSEL_INT                       (1ULL << 20)
 #define ARCH_PERFMON_EVENTSEL_ANY                       (1ULL << 21)
 #define ARCH_PERFMON_EVENTSEL_ENABLE                    (1ULL << 22)
 #define ARCH_PERFMON_EVENTSEL_INV                       (1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK                     0xFF000000ULL
 
-#define AMD_PERFMON_EVENTSEL_GUESTONLY                  (1ULL << 40)
-#define AMD_PERFMON_EVENTSEL_HOSTONLY                   (1ULL << 41)
-
 #define AMD64_EVENTSEL_EVENT    \
         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
 #define INTEL_ARCH_EVENT_MASK   \
@@ -46,17 +43,14 @@
 #define AMD64_RAW_EVENT_MASK            \
         (X86_RAW_EVENT_MASK          |  \
          AMD64_EVENTSEL_EVENT)
-#define AMD64_NUM_COUNTERS                              4
-#define AMD64_NUM_COUNTERS_CORE                         6
 
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL           0x3c
+#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                 0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
-#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX         0
+#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX                  0
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
                 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
 
-#define ARCH_PERFMON_BRANCH_MISSES_RETIRED              6
-#define ARCH_PERFMON_EVENTS_COUNT                       7
+#define ARCH_PERFMON_BRANCH_MISSES_RETIRED                       6
 
 /*
  * Intel "Architectural Performance Monitoring" CPUID
@@ -72,19 +66,6 @@ union cpuid10_eax {
         unsigned int full;
 };
 
-union cpuid10_ebx {
-        struct {
-                unsigned int no_unhalted_core_cycles:1;
-                unsigned int no_instructions_retired:1;
-                unsigned int no_unhalted_reference_cycles:1;
-                unsigned int no_llc_reference:1;
-                unsigned int no_llc_misses:1;
-                unsigned int no_branch_instruction_retired:1;
-                unsigned int no_branch_misses_retired:1;
-        } split;
-        unsigned int full;
-};
-
 union cpuid10_edx {
         struct {
                 unsigned int num_counters_fixed:5;
@@ -94,15 +75,6 @@ union cpuid10_edx {
         unsigned int full;
 };
 
-struct x86_pmu_capability {
-        int             version;
-        int             num_counters_gp;
-        int             num_counters_fixed;
-        int             bit_width_gp;
-        int             bit_width_fixed;
-        unsigned int    events_mask;
-        int             events_mask_len;
-};
 
 /*
  * Fixed-purpose performance events:
@@ -111,24 +83,23 @@ struct x86_pmu_capability {
 /*
  * All 3 fixed-mode PMCs are configured via this single MSR:
  */
-#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
+#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL                 0x38d
 
 /*
  * The counts are available in three separate MSRs:
  */
 
 /* Instr_Retired.Any: */
-#define MSR_ARCH_PERFMON_FIXED_CTR0     0x309
-#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS        (INTEL_PMC_IDX_FIXED + 0)
+#define MSR_ARCH_PERFMON_FIXED_CTR0                     0x309
+#define X86_PMC_IDX_FIXED_INSTRUCTIONS                  (X86_PMC_IDX_FIXED + 0)
 
 /* CPU_CLK_Unhalted.Core: */
-#define MSR_ARCH_PERFMON_FIXED_CTR1     0x30a
-#define INTEL_PMC_IDX_FIXED_CPU_CYCLES  (INTEL_PMC_IDX_FIXED + 1)
+#define MSR_ARCH_PERFMON_FIXED_CTR1                     0x30a
+#define X86_PMC_IDX_FIXED_CPU_CYCLES                    (X86_PMC_IDX_FIXED + 1)
 
 /* CPU_CLK_Unhalted.Ref: */
-#define MSR_ARCH_PERFMON_FIXED_CTR2     0x30b
-#define INTEL_PMC_IDX_FIXED_REF_CYCLES  (INTEL_PMC_IDX_FIXED + 2)
-#define INTEL_PMC_MSK_FIXED_REF_CYCLES  (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
+#define MSR_ARCH_PERFMON_FIXED_CTR2                     0x30b
+#define X86_PMC_IDX_FIXED_BUS_CYCLES                    (X86_PMC_IDX_FIXED + 2)
 
 /*
  * We model BTS tracing as another fixed-mode PMC.
@@ -137,75 +108,33 @@ struct x86_pmu_capability {
  * values are used by actual fixed events and higher values are used
  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
  */
-#define INTEL_PMC_IDX_FIXED_BTS                         (INTEL_PMC_IDX_FIXED + 16)
+#define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
 
-/*
- * IBS cpuid feature detection
- */
-
-#define IBS_CPUID_FEATURES              0x8000001b
-
-/*
- * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
- * bit 0 is used to indicate the existence of IBS.
- */
-#define IBS_CAPS_AVAIL                  (1U<<0)
-#define IBS_CAPS_FETCHSAM               (1U<<1)
-#define IBS_CAPS_OPSAM                  (1U<<2)
-#define IBS_CAPS_RDWROPCNT              (1U<<3)
-#define IBS_CAPS_OPCNT                  (1U<<4)
-#define IBS_CAPS_BRNTRGT                (1U<<5)
-#define IBS_CAPS_OPCNTEXT               (1U<<6)
-#define IBS_CAPS_RIPINVALIDCHK          (1U<<7)
-
-#define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
-                                         | IBS_CAPS_FETCHSAM    \
-                                         | IBS_CAPS_OPSAM)
-
-/*
- * IBS APIC setup
- */
-#define IBSCTL                          0x1cc
-#define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
-#define IBSCTL_LVT_OFFSET_MASK          0x0F
-
-/* ibs fetch bits/masks */
+/* IbsFetchCtl bits/masks */
 #define IBS_FETCH_RAND_EN       (1ULL<<57)
 #define IBS_FETCH_VAL           (1ULL<<49)
 #define IBS_FETCH_ENABLE        (1ULL<<48)
 #define IBS_FETCH_CNT           0xFFFF0000ULL
 #define IBS_FETCH_MAX_CNT       0x0000FFFFULL
 
-/* ibs op bits/masks */
-/* lower 4 bits of the current count are ignored: */
-#define IBS_OP_CUR_CNT          (0xFFFF0ULL<<32)
+/* IbsOpCtl bits */
 #define IBS_OP_CNT_CTL          (1ULL<<19)
 #define IBS_OP_VAL              (1ULL<<18)
 #define IBS_OP_ENABLE           (1ULL<<17)
 #define IBS_OP_MAX_CNT          0x0000FFFFULL
 #define IBS_OP_MAX_CNT_EXT      0x007FFFFFULL   /* not a register bit mask */
-#define IBS_RIP_INVALID         (1ULL<<38)
-
-#ifdef CONFIG_X86_LOCAL_APIC
-extern u32 get_ibs_caps(void);
-#else
-static inline u32 get_ibs_caps(void) { return 0; }
-#endif
 
 #ifdef CONFIG_PERF_EVENTS
 extern void perf_events_lapic_init(void);
 
+#define PERF_EVENT_INDEX_OFFSET                 0
+
 /*
- * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
- * unused and ABI specified to be 0, so nobody should care what we do with
- * them.
- *
- * EXACT - the IP points to the exact instruction that triggered the
- *         event (HW bugs exempt).
- * VM    - original X86_VM_MASK; see set_linear_ip().
+ * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
+ * This flag is otherwise unused and ABI specified to be 0, so nobody should
+ * care what we do with it.
  */
 #define PERF_EFLAGS_EXACT       (1UL << 3)
-#define PERF_EFLAGS_VM          (1UL << 5)
 
 struct pt_regs;
 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
@@ -230,38 +159,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
         );                                                      \
 }
 
-struct perf_guest_switch_msr {
-        unsigned msr;
-        u64 host, guest;
-};
-
-extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
-extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
-extern void perf_check_microcode(void);
 #else
-static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
-{
-        *nr = 0;
-        return NULL;
-}
-
-static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
-{
-        memset(cap, 0, sizeof(*cap));
-}
-
 static inline void perf_events_lapic_init(void) { }
-static inline void perf_check_microcode(void) { }
 #endif
 
-#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
- extern void amd_pmu_enable_virt(void);
- extern void amd_pmu_disable_virt(void);
-#else
- static inline void amd_pmu_enable_virt(void) { }
- static inline void amd_pmu_disable_virt(void) { }
-#endif
-
-#define arch_perf_out_copy_user copy_from_user_nmi
-
 #endif /* _ASM_X86_PERF_EVENT_H */
diff --git a/arch/x86/include/asm/pgtable-2level.h b/arch/x86/include/asm/pgtable-2level.h
index f2b489cf160..98391db840c 100644
--- a/arch/x86/include/asm/pgtable-2level.h
+++ b/arch/x86/include/asm/pgtable-2level.h
@@ -2,9 +2,9 @@
 #define _ASM_X86_PGTABLE_2LEVEL_H
 
 #define pte_ERROR(e) \
-        pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
 #define pgd_ERROR(e) \
-        pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
 /*
  * Certain architectures need to do special things when PTEs
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index 4cc9f2b7cdc..effff47a3c8 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -9,13 +9,13 @@
  */
 
 #define pte_ERROR(e)                                                    \
-        pr_err("%s:%d: bad pte %p(%08lx%08lx)\n",                       \
+        printk("%s:%d: bad pte %p(%08lx%08lx).\n",                      \
                __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
 #define pmd_ERROR(e)                                                    \
-        pr_err("%s:%d: bad pmd %p(%016Lx)\n",                           \
+        printk("%s:%d: bad pmd %p(%016Lx).\n",                          \
                __FILE__, __LINE__, &(e), pmd_val(e))
 #define pgd_ERROR(e)                                                    \
-        pr_err("%s:%d: bad pgd %p(%016Lx)\n",                           \
+        printk("%s:%d: bad pgd %p(%016Lx).\n",                          \
                __FILE__, __LINE__, &(e), pgd_val(e))
 
 /* Rules for using set_pte: the pte being assigned *must* be
@@ -31,60 +31,6 @@ static inline void native_set_pte(pte_t *ptep, pte_t pte)
         ptep->pte_low = pte.pte_low;
 }
 
-#define pmd_read_atomic pmd_read_atomic
-/*
- * pte_offset_map_lock on 32bit PAE kernels was reading the pmd_t with
- * a "*pmdp" dereference done by gcc. Problem is, in certain places
- * where pte_offset_map_lock is called, concurrent page faults are
- * allowed, if the mmap_sem is hold for reading. An example is mincore
- * vs page faults vs MADV_DONTNEED. On the page fault side
- * pmd_populate rightfully does a set_64bit, but if we're reading the
- * pmd_t with a "*pmdp" on the mincore side, a SMP race can happen
- * because gcc will not read the 64bit of the pmd atomically. To fix
- * this all places running pmd_offset_map_lock() while holding the
- * mmap_sem in read mode, shall read the pmdp pointer using this
- * function to know if the pmd is null nor not, and in turn to know if
- * they can run pmd_offset_map_lock or pmd_trans_huge or other pmd
- * operations.
- *
- * Without THP if the mmap_sem is hold for reading, the pmd can only
- * transition from null to not null while pmd_read_atomic runs. So
- * we can always return atomic pmd values with this function.
- *
- * With THP if the mmap_sem is hold for reading, the pmd can become
- * trans_huge or none or point to a pte (and in turn become "stable")
- * at any time under pmd_read_atomic. We could read it really
- * atomically here with a atomic64_read for the THP enabled case (and
- * it would be a whole lot simpler), but to avoid using cmpxchg8b we
- * only return an atomic pmdval if the low part of the pmdval is later
- * found stable (i.e. pointing to a pte). And we're returning a none
- * pmdval if the low part of the pmd is none. In some cases the high
- * and low part of the pmdval returned may not be consistent if THP is
- * enabled (the low part may point to previously mapped hugepage,
- * while the high part may point to a more recently mapped hugepage),
- * but pmd_none_or_trans_huge_or_clear_bad() only needs the low part
- * of the pmd to be read atomically to decide if the pmd is unstable
- * or not, with the only exception of when the low part of the pmd is
- * zero in which case we return a none pmd.
- */
-static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
-{
-        pmdval_t ret;
-        u32 *tmp = (u32 *)pmdp;
-
-        ret = (pmdval_t) (*tmp);
-        if (ret) {
-                /*
-                 * If the low part is null, we must not read the high part
-                 * or we can end up with a partial pmd.
-                 */
-                smp_rmb();
-                ret |= ((pmdval_t)*(tmp + 1)) << 32;
-        }
-
-        return (pmd_t) { ret };
-}
-
 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
 {
         set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 5199db2923d..18601c86fab 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -146,7 +146,8 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
 
 static inline int pmd_large(pmd_t pte)
 {
-        return pmd_flags(pte) & _PAGE_PSE;
+        return (pmd_flags(pte) & (_PAGE_PSE | _PAGE_PRESENT)) ==
+                (_PAGE_PSE | _PAGE_PRESENT);
 }
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
@@ -383,9 +384,9 @@ pte_t *populate_extra_pte(unsigned long vaddr);
 #endif  /* __ASSEMBLY__ */
 
 #ifdef CONFIG_X86_32
-# include <asm/pgtable_32.h>
+# include "pgtable_32.h"
 #else
-# include <asm/pgtable_64.h>
+# include "pgtable_64.h"
 #endif
 
 #ifndef __ASSEMBLY__
@@ -404,14 +405,7 @@ static inline int pte_same(pte_t a, pte_t b)
 
 static inline int pte_present(pte_t a)
 {
-        return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE |
-                               _PAGE_NUMA);
-}
-
-#define pte_accessible pte_accessible
-static inline int pte_accessible(pte_t a)
-{
-        return pte_flags(a) & _PAGE_PRESENT;
+        return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
 }
 
 static inline int pte_hidden(pte_t pte)
@@ -421,14 +415,7 @@ static inline int pte_hidden(pte_t pte)
 
 static inline int pmd_present(pmd_t pmd)
 {
-        /*
-         * Checking for _PAGE_PSE is needed too because
-         * split_huge_page will temporarily clear the present bit (but
-         * the _PAGE_PSE flag will remain set at all times while the
-         * _PAGE_PRESENT bit is clear).
-         */
-        return pmd_flags(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PSE |
-                                 _PAGE_NUMA);
+        return pmd_flags(pmd) & _PAGE_PRESENT;
 }
 
 static inline int pmd_none(pmd_t pmd)
@@ -487,11 +474,6 @@ static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
 
 static inline int pmd_bad(pmd_t pmd)
 {
-#ifdef CONFIG_NUMA_BALANCING
-        /* pmd_numa check */
-        if ((pmd_flags(pmd) & (_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA)
-                return 0;
-#endif
         return (pmd_flags(pmd) & ~_PAGE_USER) != _KERNPG_TABLE;
 }
 
@@ -721,7 +703,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm,
         pte_update(mm, addr, ptep);
 }
 
-#define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
+#define flush_tlb_fix_spurious_fault(vma, address)
 
 #define mk_pmd(page, pgprot)   pfn_pmd(page_to_pfn(page), (pgprot))
 
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index 8faa215a503..0c92113c4cb 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -71,7 +71,6 @@ do {						\
  * tables contain all the necessary information.
  */
 #define update_mmu_cache(vma, address, ptep) do { } while (0)
-#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 47356f9df82..975f709e09a 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -26,16 +26,16 @@ extern pgd_t init_level4_pgt[];
 extern void paging_init(void);
 
 #define pte_ERROR(e)                                    \
-        pr_err("%s:%d: bad pte %p(%016lx)\n",           \
+        printk("%s:%d: bad pte %p(%016lx).\n",          \
                __FILE__, __LINE__, &(e), pte_val(e))
 #define pmd_ERROR(e)                                    \
-        pr_err("%s:%d: bad pmd %p(%016lx)\n",           \
+        printk("%s:%d: bad pmd %p(%016lx).\n",          \
                __FILE__, __LINE__, &(e), pmd_val(e))
 #define pud_ERROR(e)                                    \
-        pr_err("%s:%d: bad pud %p(%016lx)\n",           \
+        printk("%s:%d: bad pud %p(%016lx).\n",          \
                __FILE__, __LINE__, &(e), pud_val(e))
 #define pgd_ERROR(e)                                    \
-        pr_err("%s:%d: bad pgd %p(%016lx)\n",           \
+        printk("%s:%d: bad pgd %p(%016lx).\n",          \
                __FILE__, __LINE__, &(e), pgd_val(e))
 
 struct mm_struct;
@@ -143,7 +143,6 @@ static inline int pgd_large(pgd_t pgd) { return 0; }
 #define pte_unmap(pte) ((void)(pte))/* NOP */
 
 #define update_mmu_cache(vma, address, ptep) do { } while (0)
-#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 
 /* Encode and de-code a swap entry */
 #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 3c32db8c539..013286a10c2 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -64,26 +64,6 @@
 #define _PAGE_FILE      (_AT(pteval_t, 1) << _PAGE_BIT_FILE)
 #define _PAGE_PROTNONE  (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
 
-/*
- * _PAGE_NUMA indicates that this page will trigger a numa hinting
- * minor page fault to gather numa placement statistics (see
- * pte_numa()). The bit picked (8) is within the range between
- * _PAGE_FILE (6) and _PAGE_PROTNONE (8) bits. Therefore, it doesn't
- * require changes to the swp entry format because that bit is always
- * zero when the pte is not present.
- *
- * The bit picked must be always zero when the pmd is present and not
- * present, so that we don't lose information when we set it while
- * atomically clearing the present bit.
- *
- * Because we shared the same bit (8) with _PAGE_PROTNONE this can be
- * interpreted as _PAGE_NUMA only in places that _PAGE_PROTNONE
- * couldn't reach, like handle_mm_fault() (see access_error in
- * arch/x86/mm/fault.c, the vma protection must not be PROT_NONE for
- * handle_mm_fault() to be invoked).
- */
-#define _PAGE_NUMA      _PAGE_PROTNONE
-
 #define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |        \
                          _PAGE_ACCESSED | _PAGE_DIRTY)
 #define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED |    \
@@ -194,9 +174,9 @@
 #endif
 
 #ifdef CONFIG_X86_32
-# include <asm/pgtable_32_types.h>
+# include "pgtable_32_types.h"
 #else
-# include <asm/pgtable_64_types.h>
+# include "pgtable_64_types.h"
 #endif
 
 #ifndef __ASSEMBLY__
@@ -323,9 +303,11 @@ void set_pte_vaddr(unsigned long vaddr, pte_t pte);
 
 extern void native_pagetable_reserve(u64 start, u64 end);
 #ifdef CONFIG_X86_32
-extern void native_pagetable_init(void);
+extern void native_pagetable_setup_start(pgd_t *base);
+extern void native_pagetable_setup_done(pgd_t *base);
 #else
-#define native_pagetable_init        paging_init
+#define native_pagetable_setup_start x86_init_pgd_noop
+#define native_pagetable_setup_done  x86_init_pgd_noop
 #endif
 
 struct seq_file;
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index f565f6dd59d..bb7133dc155 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -1,5 +1,13 @@
+#ifdef __KERNEL__
 # ifdef CONFIG_X86_32
-#  include <asm/posix_types_32.h>
+#  include "posix_types_32.h"
 # else
-#  include <asm/posix_types_64.h>
+#  include "posix_types_64.h"
 # endif
+#else
+# ifdef __i386__
+#  include "posix_types_32.h"
+# else
+#  include "posix_types_64.h"
+# endif
+#endif
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index 39fb618e221..2dddb317bb3 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -1,11 +1,102 @@
 #ifndef _ASM_X86_PROCESSOR_FLAGS_H
 #define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
 
-#include <uapi/asm/processor-flags.h>
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF   0x00000010 /* Auxiliary carry Flag */
+#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
 
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE      0x00000001 /* Protection Enable */
+#define X86_CR0_MP      0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM      0x00000004 /* Emulation */
+#define X86_CR0_TS      0x00000008 /* Task Switched */
+#define X86_CR0_ET      0x00000010 /* Extension Type */
+#define X86_CR0_NE      0x00000020 /* Numeric Error */
+#define X86_CR0_WP      0x00010000 /* Write Protect */
+#define X86_CR0_AM      0x00040000 /* Alignment Mask */
+#define X86_CR0_NW      0x20000000 /* Not Write-through */
+#define X86_CR0_CD      0x40000000 /* Cache Disable */
+#define X86_CR0_PG      0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT     0x00000008 /* Page Write Through */
+#define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME     0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI     0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD     0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE      0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE     0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE     0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE     0x00000040 /* Machine check enable */
+#define X86_CR4_PGE     0x00000080 /* enable global pages */
+#define X86_CR4_PCE     0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
+#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+#define X86_CR4_SMEP    0x00100000 /* enable SMEP support */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR     0x0000000F /* task priority register */
+
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+
+/*
+ *      NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0       0x20
+#define CX86_GCR        0xb8
+#define CX86_CCR0       0xc0
+#define CX86_CCR1       0xc1
+#define CX86_CCR2       0xc2
+#define CX86_CCR3       0xc3
+#define CX86_CCR4       0xe8
+#define CX86_CCR5       0xe9
+#define CX86_CCR6       0xea
+#define CX86_CCR7       0xeb
+#define CX86_PCR1       0xf0
+#define CX86_DIR0       0xfe
+#define CX86_DIR1       0xff
+#define CX86_ARR_BASE   0xc4
+#define CX86_RCR_BASE   0xdc
+
+#ifdef __KERNEL__
 #ifdef CONFIG_VM86
 #define X86_VM_MASK     X86_EFLAGS_VM
 #else
 #define X86_VM_MASK     0 /* No VM86 support */
 #endif
+#endif
+
 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 888184b2fc8..0d1171c9772 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -14,13 +14,13 @@ struct mm_struct;
 #include <asm/sigcontext.h>
 #include <asm/current.h>
 #include <asm/cpufeature.h>
+#include <asm/system.h>
 #include <asm/page.h>
 #include <asm/pgtable_types.h>
 #include <asm/percpu.h>
 #include <asm/msr.h>
 #include <asm/desc_defs.h>
 #include <asm/nops.h>
-#include <asm/special_insns.h>
 
 #include <linux/personality.h>
 #include <linux/cpumask.h>
@@ -29,15 +29,6 @@ struct mm_struct;
 #include <linux/math64.h>
 #include <linux/init.h>
 #include <linux/err.h>
-#include <linux/irqflags.h>
-
-/*
- * We handle most unaligned accesses in hardware.  On the other hand
- * unaligned DMA can be quite expensive on some Nehalem processors.
- *
- * Based on this we disable the IP header alignment in network drivers.
- */
-#define NET_IP_ALIGN    0
 
 #define HBP_NUM 4
 /*
@@ -61,19 +52,6 @@ static inline void *current_text_addr(void)
 # define ARCH_MIN_MMSTRUCT_ALIGN        0
 #endif
 
-enum tlb_infos {
-        ENTRIES,
-        NR_INFO
-};
-
-extern u16 __read_mostly tlb_lli_4k[NR_INFO];
-extern u16 __read_mostly tlb_lli_2m[NR_INFO];
-extern u16 __read_mostly tlb_lli_4m[NR_INFO];
-extern u16 __read_mostly tlb_lld_4k[NR_INFO];
-extern u16 __read_mostly tlb_lld_2m[NR_INFO];
-extern u16 __read_mostly tlb_lld_4m[NR_INFO];
-extern s8  __read_mostly tlb_flushall_shift;
-
 /*
  *  CPU type and hardware bug flags. Kept separately for each CPU.
  *  Members of this structure are referenced in head.S, so think twice
@@ -121,6 +99,7 @@ struct cpuinfo_x86 {
         u16                     apicid;
         u16                     initial_apicid;
         u16                     x86_clflush_size;
+#ifdef CONFIG_SMP
         /* number of cores as seen by the OS: */
         u16                     booted_cores;
         /* Physical processor id: */
@@ -131,7 +110,7 @@ struct cpuinfo_x86 {
         u8                      compute_unit_id;
         /* Index into per_cpu list: */
         u16                     cpu_index;
-        u32                     microcode;
+#endif
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 #define X86_VENDOR_INTEL        0
@@ -178,14 +157,15 @@ static inline int hlt_works(int cpu)
 
 extern void cpu_detect(struct cpuinfo_x86 *c);
 
+extern struct pt_regs *idle_regs(struct pt_regs *);
+
 extern void early_cpu_init(void);
 extern void identify_boot_cpu(void);
 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 extern void print_cpu_info(struct cpuinfo_x86 *);
-void print_cpu_msr(struct cpuinfo_x86 *);
 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
-extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
+extern unsigned short num_cache_leaves;
 
 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 extern void detect_ht(struct cpuinfo_x86 *c);
@@ -199,8 +179,7 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
               "=b" (*ebx),
               "=c" (*ecx),
               "=d" (*edx)
-            : "0" (*eax), "2" (*ecx)
-            : "memory");
+            : "0" (*eax), "2" (*ecx));
 }
 
 static inline void load_cr3(pgd_t *pgdir)
@@ -395,8 +374,6 @@ union thread_xstate {
 };
 
 struct fpu {
-        unsigned int last_cpu;
-        unsigned int has_fpu;
         union thread_xstate *state;
 };
 
@@ -421,6 +398,7 @@ DECLARE_INIT_PER_CPU(irq_stack_union);
 
 DECLARE_PER_CPU(char *, irq_stack_ptr);
 DECLARE_PER_CPU(unsigned int, irq_count);
+extern unsigned long kernel_eflags;
 extern asmlinkage void ignore_sysret(void);
 #else   /* X86_64 */
 #ifdef CONFIG_CC_STACKPROTECTOR
@@ -473,7 +451,7 @@ struct thread_struct {
         unsigned long           ptrace_dr7;
         /* Fault info: */
         unsigned long           cr2;
-        unsigned long           trap_nr;
+        unsigned long           trap_no;
         unsigned long           error_code;
         /* floating point and extended processor state */
         struct fpu              fpu;
@@ -494,6 +472,61 @@ struct thread_struct {
         unsigned                io_bitmap_max;
 };
 
+static inline unsigned long native_get_debugreg(int regno)
+{
+        unsigned long val = 0;  /* Damn you, gcc! */
+
+        switch (regno) {
+        case 0:
+                asm("mov %%db0, %0" :"=r" (val));
+                break;
+        case 1:
+                asm("mov %%db1, %0" :"=r" (val));
+                break;
+        case 2:
+                asm("mov %%db2, %0" :"=r" (val));
+                break;
+        case 3:
+                asm("mov %%db3, %0" :"=r" (val));
+                break;
+        case 6:
+                asm("mov %%db6, %0" :"=r" (val));
+                break;
+        case 7:
+                asm("mov %%db7, %0" :"=r" (val));
+                break;
+        default:
+                BUG();
+        }
+        return val;
+}
+
+static inline void native_set_debugreg(int regno, unsigned long value)
+{
+        switch (regno) {
+        case 0:
+                asm("mov %0, %%db0"     ::"r" (value));
+                break;
+        case 1:
+                asm("mov %0, %%db1"     ::"r" (value));
+                break;
+        case 2:
+                asm("mov %0, %%db2"     ::"r" (value));
+                break;
+        case 3:
+                asm("mov %0, %%db3"     ::"r" (value));
+                break;
+        case 6:
+                asm("mov %0, %%db6"     ::"r" (value));
+                break;
+        case 7:
+                asm("mov %0, %%db7"     ::"r" (value));
+                break;
+        default:
+                BUG();
+        }
+}
+
 /*
  * Set IOPL bits in EFLAGS from given mask
  */
@@ -539,6 +572,14 @@ static inline void native_swapgs(void)
 #define __cpuid                 native_cpuid
 #define paravirt_enabled()      0
 
+/*
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register)                             \
+        (var) = native_get_debugreg(register)
+#define set_debugreg(value, register)                           \
+        native_set_debugreg(register, value)
+
 static inline void load_sp0(struct tss_struct *tss,
                             struct thread_struct *thread)
 {
@@ -554,16 +595,13 @@ static inline void load_sp0(struct tss_struct *tss,
  * enable), so that any CPU's that boot up
  * after us can get the correct flags.
  */
-extern unsigned long mmu_cr4_features;
-extern u32 *trampoline_cr4_features;
+extern unsigned long            mmu_cr4_features;
 
 static inline void set_in_cr4(unsigned long mask)
 {
         unsigned long cr4;
 
         mmu_cr4_features |= mask;
-        if (trampoline_cr4_features)
-                *trampoline_cr4_features = mmu_cr4_features;
         cr4 = read_cr4();
         cr4 |= mask;
         write_cr4(cr4);
@@ -574,8 +612,6 @@ static inline void clear_in_cr4(unsigned long mask)
         unsigned long cr4;
 
         mmu_cr4_features &= ~mask;
-        if (trampoline_cr4_features)
-                *trampoline_cr4_features = mmu_cr4_features;
         cr4 = read_cr4();
         cr4 &= ~mask;
         write_cr4(cr4);
@@ -586,9 +622,17 @@ typedef struct {
 } mm_segment_t;
 
 
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
 /* Free all resources held by a thread. */
 extern void release_thread(struct task_struct *);
 
+/* Prepare to copy thread state - unlazy all lazy state */
+extern void prepare_to_copy(struct task_struct *tsk);
+
 unsigned long get_wchan(struct task_struct *p);
 
 /*
@@ -670,29 +714,18 @@ static inline void sync_core(void)
 {
         int tmp;
 
-#ifdef CONFIG_M486
-        /*
-         * Do a CPUID if available, otherwise do a jump.  The jump
-         * can conveniently enough be the jump around CPUID.
-         */
-        asm volatile("cmpl %2,%1\n\t"
-                     "jl 1f\n\t"
-                     "cpuid\n"
-                     "1:"
-                     : "=a" (tmp)
-                     : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
-                     : "ebx", "ecx", "edx", "memory");
-#else
-        /*
-         * CPUID is a barrier to speculative execution.
-         * Prefetched instructions are automatically
-         * invalidated when modified.
-         */
-        asm volatile("cpuid"
-                     : "=a" (tmp)
-                     : "0" (1)
-                     : "ebx", "ecx", "edx", "memory");
+#if defined(CONFIG_M386) || defined(CONFIG_M486)
+        if (boot_cpu_data.x86 < 5)
+                /* There is no speculative execution.
+                 * jmp is a barrier to prefetching. */
+                asm volatile("jmp 1f\n1:\n" ::: "memory");
+        else
 #endif
+                /* cpuid is a barrier to speculative execution.
+                 * Prefetched instructions are automatically
+                 * invalidated when modified. */
+                asm volatile("cpuid" : "=a" (tmp) : "0" (1)
+                             : "ebx", "ecx", "edx", "memory");
 }
 
 static inline void __monitor(const void *eax, unsigned long ecx,
@@ -762,8 +795,6 @@ static inline void update_debugctlmsr(unsigned long debugctlmsr)
         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 }
 
-extern void set_task_blockstep(struct task_struct *task, bool on);
-
 /*
  * from system description table in BIOS. Mostly for MCA use, but
  * others may find it useful:
@@ -893,9 +924,9 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
                                         0xc0000000 : 0xFFFFe000)
 
-#define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
+#define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
-#define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
+#define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 
 #define STACK_TOP               TASK_SIZE
@@ -917,12 +948,6 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
 
 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 extern unsigned long KSTK_ESP(struct task_struct *task);
-
-/*
- * User space RSP while inside the SYSCALL fast path
- */
-DECLARE_PER_CPU(unsigned long, old_rsp);
-
 #endif /* CONFIG_X86_64 */
 
 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
@@ -994,12 +1019,4 @@ extern bool cpu_has_amd_erratum(const int *);
 #define cpu_has_amd_erratum(x)  (false)
 #endif /* CONFIG_CPU_SUP_AMD */
 
-extern unsigned long arch_align_stack(unsigned long sp);
-extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
-
-void default_idle(void);
-bool set_pm_idle_to_default(void);
-
-void stop_this_cpu(void *dummy);
-
 #endif /* _ASM_X86_PROCESSOR_H */
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index 60bef663609..644dd885f05 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -21,6 +21,7 @@
 #include <asm/irq.h>
 #include <linux/atomic.h>
 #include <asm/setup.h>
+#include <asm/irq_controller.h>
 
 #ifdef CONFIG_OF
 extern int of_ioapic;
@@ -42,6 +43,15 @@ extern char cmd_line[COMMAND_LINE_SIZE];
 #define pci_address_to_pio pci_address_to_pio
 unsigned long pci_address_to_pio(phys_addr_t addr);
 
+/**
+ * irq_dispose_mapping - Unmap an interrupt
+ * @virq: linux virq number of the interrupt to unmap
+ *
+ * FIXME: We really should implement proper virq handling like power,
+ * but that's going to be major surgery.
+ */
+static inline void irq_dispose_mapping(unsigned int virq) { }
+
 #define HAVE_ARCH_DEVTREE_FIXUPS
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 942a08623a1..35664547125 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -1,12 +1,44 @@
 #ifndef _ASM_X86_PTRACE_H
 #define _ASM_X86_PTRACE_H
 
+#include <linux/compiler.h>     /* For __user */
+#include <asm/ptrace-abi.h>
+#include <asm/processor-flags.h>
+
+#ifdef __KERNEL__
 #include <asm/segment.h>
 #include <asm/page_types.h>
-#include <uapi/asm/ptrace.h>
+#endif
 
 #ifndef __ASSEMBLY__
+
 #ifdef __i386__
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#ifndef __KERNEL__
+
+struct pt_regs {
+        long ebx;
+        long ecx;
+        long edx;
+        long esi;
+        long edi;
+        long ebp;
+        long eax;
+        int  xds;
+        int  xes;
+        int  xfs;
+        int  xgs;
+        long orig_eax;
+        long eip;
+        int  xcs;
+        long eflags;
+        long esp;
+        int  xss;
+};
+
+#else /* __KERNEL__ */
 
 struct pt_regs {
         unsigned long bx;
@@ -28,8 +60,42 @@ struct pt_regs {
         unsigned long ss;
 };
 
+#endif /* __KERNEL__ */
+
 #else /* __i386__ */
 
+#ifndef __KERNEL__
+
+struct pt_regs {
+        unsigned long r15;
+        unsigned long r14;
+        unsigned long r13;
+        unsigned long r12;
+        unsigned long rbp;
+        unsigned long rbx;
+/* arguments: non interrupts/non tracing syscalls only save up to here*/
+        unsigned long r11;
+        unsigned long r10;
+        unsigned long r9;
+        unsigned long r8;
+        unsigned long rax;
+        unsigned long rcx;
+        unsigned long rdx;
+        unsigned long rsi;
+        unsigned long rdi;
+        unsigned long orig_rax;
+/* end of arguments */
+/* cpu exception frame or undefined */
+        unsigned long rip;
+        unsigned long cs;
+        unsigned long eflags;
+        unsigned long rsp;
+        unsigned long ss;
+/* top of stack page */
+};
+
+#else /* __KERNEL__ */
+
 struct pt_regs {
         unsigned long r15;
         unsigned long r14;
@@ -58,8 +124,12 @@ struct pt_regs {
 /* top of stack page */
 };
 
+#endif /* __KERNEL__ */
 #endif /* !__i386__ */
 
+
+#ifdef __KERNEL__
+
 #include <linux/init.h>
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt_types.h>
@@ -75,6 +145,7 @@ extern unsigned long
 convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs);
 extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
                          int error_code, int si_code);
+void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
 
 extern long syscall_trace_enter(struct pt_regs *);
 extern void syscall_trace_leave(struct pt_regs *);
@@ -133,23 +204,23 @@ static inline bool user_64bit_mode(struct pt_regs *regs)
         return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs;
 #endif
 }
-
-#define current_user_stack_pointer()    this_cpu_read(old_rsp)
-/* ia32 vs. x32 difference */
-#define compat_user_stack_pointer()     \
-        (test_thread_flag(TIF_IA32)     \
-         ? current_pt_regs()->sp        \
-         : this_cpu_read(old_rsp))
 #endif
 
-#ifdef CONFIG_X86_32
-extern unsigned long kernel_stack_pointer(struct pt_regs *regs);
-#else
+/*
+ * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode
+ * when it traps.  The previous stack will be directly underneath the saved
+ * registers, and 'sp/ss' won't even have been saved. Thus the '&regs->sp'.
+ *
+ * This is valid only for kernel mode traps.
+ */
 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 {
+#ifdef CONFIG_X86_32
+        return (unsigned long)(&regs->sp);
+#else
         return regs->sp;
-}
 #endif
+}
 
 #define GET_IP(regs) ((regs)->ip)
 #define GET_FP(regs) ((regs)->bp)
@@ -176,15 +247,6 @@ static inline unsigned long regs_get_register(struct pt_regs *regs,
 {
         if (unlikely(offset > MAX_REG_OFFSET))
                 return 0;
-#ifdef CONFIG_X86_32
-        /*
-         * Traps from the kernel do not save sp and ss.
-         * Use the helper function to retrieve sp.
-         */
-        if (offset == offsetof(struct pt_regs, sp) &&
-            regs->cs == __KERNEL_CS)
-                return kernel_stack_pointer(regs);
-#endif
         return *(unsigned long *)((unsigned long)regs + offset);
 }
 
@@ -238,5 +300,8 @@ extern int do_get_thread_area(struct task_struct *p, int idx,
 extern int do_set_thread_area(struct task_struct *p, int idx,
                               struct user_desc __user *info, int can_allocate);
 
+#endif /* __KERNEL__ */
+
 #endif /* !__ASSEMBLY__ */
+
 #endif /* _ASM_X86_PTRACE_H */
diff --git a/arch/x86/include/asm/pvclock-abi.h b/arch/x86/include/asm/pvclock-abi.h
index 6167fd79818..35f2d1948ad 100644
--- a/arch/x86/include/asm/pvclock-abi.h
+++ b/arch/x86/include/asm/pvclock-abi.h
@@ -40,6 +40,5 @@ struct pvclock_wall_clock {
 } __attribute__((__packed__));
 
 #define PVCLOCK_TSC_STABLE_BIT  (1 << 0)
-#define PVCLOCK_GUEST_STOPPED   (1 << 1)
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_X86_PVCLOCK_ABI_H */
diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h
index 109a9dd5d45..c59cc97fe6c 100644
--- a/arch/x86/include/asm/pvclock.h
+++ b/arch/x86/include/asm/pvclock.h
@@ -6,7 +6,6 @@
 
 /* some helper functions for xen and kvm pv clock sources */
 cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src);
-u8 pvclock_read_flags(struct pvclock_vcpu_time_info *src);
 void pvclock_set_flags(u8 flags);
 unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src);
 void pvclock_read_wallclock(struct pvclock_wall_clock *wall,
@@ -57,50 +56,4 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift)
         return product;
 }
 
-static __always_inline
-u64 pvclock_get_nsec_offset(const struct pvclock_vcpu_time_info *src)
-{
-        u64 delta = __native_read_tsc() - src->tsc_timestamp;
-        return pvclock_scale_delta(delta, src->tsc_to_system_mul,
-                                   src->tsc_shift);
-}
-
-static __always_inline
-unsigned __pvclock_read_cycles(const struct pvclock_vcpu_time_info *src,
-                               cycle_t *cycles, u8 *flags)
-{
-        unsigned version;
-        cycle_t ret, offset;
-        u8 ret_flags;
-
-        version = src->version;
-        /* Note: emulated platforms which do not advertise SSE2 support
-         * result in kvmclock not using the necessary RDTSC barriers.
-         * Without barriers, it is possible that RDTSC instruction reads from
-         * the time stamp counter outside rdtsc_barrier protected section
-         * below, resulting in violation of monotonicity.
-         */
-        rdtsc_barrier();
-        offset = pvclock_get_nsec_offset(src);
-        ret = src->system_time + offset;
-        ret_flags = src->flags;
-        rdtsc_barrier();
-
-        *cycles = ret;
-        *flags = ret_flags;
-        return version;
-}
-
-struct pvclock_vsyscall_time_info {
-        struct pvclock_vcpu_time_info pvti;
-        u32 migrate_count;
-} __attribute__((__aligned__(SMP_CACHE_BYTES)));
-
-#define PVTI_SIZE sizeof(struct pvclock_vsyscall_time_info)
-#define PVCLOCK_VSYSCALL_NR_PAGES (((NR_CPUS-1)/(PAGE_SIZE/PVTI_SIZE))+1)
-
-int __init pvclock_init_vsyscall(struct pvclock_vsyscall_time_info *i,
-                                 int size);
-struct pvclock_vcpu_time_info *pvclock_get_vsyscall_time_info(int cpu);
-
 #endif /* _ASM_X86_PVCLOCK_H */
diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h
deleted file mode 100644
index fe1ec5bcd84..00000000000
--- a/arch/x86/include/asm/realmode.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef _ARCH_X86_REALMODE_H
-#define _ARCH_X86_REALMODE_H
-
-#include <linux/types.h>
-#include <asm/io.h>
-
-/* This must match data at realmode.S */
-struct real_mode_header {
-        u32     text_start;
-        u32     ro_end;
-        /* SMP trampoline */
-        u32     trampoline_start;
-        u32     trampoline_status;
-        u32     trampoline_header;
-#ifdef CONFIG_X86_64
-        u32     trampoline_pgd;
-#endif
-        /* ACPI S3 wakeup */
-#ifdef CONFIG_ACPI_SLEEP
-        u32     wakeup_start;
-        u32     wakeup_header;
-#endif
-        /* APM/BIOS reboot */
-        u32     machine_real_restart_asm;
-#ifdef CONFIG_X86_64
-        u32     machine_real_restart_seg;
-#endif
-};
-
-/* This must match data at trampoline_32/64.S */
-struct trampoline_header {
-#ifdef CONFIG_X86_32
-        u32 start;
-        u16 gdt_pad;
-        u16 gdt_limit;
-        u32 gdt_base;
-#else
-        u64 start;
-        u64 efer;
-        u32 cr4;
-#endif
-};
-
-extern struct real_mode_header *real_mode_header;
-extern unsigned char real_mode_blob_end[];
-
-extern unsigned long init_rsp;
-extern unsigned long initial_code;
-extern unsigned long initial_gs;
-
-extern unsigned char real_mode_blob[];
-extern unsigned char real_mode_relocs[];
-
-#ifdef CONFIG_X86_32
-extern unsigned char startup_32_smp[];
-extern unsigned char boot_gdt[];
-#else
-extern unsigned char secondary_startup_64[];
-#endif
-
-extern void __init setup_real_mode(void);
-
-#endif /* _ARCH_X86_REALMODE_H */
diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h
index a82c4f1b4d8..3250e3d605d 100644
--- a/arch/x86/include/asm/reboot.h
+++ b/arch/x86/include/asm/reboot.h
@@ -18,12 +18,12 @@ extern struct machine_ops machine_ops;
 
 void native_machine_crash_shutdown(struct pt_regs *regs);
 void native_machine_shutdown(void);
-void __noreturn machine_real_restart(unsigned int type);
-/* These must match dispatch in arch/x86/realmore/rm/reboot.S */
+void machine_real_restart(unsigned int type);
+/* These must match dispatch_table in reboot_32.S */
 #define MRR_BIOS        0
 #define MRR_APM         1
 
-typedef void (*nmi_shootdown_cb)(int, struct pt_regs*);
+typedef void (*nmi_shootdown_cb)(int, struct die_args*);
 void nmi_shootdown_cpus(nmi_shootdown_cb callback);
 
 #endif /* _ASM_X86_REBOOT_H */
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index 2dbe4a721ce..df4cd32b4cc 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -204,7 +204,13 @@ static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
  */
 static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
 {
-        return delta + xadd(&sem->count, delta);
+        long tmp = delta;
+
+        asm volatile(LOCK_PREFIX "xadd %0,%1"
+                     : "+r" (tmp), "+m" (sem->count)
+                     : : "memory");
+
+        return tmp + delta;
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/x86/include/asm/seccomp.h b/arch/x86/include/asm/seccomp.h
index 0f3d7f09922..c62e58a5a90 100644
--- a/arch/x86/include/asm/seccomp.h
+++ b/arch/x86/include/asm/seccomp.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/seccomp_32.h>
+# include "seccomp_32.h"
 #else
-# include <asm/seccomp_64.h>
+# include "seccomp_64.h"
 #endif
diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h
index c48a95035a7..5e641715c3f 100644
--- a/arch/x86/include/asm/segment.h
+++ b/arch/x86/include/asm/segment.h
@@ -205,70 +205,14 @@
 
 #define IDT_ENTRIES 256
 #define NUM_EXCEPTION_VECTORS 32
-/* Bitmask of exception vectors which push an error code on the stack */
-#define EXCEPTION_ERRCODE_MASK  0x00027d00
 #define GDT_SIZE (GDT_ENTRIES * 8)
 #define GDT_ENTRY_TLS_ENTRIES 3
 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
-extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][2+2+5];
-
-/*
- * Load a segment. Fall back on loading the zero
- * segment if something goes wrong..
- */
-#define loadsegment(seg, value)                                         \
-do {                                                                    \
-        unsigned short __val = (value);                                 \
-                                                                        \
-        asm volatile("                                          \n"     \
-                     "1:        movl %k0,%%" #seg "             \n"     \
-                                                                        \
-                     ".section .fixup,\"ax\"                    \n"     \
-                     "2:        xorl %k0,%k0                    \n"     \
-                     "          jmp 1b                          \n"     \
-                     ".previous                                 \n"     \
-                                                                        \
-                     _ASM_EXTABLE(1b, 2b)                               \
-                                                                        \
-                     : "+r" (__val) : : "memory");                      \
-} while (0)
-
-/*
- * Save a segment register away
- */
-#define savesegment(seg, value)                         \
-        asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
-
-/*
- * x86_32 user gs accessors.
- */
-#ifdef CONFIG_X86_32
-#ifdef CONFIG_X86_32_LAZY_GS
-#define get_user_gs(regs)       (u16)({unsigned long v; savesegment(gs, v); v;})
-#define set_user_gs(regs, v)    loadsegment(gs, (unsigned long)(v))
-#define task_user_gs(tsk)       ((tsk)->thread.gs)
-#define lazy_save_gs(v)         savesegment(gs, (v))
-#define lazy_load_gs(v)         loadsegment(gs, (v))
-#else   /* X86_32_LAZY_GS */
-#define get_user_gs(regs)       (u16)((regs)->gs)
-#define set_user_gs(regs, v)    do { (regs)->gs = (v); } while (0)
-#define task_user_gs(tsk)       (task_pt_regs(tsk)->gs)
-#define lazy_save_gs(v)         do { } while (0)
-#define lazy_load_gs(v)         do { } while (0)
-#endif  /* X86_32_LAZY_GS */
-#endif  /* X86_32 */
-
-static inline unsigned long get_limit(unsigned long segment)
-{
-        unsigned long __limit;
-        asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
-        return __limit + 1;
-}
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __KERNEL__ */
+extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][10];
+#endif
+#endif
 
 #endif /* _ASM_X86_SEGMENT_H */
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index b7bf3505e1e..9756551ec76 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -1,8 +1,7 @@
 #ifndef _ASM_X86_SETUP_H
 #define _ASM_X86_SETUP_H
 
-#include <uapi/asm/setup.h>
-
+#ifdef __KERNEL__
 
 #define COMMAND_LINE_SIZE 2048
 
@@ -48,7 +47,7 @@ extern void reserve_standard_io_resources(void);
 extern void i386_reserve_resources(void);
 extern void setup_default_timer_irq(void);
 
-#ifdef CONFIG_X86_INTEL_MID
+#ifdef CONFIG_X86_MRST
 extern void x86_mrst_early_setup(void);
 #else
 static inline void x86_mrst_early_setup(void) { }
@@ -124,4 +123,6 @@ void __init x86_64_start_reservations(char *real_mode_data);
         .size .brk.name,.-1b;                           \
         .popsection
 #endif /* __ASSEMBLY__ */
+#endif  /*  __KERNEL__  */
+
 #endif /* _ASM_X86_SETUP_H */
diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h
index 9dfce4e0417..04459d25e66 100644
--- a/arch/x86/include/asm/sigcontext.h
+++ b/arch/x86/include/asm/sigcontext.h
@@ -1,9 +1,104 @@
 #ifndef _ASM_X86_SIGCONTEXT_H
 #define _ASM_X86_SIGCONTEXT_H
 
-#include <uapi/asm/sigcontext.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define FP_XSTATE_MAGIC1        0x46505853U
+#define FP_XSTATE_MAGIC2        0x46505845U
+#define FP_XSTATE_MAGIC2_SIZE   sizeof(FP_XSTATE_MAGIC2)
+
+/*
+ * bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame
+ * are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes
+ * are used to extended the fpstate pointer in the sigcontext, which now
+ * includes the extended state information along with fpstate information.
+ *
+ * Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved
+ * area and FP_XSTATE_MAGIC2 at the end of memory layout
+ * (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the
+ * extended state information in the memory layout pointed by the fpstate
+ * pointer in sigcontext.
+ */
+struct _fpx_sw_bytes {
+        __u32 magic1;           /* FP_XSTATE_MAGIC1 */
+        __u32 extended_size;    /* total size of the layout referred by
+                                 * fpstate pointer in the sigcontext.
+                                 */
+        __u64 xstate_bv;
+                                /* feature bit mask (including fp/sse/extended
+                                 * state) that is present in the memory
+                                 * layout.
+                                 */
+        __u32 xstate_size;      /* actual xsave state size, based on the
+                                 * features saved in the layout.
+                                 * 'extended_size' will be greater than
+                                 * 'xstate_size'.
+                                 */
+        __u32 padding[7];       /*  for future use. */
+};
 
 #ifdef __i386__
+/*
+ * As documented in the iBCS2 standard..
+ *
+ * The first part of "struct _fpstate" is just the normal i387
+ * hardware setup, the extra "status" word is used to save the
+ * coprocessor status word before entering the handler.
+ *
+ * Pentium III FXSR, SSE support
+ *      Gareth Hughes <gareth@valinux.com>, May 2000
+ *
+ * The FPU state data structure has had to grow to accommodate the
+ * extended FPU state required by the Streaming SIMD Extensions.
+ * There is no documented standard to accomplish this at the moment.
+ */
+struct _fpreg {
+        unsigned short significand[4];
+        unsigned short exponent;
+};
+
+struct _fpxreg {
+        unsigned short significand[4];
+        unsigned short exponent;
+        unsigned short padding[3];
+};
+
+struct _xmmreg {
+        unsigned long element[4];
+};
+
+struct _fpstate {
+        /* Regular FPU environment */
+        unsigned long   cw;
+        unsigned long   sw;
+        unsigned long   tag;
+        unsigned long   ipoff;
+        unsigned long   cssel;
+        unsigned long   dataoff;
+        unsigned long   datasel;
+        struct _fpreg   _st[8];
+        unsigned short  status;
+        unsigned short  magic;          /* 0xffff = regular FPU data only */
+
+        /* FXSR FPU environment */
+        unsigned long   _fxsr_env[6];   /* FXSR FPU env is ignored */
+        unsigned long   mxcsr;
+        unsigned long   reserved;
+        struct _fpxreg  _fxsr_st[8];    /* FXSR FPU reg data is ignored */
+        struct _xmmreg  _xmm[8];
+        unsigned long   padding1[44];
+
+        union {
+                unsigned long   padding2[12];
+                struct _fpx_sw_bytes sw_reserved; /* represents the extended
+                                                   * state info */
+        };
+};
+
+#define X86_FXSR_MAGIC          0x0000
+
+#ifdef __KERNEL__
 struct sigcontext {
         unsigned short gs, __gsh;
         unsigned short fs, __fsh;
@@ -36,7 +131,62 @@ struct sigcontext {
         unsigned long oldmask;
         unsigned long cr2;
 };
+#else /* __KERNEL__ */
+/*
+ * User-space might still rely on the old definition:
+ */
+struct sigcontext {
+        unsigned short gs, __gsh;
+        unsigned short fs, __fsh;
+        unsigned short es, __esh;
+        unsigned short ds, __dsh;
+        unsigned long edi;
+        unsigned long esi;
+        unsigned long ebp;
+        unsigned long esp;
+        unsigned long ebx;
+        unsigned long edx;
+        unsigned long ecx;
+        unsigned long eax;
+        unsigned long trapno;
+        unsigned long err;
+        unsigned long eip;
+        unsigned short cs, __csh;
+        unsigned long eflags;
+        unsigned long esp_at_signal;
+        unsigned short ss, __ssh;
+        struct _fpstate __user *fpstate;
+        unsigned long oldmask;
+        unsigned long cr2;
+};
+#endif /* !__KERNEL__ */
+
 #else /* __i386__ */
+
+/* FXSAVE frame */
+/* Note: reserved1/2 may someday contain valuable data. Always save/restore
+   them when you change signal frames. */
+struct _fpstate {
+        __u16   cwd;
+        __u16   swd;
+        __u16   twd;            /* Note this is not the same as the
+                                   32bit/x87/FSAVE twd */
+        __u16   fop;
+        __u64   rip;
+        __u64   rdp;
+        __u32   mxcsr;
+        __u32   mxcsr_mask;
+        __u32   st_space[32];   /* 8*16 bytes for each FP-reg */
+        __u32   xmm_space[64];  /* 16*16 bytes for each XMM-reg  */
+        __u32   reserved2[12];
+        union {
+                __u32   reserved3[12];
+                struct _fpx_sw_bytes sw_reserved; /* represents the extended
+                                                   * state information */
+        };
+};
+
+#ifdef __KERNEL__
 struct sigcontext {
         unsigned long r8;
         unsigned long r9;
@@ -75,5 +225,66 @@ struct sigcontext {
         void __user *fpstate;           /* zero when no FPU/extended context */
         unsigned long reserved1[8];
 };
+#else /* __KERNEL__ */
+/*
+ * User-space might still rely on the old definition:
+ */
+struct sigcontext {
+        unsigned long r8;
+        unsigned long r9;
+        unsigned long r10;
+        unsigned long r11;
+        unsigned long r12;
+        unsigned long r13;
+        unsigned long r14;
+        unsigned long r15;
+        unsigned long rdi;
+        unsigned long rsi;
+        unsigned long rbp;
+        unsigned long rbx;
+        unsigned long rdx;
+        unsigned long rax;
+        unsigned long rcx;
+        unsigned long rsp;
+        unsigned long rip;
+        unsigned long eflags;           /* RFLAGS */
+        unsigned short cs;
+        unsigned short gs;
+        unsigned short fs;
+        unsigned short __pad0;
+        unsigned long err;
+        unsigned long trapno;
+        unsigned long oldmask;
+        unsigned long cr2;
+        struct _fpstate __user *fpstate;        /* zero when no FPU context */
+        unsigned long reserved1[8];
+};
+#endif /* !__KERNEL__ */
+
 #endif /* !__i386__ */
+
+struct _xsave_hdr {
+        __u64 xstate_bv;
+        __u64 reserved1[2];
+        __u64 reserved2[5];
+};
+
+struct _ymmh_state {
+        /* 16 * 16 bytes for each YMMH-reg */
+        __u32 ymmh_space[64];
+};
+
+/*
+ * Extended state pointed by the fpstate pointer in the sigcontext.
+ * In addition to the fpstate, information encoded in the xstate_hdr
+ * indicates the presence of other extended state information
+ * supported by the processor and OS.
+ */
+struct _xstate {
+        struct _fpstate fpstate;
+        struct _xsave_hdr xstate_hdr;
+        struct _ymmh_state ymmh;
+        /* new processor state extensions go here */
+};
+
 #endif /* _ASM_X86_SIGCONTEXT_H */
diff --git a/arch/x86/include/asm/sigframe.h b/arch/x86/include/asm/sigframe.h
index 7c7c27c97da..4e0fe26d27d 100644
--- a/arch/x86/include/asm/sigframe.h
+++ b/arch/x86/include/asm/sigframe.h
@@ -59,25 +59,12 @@ struct rt_sigframe_ia32 {
 #endif /* defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) */
 
 #ifdef CONFIG_X86_64
-
 struct rt_sigframe {
         char __user *pretcode;
         struct ucontext uc;
         struct siginfo info;
         /* fp state follows here */
 };
-
-#ifdef CONFIG_X86_X32_ABI
-
-struct rt_sigframe_x32 {
-        u64 pretcode;
-        struct ucontext_x32 uc;
-        compat_siginfo_t info;
-        /* fp state follows here */
-};
-
-#endif /* CONFIG_X86_X32_ABI */
-
 #endif /* CONFIG_X86_64 */
 
 #endif /* _ASM_X86_SIGFRAME_H */
diff --git a/arch/x86/include/asm/sighandling.h b/arch/x86/include/asm/sighandling.h
deleted file mode 100644
index beff97f7df3..00000000000
--- a/arch/x86/include/asm/sighandling.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ASM_X86_SIGHANDLING_H
-#define _ASM_X86_SIGHANDLING_H
-
-#include <linux/compiler.h>
-#include <linux/ptrace.h>
-#include <linux/signal.h>
-
-#include <asm/processor-flags.h>
-
-#define __FIX_EFLAGS    (X86_EFLAGS_AC | X86_EFLAGS_OF | \
-                         X86_EFLAGS_DF | X86_EFLAGS_TF | X86_EFLAGS_SF | \
-                         X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \
-                         X86_EFLAGS_CF)
-
-void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
-
-int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
-                       unsigned long *pax);
-int setup_sigcontext(struct sigcontext __user *sc, void __user *fpstate,
-                     struct pt_regs *regs, unsigned long mask);
-
-#endif /* _ASM_X86_SIGHANDLING_H */
diff --git a/arch/x86/include/asm/signal.h b/arch/x86/include/asm/signal.h
index 216bf364a7e..598457cbd0f 100644
--- a/arch/x86/include/asm/signal.h
+++ b/arch/x86/include/asm/signal.h
@@ -2,6 +2,14 @@
 #define _ASM_X86_SIGNAL_H
 
 #ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/compiler.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+#ifdef __KERNEL__
 #include <linux/linkage.h>
 
 /* Most things should be clean enough to redefine this at will, if care
@@ -23,15 +31,102 @@ typedef struct {
         unsigned long sig[_NSIG_WORDS];
 } sigset_t;
 
-#ifndef CONFIG_COMPAT
-typedef sigset_t compat_sigset_t;
-#endif
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
 
+#endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
-#include <uapi/asm/signal.h>
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001u
+#define SA_NOCLDWAIT    0x00000002u
+#define SA_SIGINFO      0x00000004u
+#define SA_ONSTACK      0x08000000u
+#define SA_RESTART      0x10000000u
+#define SA_NODEFER      0x40000000u
+#define SA_RESETHAND    0x80000000u
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal-defs.h>
+
 #ifndef __ASSEMBLY__
+
+# ifdef __KERNEL__
 extern void do_notify_resume(struct pt_regs *, void *, __u32);
+# endif /* __KERNEL__ */
+
 #ifdef __i386__
+# ifdef __KERNEL__
 struct old_sigaction {
         __sighandler_t sa_handler;
         old_sigset_t sa_mask;
@@ -50,8 +145,45 @@ struct k_sigaction {
         struct sigaction sa;
 };
 
+# else /* __KERNEL__ */
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+# endif /* ! __KERNEL__ */
 #else /* __i386__ */
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
 #endif /* !__i386__ */
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
 #include <asm/sigcontext.h>
 
 #ifdef __i386__
@@ -124,5 +256,9 @@ struct pt_regs;
 
 #endif /* !__i386__ */
 
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_X86_SIGNAL_H */
diff --git a/arch/x86/include/asm/smap.h b/arch/x86/include/asm/smap.h
deleted file mode 100644
index 8d3120f4e27..00000000000
--- a/arch/x86/include/asm/smap.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Supervisor Mode Access Prevention support
- *
- * Copyright (C) 2012 Intel Corporation
- * Author: H. Peter Anvin <hpa@linux.intel.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2
- * of the License.
- */
-
-#ifndef _ASM_X86_SMAP_H
-#define _ASM_X86_SMAP_H
-
-#include <linux/stringify.h>
-#include <asm/nops.h>
-#include <asm/cpufeature.h>
-
-/* "Raw" instruction opcodes */
-#define __ASM_CLAC      .byte 0x0f,0x01,0xca
-#define __ASM_STAC      .byte 0x0f,0x01,0xcb
-
-#ifdef __ASSEMBLY__
-
-#include <asm/alternative-asm.h>
-
-#ifdef CONFIG_X86_SMAP
-
-#define ASM_CLAC                                                        \
-        661: ASM_NOP3 ;                                                 \
-        .pushsection .altinstr_replacement, "ax" ;                      \
-        662: __ASM_CLAC ;                                               \
-        .popsection ;                                                   \
-        .pushsection .altinstructions, "a" ;                            \
-        altinstruction_entry 661b, 662b, X86_FEATURE_SMAP, 3, 3 ;       \
-        .popsection
-
-#define ASM_STAC                                                        \
-        661: ASM_NOP3 ;                                                 \
-        .pushsection .altinstr_replacement, "ax" ;                      \
-        662: __ASM_STAC ;                                               \
-        .popsection ;                                                   \
-        .pushsection .altinstructions, "a" ;                            \
-        altinstruction_entry 661b, 662b, X86_FEATURE_SMAP, 3, 3 ;       \
-        .popsection
-
-#else /* CONFIG_X86_SMAP */
-
-#define ASM_CLAC
-#define ASM_STAC
-
-#endif /* CONFIG_X86_SMAP */
-
-#else /* __ASSEMBLY__ */
-
-#include <asm/alternative.h>
-
-#ifdef CONFIG_X86_SMAP
-
-static __always_inline void clac(void)
-{
-        /* Note: a barrier is implicit in alternative() */
-        alternative(ASM_NOP3, __stringify(__ASM_CLAC), X86_FEATURE_SMAP);
-}
-
-static __always_inline void stac(void)
-{
-        /* Note: a barrier is implicit in alternative() */
-        alternative(ASM_NOP3, __stringify(__ASM_STAC), X86_FEATURE_SMAP);
-}
-
-/* These macros can be used in asm() statements */
-#define ASM_CLAC \
-        ALTERNATIVE(ASM_NOP3, __stringify(__ASM_CLAC), X86_FEATURE_SMAP)
-#define ASM_STAC \
-        ALTERNATIVE(ASM_NOP3, __stringify(__ASM_STAC), X86_FEATURE_SMAP)
-
-#else /* CONFIG_X86_SMAP */
-
-static inline void clac(void) { }
-static inline void stac(void) { }
-
-#define ASM_CLAC
-#define ASM_STAC
-
-#endif /* CONFIG_X86_SMAP */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_X86_SMAP_H */
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index b073aaea747..73b11bc0ae6 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -31,12 +31,12 @@ static inline bool cpu_has_ht_siblings(void)
         return has_siblings;
 }
 
-DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
-DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
+DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
+DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
 /* cpus sharing the last level cache: */
-DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
-DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id);
-DECLARE_PER_CPU_READ_MOSTLY(int, cpu_number);
+DECLARE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
+DECLARE_PER_CPU(u16, cpu_llc_id);
+DECLARE_PER_CPU(int, cpu_number);
 
 static inline struct cpumask *cpu_sibling_mask(int cpu)
 {
@@ -53,17 +53,15 @@ static inline struct cpumask *cpu_llc_shared_mask(int cpu)
         return per_cpu(cpu_llc_shared_map, cpu);
 }
 
-DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid);
-DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
+DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
+DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
-DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid);
+DECLARE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid);
 #endif
 
 /* Static state in head.S used to set up a CPU */
 extern unsigned long stack_start; /* Initial stack pointer address */
 
-struct task_struct;
-
 struct smp_ops {
         void (*smp_prepare_boot_cpu)(void);
         void (*smp_prepare_cpus)(unsigned max_cpus);
@@ -72,7 +70,7 @@ struct smp_ops {
         void (*stop_other_cpus)(int wait);
         void (*smp_send_reschedule)(int cpu);
 
-        int (*cpu_up)(unsigned cpu, struct task_struct *tidle);
+        int (*cpu_up)(unsigned cpu);
         int (*cpu_disable)(void);
         void (*cpu_die)(unsigned int cpu);
         void (*play_dead)(void);
@@ -115,9 +113,9 @@ static inline void smp_cpus_done(unsigned int max_cpus)
         smp_ops.smp_cpus_done(max_cpus);
 }
 
-static inline int __cpu_up(unsigned int cpu, struct task_struct *tidle)
+static inline int __cpu_up(unsigned int cpu)
 {
-        return smp_ops.cpu_up(cpu, tidle);
+        return smp_ops.cpu_up(cpu);
 }
 
 static inline int __cpu_disable(void)
@@ -154,7 +152,7 @@ void cpu_disable_common(void);
 void native_smp_prepare_boot_cpu(void);
 void native_smp_prepare_cpus(unsigned int max_cpus);
 void native_smp_cpus_done(unsigned int max_cpus);
-int native_cpu_up(unsigned int cpunum, struct task_struct *tidle);
+int native_cpu_up(unsigned int cpunum);
 int native_cpu_disable(void);
 void native_cpu_die(unsigned int cpu);
 void native_play_dead(void);
@@ -164,12 +162,15 @@ int wbinvd_on_all_cpus(void);
 
 void native_send_call_func_ipi(const struct cpumask *mask);
 void native_send_call_func_single_ipi(int cpu);
-void x86_idle_thread_init(unsigned int cpu, struct task_struct *idle);
 
-void smp_store_boot_cpu_info(void);
 void smp_store_cpu_info(int id);
 #define cpu_physical_id(cpu)    per_cpu(x86_cpu_to_apicid, cpu)
 
+/* We don't mark CPUs online until __cpu_up(), so we need another measure */
+static inline int num_booting_cpus(void)
+{
+        return cpumask_weight(cpu_callout_mask);
+}
 #else /* !CONFIG_SMP */
 #define wbinvd_on_cpu(cpu)     wbinvd()
 static inline int wbinvd_on_all_cpus(void)
@@ -187,11 +188,11 @@ extern unsigned disabled_cpus __cpuinitdata;
  * from the initial startup. We map APIC_BASE very early in page_setup(),
  * so this is correct in the x86 case.
  */
-#define raw_smp_processor_id() (this_cpu_read(cpu_number))
+#define raw_smp_processor_id() (percpu_read(cpu_number))
 extern int safe_smp_processor_id(void);
 
 #elif defined(CONFIG_X86_64_SMP)
-#define raw_smp_processor_id() (this_cpu_read(cpu_number))
+#define raw_smp_processor_id() (percpu_read(cpu_number))
 
 #define stack_smp_processor_id()                                        \
 ({                                                              \
@@ -224,11 +225,5 @@ extern int hard_smp_processor_id(void);
 
 #endif /* CONFIG_X86_LOCAL_APIC */
 
-#ifdef CONFIG_DEBUG_NMI_SELFTEST
-extern void nmi_selftest(void);
-#else
-#define nmi_selftest() do { } while (0)
-#endif
-
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_X86_SMP_H */
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
deleted file mode 100644
index 41fc93a2e22..00000000000
--- a/arch/x86/include/asm/special_insns.h
+++ /dev/null
@@ -1,199 +0,0 @@
-#ifndef _ASM_X86_SPECIAL_INSNS_H
-#define _ASM_X86_SPECIAL_INSNS_H
-
-
-#ifdef __KERNEL__
-
-static inline void native_clts(void)
-{
-        asm volatile("clts");
-}
-
-/*
- * Volatile isn't enough to prevent the compiler from reordering the
- * read/write functions for the control registers and messing everything up.
- * A memory clobber would solve the problem, but would prevent reordering of
- * all loads stores around it, which can hurt performance. Solution is to
- * use a variable and mimic reads and writes to it to enforce serialization
- */
-static unsigned long __force_order;
-
-static inline unsigned long native_read_cr0(void)
-{
-        unsigned long val;
-        asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
-        return val;
-}
-
-static inline void native_write_cr0(unsigned long val)
-{
-        asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr2(void)
-{
-        unsigned long val;
-        asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
-        return val;
-}
-
-static inline void native_write_cr2(unsigned long val)
-{
-        asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr3(void)
-{
-        unsigned long val;
-        asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
-        return val;
-}
-
-static inline void native_write_cr3(unsigned long val)
-{
-        asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
-}
-
-static inline unsigned long native_read_cr4(void)
-{
-        unsigned long val;
-        asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
-        return val;
-}
-
-static inline unsigned long native_read_cr4_safe(void)
-{
-        unsigned long val;
-        /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
-         * exists, so it will never fail. */
-#ifdef CONFIG_X86_32
-        asm volatile("1: mov %%cr4, %0\n"
-                     "2:\n"
-                     _ASM_EXTABLE(1b, 2b)
-                     : "=r" (val), "=m" (__force_order) : "0" (0));
-#else
-        val = native_read_cr4();
-#endif
-        return val;
-}
-
-static inline void native_write_cr4(unsigned long val)
-{
-        asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
-}
-
-#ifdef CONFIG_X86_64
-static inline unsigned long native_read_cr8(void)
-{
-        unsigned long cr8;
-        asm volatile("movq %%cr8,%0" : "=r" (cr8));
-        return cr8;
-}
-
-static inline void native_write_cr8(unsigned long val)
-{
-        asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
-}
-#endif
-
-static inline void native_wbinvd(void)
-{
-        asm volatile("wbinvd": : :"memory");
-}
-
-extern void native_load_gs_index(unsigned);
-
-#ifdef CONFIG_PARAVIRT
-#include <asm/paravirt.h>
-#else
-
-static inline unsigned long read_cr0(void)
-{
-        return native_read_cr0();
-}
-
-static inline void write_cr0(unsigned long x)
-{
-        native_write_cr0(x);
-}
-
-static inline unsigned long read_cr2(void)
-{
-        return native_read_cr2();
-}
-
-static inline void write_cr2(unsigned long x)
-{
-        native_write_cr2(x);
-}
-
-static inline unsigned long read_cr3(void)
-{
-        return native_read_cr3();
-}
-
-static inline void write_cr3(unsigned long x)
-{
-        native_write_cr3(x);
-}
-
-static inline unsigned long read_cr4(void)
-{
-        return native_read_cr4();
-}
-
-static inline unsigned long read_cr4_safe(void)
-{
-        return native_read_cr4_safe();
-}
-
-static inline void write_cr4(unsigned long x)
-{
-        native_write_cr4(x);
-}
-
-static inline void wbinvd(void)
-{
-        native_wbinvd();
-}
-
-#ifdef CONFIG_X86_64
-
-static inline unsigned long read_cr8(void)
-{
-        return native_read_cr8();
-}
-
-static inline void write_cr8(unsigned long x)
-{
-        native_write_cr8(x);
-}
-
-static inline void load_gs_index(unsigned selector)
-{
-        native_load_gs_index(selector);
-}
-
-#endif
-
-/* Clear the 'TS' bit */
-static inline void clts(void)
-{
-        native_clts();
-}
-
-#endif/* CONFIG_PARAVIRT */
-
-#define stts() write_cr0(read_cr0() | X86_CR0_TS)
-
-static inline void clflush(volatile void *__p)
-{
-        asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
-}
-
-#define nop() asm volatile ("nop")
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_X86_SPECIAL_INSNS_H */
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 33692eaabab..ee67edf86fd 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -12,15 +12,18 @@
  * Simple spin lock operations.  There are two variants, one clears IRQ's
  * on the local processor, one does not.
  *
- * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
+ * These are fair FIFO ticket locks, which are currently limited to 256
+ * CPUs.
  *
  * (the type definitions are in asm/spinlock_types.h)
  */
 
 #ifdef CONFIG_X86_32
 # define LOCK_PTR_REG "a"
+# define REG_PTR_MODE "k"
 #else
 # define LOCK_PTR_REG "D"
+# define REG_PTR_MODE "q"
 #endif
 
 #if defined(CONFIG_X86_32) && \
@@ -46,53 +49,126 @@
  * issues and should be optimal for the uncontended case. Note the tail must be
  * in the high part, because a wide xadd increment of the low part would carry
  * up and contaminate the high part.
+ *
+ * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
+ * save some instructions and make the code more elegant. There really isn't
+ * much between them in performance though, especially as locks are out of line.
  */
+#if (NR_CPUS < 256)
+#define TICKET_SHIFT 8
+
 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
 {
-        register struct __raw_tickets inc = { .tail = 1 };
-
-        inc = xadd(&lock->tickets, inc);
-
-        for (;;) {
-                if (inc.head == inc.tail)
-                        break;
-                cpu_relax();
-                inc.head = ACCESS_ONCE(lock->tickets.head);
-        }
-        barrier();              /* make sure nothing creeps before the lock is taken */
+        short inc = 0x0100;
+
+        asm volatile (
+                LOCK_PREFIX "xaddw %w0, %1\n"
+                "1:\t"
+                "cmpb %h0, %b0\n\t"
+                "je 2f\n\t"
+                "rep ; nop\n\t"
+                "movb %1, %b0\n\t"
+                /* don't need lfence here, because loads are in-order */
+                "jmp 1b\n"
+                "2:"
+                : "+Q" (inc), "+m" (lock->slock)
+                :
+                : "memory", "cc");
 }
 
 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
 {
-        arch_spinlock_t old, new;
+        int tmp, new;
+
+        asm volatile("movzwl %2, %0\n\t"
+                     "cmpb %h0,%b0\n\t"
+                     "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
+                     "jne 1f\n\t"
+                     LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
+                     "1:"
+                     "sete %b1\n\t"
+                     "movzbl %b1,%0\n\t"
+                     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
+                     :
+                     : "memory", "cc");
+
+        return tmp;
+}
 
-        old.tickets = ACCESS_ONCE(lock->tickets);
-        if (old.tickets.head != old.tickets.tail)
-                return 0;
+static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
+{
+        asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
+                     : "+m" (lock->slock)
+                     :
+                     : "memory", "cc");
+}
+#else
+#define TICKET_SHIFT 16
 
-        new.head_tail = old.head_tail + (1 << TICKET_SHIFT);
+static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
+{
+        int inc = 0x00010000;
+        int tmp;
+
+        asm volatile(LOCK_PREFIX "xaddl %0, %1\n"
+                     "movzwl %w0, %2\n\t"
+                     "shrl $16, %0\n\t"
+                     "1:\t"
+                     "cmpl %0, %2\n\t"
+                     "je 2f\n\t"
+                     "rep ; nop\n\t"
+                     "movzwl %1, %2\n\t"
+                     /* don't need lfence here, because loads are in-order */
+                     "jmp 1b\n"
+                     "2:"
+                     : "+r" (inc), "+m" (lock->slock), "=&r" (tmp)
+                     :
+                     : "memory", "cc");
+}
 
-        /* cmpxchg is a full barrier, so nothing can move before it */
-        return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
+static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
+{
+        int tmp;
+        int new;
+
+        asm volatile("movl %2,%0\n\t"
+                     "movl %0,%1\n\t"
+                     "roll $16, %0\n\t"
+                     "cmpl %0,%1\n\t"
+                     "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
+                     "jne 1f\n\t"
+                     LOCK_PREFIX "cmpxchgl %1,%2\n\t"
+                     "1:"
+                     "sete %b1\n\t"
+                     "movzbl %b1,%0\n\t"
+                     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
+                     :
+                     : "memory", "cc");
+
+        return tmp;
 }
 
 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
-        __add(&lock->tickets.head, 1, UNLOCK_LOCK_PREFIX);
+        asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
+                     : "+m" (lock->slock)
+                     :
+                     : "memory", "cc");
 }
+#endif
 
 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
 {
-        struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
+        int tmp = ACCESS_ONCE(lock->slock);
 
-        return tmp.tail != tmp.head;
+        return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
 }
 
 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
 {
-        struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
+        int tmp = ACCESS_ONCE(lock->slock);
 
-        return (__ticket_t)(tmp.tail - tmp.head) > 1;
+        return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1;
 }
 
 #ifndef CONFIG_PARAVIRT_SPINLOCKS
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index ad0ad07fc00..7c7a486fcb6 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -5,28 +5,11 @@
 # error "please don't include this file directly"
 #endif
 
-#include <linux/types.h>
-
-#if (CONFIG_NR_CPUS < 256)
-typedef u8  __ticket_t;
-typedef u16 __ticketpair_t;
-#else
-typedef u16 __ticket_t;
-typedef u32 __ticketpair_t;
-#endif
-
-#define TICKET_SHIFT    (sizeof(__ticket_t) * 8)
-
 typedef struct arch_spinlock {
-        union {
-                __ticketpair_t head_tail;
-                struct __raw_tickets {
-                        __ticket_t head, tail;
-                } tickets;
-        };
+        unsigned int slock;
 } arch_spinlock_t;
 
-#define __ARCH_SPIN_LOCK_UNLOCKED       { { 0 } }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 #include <asm/rwlock.h>
 
diff --git a/arch/x86/include/asm/sta2x11.h b/arch/x86/include/asm/sta2x11.h
deleted file mode 100644
index e9d32df89cc..00000000000
--- a/arch/x86/include/asm/sta2x11.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Header file for STMicroelectronics ConneXt (STA2X11) IOHub
- */
-#ifndef __ASM_STA2X11_H
-#define __ASM_STA2X11_H
-
-#include <linux/pci.h>
-
-/* This needs to be called from the MFD to configure its sub-devices */
-struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev);
-
-#endif /* __ASM_STA2X11_H */
diff --git a/arch/x86/include/asm/stackprotector.h b/arch/x86/include/asm/stackprotector.h
index 6a998598f17..15751776356 100644
--- a/arch/x86/include/asm/stackprotector.h
+++ b/arch/x86/include/asm/stackprotector.h
@@ -38,6 +38,7 @@
 #include <asm/tsc.h>
 #include <asm/processor.h>
 #include <asm/percpu.h>
+#include <asm/system.h>
 #include <asm/desc.h>
 #include <linux/random.h>
 
@@ -75,9 +76,9 @@ static __always_inline void boot_init_stack_canary(void)
 
         current->stack_canary = canary;
 #ifdef CONFIG_X86_64
-        this_cpu_write(irq_stack_union.stack_canary, canary);
+        percpu_write(irq_stack_union.stack_canary, canary);
 #else
-        this_cpu_write(stack_canary.canary, canary);
+        percpu_write(stack_canary.canary, canary);
 #endif
 }
 
diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h
index 09224d7a586..6dfd6d9373a 100644
--- a/arch/x86/include/asm/string.h
+++ b/arch/x86/include/asm/string.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/string_32.h>
+# include "string_32.h"
 #else
-# include <asm/string_64.h>
+# include "string_64.h"
 #endif
diff --git a/arch/x86/include/asm/suspend.h b/arch/x86/include/asm/suspend.h
index 2fab6c2c357..9bd521fe457 100644
--- a/arch/x86/include/asm/suspend.h
+++ b/arch/x86/include/asm/suspend.h
@@ -1,5 +1,5 @@
 #ifdef CONFIG_X86_32
-# include <asm/suspend_32.h>
+# include "suspend_32.h"
 #else
-# include <asm/suspend_64.h>
+# include "suspend_64.h"
 #endif
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 6136d99f537..f2b83bc7d78 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -1,9 +1,6 @@
 #ifndef __SVM_H
 #define __SVM_H
 
-#include <uapi/asm/svm.h>
-
-
 enum {
         INTERCEPT_INTR,
         INTERCEPT_NMI,
@@ -267,6 +264,81 @@ struct __attribute__ ((__packed__)) vmcb {
 
 #define SVM_EXITINFO_REG_MASK 0x0F
 
+#define SVM_EXIT_READ_CR0       0x000
+#define SVM_EXIT_READ_CR3       0x003
+#define SVM_EXIT_READ_CR4       0x004
+#define SVM_EXIT_READ_CR8       0x008
+#define SVM_EXIT_WRITE_CR0      0x010
+#define SVM_EXIT_WRITE_CR3      0x013
+#define SVM_EXIT_WRITE_CR4      0x014
+#define SVM_EXIT_WRITE_CR8      0x018
+#define SVM_EXIT_READ_DR0       0x020
+#define SVM_EXIT_READ_DR1       0x021
+#define SVM_EXIT_READ_DR2       0x022
+#define SVM_EXIT_READ_DR3       0x023
+#define SVM_EXIT_READ_DR4       0x024
+#define SVM_EXIT_READ_DR5       0x025
+#define SVM_EXIT_READ_DR6       0x026
+#define SVM_EXIT_READ_DR7       0x027
+#define SVM_EXIT_WRITE_DR0      0x030
+#define SVM_EXIT_WRITE_DR1      0x031
+#define SVM_EXIT_WRITE_DR2      0x032
+#define SVM_EXIT_WRITE_DR3      0x033
+#define SVM_EXIT_WRITE_DR4      0x034
+#define SVM_EXIT_WRITE_DR5      0x035
+#define SVM_EXIT_WRITE_DR6      0x036
+#define SVM_EXIT_WRITE_DR7      0x037
+#define SVM_EXIT_EXCP_BASE      0x040
+#define SVM_EXIT_INTR           0x060
+#define SVM_EXIT_NMI            0x061
+#define SVM_EXIT_SMI            0x062
+#define SVM_EXIT_INIT           0x063
+#define SVM_EXIT_VINTR          0x064
+#define SVM_EXIT_CR0_SEL_WRITE  0x065
+#define SVM_EXIT_IDTR_READ      0x066
+#define SVM_EXIT_GDTR_READ      0x067
+#define SVM_EXIT_LDTR_READ      0x068
+#define SVM_EXIT_TR_READ        0x069
+#define SVM_EXIT_IDTR_WRITE     0x06a
+#define SVM_EXIT_GDTR_WRITE     0x06b
+#define SVM_EXIT_LDTR_WRITE     0x06c
+#define SVM_EXIT_TR_WRITE       0x06d
+#define SVM_EXIT_RDTSC          0x06e
+#define SVM_EXIT_RDPMC          0x06f
+#define SVM_EXIT_PUSHF          0x070
+#define SVM_EXIT_POPF           0x071
+#define SVM_EXIT_CPUID          0x072
+#define SVM_EXIT_RSM            0x073
+#define SVM_EXIT_IRET           0x074
+#define SVM_EXIT_SWINT          0x075
+#define SVM_EXIT_INVD           0x076
+#define SVM_EXIT_PAUSE          0x077
+#define SVM_EXIT_HLT            0x078
+#define SVM_EXIT_INVLPG         0x079
+#define SVM_EXIT_INVLPGA        0x07a
+#define SVM_EXIT_IOIO           0x07b
+#define SVM_EXIT_MSR            0x07c
+#define SVM_EXIT_TASK_SWITCH    0x07d
+#define SVM_EXIT_FERR_FREEZE    0x07e
+#define SVM_EXIT_SHUTDOWN       0x07f
+#define SVM_EXIT_VMRUN          0x080
+#define SVM_EXIT_VMMCALL        0x081
+#define SVM_EXIT_VMLOAD         0x082
+#define SVM_EXIT_VMSAVE         0x083
+#define SVM_EXIT_STGI           0x084
+#define SVM_EXIT_CLGI           0x085
+#define SVM_EXIT_SKINIT         0x086
+#define SVM_EXIT_RDTSCP         0x087
+#define SVM_EXIT_ICEBP          0x088
+#define SVM_EXIT_WBINVD         0x089
+#define SVM_EXIT_MONITOR        0x08a
+#define SVM_EXIT_MWAIT          0x08b
+#define SVM_EXIT_MWAIT_COND     0x08c
+#define SVM_EXIT_XSETBV         0x08d
+#define SVM_EXIT_NPF            0x400
+
+#define SVM_EXIT_ERR            -1
+
 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
 
 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
@@ -277,3 +349,4 @@ struct __attribute__ ((__packed__)) vmcb {
 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
 
 #endif
+
diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h
deleted file mode 100644
index 4ec45b3abba..00000000000
--- a/arch/x86/include/asm/switch_to.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef _ASM_X86_SWITCH_TO_H
-#define _ASM_X86_SWITCH_TO_H
-
-struct task_struct; /* one of the stranger aspects of C forward declarations */
-struct task_struct *__switch_to(struct task_struct *prev,
-                                struct task_struct *next);
-struct tss_struct;
-void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
-                      struct tss_struct *tss);
-
-#ifdef CONFIG_X86_32
-
-#ifdef CONFIG_CC_STACKPROTECTOR
-#define __switch_canary                                                 \
-        "movl %P[task_canary](%[next]), %%ebx\n\t"                      \
-        "movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
-#define __switch_canary_oparam                                          \
-        , [stack_canary] "=m" (stack_canary.canary)
-#define __switch_canary_iparam                                          \
-        , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
-#else   /* CC_STACKPROTECTOR */
-#define __switch_canary
-#define __switch_canary_oparam
-#define __switch_canary_iparam
-#endif  /* CC_STACKPROTECTOR */
-
-/*
- * Saving eflags is important. It switches not only IOPL between tasks,
- * it also protects other tasks from NT leaking through sysenter etc.
- */
-#define switch_to(prev, next, last)                                     \
-do {                                                                    \
-        /*                                                              \
-         * Context-switching clobbers all registers, so we clobber      \
-         * them explicitly, via unused output variables.                \
-         * (EAX and EBP is not listed because EBP is saved/restored     \
-         * explicitly for wchan access and EAX is the return value of   \
-         * __switch_to())                                               \
-         */                                                             \
-        unsigned long ebx, ecx, edx, esi, edi;                          \
-                                                                        \
-        asm volatile("pushfl\n\t"               /* save    flags */     \
-                     "pushl %%ebp\n\t"          /* save    EBP   */     \
-                     "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
-                     "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
-                     "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
-                     "pushl %[next_ip]\n\t"     /* restore EIP   */     \
-                     __switch_canary                                    \
-                     "jmp __switch_to\n"        /* regparm call  */     \
-                     "1:\t"                                             \
-                     "popl %%ebp\n\t"           /* restore EBP   */     \
-                     "popfl\n"                  /* restore flags */     \
-                                                                        \
-                     /* output parameters */                            \
-                     : [prev_sp] "=m" (prev->thread.sp),                \
-                       [prev_ip] "=m" (prev->thread.ip),                \
-                       "=a" (last),                                     \
-                                                                        \
-                       /* clobbered output registers: */                \
-                       "=b" (ebx), "=c" (ecx), "=d" (edx),              \
-                       "=S" (esi), "=D" (edi)                           \
-                                                                        \
-                       __switch_canary_oparam                           \
-                                                                        \
-                       /* input parameters: */                          \
-                     : [next_sp]  "m" (next->thread.sp),                \
-                       [next_ip]  "m" (next->thread.ip),                \
-                                                                        \
-                       /* regparm parameters for __switch_to(): */      \
-                       [prev]     "a" (prev),                           \
-                       [next]     "d" (next)                            \
-                                                                        \
-                       __switch_canary_iparam                           \
-                                                                        \
-                     : /* reloaded segment registers */                 \
-                        "memory");                                      \
-} while (0)
-
-#else /* CONFIG_X86_32 */
-
-/* frame pointer must be last for get_wchan */
-#define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
-#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
-
-#define __EXTRA_CLOBBER  \
-        , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
-          "r12", "r13", "r14", "r15"
-
-#ifdef CONFIG_CC_STACKPROTECTOR
-#define __switch_canary                                                   \
-        "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
-        "movq %%r8,"__percpu_arg([gs_canary])"\n\t"
-#define __switch_canary_oparam                                            \
-        , [gs_canary] "=m" (irq_stack_union.stack_canary)
-#define __switch_canary_iparam                                            \
-        , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
-#else   /* CC_STACKPROTECTOR */
-#define __switch_canary
-#define __switch_canary_oparam
-#define __switch_canary_iparam
-#endif  /* CC_STACKPROTECTOR */
-
-/* Save restore flags to clear handle leaking NT */
-#define switch_to(prev, next, last) \
-        asm volatile(SAVE_CONTEXT                                         \
-             "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
-             "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
-             "call __switch_to\n\t"                                       \
-             "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
-             __switch_canary                                              \
-             "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
-             "movq %%rax,%%rdi\n\t"                                       \
-             "testl  %[_tif_fork],%P[ti_flags](%%r8)\n\t"                 \
-             "jnz   ret_from_fork\n\t"                                    \
-             RESTORE_CONTEXT                                              \
-             : "=a" (last)                                                \
-               __switch_canary_oparam                                     \
-             : [next] "S" (next), [prev] "D" (prev),                      \
-               [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
-               [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
-               [_tif_fork] "i" (_TIF_FORK),                               \
-               [thread_info] "i" (offsetof(struct task_struct, stack)),   \
-               [current_task] "m" (current_task)                          \
-               __switch_canary_iparam                                     \
-             : "memory", "cc" __EXTRA_CLOBBER)
-
-#endif /* CONFIG_X86_32 */
-
-#endif /* _ASM_X86_SWITCH_TO_H */
diff --git a/arch/x86/include/asm/sys_ia32.h b/arch/x86/include/asm/sys_ia32.h
index 31f61f96e0f..cb238526a9f 100644
--- a/arch/x86/include/asm/sys_ia32.h
+++ b/arch/x86/include/asm/sys_ia32.h
@@ -10,8 +10,6 @@
 #ifndef _ASM_X86_SYS_IA32_H
 #define _ASM_X86_SYS_IA32_H
 
-#ifdef CONFIG_COMPAT
-
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
@@ -38,9 +36,11 @@ asmlinkage long sys32_rt_sigaction(int, struct sigaction32 __user *,
                                    struct sigaction32 __user *, unsigned int);
 asmlinkage long sys32_sigaction(int, struct old_sigaction32 __user *,
                                 struct old_sigaction32 __user *);
+asmlinkage long sys32_rt_sigprocmask(int, compat_sigset_t __user *,
+                                     compat_sigset_t __user *, unsigned int);
 asmlinkage long sys32_alarm(unsigned int);
 
-asmlinkage long sys32_waitpid(compat_pid_t, unsigned int __user *, int);
+asmlinkage long sys32_waitpid(compat_pid_t, unsigned int *, int);
 asmlinkage long sys32_sysfs(int, u32, u32);
 
 asmlinkage long sys32_sched_rr_get_interval(compat_pid_t,
@@ -54,6 +54,10 @@ asmlinkage long sys32_pwrite(unsigned int, const char __user *, u32, u32, u32);
 asmlinkage long sys32_personality(unsigned long);
 asmlinkage long sys32_sendfile(int, int, compat_off_t __user *, s32);
 
+asmlinkage long sys32_execve(const char __user *, compat_uptr_t __user *,
+                             compat_uptr_t __user *, struct pt_regs *);
+asmlinkage long sys32_clone(unsigned int, unsigned int, struct pt_regs *);
+
 long sys32_lseek(unsigned int, int, unsigned int);
 long sys32_kill(int, int);
 long sys32_fadvise64_64(int, __u32, __u32, __u32, __u32, int);
@@ -69,6 +73,8 @@ asmlinkage long sys32_fallocate(int, int, unsigned,
 
 /* ia32/ia32_signal.c */
 asmlinkage long sys32_sigsuspend(int, int, old_sigset_t);
+asmlinkage long sys32_sigaltstack(const stack_ia32_t __user *,
+                                  stack_ia32_t __user *, struct pt_regs *);
 asmlinkage long sys32_sigreturn(struct pt_regs *);
 asmlinkage long sys32_rt_sigreturn(struct pt_regs *);
 
@@ -77,7 +83,4 @@ asmlinkage long sys32_ipc(u32, int, int, int, compat_uptr_t, u32);
 
 asmlinkage long sys32_fanotify_mark(int, unsigned int, u32, u32, int,
                                     const char __user *);
-
-#endif /* CONFIG_COMPAT */
-
 #endif /* _ASM_X86_SYS_IA32_H */
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 1ace47b6259..c4a348f7bd4 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -13,12 +13,8 @@
 #ifndef _ASM_X86_SYSCALL_H
 #define _ASM_X86_SYSCALL_H
 
-#include <linux/audit.h>
 #include <linux/sched.h>
 #include <linux/err.h>
-#include <asm/asm-offsets.h>    /* For NR_syscalls */
-#include <asm/thread_info.h>    /* for TS_COMPAT */
-#include <asm/unistd.h>
 
 extern const unsigned long sys_call_table[];
 
@@ -29,13 +25,13 @@ extern const unsigned long sys_call_table[];
  */
 static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
-        return regs->orig_ax & __SYSCALL_MASK;
+        return regs->orig_ax;
 }
 
 static inline void syscall_rollback(struct task_struct *task,
                                     struct pt_regs *regs)
 {
-        regs->ax = regs->orig_ax & __SYSCALL_MASK;
+        regs->ax = regs->orig_ax;
 }
 
 static inline long syscall_get_error(struct task_struct *task,
@@ -90,12 +86,6 @@ static inline void syscall_set_arguments(struct task_struct *task,
         memcpy(&regs->bx + i, args, n * sizeof(args[0]));
 }
 
-static inline int syscall_get_arch(struct task_struct *task,
-                                   struct pt_regs *regs)
-{
-        return AUDIT_ARCH_I386;
-}
-
 #else    /* CONFIG_X86_64 */
 
 static inline void syscall_get_arguments(struct task_struct *task,
@@ -220,25 +210,6 @@ static inline void syscall_set_arguments(struct task_struct *task,
                 }
 }
 
-static inline int syscall_get_arch(struct task_struct *task,
-                                   struct pt_regs *regs)
-{
-#ifdef CONFIG_IA32_EMULATION
-        /*
-         * TS_COMPAT is set for 32-bit syscall entry and then
-         * remains set until we return to user mode.
-         *
-         * TIF_IA32 tasks should always have TS_COMPAT set at
-         * system call time.
-         *
-         * x32 tasks should be considered AUDIT_ARCH_X86_64.
-         */
-        if (task_thread_info(task)->status & TS_COMPAT)
-                return AUDIT_ARCH_I386;
-#endif
-        /* Both x32 and x86_64 are considered "64-bit". */
-        return AUDIT_ARCH_X86_64;
-}
 #endif  /* CONFIG_X86_32 */
 
 #endif  /* _ASM_X86_SYSCALL_H */
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h
index 58b7e3eac0a..f1d8b441fc7 100644
--- a/arch/x86/include/asm/syscalls.h
+++ b/arch/x86/include/asm/syscalls.h
@@ -20,11 +20,23 @@
 asmlinkage long sys_ioperm(unsigned long, unsigned long, int);
 long sys_iopl(unsigned int, struct pt_regs *);
 
+/* kernel/process.c */
+int sys_fork(struct pt_regs *);
+int sys_vfork(struct pt_regs *);
+long sys_execve(const char __user *,
+                const char __user *const __user *,
+                const char __user *const __user *, struct pt_regs *);
+long sys_clone(unsigned long, unsigned long, void __user *,
+               void __user *, struct pt_regs *);
+
 /* kernel/ldt.c */
 asmlinkage int sys_modify_ldt(int, void __user *, unsigned long);
 
 /* kernel/signal.c */
 long sys_rt_sigreturn(struct pt_regs *);
+long sys_sigaltstack(const stack_t __user *, stack_t __user *,
+                     struct pt_regs *);
+
 
 /* kernel/tls.c */
 asmlinkage int sys_set_thread_area(struct user_desc __user *);
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 2d946e63ee8..a1fe5c127b5 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -40,8 +40,7 @@ struct thread_info {
                                                 */
         __u8                    supervisor_stack[0];
 #endif
-        unsigned int            sig_on_uaccess_error:1;
-        unsigned int            uaccess_err:1;  /* uaccess failed */
+        int                     uaccess_err;
 };
 
 #define INIT_THREAD_INFO(tsk)                   \
@@ -79,60 +78,55 @@ struct thread_info {
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_SINGLESTEP          4       /* reenable singlestep on user return*/
+#define TIF_IRET                5       /* force IRET */
 #define TIF_SYSCALL_EMU         6       /* syscall emulation active */
 #define TIF_SYSCALL_AUDIT       7       /* syscall auditing active */
 #define TIF_SECCOMP             8       /* secure computing */
 #define TIF_MCE_NOTIFY          10      /* notify userspace of an MCE */
 #define TIF_USER_RETURN_NOTIFY  11      /* notify kernel of userspace return */
-#define TIF_UPROBE              12      /* breakpointed or singlestepping */
 #define TIF_NOTSC               16      /* TSC is not accessible in userland */
-#define TIF_IA32                17      /* IA32 compatibility process */
+#define TIF_IA32                17      /* 32bit process */
 #define TIF_FORK                18      /* ret_from_fork */
-#define TIF_NOHZ                19      /* in adaptive nohz mode */
 #define TIF_MEMDIE              20      /* is terminating due to OOM killer */
 #define TIF_DEBUG               21      /* uses debug registers */
 #define TIF_IO_BITMAP           22      /* uses I/O bitmap */
+#define TIF_FREEZE              23      /* is freezing for suspend */
 #define TIF_FORCED_TF           24      /* true if TF in eflags artificially */
 #define TIF_BLOCKSTEP           25      /* set when we want DEBUGCTLMSR_BTF */
 #define TIF_LAZY_MMU_UPDATES    27      /* task is updating the mmu lazily */
 #define TIF_SYSCALL_TRACEPOINT  28      /* syscall tracepoint instrumentation */
-#define TIF_ADDR32              29      /* 32-bit address space on 64 bits */
-#define TIF_X32                 30      /* 32-bit native x86-64 binary */
 
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_IRET               (1 << TIF_IRET)
 #define _TIF_SYSCALL_EMU        (1 << TIF_SYSCALL_EMU)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
 #define _TIF_MCE_NOTIFY         (1 << TIF_MCE_NOTIFY)
 #define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
-#define _TIF_UPROBE             (1 << TIF_UPROBE)
 #define _TIF_NOTSC              (1 << TIF_NOTSC)
 #define _TIF_IA32               (1 << TIF_IA32)
 #define _TIF_FORK               (1 << TIF_FORK)
-#define _TIF_NOHZ               (1 << TIF_NOHZ)
 #define _TIF_DEBUG              (1 << TIF_DEBUG)
 #define _TIF_IO_BITMAP          (1 << TIF_IO_BITMAP)
+#define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_FORCED_TF          (1 << TIF_FORCED_TF)
 #define _TIF_BLOCKSTEP          (1 << TIF_BLOCKSTEP)
 #define _TIF_LAZY_MMU_UPDATES   (1 << TIF_LAZY_MMU_UPDATES)
 #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
-#define _TIF_ADDR32             (1 << TIF_ADDR32)
-#define _TIF_X32                (1 << TIF_X32)
 
 /* work to do in syscall_trace_enter() */
 #define _TIF_WORK_SYSCALL_ENTRY \
         (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_EMU | _TIF_SYSCALL_AUDIT |   \
-         _TIF_SECCOMP | _TIF_SINGLESTEP | _TIF_SYSCALL_TRACEPOINT |     \
-         _TIF_NOHZ)
+         _TIF_SECCOMP | _TIF_SINGLESTEP | _TIF_SYSCALL_TRACEPOINT)
 
 /* work to do in syscall_trace_leave() */
 #define _TIF_WORK_SYSCALL_EXIT  \
         (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP |    \
-         _TIF_SYSCALL_TRACEPOINT | _TIF_NOHZ)
+         _TIF_SYSCALL_TRACEPOINT)
 
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK                                                  \
@@ -142,8 +136,7 @@ struct thread_info {
 
 /* work to do on any return to user space */
 #define _TIF_ALLWORK_MASK                                               \
-        ((0x0000FFFF & ~_TIF_SECCOMP) | _TIF_SYSCALL_TRACEPOINT |       \
-        _TIF_NOHZ)
+        ((0x0000FFFF & ~_TIF_SECCOMP) | _TIF_SYSCALL_TRACEPOINT)
 
 /* Only used for 64 bit */
 #define _TIF_DO_NOTIFY_MASK                                             \
@@ -159,6 +152,24 @@ struct thread_info {
 
 #define PREEMPT_ACTIVE          0x10000000
 
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
+#else
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
+#endif
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#define alloc_thread_info_node(tsk, node)                               \
+({                                                                      \
+        struct page *page = alloc_pages_node(node, THREAD_FLAGS,        \
+                                             THREAD_ORDER);             \
+        struct thread_info *ret = page ? page_address(page) : NULL;     \
+                                                                        \
+        ret;                                                            \
+})
+
 #ifdef CONFIG_X86_32
 
 #define STACK_WARN      (THREAD_SIZE/8)
@@ -208,7 +219,7 @@ DECLARE_PER_CPU(unsigned long, kernel_stack);
 static inline struct thread_info *current_thread_info(void)
 {
         struct thread_info *ti;
-        ti = (void *)(this_cpu_read_stable(kernel_stack) +
+        ti = (void *)(percpu_read_stable(kernel_stack) +
                       KERNEL_STACK_OFFSET - THREAD_SIZE);
         return ti;
 }
@@ -220,12 +231,6 @@ static inline struct thread_info *current_thread_info(void)
         movq PER_CPU_VAR(kernel_stack),reg ; \
         subq $(THREAD_SIZE-KERNEL_STACK_OFFSET),reg
 
-/*
- * Same if PER_CPU_VAR(kernel_stack) is, perhaps with some offset, already in
- * a certain register (to be used in assembler memory operands).
- */
-#define THREAD_INFO(reg, off) KERNEL_STACK_OFFSET+(off)-THREAD_SIZE(reg)
-
 #endif
 
 #endif /* !X86_32 */
@@ -237,6 +242,8 @@ static inline struct thread_info *current_thread_info(void)
  * ever touches our thread-synchronous status, so we don't
  * have to worry about atomic accesses.
  */
+#define TS_USEDFPU              0x0001  /* FPU was used by this task
+                                           this quantum (SMP) */
 #define TS_COMPAT               0x0002  /* 32bit syscall active (64BIT)*/
 #define TS_POLLING              0x0004  /* idle task polling need_resched,
                                            skip sending interrupt */
@@ -250,41 +257,14 @@ static inline void set_restore_sigmask(void)
 {
         struct thread_info *ti = current_thread_info();
         ti->status |= TS_RESTORE_SIGMASK;
-        WARN_ON(!test_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags));
-}
-static inline void clear_restore_sigmask(void)
-{
-        current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-}
-static inline bool test_restore_sigmask(void)
-{
-        return current_thread_info()->status & TS_RESTORE_SIGMASK;
-}
-static inline bool test_and_clear_restore_sigmask(void)
-{
-        struct thread_info *ti = current_thread_info();
-        if (!(ti->status & TS_RESTORE_SIGMASK))
-                return false;
-        ti->status &= ~TS_RESTORE_SIGMASK;
-        return true;
-}
-
-static inline bool is_ia32_task(void)
-{
-#ifdef CONFIG_X86_32
-        return true;
-#endif
-#ifdef CONFIG_IA32_EMULATION
-        if (current_thread_info()->status & TS_COMPAT)
-                return true;
-#endif
-        return false;
+        set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags);
 }
 #endif  /* !__ASSEMBLY__ */
 
 #ifndef __ASSEMBLY__
 extern void arch_task_cache_init(void);
+extern void free_thread_info(struct thread_info *ti);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
-extern void arch_release_task_struct(struct task_struct *tsk);
+#define arch_task_cache_init arch_task_cache_init
 #endif
 #endif /* _ASM_X86_THREAD_INFO_H */
diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h
index 34baa0eb5d0..431793e5d48 100644
--- a/arch/x86/include/asm/timer.h
+++ b/arch/x86/include/asm/timer.h
@@ -57,10 +57,14 @@ DECLARE_PER_CPU(unsigned long long, cyc2ns_offset);
 
 static inline unsigned long long __cycles_2_ns(unsigned long long cyc)
 {
+        unsigned long long quot;
+        unsigned long long rem;
         int cpu = smp_processor_id();
         unsigned long long ns = per_cpu(cyc2ns_offset, cpu);
-        ns += mult_frac(cyc, per_cpu(cyc2ns, cpu),
-                        (1UL << CYC2NS_SCALE_FACTOR));
+        quot = (cyc >> CYC2NS_SCALE_FACTOR);
+        rem = cyc & ((1ULL << CYC2NS_SCALE_FACTOR) - 1);
+        ns += quot * per_cpu(cyc2ns, cpu) +
+                ((rem * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR);
         return ns;
 }
 
diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h
index 4fef20773b8..829215fef9e 100644
--- a/arch/x86/include/asm/tlb.h
+++ b/arch/x86/include/asm/tlb.h
@@ -4,14 +4,7 @@
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma) do { } while (0)
 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-#define tlb_flush(tlb)                                                  \
-{                                                                       \
-        if (tlb->fullmm == 0)                                           \
-                flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, 0UL); \
-        else                                                            \
-                flush_tlb_mm_range(tlb->mm, 0UL, TLB_FLUSH_ALL, 0UL);   \
-}
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
 
 #include <asm-generic/tlb.h>
 
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 0fee48e279c..169be8938b9 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -5,7 +5,7 @@
 #include <linux/sched.h>
 
 #include <asm/processor.h>
-#include <asm/special_insns.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
@@ -56,10 +56,17 @@ static inline void __flush_tlb_all(void)
 
 static inline void __flush_tlb_one(unsigned long addr)
 {
+        if (cpu_has_invlpg)
                 __flush_tlb_single(addr);
+        else
+                __flush_tlb();
 }
 
-#define TLB_FLUSH_ALL   -1UL
+#ifdef CONFIG_X86_32
+# define TLB_FLUSH_ALL  0xffffffff
+#else
+# define TLB_FLUSH_ALL  -1ULL
+#endif
 
 /*
  * TLB flushing:
@@ -70,10 +77,14 @@ static inline void __flush_tlb_one(unsigned long addr)
  *  - flush_tlb_page(vma, vmaddr) flushes one page
  *  - flush_tlb_range(vma, start, end) flushes a range of pages
  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- *  - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
+ *  - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
  *
  * ..but the i386 has somewhat limited tlb flushing capabilities,
  * and page-granular flushes are available only on i486 and up.
+ *
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
  */
 
 #ifndef CONFIG_SMP
@@ -102,17 +113,9 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
                 __flush_tlb();
 }
 
-static inline void flush_tlb_mm_range(struct mm_struct *mm,
-           unsigned long start, unsigned long end, unsigned long vmflag)
-{
-        if (mm == current->active_mm)
-                __flush_tlb();
-}
-
 static inline void native_flush_tlb_others(const struct cpumask *cpumask,
                                            struct mm_struct *mm,
-                                           unsigned long start,
-                                           unsigned long end)
+                                           unsigned long va)
 {
 }
 
@@ -120,35 +123,27 @@ static inline void reset_lazy_tlbstate(void)
 {
 }
 
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                          unsigned long end)
-{
-        flush_tlb_all();
-}
-
 #else  /* SMP */
 
 #include <asm/smp.h>
 
 #define local_flush_tlb() __flush_tlb()
 
-#define flush_tlb_mm(mm)        flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
-
-#define flush_tlb_range(vma, start, end)        \
-                flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
-
 extern void flush_tlb_all(void);
 extern void flush_tlb_current_task(void);
+extern void flush_tlb_mm(struct mm_struct *);
 extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
-                                unsigned long end, unsigned long vmflag);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 
 #define flush_tlb()     flush_tlb_current_task()
 
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                   unsigned long start, unsigned long end)
+{
+        flush_tlb_mm(vma->vm_mm);
+}
+
 void native_flush_tlb_others(const struct cpumask *cpumask,
-                                struct mm_struct *mm,
-                                unsigned long start, unsigned long end);
+                             struct mm_struct *mm, unsigned long va);
 
 #define TLBSTATE_OK     1
 #define TLBSTATE_LAZY   2
@@ -161,15 +156,20 @@ DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
 
 static inline void reset_lazy_tlbstate(void)
 {
-        this_cpu_write(cpu_tlbstate.state, 0);
-        this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
+        percpu_write(cpu_tlbstate.state, 0);
+        percpu_write(cpu_tlbstate.active_mm, &init_mm);
 }
 
 #endif  /* SMP */
 
 #ifndef CONFIG_PARAVIRT
-#define flush_tlb_others(mask, mm, start, end)  \
-        native_flush_tlb_others(mask, mm, start, end)
+#define flush_tlb_others(mask, mm, va)  native_flush_tlb_others(mask, mm, va)
 #endif
 
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        flush_tlb_all();
+}
+
 #endif /* _ASM_X86_TLBFLUSH_H */
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 095b21507b6..c00692476e9 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -92,8 +92,48 @@ extern void setup_node_to_cpumask_map(void);
 
 #define pcibus_to_node(bus) __pcibus_to_node(bus)
 
+#ifdef CONFIG_X86_32
+# define SD_CACHE_NICE_TRIES    1
+# define SD_IDLE_IDX            1
+#else
+# define SD_CACHE_NICE_TRIES    2
+# define SD_IDLE_IDX            2
+#endif
+
+/* sched_domains SD_NODE_INIT for NUMA machines */
+#define SD_NODE_INIT (struct sched_domain) {                            \
+        .min_interval           = 8,                                    \
+        .max_interval           = 32,                                   \
+        .busy_factor            = 32,                                   \
+        .imbalance_pct          = 125,                                  \
+        .cache_nice_tries       = SD_CACHE_NICE_TRIES,                  \
+        .busy_idx               = 3,                                    \
+        .idle_idx               = SD_IDLE_IDX,                          \
+        .newidle_idx            = 0,                                    \
+        .wake_idx               = 0,                                    \
+        .forkexec_idx           = 0,                                    \
+                                                                        \
+        .flags                  = 1*SD_LOAD_BALANCE                     \
+                                | 1*SD_BALANCE_NEWIDLE                  \
+                                | 1*SD_BALANCE_EXEC                     \
+                                | 1*SD_BALANCE_FORK                     \
+                                | 0*SD_BALANCE_WAKE                     \
+                                | 1*SD_WAKE_AFFINE                      \
+                                | 0*SD_PREFER_LOCAL                     \
+                                | 0*SD_SHARE_CPUPOWER                   \
+                                | 0*SD_POWERSAVINGS_BALANCE             \
+                                | 0*SD_SHARE_PKG_RESOURCES              \
+                                | 1*SD_SERIALIZE                        \
+                                | 0*SD_PREFER_SIBLING                   \
+                                ,                                       \
+        .last_balance           = jiffies,                              \
+        .balance_interval       = 1,                                    \
+}
+
+#ifdef CONFIG_X86_64
 extern int __node_distance(int, int);
 #define node_distance(a, b) __node_distance(a, b)
+#endif
 
 #else /* !CONFIG_NUMA */
 
@@ -134,7 +174,7 @@ static inline void arch_fix_phys_package_id(int num, u32 slot)
 }
 
 struct pci_bus;
-void x86_pci_root_bus_resources(int bus, struct list_head *resources);
+void x86_pci_root_bus_res_quirks(struct pci_bus *b);
 
 #ifdef CONFIG_SMP
 #define mc_capable()    ((boot_cpu_data.x86_max_cores > 1) && \
diff --git a/arch/x86/include/asm/trace_clock.h b/arch/x86/include/asm/trace_clock.h
deleted file mode 100644
index beab86cc282..00000000000
--- a/arch/x86/include/asm/trace_clock.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_X86_TRACE_CLOCK_H
-#define _ASM_X86_TRACE_CLOCK_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#ifdef CONFIG_X86_TSC
-
-extern u64 notrace trace_clock_x86_tsc(void);
-
-# define ARCH_TRACE_CLOCKS \
-        { trace_clock_x86_tsc,  "x86-tsc",      .in_ns = 0 },
-
-#else /* !CONFIG_X86_TSC */
-
-#define ARCH_TRACE_CLOCKS
-
-#endif
-
-#endif  /* _ASM_X86_TRACE_CLOCK_H */
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index 88eae2aec61..0012d0902c5 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -89,29 +89,4 @@ asmlinkage void smp_thermal_interrupt(void);
 asmlinkage void mce_threshold_interrupt(void);
 #endif
 
-/* Interrupts/Exceptions */
-enum {
-        X86_TRAP_DE = 0,        /*  0, Divide-by-zero */
-        X86_TRAP_DB,            /*  1, Debug */
-        X86_TRAP_NMI,           /*  2, Non-maskable Interrupt */
-        X86_TRAP_BP,            /*  3, Breakpoint */
-        X86_TRAP_OF,            /*  4, Overflow */
-        X86_TRAP_BR,            /*  5, Bound Range Exceeded */
-        X86_TRAP_UD,            /*  6, Invalid Opcode */
-        X86_TRAP_NM,            /*  7, Device Not Available */
-        X86_TRAP_DF,            /*  8, Double Fault */
-        X86_TRAP_OLD_MF,        /*  9, Coprocessor Segment Overrun */
-        X86_TRAP_TS,            /* 10, Invalid TSS */
-        X86_TRAP_NP,            /* 11, Segment Not Present */
-        X86_TRAP_SS,            /* 12, Stack Segment Fault */
-        X86_TRAP_GP,            /* 13, General Protection Fault */
-        X86_TRAP_PF,            /* 14, Page Fault */
-        X86_TRAP_SPURIOUS,      /* 15, Spurious Interrupt */
-        X86_TRAP_MF,            /* 16, x87 Floating-Point Exception */
-        X86_TRAP_AC,            /* 17, Alignment Check */
-        X86_TRAP_MC,            /* 18, Machine Check */
-        X86_TRAP_XF,            /* 19, SIMD Floating-Point Exception */
-        X86_TRAP_IRET = 32,     /* 32, IRET Exception */
-};
-
 #endif /* _ASM_X86_TRAPS_H */
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index c91e8b9d588..83e2efd181e 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,8 +51,6 @@ extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
 extern unsigned long native_calibrate_tsc(void);
 
-extern int tsc_clocksource_reliable;
-
 /*
  * Boot-time check whether the TSCs are synchronized across
  * all CPUs/cores:
@@ -61,7 +59,7 @@ extern void check_tsc_sync_source(int cpu);
 extern void check_tsc_sync_target(void);
 
 extern int notsc_setup(char *);
-extern void tsc_save_sched_clock_state(void);
-extern void tsc_restore_sched_clock_state(void);
+extern void save_sched_clock_state(void);
+extern void restore_sched_clock_state(void);
 
 #endif /* _ASM_X86_TSC_H */
diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h
index 1709801d18e..36361bf6fdd 100644
--- a/arch/x86/include/asm/uaccess.h
+++ b/arch/x86/include/asm/uaccess.h
@@ -9,7 +9,6 @@
 #include <linux/string.h>
 #include <asm/asm.h>
 #include <asm/page.h>
-#include <asm/smap.h>
 
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
@@ -33,9 +32,9 @@
 
 #define segment_eq(a, b)        ((a).seg == (b).seg)
 
-#define user_addr_max() (current_thread_info()->addr_limit.seg)
-#define __addr_ok(addr)         \
-        ((unsigned long __force)(addr) < user_addr_max())
+#define __addr_ok(addr)                                 \
+        ((unsigned long __force)(addr) <                \
+         (current_thread_info()->addr_limit.seg))
 
 /*
  * Test whether a block of memory is a valid user space address.
@@ -47,14 +46,14 @@
  * This needs 33-bit (65-bit for x86_64) arithmetic. We have a carry...
  */
 
-#define __range_not_ok(addr, size, limit)                               \
+#define __range_not_ok(addr, size)                                      \
 ({                                                                      \
         unsigned long flag, roksum;                                     \
         __chk_user_ptr(addr);                                           \
         asm("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0"             \
             : "=&r" (flag), "=r" (roksum)                               \
             : "1" (addr), "g" ((long)(size)),                           \
-              "rm" (limit));                                            \
+              "rm" (current_thread_info()->addr_limit.seg));            \
         flag;                                                           \
 })
 
@@ -77,16 +76,14 @@
  * checks that the pointer is in the user space range - after calling
  * this function, memory access functions may still return -EFAULT.
  */
-#define access_ok(type, addr, size) \
-        (likely(__range_not_ok(addr, size, user_addr_max()) == 0))
+#define access_ok(type, addr, size) (likely(__range_not_ok(addr, size) == 0))
 
 /*
- * The exception table consists of pairs of addresses relative to the
- * exception table enty itself: the first is the address of an
- * instruction that is allowed to fault, and the second is the address
- * at which the program should continue.  No registers are modified,
- * so it is entirely up to the continuation code to figure out what to
- * do.
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
  *
  * All the routines below use bits of fixup code that are out of line
  * with the main instruction path.  This means when everything is well,
@@ -95,14 +92,10 @@
  */
 
 struct exception_table_entry {
-        int insn, fixup;
+        unsigned long insn, fixup;
 };
-/* This is not the generic standard exception_table_entry format */
-#define ARCH_HAS_SORT_EXTABLE
-#define ARCH_HAS_SEARCH_EXTABLE
 
 extern int fixup_exception(struct pt_regs *regs);
-extern int early_fixup_exception(unsigned long *ip);
 
 /*
  * These are the main single-value transfer routines.  They automatically
@@ -193,10 +186,9 @@ extern int __get_user_bad(void);
 
 #ifdef CONFIG_X86_32
 #define __put_user_asm_u64(x, addr, err, errret)                        \
-        asm volatile(ASM_STAC "\n"                                      \
-                     "1:        movl %%eax,0(%2)\n"                     \
+        asm volatile("1:        movl %%eax,0(%2)\n"                     \
                      "2:        movl %%edx,4(%2)\n"                     \
-                     "3: " ASM_CLAC "\n"                                \
+                     "3:\n"                                             \
                      ".section .fixup,\"ax\"\n"                         \
                      "4:        movl %3,%0\n"                           \
                      "  jmp 3b\n"                                       \
@@ -207,12 +199,11 @@ extern int __get_user_bad(void);
                      : "A" (x), "r" (addr), "i" (errret), "0" (err))
 
 #define __put_user_asm_ex_u64(x, addr)                                  \
-        asm volatile(ASM_STAC "\n"                                      \
-                     "1:        movl %%eax,0(%1)\n"                     \
+        asm volatile("1:        movl %%eax,0(%1)\n"                     \
                      "2:        movl %%edx,4(%1)\n"                     \
-                     "3: " ASM_CLAC "\n"                                \
-                     _ASM_EXTABLE_EX(1b, 2b)                            \
-                     _ASM_EXTABLE_EX(2b, 3b)                            \
+                     "3:\n"                                             \
+                     _ASM_EXTABLE(1b, 2b - 1b)                          \
+                     _ASM_EXTABLE(2b, 3b - 2b)                          \
                      : : "A" (x), "r" (addr))
 
 #define __put_user_x8(x, ptr, __ret_pu)                         \
@@ -237,6 +228,8 @@ extern void __put_user_2(void);
 extern void __put_user_4(void);
 extern void __put_user_8(void);
 
+#ifdef CONFIG_X86_WP_WORKS_OK
+
 /**
  * put_user: - Write a simple value into user space.
  * @x:   Value to copy to user space.
@@ -324,6 +317,29 @@ do {									\
         }                                                               \
 } while (0)
 
+#else
+
+#define __put_user_size(x, ptr, size, retval, errret)                   \
+do {                                                                    \
+        __typeof__(*(ptr))__pus_tmp = x;                                \
+        retval = 0;                                                     \
+                                                                        \
+        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0))    \
+                retval = errret;                                        \
+} while (0)
+
+#define put_user(x, ptr)                                        \
+({                                                              \
+        int __ret_pu;                                           \
+        __typeof__(*(ptr))__pus_tmp = x;                        \
+        __ret_pu = 0;                                           \
+        if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp,         \
+                                       sizeof(*(ptr))) != 0))   \
+                __ret_pu = -EFAULT;                             \
+        __ret_pu;                                               \
+})
+#endif
+
 #ifdef CONFIG_X86_32
 #define __get_user_asm_u64(x, ptr, retval, errret)      (x) = __get_user_bad()
 #define __get_user_asm_ex_u64(x, ptr)                   (x) = __get_user_bad()
@@ -357,9 +373,8 @@ do {									\
 } while (0)
 
 #define __get_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
-        asm volatile(ASM_STAC "\n"                                      \
-                     "1:        mov"itype" %2,%"rtype"1\n"              \
-                     "2: " ASM_CLAC "\n"                                \
+        asm volatile("1:        mov"itype" %2,%"rtype"1\n"              \
+                     "2:\n"                                             \
                      ".section .fixup,\"ax\"\n"                         \
                      "3:        mov %3,%0\n"                            \
                      "  xor"itype" %"rtype"1,%"rtype"1\n"               \
@@ -393,7 +408,7 @@ do {									\
 #define __get_user_asm_ex(x, addr, itype, rtype, ltype)                 \
         asm volatile("1:        mov"itype" %1,%"rtype"0\n"              \
                      "2:\n"                                             \
-                     _ASM_EXTABLE_EX(1b, 2b)                            \
+                     _ASM_EXTABLE(1b, 2b - 1b)                          \
                      : ltype(x) : "m" (__m(addr)))
 
 #define __put_user_nocheck(x, ptr, size)                        \
@@ -422,9 +437,8 @@ struct __large_struct { unsigned long buf[100]; };
  * aliasing issues.
  */
 #define __put_user_asm(x, addr, err, itype, rtype, ltype, errret)       \
-        asm volatile(ASM_STAC "\n"                                      \
-                     "1:        mov"itype" %"rtype"1,%2\n"              \
-                     "2: " ASM_CLAC "\n"                                \
+        asm volatile("1:        mov"itype" %"rtype"1,%2\n"              \
+                     "2:\n"                                             \
                      ".section .fixup,\"ax\"\n"                         \
                      "3:        mov %3,%0\n"                            \
                      "  jmp 2b\n"                                       \
@@ -436,20 +450,20 @@ struct __large_struct { unsigned long buf[100]; };
 #define __put_user_asm_ex(x, addr, itype, rtype, ltype)                 \
         asm volatile("1:        mov"itype" %"rtype"0,%1\n"              \
                      "2:\n"                                             \
-                     _ASM_EXTABLE_EX(1b, 2b)                            \
+                     _ASM_EXTABLE(1b, 2b - 1b)                          \
                      : : ltype(x), "m" (__m(addr)))
 
 /*
  * uaccess_try and catch
  */
 #define uaccess_try     do {                                            \
+        int prev_err = current_thread_info()->uaccess_err;              \
         current_thread_info()->uaccess_err = 0;                         \
-        stac();                                                         \
         barrier();
 
 #define uaccess_catch(err)                                              \
-        clac();                                                         \
-        (err) |= (current_thread_info()->uaccess_err ? -EFAULT : 0);    \
+        (err) |= current_thread_info()->uaccess_err;                    \
+        current_thread_info()->uaccess_err = prev_err;                  \
 } while (0)
 
 /**
@@ -518,22 +532,31 @@ struct __large_struct { unsigned long buf[100]; };
         (x) = (__force __typeof__(*(ptr)))__gue_val;                    \
 } while (0)
 
+#ifdef CONFIG_X86_WP_WORKS_OK
+
 #define put_user_try            uaccess_try
 #define put_user_catch(err)     uaccess_catch(err)
 
 #define put_user_ex(x, ptr)                                             \
         __put_user_size_ex((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
 
-extern unsigned long
-copy_from_user_nmi(void *to, const void __user *from, unsigned long n);
-extern __must_check long
-strncpy_from_user(char *dst, const char __user *src, long count);
+#else /* !CONFIG_X86_WP_WORKS_OK */
 
-extern __must_check long strlen_user(const char __user *str);
-extern __must_check long strnlen_user(const char __user *str, long n);
+#define put_user_try            do {            \
+        int __uaccess_err = 0;
 
-unsigned long __must_check clear_user(void __user *mem, unsigned long len);
-unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
+#define put_user_catch(err)                     \
+        (err) |= __uaccess_err;                 \
+} while (0)
+
+#define put_user_ex(x, ptr)     do {            \
+        __uaccess_err |= __put_user(x, ptr);    \
+} while (0)
+
+#endif /* CONFIG_X86_WP_WORKS_OK */
+
+extern unsigned long
+copy_from_user_nmi(void *to, const void __user *from, unsigned long n);
 
 /*
  * movsl can be slow when source and dest are not both 8-byte aligned
@@ -547,9 +570,9 @@ extern struct movsl_mask {
 #define ARCH_HAS_NOCACHE_UACCESS 1
 
 #ifdef CONFIG_X86_32
-# include <asm/uaccess_32.h>
+# include "uaccess_32.h"
 #else
-# include <asm/uaccess_64.h>
+# include "uaccess_64.h"
 #endif
 
 #endif /* _ASM_X86_UACCESS_H */
diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h
index 7f760a9f1f6..566e803cc60 100644
--- a/arch/x86/include/asm/uaccess_32.h
+++ b/arch/x86/include/asm/uaccess_32.h
@@ -213,4 +213,29 @@ static inline unsigned long __must_check copy_from_user(void *to,
         return n;
 }
 
+long __must_check strncpy_from_user(char *dst, const char __user *src,
+                                    long count);
+long __must_check __strncpy_from_user(char *dst,
+                                      const char __user *src, long count);
+
+/**
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+#define strlen_user(str) strnlen_user(str, LONG_MAX)
+
+long strnlen_user(const char __user *str, long n);
+unsigned long __must_check clear_user(void __user *mem, unsigned long len);
+unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
+
 #endif /* _ASM_X86_UACCESS_32_H */
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 142810c457d..1c66d30971a 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -17,8 +17,6 @@
 
 /* Handles exceptions in both to and from, but doesn't do access_ok */
 __must_check unsigned long
-copy_user_enhanced_fast_string(void *to, const void *from, unsigned len);
-__must_check unsigned long
 copy_user_generic_string(void *to, const void *from, unsigned len);
 __must_check unsigned long
 copy_user_generic_unrolled(void *to, const void *from, unsigned len);
@@ -28,16 +26,9 @@ copy_user_generic(void *to, const void *from, unsigned len)
 {
         unsigned ret;
 
-        /*
-         * If CPU has ERMS feature, use copy_user_enhanced_fast_string.
-         * Otherwise, if CPU has rep_good feature, use copy_user_generic_string.
-         * Otherwise, use copy_user_generic_unrolled.
-         */
-        alternative_call_2(copy_user_generic_unrolled,
+        alternative_call(copy_user_generic_unrolled,
                          copy_user_generic_string,
                          X86_FEATURE_REP_GOOD,
-                         copy_user_enhanced_fast_string,
-                         X86_FEATURE_ERMS,
                          ASM_OUTPUT2("=a" (ret), "=D" (to), "=S" (from),
                                      "=d" (len)),
                          "1" (to), "2" (from), "3" (len)
@@ -217,6 +208,16 @@ int __copy_in_user(void __user *dst, const void __user *src, unsigned size)
         }
 }
 
+__must_check long
+strncpy_from_user(char *dst, const char __user *src, long count);
+__must_check long
+__strncpy_from_user(char *dst, const char __user *src, long count);
+__must_check long strnlen_user(const char __user *str, long n);
+__must_check long __strnlen_user(const char __user *str, long n);
+__must_check long strlen_user(const char __user *str);
+__must_check unsigned long clear_user(void __user *mem, unsigned long len);
+__must_check unsigned long __clear_user(void __user *mem, unsigned long len);
+
 static __must_check __always_inline int
 __copy_from_user_inatomic(void *dst, const void __user *src, unsigned size)
 {
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index a0790e07ba6..2a58ed3e51d 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -1,63 +1,13 @@
-#ifndef _ASM_X86_UNISTD_H
-#define _ASM_X86_UNISTD_H 1
-
-#include <uapi/asm/unistd.h>
-
-
-# ifdef CONFIG_X86_X32_ABI
-#  define __SYSCALL_MASK (~(__X32_SYSCALL_BIT))
+#ifdef __KERNEL__
+# ifdef CONFIG_X86_32
+#  include "unistd_32.h"
 # else
-#  define __SYSCALL_MASK (~0)
+#  include "unistd_64.h"
 # endif
-
-# ifdef CONFIG_X86_32
-
-#  include <asm/unistd_32.h>
-#  define __ARCH_WANT_STAT64
-#  define __ARCH_WANT_SYS_IPC
-#  define __ARCH_WANT_SYS_OLD_MMAP
-#  define __ARCH_WANT_SYS_OLD_SELECT
-
+#else
+# ifdef __i386__
+#  include "unistd_32.h"
 # else
-
-#  include <asm/unistd_64.h>
-#  include <asm/unistd_64_x32.h>
-#  define __ARCH_WANT_COMPAT_SYS_TIME
-
+#  include "unistd_64.h"
 # endif
-
-# define __ARCH_WANT_OLD_READDIR
-# define __ARCH_WANT_OLD_STAT
-# define __ARCH_WANT_SYS_ALARM
-# define __ARCH_WANT_SYS_FADVISE64
-# define __ARCH_WANT_SYS_GETHOSTNAME
-# define __ARCH_WANT_SYS_GETPGRP
-# define __ARCH_WANT_SYS_LLSEEK
-# define __ARCH_WANT_SYS_NICE
-# define __ARCH_WANT_SYS_OLDUMOUNT
-# define __ARCH_WANT_SYS_OLD_GETRLIMIT
-# define __ARCH_WANT_SYS_OLD_UNAME
-# define __ARCH_WANT_SYS_PAUSE
-# define __ARCH_WANT_SYS_RT_SIGACTION
-# define __ARCH_WANT_SYS_RT_SIGSUSPEND
-# define __ARCH_WANT_SYS_SGETMASK
-# define __ARCH_WANT_SYS_SIGNAL
-# define __ARCH_WANT_SYS_SIGPENDING
-# define __ARCH_WANT_SYS_SIGPROCMASK
-# define __ARCH_WANT_SYS_SOCKETCALL
-# define __ARCH_WANT_SYS_TIME
-# define __ARCH_WANT_SYS_UTIME
-# define __ARCH_WANT_SYS_WAITPID
-# define __ARCH_WANT_SYS_FORK
-# define __ARCH_WANT_SYS_VFORK
-# define __ARCH_WANT_SYS_CLONE
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-# define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-#endif /* _ASM_X86_UNISTD_H */
+#endif
diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h
deleted file mode 100644
index 8ff8be7835a..00000000000
--- a/arch/x86/include/asm/uprobes.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _ASM_UPROBES_H
-#define _ASM_UPROBES_H
-/*
- * User-space Probes (UProbes) for x86
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) IBM Corporation, 2008-2011
- * Authors:
- *      Srikar Dronamraju
- *      Jim Keniston
- */
-
-#include <linux/notifier.h>
-
-typedef u8 uprobe_opcode_t;
-
-#define MAX_UINSN_BYTES                   16
-#define UPROBE_XOL_SLOT_BYTES            128    /* to keep it cache aligned */
-
-#define UPROBE_SWBP_INSN                0xcc
-#define UPROBE_SWBP_INSN_SIZE              1
-
-struct arch_uprobe {
-        u16                             fixups;
-        u8                              insn[MAX_UINSN_BYTES];
-#ifdef CONFIG_X86_64
-        unsigned long                   rip_rela_target_address;
-#endif
-};
-
-struct arch_uprobe_task {
-#ifdef CONFIG_X86_64
-        unsigned long                   saved_scratch_register;
-#endif
-        unsigned int                    saved_trap_nr;
-        unsigned int                    saved_tf;
-};
-
-extern int  arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm, unsigned long addr);
-extern int  arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs);
-extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
-extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
-extern int  arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data);
-extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
-#endif  /* _ASM_UPROBES_H */
diff --git a/arch/x86/include/asm/user.h b/arch/x86/include/asm/user.h
index ccab4af1646..24532c7da3d 100644
--- a/arch/x86/include/asm/user.h
+++ b/arch/x86/include/asm/user.h
@@ -2,9 +2,9 @@
 #define _ASM_X86_USER_H
 
 #ifdef CONFIG_X86_32
-# include <asm/user_32.h>
+# include "user_32.h"
 #else
-# include <asm/user_64.h>
+# include "user_64.h"
 #endif
 
 #include <asm/types.h>
diff --git a/arch/x86/include/asm/uv/uv.h b/arch/x86/include/asm/uv/uv.h
index b47c2a82ff1..3bb9491b765 100644
--- a/arch/x86/include/asm/uv/uv.h
+++ b/arch/x86/include/asm/uv/uv.h
@@ -15,8 +15,7 @@ extern void uv_nmi_init(void);
 extern void uv_system_init(void);
 extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                                  struct mm_struct *mm,
-                                                 unsigned long start,
-                                                 unsigned end,
+                                                 unsigned long va,
                                                  unsigned int cpu);
 
 #else   /* X86_UV */
@@ -27,7 +26,7 @@ static inline void uv_cpu_init(void)	{ }
 static inline void uv_system_init(void) { }
 static inline const struct cpumask *
 uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,
-                    unsigned long start, unsigned long end, unsigned int cpu)
+                    unsigned long va, unsigned int cpu)
 { return cpumask; }
 
 #endif  /* X86_UV */
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index a06983cdc12..0c767a8e000 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -65,7 +65,7 @@
  * UV2: Bit 19 selects between
  *  (0): 10 microsecond timebase and
  *  (1): 80 microseconds
- *  we're using 560us, similar to UV1: 65 units of 10us
+ *  we're using 655us, similar to UV1: 65 units of 10us
  */
 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
@@ -140,9 +140,6 @@
 #define IPI_RESET_LIMIT                 1
 /* after this # consecutive successes, bump up the throttle if it was lowered */
 #define COMPLETE_THRESHOLD              5
-/* after this # of giveups (fall back to kernel IPI's) disable the use of
-   the BAU for a period of time */
-#define GIVEUP_LIMIT                    100
 
 #define UV_LB_SUBNODEID                 0x10
 
@@ -152,6 +149,7 @@
 /* 4 bits of software ack period */
 #define UV2_ACK_MASK                    0x7UL
 #define UV2_ACK_UNITS_SHFT              3
+#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
 /*
@@ -177,7 +175,7 @@
                                                    microseconds */
 #define CONGESTED_REPS                  10      /* long delays averaged over
                                                    this many broadcasts */
-#define DISABLED_PERIOD                 10      /* time for the bau to be
+#define CONGESTED_PERIOD                30      /* time for the bau to be
                                                    disabled, in seconds */
 /* see msg_type: */
 #define MSG_NOOP                        0
@@ -237,10 +235,10 @@ struct bau_msg_payload {
 
 
 /*
- * UV1 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
+ * Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
  * see table 4.2.3.0.1 in broacast_assist spec.
  */
-struct uv1_bau_msg_header {
+struct bau_msg_header {
         unsigned int    dest_subnodeid:6;       /* must be 0x10, for the LB */
         /* bits 5:0 */
         unsigned int    base_dest_nasid:15;     /* nasid of the first bit */
@@ -320,87 +318,19 @@ struct uv1_bau_msg_header {
 };
 
 /*
- * UV2 Message header:  16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
- * see figure 9-2 of harp_sys.pdf
- */
-struct uv2_bau_msg_header {
-        unsigned int    base_dest_nasid:15;     /* nasid of the first bit */
-        /* bits 14:0 */                         /* in uvhub map */
-        unsigned int    dest_subnodeid:5;       /* must be 0x10, for the LB */
-        /* bits 19:15 */
-        unsigned int    rsvd_1:1;               /* must be zero */
-        /* bit 20 */
-        /* Address bits 59:21 */
-        /* bits 25:2 of address (44:21) are payload */
-        /* these next 24 bits become bytes 12-14 of msg */
-        /* bits 28:21 land in byte 12 */
-        unsigned int    replied_to:1;           /* sent as 0 by the source to
-                                                   byte 12 */
-        /* bit 21 */
-        unsigned int    msg_type:3;             /* software type of the
-                                                   message */
-        /* bits 24:22 */
-        unsigned int    canceled:1;             /* message canceled, resource
-                                                   is to be freed*/
-        /* bit 25 */
-        unsigned int    payload_1:3;            /* not currently used */
-        /* bits 28:26 */
-
-        /* bits 36:29 land in byte 13 */
-        unsigned int    payload_2a:3;           /* not currently used */
-        unsigned int    payload_2b:5;           /* not currently used */
-        /* bits 36:29 */
-
-        /* bits 44:37 land in byte 14 */
-        unsigned int    payload_3:8;            /* not currently used */
-        /* bits 44:37 */
-
-        unsigned int    rsvd_2:7;               /* reserved */
-        /* bits 51:45 */
-        unsigned int    swack_flag:1;           /* software acknowledge flag */
-        /* bit 52 */
-        unsigned int    rsvd_3a:3;              /* must be zero */
-        unsigned int    rsvd_3b:8;              /* must be zero */
-        unsigned int    rsvd_3c:8;              /* must be zero */
-        unsigned int    rsvd_3d:3;              /* must be zero */
-        /* bits 74:53 */
-        unsigned int    fairness:3;             /* usually zero */
-        /* bits 77:75 */
-
-        unsigned int    sequence:16;            /* message sequence number */
-        /* bits 93:78  Suppl_A  */
-        unsigned int    chaining:1;             /* next descriptor is part of
-                                                   this activation*/
-        /* bit 94 */
-        unsigned int    multilevel:1;           /* multi-level multicast
-                                                   format */
-        /* bit 95 */
-        unsigned int    rsvd_4:24;              /* ordered / source node /
-                                                   source subnode / aging
-                                                   must be zero */
-        /* bits 119:96 */
-        unsigned int    command:8;              /* message type */
-        /* bits 127:120 */
-};
-
-/*
  * The activation descriptor:
  * The format of the message to send, plus all accompanying control
  * Should be 64 bytes
  */
 struct bau_desc {
-        struct pnmask                           distribution;
+        struct pnmask                   distribution;
         /*
          * message template, consisting of header and payload:
          */
-        union bau_msg_header {
-                struct uv1_bau_msg_header       uv1_hdr;
-                struct uv2_bau_msg_header       uv2_hdr;
-        } header;
-
-        struct bau_msg_payload                  payload;
+        struct bau_msg_header           header;
+        struct bau_msg_payload          payload;
 };
-/* UV1:
+/*
  *   -payload--    ---------header------
  *   bytes 0-11    bits 41-56  bits 58-81
  *       A           B  (2)      C (3)
@@ -410,16 +340,6 @@ struct bau_desc {
  *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
  *   ------------payload queue-----------
  */
-/* UV2:
- *   -payload--    ---------header------
- *   bytes 0-11    bits 70-78  bits 21-44
- *       A           B  (2)      C (3)
- *
- *            A/B/C are moved to:
- *       A            C          B
- *   bytes 0-11  bytes 12-14  bytes 16-17  (byte 15 filled in by hw as vector)
- *   ------------payload queue-----------
- */
 
 /*
  * The payload queue on the destination side is an array of these.
@@ -465,6 +385,7 @@ struct bau_pq_entry {
 struct msg_desc {
         struct bau_pq_entry     *msg;
         int                     msg_slot;
+        int                     swack_slot;
         struct bau_pq_entry     *queue_first;
         struct bau_pq_entry     *queue_last;
 };
@@ -484,7 +405,6 @@ struct ptc_stats {
                                                    requests */
         unsigned long   s_stimeout;             /* source side timeouts */
         unsigned long   s_dtimeout;             /* destination side timeouts */
-        unsigned long   s_strongnacks;          /* number of strong nack's */
         unsigned long   s_time;                 /* time spent in sending side */
         unsigned long   s_retriesok;            /* successful retries */
         unsigned long   s_ntargcpu;             /* total number of cpu's
@@ -519,15 +439,6 @@ struct ptc_stats {
         unsigned long   s_retry_messages;       /* retry broadcasts */
         unsigned long   s_bau_reenabled;        /* for bau enable/disable */
         unsigned long   s_bau_disabled;         /* for bau enable/disable */
-        unsigned long   s_uv2_wars;             /* uv2 workaround, perm. busy */
-        unsigned long   s_uv2_wars_hw;          /* uv2 workaround, hiwater */
-        unsigned long   s_uv2_war_waits;        /* uv2 workaround, long waits */
-        unsigned long   s_overipilimit;         /* over the ipi reset limit */
-        unsigned long   s_giveuplimit;          /* disables, over giveup limit*/
-        unsigned long   s_enters;               /* entries to the driver */
-        unsigned long   s_ipifordisabled;       /* fall back to IPI; disabled */
-        unsigned long   s_plugged;              /* plugged by h/w bug*/
-        unsigned long   s_congested;            /* giveup on long wait */
         /* destination statistics */
         unsigned long   d_alltlb;               /* times all tlb's on this
                                                    cpu were flushed */
@@ -594,26 +505,21 @@ struct bau_control {
         int                     timeout_tries;
         int                     ipi_attempts;
         int                     conseccompletes;
-        short                   nobau;
-        short                   baudisabled;
+        int                     baudisabled;
+        int                     set_bau_off;
         short                   cpu;
         short                   osnode;
         short                   uvhub_cpu;
         short                   uvhub;
-        short                   uvhub_version;
         short                   cpus_in_socket;
         short                   cpus_in_uvhub;
         short                   partition_base_pnode;
-        short                   busy;       /* all were busy (war) */
         unsigned short          message_number;
         unsigned short          uvhub_quiesce;
         short                   socket_acknowledge_count[DEST_Q_SIZE];
         cycles_t                send_message;
-        cycles_t                period_end;
-        cycles_t                period_time;
         spinlock_t              uvhub_lock;
         spinlock_t              queue_lock;
-        spinlock_t              disable_lock;
         /* tunables */
         int                     max_concurr;
         int                     max_concurr_const;
@@ -624,9 +530,8 @@ struct bau_control {
         int                     complete_threshold;
         int                     cong_response_us;
         int                     cong_reps;
-        cycles_t                disabled_period;
-        int                     period_giveups;
-        int                     giveup_limit;
+        int                     cong_period;
+        cycles_t                period_time;
         long                    period_requests;
         struct hub_and_pnode    *thp;
 };
@@ -686,11 +591,6 @@ static inline void write_mmr_sw_ack(unsigned long mr)
         uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
 }
 
-static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
-{
-        write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
-}
-
 static inline unsigned long read_mmr_sw_ack(void)
 {
         return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
@@ -757,7 +657,11 @@ static inline int atomic_read_short(const struct atomic_short *v)
  */
 static inline int atom_asr(short i, struct atomic_short *v)
 {
-        return i + xadd(&v->counter, i);
+        short __i = i;
+        asm volatile(LOCK_PREFIX "xaddw %0, %1"
+                        : "+r" (i), "+m" (v->counter)
+                        : : "memory");
+        return i + __i;
 }
 
 /*
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 21f7385badb..54a13aaebc4 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -318,13 +318,13 @@ uv_gpa_in_mmr_space(unsigned long gpa)
 /* UV global physical address --> socket phys RAM */
 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
 {
-        unsigned long paddr;
+        unsigned long paddr = gpa & uv_hub_info->gpa_mask;
         unsigned long remap_base = uv_hub_info->lowmem_remap_base;
         unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
 
         gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
                 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
-        paddr = gpa & uv_hub_info->gpa_mask;
+        gpa = gpa & uv_hub_info->gpa_mask;
         if (paddr >= remap_base && paddr < remap_base + remap_top)
                 paddr -= remap_base;
         return paddr;
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index cf1d73643f6..10474fb1185 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -57,7 +57,6 @@
 
 #define UV1_HUB_PART_NUMBER     0x88a5
 #define UV2_HUB_PART_NUMBER     0x8eb8
-#define UV2_HUB_PART_NUMBER_X   0x1111
 
 /* Compat: if this #define is present, UV headers support UV2 */
 #define UV2_HUB_IS_SUPPORTED    1
diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h
index fddb53d6391..bb0522850b7 100644
--- a/arch/x86/include/asm/vdso.h
+++ b/arch/x86/include/asm/vdso.h
@@ -11,8 +11,7 @@ extern const char VDSO32_PRELINK[];
 #define VDSO32_SYMBOL(base, name)                                       \
 ({                                                                      \
         extern const char VDSO32_##name[];                              \
-        (void __user *)(VDSO32_##name - VDSO32_PRELINK +                \
-                        (unsigned long)(base));                         \
+        (void *)(VDSO32_##name - VDSO32_PRELINK + (unsigned long)(base)); \
 })
 #endif
 
diff --git a/arch/x86/include/asm/vga.h b/arch/x86/include/asm/vga.h
index 44282fbf7bf..c4b9dc2f67c 100644
--- a/arch/x86/include/asm/vga.h
+++ b/arch/x86/include/asm/vga.h
@@ -17,10 +17,4 @@
 #define vga_readb(x) (*(x))
 #define vga_writeb(x, y) (*(y) = (x))
 
-#ifdef CONFIG_FB_EFI
-#define __ARCH_HAS_VGA_DEFAULT_DEVICE
-extern struct pci_dev *vga_default_device(void);
-extern void vga_set_default_device(struct pci_dev *pdev);
-#endif
-
 #endif /* _ASM_X86_VGA_H */
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 46e24d36b7d..815285bcace 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -5,8 +5,13 @@
 #include <linux/clocksource.h>
 
 struct vsyscall_gtod_data {
-        seqcount_t      seq;
+        seqlock_t       lock;
 
+        /* open coded 'struct timespec' */
+        time_t          wall_time_sec;
+        u32             wall_time_nsec;
+
+        struct timezone sys_tz;
         struct { /* extract of a clocksource struct */
                 int vclock_mode;
                 cycle_t cycle_last;
@@ -14,16 +19,8 @@ struct vsyscall_gtod_data {
                 u32     mult;
                 u32     shift;
         } clock;
-
-        /* open coded 'struct timespec' */
-        time_t          wall_time_sec;
-        u64             wall_time_snsec;
-        u64             monotonic_time_snsec;
-        time_t          monotonic_time_sec;
-
-        struct timezone sys_tz;
+        struct timespec wall_to_monotonic;
         struct timespec wall_time_coarse;
-        struct timespec monotonic_time_coarse;
 };
 extern struct vsyscall_gtod_data vsyscall_gtod_data;
 
diff --git a/arch/x86/include/asm/virtext.h b/arch/x86/include/asm/virtext.h
index 5da71c27cc5..e0f9aa16358 100644
--- a/arch/x86/include/asm/virtext.h
+++ b/arch/x86/include/asm/virtext.h
@@ -16,6 +16,7 @@
 #define _ASM_X86_VIRTEX_H
 
 #include <asm/processor.h>
+#include <asm/system.h>
 
 #include <asm/vmx.h>
 #include <asm/svm.h>
diff --git a/arch/x86/include/asm/vm86.h b/arch/x86/include/asm/vm86.h
index 1d8de3f3fec..f9303602fbc 100644
--- a/arch/x86/include/asm/vm86.h
+++ b/arch/x86/include/asm/vm86.h
@@ -1,9 +1,133 @@
 #ifndef _ASM_X86_VM86_H
 #define _ASM_X86_VM86_H
 
+/*
+ * I'm guessing at the VIF/VIP flag usage, but hope that this is how
+ * the Pentium uses them. Linux will return from vm86 mode when both
+ * VIF and VIP is set.
+ *
+ * On a Pentium, we could probably optimize the virtual flags directly
+ * in the eflags register instead of doing it "by hand" in vflags...
+ *
+ * Linus
+ */
+
+#include <asm/processor-flags.h>
+
+#define BIOSSEG         0x0f000
+
+#define CPU_086         0
+#define CPU_186         1
+#define CPU_286         2
+#define CPU_386         3
+#define CPU_486         4
+#define CPU_586         5
+
+/*
+ * Return values for the 'vm86()' system call
+ */
+#define VM86_TYPE(retval)       ((retval) & 0xff)
+#define VM86_ARG(retval)        ((retval) >> 8)
+
+#define VM86_SIGNAL     0       /* return due to signal */
+#define VM86_UNKNOWN    1       /* unhandled GP fault
+                                   - IO-instruction or similar */
+#define VM86_INTx       2       /* int3/int x instruction (ARG = x) */
+#define VM86_STI        3       /* sti/popf/iret instruction enabled
+                                   virtual interrupts */
+
+/*
+ * Additional return values when invoking new vm86()
+ */
+#define VM86_PICRETURN  4       /* return due to pending PIC request */
+#define VM86_TRAP       6       /* return due to DOS-debugger request */
+
+/*
+ * function codes when invoking new vm86()
+ */
+#define VM86_PLUS_INSTALL_CHECK 0
+#define VM86_ENTER              1
+#define VM86_ENTER_NO_BYPASS    2
+#define VM86_REQUEST_IRQ        3
+#define VM86_FREE_IRQ           4
+#define VM86_GET_IRQ_BITS       5
+#define VM86_GET_AND_RESET_IRQ  6
+
+/*
+ * This is the stack-layout seen by the user space program when we have
+ * done a translation of "SAVE_ALL" from vm86 mode. The real kernel layout
+ * is 'kernel_vm86_regs' (see below).
+ */
+
+struct vm86_regs {
+/*
+ * normal regs, with special meaning for the segment descriptors..
+ */
+        long ebx;
+        long ecx;
+        long edx;
+        long esi;
+        long edi;
+        long ebp;
+        long eax;
+        long __null_ds;
+        long __null_es;
+        long __null_fs;
+        long __null_gs;
+        long orig_eax;
+        long eip;
+        unsigned short cs, __csh;
+        long eflags;
+        long esp;
+        unsigned short ss, __ssh;
+/*
+ * these are specific to v86 mode:
+ */
+        unsigned short es, __esh;
+        unsigned short ds, __dsh;
+        unsigned short fs, __fsh;
+        unsigned short gs, __gsh;
+};
+
+struct revectored_struct {
+        unsigned long __map[8];                 /* 256 bits */
+};
+
+struct vm86_struct {
+        struct vm86_regs regs;
+        unsigned long flags;
+        unsigned long screen_bitmap;
+        unsigned long cpu_type;
+        struct revectored_struct int_revectored;
+        struct revectored_struct int21_revectored;
+};
+
+/*
+ * flags masks
+ */
+#define VM86_SCREEN_BITMAP      0x0001
+
+struct vm86plus_info_struct {
+        unsigned long force_return_for_pic:1;
+        unsigned long vm86dbg_active:1;       /* for debugger */
+        unsigned long vm86dbg_TFpendig:1;     /* for debugger */
+        unsigned long unused:28;
+        unsigned long is_vm86pus:1;           /* for vm86 internal use */
+        unsigned char vm86dbg_intxxtab[32];   /* for debugger */
+};
+struct vm86plus_struct {
+        struct vm86_regs regs;
+        unsigned long flags;
+        unsigned long screen_bitmap;
+        unsigned long cpu_type;
+        struct revectored_struct int_revectored;
+        struct revectored_struct int21_revectored;
+        struct vm86plus_info_struct vm86plus;
+};
+
+#ifdef __KERNEL__
 
 #include <asm/ptrace.h>
-#include <uapi/asm/vm86.h>
 
 /*
  * This is the (kernel) stack-layout when we have done a "SAVE_ALL" from vm86
@@ -79,4 +203,6 @@ static inline int handle_vm86_trap(struct kernel_vm86_regs *a, long b, int c)
 
 #endif /* CONFIG_VM86 */
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_X86_VM86_H */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 235b49fa554..2caf290e989 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -1,3 +1,6 @@
+#ifndef VMX_H
+#define VMX_H
+
 /*
  * vmx.h: VMX Architecture related definitions
  * Copyright (c) 2004, Intel Corporation.
@@ -21,12 +24,8 @@
  *    Yaniv Kamay <yaniv@qumranet.com>
  *
  */
-#ifndef VMX_H
-#define VMX_H
-
 
 #include <linux/types.h>
-#include <uapi/asm/vmx.h>
 
 /*
  * Definitions of Primary Processor-Based VM-Execution Controls.
@@ -61,7 +60,6 @@
 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
-#define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
 
 
 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
@@ -242,6 +240,48 @@ enum vmcs_field {
         HOST_RIP                        = 0x00006c16,
 };
 
+#define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
+
+#define EXIT_REASON_EXCEPTION_NMI       0
+#define EXIT_REASON_EXTERNAL_INTERRUPT  1
+#define EXIT_REASON_TRIPLE_FAULT        2
+
+#define EXIT_REASON_PENDING_INTERRUPT   7
+#define EXIT_REASON_NMI_WINDOW          8
+#define EXIT_REASON_TASK_SWITCH         9
+#define EXIT_REASON_CPUID               10
+#define EXIT_REASON_HLT                 12
+#define EXIT_REASON_INVD                13
+#define EXIT_REASON_INVLPG              14
+#define EXIT_REASON_RDPMC               15
+#define EXIT_REASON_RDTSC               16
+#define EXIT_REASON_VMCALL              18
+#define EXIT_REASON_VMCLEAR             19
+#define EXIT_REASON_VMLAUNCH            20
+#define EXIT_REASON_VMPTRLD             21
+#define EXIT_REASON_VMPTRST             22
+#define EXIT_REASON_VMREAD              23
+#define EXIT_REASON_VMRESUME            24
+#define EXIT_REASON_VMWRITE             25
+#define EXIT_REASON_VMOFF               26
+#define EXIT_REASON_VMON                27
+#define EXIT_REASON_CR_ACCESS           28
+#define EXIT_REASON_DR_ACCESS           29
+#define EXIT_REASON_IO_INSTRUCTION      30
+#define EXIT_REASON_MSR_READ            31
+#define EXIT_REASON_MSR_WRITE           32
+#define EXIT_REASON_INVALID_STATE       33
+#define EXIT_REASON_MWAIT_INSTRUCTION   36
+#define EXIT_REASON_MONITOR_INSTRUCTION 39
+#define EXIT_REASON_PAUSE_INSTRUCTION   40
+#define EXIT_REASON_MCE_DURING_VMENTRY   41
+#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
+#define EXIT_REASON_APIC_ACCESS         44
+#define EXIT_REASON_EPT_VIOLATION       48
+#define EXIT_REASON_EPT_MISCONFIG       49
+#define EXIT_REASON_WBINVD              54
+#define EXIT_REASON_XSETBV              55
+
 /*
  * Interruption-information format
  */
@@ -310,18 +350,6 @@ enum vmcs_field {
 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 
 
-/*
- * Exit Qualifications for APIC-Access
- */
-#define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
-#define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
-#define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
-#define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
-#define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
-#define TYPE_LINEAR_APIC_EVENT          (3 << 12)
-#define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
-#define TYPE_PHYSICAL_APIC_INST         (15 << 12)
-
 /* segment AR */
 #define SEGMENT_AR_L_MASK (1 << 13)
 
@@ -364,7 +392,7 @@ enum vmcs_field {
 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
-#define VMX_EPT_AD_BIT                              (1ull << 21)
+#define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 
@@ -375,14 +403,11 @@ enum vmcs_field {
 #define VMX_EPT_MAX_GAW                         0x4
 #define VMX_EPT_MT_EPTE_SHIFT                   3
 #define VMX_EPT_GAW_EPTP_SHIFT                  3
-#define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
 #define VMX_EPT_DEFAULT_MT                      0x6ull
 #define VMX_EPT_READABLE_MASK                   0x1ull
 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
-#define VMX_EPT_ACCESS_BIT                              (1ull << 8)
-#define VMX_EPT_DIRTY_BIT                               (1ull << 9)
 
 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index 2a46ca720af..eaea1d31f75 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -1,8 +1,20 @@
 #ifndef _ASM_X86_VSYSCALL_H
 #define _ASM_X86_VSYSCALL_H
 
+enum vsyscall_num {
+        __NR_vgettimeofday,
+        __NR_vtime,
+        __NR_vgetcpu,
+};
+
+#define VSYSCALL_START (-10UL << 20)
+#define VSYSCALL_SIZE 1024
+#define VSYSCALL_END (-2UL << 20)
+#define VSYSCALL_MAPPED_PAGES 1
+#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr))
+
+#ifdef __KERNEL__
 #include <linux/seqlock.h>
-#include <uapi/asm/vsyscall.h>
 
 #define VGETCPU_RDTSCP  1
 #define VGETCPU_LSL     2
@@ -21,24 +33,6 @@ extern void map_vsyscall(void);
  */
 extern bool emulate_vsyscall(struct pt_regs *regs, unsigned long address);
 
-#ifdef CONFIG_X86_64
-
-#define VGETCPU_CPU_MASK 0xfff
-
-static inline unsigned int __getcpu(void)
-{
-        unsigned int p;
-
-        if (VVAR(vgetcpu_mode) == VGETCPU_RDTSCP) {
-                /* Load per CPU data from RDTSCP */
-                native_read_tscp(&p);
-        } else {
-                /* Load per CPU data from GDT */
-                asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
-        }
-
-        return p;
-}
-#endif /* CONFIG_X86_64 */
+#endif /* __KERNEL__ */
 
 #endif /* _ASM_X86_VSYSCALL_H */
diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h
deleted file mode 100644
index 5b238981542..00000000000
--- a/arch/x86/include/asm/word-at-a-time.h
+++ /dev/null
@@ -1,105 +0,0 @@
-#ifndef _ASM_WORD_AT_A_TIME_H
-#define _ASM_WORD_AT_A_TIME_H
-
-#include <linux/kernel.h>
-
-/*
- * This is largely generic for little-endian machines, but the
- * optimal byte mask counting is probably going to be something
- * that is architecture-specific. If you have a reliably fast
- * bit count instruction, that might be better than the multiply
- * and shift, for example.
- */
-struct word_at_a_time {
-        const unsigned long one_bits, high_bits;
-};
-
-#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
-
-#ifdef CONFIG_64BIT
-
-/*
- * Jan Achrenius on G+: microoptimized version of
- * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56"
- * that works for the bytemasks without having to
- * mask them first.
- */
-static inline long count_masked_bytes(unsigned long mask)
-{
-        return mask*0x0001020304050608ul >> 56;
-}
-
-#else   /* 32-bit case */
-
-/* Carl Chatfield / Jan Achrenius G+ version for 32-bit */
-static inline long count_masked_bytes(long mask)
-{
-        /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */
-        long a = (0x0ff0001+mask) >> 23;
-        /* Fix the 1 for 00 case */
-        return a & mask;
-}
-
-#endif
-
-/* Return nonzero if it has a zero */
-static inline unsigned long has_zero(unsigned long a, unsigned long *bits, const struct word_at_a_time *c)
-{
-        unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
-        *bits = mask;
-        return mask;
-}
-
-static inline unsigned long prep_zero_mask(unsigned long a, unsigned long bits, const struct word_at_a_time *c)
-{
-        return bits;
-}
-
-static inline unsigned long create_zero_mask(unsigned long bits)
-{
-        bits = (bits - 1) & ~bits;
-        return bits >> 7;
-}
-
-/* The mask we created is directly usable as a bytemask */
-#define zero_bytemask(mask) (mask)
-
-static inline unsigned long find_zero(unsigned long mask)
-{
-        return count_masked_bytes(mask);
-}
-
-/*
- * Load an unaligned word from kernel space.
- *
- * In the (very unlikely) case of the word being a page-crosser
- * and the next page not being mapped, take the exception and
- * return zeroes in the non-existing part.
- */
-static inline unsigned long load_unaligned_zeropad(const void *addr)
-{
-        unsigned long ret, dummy;
-
-        asm(
-                "1:\tmov %2,%0\n"
-                "2:\n"
-                ".section .fixup,\"ax\"\n"
-                "3:\t"
-                "lea %2,%1\n\t"
-                "and %3,%1\n\t"
-                "mov (%1),%0\n\t"
-                "leal %2,%%ecx\n\t"
-                "andl %4,%%ecx\n\t"
-                "shll $3,%%ecx\n\t"
-                "shr %%cl,%0\n\t"
-                "jmp 2b\n"
-                ".previous\n"
-                _ASM_EXTABLE(1b, 3b)
-                :"=&r" (ret),"=&c" (dummy)
-                :"m" (*(unsigned long *)addr),
-                 "i" (-sizeof(unsigned long)),
-                 "i" (sizeof(unsigned long)-1));
-        return ret;
-}
-
-#endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/x86/include/asm/x2apic.h b/arch/x86/include/asm/x2apic.h
index f90f0a587c6..6bf5b8e478c 100644
--- a/arch/x86/include/asm/x2apic.h
+++ b/arch/x86/include/asm/x2apic.h
@@ -9,9 +9,13 @@
 #include <asm/ipi.h>
 #include <linux/cpumask.h>
 
-static int x2apic_apic_id_valid(int apicid)
+/*
+ * Need to use more than cpu 0, because we need more vectors
+ * when MSI-X are used.
+ */
+static const struct cpumask *x2apic_target_cpus(void)
 {
-        return 1;
+        return cpu_online_mask;
 }
 
 static int x2apic_apic_id_registered(void)
@@ -19,6 +23,15 @@ static int x2apic_apic_id_registered(void)
         return 1;
 }
 
+/*
+ * For now each logical cpu is in its own vector allocation domain.
+ */
+static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
+{
+        cpumask_clear(retmask);
+        cpumask_set_cpu(cpu, retmask);
+}
+
 static void
 __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
 {
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 57693498519..d3d859035af 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -7,7 +7,6 @@
 struct mpc_bus;
 struct mpc_cpu;
 struct mpc_table;
-struct cpuinfo_x86;
 
 /**
  * struct x86_init_mpparse - platform specific mpparse ops
@@ -81,13 +80,12 @@ struct x86_init_mapping {
 
 /**
  * struct x86_init_paging - platform specific paging functions
- * @pagetable_init:     platform specific paging initialization call to setup
- *                      the kernel pagetables and prepare accessors functions.
- *                      Callback must call paging_init(). Called once after the
- *                      direct mapping for phys memory is available.
+ * @pagetable_setup_start:      platform specific pre paging_init() call
+ * @pagetable_setup_done:       platform specific post paging_init() call
  */
 struct x86_init_paging {
-        void (*pagetable_init)(void);
+        void (*pagetable_setup_start)(pgd_t *base);
+        void (*pagetable_setup_done)(pgd_t *base);
 };
 
 /**
@@ -146,12 +144,9 @@ struct x86_init_ops {
 /**
  * struct x86_cpuinit_ops - platform specific cpu hotplug setups
  * @setup_percpu_clockev:       set up the per cpu clock event device
- * @early_percpu_clock_init:    early init of the per cpu clock event device
  */
 struct x86_cpuinit_ops {
         void (*setup_percpu_clockev)(void);
-        void (*early_percpu_clock_init)(void);
-        void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node);
 };
 
 /**
@@ -162,9 +157,6 @@ struct x86_cpuinit_ops {
  * @is_untracked_pat_range      exclude from PAT logic
  * @nmi_init                    enable NMI on cpus
  * @i8042_detect                pre-detect if i8042 controller exists
- * @save_sched_clock_state:     save state for sched_clock() on suspend
- * @restore_sched_clock_state:  restore state for sched_clock() on resume
- * @apic_post_init:             adjust apic if neeeded
  */
 struct x86_platform_ops {
         unsigned long (*calibrate_tsc)(void);
@@ -173,11 +165,7 @@ struct x86_platform_ops {
         void (*iommu_shutdown)(void);
         bool (*is_untracked_pat_range)(u64 start, u64 end);
         void (*nmi_init)(void);
-        unsigned char (*get_nmi_reason)(void);
         int (*i8042_detect)(void);
-        void (*save_sched_clock_state)(void);
-        void (*restore_sched_clock_state)(void);
-        void (*apic_post_init)(void);
 };
 
 struct pci_dev;
@@ -186,21 +174,13 @@ struct x86_msi_ops {
         int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
         void (*teardown_msi_irq)(unsigned int irq);
         void (*teardown_msi_irqs)(struct pci_dev *dev);
-        void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
-};
-
-struct x86_io_apic_ops {
-        void            (*init)  (void);
-        unsigned int    (*read)  (unsigned int apic, unsigned int reg);
-        void            (*write) (unsigned int apic, unsigned int reg, unsigned int value);
-        void            (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
 };
 
 extern struct x86_init_ops x86_init;
 extern struct x86_cpuinit_ops x86_cpuinit;
 extern struct x86_platform_ops x86_platform;
 extern struct x86_msi_ops x86_msi;
-extern struct x86_io_apic_ops x86_io_apic_ops;
+
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
 
diff --git a/arch/x86/include/asm/xen/events.h b/arch/x86/include/asm/xen/events.h
index cc146d51449..1df35417c41 100644
--- a/arch/x86/include/asm/xen/events.h
+++ b/arch/x86/include/asm/xen/events.h
@@ -6,7 +6,6 @@ enum ipi_vector {
         XEN_CALL_FUNCTION_VECTOR,
         XEN_CALL_FUNCTION_SINGLE_VECTOR,
         XEN_SPIN_UNLOCK_VECTOR,
-        XEN_IRQ_WORK_VECTOR,
 
         XEN_NR_IPIS,
 };
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index c20d1ce62dc..417777de5a4 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -47,8 +47,6 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/sched.h>
 #include <xen/interface/physdev.h>
-#include <xen/interface/platform.h>
-#include <xen/interface/xen-mca.h>
 
 /*
  * The hypercall asms have to meet several constraints:
@@ -303,20 +301,6 @@ HYPERVISOR_set_timer_op(u64 timeout)
 }
 
 static inline int
-HYPERVISOR_mca(struct xen_mc *mc_op)
-{
-        mc_op->interface_version = XEN_MCA_INTERFACE_VERSION;
-        return _hypercall1(int, mca, mc_op);
-}
-
-static inline int
-HYPERVISOR_dom0_op(struct xen_platform_op *platform_op)
-{
-        platform_op->interface_version = XENPF_INTERFACE_VERSION;
-        return _hypercall1(int, dom0_op, platform_op);
-}
-
-static inline int
 HYPERVISOR_set_debugreg(int reg, unsigned long value)
 {
         return _hypercall2(int, set_debugreg, reg, value);
@@ -359,14 +343,18 @@ HYPERVISOR_update_va_mapping(unsigned long va, pte_t new_val,
                 return _hypercall4(int, update_va_mapping, va,
                                    new_val.pte, new_val.pte >> 32, flags);
 }
-extern int __must_check xen_event_channel_op_compat(int, void *);
 
 static inline int
 HYPERVISOR_event_channel_op(int cmd, void *arg)
 {
         int rc = _hypercall2(int, event_channel_op, cmd, arg);
-        if (unlikely(rc == -ENOSYS))
-                rc = xen_event_channel_op_compat(cmd, arg);
+        if (unlikely(rc == -ENOSYS)) {
+                struct evtchn_op op;
+                op.cmd = cmd;
+                memcpy(&op.u, arg, sizeof(op.u));
+                rc = _hypercall1(int, event_channel_op_compat, &op);
+                memcpy(arg, &op.u, sizeof(op.u));
+        }
         return rc;
 }
 
@@ -382,14 +370,17 @@ HYPERVISOR_console_io(int cmd, int count, char *str)
         return _hypercall3(int, console_io, cmd, count, str);
 }
 
-extern int __must_check HYPERVISOR_physdev_op_compat(int, void *);
-
 static inline int
 HYPERVISOR_physdev_op(int cmd, void *arg)
 {
         int rc = _hypercall2(int, physdev_op, cmd, arg);
-        if (unlikely(rc == -ENOSYS))
-                rc = HYPERVISOR_physdev_op_compat(cmd, arg);
+        if (unlikely(rc == -ENOSYS)) {
+                struct physdev_op op;
+                op.cmd = cmd;
+                memcpy(&op.u, arg, sizeof(op.u));
+                rc = _hypercall1(int, physdev_op_compat, &op);
+                memcpy(arg, &op.u, sizeof(op.u));
+        }
         return rc;
 }
 
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index 125f344f06a..66d0fff1ee8 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -33,6 +33,7 @@
 #ifndef _ASM_X86_XEN_HYPERVISOR_H
 #define _ASM_X86_XEN_HYPERVISOR_H
 
+/* arch/i386/kernel/setup.c */
 extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
 
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index fd9cb7695b5..5d4922ad4b9 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -47,23 +47,14 @@
 #endif
 
 #ifndef __ASSEMBLY__
-/* Explicitly size integers that represent pfns in the public interface
- * with Xen so that on ARM we can have one ABI that works for 32 and 64
- * bit guests. */
-typedef unsigned long xen_pfn_t;
-#define PRI_xen_pfn "lx"
-typedef unsigned long xen_ulong_t;
-#define PRI_xen_ulong "lx"
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
 DEFINE_GUEST_HANDLE(char);
 DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
-DEFINE_GUEST_HANDLE(uint64_t);
-DEFINE_GUEST_HANDLE(uint32_t);
-DEFINE_GUEST_HANDLE(xen_pfn_t);
-DEFINE_GUEST_HANDLE(xen_ulong_t);
 #endif
 
 #ifndef HYPERVISOR_VIRT_START
@@ -123,13 +114,11 @@ struct arch_shared_info {
 #endif  /* !__ASSEMBLY__ */
 
 #ifdef CONFIG_X86_32
-#include <asm/xen/interface_32.h>
+#include "interface_32.h"
 #else
-#include <asm/xen/interface_64.h>
+#include "interface_64.h"
 #endif
 
-#include <asm/pvclock-abi.h>
-
 #ifndef __ASSEMBLY__
 /*
  * The following is all CPU context. Note that the fpu_ctxt block is filled
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 472b9b78301..7ff4669580c 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -12,7 +12,6 @@
 #include <asm/pgtable.h>
 
 #include <xen/interface/xen.h>
-#include <xen/grant_table.h>
 #include <xen/features.h>
 
 /* Xen machine address */
@@ -44,18 +43,19 @@ extern unsigned long  machine_to_phys_nr;
 
 extern unsigned long get_phys_to_machine(unsigned long pfn);
 extern bool set_phys_to_machine(unsigned long pfn, unsigned long mfn);
-extern bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn);
 extern bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn);
 extern unsigned long set_phys_range_identity(unsigned long pfn_s,
                                              unsigned long pfn_e);
 
 extern int m2p_add_override(unsigned long mfn, struct page *page,
-                            struct gnttab_map_grant_ref *kmap_op);
-extern int m2p_remove_override(struct page *page,
-                                struct gnttab_map_grant_ref *kmap_op);
+                            bool clear_pte);
+extern int m2p_remove_override(struct page *page, bool clear_pte);
 extern struct page *m2p_find_override(unsigned long mfn);
 extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn);
 
+#ifdef CONFIG_XEN_DEBUG_FS
+extern int p2m_dump_show(struct seq_file *m, void *v);
+#endif
 static inline unsigned long pfn_to_mfn(unsigned long pfn)
 {
         unsigned long mfn;
diff --git a/arch/x86/include/asm/xen/swiotlb-xen.h b/arch/x86/include/asm/xen/swiotlb-xen.h
index ee52fcac6f7..1be1ab7d6a4 100644
--- a/arch/x86/include/asm/xen/swiotlb-xen.h
+++ b/arch/x86/include/asm/xen/swiotlb-xen.h
@@ -5,12 +5,10 @@
 extern int xen_swiotlb;
 extern int __init pci_xen_swiotlb_detect(void);
 extern void __init pci_xen_swiotlb_init(void);
-extern int pci_xen_swiotlb_init_late(void);
 #else
 #define xen_swiotlb (0)
 static inline int __init pci_xen_swiotlb_detect(void) { return 0; }
 static inline void __init pci_xen_swiotlb_init(void) { }
-static inline int pci_xen_swiotlb_init_late(void) { return -ENXIO; }
 #endif
 
 #endif /* _ASM_X86_SWIOTLB_XEN_H */
diff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h
index f8fde90bc45..7fcf6f3dbcc 100644
--- a/arch/x86/include/asm/xor.h
+++ b/arch/x86/include/asm/xor.h
@@ -3,8 +3,8 @@
 # include <asm-generic/xor.h>
 #else
 #ifdef CONFIG_X86_32
-# include <asm/xor_32.h>
+# include "xor_32.h"
 #else
-# include <asm/xor_64.h>
+# include "xor_64.h"
 #endif
 #endif
diff --git a/arch/x86/include/asm/xor_32.h b/arch/x86/include/asm/xor_32.h
index f79cb7ec0e0..133b40a0f49 100644
--- a/arch/x86/include/asm/xor_32.h
+++ b/arch/x86/include/asm/xor_32.h
@@ -534,6 +534,38 @@ static struct xor_block_template xor_block_p5_mmx = {
  * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
  */
 
+#define XMMS_SAVE                               \
+do {                                            \
+        preempt_disable();                      \
+        cr0 = read_cr0();                       \
+        clts();                                 \
+        asm volatile(                           \
+                "movups %%xmm0,(%0)     ;\n\t"  \
+                "movups %%xmm1,0x10(%0) ;\n\t"  \
+                "movups %%xmm2,0x20(%0) ;\n\t"  \
+                "movups %%xmm3,0x30(%0) ;\n\t"  \
+                :                               \
+                : "r" (xmm_save)                \
+                : "memory");                    \
+} while (0)
+
+#define XMMS_RESTORE                            \
+do {                                            \
+        asm volatile(                           \
+                "sfence                 ;\n\t"  \
+                "movups (%0),%%xmm0     ;\n\t"  \
+                "movups 0x10(%0),%%xmm1 ;\n\t"  \
+                "movups 0x20(%0),%%xmm2 ;\n\t"  \
+                "movups 0x30(%0),%%xmm3 ;\n\t"  \
+                :                               \
+                : "r" (xmm_save)                \
+                : "memory");                    \
+        write_cr0(cr0);                         \
+        preempt_enable();                       \
+} while (0)
+
+#define ALIGN16 __attribute__((aligned(16)))
+
 #define OFFS(x)         "16*("#x")"
 #define PF_OFFS(x)      "256+16*("#x")"
 #define PF0(x)          "       prefetchnta "PF_OFFS(x)"(%1)            ;\n"
@@ -555,8 +587,10 @@ static void
 xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
 {
         unsigned long lines = bytes >> 8;
+        char xmm_save[16*4] ALIGN16;
+        int cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -599,7 +633,7 @@ xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
         :
         : "memory");
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -607,8 +641,10 @@ xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3)
 {
         unsigned long lines = bytes >> 8;
+        char xmm_save[16*4] ALIGN16;
+        int cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -658,7 +694,7 @@ xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
         :
         : "memory" );
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -666,8 +702,10 @@ xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3, unsigned long *p4)
 {
         unsigned long lines = bytes >> 8;
+        char xmm_save[16*4] ALIGN16;
+        int cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -724,7 +762,7 @@ xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
         :
         : "memory" );
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -732,8 +770,10 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3, unsigned long *p4, unsigned long *p5)
 {
         unsigned long lines = bytes >> 8;
+        char xmm_save[16*4] ALIGN16;
+        int cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         /* Make sure GCC forgets anything it knows about p4 or p5,
            such that it won't pass to the asm volatile below a
@@ -810,7 +850,7 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
            like assuming they have some legal value.  */
         asm("" : "=r" (p4), "=r" (p5));
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static struct xor_block_template xor_block_pIII_sse = {
@@ -821,9 +861,6 @@ static struct xor_block_template xor_block_pIII_sse = {
         .do_5 = xor_sse_5,
 };
 
-/* Also try the AVX routines */
-#include <asm/xor_avx.h>
-
 /* Also try the generic routines.  */
 #include <asm-generic/xor.h>
 
@@ -834,7 +871,6 @@ do {							\
         xor_speed(&xor_block_8regs_p);                  \
         xor_speed(&xor_block_32regs);                   \
         xor_speed(&xor_block_32regs_p);                 \
-        AVX_XOR_SPEED;                                  \
         if (cpu_has_xmm)                                \
                 xor_speed(&xor_block_pIII_sse);         \
         if (cpu_has_mmx) {                              \
@@ -847,6 +883,6 @@ do {							\
    We may also be able to load into the L1 only depending on how the cpu
    deals with a load to a line that is being prefetched.  */
 #define XOR_SELECT_TEMPLATE(FASTEST)                    \
-        AVX_SELECT(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
+        (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
 
 #endif /* _ASM_X86_XOR_32_H */
diff --git a/arch/x86/include/asm/xor_64.h b/arch/x86/include/asm/xor_64.h
index 87ac522c4af..1549b5e261f 100644
--- a/arch/x86/include/asm/xor_64.h
+++ b/arch/x86/include/asm/xor_64.h
@@ -34,7 +34,41 @@
  * no advantages to be gotten from x86-64 here anyways.
  */
 
-#include <asm/i387.h>
+typedef struct {
+        unsigned long a, b;
+} __attribute__((aligned(16))) xmm_store_t;
+
+/* Doesn't use gcc to save the XMM registers, because there is no easy way to
+   tell it to do a clts before the register saving. */
+#define XMMS_SAVE                               \
+do {                                            \
+        preempt_disable();                      \
+        asm volatile(                           \
+                "movq %%cr0,%0          ;\n\t"  \
+                "clts                   ;\n\t"  \
+                "movups %%xmm0,(%1)     ;\n\t"  \
+                "movups %%xmm1,0x10(%1) ;\n\t"  \
+                "movups %%xmm2,0x20(%1) ;\n\t"  \
+                "movups %%xmm3,0x30(%1) ;\n\t"  \
+                : "=&r" (cr0)                   \
+                : "r" (xmm_save)                \
+                : "memory");                    \
+} while (0)
+
+#define XMMS_RESTORE                            \
+do {                                            \
+        asm volatile(                           \
+                "sfence                 ;\n\t"  \
+                "movups (%1),%%xmm0     ;\n\t"  \
+                "movups 0x10(%1),%%xmm1 ;\n\t"  \
+                "movups 0x20(%1),%%xmm2 ;\n\t"  \
+                "movups 0x30(%1),%%xmm3 ;\n\t"  \
+                "movq   %0,%%cr0        ;\n\t"  \
+                :                               \
+                : "r" (cr0), "r" (xmm_save)     \
+                : "memory");                    \
+        preempt_enable();                       \
+} while (0)
 
 #define OFFS(x)         "16*("#x")"
 #define PF_OFFS(x)      "256+16*("#x")"
@@ -57,8 +91,10 @@ static void
 xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
 {
         unsigned int lines = bytes >> 8;
+        unsigned long cr0;
+        xmm_store_t xmm_save[4];
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -99,7 +135,7 @@ xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
         : [inc] "r" (256UL)
         : "memory");
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -107,8 +143,11 @@ xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3)
 {
         unsigned int lines = bytes >> 8;
+        xmm_store_t xmm_save[4];
+        unsigned long cr0;
+
+        XMMS_SAVE;
 
-        kernel_fpu_begin();
         asm volatile(
 #undef BLOCK
 #define BLOCK(i) \
@@ -155,7 +194,7 @@ xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
         : [inc] "r" (256UL)
         : "memory");
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -163,8 +202,10 @@ xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3, unsigned long *p4)
 {
         unsigned int lines = bytes >> 8;
+        xmm_store_t xmm_save[4];
+        unsigned long cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -220,7 +261,7 @@ xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
         : [inc] "r" (256UL)
         : "memory" );
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static void
@@ -228,8 +269,10 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
           unsigned long *p3, unsigned long *p4, unsigned long *p5)
 {
         unsigned int lines = bytes >> 8;
+        xmm_store_t xmm_save[4];
+        unsigned long cr0;
 
-        kernel_fpu_begin();
+        XMMS_SAVE;
 
         asm volatile(
 #undef BLOCK
@@ -293,7 +336,7 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
         : [inc] "r" (256UL)
         : "memory");
 
-        kernel_fpu_end();
+        XMMS_RESTORE;
 }
 
 static struct xor_block_template xor_block_sse = {
@@ -304,21 +347,15 @@ static struct xor_block_template xor_block_sse = {
         .do_5 = xor_sse_5,
 };
 
-
-/* Also try the AVX routines */
-#include <asm/xor_avx.h>
-
 #undef XOR_TRY_TEMPLATES
 #define XOR_TRY_TEMPLATES                       \
 do {                                            \
-        AVX_XOR_SPEED;                          \
         xor_speed(&xor_block_sse);              \
 } while (0)
 
 /* We force the use of the SSE xor block because it can write around L2.
    We may also be able to load into the L1 only depending on how the cpu
    deals with a load to a line that is being prefetched.  */
-#define XOR_SELECT_TEMPLATE(FASTEST) \
-        AVX_SELECT(&xor_block_sse)
+#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
 
 #endif /* _ASM_X86_XOR_64_H */
diff --git a/arch/x86/include/asm/xor_avx.h b/arch/x86/include/asm/xor_avx.h
deleted file mode 100644
index 7ea79c5fa1f..00000000000
--- a/arch/x86/include/asm/xor_avx.h
+++ /dev/null
@@ -1,184 +0,0 @@
-#ifndef _ASM_X86_XOR_AVX_H
-#define _ASM_X86_XOR_AVX_H
-
-/*
- * Optimized RAID-5 checksumming functions for AVX
- *
- * Copyright (C) 2012 Intel Corporation
- * Author: Jim Kukunas <james.t.kukunas@linux.intel.com>
- *
- * Based on Ingo Molnar and Zach Brown's respective MMX and SSE routines
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2
- * of the License.
- */
-
-#ifdef CONFIG_AS_AVX
-
-#include <linux/compiler.h>
-#include <asm/i387.h>
-
-#define BLOCK4(i) \
-                BLOCK(32 * i, 0) \
-                BLOCK(32 * (i + 1), 1) \
-                BLOCK(32 * (i + 2), 2) \
-                BLOCK(32 * (i + 3), 3)
-
-#define BLOCK16() \
-                BLOCK4(0) \
-                BLOCK4(4) \
-                BLOCK4(8) \
-                BLOCK4(12)
-
-static void xor_avx_2(unsigned long bytes, unsigned long *p0, unsigned long *p1)
-{
-        unsigned long lines = bytes >> 9;
-
-        kernel_fpu_begin();
-
-        while (lines--) {
-#undef BLOCK
-#define BLOCK(i, reg) \
-do { \
-        asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm"  #reg : : \
-                "m" (p0[i / sizeof(*p0)])); \
-        asm volatile("vmovdqa %%ymm" #reg ", %0" : \
-                "=m" (p0[i / sizeof(*p0)])); \
-} while (0);
-
-                BLOCK16()
-
-                p0 = (unsigned long *)((uintptr_t)p0 + 512);
-                p1 = (unsigned long *)((uintptr_t)p1 + 512);
-        }
-
-        kernel_fpu_end();
-}
-
-static void xor_avx_3(unsigned long bytes, unsigned long *p0, unsigned long *p1,
-        unsigned long *p2)
-{
-        unsigned long lines = bytes >> 9;
-
-        kernel_fpu_begin();
-
-        while (lines--) {
-#undef BLOCK
-#define BLOCK(i, reg) \
-do { \
-        asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p1[i / sizeof(*p1)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p0[i / sizeof(*p0)])); \
-        asm volatile("vmovdqa %%ymm" #reg ", %0" : \
-                "=m" (p0[i / sizeof(*p0)])); \
-} while (0);
-
-                BLOCK16()
-
-                p0 = (unsigned long *)((uintptr_t)p0 + 512);
-                p1 = (unsigned long *)((uintptr_t)p1 + 512);
-                p2 = (unsigned long *)((uintptr_t)p2 + 512);
-        }
-
-        kernel_fpu_end();
-}
-
-static void xor_avx_4(unsigned long bytes, unsigned long *p0, unsigned long *p1,
-        unsigned long *p2, unsigned long *p3)
-{
-        unsigned long lines = bytes >> 9;
-
-        kernel_fpu_begin();
-
-        while (lines--) {
-#undef BLOCK
-#define BLOCK(i, reg) \
-do { \
-        asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p3[i / sizeof(*p3)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p2[i / sizeof(*p2)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p1[i / sizeof(*p1)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p0[i / sizeof(*p0)])); \
-        asm volatile("vmovdqa %%ymm" #reg ", %0" : \
-                "=m" (p0[i / sizeof(*p0)])); \
-} while (0);
-
-                BLOCK16();
-
-                p0 = (unsigned long *)((uintptr_t)p0 + 512);
-                p1 = (unsigned long *)((uintptr_t)p1 + 512);
-                p2 = (unsigned long *)((uintptr_t)p2 + 512);
-                p3 = (unsigned long *)((uintptr_t)p3 + 512);
-        }
-
-        kernel_fpu_end();
-}
-
-static void xor_avx_5(unsigned long bytes, unsigned long *p0, unsigned long *p1,
-        unsigned long *p2, unsigned long *p3, unsigned long *p4)
-{
-        unsigned long lines = bytes >> 9;
-
-        kernel_fpu_begin();
-
-        while (lines--) {
-#undef BLOCK
-#define BLOCK(i, reg) \
-do { \
-        asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p4[i / sizeof(*p4)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p3[i / sizeof(*p3)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p2[i / sizeof(*p2)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p1[i / sizeof(*p1)])); \
-        asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
-                "m" (p0[i / sizeof(*p0)])); \
-        asm volatile("vmovdqa %%ymm" #reg ", %0" : \
-                "=m" (p0[i / sizeof(*p0)])); \
-} while (0);
-
-                BLOCK16()
-
-                p0 = (unsigned long *)((uintptr_t)p0 + 512);
-                p1 = (unsigned long *)((uintptr_t)p1 + 512);
-                p2 = (unsigned long *)((uintptr_t)p2 + 512);
-                p3 = (unsigned long *)((uintptr_t)p3 + 512);
-                p4 = (unsigned long *)((uintptr_t)p4 + 512);
-        }
-
-        kernel_fpu_end();
-}
-
-static struct xor_block_template xor_block_avx = {
-        .name = "avx",
-        .do_2 = xor_avx_2,
-        .do_3 = xor_avx_3,
-        .do_4 = xor_avx_4,
-        .do_5 = xor_avx_5,
-};
-
-#define AVX_XOR_SPEED \
-do { \
-        if (cpu_has_avx) \
-                xor_speed(&xor_block_avx); \
-} while (0)
-
-#define AVX_SELECT(FASTEST) \
-        (cpu_has_avx ? &xor_block_avx : FASTEST)
-
-#else
-
-#define AVX_XOR_SPEED {}
-
-#define AVX_SELECT(FASTEST) (FASTEST)
-
-#endif
-#endif
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cdabb5a..c6ce2452f10 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -34,14 +34,17 @@
 extern unsigned int xstate_size;
 extern u64 pcntxt_mask;
 extern u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS];
-extern struct xsave_struct *init_xstate_buf;
 
 extern void xsave_init(void);
 extern void update_regset_xstate_info(unsigned int size, u64 xstate_mask);
 extern int init_fpu(struct task_struct *child);
+extern int check_for_xstate(struct i387_fxsave_struct __user *buf,
+                            void __user *fpstate,
+                            struct _fpx_sw_bytes *sw);
 
-static inline int fpu_xrstor_checking(struct xsave_struct *fx)
+static inline int fpu_xrstor_checking(struct fpu *fpu)
 {
+        struct xsave_struct *fx = &fpu->state->xsave;
         int err;
 
         asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
@@ -66,21 +69,27 @@ static inline int xsave_user(struct xsave_struct __user *buf)
          * Clear the xsave header first, so that reserved fields are
          * initialized to zero.
          */
-        err = __clear_user(&buf->xsave_hdr, sizeof(buf->xsave_hdr));
+        err = __clear_user(&buf->xsave_hdr,
+                           sizeof(struct xsave_hdr_struct));
         if (unlikely(err))
                 return -EFAULT;
 
-        __asm__ __volatile__(ASM_STAC "\n"
-                             "1: .byte " REX_PREFIX "0x0f,0xae,0x27\n"
-                             "2: " ASM_CLAC "\n"
+        __asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x27\n"
+                             "2:\n"
                              ".section .fixup,\"ax\"\n"
                              "3:  movl $-1,%[err]\n"
                              "    jmp  2b\n"
                              ".previous\n"
-                             _ASM_EXTABLE(1b,3b)
+                             ".section __ex_table,\"a\"\n"
+                             _ASM_ALIGN "\n"
+                             _ASM_PTR "1b,3b\n"
+                             ".previous"
                              : [err] "=r" (err)
                              : "D" (buf), "a" (-1), "d" (-1), "0" (0)
                              : "memory");
+        if (unlikely(err) && __clear_user(buf, xstate_size))
+                err = -EFAULT;
+        /* No need to clear here because the caller clears USED_MATH */
         return err;
 }
 
@@ -91,14 +100,16 @@ static inline int xrestore_user(struct xsave_struct __user *buf, u64 mask)
         u32 lmask = mask;
         u32 hmask = mask >> 32;
 
-        __asm__ __volatile__(ASM_STAC "\n"
-                             "1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n"
-                             "2: " ASM_CLAC "\n"
+        __asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n"
+                             "2:\n"
                              ".section .fixup,\"ax\"\n"
                              "3:  movl $-1,%[err]\n"
                              "    jmp  2b\n"
                              ".previous\n"
-                             _ASM_EXTABLE(1b,3b)
+                             ".section __ex_table,\"a\"\n"
+                             _ASM_ALIGN "\n"
+                             _ASM_PTR "1b,3b\n"
+                             ".previous"
                              : [err] "=r" (err)
                              : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0)
                              : "memory");       /* memory required? */
diff --git a/arch/x86/include/uapi/asm/Kbuild b/arch/x86/include/uapi/asm/Kbuild
deleted file mode 100644
index 09409c44f9a..00000000000
--- a/arch/x86/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,64 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-genhdr-y += unistd_32.h
-genhdr-y += unistd_64.h
-genhdr-y += unistd_x32.h
-header-y += a.out.h
-header-y += auxvec.h
-header-y += bitsperlong.h
-header-y += boot.h
-header-y += bootparam.h
-header-y += byteorder.h
-header-y += debugreg.h
-header-y += e820.h
-header-y += errno.h
-header-y += fcntl.h
-header-y += hw_breakpoint.h
-header-y += hyperv.h
-header-y += ioctl.h
-header-y += ioctls.h
-header-y += ipcbuf.h
-header-y += ist.h
-header-y += kvm.h
-header-y += kvm_para.h
-header-y += ldt.h
-header-y += mce.h
-header-y += mman.h
-header-y += msgbuf.h
-header-y += msr-index.h
-header-y += msr.h
-header-y += mtrr.h
-header-y += param.h
-header-y += perf_regs.h
-header-y += poll.h
-header-y += posix_types.h
-header-y += posix_types_32.h
-header-y += posix_types_64.h
-header-y += posix_types_x32.h
-header-y += prctl.h
-header-y += processor-flags.h
-header-y += ptrace-abi.h
-header-y += ptrace.h
-header-y += resource.h
-header-y += sembuf.h
-header-y += setup.h
-header-y += shmbuf.h
-header-y += sigcontext.h
-header-y += sigcontext32.h
-header-y += siginfo.h
-header-y += signal.h
-header-y += socket.h
-header-y += sockios.h
-header-y += stat.h
-header-y += statfs.h
-header-y += svm.h
-header-y += swab.h
-header-y += termbits.h
-header-y += termios.h
-header-y += types.h
-header-y += ucontext.h
-header-y += unistd.h
-header-y += vm86.h
-header-y += vmx.h
-header-y += vsyscall.h
diff --git a/arch/x86/include/uapi/asm/a.out.h b/arch/x86/include/uapi/asm/a.out.h
deleted file mode 100644
index 4684f97a5bb..00000000000
--- a/arch/x86/include/uapi/asm/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_X86_A_OUT_H
-#define _ASM_X86_A_OUT_H
-
-struct exec
-{
-        unsigned int a_info;    /* Use macros N_MAGIC, etc for access */
-        unsigned a_text;        /* length of text, in bytes */
-        unsigned a_data;        /* length of data, in bytes */
-        unsigned a_bss;         /* length of uninitialized data area for file, in bytes */
-        unsigned a_syms;        /* length of symbol table data in file, in bytes */
-        unsigned a_entry;       /* start address */
-        unsigned a_trsize;      /* length of relocation info for text, in bytes */
-        unsigned a_drsize;      /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* _ASM_X86_A_OUT_H */
diff --git a/arch/x86/include/uapi/asm/auxvec.h b/arch/x86/include/uapi/asm/auxvec.h
deleted file mode 100644
index 77203ac352d..00000000000
--- a/arch/x86/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_X86_AUXVEC_H
-#define _ASM_X86_AUXVEC_H
-/*
- * Architecture-neutral AT_ values in 0-17, leave some room
- * for more of them, start the x86-specific ones at 32.
- */
-#ifdef __i386__
-#define AT_SYSINFO              32
-#endif
-#define AT_SYSINFO_EHDR         33
-
-/* entries in ARCH_DLINFO: */
-#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64)
-# define AT_VECTOR_SIZE_ARCH 2
-#else /* else it's non-compat x86-64 */
-# define AT_VECTOR_SIZE_ARCH 1
-#endif
-
-#endif /* _ASM_X86_AUXVEC_H */
diff --git a/arch/x86/include/uapi/asm/bitsperlong.h b/arch/x86/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index b0ae1c4dc79..00000000000
--- a/arch/x86/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_X86_BITSPERLONG_H
-#define __ASM_X86_BITSPERLONG_H
-
-#ifdef __x86_64__
-# define __BITS_PER_LONG 64
-#else
-# define __BITS_PER_LONG 32
-#endif
-
-#include <asm-generic/bitsperlong.h>
-
-#endif /* __ASM_X86_BITSPERLONG_H */
-
diff --git a/arch/x86/include/uapi/asm/boot.h b/arch/x86/include/uapi/asm/boot.h
deleted file mode 100644
index 94292c4c812..00000000000
--- a/arch/x86/include/uapi/asm/boot.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _UAPI_ASM_X86_BOOT_H
-#define _UAPI_ASM_X86_BOOT_H
-
-/* Internal svga startup constants */
-#define NORMAL_VGA      0xffff          /* 80x25 mode */
-#define EXTENDED_VGA    0xfffe          /* 80x50 mode */
-#define ASK_VGA         0xfffd          /* ask for it at bootup */
-
-
-#endif /* _UAPI_ASM_X86_BOOT_H */
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
deleted file mode 100644
index 92862cd9020..00000000000
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ /dev/null
@@ -1,139 +0,0 @@
-#ifndef _ASM_X86_BOOTPARAM_H
-#define _ASM_X86_BOOTPARAM_H
-
-#include <linux/types.h>
-#include <linux/screen_info.h>
-#include <linux/apm_bios.h>
-#include <linux/edd.h>
-#include <asm/e820.h>
-#include <asm/ist.h>
-#include <video/edid.h>
-
-/* setup data types */
-#define SETUP_NONE                      0
-#define SETUP_E820_EXT                  1
-#define SETUP_DTB                       2
-#define SETUP_PCI                       3
-
-/* extensible setup data list node */
-struct setup_data {
-        __u64 next;
-        __u32 type;
-        __u32 len;
-        __u8 data[0];
-};
-
-struct setup_header {
-        __u8    setup_sects;
-        __u16   root_flags;
-        __u32   syssize;
-        __u16   ram_size;
-#define RAMDISK_IMAGE_START_MASK        0x07FF
-#define RAMDISK_PROMPT_FLAG             0x8000
-#define RAMDISK_LOAD_FLAG               0x4000
-        __u16   vid_mode;
-        __u16   root_dev;
-        __u16   boot_flag;
-        __u16   jump;
-        __u32   header;
-        __u16   version;
-        __u32   realmode_swtch;
-        __u16   start_sys;
-        __u16   kernel_version;
-        __u8    type_of_loader;
-        __u8    loadflags;
-#define LOADED_HIGH     (1<<0)
-#define QUIET_FLAG      (1<<5)
-#define KEEP_SEGMENTS   (1<<6)
-#define CAN_USE_HEAP    (1<<7)
-        __u16   setup_move_size;
-        __u32   code32_start;
-        __u32   ramdisk_image;
-        __u32   ramdisk_size;
-        __u32   bootsect_kludge;
-        __u16   heap_end_ptr;
-        __u8    ext_loader_ver;
-        __u8    ext_loader_type;
-        __u32   cmd_line_ptr;
-        __u32   initrd_addr_max;
-        __u32   kernel_alignment;
-        __u8    relocatable_kernel;
-        __u8    _pad2[3];
-        __u32   cmdline_size;
-        __u32   hardware_subarch;
-        __u64   hardware_subarch_data;
-        __u32   payload_offset;
-        __u32   payload_length;
-        __u64   setup_data;
-        __u64   pref_address;
-        __u32   init_size;
-        __u32   handover_offset;
-} __attribute__((packed));
-
-struct sys_desc_table {
-        __u16 length;
-        __u8  table[14];
-};
-
-/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */
-struct olpc_ofw_header {
-        __u32 ofw_magic;        /* OFW signature */
-        __u32 ofw_version;
-        __u32 cif_handler;      /* callback into OFW */
-        __u32 irq_desc_table;
-} __attribute__((packed));
-
-struct efi_info {
-        __u32 efi_loader_signature;
-        __u32 efi_systab;
-        __u32 efi_memdesc_size;
-        __u32 efi_memdesc_version;
-        __u32 efi_memmap;
-        __u32 efi_memmap_size;
-        __u32 efi_systab_hi;
-        __u32 efi_memmap_hi;
-};
-
-/* The so-called "zeropage" */
-struct boot_params {
-        struct screen_info screen_info;                 /* 0x000 */
-        struct apm_bios_info apm_bios_info;             /* 0x040 */
-        __u8  _pad2[4];                                 /* 0x054 */
-        __u64  tboot_addr;                              /* 0x058 */
-        struct ist_info ist_info;                       /* 0x060 */
-        __u8  _pad3[16];                                /* 0x070 */
-        __u8  hd0_info[16];     /* obsolete! */         /* 0x080 */
-        __u8  hd1_info[16];     /* obsolete! */         /* 0x090 */
-        struct sys_desc_table sys_desc_table;           /* 0x0a0 */
-        struct olpc_ofw_header olpc_ofw_header;         /* 0x0b0 */
-        __u8  _pad4[128];                               /* 0x0c0 */
-        struct edid_info edid_info;                     /* 0x140 */
-        struct efi_info efi_info;                       /* 0x1c0 */
-        __u32 alt_mem_k;                                /* 0x1e0 */
-        __u32 scratch;          /* Scratch field! */    /* 0x1e4 */
-        __u8  e820_entries;                             /* 0x1e8 */
-        __u8  eddbuf_entries;                           /* 0x1e9 */
-        __u8  edd_mbr_sig_buf_entries;                  /* 0x1ea */
-        __u8  kbd_status;                               /* 0x1eb */
-        __u8  _pad6[5];                                 /* 0x1ec */
-        struct setup_header hdr;    /* setup header */  /* 0x1f1 */
-        __u8  _pad7[0x290-0x1f1-sizeof(struct setup_header)];
-        __u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX];      /* 0x290 */
-        struct e820entry e820_map[E820MAX];             /* 0x2d0 */
-        __u8  _pad8[48];                                /* 0xcd0 */
-        struct edd_info eddbuf[EDDMAXNR];               /* 0xd00 */
-        __u8  _pad9[276];                               /* 0xeec */
-} __attribute__((packed));
-
-enum {
-        X86_SUBARCH_PC = 0,
-        X86_SUBARCH_LGUEST,
-        X86_SUBARCH_XEN,
-        X86_SUBARCH_MRST,
-        X86_SUBARCH_CE4100,
-        X86_NR_SUBARCHS,
-};
-
-
-
-#endif /* _ASM_X86_BOOTPARAM_H */
diff --git a/arch/x86/include/uapi/asm/byteorder.h b/arch/x86/include/uapi/asm/byteorder.h
deleted file mode 100644
index b13a7a88f3e..00000000000
--- a/arch/x86/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_X86_BYTEORDER_H
-#define _ASM_X86_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _ASM_X86_BYTEORDER_H */
diff --git a/arch/x86/include/uapi/asm/debugreg.h b/arch/x86/include/uapi/asm/debugreg.h
deleted file mode 100644
index 3c0874dd986..00000000000
--- a/arch/x86/include/uapi/asm/debugreg.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef _UAPI_ASM_X86_DEBUGREG_H
-#define _UAPI_ASM_X86_DEBUGREG_H
-
-
-/* Indicate the register numbers for a number of the specific
-   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
-#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
-#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
-
-#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
-#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
-
-/* Define a few things for the status register.  We can use this to determine
-   which debugging register was responsible for the trap.  The other bits
-   are either reserved or not of interest to us. */
-
-/* Define reserved bits in DR6 which are always set to 1 */
-#define DR6_RESERVED    (0xFFFF0FF0)
-
-#define DR_TRAP0        (0x1)           /* db0 */
-#define DR_TRAP1        (0x2)           /* db1 */
-#define DR_TRAP2        (0x4)           /* db2 */
-#define DR_TRAP3        (0x8)           /* db3 */
-#define DR_TRAP_BITS    (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
-
-#define DR_STEP         (0x4000)        /* single-step */
-#define DR_SWITCH       (0x8000)        /* task switch */
-
-/* Now define a bunch of things for manipulating the control register.
-   The top two bytes of the control register consist of 4 fields of 4
-   bits - each field corresponds to one of the four debug registers,
-   and indicates what types of access we trap on, and how large the data
-   field is that we are looking at */
-
-#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
-#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
-
-#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
-#define DR_RW_WRITE (0x1)
-#define DR_RW_READ (0x3)
-
-#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
-#define DR_LEN_2 (0x4)
-#define DR_LEN_4 (0xC)
-#define DR_LEN_8 (0x8)
-
-/* The low byte to the control register determine which registers are
-   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
-   that the processor will reset the bit after a task switch and the other
-   is global meaning that we have to explicitly reset the bit.  With linux,
-   you can use either one, since we explicitly zero the register when we enter
-   kernel mode. */
-
-#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
-#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
-#define DR_LOCAL_ENABLE (0x1)      /* Local enable for reg 0 */
-#define DR_GLOBAL_ENABLE (0x2)     /* Global enable for reg 0 */
-#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
-
-#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
-#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
-
-/* The second byte to the control register has a few special things.
-   We can slow the instruction pipeline for instructions coming via the
-   gdt or the ldt if we want to.  I am not sure why this is an advantage */
-
-#ifdef __i386__
-#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
-#else
-#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
-#endif
-
-#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
-#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
-
-/*
- * HW breakpoint additions
- */
-
-#endif /* _UAPI_ASM_X86_DEBUGREG_H */
diff --git a/arch/x86/include/uapi/asm/e820.h b/arch/x86/include/uapi/asm/e820.h
deleted file mode 100644
index bbae0247070..00000000000
--- a/arch/x86/include/uapi/asm/e820.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef _UAPI_ASM_X86_E820_H
-#define _UAPI_ASM_X86_E820_H
-#define E820MAP 0x2d0           /* our map */
-#define E820MAX 128             /* number of entries in E820MAP */
-
-/*
- * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
- * constrained space in the zeropage.  If we have more nodes than
- * that, and if we've booted off EFI firmware, then the EFI tables
- * passed us from the EFI firmware can list more nodes.  Size our
- * internal memory map tables to have room for these additional
- * nodes, based on up to three entries per node for which the
- * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
- * plus E820MAX, allowing space for the possible duplicate E820
- * entries that might need room in the same arrays, prior to the
- * call to sanitize_e820_map() to remove duplicates.  The allowance
- * of three memory map entries per node is "enough" entries for
- * the initial hardware platform motivating this mechanism to make
- * use of additional EFI map entries.  Future platforms may want
- * to allow more than three entries per node or otherwise refine
- * this size.
- */
-
-/*
- * Odd: 'make headers_check' complains about numa.h if I try
- * to collapse the next two #ifdef lines to a single line:
- *      #if defined(__KERNEL__) && defined(CONFIG_EFI)
- */
-#ifndef __KERNEL__
-#define E820_X_MAX E820MAX
-#endif
-
-#define E820NR  0x1e8           /* # entries in E820MAP */
-
-#define E820_RAM        1
-#define E820_RESERVED   2
-#define E820_ACPI       3
-#define E820_NVS        4
-#define E820_UNUSABLE   5
-
-
-/*
- * reserved RAM used by kernel itself
- * if CONFIG_INTEL_TXT is enabled, memory of this type will be
- * included in the S3 integrity calculation and so should not include
- * any memory that BIOS might alter over the S3 transition
- */
-#define E820_RESERVED_KERN        128
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-struct e820entry {
-        __u64 addr;     /* start of memory segment */
-        __u64 size;     /* size of memory segment */
-        __u32 type;     /* type of memory segment */
-} __attribute__((packed));
-
-struct e820map {
-        __u32 nr_map;
-        struct e820entry map[E820_X_MAX];
-};
-
-#define ISA_START_ADDRESS       0xa0000
-#define ISA_END_ADDRESS         0x100000
-
-#define BIOS_BEGIN              0x000a0000
-#define BIOS_END                0x00100000
-
-#define BIOS_ROM_BASE           0xffe00000
-#define BIOS_ROM_END            0xffffffff
-
-#endif /* __ASSEMBLY__ */
-
-
-#endif /* _UAPI_ASM_X86_E820_H */
diff --git a/arch/x86/include/uapi/asm/errno.h b/arch/x86/include/uapi/asm/errno.h
deleted file mode 100644
index 4c82b503d92..00000000000
--- a/arch/x86/include/uapi/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/arch/x86/include/uapi/asm/fcntl.h b/arch/x86/include/uapi/asm/fcntl.h
deleted file mode 100644
index 46ab12db573..00000000000
--- a/arch/x86/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/fcntl.h>
diff --git a/arch/x86/include/uapi/asm/hw_breakpoint.h b/arch/x86/include/uapi/asm/hw_breakpoint.h
deleted file mode 100644
index 79a9626b550..00000000000
--- a/arch/x86/include/uapi/asm/hw_breakpoint.h
+++ /dev/null
@@ -1 +0,0 @@
-/* */
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
deleted file mode 100644
index b80420bcd09..00000000000
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ /dev/null
@@ -1,194 +0,0 @@
-#ifndef _ASM_X86_HYPERV_H
-#define _ASM_X86_HYPERV_H
-
-#include <linux/types.h>
-
-/*
- * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
- * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
- */
-#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
-#define HYPERV_CPUID_INTERFACE                  0x40000001
-#define HYPERV_CPUID_VERSION                    0x40000002
-#define HYPERV_CPUID_FEATURES                   0x40000003
-#define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
-#define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
-
-#define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
-#define HYPERV_CPUID_MIN                        0x40000005
-#define HYPERV_CPUID_MAX                        0x4000ffff
-
-/*
- * Feature identification. EAX indicates which features are available
- * to the partition based upon the current partition privileges.
- */
-
-/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
-#define HV_X64_MSR_VP_RUNTIME_AVAILABLE         (1 << 0)
-/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
-#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE     (1 << 1)
-/*
- * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
- * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
- */
-#define HV_X64_MSR_SYNIC_AVAILABLE              (1 << 2)
-/*
- * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
- * HV_X64_MSR_STIMER3_COUNT) available
- */
-#define HV_X64_MSR_SYNTIMER_AVAILABLE           (1 << 3)
-/*
- * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
- * are available
- */
-#define HV_X64_MSR_APIC_ACCESS_AVAILABLE        (1 << 4)
-/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
-#define HV_X64_MSR_HYPERCALL_AVAILABLE          (1 << 5)
-/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
-#define HV_X64_MSR_VP_INDEX_AVAILABLE           (1 << 6)
-/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
-#define HV_X64_MSR_RESET_AVAILABLE              (1 << 7)
- /*
-  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
-  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
-  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
-  */
-#define HV_X64_MSR_STAT_PAGES_AVAILABLE         (1 << 8)
-
-/*
- * Feature identification: EBX indicates which flags were specified at
- * partition creation. The format is the same as the partition creation
- * flag structure defined in section Partition Creation Flags.
- */
-#define HV_X64_CREATE_PARTITIONS                (1 << 0)
-#define HV_X64_ACCESS_PARTITION_ID              (1 << 1)
-#define HV_X64_ACCESS_MEMORY_POOL               (1 << 2)
-#define HV_X64_ADJUST_MESSAGE_BUFFERS           (1 << 3)
-#define HV_X64_POST_MESSAGES                    (1 << 4)
-#define HV_X64_SIGNAL_EVENTS                    (1 << 5)
-#define HV_X64_CREATE_PORT                      (1 << 6)
-#define HV_X64_CONNECT_PORT                     (1 << 7)
-#define HV_X64_ACCESS_STATS                     (1 << 8)
-#define HV_X64_DEBUGGING                        (1 << 11)
-#define HV_X64_CPU_POWER_MANAGEMENT             (1 << 12)
-#define HV_X64_CONFIGURE_PROFILER               (1 << 13)
-
-/*
- * Feature identification. EDX indicates which miscellaneous features
- * are available to the partition.
- */
-/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
-#define HV_X64_MWAIT_AVAILABLE                          (1 << 0)
-/* Guest debugging support is available */
-#define HV_X64_GUEST_DEBUGGING_AVAILABLE                (1 << 1)
-/* Performance Monitor support is available*/
-#define HV_X64_PERF_MONITOR_AVAILABLE                   (1 << 2)
-/* Support for physical CPU dynamic partitioning events is available*/
-#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       (1 << 3)
-/*
- * Support for passing hypercall input parameter block via XMM
- * registers is available
- */
-#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           (1 << 4)
-/* Support for a virtual guest idle state is available */
-#define HV_X64_GUEST_IDLE_STATE_AVAILABLE               (1 << 5)
-
-/*
- * Implementation recommendations. Indicates which behaviors the hypervisor
- * recommends the OS implement for optimal performance.
- */
- /*
-  * Recommend using hypercall for address space switches rather
-  * than MOV to CR3 instruction
-  */
-#define HV_X64_MWAIT_RECOMMENDED                (1 << 0)
-/* Recommend using hypercall for local TLB flushes rather
- * than INVLPG or MOV to CR3 instructions */
-#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED      (1 << 1)
-/*
- * Recommend using hypercall for remote TLB flushes rather
- * than inter-processor interrupts
- */
-#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED     (1 << 2)
-/*
- * Recommend using MSRs for accessing APIC registers
- * EOI, ICR and TPR rather than their memory-mapped counterparts
- */
-#define HV_X64_APIC_ACCESS_RECOMMENDED          (1 << 3)
-/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
-#define HV_X64_SYSTEM_RESET_RECOMMENDED         (1 << 4)
-/*
- * Recommend using relaxed timing for this partition. If used,
- * the VM should disable any watchdog timeouts that rely on the
- * timely delivery of external interrupts
- */
-#define HV_X64_RELAXED_TIMING_RECOMMENDED       (1 << 5)
-
-/* MSR used to identify the guest OS. */
-#define HV_X64_MSR_GUEST_OS_ID                  0x40000000
-
-/* MSR used to setup pages used to communicate with the hypervisor. */
-#define HV_X64_MSR_HYPERCALL                    0x40000001
-
-/* MSR used to provide vcpu index */
-#define HV_X64_MSR_VP_INDEX                     0x40000002
-
-/* MSR used to read the per-partition time reference counter */
-#define HV_X64_MSR_TIME_REF_COUNT               0x40000020
-
-/* Define the virtual APIC registers */
-#define HV_X64_MSR_EOI                          0x40000070
-#define HV_X64_MSR_ICR                          0x40000071
-#define HV_X64_MSR_TPR                          0x40000072
-#define HV_X64_MSR_APIC_ASSIST_PAGE             0x40000073
-
-/* Define synthetic interrupt controller model specific registers. */
-#define HV_X64_MSR_SCONTROL                     0x40000080
-#define HV_X64_MSR_SVERSION                     0x40000081
-#define HV_X64_MSR_SIEFP                        0x40000082
-#define HV_X64_MSR_SIMP                         0x40000083
-#define HV_X64_MSR_EOM                          0x40000084
-#define HV_X64_MSR_SINT0                        0x40000090
-#define HV_X64_MSR_SINT1                        0x40000091
-#define HV_X64_MSR_SINT2                        0x40000092
-#define HV_X64_MSR_SINT3                        0x40000093
-#define HV_X64_MSR_SINT4                        0x40000094
-#define HV_X64_MSR_SINT5                        0x40000095
-#define HV_X64_MSR_SINT6                        0x40000096
-#define HV_X64_MSR_SINT7                        0x40000097
-#define HV_X64_MSR_SINT8                        0x40000098
-#define HV_X64_MSR_SINT9                        0x40000099
-#define HV_X64_MSR_SINT10                       0x4000009A
-#define HV_X64_MSR_SINT11                       0x4000009B
-#define HV_X64_MSR_SINT12                       0x4000009C
-#define HV_X64_MSR_SINT13                       0x4000009D
-#define HV_X64_MSR_SINT14                       0x4000009E
-#define HV_X64_MSR_SINT15                       0x4000009F
-
-
-#define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
-#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
-#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
-                (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
-
-/* Declare the various hypercall operations. */
-#define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT         0x0008
-
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE              0x00000001
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT       12
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK        \
-                (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
-
-#define HV_PROCESSOR_POWER_STATE_C0             0
-#define HV_PROCESSOR_POWER_STATE_C1             1
-#define HV_PROCESSOR_POWER_STATE_C2             2
-#define HV_PROCESSOR_POWER_STATE_C3             3
-
-/* hypercall status code */
-#define HV_STATUS_SUCCESS                       0
-#define HV_STATUS_INVALID_HYPERCALL_CODE        2
-#define HV_STATUS_INVALID_HYPERCALL_INPUT       3
-#define HV_STATUS_INVALID_ALIGNMENT             4
-#define HV_STATUS_INSUFFICIENT_BUFFERS          19
-
-#endif
diff --git a/arch/x86/include/uapi/asm/ioctl.h b/arch/x86/include/uapi/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe..00000000000
--- a/arch/x86/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/arch/x86/include/uapi/asm/ioctls.h b/arch/x86/include/uapi/asm/ioctls.h
deleted file mode 100644
index ec34c760665..00000000000
--- a/arch/x86/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctls.h>
diff --git a/arch/x86/include/uapi/asm/ipcbuf.h b/arch/x86/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d..00000000000
--- a/arch/x86/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/x86/include/uapi/asm/ist.h b/arch/x86/include/uapi/asm/ist.h
deleted file mode 100644
index bad9f5ea407..00000000000
--- a/arch/x86/include/uapi/asm/ist.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Include file for the interface to IST BIOS
- * Copyright 2002 Andy Grover <andrew.grover@intel.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- */
-#ifndef _UAPI_ASM_X86_IST_H
-#define _UAPI_ASM_X86_IST_H
-
-
-
-#include <linux/types.h>
-
-struct ist_info {
-        __u32 signature;
-        __u32 command;
-        __u32 event;
-        __u32 perf_level;
-};
-
-#endif /* _UAPI_ASM_X86_IST_H */
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
deleted file mode 100644
index a65ec29e6ff..00000000000
--- a/arch/x86/include/uapi/asm/kvm.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef _ASM_X86_KVM_H
-#define _ASM_X86_KVM_H
-
-/*
- * KVM x86 specific structures and definitions
- *
- */
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-#define DE_VECTOR 0
-#define DB_VECTOR 1
-#define BP_VECTOR 3
-#define OF_VECTOR 4
-#define BR_VECTOR 5
-#define UD_VECTOR 6
-#define NM_VECTOR 7
-#define DF_VECTOR 8
-#define TS_VECTOR 10
-#define NP_VECTOR 11
-#define SS_VECTOR 12
-#define GP_VECTOR 13
-#define PF_VECTOR 14
-#define MF_VECTOR 16
-#define MC_VECTOR 18
-
-/* Select x86 specific features in <linux/kvm.h> */
-#define __KVM_HAVE_PIT
-#define __KVM_HAVE_IOAPIC
-#define __KVM_HAVE_IRQ_LINE
-#define __KVM_HAVE_DEVICE_ASSIGNMENT
-#define __KVM_HAVE_MSI
-#define __KVM_HAVE_USER_NMI
-#define __KVM_HAVE_GUEST_DEBUG
-#define __KVM_HAVE_MSIX
-#define __KVM_HAVE_MCE
-#define __KVM_HAVE_PIT_STATE2
-#define __KVM_HAVE_XEN_HVM
-#define __KVM_HAVE_VCPU_EVENTS
-#define __KVM_HAVE_DEBUGREGS
-#define __KVM_HAVE_XSAVE
-#define __KVM_HAVE_XCRS
-#define __KVM_HAVE_READONLY_MEM
-
-/* Architectural interrupt line count. */
-#define KVM_NR_INTERRUPTS 256
-
-struct kvm_memory_alias {
-        __u32 slot;  /* this has a different namespace than memory slots */
-        __u32 flags;
-        __u64 guest_phys_addr;
-        __u64 memory_size;
-        __u64 target_phys_addr;
-};
-
-/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
-struct kvm_pic_state {
-        __u8 last_irr;  /* edge detection */
-        __u8 irr;               /* interrupt request register */
-        __u8 imr;               /* interrupt mask register */
-        __u8 isr;               /* interrupt service register */
-        __u8 priority_add;      /* highest irq priority */
-        __u8 irq_base;
-        __u8 read_reg_select;
-        __u8 poll;
-        __u8 special_mask;
-        __u8 init_state;
-        __u8 auto_eoi;
-        __u8 rotate_on_auto_eoi;
-        __u8 special_fully_nested_mode;
-        __u8 init4;             /* true if 4 byte init */
-        __u8 elcr;              /* PIIX edge/trigger selection */
-        __u8 elcr_mask;
-};
-
-#define KVM_IOAPIC_NUM_PINS  24
-struct kvm_ioapic_state {
-        __u64 base_address;
-        __u32 ioregsel;
-        __u32 id;
-        __u32 irr;
-        __u32 pad;
-        union {
-                __u64 bits;
-                struct {
-                        __u8 vector;
-                        __u8 delivery_mode:3;
-                        __u8 dest_mode:1;
-                        __u8 delivery_status:1;
-                        __u8 polarity:1;
-                        __u8 remote_irr:1;
-                        __u8 trig_mode:1;
-                        __u8 mask:1;
-                        __u8 reserve:7;
-                        __u8 reserved[4];
-                        __u8 dest_id;
-                } fields;
-        } redirtbl[KVM_IOAPIC_NUM_PINS];
-};
-
-#define KVM_IRQCHIP_PIC_MASTER   0
-#define KVM_IRQCHIP_PIC_SLAVE    1
-#define KVM_IRQCHIP_IOAPIC       2
-#define KVM_NR_IRQCHIPS          3
-
-/* for KVM_GET_REGS and KVM_SET_REGS */
-struct kvm_regs {
-        /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
-        __u64 rax, rbx, rcx, rdx;
-        __u64 rsi, rdi, rsp, rbp;
-        __u64 r8,  r9,  r10, r11;
-        __u64 r12, r13, r14, r15;
-        __u64 rip, rflags;
-};
-
-/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
-#define KVM_APIC_REG_SIZE 0x400
-struct kvm_lapic_state {
-        char regs[KVM_APIC_REG_SIZE];
-};
-
-struct kvm_segment {
-        __u64 base;
-        __u32 limit;
-        __u16 selector;
-        __u8  type;
-        __u8  present, dpl, db, s, l, g, avl;
-        __u8  unusable;
-        __u8  padding;
-};
-
-struct kvm_dtable {
-        __u64 base;
-        __u16 limit;
-        __u16 padding[3];
-};
-
-
-/* for KVM_GET_SREGS and KVM_SET_SREGS */
-struct kvm_sregs {
-        /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
-        struct kvm_segment cs, ds, es, fs, gs, ss;
-        struct kvm_segment tr, ldt;
-        struct kvm_dtable gdt, idt;
-        __u64 cr0, cr2, cr3, cr4, cr8;
-        __u64 efer;
-        __u64 apic_base;
-        __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
-};
-
-/* for KVM_GET_FPU and KVM_SET_FPU */
-struct kvm_fpu {
-        __u8  fpr[8][16];
-        __u16 fcw;
-        __u16 fsw;
-        __u8  ftwx;  /* in fxsave format */
-        __u8  pad1;
-        __u16 last_opcode;
-        __u64 last_ip;
-        __u64 last_dp;
-        __u8  xmm[16][16];
-        __u32 mxcsr;
-        __u32 pad2;
-};
-
-struct kvm_msr_entry {
-        __u32 index;
-        __u32 reserved;
-        __u64 data;
-};
-
-/* for KVM_GET_MSRS and KVM_SET_MSRS */
-struct kvm_msrs {
-        __u32 nmsrs; /* number of msrs in entries */
-        __u32 pad;
-
-        struct kvm_msr_entry entries[0];
-};
-
-/* for KVM_GET_MSR_INDEX_LIST */
-struct kvm_msr_list {
-        __u32 nmsrs; /* number of msrs in entries */
-        __u32 indices[0];
-};
-
-
-struct kvm_cpuid_entry {
-        __u32 function;
-        __u32 eax;
-        __u32 ebx;
-        __u32 ecx;
-        __u32 edx;
-        __u32 padding;
-};
-
-/* for KVM_SET_CPUID */
-struct kvm_cpuid {
-        __u32 nent;
-        __u32 padding;
-        struct kvm_cpuid_entry entries[0];
-};
-
-struct kvm_cpuid_entry2 {
-        __u32 function;
-        __u32 index;
-        __u32 flags;
-        __u32 eax;
-        __u32 ebx;
-        __u32 ecx;
-        __u32 edx;
-        __u32 padding[3];
-};
-
-#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
-#define KVM_CPUID_FLAG_STATEFUL_FUNC    2
-#define KVM_CPUID_FLAG_STATE_READ_NEXT  4
-
-/* for KVM_SET_CPUID2 */
-struct kvm_cpuid2 {
-        __u32 nent;
-        __u32 padding;
-        struct kvm_cpuid_entry2 entries[0];
-};
-
-/* for KVM_GET_PIT and KVM_SET_PIT */
-struct kvm_pit_channel_state {
-        __u32 count; /* can be 65536 */
-        __u16 latched_count;
-        __u8 count_latched;
-        __u8 status_latched;
-        __u8 status;
-        __u8 read_state;
-        __u8 write_state;
-        __u8 write_latch;
-        __u8 rw_mode;
-        __u8 mode;
-        __u8 bcd;
-        __u8 gate;
-        __s64 count_load_time;
-};
-
-struct kvm_debug_exit_arch {
-        __u32 exception;
-        __u32 pad;
-        __u64 pc;
-        __u64 dr6;
-        __u64 dr7;
-};
-
-#define KVM_GUESTDBG_USE_SW_BP          0x00010000
-#define KVM_GUESTDBG_USE_HW_BP          0x00020000
-#define KVM_GUESTDBG_INJECT_DB          0x00040000
-#define KVM_GUESTDBG_INJECT_BP          0x00080000
-
-/* for KVM_SET_GUEST_DEBUG */
-struct kvm_guest_debug_arch {
-        __u64 debugreg[8];
-};
-
-struct kvm_pit_state {
-        struct kvm_pit_channel_state channels[3];
-};
-
-#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
-
-struct kvm_pit_state2 {
-        struct kvm_pit_channel_state channels[3];
-        __u32 flags;
-        __u32 reserved[9];
-};
-
-struct kvm_reinject_control {
-        __u8 pit_reinject;
-        __u8 reserved[31];
-};
-
-/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
-#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
-#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
-#define KVM_VCPUEVENT_VALID_SHADOW      0x00000004
-
-/* Interrupt shadow states */
-#define KVM_X86_SHADOW_INT_MOV_SS       0x01
-#define KVM_X86_SHADOW_INT_STI          0x02
-
-/* for KVM_GET/SET_VCPU_EVENTS */
-struct kvm_vcpu_events {
-        struct {
-                __u8 injected;
-                __u8 nr;
-                __u8 has_error_code;
-                __u8 pad;
-                __u32 error_code;
-        } exception;
-        struct {
-                __u8 injected;
-                __u8 nr;
-                __u8 soft;
-                __u8 shadow;
-        } interrupt;
-        struct {
-                __u8 injected;
-                __u8 pending;
-                __u8 masked;
-                __u8 pad;
-        } nmi;
-        __u32 sipi_vector;
-        __u32 flags;
-        __u32 reserved[10];
-};
-
-/* for KVM_GET/SET_DEBUGREGS */
-struct kvm_debugregs {
-        __u64 db[4];
-        __u64 dr6;
-        __u64 dr7;
-        __u64 flags;
-        __u64 reserved[9];
-};
-
-/* for KVM_CAP_XSAVE */
-struct kvm_xsave {
-        __u32 region[1024];
-};
-
-#define KVM_MAX_XCRS    16
-
-struct kvm_xcr {
-        __u32 xcr;
-        __u32 reserved;
-        __u64 value;
-};
-
-struct kvm_xcrs {
-        __u32 nr_xcrs;
-        __u32 flags;
-        struct kvm_xcr xcrs[KVM_MAX_XCRS];
-        __u64 padding[16];
-};
-
-/* definition of registers in kvm_run */
-struct kvm_sync_regs {
-};
-
-#endif /* _ASM_X86_KVM_H */
diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h
deleted file mode 100644
index 06fdbd987e9..00000000000
--- a/arch/x86/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef _UAPI_ASM_X86_KVM_PARA_H
-#define _UAPI_ASM_X86_KVM_PARA_H
-
-#include <linux/types.h>
-#include <asm/hyperv.h>
-
-/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
- * should be used to determine that a VM is running under KVM.
- */
-#define KVM_CPUID_SIGNATURE     0x40000000
-
-/* This CPUID returns a feature bitmap in eax.  Before enabling a particular
- * paravirtualization, the appropriate feature bit should be checked.
- */
-#define KVM_CPUID_FEATURES      0x40000001
-#define KVM_FEATURE_CLOCKSOURCE         0
-#define KVM_FEATURE_NOP_IO_DELAY        1
-#define KVM_FEATURE_MMU_OP              2
-/* This indicates that the new set of kvmclock msrs
- * are available. The use of 0x11 and 0x12 is deprecated
- */
-#define KVM_FEATURE_CLOCKSOURCE2        3
-#define KVM_FEATURE_ASYNC_PF            4
-#define KVM_FEATURE_STEAL_TIME          5
-#define KVM_FEATURE_PV_EOI              6
-
-/* The last 8 bits are used to indicate how to interpret the flags field
- * in pvclock structure. If no bits are set, all flags are ignored.
- */
-#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT      24
-
-#define MSR_KVM_WALL_CLOCK  0x11
-#define MSR_KVM_SYSTEM_TIME 0x12
-
-#define KVM_MSR_ENABLED 1
-/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
-#define MSR_KVM_WALL_CLOCK_NEW  0x4b564d00
-#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
-#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
-#define MSR_KVM_STEAL_TIME  0x4b564d03
-#define MSR_KVM_PV_EOI_EN      0x4b564d04
-
-struct kvm_steal_time {
-        __u64 steal;
-        __u32 version;
-        __u32 flags;
-        __u32 pad[12];
-};
-
-#define KVM_STEAL_ALIGNMENT_BITS 5
-#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
-#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
-
-#define KVM_MAX_MMU_OP_BATCH           32
-
-#define KVM_ASYNC_PF_ENABLED                    (1 << 0)
-#define KVM_ASYNC_PF_SEND_ALWAYS                (1 << 1)
-
-/* Operations for KVM_HC_MMU_OP */
-#define KVM_MMU_OP_WRITE_PTE            1
-#define KVM_MMU_OP_FLUSH_TLB            2
-#define KVM_MMU_OP_RELEASE_PT           3
-
-/* Payload for KVM_HC_MMU_OP */
-struct kvm_mmu_op_header {
-        __u32 op;
-        __u32 pad;
-};
-
-struct kvm_mmu_op_write_pte {
-        struct kvm_mmu_op_header header;
-        __u64 pte_phys;
-        __u64 pte_val;
-};
-
-struct kvm_mmu_op_flush_tlb {
-        struct kvm_mmu_op_header header;
-};
-
-struct kvm_mmu_op_release_pt {
-        struct kvm_mmu_op_header header;
-        __u64 pt_phys;
-};
-
-#define KVM_PV_REASON_PAGE_NOT_PRESENT 1
-#define KVM_PV_REASON_PAGE_READY 2
-
-struct kvm_vcpu_pv_apf_data {
-        __u32 reason;
-        __u8 pad[60];
-        __u32 enabled;
-};
-
-#define KVM_PV_EOI_BIT 0
-#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
-#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
-#define KVM_PV_EOI_DISABLED 0x0
-
-
-#endif /* _UAPI_ASM_X86_KVM_PARA_H */
diff --git a/arch/x86/include/uapi/asm/ldt.h b/arch/x86/include/uapi/asm/ldt.h
deleted file mode 100644
index 46727eb37bf..00000000000
--- a/arch/x86/include/uapi/asm/ldt.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * ldt.h
- *
- * Definitions of structures used with the modify_ldt system call.
- */
-#ifndef _ASM_X86_LDT_H
-#define _ASM_X86_LDT_H
-
-/* Maximum number of LDT entries supported. */
-#define LDT_ENTRIES     8192
-/* The size of each LDT entry. */
-#define LDT_ENTRY_SIZE  8
-
-#ifndef __ASSEMBLY__
-/*
- * Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
- * not to the default values if you still want to do syscalls. This
- * call is more for 32bit mode therefore.
- */
-struct user_desc {
-        unsigned int  entry_number;
-        unsigned int  base_addr;
-        unsigned int  limit;
-        unsigned int  seg_32bit:1;
-        unsigned int  contents:2;
-        unsigned int  read_exec_only:1;
-        unsigned int  limit_in_pages:1;
-        unsigned int  seg_not_present:1;
-        unsigned int  useable:1;
-#ifdef __x86_64__
-        unsigned int  lm:1;
-#endif
-};
-
-#define MODIFY_LDT_CONTENTS_DATA        0
-#define MODIFY_LDT_CONTENTS_STACK       1
-#define MODIFY_LDT_CONTENTS_CODE        2
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_X86_LDT_H */
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
deleted file mode 100644
index 58c829871c3..00000000000
--- a/arch/x86/include/uapi/asm/mce.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef _UAPI_ASM_X86_MCE_H
-#define _UAPI_ASM_X86_MCE_H
-
-#include <linux/types.h>
-#include <asm/ioctls.h>
-
-/*
- * Machine Check support for x86
- */
-
-/* MCG_CAP register defines */
-#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
-#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
-#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
-#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
-#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
-#define MCG_EXT_CNT_SHIFT       16
-#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
-#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
-
-/* MCG_STATUS register defines */
-#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
-#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
-#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
-
-/* MCi_STATUS register defines */
-#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
-#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
-#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
-#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
-#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
-#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
-#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
-#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
-#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
-#define MCACOD            0xffff     /* MCA Error Code */
-
-/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
-#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
-#define MCACOD_SCRUBMSK 0xfff0
-#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
-#define MCACOD_DATA     0x0134  /* Data Load */
-#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
-
-/* MCi_MISC register defines */
-#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
-#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
-#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
-#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
-#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
-#define  MCI_MISC_ADDR_MEM      3       /* memory address */
-#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
-
-/* CTL2 register defines */
-#define MCI_CTL2_CMCI_EN                (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
-
-#define MCJ_CTX_MASK            3
-#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
-#define MCJ_CTX_RANDOM          0    /* inject context: random */
-#define MCJ_CTX_PROCESS         0x1  /* inject context: process */
-#define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
-#define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
-#define MCJ_EXCEPTION           0x8  /* raise as exception */
-#define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
-
-/* Fields are zero when not available */
-struct mce {
-        __u64 status;
-        __u64 misc;
-        __u64 addr;
-        __u64 mcgstatus;
-        __u64 ip;
-        __u64 tsc;      /* cpu time stamp counter */
-        __u64 time;     /* wall time_t when error was detected */
-        __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
-        __u8  inject_flags;     /* software inject flags */
-        __u16  pad;
-        __u32 cpuid;    /* CPUID 1 EAX */
-        __u8  cs;               /* code segment */
-        __u8  bank;     /* machine check bank */
-        __u8  cpu;      /* cpu number; obsolete; use extcpu now */
-        __u8  finished;   /* entry is valid */
-        __u32 extcpu;   /* linux cpu number that detected the error */
-        __u32 socketid; /* CPU socket ID */
-        __u32 apicid;   /* CPU initial apic ID */
-        __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
-};
-
-/*
- * This structure contains all data related to the MCE log.  Also
- * carries a signature to make it easier to find from external
- * debugging tools.  Each entry is only valid when its finished flag
- * is set.
- */
-
-#define MCE_LOG_LEN 32
-
-struct mce_log {
-        char signature[12]; /* "MACHINECHECK" */
-        unsigned len;       /* = MCE_LOG_LEN */
-        unsigned next;
-        unsigned flags;
-        unsigned recordlen;     /* length of struct mce */
-        struct mce entry[MCE_LOG_LEN];
-};
-
-#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
-
-#define MCE_LOG_SIGNATURE       "MACHINECHECK"
-
-#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
-#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
-#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
-
-/* Software defined banks */
-#define MCE_EXTENDED_BANK       128
-#define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
-#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)
-
-#endif /* _UAPI_ASM_X86_MCE_H */
diff --git a/arch/x86/include/uapi/asm/mman.h b/arch/x86/include/uapi/asm/mman.h
deleted file mode 100644
index 513b05f15bb..00000000000
--- a/arch/x86/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_X86_MMAN_H
-#define _ASM_X86_MMAN_H
-
-#define MAP_32BIT       0x40            /* only give out 32bit addresses */
-
-#define MAP_HUGE_2MB    (21 << MAP_HUGE_SHIFT)
-#define MAP_HUGE_1GB    (30 << MAP_HUGE_SHIFT)
-
-#include <asm-generic/mman.h>
-
-#endif /* _ASM_X86_MMAN_H */
diff --git a/arch/x86/include/uapi/asm/msgbuf.h b/arch/x86/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 809134c644a..00000000000
--- a/arch/x86/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/msgbuf.h>
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
deleted file mode 100644
index 433a59fb1a7..00000000000
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ /dev/null
@@ -1,525 +0,0 @@
-#ifndef _ASM_X86_MSR_INDEX_H
-#define _ASM_X86_MSR_INDEX_H
-
-/* CPU model specific register (MSR) numbers */
-
-/* x86-64 specific MSRs */
-#define MSR_EFER                0xc0000080 /* extended feature register */
-#define MSR_STAR                0xc0000081 /* legacy mode SYSCALL target */
-#define MSR_LSTAR               0xc0000082 /* long mode SYSCALL target */
-#define MSR_CSTAR               0xc0000083 /* compat mode SYSCALL target */
-#define MSR_SYSCALL_MASK        0xc0000084 /* EFLAGS mask for syscall */
-#define MSR_FS_BASE             0xc0000100 /* 64bit FS base */
-#define MSR_GS_BASE             0xc0000101 /* 64bit GS base */
-#define MSR_KERNEL_GS_BASE      0xc0000102 /* SwapGS GS shadow */
-#define MSR_TSC_AUX             0xc0000103 /* Auxiliary TSC */
-
-/* EFER bits: */
-#define _EFER_SCE               0  /* SYSCALL/SYSRET */
-#define _EFER_LME               8  /* Long mode enable */
-#define _EFER_LMA               10 /* Long mode active (read-only) */
-#define _EFER_NX                11 /* No execute enable */
-#define _EFER_SVME              12 /* Enable virtualization */
-#define _EFER_LMSLE             13 /* Long Mode Segment Limit Enable */
-#define _EFER_FFXSR             14 /* Enable Fast FXSAVE/FXRSTOR */
-
-#define EFER_SCE                (1<<_EFER_SCE)
-#define EFER_LME                (1<<_EFER_LME)
-#define EFER_LMA                (1<<_EFER_LMA)
-#define EFER_NX                 (1<<_EFER_NX)
-#define EFER_SVME               (1<<_EFER_SVME)
-#define EFER_LMSLE              (1<<_EFER_LMSLE)
-#define EFER_FFXSR              (1<<_EFER_FFXSR)
-
-/* Intel MSRs. Some also available on other CPUs */
-#define MSR_IA32_PERFCTR0               0x000000c1
-#define MSR_IA32_PERFCTR1               0x000000c2
-#define MSR_FSB_FREQ                    0x000000cd
-#define MSR_NHM_PLATFORM_INFO           0x000000ce
-
-#define MSR_NHM_SNB_PKG_CST_CFG_CTL     0x000000e2
-#define NHM_C3_AUTO_DEMOTE              (1UL << 25)
-#define NHM_C1_AUTO_DEMOTE              (1UL << 26)
-#define ATM_LNC_C6_AUTO_DEMOTE          (1UL << 25)
-#define SNB_C1_AUTO_UNDEMOTE            (1UL << 27)
-#define SNB_C3_AUTO_UNDEMOTE            (1UL << 28)
-
-#define MSR_MTRRcap                     0x000000fe
-#define MSR_IA32_BBL_CR_CTL             0x00000119
-#define MSR_IA32_BBL_CR_CTL3            0x0000011e
-
-#define MSR_IA32_SYSENTER_CS            0x00000174
-#define MSR_IA32_SYSENTER_ESP           0x00000175
-#define MSR_IA32_SYSENTER_EIP           0x00000176
-
-#define MSR_IA32_MCG_CAP                0x00000179
-#define MSR_IA32_MCG_STATUS             0x0000017a
-#define MSR_IA32_MCG_CTL                0x0000017b
-
-#define MSR_OFFCORE_RSP_0               0x000001a6
-#define MSR_OFFCORE_RSP_1               0x000001a7
-#define MSR_NHM_TURBO_RATIO_LIMIT       0x000001ad
-#define MSR_IVT_TURBO_RATIO_LIMIT       0x000001ae
-
-#define MSR_LBR_SELECT                  0x000001c8
-#define MSR_LBR_TOS                     0x000001c9
-#define MSR_LBR_NHM_FROM                0x00000680
-#define MSR_LBR_NHM_TO                  0x000006c0
-#define MSR_LBR_CORE_FROM               0x00000040
-#define MSR_LBR_CORE_TO                 0x00000060
-
-#define MSR_IA32_PEBS_ENABLE            0x000003f1
-#define MSR_IA32_DS_AREA                0x00000600
-#define MSR_IA32_PERF_CAPABILITIES      0x00000345
-
-#define MSR_MTRRfix64K_00000            0x00000250
-#define MSR_MTRRfix16K_80000            0x00000258
-#define MSR_MTRRfix16K_A0000            0x00000259
-#define MSR_MTRRfix4K_C0000             0x00000268
-#define MSR_MTRRfix4K_C8000             0x00000269
-#define MSR_MTRRfix4K_D0000             0x0000026a
-#define MSR_MTRRfix4K_D8000             0x0000026b
-#define MSR_MTRRfix4K_E0000             0x0000026c
-#define MSR_MTRRfix4K_E8000             0x0000026d
-#define MSR_MTRRfix4K_F0000             0x0000026e
-#define MSR_MTRRfix4K_F8000             0x0000026f
-#define MSR_MTRRdefType                 0x000002ff
-
-#define MSR_IA32_CR_PAT                 0x00000277
-
-#define MSR_IA32_DEBUGCTLMSR            0x000001d9
-#define MSR_IA32_LASTBRANCHFROMIP       0x000001db
-#define MSR_IA32_LASTBRANCHTOIP         0x000001dc
-#define MSR_IA32_LASTINTFROMIP          0x000001dd
-#define MSR_IA32_LASTINTTOIP            0x000001de
-
-/* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR                 (1UL <<  0) /* last branch recording */
-#define DEBUGCTLMSR_BTF                 (1UL <<  1) /* single-step on branches */
-#define DEBUGCTLMSR_TR                  (1UL <<  6)
-#define DEBUGCTLMSR_BTS                 (1UL <<  7)
-#define DEBUGCTLMSR_BTINT               (1UL <<  8)
-#define DEBUGCTLMSR_BTS_OFF_OS          (1UL <<  9)
-#define DEBUGCTLMSR_BTS_OFF_USR         (1UL << 10)
-#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1UL << 11)
-
-#define MSR_IA32_MC0_CTL                0x00000400
-#define MSR_IA32_MC0_STATUS             0x00000401
-#define MSR_IA32_MC0_ADDR               0x00000402
-#define MSR_IA32_MC0_MISC               0x00000403
-
-/* C-state Residency Counters */
-#define MSR_PKG_C3_RESIDENCY            0x000003f8
-#define MSR_PKG_C6_RESIDENCY            0x000003f9
-#define MSR_PKG_C7_RESIDENCY            0x000003fa
-#define MSR_CORE_C3_RESIDENCY           0x000003fc
-#define MSR_CORE_C6_RESIDENCY           0x000003fd
-#define MSR_CORE_C7_RESIDENCY           0x000003fe
-#define MSR_PKG_C2_RESIDENCY            0x0000060d
-
-/* Run Time Average Power Limiting (RAPL) Interface */
-
-#define MSR_RAPL_POWER_UNIT             0x00000606
-
-#define MSR_PKG_POWER_LIMIT             0x00000610
-#define MSR_PKG_ENERGY_STATUS           0x00000611
-#define MSR_PKG_PERF_STATUS             0x00000613
-#define MSR_PKG_POWER_INFO              0x00000614
-
-#define MSR_DRAM_POWER_LIMIT            0x00000618
-#define MSR_DRAM_ENERGY_STATUS          0x00000619
-#define MSR_DRAM_PERF_STATUS            0x0000061b
-#define MSR_DRAM_POWER_INFO             0x0000061c
-
-#define MSR_PP0_POWER_LIMIT             0x00000638
-#define MSR_PP0_ENERGY_STATUS           0x00000639
-#define MSR_PP0_POLICY                  0x0000063a
-#define MSR_PP0_PERF_STATUS             0x0000063b
-
-#define MSR_PP1_POWER_LIMIT             0x00000640
-#define MSR_PP1_ENERGY_STATUS           0x00000641
-#define MSR_PP1_POLICY                  0x00000642
-
-#define MSR_AMD64_MC0_MASK              0xc0010044
-
-#define MSR_IA32_MCx_CTL(x)             (MSR_IA32_MC0_CTL + 4*(x))
-#define MSR_IA32_MCx_STATUS(x)          (MSR_IA32_MC0_STATUS + 4*(x))
-#define MSR_IA32_MCx_ADDR(x)            (MSR_IA32_MC0_ADDR + 4*(x))
-#define MSR_IA32_MCx_MISC(x)            (MSR_IA32_MC0_MISC + 4*(x))
-
-#define MSR_AMD64_MCx_MASK(x)           (MSR_AMD64_MC0_MASK + (x))
-
-/* These are consecutive and not in the normal 4er MCE bank block */
-#define MSR_IA32_MC0_CTL2               0x00000280
-#define MSR_IA32_MCx_CTL2(x)            (MSR_IA32_MC0_CTL2 + (x))
-
-#define MSR_P6_PERFCTR0                 0x000000c1
-#define MSR_P6_PERFCTR1                 0x000000c2
-#define MSR_P6_EVNTSEL0                 0x00000186
-#define MSR_P6_EVNTSEL1                 0x00000187
-
-#define MSR_KNC_PERFCTR0               0x00000020
-#define MSR_KNC_PERFCTR1               0x00000021
-#define MSR_KNC_EVNTSEL0               0x00000028
-#define MSR_KNC_EVNTSEL1               0x00000029
-
-/* AMD64 MSRs. Not complete. See the architecture manual for a more
-   complete list. */
-
-#define MSR_AMD64_PATCH_LEVEL           0x0000008b
-#define MSR_AMD64_TSC_RATIO             0xc0000104
-#define MSR_AMD64_NB_CFG                0xc001001f
-#define MSR_AMD64_PATCH_LOADER          0xc0010020
-#define MSR_AMD64_OSVW_ID_LENGTH        0xc0010140
-#define MSR_AMD64_OSVW_STATUS           0xc0010141
-#define MSR_AMD64_DC_CFG                0xc0011022
-#define MSR_AMD64_IBSFETCHCTL           0xc0011030
-#define MSR_AMD64_IBSFETCHLINAD         0xc0011031
-#define MSR_AMD64_IBSFETCHPHYSAD        0xc0011032
-#define MSR_AMD64_IBSFETCH_REG_COUNT    3
-#define MSR_AMD64_IBSFETCH_REG_MASK     ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
-#define MSR_AMD64_IBSOPCTL              0xc0011033
-#define MSR_AMD64_IBSOPRIP              0xc0011034
-#define MSR_AMD64_IBSOPDATA             0xc0011035
-#define MSR_AMD64_IBSOPDATA2            0xc0011036
-#define MSR_AMD64_IBSOPDATA3            0xc0011037
-#define MSR_AMD64_IBSDCLINAD            0xc0011038
-#define MSR_AMD64_IBSDCPHYSAD           0xc0011039
-#define MSR_AMD64_IBSOP_REG_COUNT       7
-#define MSR_AMD64_IBSOP_REG_MASK        ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
-#define MSR_AMD64_IBSCTL                0xc001103a
-#define MSR_AMD64_IBSBRTARGET           0xc001103b
-#define MSR_AMD64_IBS_REG_COUNT_MAX     8 /* includes MSR_AMD64_IBSBRTARGET */
-
-/* Fam 15h MSRs */
-#define MSR_F15H_PERF_CTL               0xc0010200
-#define MSR_F15H_PERF_CTR               0xc0010201
-
-/* Fam 10h MSRs */
-#define MSR_FAM10H_MMIO_CONF_BASE       0xc0010058
-#define FAM10H_MMIO_CONF_ENABLE         (1<<0)
-#define FAM10H_MMIO_CONF_BUSRANGE_MASK  0xf
-#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
-#define FAM10H_MMIO_CONF_BASE_MASK      0xfffffffULL
-#define FAM10H_MMIO_CONF_BASE_SHIFT     20
-#define MSR_FAM10H_NODE_ID              0xc001100c
-
-/* K8 MSRs */
-#define MSR_K8_TOP_MEM1                 0xc001001a
-#define MSR_K8_TOP_MEM2                 0xc001001d
-#define MSR_K8_SYSCFG                   0xc0010010
-#define MSR_K8_INT_PENDING_MSG          0xc0010055
-/* C1E active bits in int pending message */
-#define K8_INTP_C1E_ACTIVE_MASK         0x18000000
-#define MSR_K8_TSEG_ADDR                0xc0010112
-#define K8_MTRRFIXRANGE_DRAM_ENABLE     0x00040000 /* MtrrFixDramEn bit    */
-#define K8_MTRRFIXRANGE_DRAM_MODIFY     0x00080000 /* MtrrFixDramModEn bit */
-#define K8_MTRR_RDMEM_WRMEM_MASK        0x18181818 /* Mask: RdMem|WrMem    */
-
-/* K7 MSRs */
-#define MSR_K7_EVNTSEL0                 0xc0010000
-#define MSR_K7_PERFCTR0                 0xc0010004
-#define MSR_K7_EVNTSEL1                 0xc0010001
-#define MSR_K7_PERFCTR1                 0xc0010005
-#define MSR_K7_EVNTSEL2                 0xc0010002
-#define MSR_K7_PERFCTR2                 0xc0010006
-#define MSR_K7_EVNTSEL3                 0xc0010003
-#define MSR_K7_PERFCTR3                 0xc0010007
-#define MSR_K7_CLK_CTL                  0xc001001b
-#define MSR_K7_HWCR                     0xc0010015
-#define MSR_K7_FID_VID_CTL              0xc0010041
-#define MSR_K7_FID_VID_STATUS           0xc0010042
-
-/* K6 MSRs */
-#define MSR_K6_WHCR                     0xc0000082
-#define MSR_K6_UWCCR                    0xc0000085
-#define MSR_K6_EPMR                     0xc0000086
-#define MSR_K6_PSOR                     0xc0000087
-#define MSR_K6_PFIR                     0xc0000088
-
-/* Centaur-Hauls/IDT defined MSRs. */
-#define MSR_IDT_FCR1                    0x00000107
-#define MSR_IDT_FCR2                    0x00000108
-#define MSR_IDT_FCR3                    0x00000109
-#define MSR_IDT_FCR4                    0x0000010a
-
-#define MSR_IDT_MCR0                    0x00000110
-#define MSR_IDT_MCR1                    0x00000111
-#define MSR_IDT_MCR2                    0x00000112
-#define MSR_IDT_MCR3                    0x00000113
-#define MSR_IDT_MCR4                    0x00000114
-#define MSR_IDT_MCR5                    0x00000115
-#define MSR_IDT_MCR6                    0x00000116
-#define MSR_IDT_MCR7                    0x00000117
-#define MSR_IDT_MCR_CTRL                0x00000120
-
-/* VIA Cyrix defined MSRs*/
-#define MSR_VIA_FCR                     0x00001107
-#define MSR_VIA_LONGHAUL                0x0000110a
-#define MSR_VIA_RNG                     0x0000110b
-#define MSR_VIA_BCR2                    0x00001147
-
-/* Transmeta defined MSRs */
-#define MSR_TMTA_LONGRUN_CTRL           0x80868010
-#define MSR_TMTA_LONGRUN_FLAGS          0x80868011
-#define MSR_TMTA_LRTI_READOUT           0x80868018
-#define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
-
-/* Intel defined MSRs. */
-#define MSR_IA32_P5_MC_ADDR             0x00000000
-#define MSR_IA32_P5_MC_TYPE             0x00000001
-#define MSR_IA32_TSC                    0x00000010
-#define MSR_IA32_PLATFORM_ID            0x00000017
-#define MSR_IA32_EBL_CR_POWERON         0x0000002a
-#define MSR_EBC_FREQUENCY_ID            0x0000002c
-#define MSR_IA32_FEATURE_CONTROL        0x0000003a
-#define MSR_IA32_TSC_ADJUST             0x0000003b
-
-#define FEATURE_CONTROL_LOCKED                          (1<<0)
-#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX        (1<<1)
-#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1<<2)
-
-#define MSR_IA32_APICBASE               0x0000001b
-#define MSR_IA32_APICBASE_BSP           (1<<8)
-#define MSR_IA32_APICBASE_ENABLE        (1<<11)
-#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
-
-#define MSR_IA32_TSCDEADLINE            0x000006e0
-
-#define MSR_IA32_UCODE_WRITE            0x00000079
-#define MSR_IA32_UCODE_REV              0x0000008b
-
-#define MSR_IA32_PERF_STATUS            0x00000198
-#define MSR_IA32_PERF_CTL               0x00000199
-#define MSR_AMD_PSTATE_DEF_BASE         0xc0010064
-#define MSR_AMD_PERF_STATUS             0xc0010063
-#define MSR_AMD_PERF_CTL                0xc0010062
-
-#define MSR_IA32_MPERF                  0x000000e7
-#define MSR_IA32_APERF                  0x000000e8
-
-#define MSR_IA32_THERM_CONTROL          0x0000019a
-#define MSR_IA32_THERM_INTERRUPT        0x0000019b
-
-#define THERM_INT_HIGH_ENABLE           (1 << 0)
-#define THERM_INT_LOW_ENABLE            (1 << 1)
-#define THERM_INT_PLN_ENABLE            (1 << 24)
-
-#define MSR_IA32_THERM_STATUS           0x0000019c
-
-#define THERM_STATUS_PROCHOT            (1 << 0)
-#define THERM_STATUS_POWER_LIMIT        (1 << 10)
-
-#define MSR_THERM2_CTL                  0x0000019d
-
-#define MSR_THERM2_CTL_TM_SELECT        (1ULL << 16)
-
-#define MSR_IA32_MISC_ENABLE            0x000001a0
-
-#define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
-
-#define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
-#define ENERGY_PERF_BIAS_PERFORMANCE    0
-#define ENERGY_PERF_BIAS_NORMAL         6
-#define ENERGY_PERF_BIAS_POWERSAVE      15
-
-#define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1
-
-#define PACKAGE_THERM_STATUS_PROCHOT            (1 << 0)
-#define PACKAGE_THERM_STATUS_POWER_LIMIT        (1 << 10)
-
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT        0x000001b2
-
-#define PACKAGE_THERM_INT_HIGH_ENABLE           (1 << 0)
-#define PACKAGE_THERM_INT_LOW_ENABLE            (1 << 1)
-#define PACKAGE_THERM_INT_PLN_ENABLE            (1 << 24)
-
-/* Thermal Thresholds Support */
-#define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
-#define THERM_SHIFT_THRESHOLD0        8
-#define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
-#define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
-#define THERM_SHIFT_THRESHOLD1        16
-#define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
-#define THERM_STATUS_THRESHOLD0        (1 << 6)
-#define THERM_LOG_THRESHOLD0           (1 << 7)
-#define THERM_STATUS_THRESHOLD1        (1 << 8)
-#define THERM_LOG_THRESHOLD1           (1 << 9)
-
-/* MISC_ENABLE bits: architectural */
-#define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << 0)
-#define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
-#define MSR_IA32_MISC_ENABLE_EMON               (1ULL << 7)
-#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL        (1ULL << 11)
-#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL       (1ULL << 12)
-#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
-#define MSR_IA32_MISC_ENABLE_MWAIT              (1ULL << 18)
-#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID        (1ULL << 22)
-#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE       (1ULL << 23)
-#define MSR_IA32_MISC_ENABLE_XD_DISABLE         (1ULL << 34)
-
-/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
-#define MSR_IA32_MISC_ENABLE_X87_COMPAT         (1ULL << 2)
-#define MSR_IA32_MISC_ENABLE_TM1                (1ULL << 3)
-#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
-#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE    (1ULL << 6)
-#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK      (1ULL << 8)
-#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE   (1ULL << 9)
-#define MSR_IA32_MISC_ENABLE_FERR               (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX     (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_TM2                (1ULL << 13)
-#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE   (1ULL << 19)
-#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK     (1ULL << 20)
-#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT        (1ULL << 24)
-#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE   (1ULL << 37)
-#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE      (1ULL << 38)
-#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE    (1ULL << 39)
-
-#define MSR_IA32_TSC_DEADLINE           0x000006E0
-
-/* P4/Xeon+ specific */
-#define MSR_IA32_MCG_EAX                0x00000180
-#define MSR_IA32_MCG_EBX                0x00000181
-#define MSR_IA32_MCG_ECX                0x00000182
-#define MSR_IA32_MCG_EDX                0x00000183
-#define MSR_IA32_MCG_ESI                0x00000184
-#define MSR_IA32_MCG_EDI                0x00000185
-#define MSR_IA32_MCG_EBP                0x00000186
-#define MSR_IA32_MCG_ESP                0x00000187
-#define MSR_IA32_MCG_EFLAGS             0x00000188
-#define MSR_IA32_MCG_EIP                0x00000189
-#define MSR_IA32_MCG_RESERVED           0x0000018a
-
-/* Pentium IV performance counter MSRs */
-#define MSR_P4_BPU_PERFCTR0             0x00000300
-#define MSR_P4_BPU_PERFCTR1             0x00000301
-#define MSR_P4_BPU_PERFCTR2             0x00000302
-#define MSR_P4_BPU_PERFCTR3             0x00000303
-#define MSR_P4_MS_PERFCTR0              0x00000304
-#define MSR_P4_MS_PERFCTR1              0x00000305
-#define MSR_P4_MS_PERFCTR2              0x00000306
-#define MSR_P4_MS_PERFCTR3              0x00000307
-#define MSR_P4_FLAME_PERFCTR0           0x00000308
-#define MSR_P4_FLAME_PERFCTR1           0x00000309
-#define MSR_P4_FLAME_PERFCTR2           0x0000030a
-#define MSR_P4_FLAME_PERFCTR3           0x0000030b
-#define MSR_P4_IQ_PERFCTR0              0x0000030c
-#define MSR_P4_IQ_PERFCTR1              0x0000030d
-#define MSR_P4_IQ_PERFCTR2              0x0000030e
-#define MSR_P4_IQ_PERFCTR3              0x0000030f
-#define MSR_P4_IQ_PERFCTR4              0x00000310
-#define MSR_P4_IQ_PERFCTR5              0x00000311
-#define MSR_P4_BPU_CCCR0                0x00000360
-#define MSR_P4_BPU_CCCR1                0x00000361
-#define MSR_P4_BPU_CCCR2                0x00000362
-#define MSR_P4_BPU_CCCR3                0x00000363
-#define MSR_P4_MS_CCCR0                 0x00000364
-#define MSR_P4_MS_CCCR1                 0x00000365
-#define MSR_P4_MS_CCCR2                 0x00000366
-#define MSR_P4_MS_CCCR3                 0x00000367
-#define MSR_P4_FLAME_CCCR0              0x00000368
-#define MSR_P4_FLAME_CCCR1              0x00000369
-#define MSR_P4_FLAME_CCCR2              0x0000036a
-#define MSR_P4_FLAME_CCCR3              0x0000036b
-#define MSR_P4_IQ_CCCR0                 0x0000036c
-#define MSR_P4_IQ_CCCR1                 0x0000036d
-#define MSR_P4_IQ_CCCR2                 0x0000036e
-#define MSR_P4_IQ_CCCR3                 0x0000036f
-#define MSR_P4_IQ_CCCR4                 0x00000370
-#define MSR_P4_IQ_CCCR5                 0x00000371
-#define MSR_P4_ALF_ESCR0                0x000003ca
-#define MSR_P4_ALF_ESCR1                0x000003cb
-#define MSR_P4_BPU_ESCR0                0x000003b2
-#define MSR_P4_BPU_ESCR1                0x000003b3
-#define MSR_P4_BSU_ESCR0                0x000003a0
-#define MSR_P4_BSU_ESCR1                0x000003a1
-#define MSR_P4_CRU_ESCR0                0x000003b8
-#define MSR_P4_CRU_ESCR1                0x000003b9
-#define MSR_P4_CRU_ESCR2                0x000003cc
-#define MSR_P4_CRU_ESCR3                0x000003cd
-#define MSR_P4_CRU_ESCR4                0x000003e0
-#define MSR_P4_CRU_ESCR5                0x000003e1
-#define MSR_P4_DAC_ESCR0                0x000003a8
-#define MSR_P4_DAC_ESCR1                0x000003a9
-#define MSR_P4_FIRM_ESCR0               0x000003a4
-#define MSR_P4_FIRM_ESCR1               0x000003a5
-#define MSR_P4_FLAME_ESCR0              0x000003a6
-#define MSR_P4_FLAME_ESCR1              0x000003a7
-#define MSR_P4_FSB_ESCR0                0x000003a2
-#define MSR_P4_FSB_ESCR1                0x000003a3
-#define MSR_P4_IQ_ESCR0                 0x000003ba
-#define MSR_P4_IQ_ESCR1                 0x000003bb
-#define MSR_P4_IS_ESCR0                 0x000003b4
-#define MSR_P4_IS_ESCR1                 0x000003b5
-#define MSR_P4_ITLB_ESCR0               0x000003b6
-#define MSR_P4_ITLB_ESCR1               0x000003b7
-#define MSR_P4_IX_ESCR0                 0x000003c8
-#define MSR_P4_IX_ESCR1                 0x000003c9
-#define MSR_P4_MOB_ESCR0                0x000003aa
-#define MSR_P4_MOB_ESCR1                0x000003ab
-#define MSR_P4_MS_ESCR0                 0x000003c0
-#define MSR_P4_MS_ESCR1                 0x000003c1
-#define MSR_P4_PMH_ESCR0                0x000003ac
-#define MSR_P4_PMH_ESCR1                0x000003ad
-#define MSR_P4_RAT_ESCR0                0x000003bc
-#define MSR_P4_RAT_ESCR1                0x000003bd
-#define MSR_P4_SAAT_ESCR0               0x000003ae
-#define MSR_P4_SAAT_ESCR1               0x000003af
-#define MSR_P4_SSU_ESCR0                0x000003be
-#define MSR_P4_SSU_ESCR1                0x000003bf /* guess: not in manual */
-
-#define MSR_P4_TBPU_ESCR0               0x000003c2
-#define MSR_P4_TBPU_ESCR1               0x000003c3
-#define MSR_P4_TC_ESCR0                 0x000003c4
-#define MSR_P4_TC_ESCR1                 0x000003c5
-#define MSR_P4_U2L_ESCR0                0x000003b0
-#define MSR_P4_U2L_ESCR1                0x000003b1
-
-#define MSR_P4_PEBS_MATRIX_VERT         0x000003f2
-
-/* Intel Core-based CPU performance counters */
-#define MSR_CORE_PERF_FIXED_CTR0        0x00000309
-#define MSR_CORE_PERF_FIXED_CTR1        0x0000030a
-#define MSR_CORE_PERF_FIXED_CTR2        0x0000030b
-#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x0000038d
-#define MSR_CORE_PERF_GLOBAL_STATUS     0x0000038e
-#define MSR_CORE_PERF_GLOBAL_CTRL       0x0000038f
-#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x00000390
-
-/* Geode defined MSRs */
-#define MSR_GEODE_BUSCONT_CONF0         0x00001900
-
-/* Intel VT MSRs */
-#define MSR_IA32_VMX_BASIC              0x00000480
-#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
-#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
-#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
-#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
-#define MSR_IA32_VMX_MISC               0x00000485
-#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
-#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
-#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
-#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
-#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
-#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
-#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
-
-/* VMX_BASIC bits and bitmasks */
-#define VMX_BASIC_VMCS_SIZE_SHIFT       32
-#define VMX_BASIC_64            0x0001000000000000LLU
-#define VMX_BASIC_MEM_TYPE_SHIFT        50
-#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
-#define VMX_BASIC_MEM_TYPE_WB   6LLU
-#define VMX_BASIC_INOUT         0x0040000000000000LLU
-
-/* AMD-V MSRs */
-
-#define MSR_VM_CR                       0xc0010114
-#define MSR_VM_IGNNE                    0xc0010115
-#define MSR_VM_HSAVE_PA                 0xc0010117
-
-#endif /* _ASM_X86_MSR_INDEX_H */
diff --git a/arch/x86/include/uapi/asm/msr.h b/arch/x86/include/uapi/asm/msr.h
deleted file mode 100644
index 155e51048fa..00000000000
--- a/arch/x86/include/uapi/asm/msr.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _UAPI_ASM_X86_MSR_H
-#define _UAPI_ASM_X86_MSR_H
-
-#include <asm/msr-index.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-#define X86_IOC_RDMSR_REGS      _IOWR('c', 0xA0, __u32[8])
-#define X86_IOC_WRMSR_REGS      _IOWR('c', 0xA1, __u32[8])
-
-#endif /* __ASSEMBLY__ */
-#endif /* _UAPI_ASM_X86_MSR_H */
diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/mtrr.h
deleted file mode 100644
index d0acb658c8f..00000000000
--- a/arch/x86/include/uapi/asm/mtrr.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*  Generic MTRR (Memory Type Range Register) ioctls.
-
-    Copyright (C) 1997-1999  Richard Gooch
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Richard Gooch may be reached by email at  rgooch@atnf.csiro.au
-    The postal address is:
-      Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
-*/
-#ifndef _UAPI_ASM_X86_MTRR_H
-#define _UAPI_ASM_X86_MTRR_H
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#include <linux/errno.h>
-
-#define MTRR_IOCTL_BASE 'M'
-
-/* Warning: this structure has a different order from i386
-   on x86-64. The 32bit emulation code takes care of that.
-   But you need to use this for 64bit, otherwise your X server
-   will break. */
-
-#ifdef __i386__
-struct mtrr_sentry {
-    unsigned long base;    /*  Base address     */
-    unsigned int size;    /*  Size of region   */
-    unsigned int type;     /*  Type of region   */
-};
-
-struct mtrr_gentry {
-    unsigned int regnum;   /*  Register number  */
-    unsigned long base;    /*  Base address     */
-    unsigned int size;    /*  Size of region   */
-    unsigned int type;     /*  Type of region   */
-};
-
-#else /* __i386__ */
-
-struct mtrr_sentry {
-        __u64 base;             /*  Base address     */
-        __u32 size;             /*  Size of region   */
-        __u32 type;             /*  Type of region   */
-};
-
-struct mtrr_gentry {
-        __u64 base;             /*  Base address     */
-        __u32 size;             /*  Size of region   */
-        __u32 regnum;           /*  Register number  */
-        __u32 type;             /*  Type of region   */
-        __u32 _pad;             /*  Unused           */
-};
-
-#endif /* !__i386__ */
-
-struct mtrr_var_range {
-        __u32 base_lo;
-        __u32 base_hi;
-        __u32 mask_lo;
-        __u32 mask_hi;
-};
-
-/* In the Intel processor's MTRR interface, the MTRR type is always held in
-   an 8 bit field: */
-typedef __u8 mtrr_type;
-
-#define MTRR_NUM_FIXED_RANGES 88
-#define MTRR_MAX_VAR_RANGES 256
-
-struct mtrr_state_type {
-        struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
-        mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
-        unsigned char enabled;
-        unsigned char have_fixed;
-        mtrr_type def_type;
-};
-
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-/*  These are the various ioctls  */
-#define MTRRIOC_ADD_ENTRY        _IOW(MTRR_IOCTL_BASE,  0, struct mtrr_sentry)
-#define MTRRIOC_SET_ENTRY        _IOW(MTRR_IOCTL_BASE,  1, struct mtrr_sentry)
-#define MTRRIOC_DEL_ENTRY        _IOW(MTRR_IOCTL_BASE,  2, struct mtrr_sentry)
-#define MTRRIOC_GET_ENTRY        _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
-#define MTRRIOC_KILL_ENTRY       _IOW(MTRR_IOCTL_BASE,  4, struct mtrr_sentry)
-#define MTRRIOC_ADD_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  5, struct mtrr_sentry)
-#define MTRRIOC_SET_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  6, struct mtrr_sentry)
-#define MTRRIOC_DEL_PAGE_ENTRY   _IOW(MTRR_IOCTL_BASE,  7, struct mtrr_sentry)
-#define MTRRIOC_GET_PAGE_ENTRY   _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
-#define MTRRIOC_KILL_PAGE_ENTRY  _IOW(MTRR_IOCTL_BASE,  9, struct mtrr_sentry)
-
-/*  These are the region types  */
-#define MTRR_TYPE_UNCACHABLE 0
-#define MTRR_TYPE_WRCOMB     1
-/*#define MTRR_TYPE_         2*/
-/*#define MTRR_TYPE_         3*/
-#define MTRR_TYPE_WRTHROUGH  4
-#define MTRR_TYPE_WRPROT     5
-#define MTRR_TYPE_WRBACK     6
-#define MTRR_NUM_TYPES       7
-
-
-#endif /* _UAPI_ASM_X86_MTRR_H */
diff --git a/arch/x86/include/uapi/asm/param.h b/arch/x86/include/uapi/asm/param.h
deleted file mode 100644
index 965d4542797..00000000000
--- a/arch/x86/include/uapi/asm/param.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/param.h>
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
deleted file mode 100644
index 3f2207bfd17..00000000000
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _ASM_X86_PERF_REGS_H
-#define _ASM_X86_PERF_REGS_H
-
-enum perf_event_x86_regs {
-        PERF_REG_X86_AX,
-        PERF_REG_X86_BX,
-        PERF_REG_X86_CX,
-        PERF_REG_X86_DX,
-        PERF_REG_X86_SI,
-        PERF_REG_X86_DI,
-        PERF_REG_X86_BP,
-        PERF_REG_X86_SP,
-        PERF_REG_X86_IP,
-        PERF_REG_X86_FLAGS,
-        PERF_REG_X86_CS,
-        PERF_REG_X86_SS,
-        PERF_REG_X86_DS,
-        PERF_REG_X86_ES,
-        PERF_REG_X86_FS,
-        PERF_REG_X86_GS,
-        PERF_REG_X86_R8,
-        PERF_REG_X86_R9,
-        PERF_REG_X86_R10,
-        PERF_REG_X86_R11,
-        PERF_REG_X86_R12,
-        PERF_REG_X86_R13,
-        PERF_REG_X86_R14,
-        PERF_REG_X86_R15,
-
-        PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
-        PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
-};
-#endif /* _ASM_X86_PERF_REGS_H */
diff --git a/arch/x86/include/uapi/asm/poll.h b/arch/x86/include/uapi/asm/poll.h
deleted file mode 100644
index c98509d3149..00000000000
--- a/arch/x86/include/uapi/asm/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/arch/x86/include/uapi/asm/posix_types.h b/arch/x86/include/uapi/asm/posix_types.h
deleted file mode 100644
index 85506b38362..00000000000
--- a/arch/x86/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __KERNEL__
-# ifdef __i386__
-#  include <asm/posix_types_32.h>
-# elif defined(__ILP32__)
-#  include <asm/posix_types_x32.h>
-# else
-#  include <asm/posix_types_64.h>
-# endif
-#endif
diff --git a/arch/x86/include/uapi/asm/posix_types_32.h b/arch/x86/include/uapi/asm/posix_types_32.h
deleted file mode 100644
index 8e525059e7d..00000000000
--- a/arch/x86/include/uapi/asm/posix_types_32.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASM_X86_POSIX_TYPES_32_H
-#define _ASM_X86_POSIX_TYPES_32_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short  __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short  __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short  __kernel_uid_t;
-typedef unsigned short  __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short  __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_X86_POSIX_TYPES_32_H */
diff --git a/arch/x86/include/uapi/asm/posix_types_64.h b/arch/x86/include/uapi/asm/posix_types_64.h
deleted file mode 100644
index cba0c1ead16..00000000000
--- a/arch/x86/include/uapi/asm/posix_types_64.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_X86_POSIX_TYPES_64_H
-#define _ASM_X86_POSIX_TYPES_64_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-#define __kernel_old_uid_t __kernel_old_uid_t
-
-typedef unsigned long   __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_X86_POSIX_TYPES_64_H */
diff --git a/arch/x86/include/uapi/asm/posix_types_x32.h b/arch/x86/include/uapi/asm/posix_types_x32.h
deleted file mode 100644
index 85f9bdafa93..00000000000
--- a/arch/x86/include/uapi/asm/posix_types_x32.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_X86_POSIX_TYPES_X32_H
-#define _ASM_X86_POSIX_TYPES_X32_H
-
-/*
- * This file is only used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- *
- * These types should generally match the ones used by the 64-bit kernel,
- *
- */
-
-typedef long long __kernel_long_t;
-typedef unsigned long long __kernel_ulong_t;
-#define __kernel_long_t __kernel_long_t
-
-#include <asm/posix_types_64.h>
-
-#endif /* _ASM_X86_POSIX_TYPES_X32_H */
diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/prctl.h
deleted file mode 100644
index 3ac5032fae0..00000000000
--- a/arch/x86/include/uapi/asm/prctl.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ASM_X86_PRCTL_H
-#define _ASM_X86_PRCTL_H
-
-#define ARCH_SET_GS 0x1001
-#define ARCH_SET_FS 0x1002
-#define ARCH_GET_FS 0x1003
-#define ARCH_GET_GS 0x1004
-
-#endif /* _ASM_X86_PRCTL_H */
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h
deleted file mode 100644
index 54991a74604..00000000000
--- a/arch/x86/include/uapi/asm/processor-flags.h
+++ /dev/null
@@ -1,99 +0,0 @@
-#ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H
-#define _UAPI_ASM_X86_PROCESSOR_FLAGS_H
-/* Various flags defined: can be included from assembler. */
-
-/*
- * EFLAGS bits
- */
-#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
-#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
-#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF   0x00000010 /* Auxiliary carry Flag */
-#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
-
-/*
- * Basic CPU control in CR0
- */
-#define X86_CR0_PE      0x00000001 /* Protection Enable */
-#define X86_CR0_MP      0x00000002 /* Monitor Coprocessor */
-#define X86_CR0_EM      0x00000004 /* Emulation */
-#define X86_CR0_TS      0x00000008 /* Task Switched */
-#define X86_CR0_ET      0x00000010 /* Extension Type */
-#define X86_CR0_NE      0x00000020 /* Numeric Error */
-#define X86_CR0_WP      0x00010000 /* Write Protect */
-#define X86_CR0_AM      0x00040000 /* Alignment Mask */
-#define X86_CR0_NW      0x20000000 /* Not Write-through */
-#define X86_CR0_CD      0x40000000 /* Cache Disable */
-#define X86_CR0_PG      0x80000000 /* Paging */
-
-/*
- * Paging options in CR3
- */
-#define X86_CR3_PWT     0x00000008 /* Page Write Through */
-#define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
-#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
-
-/*
- * Intel CPU features in CR4
- */
-#define X86_CR4_VME     0x00000001 /* enable vm86 extensions */
-#define X86_CR4_PVI     0x00000002 /* virtual interrupts flag enable */
-#define X86_CR4_TSD     0x00000004 /* disable time stamp at ipl 3 */
-#define X86_CR4_DE      0x00000008 /* enable debugging extensions */
-#define X86_CR4_PSE     0x00000010 /* enable page size extensions */
-#define X86_CR4_PAE     0x00000020 /* enable physical address extensions */
-#define X86_CR4_MCE     0x00000040 /* Machine check enable */
-#define X86_CR4_PGE     0x00000080 /* enable global pages */
-#define X86_CR4_PCE     0x00000100 /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
-#define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
-#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
-#define X86_CR4_PCIDE   0x00020000 /* enable PCID support */
-#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
-#define X86_CR4_SMEP    0x00100000 /* enable SMEP support */
-#define X86_CR4_SMAP    0x00200000 /* enable SMAP support */
-
-/*
- * x86-64 Task Priority Register, CR8
- */
-#define X86_CR8_TPR     0x0000000F /* task priority register */
-
-/*
- * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
- */
-
-/*
- *      NSC/Cyrix CPU configuration register indexes
- */
-#define CX86_PCR0       0x20
-#define CX86_GCR        0xb8
-#define CX86_CCR0       0xc0
-#define CX86_CCR1       0xc1
-#define CX86_CCR2       0xc2
-#define CX86_CCR3       0xc3
-#define CX86_CCR4       0xe8
-#define CX86_CCR5       0xe9
-#define CX86_CCR6       0xea
-#define CX86_CCR7       0xeb
-#define CX86_PCR1       0xf0
-#define CX86_DIR0       0xfe
-#define CX86_DIR1       0xff
-#define CX86_ARR_BASE   0xc4
-#define CX86_RCR_BASE   0xdc
-
-
-#endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */
diff --git a/arch/x86/include/uapi/asm/ptrace-abi.h b/arch/x86/include/uapi/asm/ptrace-abi.h
deleted file mode 100644
index 7b0a55a8885..00000000000
--- a/arch/x86/include/uapi/asm/ptrace-abi.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef _ASM_X86_PTRACE_ABI_H
-#define _ASM_X86_PTRACE_ABI_H
-
-#ifdef __i386__
-
-#define EBX 0
-#define ECX 1
-#define EDX 2
-#define ESI 3
-#define EDI 4
-#define EBP 5
-#define EAX 6
-#define DS 7
-#define ES 8
-#define FS 9
-#define GS 10
-#define ORIG_EAX 11
-#define EIP 12
-#define CS  13
-#define EFL 14
-#define UESP 15
-#define SS   16
-#define FRAME_SIZE 17
-
-#else /* __i386__ */
-
-#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS)
-#define R15 0
-#define R14 8
-#define R13 16
-#define R12 24
-#define RBP 32
-#define RBX 40
-/* arguments: interrupts/non tracing syscalls only save up to here*/
-#define R11 48
-#define R10 56
-#define R9 64
-#define R8 72
-#define RAX 80
-#define RCX 88
-#define RDX 96
-#define RSI 104
-#define RDI 112
-#define ORIG_RAX 120       /* = ERROR */
-/* end of arguments */
-/* cpu exception frame or undefined in case of fast syscall. */
-#define RIP 128
-#define CS 136
-#define EFLAGS 144
-#define RSP 152
-#define SS 160
-#define ARGOFFSET R11
-#endif /* __ASSEMBLY__ */
-
-/* top of stack page */
-#define FRAME_SIZE 168
-
-#endif /* !__i386__ */
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-#define PTRACE_GETFPREGS          14
-#define PTRACE_SETFPREGS          15
-#define PTRACE_GETFPXREGS         18
-#define PTRACE_SETFPXREGS         19
-
-#define PTRACE_OLDSETOPTIONS      21
-
-/* only useful for access 32bit programs / kernels */
-#define PTRACE_GET_THREAD_AREA    25
-#define PTRACE_SET_THREAD_AREA    26
-
-#ifdef __x86_64__
-# define PTRACE_ARCH_PRCTL        30
-#endif
-
-#define PTRACE_SYSEMU             31
-#define PTRACE_SYSEMU_SINGLESTEP  32
-
-#define PTRACE_SINGLEBLOCK      33      /* resume execution until next branch */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-
-#endif /* _ASM_X86_PTRACE_ABI_H */
diff --git a/arch/x86/include/uapi/asm/ptrace.h b/arch/x86/include/uapi/asm/ptrace.h
deleted file mode 100644
index ac4b9aa4d99..00000000000
--- a/arch/x86/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef _UAPI_ASM_X86_PTRACE_H
-#define _UAPI_ASM_X86_PTRACE_H
-
-#include <linux/compiler.h>     /* For __user */
-#include <asm/ptrace-abi.h>
-#include <asm/processor-flags.h>
-
-
-#ifndef __ASSEMBLY__
-
-#ifdef __i386__
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-#ifndef __KERNEL__
-
-struct pt_regs {
-        long ebx;
-        long ecx;
-        long edx;
-        long esi;
-        long edi;
-        long ebp;
-        long eax;
-        int  xds;
-        int  xes;
-        int  xfs;
-        int  xgs;
-        long orig_eax;
-        long eip;
-        int  xcs;
-        long eflags;
-        long esp;
-        int  xss;
-};
-
-#endif /* __KERNEL__ */
-
-#else /* __i386__ */
-
-#ifndef __KERNEL__
-
-struct pt_regs {
-        unsigned long r15;
-        unsigned long r14;
-        unsigned long r13;
-        unsigned long r12;
-        unsigned long rbp;
-        unsigned long rbx;
-/* arguments: non interrupts/non tracing syscalls only save up to here*/
-        unsigned long r11;
-        unsigned long r10;
-        unsigned long r9;
-        unsigned long r8;
-        unsigned long rax;
-        unsigned long rcx;
-        unsigned long rdx;
-        unsigned long rsi;
-        unsigned long rdi;
-        unsigned long orig_rax;
-/* end of arguments */
-/* cpu exception frame or undefined */
-        unsigned long rip;
-        unsigned long cs;
-        unsigned long eflags;
-        unsigned long rsp;
-        unsigned long ss;
-/* top of stack page */
-};
-
-#endif /* __KERNEL__ */
-#endif /* !__i386__ */
-
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _UAPI_ASM_X86_PTRACE_H */
diff --git a/arch/x86/include/uapi/asm/resource.h b/arch/x86/include/uapi/asm/resource.h
deleted file mode 100644
index 04bc4db8921..00000000000
--- a/arch/x86/include/uapi/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/resource.h>
diff --git a/arch/x86/include/uapi/asm/sembuf.h b/arch/x86/include/uapi/asm/sembuf.h
deleted file mode 100644
index ee50c801f7b..00000000000
--- a/arch/x86/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _ASM_X86_SEMBUF_H
-#define _ASM_X86_SEMBUF_H
-
-/*
- * The semid64_ds structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-struct semid64_ds {
-        struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;      /* last semop time */
-        unsigned long   __unused1;
-        __kernel_time_t sem_ctime;      /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;      /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASM_X86_SEMBUF_H */
diff --git a/arch/x86/include/uapi/asm/setup.h b/arch/x86/include/uapi/asm/setup.h
deleted file mode 100644
index 79a9626b550..00000000000
--- a/arch/x86/include/uapi/asm/setup.h
+++ /dev/null
@@ -1 +0,0 @@
-/* */
diff --git a/arch/x86/include/uapi/asm/shmbuf.h b/arch/x86/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 83c05fc2de3..00000000000
--- a/arch/x86/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/shmbuf.h>
diff --git a/arch/x86/include/uapi/asm/sigcontext.h b/arch/x86/include/uapi/asm/sigcontext.h
deleted file mode 100644
index d8b9f9081e8..00000000000
--- a/arch/x86/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,221 +0,0 @@
-#ifndef _UAPI_ASM_X86_SIGCONTEXT_H
-#define _UAPI_ASM_X86_SIGCONTEXT_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#define FP_XSTATE_MAGIC1        0x46505853U
-#define FP_XSTATE_MAGIC2        0x46505845U
-#define FP_XSTATE_MAGIC2_SIZE   sizeof(FP_XSTATE_MAGIC2)
-
-/*
- * bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame
- * are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes
- * are used to extended the fpstate pointer in the sigcontext, which now
- * includes the extended state information along with fpstate information.
- *
- * Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved
- * area and FP_XSTATE_MAGIC2 at the end of memory layout
- * (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the
- * extended state information in the memory layout pointed by the fpstate
- * pointer in sigcontext.
- */
-struct _fpx_sw_bytes {
-        __u32 magic1;           /* FP_XSTATE_MAGIC1 */
-        __u32 extended_size;    /* total size of the layout referred by
-                                 * fpstate pointer in the sigcontext.
-                                 */
-        __u64 xstate_bv;
-                                /* feature bit mask (including fp/sse/extended
-                                 * state) that is present in the memory
-                                 * layout.
-                                 */
-        __u32 xstate_size;      /* actual xsave state size, based on the
-                                 * features saved in the layout.
-                                 * 'extended_size' will be greater than
-                                 * 'xstate_size'.
-                                 */
-        __u32 padding[7];       /*  for future use. */
-};
-
-#ifdef __i386__
-/*
- * As documented in the iBCS2 standard..
- *
- * The first part of "struct _fpstate" is just the normal i387
- * hardware setup, the extra "status" word is used to save the
- * coprocessor status word before entering the handler.
- *
- * Pentium III FXSR, SSE support
- *      Gareth Hughes <gareth@valinux.com>, May 2000
- *
- * The FPU state data structure has had to grow to accommodate the
- * extended FPU state required by the Streaming SIMD Extensions.
- * There is no documented standard to accomplish this at the moment.
- */
-struct _fpreg {
-        unsigned short significand[4];
-        unsigned short exponent;
-};
-
-struct _fpxreg {
-        unsigned short significand[4];
-        unsigned short exponent;
-        unsigned short padding[3];
-};
-
-struct _xmmreg {
-        unsigned long element[4];
-};
-
-struct _fpstate {
-        /* Regular FPU environment */
-        unsigned long   cw;
-        unsigned long   sw;
-        unsigned long   tag;
-        unsigned long   ipoff;
-        unsigned long   cssel;
-        unsigned long   dataoff;
-        unsigned long   datasel;
-        struct _fpreg   _st[8];
-        unsigned short  status;
-        unsigned short  magic;          /* 0xffff = regular FPU data only */
-
-        /* FXSR FPU environment */
-        unsigned long   _fxsr_env[6];   /* FXSR FPU env is ignored */
-        unsigned long   mxcsr;
-        unsigned long   reserved;
-        struct _fpxreg  _fxsr_st[8];    /* FXSR FPU reg data is ignored */
-        struct _xmmreg  _xmm[8];
-        unsigned long   padding1[44];
-
-        union {
-                unsigned long   padding2[12];
-                struct _fpx_sw_bytes sw_reserved; /* represents the extended
-                                                   * state info */
-        };
-};
-
-#define X86_FXSR_MAGIC          0x0000
-
-#ifndef __KERNEL__
-/*
- * User-space might still rely on the old definition:
- */
-struct sigcontext {
-        unsigned short gs, __gsh;
-        unsigned short fs, __fsh;
-        unsigned short es, __esh;
-        unsigned short ds, __dsh;
-        unsigned long edi;
-        unsigned long esi;
-        unsigned long ebp;
-        unsigned long esp;
-        unsigned long ebx;
-        unsigned long edx;
-        unsigned long ecx;
-        unsigned long eax;
-        unsigned long trapno;
-        unsigned long err;
-        unsigned long eip;
-        unsigned short cs, __csh;
-        unsigned long eflags;
-        unsigned long esp_at_signal;
-        unsigned short ss, __ssh;
-        struct _fpstate __user *fpstate;
-        unsigned long oldmask;
-        unsigned long cr2;
-};
-#endif /* !__KERNEL__ */
-
-#else /* __i386__ */
-
-/* FXSAVE frame */
-/* Note: reserved1/2 may someday contain valuable data. Always save/restore
-   them when you change signal frames. */
-struct _fpstate {
-        __u16   cwd;
-        __u16   swd;
-        __u16   twd;            /* Note this is not the same as the
-                                   32bit/x87/FSAVE twd */
-        __u16   fop;
-        __u64   rip;
-        __u64   rdp;
-        __u32   mxcsr;
-        __u32   mxcsr_mask;
-        __u32   st_space[32];   /* 8*16 bytes for each FP-reg */
-        __u32   xmm_space[64];  /* 16*16 bytes for each XMM-reg  */
-        __u32   reserved2[12];
-        union {
-                __u32   reserved3[12];
-                struct _fpx_sw_bytes sw_reserved; /* represents the extended
-                                                   * state information */
-        };
-};
-
-#ifndef __KERNEL__
-/*
- * User-space might still rely on the old definition:
- */
-struct sigcontext {
-        __u64 r8;
-        __u64 r9;
-        __u64 r10;
-        __u64 r11;
-        __u64 r12;
-        __u64 r13;
-        __u64 r14;
-        __u64 r15;
-        __u64 rdi;
-        __u64 rsi;
-        __u64 rbp;
-        __u64 rbx;
-        __u64 rdx;
-        __u64 rax;
-        __u64 rcx;
-        __u64 rsp;
-        __u64 rip;
-        __u64 eflags;           /* RFLAGS */
-        __u16 cs;
-        __u16 gs;
-        __u16 fs;
-        __u16 __pad0;
-        __u64 err;
-        __u64 trapno;
-        __u64 oldmask;
-        __u64 cr2;
-        struct _fpstate __user *fpstate;        /* zero when no FPU context */
-#ifdef __ILP32__
-        __u32 __fpstate_pad;
-#endif
-        __u64 reserved1[8];
-};
-#endif /* !__KERNEL__ */
-
-#endif /* !__i386__ */
-
-struct _xsave_hdr {
-        __u64 xstate_bv;
-        __u64 reserved1[2];
-        __u64 reserved2[5];
-};
-
-struct _ymmh_state {
-        /* 16 * 16 bytes for each YMMH-reg */
-        __u32 ymmh_space[64];
-};
-
-/*
- * Extended state pointed by the fpstate pointer in the sigcontext.
- * In addition to the fpstate, information encoded in the xstate_hdr
- * indicates the presence of other extended state information
- * supported by the processor and OS.
- */
-struct _xstate {
-        struct _fpstate fpstate;
-        struct _xsave_hdr xstate_hdr;
-        struct _ymmh_state ymmh;
-        /* new processor state extensions go here */
-};
-
-#endif /* _UAPI_ASM_X86_SIGCONTEXT_H */
diff --git a/arch/x86/include/uapi/asm/sigcontext32.h b/arch/x86/include/uapi/asm/sigcontext32.h
deleted file mode 100644
index ad1478c4ae1..00000000000
--- a/arch/x86/include/uapi/asm/sigcontext32.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _ASM_X86_SIGCONTEXT32_H
-#define _ASM_X86_SIGCONTEXT32_H
-
-#include <linux/types.h>
-
-/* signal context for 32bit programs. */
-
-#define X86_FXSR_MAGIC          0x0000
-
-struct _fpreg {
-        unsigned short significand[4];
-        unsigned short exponent;
-};
-
-struct _fpxreg {
-        unsigned short significand[4];
-        unsigned short exponent;
-        unsigned short padding[3];
-};
-
-struct _xmmreg {
-        __u32   element[4];
-};
-
-/* FSAVE frame with extensions */
-struct _fpstate_ia32 {
-        /* Regular FPU environment */
-        __u32   cw;
-        __u32   sw;
-        __u32   tag;    /* not compatible to 64bit twd */
-        __u32   ipoff;
-        __u32   cssel;
-        __u32   dataoff;
-        __u32   datasel;
-        struct _fpreg   _st[8];
-        unsigned short  status;
-        unsigned short  magic;          /* 0xffff = regular FPU data only */
-
-        /* FXSR FPU environment */
-        __u32   _fxsr_env[6];
-        __u32   mxcsr;
-        __u32   reserved;
-        struct _fpxreg  _fxsr_st[8];
-        struct _xmmreg  _xmm[8];        /* It's actually 16 */
-        __u32   padding[44];
-        union {
-                __u32 padding2[12];
-                struct _fpx_sw_bytes sw_reserved;
-        };
-};
-
-struct sigcontext_ia32 {
-       unsigned short gs, __gsh;
-       unsigned short fs, __fsh;
-       unsigned short es, __esh;
-       unsigned short ds, __dsh;
-       unsigned int di;
-       unsigned int si;
-       unsigned int bp;
-       unsigned int sp;
-       unsigned int bx;
-       unsigned int dx;
-       unsigned int cx;
-       unsigned int ax;
-       unsigned int trapno;
-       unsigned int err;
-       unsigned int ip;
-       unsigned short cs, __csh;
-       unsigned int flags;
-       unsigned int sp_at_signal;
-       unsigned short ss, __ssh;
-       unsigned int fpstate;            /* really (struct _fpstate_ia32 *) */
-       unsigned int oldmask;
-       unsigned int cr2;
-};
-
-#endif /* _ASM_X86_SIGCONTEXT32_H */
diff --git a/arch/x86/include/uapi/asm/siginfo.h b/arch/x86/include/uapi/asm/siginfo.h
deleted file mode 100644
index 34c47b3341c..00000000000
--- a/arch/x86/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _ASM_X86_SIGINFO_H
-#define _ASM_X86_SIGINFO_H
-
-#ifdef __x86_64__
-# ifdef __ILP32__ /* x32 */
-typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
-#  define __ARCH_SI_CLOCK_T             __kernel_si_clock_t
-#  define __ARCH_SI_ATTRIBUTES          __attribute__((aligned(8)))
-# else /* x86-64 */
-#  define __ARCH_SI_PREAMBLE_SIZE       (4 * sizeof(int))
-# endif
-#endif
-
-#include <asm-generic/siginfo.h>
-
-#endif /* _ASM_X86_SIGINFO_H */
diff --git a/arch/x86/include/uapi/asm/signal.h b/arch/x86/include/uapi/asm/signal.h
deleted file mode 100644
index aa7d6ae39e0..00000000000
--- a/arch/x86/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,139 +0,0 @@
-#ifndef _UAPI_ASM_X86_SIGNAL_H
-#define _UAPI_ASM_X86_SIGNAL_H
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/compiler.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGIOT           6
-#define SIGBUS           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGUSR1         10
-#define SIGSEGV         11
-#define SIGUSR2         12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGSTKFLT       16
-#define SIGCHLD         17
-#define SIGCONT         18
-#define SIGSTOP         19
-#define SIGTSTP         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGURG          23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGIO           29
-#define SIGPOLL         SIGIO
-/*
-#define SIGLOST         29
-*/
-#define SIGPWR          30
-#define SIGSYS          31
-#define SIGUNUSED       31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP    0x00000001u
-#define SA_NOCLDWAIT    0x00000002u
-#define SA_SIGINFO      0x00000004u
-#define SA_ONSTACK      0x08000000u
-#define SA_RESTART      0x10000000u
-#define SA_NODEFER      0x40000000u
-#define SA_RESETHAND    0x80000000u
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-#define SA_RESTORER     0x04000000
-
-#define MINSIGSTKSZ     2048
-#define SIGSTKSZ        8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __ASSEMBLY__
-
-
-#ifdef __i386__
-# ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-          __sighandler_t _sa_handler;
-          void (*_sa_sigaction)(int, struct siginfo *, void *);
-        } _u;
-        sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-# endif /* ! __KERNEL__ */
-#else /* __i386__ */
-
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        __sigrestore_t sa_restorer;
-        sigset_t sa_mask;               /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-
-#endif /* !__i386__ */
-
-typedef struct sigaltstack {
-        void __user *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _UAPI_ASM_X86_SIGNAL_H */
diff --git a/arch/x86/include/uapi/asm/socket.h b/arch/x86/include/uapi/asm/socket.h
deleted file mode 100644
index 6b71384b9d8..00000000000
--- a/arch/x86/include/uapi/asm/socket.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/socket.h>
diff --git a/arch/x86/include/uapi/asm/sockios.h b/arch/x86/include/uapi/asm/sockios.h
deleted file mode 100644
index def6d4746ee..00000000000
--- a/arch/x86/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/sockios.h>
diff --git a/arch/x86/include/uapi/asm/stat.h b/arch/x86/include/uapi/asm/stat.h
deleted file mode 100644
index 7b3ddc34858..00000000000
--- a/arch/x86/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,135 +0,0 @@
-#ifndef _ASM_X86_STAT_H
-#define _ASM_X86_STAT_H
-
-#define STAT_HAVE_NSEC 1
-
-#ifdef __i386__
-struct stat {
-        unsigned long  st_dev;
-        unsigned long  st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned long  st_rdev;
-        unsigned long  st_size;
-        unsigned long  st_blksize;
-        unsigned long  st_blocks;
-        unsigned long  st_atime;
-        unsigned long  st_atime_nsec;
-        unsigned long  st_mtime;
-        unsigned long  st_mtime_nsec;
-        unsigned long  st_ctime;
-        unsigned long  st_ctime_nsec;
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-/* We don't need to memset the whole thing just to initialize the padding */
-#define INIT_STRUCT_STAT_PADDING(st) do {       \
-        st.__unused4 = 0;                       \
-        st.__unused5 = 0;                       \
-} while (0)
-
-#define STAT64_HAS_BROKEN_ST_INO        1
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-        unsigned long long      st_dev;
-        unsigned char   __pad0[4];
-
-        unsigned long   __st_ino;
-
-        unsigned int    st_mode;
-        unsigned int    st_nlink;
-
-        unsigned long   st_uid;
-        unsigned long   st_gid;
-
-        unsigned long long      st_rdev;
-        unsigned char   __pad3[4];
-
-        long long       st_size;
-        unsigned long   st_blksize;
-
-        /* Number 512-byte blocks allocated. */
-        unsigned long long      st_blocks;
-
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec;
-
-        unsigned long   st_mtime;
-        unsigned int    st_mtime_nsec;
-
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-
-        unsigned long long      st_ino;
-};
-
-/* We don't need to memset the whole thing just to initialize the padding */
-#define INIT_STRUCT_STAT64_PADDING(st) do {             \
-        memset(&st.__pad0, 0, sizeof(st.__pad0));       \
-        memset(&st.__pad3, 0, sizeof(st.__pad3));       \
-} while (0)
-
-#else /* __i386__ */
-
-struct stat {
-        unsigned long   st_dev;
-        unsigned long   st_ino;
-        unsigned long   st_nlink;
-
-        unsigned int    st_mode;
-        unsigned int    st_uid;
-        unsigned int    st_gid;
-        unsigned int    __pad0;
-        unsigned long   st_rdev;
-        long            st_size;
-        long            st_blksize;
-        long            st_blocks;      /* Number 512-byte blocks allocated. */
-
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec;
-        unsigned long   st_mtime;
-        unsigned long   st_mtime_nsec;
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-        long            __unused[3];
-};
-
-/* We don't need to memset the whole thing just to initialize the padding */
-#define INIT_STRUCT_STAT_PADDING(st) do {       \
-        st.__pad0 = 0;                          \
-        st.__unused[0] = 0;                     \
-        st.__unused[1] = 0;                     \
-        st.__unused[2] = 0;                     \
-} while (0)
-
-#endif
-
-/* for 32bit emulation and 32 bit kernels */
-struct __old_kernel_stat {
-        unsigned short st_dev;
-        unsigned short st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-#ifdef __i386__
-        unsigned long  st_size;
-        unsigned long  st_atime;
-        unsigned long  st_mtime;
-        unsigned long  st_ctime;
-#else
-        unsigned int  st_size;
-        unsigned int  st_atime;
-        unsigned int  st_mtime;
-        unsigned int  st_ctime;
-#endif
-};
-
-#endif /* _ASM_X86_STAT_H */
diff --git a/arch/x86/include/uapi/asm/statfs.h b/arch/x86/include/uapi/asm/statfs.h
deleted file mode 100644
index 2d0adbf99a8..00000000000
--- a/arch/x86/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_X86_STATFS_H
-#define _ASM_X86_STATFS_H
-
-/*
- * We need compat_statfs64 to be packed, because the i386 ABI won't
- * add padding at the end to bring it to a multiple of 8 bytes, but
- * the x86_64 ABI will.
- */
-#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
-
-#include <asm-generic/statfs.h>
-#endif /* _ASM_X86_STATFS_H */
diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h
deleted file mode 100644
index b5d7640abc5..00000000000
--- a/arch/x86/include/uapi/asm/svm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _UAPI__SVM_H
-#define _UAPI__SVM_H
-
-#define SVM_EXIT_READ_CR0      0x000
-#define SVM_EXIT_READ_CR3      0x003
-#define SVM_EXIT_READ_CR4      0x004
-#define SVM_EXIT_READ_CR8      0x008
-#define SVM_EXIT_WRITE_CR0     0x010
-#define SVM_EXIT_WRITE_CR3     0x013
-#define SVM_EXIT_WRITE_CR4     0x014
-#define SVM_EXIT_WRITE_CR8     0x018
-#define SVM_EXIT_READ_DR0      0x020
-#define SVM_EXIT_READ_DR1      0x021
-#define SVM_EXIT_READ_DR2      0x022
-#define SVM_EXIT_READ_DR3      0x023
-#define SVM_EXIT_READ_DR4      0x024
-#define SVM_EXIT_READ_DR5      0x025
-#define SVM_EXIT_READ_DR6      0x026
-#define SVM_EXIT_READ_DR7      0x027
-#define SVM_EXIT_WRITE_DR0     0x030
-#define SVM_EXIT_WRITE_DR1     0x031
-#define SVM_EXIT_WRITE_DR2     0x032
-#define SVM_EXIT_WRITE_DR3     0x033
-#define SVM_EXIT_WRITE_DR4     0x034
-#define SVM_EXIT_WRITE_DR5     0x035
-#define SVM_EXIT_WRITE_DR6     0x036
-#define SVM_EXIT_WRITE_DR7     0x037
-#define SVM_EXIT_EXCP_BASE     0x040
-#define SVM_EXIT_INTR          0x060
-#define SVM_EXIT_NMI           0x061
-#define SVM_EXIT_SMI           0x062
-#define SVM_EXIT_INIT          0x063
-#define SVM_EXIT_VINTR         0x064
-#define SVM_EXIT_CR0_SEL_WRITE 0x065
-#define SVM_EXIT_IDTR_READ     0x066
-#define SVM_EXIT_GDTR_READ     0x067
-#define SVM_EXIT_LDTR_READ     0x068
-#define SVM_EXIT_TR_READ       0x069
-#define SVM_EXIT_IDTR_WRITE    0x06a
-#define SVM_EXIT_GDTR_WRITE    0x06b
-#define SVM_EXIT_LDTR_WRITE    0x06c
-#define SVM_EXIT_TR_WRITE      0x06d
-#define SVM_EXIT_RDTSC         0x06e
-#define SVM_EXIT_RDPMC         0x06f
-#define SVM_EXIT_PUSHF         0x070
-#define SVM_EXIT_POPF          0x071
-#define SVM_EXIT_CPUID         0x072
-#define SVM_EXIT_RSM           0x073
-#define SVM_EXIT_IRET          0x074
-#define SVM_EXIT_SWINT         0x075
-#define SVM_EXIT_INVD          0x076
-#define SVM_EXIT_PAUSE         0x077
-#define SVM_EXIT_HLT           0x078
-#define SVM_EXIT_INVLPG        0x079
-#define SVM_EXIT_INVLPGA       0x07a
-#define SVM_EXIT_IOIO          0x07b
-#define SVM_EXIT_MSR           0x07c
-#define SVM_EXIT_TASK_SWITCH   0x07d
-#define SVM_EXIT_FERR_FREEZE   0x07e
-#define SVM_EXIT_SHUTDOWN      0x07f
-#define SVM_EXIT_VMRUN         0x080
-#define SVM_EXIT_VMMCALL       0x081
-#define SVM_EXIT_VMLOAD        0x082
-#define SVM_EXIT_VMSAVE        0x083
-#define SVM_EXIT_STGI          0x084
-#define SVM_EXIT_CLGI          0x085
-#define SVM_EXIT_SKINIT        0x086
-#define SVM_EXIT_RDTSCP        0x087
-#define SVM_EXIT_ICEBP         0x088
-#define SVM_EXIT_WBINVD        0x089
-#define SVM_EXIT_MONITOR       0x08a
-#define SVM_EXIT_MWAIT         0x08b
-#define SVM_EXIT_MWAIT_COND    0x08c
-#define SVM_EXIT_XSETBV        0x08d
-#define SVM_EXIT_NPF           0x400
-
-#define SVM_EXIT_ERR           -1
-
-#define SVM_EXIT_REASONS \
-        { SVM_EXIT_READ_CR0,    "read_cr0" }, \
-        { SVM_EXIT_READ_CR3,    "read_cr3" }, \
-        { SVM_EXIT_READ_CR4,    "read_cr4" }, \
-        { SVM_EXIT_READ_CR8,    "read_cr8" }, \
-        { SVM_EXIT_WRITE_CR0,   "write_cr0" }, \
-        { SVM_EXIT_WRITE_CR3,   "write_cr3" }, \
-        { SVM_EXIT_WRITE_CR4,   "write_cr4" }, \
-        { SVM_EXIT_WRITE_CR8,   "write_cr8" }, \
-        { SVM_EXIT_READ_DR0,    "read_dr0" }, \
-        { SVM_EXIT_READ_DR1,    "read_dr1" }, \
-        { SVM_EXIT_READ_DR2,    "read_dr2" }, \
-        { SVM_EXIT_READ_DR3,    "read_dr3" }, \
-        { SVM_EXIT_WRITE_DR0,   "write_dr0" }, \
-        { SVM_EXIT_WRITE_DR1,   "write_dr1" }, \
-        { SVM_EXIT_WRITE_DR2,   "write_dr2" }, \
-        { SVM_EXIT_WRITE_DR3,   "write_dr3" }, \
-        { SVM_EXIT_WRITE_DR5,   "write_dr5" }, \
-        { SVM_EXIT_WRITE_DR7,   "write_dr7" }, \
-        { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" }, \
-        { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" }, \
-        { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" }, \
-        { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" }, \
-        { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" }, \
-        { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" }, \
-        { SVM_EXIT_INTR,        "interrupt" }, \
-        { SVM_EXIT_NMI,         "nmi" }, \
-        { SVM_EXIT_SMI,         "smi" }, \
-        { SVM_EXIT_INIT,        "init" }, \
-        { SVM_EXIT_VINTR,       "vintr" }, \
-        { SVM_EXIT_CPUID,       "cpuid" }, \
-        { SVM_EXIT_INVD,        "invd" }, \
-        { SVM_EXIT_HLT,         "hlt" }, \
-        { SVM_EXIT_INVLPG,      "invlpg" }, \
-        { SVM_EXIT_INVLPGA,     "invlpga" }, \
-        { SVM_EXIT_IOIO,        "io" }, \
-        { SVM_EXIT_MSR,         "msr" }, \
-        { SVM_EXIT_TASK_SWITCH, "task_switch" }, \
-        { SVM_EXIT_SHUTDOWN,    "shutdown" }, \
-        { SVM_EXIT_VMRUN,       "vmrun" }, \
-        { SVM_EXIT_VMMCALL,     "hypercall" }, \
-        { SVM_EXIT_VMLOAD,      "vmload" }, \
-        { SVM_EXIT_VMSAVE,      "vmsave" }, \
-        { SVM_EXIT_STGI,        "stgi" }, \
-        { SVM_EXIT_CLGI,        "clgi" }, \
-        { SVM_EXIT_SKINIT,      "skinit" }, \
-        { SVM_EXIT_WBINVD,      "wbinvd" }, \
-        { SVM_EXIT_MONITOR,     "monitor" }, \
-        { SVM_EXIT_MWAIT,       "mwait" }, \
-        { SVM_EXIT_XSETBV,      "xsetbv" }, \
-        { SVM_EXIT_NPF,         "npf" }
-
-
-#endif /* _UAPI__SVM_H */
diff --git a/arch/x86/include/uapi/asm/swab.h b/arch/x86/include/uapi/asm/swab.h
deleted file mode 100644
index 7f235c7105c..00000000000
--- a/arch/x86/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _ASM_X86_SWAB_H
-#define _ASM_X86_SWAB_H
-
-#include <linux/types.h>
-#include <linux/compiler.h>
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
-{
-        asm("bswapl %0" : "=r" (val) : "0" (val));
-        return val;
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute_const__ __u64 __arch_swab64(__u64 val)
-{
-#ifdef __i386__
-        union {
-                struct {
-                        __u32 a;
-                        __u32 b;
-                } s;
-                __u64 u;
-        } v;
-        v.u = val;
-        asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
-            : "=r" (v.s.a), "=r" (v.s.b)
-            : "0" (v.s.a), "1" (v.s.b));
-        return v.u;
-#else /* __i386__ */
-        asm("bswapq %0" : "=r" (val) : "0" (val));
-        return val;
-#endif
-}
-#define __arch_swab64 __arch_swab64
-
-#endif /* _ASM_X86_SWAB_H */
diff --git a/arch/x86/include/uapi/asm/termbits.h b/arch/x86/include/uapi/asm/termbits.h
deleted file mode 100644
index 3935b106de7..00000000000
--- a/arch/x86/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termbits.h>
diff --git a/arch/x86/include/uapi/asm/termios.h b/arch/x86/include/uapi/asm/termios.h
deleted file mode 100644
index 280d78a9d96..00000000000
--- a/arch/x86/include/uapi/asm/termios.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/termios.h>
diff --git a/arch/x86/include/uapi/asm/types.h b/arch/x86/include/uapi/asm/types.h
deleted file mode 100644
index 8e8c23fef08..00000000000
--- a/arch/x86/include/uapi/asm/types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_X86_TYPES_H
-#define _ASM_X86_TYPES_H
-
-#include <asm-generic/types.h>
-
-#endif /* _ASM_X86_TYPES_H */
diff --git a/arch/x86/include/uapi/asm/ucontext.h b/arch/x86/include/uapi/asm/ucontext.h
deleted file mode 100644
index b7c29c8017f..00000000000
--- a/arch/x86/include/uapi/asm/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_X86_UCONTEXT_H
-#define _ASM_X86_UCONTEXT_H
-
-#define UC_FP_XSTATE    0x1     /* indicates the presence of extended state
-                                 * information in the memory layout pointed
-                                 * by the fpstate pointer in the ucontext's
-                                 * sigcontext struct (uc_mcontext).
-                                 */
-
-#include <asm-generic/ucontext.h>
-
-#endif /* _ASM_X86_UCONTEXT_H */
diff --git a/arch/x86/include/uapi/asm/unistd.h b/arch/x86/include/uapi/asm/unistd.h
deleted file mode 100644
index a26df0d75cd..00000000000
--- a/arch/x86/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _UAPI_ASM_X86_UNISTD_H
-#define _UAPI_ASM_X86_UNISTD_H
-
-/* x32 syscall flag bit */
-#define __X32_SYSCALL_BIT       0x40000000
-
-#ifndef __KERNEL__
-# ifdef __i386__
-#  include <asm/unistd_32.h>
-# elif defined(__ILP32__)
-#  include <asm/unistd_x32.h>
-# else
-#  include <asm/unistd_64.h>
-# endif
-#endif
-
-#endif /* _UAPI_ASM_X86_UNISTD_H */
diff --git a/arch/x86/include/uapi/asm/vm86.h b/arch/x86/include/uapi/asm/vm86.h
deleted file mode 100644
index e0b243e9d85..00000000000
--- a/arch/x86/include/uapi/asm/vm86.h
+++ /dev/null
@@ -1,129 +0,0 @@
-#ifndef _UAPI_ASM_X86_VM86_H
-#define _UAPI_ASM_X86_VM86_H
-
-/*
- * I'm guessing at the VIF/VIP flag usage, but hope that this is how
- * the Pentium uses them. Linux will return from vm86 mode when both
- * VIF and VIP is set.
- *
- * On a Pentium, we could probably optimize the virtual flags directly
- * in the eflags register instead of doing it "by hand" in vflags...
- *
- * Linus
- */
-
-#include <asm/processor-flags.h>
-
-#define BIOSSEG         0x0f000
-
-#define CPU_086         0
-#define CPU_186         1
-#define CPU_286         2
-#define CPU_386         3
-#define CPU_486         4
-#define CPU_586         5
-
-/*
- * Return values for the 'vm86()' system call
- */
-#define VM86_TYPE(retval)       ((retval) & 0xff)
-#define VM86_ARG(retval)        ((retval) >> 8)
-
-#define VM86_SIGNAL     0       /* return due to signal */
-#define VM86_UNKNOWN    1       /* unhandled GP fault
-                                   - IO-instruction or similar */
-#define VM86_INTx       2       /* int3/int x instruction (ARG = x) */
-#define VM86_STI        3       /* sti/popf/iret instruction enabled
-                                   virtual interrupts */
-
-/*
- * Additional return values when invoking new vm86()
- */
-#define VM86_PICRETURN  4       /* return due to pending PIC request */
-#define VM86_TRAP       6       /* return due to DOS-debugger request */
-
-/*
- * function codes when invoking new vm86()
- */
-#define VM86_PLUS_INSTALL_CHECK 0
-#define VM86_ENTER              1
-#define VM86_ENTER_NO_BYPASS    2
-#define VM86_REQUEST_IRQ        3
-#define VM86_FREE_IRQ           4
-#define VM86_GET_IRQ_BITS       5
-#define VM86_GET_AND_RESET_IRQ  6
-
-/*
- * This is the stack-layout seen by the user space program when we have
- * done a translation of "SAVE_ALL" from vm86 mode. The real kernel layout
- * is 'kernel_vm86_regs' (see below).
- */
-
-struct vm86_regs {
-/*
- * normal regs, with special meaning for the segment descriptors..
- */
-        long ebx;
-        long ecx;
-        long edx;
-        long esi;
-        long edi;
-        long ebp;
-        long eax;
-        long __null_ds;
-        long __null_es;
-        long __null_fs;
-        long __null_gs;
-        long orig_eax;
-        long eip;
-        unsigned short cs, __csh;
-        long eflags;
-        long esp;
-        unsigned short ss, __ssh;
-/*
- * these are specific to v86 mode:
- */
-        unsigned short es, __esh;
-        unsigned short ds, __dsh;
-        unsigned short fs, __fsh;
-        unsigned short gs, __gsh;
-};
-
-struct revectored_struct {
-        unsigned long __map[8];                 /* 256 bits */
-};
-
-struct vm86_struct {
-        struct vm86_regs regs;
-        unsigned long flags;
-        unsigned long screen_bitmap;
-        unsigned long cpu_type;
-        struct revectored_struct int_revectored;
-        struct revectored_struct int21_revectored;
-};
-
-/*
- * flags masks
- */
-#define VM86_SCREEN_BITMAP      0x0001
-
-struct vm86plus_info_struct {
-        unsigned long force_return_for_pic:1;
-        unsigned long vm86dbg_active:1;       /* for debugger */
-        unsigned long vm86dbg_TFpendig:1;     /* for debugger */
-        unsigned long unused:28;
-        unsigned long is_vm86pus:1;           /* for vm86 internal use */
-        unsigned char vm86dbg_intxxtab[32];   /* for debugger */
-};
-struct vm86plus_struct {
-        struct vm86_regs regs;
-        unsigned long flags;
-        unsigned long screen_bitmap;
-        unsigned long cpu_type;
-        struct revectored_struct int_revectored;
-        struct revectored_struct int21_revectored;
-        struct vm86plus_info_struct vm86plus;
-};
-
-
-#endif /* _UAPI_ASM_X86_VM86_H */
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
deleted file mode 100644
index 979d03bce13..00000000000
--- a/arch/x86/include/uapi/asm/vmx.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * vmx.h: VMX Architecture related definitions
- * Copyright (c) 2004, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * A few random additions are:
- * Copyright (C) 2006 Qumranet
- *    Avi Kivity <avi@qumranet.com>
- *    Yaniv Kamay <yaniv@qumranet.com>
- *
- */
-#ifndef _UAPIVMX_H
-#define _UAPIVMX_H
-
-
-#define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
-
-#define EXIT_REASON_EXCEPTION_NMI       0
-#define EXIT_REASON_EXTERNAL_INTERRUPT  1
-#define EXIT_REASON_TRIPLE_FAULT        2
-
-#define EXIT_REASON_PENDING_INTERRUPT   7
-#define EXIT_REASON_NMI_WINDOW          8
-#define EXIT_REASON_TASK_SWITCH         9
-#define EXIT_REASON_CPUID               10
-#define EXIT_REASON_HLT                 12
-#define EXIT_REASON_INVD                13
-#define EXIT_REASON_INVLPG              14
-#define EXIT_REASON_RDPMC               15
-#define EXIT_REASON_RDTSC               16
-#define EXIT_REASON_VMCALL              18
-#define EXIT_REASON_VMCLEAR             19
-#define EXIT_REASON_VMLAUNCH            20
-#define EXIT_REASON_VMPTRLD             21
-#define EXIT_REASON_VMPTRST             22
-#define EXIT_REASON_VMREAD              23
-#define EXIT_REASON_VMRESUME            24
-#define EXIT_REASON_VMWRITE             25
-#define EXIT_REASON_VMOFF               26
-#define EXIT_REASON_VMON                27
-#define EXIT_REASON_CR_ACCESS           28
-#define EXIT_REASON_DR_ACCESS           29
-#define EXIT_REASON_IO_INSTRUCTION      30
-#define EXIT_REASON_MSR_READ            31
-#define EXIT_REASON_MSR_WRITE           32
-#define EXIT_REASON_INVALID_STATE       33
-#define EXIT_REASON_MWAIT_INSTRUCTION   36
-#define EXIT_REASON_MONITOR_INSTRUCTION 39
-#define EXIT_REASON_PAUSE_INSTRUCTION   40
-#define EXIT_REASON_MCE_DURING_VMENTRY  41
-#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
-#define EXIT_REASON_APIC_ACCESS         44
-#define EXIT_REASON_EPT_VIOLATION       48
-#define EXIT_REASON_EPT_MISCONFIG       49
-#define EXIT_REASON_WBINVD              54
-#define EXIT_REASON_XSETBV              55
-#define EXIT_REASON_INVPCID             58
-
-#define VMX_EXIT_REASONS \
-        { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
-        { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
-        { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
-        { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
-        { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
-        { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
-        { EXIT_REASON_CPUID,                 "CPUID" }, \
-        { EXIT_REASON_HLT,                   "HLT" }, \
-        { EXIT_REASON_INVLPG,                "INVLPG" }, \
-        { EXIT_REASON_RDPMC,                 "RDPMC" }, \
-        { EXIT_REASON_RDTSC,                 "RDTSC" }, \
-        { EXIT_REASON_VMCALL,                "VMCALL" }, \
-        { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
-        { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
-        { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
-        { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
-        { EXIT_REASON_VMREAD,                "VMREAD" }, \
-        { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
-        { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
-        { EXIT_REASON_VMOFF,                 "VMOFF" }, \
-        { EXIT_REASON_VMON,                  "VMON" }, \
-        { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
-        { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
-        { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
-        { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
-        { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
-        { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
-        { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
-        { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
-        { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
-        { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
-        { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
-        { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
-        { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
-        { EXIT_REASON_WBINVD,                "WBINVD" }
-
-
-#endif /* _UAPIVMX_H */
diff --git a/arch/x86/include/uapi/asm/vsyscall.h b/arch/x86/include/uapi/asm/vsyscall.h
deleted file mode 100644
index 85dc1b3825a..00000000000
--- a/arch/x86/include/uapi/asm/vsyscall.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _UAPI_ASM_X86_VSYSCALL_H
-#define _UAPI_ASM_X86_VSYSCALL_H
-
-enum vsyscall_num {
-        __NR_vgettimeofday,
-        __NR_vtime,
-        __NR_vgetcpu,
-};
-
-#define VSYSCALL_START (-10UL << 20)
-#define VSYSCALL_SIZE 1024
-#define VSYSCALL_END (-2UL << 20)
-#define VSYSCALL_MAPPED_PAGES 1
-#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr))
-
-
-#endif /* _UAPI_ASM_X86_VSYSCALL_H */