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authorIngo Molnar <mingo@elte.hu>2008-10-28 11:54:49 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-28 11:54:49 -0400
commitd1a76187a5be4f89c6cb19d800cb5fb7aac735c5 (patch)
tree2fac3ffbfffc7560eeef8364b541d0d7a0057920 /arch/x86/include/asm/summit
parentc7e78cff6b7518212247fb20b1dc6411540dc9af (diff)
parent0173a3265b228da319ceb9c1ec6a5682fd1b2d92 (diff)
Merge commit 'v2.6.28-rc2' into core/locking
Conflicts: arch/um/include/asm/system.h
Diffstat (limited to 'arch/x86/include/asm/summit')
-rw-r--r--arch/x86/include/asm/summit/apic.h184
-rw-r--r--arch/x86/include/asm/summit/apicdef.h13
-rw-r--r--arch/x86/include/asm/summit/ipi.h25
-rw-r--r--arch/x86/include/asm/summit/mpparse.h109
4 files changed, 331 insertions, 0 deletions
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h
new file mode 100644
index 00000000000..9b3070f1c2a
--- /dev/null
+++ b/arch/x86/include/asm/summit/apic.h
@@ -0,0 +1,184 @@
1#ifndef __ASM_SUMMIT_APIC_H
2#define __ASM_SUMMIT_APIC_H
3
4#include <asm/smp.h>
5
6#define esr_disable (1)
7#define NO_BALANCE_IRQ (0)
8
9/* In clustered mode, the high nibble of APIC ID is a cluster number.
10 * The low nibble is a 4-bit bitmap. */
11#define XAPIC_DEST_CPUS_SHIFT 4
12#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
13#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
14
15#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
16
17static inline cpumask_t target_cpus(void)
18{
19 /* CPU_MASK_ALL (0xff) has undefined behaviour with
20 * dest_LowestPrio mode logical clustered apic interrupt routing
21 * Just start on cpu 0. IRQ balancing will spread load
22 */
23 return cpumask_of_cpu(0);
24}
25
26#define INT_DELIVERY_MODE (dest_LowestPrio)
27#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
28
29static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
30{
31 return 0;
32}
33
34/* we don't use the phys_cpu_present_map to indicate apicid presence */
35static inline unsigned long check_apicid_present(int bit)
36{
37 return 1;
38}
39
40#define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
41
42extern u8 cpu_2_logical_apicid[];
43
44static inline void init_apic_ldr(void)
45{
46 unsigned long val, id;
47 int count = 0;
48 u8 my_id = (u8)hard_smp_processor_id();
49 u8 my_cluster = (u8)apicid_cluster(my_id);
50#ifdef CONFIG_SMP
51 u8 lid;
52 int i;
53
54 /* Create logical APIC IDs by counting CPUs already in cluster. */
55 for (count = 0, i = NR_CPUS; --i >= 0; ) {
56 lid = cpu_2_logical_apicid[i];
57 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
58 ++count;
59 }
60#endif
61 /* We only have a 4 wide bitmap in cluster mode. If a deranged
62 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
63 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
64 id = my_cluster | (1UL << count);
65 apic_write(APIC_DFR, APIC_DFR_VALUE);
66 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
67 val |= SET_APIC_LOGICAL_ID(id);
68 apic_write(APIC_LDR, val);
69}
70
71static inline int multi_timer_check(int apic, int irq)
72{
73 return 0;
74}
75
76static inline int apic_id_registered(void)
77{
78 return 1;
79}
80
81static inline void setup_apic_routing(void)
82{
83 printk("Enabling APIC mode: Summit. Using %d I/O APICs\n",
84 nr_ioapics);
85}
86
87static inline int apicid_to_node(int logical_apicid)
88{
89#ifdef CONFIG_SMP
90 return apicid_2_node[hard_smp_processor_id()];
91#else
92 return 0;
93#endif
94}
95
96/* Mapping from cpu number to logical apicid */
97static inline int cpu_to_logical_apicid(int cpu)
98{
99#ifdef CONFIG_SMP
100 if (cpu >= NR_CPUS)
101 return BAD_APICID;
102 return (int)cpu_2_logical_apicid[cpu];
103#else
104 return logical_smp_processor_id();
105#endif
106}
107
108static inline int cpu_present_to_apicid(int mps_cpu)
109{
110 if (mps_cpu < NR_CPUS)
111 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
112 else
113 return BAD_APICID;
114}
115
116static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
117{
118 /* For clustered we don't have a good way to do this yet - hack */
119 return physids_promote(0x0F);
120}
121
122static inline physid_mask_t apicid_to_cpu_present(int apicid)
123{
124 return physid_mask_of_physid(0);
125}
126
127static inline void setup_portio_remap(void)
128{
129}
130
131static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
132{
133 return 1;
134}
135
136static inline void enable_apic_mode(void)
137{
138}
139
140static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
141{
142 int num_bits_set;
143 int cpus_found = 0;
144 int cpu;
145 int apicid;
146
147 num_bits_set = cpus_weight(cpumask);
148 /* Return id to all */
149 if (num_bits_set == NR_CPUS)
150 return (int) 0xFF;
151 /*
152 * The cpus in the mask must all be on the apic cluster. If are not
153 * on the same apicid cluster return default value of TARGET_CPUS.
154 */
155 cpu = first_cpu(cpumask);
156 apicid = cpu_to_logical_apicid(cpu);
157 while (cpus_found < num_bits_set) {
158 if (cpu_isset(cpu, cpumask)) {
159 int new_apicid = cpu_to_logical_apicid(cpu);
160 if (apicid_cluster(apicid) !=
161 apicid_cluster(new_apicid)){
162 printk ("%s: Not a valid mask!\n", __func__);
163 return 0xFF;
164 }
165 apicid = apicid | new_apicid;
166 cpus_found++;
167 }
168 cpu++;
169 }
170 return apicid;
171}
172
173/* cpuid returns the value latched in the HW at reset, not the APIC ID
174 * register's value. For any box whose BIOS changes APIC IDs, like
175 * clustered APIC systems, we must use hard_smp_processor_id.
176 *
177 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
178 */
179static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
180{
181 return hard_smp_processor_id() >> index_msb;
182}
183
184#endif /* __ASM_SUMMIT_APIC_H */
diff --git a/arch/x86/include/asm/summit/apicdef.h b/arch/x86/include/asm/summit/apicdef.h
new file mode 100644
index 00000000000..f3fbca1f61c
--- /dev/null
+++ b/arch/x86/include/asm/summit/apicdef.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_SUMMIT_APICDEF_H
2#define __ASM_SUMMIT_APICDEF_H
3
4#define APIC_ID_MASK (0xFF<<24)
5
6static inline unsigned get_apic_id(unsigned long x)
7{
8 return (x>>24)&0xFF;
9}
10
11#define GET_APIC_ID(x) get_apic_id(x)
12
13#endif
diff --git a/arch/x86/include/asm/summit/ipi.h b/arch/x86/include/asm/summit/ipi.h
new file mode 100644
index 00000000000..53bd1e7bd7b
--- /dev/null
+++ b/arch/x86/include/asm/summit/ipi.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_SUMMIT_IPI_H
2#define __ASM_SUMMIT_IPI_H
3
4void send_IPI_mask_sequence(cpumask_t mask, int vector);
5
6static inline void send_IPI_mask(cpumask_t mask, int vector)
7{
8 send_IPI_mask_sequence(mask, vector);
9}
10
11static inline void send_IPI_allbutself(int vector)
12{
13 cpumask_t mask = cpu_online_map;
14 cpu_clear(smp_processor_id(), mask);
15
16 if (!cpus_empty(mask))
17 send_IPI_mask(mask, vector);
18}
19
20static inline void send_IPI_all(int vector)
21{
22 send_IPI_mask(cpu_online_map, vector);
23}
24
25#endif /* __ASM_SUMMIT_IPI_H */
diff --git a/arch/x86/include/asm/summit/mpparse.h b/arch/x86/include/asm/summit/mpparse.h
new file mode 100644
index 00000000000..013ce6fab2d
--- /dev/null
+++ b/arch/x86/include/asm/summit/mpparse.h
@@ -0,0 +1,109 @@
1#ifndef __ASM_SUMMIT_MPPARSE_H
2#define __ASM_SUMMIT_MPPARSE_H
3
4#include <asm/tsc.h>
5
6extern int use_cyclone;
7
8#ifdef CONFIG_X86_SUMMIT_NUMA
9extern void setup_summit(void);
10#else
11#define setup_summit() {}
12#endif
13
14static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
15 char *productid)
16{
17 if (!strncmp(oem, "IBM ENSW", 8) &&
18 (!strncmp(productid, "VIGIL SMP", 9)
19 || !strncmp(productid, "EXA", 3)
20 || !strncmp(productid, "RUTHLESS SMP", 12))){
21 mark_tsc_unstable("Summit based system");
22 use_cyclone = 1; /*enable cyclone-timer*/
23 setup_summit();
24 return 1;
25 }
26 return 0;
27}
28
29/* Hook from generic ACPI tables.c */
30static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
31{
32 if (!strncmp(oem_id, "IBM", 3) &&
33 (!strncmp(oem_table_id, "SERVIGIL", 8)
34 || !strncmp(oem_table_id, "EXA", 3))){
35 mark_tsc_unstable("Summit based system");
36 use_cyclone = 1; /*enable cyclone-timer*/
37 setup_summit();
38 return 1;
39 }
40 return 0;
41}
42
43struct rio_table_hdr {
44 unsigned char version; /* Version number of this data structure */
45 /* Version 3 adds chassis_num & WP_index */
46 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */
47 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */
48} __attribute__((packed));
49
50struct scal_detail {
51 unsigned char node_id; /* Scalability Node ID */
52 unsigned long CBAR; /* Address of 1MB register space */
53 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
54 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
55 unsigned char port1node; /* Node ID port connected to: 0xFF = None */
56 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
57 unsigned char port2node; /* Node ID port connected to: 0xFF = None */
58 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */
59 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */
60} __attribute__((packed));
61
62struct rio_detail {
63 unsigned char node_id; /* RIO Node ID */
64 unsigned long BBAR; /* Address of 1MB register space */
65 unsigned char type; /* Type of device */
66 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/
67 /* For CYC: Node ID of Twister that owns this CYC */
68 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
69 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
70 unsigned char port1node; /* Node ID port connected to: 0xFF=None */
71 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
72 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */
73 /* For CYC: 0 */
74 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */
75 /* = 0 : the XAPIC is not used, ie:*/
76 /* ints fwded to another XAPIC */
77 /* Bits1:7 Reserved */
78 /* For CYC: Bits0:7 Reserved */
79 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */
80 /* lower slot numbers/PCI bus numbers */
81 /* For CYC: No meaning */
82 unsigned char chassis_num; /* 1 based Chassis number */
83 /* For LookOut WPEGs this field indicates the */
84 /* Expansion Chassis #, enumerated from Boot */
85 /* Node WPEG external port, then Boot Node CYC */
86 /* external port, then Next Vigil chassis WPEG */
87 /* external port, etc. */
88 /* Shared Lookouts have only 1 chassis number (the */
89 /* first one assigned) */
90} __attribute__((packed));
91
92
93typedef enum {
94 CompatTwister = 0, /* Compatibility Twister */
95 AltTwister = 1, /* Alternate Twister of internal 8-way */
96 CompatCyclone = 2, /* Compatibility Cyclone */
97 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */
98 CompatWPEG = 4, /* Compatibility WPEG */
99 AltWPEG = 5, /* Second Planar WPEG */
100 LookOutAWPEG = 6, /* LookOut WPEG */
101 LookOutBWPEG = 7, /* LookOut WPEG */
102} node_type;
103
104static inline int is_WPEG(struct rio_detail *rio){
105 return (rio->type == CompatWPEG || rio->type == AltWPEG ||
106 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
107}
108
109#endif /* __ASM_SUMMIT_MPPARSE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 14:43:35 -0400