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authorJamie Iles <jamie@jamieiles.com>2011-06-06 07:43:07 -0400
committerJohn Stultz <john.stultz@linaro.org>2011-06-27 18:16:21 -0400
commit06c3df49521c1b112b777cc4946e5de057c814ba (patch)
tree34989a358e7554d82dd4e73328f492653ceeac88 /arch/x86/include/asm/apb_timer.h
parentaf4087e0e682df12bdffec5cfafc2fec9208716e (diff)
clocksource: apb: Share APB timer code with other platforms
The APB timers are an IP block from Synopsys (DesignWare APB timers) and are also found in other systems including ARM SoC's. This patch adds functions for creating clock_event_devices and clocksources from APB timers but does not do the resource allocation. This is handled in a higher layer to allow the timers to be created from multiple methods such as platform_devices. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'arch/x86/include/asm/apb_timer.h')
-rw-r--r--arch/x86/include/asm/apb_timer.h22
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index 2fefa501d3b..230000f124a 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -18,24 +18,6 @@
18 18
19#ifdef CONFIG_APB_TIMER 19#ifdef CONFIG_APB_TIMER
20 20
21/* Langwell DW APB timer registers */
22#define APBTMR_N_LOAD_COUNT 0x00
23#define APBTMR_N_CURRENT_VALUE 0x04
24#define APBTMR_N_CONTROL 0x08
25#define APBTMR_N_EOI 0x0c
26#define APBTMR_N_INT_STATUS 0x10
27
28#define APBTMRS_INT_STATUS 0xa0
29#define APBTMRS_EOI 0xa4
30#define APBTMRS_RAW_INT_STATUS 0xa8
31#define APBTMRS_COMP_VERSION 0xac
32#define APBTMRS_REG_SIZE 0x14
33
34/* register bits */
35#define APBTMR_CONTROL_ENABLE (1<<0)
36#define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */
37#define APBTMR_CONTROL_INT (1<<2)
38
39/* default memory mapped register base */ 21/* default memory mapped register base */
40#define LNW_SCU_ADDR 0xFF100000 22#define LNW_SCU_ADDR 0xFF100000
41#define LNW_EXT_TIMER_OFFSET 0x1B800 23#define LNW_EXT_TIMER_OFFSET 0x1B800
@@ -43,8 +25,8 @@
43#define LNW_EXT_TIMER_PGOFFSET 0x800 25#define LNW_EXT_TIMER_PGOFFSET 0x800
44 26
45/* APBT clock speed range from PCLK to fabric base, 25-100MHz */ 27/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
46#define APBT_MAX_FREQ 50 28#define APBT_MAX_FREQ 50000000
47#define APBT_MIN_FREQ 1 29#define APBT_MIN_FREQ 1000000
48#define APBT_MMAP_SIZE 1024 30#define APBT_MMAP_SIZE 1024
49 31
50#define APBT_DEV_USED 1 32#define APBT_DEV_USED 1