diff options
author | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-01-15 05:21:56 -0500 |
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committer | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-16 21:19:12 -0400 |
commit | 6dea1ba1c82013c108d235ec32c6d8bd9ff6b48d (patch) | |
tree | b355276d07db73b1618e045571d13348fd554399 /arch/unicore32/include | |
parent | d9bc15794d122cb7bdc9a069d22f3d3166dd31d4 (diff) |
unicore32 additional architecture files: ptrace handling
This patch adds ptrace support.
Changed from previous version:
1. disable arch_has_single_step and remove single-step instruction handler
2. add 'Ross Biro 1/23/92' contributor information
3. clean unused codes
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/include')
-rw-r--r-- | arch/unicore32/include/asm/ptrace.h | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/arch/unicore32/include/asm/ptrace.h b/arch/unicore32/include/asm/ptrace.h new file mode 100644 index 00000000000..b9caf9b0997 --- /dev/null +++ b/arch/unicore32/include/asm/ptrace.h | |||
@@ -0,0 +1,133 @@ | |||
1 | /* | ||
2 | * linux/arch/unicore32/include/asm/ptrace.h | ||
3 | * | ||
4 | * Code specific to PKUnity SoC and UniCore ISA | ||
5 | * | ||
6 | * Copyright (C) 2001-2010 GUAN Xue-tao | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | #ifndef __UNICORE_PTRACE_H__ | ||
13 | #define __UNICORE_PTRACE_H__ | ||
14 | |||
15 | #define PTRACE_GET_THREAD_AREA 22 | ||
16 | |||
17 | /* | ||
18 | * PSR bits | ||
19 | */ | ||
20 | #define USER_MODE 0x00000010 | ||
21 | #define REAL_MODE 0x00000011 | ||
22 | #define INTR_MODE 0x00000012 | ||
23 | #define PRIV_MODE 0x00000013 | ||
24 | #define ABRT_MODE 0x00000017 | ||
25 | #define EXTN_MODE 0x0000001b | ||
26 | #define SUSR_MODE 0x0000001f | ||
27 | #define MODE_MASK 0x0000001f | ||
28 | #define PSR_R_BIT 0x00000040 | ||
29 | #define PSR_I_BIT 0x00000080 | ||
30 | #define PSR_V_BIT 0x10000000 | ||
31 | #define PSR_C_BIT 0x20000000 | ||
32 | #define PSR_Z_BIT 0x40000000 | ||
33 | #define PSR_S_BIT 0x80000000 | ||
34 | |||
35 | /* | ||
36 | * Groups of PSR bits | ||
37 | */ | ||
38 | #define PSR_f 0xff000000 /* Flags */ | ||
39 | #define PSR_c 0x000000ff /* Control */ | ||
40 | |||
41 | #ifndef __ASSEMBLY__ | ||
42 | |||
43 | /* | ||
44 | * This struct defines the way the registers are stored on the | ||
45 | * stack during a system call. Note that sizeof(struct pt_regs) | ||
46 | * has to be a multiple of 8. | ||
47 | */ | ||
48 | struct pt_regs { | ||
49 | unsigned long uregs[34]; | ||
50 | }; | ||
51 | |||
52 | #define UCreg_asr uregs[32] | ||
53 | #define UCreg_pc uregs[31] | ||
54 | #define UCreg_lr uregs[30] | ||
55 | #define UCreg_sp uregs[29] | ||
56 | #define UCreg_ip uregs[28] | ||
57 | #define UCreg_fp uregs[27] | ||
58 | #define UCreg_26 uregs[26] | ||
59 | #define UCreg_25 uregs[25] | ||
60 | #define UCreg_24 uregs[24] | ||
61 | #define UCreg_23 uregs[23] | ||
62 | #define UCreg_22 uregs[22] | ||
63 | #define UCreg_21 uregs[21] | ||
64 | #define UCreg_20 uregs[20] | ||
65 | #define UCreg_19 uregs[19] | ||
66 | #define UCreg_18 uregs[18] | ||
67 | #define UCreg_17 uregs[17] | ||
68 | #define UCreg_16 uregs[16] | ||
69 | #define UCreg_15 uregs[15] | ||
70 | #define UCreg_14 uregs[14] | ||
71 | #define UCreg_13 uregs[13] | ||
72 | #define UCreg_12 uregs[12] | ||
73 | #define UCreg_11 uregs[11] | ||
74 | #define UCreg_10 uregs[10] | ||
75 | #define UCreg_09 uregs[9] | ||
76 | #define UCreg_08 uregs[8] | ||
77 | #define UCreg_07 uregs[7] | ||
78 | #define UCreg_06 uregs[6] | ||
79 | #define UCreg_05 uregs[5] | ||
80 | #define UCreg_04 uregs[4] | ||
81 | #define UCreg_03 uregs[3] | ||
82 | #define UCreg_02 uregs[2] | ||
83 | #define UCreg_01 uregs[1] | ||
84 | #define UCreg_00 uregs[0] | ||
85 | #define UCreg_ORIG_00 uregs[33] | ||
86 | |||
87 | #ifdef __KERNEL__ | ||
88 | |||
89 | #define user_mode(regs) \ | ||
90 | (processor_mode(regs) == USER_MODE) | ||
91 | |||
92 | #define processor_mode(regs) \ | ||
93 | ((regs)->UCreg_asr & MODE_MASK) | ||
94 | |||
95 | #define interrupts_enabled(regs) \ | ||
96 | (!((regs)->UCreg_asr & PSR_I_BIT)) | ||
97 | |||
98 | #define fast_interrupts_enabled(regs) \ | ||
99 | (!((regs)->UCreg_asr & PSR_R_BIT)) | ||
100 | |||
101 | /* Are the current registers suitable for user mode? | ||
102 | * (used to maintain security in signal handlers) | ||
103 | */ | ||
104 | static inline int valid_user_regs(struct pt_regs *regs) | ||
105 | { | ||
106 | unsigned long mode = regs->UCreg_asr & MODE_MASK; | ||
107 | |||
108 | /* | ||
109 | * Always clear the R (REAL) bits | ||
110 | */ | ||
111 | regs->UCreg_asr &= ~(PSR_R_BIT); | ||
112 | |||
113 | if ((regs->UCreg_asr & PSR_I_BIT) == 0) { | ||
114 | if (mode == USER_MODE) | ||
115 | return 1; | ||
116 | } | ||
117 | |||
118 | /* | ||
119 | * Force ASR to something logical... | ||
120 | */ | ||
121 | regs->UCreg_asr &= PSR_f | USER_MODE; | ||
122 | |||
123 | return 0; | ||
124 | } | ||
125 | |||
126 | #define instruction_pointer(regs) ((regs)->UCreg_pc) | ||
127 | |||
128 | #endif /* __KERNEL__ */ | ||
129 | |||
130 | #endif /* __ASSEMBLY__ */ | ||
131 | |||
132 | #endif | ||
133 | |||