Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

Pull arch/tile bug fixes from Chris Metcalf:
 "This includes Paul Gortmaker's change to fix the <asm/system.h>
  disintegration issues on tile, a fix to unbreak the tilepro ethernet
  driver, and a backlog of bugfix-only changes from internal Tilera
  development over the last few months.

  They have all been to LKML and on linux-next for the last few days.
  The EDAC change to MAINTAINERS is an oddity but discussion on the
  linux-edac list suggested I ask you to pull that change through my
  tree since they don't have a tree to pull edac changes from at the
  moment."

* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (39 commits)
  drivers/net/ethernet/tile: fix netdev_alloc_skb() bombing
  MAINTAINERS: update EDAC information
  tilepro ethernet driver: fix a few minor issues
  tile-srom.c driver: minor code cleanup
  edac: say "TILEGx" not "TILEPro" for the tilegx edac driver
  arch/tile: avoid accidentally unmasking NMI-type interrupt accidentally
  arch/tile: remove bogus performance optimization
  arch/tile: return SIGBUS for addresses that are unaligned AND invalid
  arch/tile: fix finv_buffer_remote() for tilegx
  arch/tile: use atomic exchange in arch_write_unlock()
  arch/tile: stop mentioning the "kvm" subdirectory
  arch/tile: export the page_home() function.
  arch/tile: fix pointer cast in cacheflush.c
  arch/tile: fix single-stepping over swint1 instructions on tilegx
  arch/tile: implement panic_smp_self_stop()
  arch/tile: add "nop" after "nap" to help GX idle power draw
  arch/tile: use proper memparse() for "maxmem" options
  arch/tile: fix up locking in pgtable.c slightly
  arch/tile: don't leak kernel memory when we unload modules
  arch/tile: fix bug in delay_backoff()
  ...

1 files changed, 27 insertions, 3 deletions

diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 8928aace7a6..db4fb89e12d 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -39,7 +39,21 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
 {
         char *p, *base;
         size_t step_size, load_count;
+
+        /*
+         * On TILEPro the striping granularity is a fixed 8KB; on
+         * TILE-Gx it is configurable, and we rely on the fact that
+         * the hypervisor always configures maximum striping, so that
+         * bits 9 and 10 of the PA are part of the stripe function, so
+         * every 512 bytes we hit a striping boundary.
+         *
+         */
+#ifdef __tilegx__
+        const unsigned long STRIPE_WIDTH = 512;
+#else
         const unsigned long STRIPE_WIDTH = 8192;
+#endif
+
 #ifdef __tilegx__
         /*
          * On TILE-Gx, we must disable the dstream prefetcher before doing
@@ -74,7 +88,7 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
          * memory, that one load would be sufficient, but since we may
          * be, we also need to back up to the last load issued to
          * another memory controller, which would be the point where
-         * we crossed an 8KB boundary (the granularity of striping
+         * we crossed a "striping" boundary (the granularity of striping
          * across memory controllers).  Keep backing up and doing this
          * until we are before the beginning of the buffer, or have
          * hit all the controllers.
@@ -88,12 +102,22 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
          * every cache line on a full memory stripe on each
          * controller" that we simply do that, to simplify the logic.
          *
-         * FIXME: See bug 9535 for some issues with this code.
+         * On TILE-Gx the hash-for-home function is much more complex,
+         * with the upshot being we can't readily guarantee we have
+         * hit both entries in the 128-entry AMT that were hit by any
+         * load in the entire range, so we just re-load them all.
+         * With larger buffers, we may want to consider using a hypervisor
+         * trap to issue loads directly to each hash-for-home tile for
+         * each controller (doing it from Linux would trash the TLB).
          */
         if (hfh) {
                 step_size = L2_CACHE_BYTES;
+#ifdef __tilegx__
+                load_count = (size + L2_CACHE_BYTES - 1) / L2_CACHE_BYTES;
+#else
                 load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
                               (1 << CHIP_LOG_NUM_MSHIMS());
+#endif
         } else {
                 step_size = STRIPE_WIDTH;
                 load_count = (1 << CHIP_LOG_NUM_MSHIMS());
@@ -109,7 +133,7 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
 
         /* Figure out how far back we need to go. */
         base = p - (step_size * (load_count - 2));
-        if ((long)base < (long)buffer)
+        if ((unsigned long)base < (unsigned long)buffer)
                 base = buffer;
 
         /*