sparc64: Make %pil level 15 a pseudo-NMI.

So that we can profile code even in a local_irq_disable() section,
only write 14 (instead of 15) into the %pil register to disable IRQs.

This allows PIL level 15 to serve as a pseudo NMI.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/sparc64/kernel/sun4v_ivec.S b/arch/sparc64/kernel/sun4v_ivec.S
index e2f8e1b4882..559bc5e9c19 100644
--- a/arch/sparc64/kernel/sun4v_ivec.S
+++ b/arch/sparc64/kernel/sun4v_ivec.S
@@ -186,7 +186,7 @@ sun4v_res_mondo:
          * when it's done.
          */
         rdpr    %pil, %g2
-        wrpr    %g0, 15, %pil
+        wrpr    %g0, PIL_NORMAL_MAX, %pil
         mov     %g1, %g4
         ba,pt   %xcc, etrap_irq
          rd     %pc, %g7
@@ -216,7 +216,7 @@ sun4v_res_mondo_queue_full:
         membar  #Sync
 
         rdpr    %pil, %g2
-        wrpr    %g0, 15, %pil
+        wrpr    %g0, PIL_NORMAL_MAX, %pil
         ba,pt   %xcc, etrap_irq
          rd     %pc, %g7
 #ifdef CONFIG_TRACE_IRQFLAGS
@@ -297,7 +297,7 @@ sun4v_nonres_mondo:
          * when it's done.
          */
         rdpr    %pil, %g2
-        wrpr    %g0, 15, %pil
+        wrpr    %g0, PIL_NORMAL_MAX, %pil
         mov     %g1, %g4
         ba,pt   %xcc, etrap_irq
          rd     %pc, %g7
@@ -327,7 +327,7 @@ sun4v_nonres_mondo_queue_full:
         membar  #Sync
 
         rdpr    %pil, %g2
-        wrpr    %g0, 15, %pil
+        wrpr    %g0, PIL_NORMAL_MAX, %pil
         ba,pt   %xcc, etrap_irq
          rd     %pc, %g7
 #ifdef CONFIG_TRACE_IRQFLAGS