Added missing tegra files.HEADmaster

48 files changed, 3728 insertions, 0 deletions

diff --git a/arch/sparc/include/asm/apc.h b/arch/sparc/include/asm/apc.h
new file mode 100644
index 00000000000..24e9a7d4d97
--- /dev/null
+++ b/arch/sparc/include/asm/apc.h
@@ -0,0 +1,64 @@
+/* apc - Driver definitions for power management functions
+ * of Aurora Personality Chip (APC) on SPARCstation-4/5 and 
+ * derivatives
+ *
+ * Copyright (c) 2001 Eric Brower (ebrower@usa.net)
+ *
+ */
+
+#ifndef _SPARC_APC_H
+#define _SPARC_APC_H
+
+#include <linux/ioctl.h>
+
+#define APC_IOC 'A'
+
+#define APCIOCGFANCTL _IOR(APC_IOC, 0x00, int)  /* Get fan speed        */
+#define APCIOCSFANCTL _IOW(APC_IOC, 0x01, int)  /* Set fan speed        */
+
+#define APCIOCGCPWR   _IOR(APC_IOC, 0x02, int)  /* Get CPOWER state     */
+#define APCIOCSCPWR   _IOW(APC_IOC, 0x03, int)  /* Set CPOWER state     */
+
+#define APCIOCGBPORT   _IOR(APC_IOC, 0x04, int) /* Get BPORT state      */
+#define APCIOCSBPORT   _IOW(APC_IOC, 0x05, int) /* Set BPORT state      */
+
+/*
+ * Register offsets
+ */
+#define APC_IDLE_REG    0x00
+#define APC_FANCTL_REG  0x20
+#define APC_CPOWER_REG  0x24
+#define APC_BPORT_REG   0x30
+
+#define APC_REGMASK             0x01
+#define APC_BPMASK              0x03
+
+/*
+ * IDLE - CPU standby values (set to initiate standby)
+ */
+#define APC_IDLE_ON             0x01
+
+/*
+ * FANCTL - Fan speed control state values
+ */
+#define APC_FANCTL_HI   0x00    /* Fan speed high       */
+#define APC_FANCTL_LO   0x01    /* Fan speed low        */
+
+/*
+ * CPWR - Convenience power outlet state values 
+ */
+#define APC_CPOWER_ON   0x00    /* Conv power on        */
+#define APC_CPOWER_OFF  0x01    /* Conv power off       */
+
+/*
+ * BPA/BPB - Read-Write "Bit Ports" state values (reset to 0 at power-on)
+ *
+ * WARNING: Internal usage of bit ports is platform dependent--
+ * don't modify BPORT settings unless you know what you are doing.
+ * 
+ * On SS5 BPA seems to toggle onboard ethernet loopback... -E
+ */
+#define APC_BPORT_A             0x01    /* Bit Port A           */
+#define APC_BPORT_B             0x02    /* Bit Port B           */
+
+#endif /* !(_SPARC_APC_H) */
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
new file mode 100644
index 00000000000..b2e3db63a64
--- /dev/null
+++ b/arch/sparc/include/asm/asi.h
@@ -0,0 +1,266 @@
+#ifndef _SPARC_ASI_H
+#define _SPARC_ASI_H
+
+/* asi.h:  Address Space Identifier values for the sparc.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
+ * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
+ */
+
+/* The first batch are for the sun4c. */
+
+#define ASI_NULL1           0x00
+#define ASI_NULL2           0x01
+
+/* sun4c and sun4 control registers and mmu/vac ops */
+#define ASI_CONTROL         0x02
+#define ASI_SEGMAP          0x03
+#define ASI_PTE             0x04
+#define ASI_HWFLUSHSEG      0x05
+#define ASI_HWFLUSHPAGE     0x06
+#define ASI_REGMAP          0x06
+#define ASI_HWFLUSHCONTEXT  0x07
+
+#define ASI_USERTXT         0x08
+#define ASI_KERNELTXT       0x09
+#define ASI_USERDATA        0x0a
+#define ASI_KERNELDATA      0x0b
+
+/* VAC Cache flushing on sun4c and sun4 */
+#define ASI_FLUSHSEG        0x0c
+#define ASI_FLUSHPG         0x0d
+#define ASI_FLUSHCTX        0x0e
+
+/* SPARCstation-5: only 6 bits are decoded. */
+/* wo = Write Only, rw = Read Write;        */
+/* ss = Single Size, as = All Sizes;        */
+#define ASI_M_RES00         0x00   /* Don't touch... */
+#define ASI_M_UNA01         0x01   /* Same here... */
+#define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
+#define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
+#ifndef CONFIG_SPARC_LEON
+#define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
+#else
+#define ASI_M_MMUREGS       0x19
+#endif /* CONFIG_SPARC_LEON */
+#define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
+#define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
+#define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
+#define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
+#define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
+#define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
+#define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
+#define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
+#define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
+#define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
+#define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
+
+/* The following cache flushing ASIs work only with the 'sta'
+ * instruction. Results are unpredictable for 'swap' and 'ldstuba',
+ * so don't do it.
+ */
+
+/* These ASI flushes affect external caches too. */
+#define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
+#define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
+#define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
+#define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
+#define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
+
+/* Block-copy operations are available only on certain V8 cpus. */
+#define ASI_M_BCOPY         0x17   /* Block copy */
+
+/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
+#define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
+#define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
+#define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
+#define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
+#define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
+
+/* Block-fill operations are available on certain V8 cpus */
+#define ASI_M_BFILL         0x1F
+
+/* This allows direct access to main memory, actually 0x20 to 0x2f are
+ * the available ASI's for physical ram pass-through, but I don't have
+ * any idea what the other ones do....
+ */
+
+#define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
+#define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
+#define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
+#define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
+#define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
+#define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
+#define ASI_M_SBUS         0x2E   /* Direct SBus access */
+#define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
+
+
+/* This is ROSS HyperSparc only. */
+#define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
+
+/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
+#define ASI_M_IC_FLCLEAR   0x36
+#define ASI_M_DC_FLCLEAR   0x37
+
+#define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Register rw, ss */
+
+#define ASI_M_VIKING_TMP1  0x40   /* Emulation temporary 1 on Viking */
+/* only available on SuperSparc I */
+/* #define ASI_M_VIKING_TMP2  0x41 */  /* Emulation temporary 2 on Viking */
+
+#define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
+
+/* V9 Architecture mandary ASIs. */
+#define ASI_N                   0x04 /* Nucleus                         */
+#define ASI_NL                  0x0c /* Nucleus, little endian          */
+#define ASI_AIUP                0x10 /* Primary, user                   */
+#define ASI_AIUS                0x11 /* Secondary, user                 */
+#define ASI_AIUPL               0x18 /* Primary, user, little endian    */
+#define ASI_AIUSL               0x19 /* Secondary, user, little endian  */
+#define ASI_P                   0x80 /* Primary, implicit               */
+#define ASI_S                   0x81 /* Secondary, implicit             */
+#define ASI_PNF                 0x82 /* Primary, no fault               */
+#define ASI_SNF                 0x83 /* Secondary, no fault             */
+#define ASI_PL                  0x88 /* Primary, implicit, l-endian     */
+#define ASI_SL                  0x89 /* Secondary, implicit, l-endian   */
+#define ASI_PNFL                0x8a /* Primary, no fault, l-endian     */
+#define ASI_SNFL                0x8b /* Secondary, no fault, l-endian   */
+
+/* SpitFire and later extended ASIs.  The "(III)" marker designates
+ * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
+ * Chip Multi Threading specific ASIs.  "(NG)" designates Niagara specific
+ * ASIs, "(4V)" designates SUN4V specific ASIs.
+ */
+#define ASI_PHYS_USE_EC         0x14 /* PADDR, E-cachable               */
+#define ASI_PHYS_BYPASS_EC_E    0x15 /* PADDR, E-bit                    */
+#define ASI_BLK_AIUP_4V         0x16 /* (4V) Prim, user, block ld/st    */
+#define ASI_BLK_AIUS_4V         0x17 /* (4V) Sec, user, block ld/st     */
+#define ASI_PHYS_USE_EC_L       0x1c /* PADDR, E-cachable, little endian*/
+#define ASI_PHYS_BYPASS_EC_E_L  0x1d /* PADDR, E-bit, little endian     */
+#define ASI_BLK_AIUP_L_4V       0x1e /* (4V) Prim, user, block, l-endian*/
+#define ASI_BLK_AIUS_L_4V       0x1f /* (4V) Sec, user, block, l-endian */
+#define ASI_SCRATCHPAD          0x20 /* (4V) Scratch Pad Registers      */
+#define ASI_MMU                 0x21 /* (4V) MMU Context Registers      */
+#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
+                                         * secondary, user
+                                         */
+#define ASI_NUCLEUS_QUAD_LDD    0x24 /* Cachable, qword load            */
+#define ASI_QUEUE               0x25 /* (4V) Interrupt Queue Registers  */
+#define ASI_QUAD_LDD_PHYS_4V    0x26 /* (4V) Physical, qword load       */
+#define ASI_NUCLEUS_QUAD_LDD_L  0x2c /* Cachable, qword load, l-endian  */
+#define ASI_QUAD_LDD_PHYS_L_4V  0x2e /* (4V) Phys, qword load, l-endian */
+#define ASI_PCACHE_DATA_STATUS  0x30 /* (III) PCache data stat RAM diag */
+#define ASI_PCACHE_DATA         0x31 /* (III) PCache data RAM diag      */
+#define ASI_PCACHE_TAG          0x32 /* (III) PCache tag RAM diag       */
+#define ASI_PCACHE_SNOOP_TAG    0x33 /* (III) PCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS       0x34 /* (III+) PADDR, qword load        */
+#define ASI_WCACHE_VALID_BITS   0x38 /* (III) WCache Valid Bits diag    */
+#define ASI_WCACHE_DATA         0x39 /* (III) WCache data RAM diag      */
+#define ASI_WCACHE_TAG          0x3a /* (III) WCache tag RAM diag       */
+#define ASI_WCACHE_SNOOP_TAG    0x3b /* (III) WCache snoop tag RAM diag */
+#define ASI_QUAD_LDD_PHYS_L     0x3c /* (III+) PADDR, qw-load, l-endian */
+#define ASI_SRAM_FAST_INIT      0x40 /* (III+) Fast SRAM init           */
+#define ASI_CORE_AVAILABLE      0x41 /* (CMT) LP Available              */
+#define ASI_CORE_ENABLE_STAT    0x41 /* (CMT) LP Enable Status          */
+#define ASI_CORE_ENABLE         0x41 /* (CMT) LP Enable RW              */
+#define ASI_XIR_STEERING        0x41 /* (CMT) XIR Steering RW           */
+#define ASI_CORE_RUNNING_RW     0x41 /* (CMT) LP Running RW             */
+#define ASI_CORE_RUNNING_W1S    0x41 /* (CMT) LP Running Write-One Set  */
+#define ASI_CORE_RUNNING_W1C    0x41 /* (CMT) LP Running Write-One Clr  */
+#define ASI_CORE_RUNNING_STAT   0x41 /* (CMT) LP Running Status         */
+#define ASI_CMT_ERROR_STEERING  0x41 /* (CMT) Error Steering RW         */
+#define ASI_DCACHE_INVALIDATE   0x42 /* (III) DCache Invalidate diag    */
+#define ASI_DCACHE_UTAG         0x43 /* (III) DCache uTag diag          */
+#define ASI_DCACHE_SNOOP_TAG    0x44 /* (III) DCache snoop tag RAM diag */
+#define ASI_LSU_CONTROL         0x45 /* Load-store control unit         */
+#define ASI_DCU_CONTROL_REG     0x45 /* (III) DCache Unit Control reg   */
+#define ASI_DCACHE_DATA         0x46 /* DCache data-ram diag access     */
+#define ASI_DCACHE_TAG          0x47 /* Dcache tag/valid ram diag access*/
+#define ASI_INTR_DISPATCH_STAT  0x48 /* IRQ vector dispatch status      */
+#define ASI_INTR_RECEIVE        0x49 /* IRQ vector receive status       */
+#define ASI_UPA_CONFIG          0x4a /* UPA config space                */
+#define ASI_JBUS_CONFIG         0x4a /* (IIIi) JBUS Config Register     */
+#define ASI_SAFARI_CONFIG       0x4a /* (III) Safari Config Register    */
+#define ASI_SAFARI_ADDRESS      0x4a /* (III) Safari Address Register   */
+#define ASI_ESTATE_ERROR_EN     0x4b /* E-cache error enable space      */
+#define ASI_AFSR                0x4c /* Async fault status register     */
+#define ASI_AFAR                0x4d /* Async fault address register    */
+#define ASI_EC_TAG_DATA         0x4e /* E-cache tag/valid ram diag acc  */
+#define ASI_IMMU                0x50 /* Insn-MMU main register space    */
+#define ASI_IMMU_TSB_8KB_PTR    0x51 /* Insn-MMU 8KB TSB pointer reg    */
+#define ASI_IMMU_TSB_64KB_PTR   0x52 /* Insn-MMU 64KB TSB pointer reg   */
+#define ASI_ITLB_DATA_IN        0x54 /* Insn-MMU TLB data in reg        */
+#define ASI_ITLB_DATA_ACCESS    0x55 /* Insn-MMU TLB data access reg    */
+#define ASI_ITLB_TAG_READ       0x56 /* Insn-MMU TLB tag read reg       */
+#define ASI_IMMU_DEMAP          0x57 /* Insn-MMU TLB demap              */
+#define ASI_DMMU                0x58 /* Data-MMU main register space    */
+#define ASI_DMMU_TSB_8KB_PTR    0x59 /* Data-MMU 8KB TSB pointer reg    */
+#define ASI_DMMU_TSB_64KB_PTR   0x5a /* Data-MMU 16KB TSB pointer reg   */
+#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
+#define ASI_DTLB_DATA_IN        0x5c /* Data-MMU TLB data in reg        */
+#define ASI_DTLB_DATA_ACCESS    0x5d /* Data-MMU TLB data access reg    */
+#define ASI_DTLB_TAG_READ       0x5e /* Data-MMU TLB tag read reg       */
+#define ASI_DMMU_DEMAP          0x5f /* Data-MMU TLB demap              */
+#define ASI_IIU_INST_TRAP       0x60 /* (III) Instruction Breakpoint    */
+#define ASI_INTR_ID             0x63 /* (CMT) Interrupt ID register     */
+#define ASI_CORE_ID             0x63 /* (CMT) LP ID register            */
+#define ASI_CESR_ID             0x63 /* (CMT) CESR ID register          */
+#define ASI_IC_INSTR            0x66 /* Insn cache instrucion ram diag  */
+#define ASI_IC_TAG              0x67 /* Insn cache tag/valid ram diag   */
+#define ASI_IC_STAG             0x68 /* (III) Insn cache snoop tag ram  */
+#define ASI_IC_PRE_DECODE       0x6e /* Insn cache pre-decode ram diag  */
+#define ASI_IC_NEXT_FIELD       0x6f /* Insn cache next-field ram diag  */
+#define ASI_BRPRED_ARRAY        0x6f /* (III) Branch Prediction RAM diag*/
+#define ASI_BLK_AIUP            0x70 /* Primary, user, block load/store */
+#define ASI_BLK_AIUS            0x71 /* Secondary, user, block ld/st    */
+#define ASI_MCU_CTRL_REG        0x72 /* (III) Memory controller regs    */
+#define ASI_EC_DATA             0x74 /* (III) E-cache data staging reg  */
+#define ASI_EC_CTRL             0x75 /* (III) E-cache control reg       */
+#define ASI_EC_W                0x76 /* E-cache diag write access       */
+#define ASI_UDB_ERROR_W         0x77 /* External UDB error regs W       */
+#define ASI_UDB_CONTROL_W       0x77 /* External UDB control regs W     */
+#define ASI_INTR_W              0x77 /* IRQ vector dispatch write       */
+#define ASI_INTR_DATAN_W        0x77 /* (III) Out irq vector data reg N */
+#define ASI_INTR_DISPATCH_W     0x77 /* (III) Interrupt vector dispatch */
+#define ASI_BLK_AIUPL           0x78 /* Primary, user, little, blk ld/st*/
+#define ASI_BLK_AIUSL           0x79 /* Secondary, user, little, blk ld/st*/
+#define ASI_EC_R                0x7e /* E-cache diag read access        */
+#define ASI_UDBH_ERROR_R        0x7f /* External UDB error regs rd hi   */
+#define ASI_UDBL_ERROR_R        0x7f /* External UDB error regs rd low  */
+#define ASI_UDBH_CONTROL_R      0x7f /* External UDB control regs rd hi */
+#define ASI_UDBL_CONTROL_R      0x7f /* External UDB control regs rd low*/
+#define ASI_INTR_R              0x7f /* IRQ vector dispatch read        */
+#define ASI_INTR_DATAN_R        0x7f /* (III) In irq vector data reg N  */
+#define ASI_PST8_P              0xc0 /* Primary, 8 8-bit, partial       */
+#define ASI_PST8_S              0xc1 /* Secondary, 8 8-bit, partial     */
+#define ASI_PST16_P             0xc2 /* Primary, 4 16-bit, partial      */
+#define ASI_PST16_S             0xc3 /* Secondary, 4 16-bit, partial    */
+#define ASI_PST32_P             0xc4 /* Primary, 2 32-bit, partial      */
+#define ASI_PST32_S             0xc5 /* Secondary, 2 32-bit, partial    */
+#define ASI_PST8_PL             0xc8 /* Primary, 8 8-bit, partial, L    */
+#define ASI_PST8_SL             0xc9 /* Secondary, 8 8-bit, partial, L  */
+#define ASI_PST16_PL            0xca /* Primary, 4 16-bit, partial, L   */
+#define ASI_PST16_SL            0xcb /* Secondary, 4 16-bit, partial, L */
+#define ASI_PST32_PL            0xcc /* Primary, 2 32-bit, partial, L   */
+#define ASI_PST32_SL            0xcd /* Secondary, 2 32-bit, partial, L */
+#define ASI_FL8_P               0xd0 /* Primary, 1 8-bit, fpu ld/st     */
+#define ASI_FL8_S               0xd1 /* Secondary, 1 8-bit, fpu ld/st   */
+#define ASI_FL16_P              0xd2 /* Primary, 1 16-bit, fpu ld/st    */
+#define ASI_FL16_S              0xd3 /* Secondary, 1 16-bit, fpu ld/st  */
+#define ASI_FL8_PL              0xd8 /* Primary, 1 8-bit, fpu ld/st, L  */
+#define ASI_FL8_SL              0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
+#define ASI_FL16_PL             0xda /* Primary, 1 16-bit, fpu ld/st, L */
+#define ASI_FL16_SL             0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
+#define ASI_BLK_COMMIT_P        0xe0 /* Primary, blk store commit       */
+#define ASI_BLK_COMMIT_S        0xe1 /* Secondary, blk store commit     */
+#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
+                                      * primary, implicit
+                                      */
+#define ASI_BLK_P               0xf0 /* Primary, blk ld/st              */
+#define ASI_BLK_S               0xf1 /* Secondary, blk ld/st            */
+#define ASI_BLK_PL              0xf8 /* Primary, blk ld/st, little      */
+#define ASI_BLK_SL              0xf9 /* Secondary, blk ld/st, little    */
+
+#endif /* _SPARC_ASI_H */
diff --git a/arch/sparc/include/asm/auxvec.h b/arch/sparc/include/asm/auxvec.h
new file mode 100644
index 00000000000..ad6f360261f
--- /dev/null
+++ b/arch/sparc/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMSPARC_AUXVEC_H
+#define __ASMSPARC_AUXVEC_H
+
+#endif /* !(__ASMSPARC_AUXVEC_H) */
diff --git a/arch/sparc/include/asm/bitsperlong.h b/arch/sparc/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..40dcaa3aaa5
--- /dev/null
+++ b/arch/sparc/include/asm/bitsperlong.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_ALPHA_BITSPERLONG_H
+#define __ASM_ALPHA_BITSPERLONG_H
+
+#if defined(__sparc__) && defined(__arch64__)
+#define __BITS_PER_LONG 64
+#else
+#define __BITS_PER_LONG 32
+#endif
+
+#include <asm-generic/bitsperlong.h>
+
+#endif /* __ASM_ALPHA_BITSPERLONG_H */
+
diff --git a/arch/sparc/include/asm/btfixup.h b/arch/sparc/include/asm/btfixup.h
new file mode 100644
index 00000000000..797722cf69f
--- /dev/null
+++ b/arch/sparc/include/asm/btfixup.h
@@ -0,0 +1,208 @@
+/*
+ *  asm/btfixup.h:    Macros for boot time linking.
+ *
+ *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+ 
+#ifndef _SPARC_BTFIXUP_H
+#define _SPARC_BTFIXUP_H
+
+#include <linux/init.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef MODULE
+extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
+extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
+
+#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
+#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
+#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
+#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
+#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
+
+#else
+
+#define BTFIXUP_SIMM13(__name) ___sf_##__name()
+#define BTFIXUP_HALF(__name) ___af_##__name()
+#define BTFIXUP_SETHI(__name) ___hf_##__name()
+#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
+/* This must be written in assembly and present in a sethi */
+#define BTFIXUP_BLACKBOX(__name) ___b_##__name
+#endif /* MODULE */
+
+/* Fixup call xx */
+
+#define BTFIXUPDEF_CALL(__type, __name, __args...)                                      \
+        extern __type ___f_##__name(__args);                                            \
+        extern unsigned ___fs_##__name[3];
+#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...)                                \
+        extern __type ___f_##__name(__args) __attribute_const__;                        \
+        extern unsigned ___fs_##__name[3];
+#define BTFIXUP_CALL(__name) ___f_##__name
+
+#define BTFIXUPDEF_BLACKBOX(__name)                                                     \
+        extern unsigned ___bs_##__name[2];
+
+/* Put bottom 13bits into some register variable */
+
+#define BTFIXUPDEF_SIMM13(__name)                                                       \
+        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
+        extern unsigned ___ss_##__name[2];                                              \
+        static inline unsigned int ___sf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret));                  \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_SIMM13_INIT(__name,__val)                                            \
+        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
+        extern unsigned ___ss_##__name[2];                                              \
+        static inline unsigned int ___sf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+                return ret;                                                             \
+        }
+
+/* Put either bottom 13 bits, or upper 22 bits into some register variable
+ * (depending on the value, this will lead into sethi FIX, reg; or
+ * mov FIX, reg; )
+ */
+
+#define BTFIXUPDEF_HALF(__name)                                                         \
+        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
+        extern unsigned ___as_##__name[2];                                              \
+        static inline unsigned int ___af_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret));                  \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_HALF_INIT(__name,__val)                                              \
+        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
+        extern unsigned ___as_##__name[2];                                              \
+        static inline unsigned int ___af_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
+                return ret;                                                             \
+        }
+
+/* Put upper 22 bits into some register variable */
+
+#define BTFIXUPDEF_SETHI(__name)                                                        \
+        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
+        extern unsigned ___hs_##__name[2];                                              \
+        static inline unsigned int ___hf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret));               \
+                return ret;                                                             \
+        }
+#define BTFIXUPDEF_SETHI_INIT(__name,__val)                                             \
+        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
+        extern unsigned ___hs_##__name[2];                                              \
+        static inline unsigned int ___hf_##__name(void) {                               \
+                unsigned int ret;                                                       \
+                __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" :         \
+                         "=r"(ret));                                                    \
+                return ret;                                                             \
+        }
+
+/* Put a full 32bit integer into some register variable */
+
+#define BTFIXUPDEF_INT(__name)                                                          \
+        extern unsigned char ___i_##__name;                                             \
+        extern unsigned ___is_##__name[2];
+
+#define BTFIXUPCALL_NORM        0x00000000                      /* Always call */
+#define BTFIXUPCALL_NOP         0x01000000                      /* Possibly optimize to nop */
+#define BTFIXUPCALL_RETINT(i)   (0x90102000|((i) & 0x1fff))     /* Possibly optimize to mov i, %o0 */
+#define BTFIXUPCALL_ORINT(i)    (0x90122000|((i) & 0x1fff))     /* Possibly optimize to or %o0, i, %o0 */
+#define BTFIXUPCALL_RETO0       0x01000000                      /* Return first parameter, actually a nop */
+#define BTFIXUPCALL_ANDNINT(i)  (0x902a2000|((i) & 0x1fff))     /* Possibly optimize to andn %o0, i, %o0 */
+#define BTFIXUPCALL_SWAPO0O1    0xd27a0000                      /* Possibly optimize to swap [%o0],%o1 */
+#define BTFIXUPCALL_SWAPO0G0    0xc07a0000                      /* Possibly optimize to swap [%o0],%g0 */
+#define BTFIXUPCALL_SWAPG1G2    0xc4784000                      /* Possibly optimize to swap [%g1],%g2 */
+#define BTFIXUPCALL_STG0O0      0xc0220000                      /* Possibly optimize to st %g0,[%o0] */
+#define BTFIXUPCALL_STO1O0      0xd2220000                      /* Possibly optimize to st %o1,[%o0] */
+
+#define BTFIXUPSET_CALL(__name, __addr, __insn)                                         \
+        do {                                                                            \
+                ___fs_##__name[0] |= 1;                                                 \
+                ___fs_##__name[1] = (unsigned long)__addr;                              \
+                ___fs_##__name[2] = __insn;                                             \
+        } while (0)
+        
+#define BTFIXUPSET_BLACKBOX(__name, __func)                                             \
+        do {                                                                            \
+                ___bs_##__name[0] |= 1;                                                 \
+                ___bs_##__name[1] = (unsigned long)__func;                              \
+        } while (0)
+        
+#define BTFIXUPCOPY_CALL(__name, __from)                                                \
+        do {                                                                            \
+                ___fs_##__name[0] |= 1;                                                 \
+                ___fs_##__name[1] = ___fs_##__from[1];                                  \
+                ___fs_##__name[2] = ___fs_##__from[2];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_SIMM13(__name, __val)                                                \
+        do {                                                                            \
+                ___ss_##__name[0] |= 1;                                                 \
+                ___ss_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_SIMM13(__name, __from)                                              \
+        do {                                                                            \
+                ___ss_##__name[0] |= 1;                                                 \
+                ___ss_##__name[1] = ___ss_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_HALF(__name, __val)                                                  \
+        do {                                                                            \
+                ___as_##__name[0] |= 1;                                                 \
+                ___as_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_HALF(__name, __from)                                                \
+        do {                                                                            \
+                ___as_##__name[0] |= 1;                                                 \
+                ___as_##__name[1] = ___as_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_SETHI(__name, __val)                                                 \
+        do {                                                                            \
+                ___hs_##__name[0] |= 1;                                                 \
+                ___hs_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_SETHI(__name, __from)                                               \
+        do {                                                                            \
+                ___hs_##__name[0] |= 1;                                                 \
+                ___hs_##__name[1] = ___hs_##__from[1];                                  \
+        } while (0)
+                
+#define BTFIXUPSET_INT(__name, __val)                                                   \
+        do {                                                                            \
+                ___is_##__name[0] |= 1;                                                 \
+                ___is_##__name[1] = (unsigned)__val;                                    \
+        } while (0)
+        
+#define BTFIXUPCOPY_INT(__name, __from)                                                 \
+        do {                                                                            \
+                ___is_##__name[0] |= 1;                                                 \
+                ___is_##__name[1] = ___is_##__from[1];                                  \
+        } while (0)
+        
+#define BTFIXUPVAL_CALL(__name)                                                         \
+        ((unsigned long)___fs_##__name[1])
+        
+extern void btfixup(void);
+
+#else /* __ASSEMBLY__ */
+
+#define BTFIXUP_SETHI(__name)                   %hi(___h_ ## __name)
+#define BTFIXUP_SETHI_INIT(__name,__val)        %hi(___h_ ## __name ## __btset_ ## __val)
+
+#endif /* __ASSEMBLY__ */
+        
+#endif /* !(_SPARC_BTFIXUP_H) */
diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h
new file mode 100644
index 00000000000..ccc1b6b7de6
--- /dev/null
+++ b/arch/sparc/include/asm/byteorder.h
@@ -0,0 +1,6 @@
+#ifndef _SPARC_BYTEORDER_H
+#define _SPARC_BYTEORDER_H
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _SPARC_BYTEORDER_H */
diff --git a/arch/sparc/include/asm/cmt.h b/arch/sparc/include/asm/cmt.h
new file mode 100644
index 00000000000..870db592857
--- /dev/null
+++ b/arch/sparc/include/asm/cmt.h
@@ -0,0 +1,59 @@
+#ifndef _SPARC64_CMT_H
+#define _SPARC64_CMT_H
+
+/* cmt.h: Chip Multi-Threading register definitions
+ *
+ * Copyright (C) 2004 David S. Miller (davem@redhat.com)
+ */
+
+/* ASI_CORE_ID - private */
+#define LP_ID           0x0000000000000010UL
+#define  LP_ID_MAX      0x00000000003f0000UL
+#define  LP_ID_ID       0x000000000000003fUL
+
+/* ASI_INTR_ID - private */
+#define LP_INTR_ID      0x0000000000000000UL
+#define  LP_INTR_ID_ID  0x00000000000003ffUL
+
+/* ASI_CESR_ID - private */
+#define CESR_ID         0x0000000000000040UL
+#define  CESR_ID_ID     0x00000000000000ffUL
+
+/* ASI_CORE_AVAILABLE - shared */
+#define LP_AVAIL        0x0000000000000000UL
+#define  LP_AVAIL_1     0x0000000000000002UL
+#define  LP_AVAIL_0     0x0000000000000001UL
+
+/* ASI_CORE_ENABLE_STATUS - shared */
+#define LP_ENAB_STAT    0x0000000000000010UL
+#define  LP_ENAB_STAT_1 0x0000000000000002UL
+#define  LP_ENAB_STAT_0 0x0000000000000001UL
+
+/* ASI_CORE_ENABLE - shared */
+#define LP_ENAB         0x0000000000000020UL
+#define  LP_ENAB_1      0x0000000000000002UL
+#define  LP_ENAB_0      0x0000000000000001UL
+
+/* ASI_CORE_RUNNING - shared */
+#define LP_RUNNING_RW   0x0000000000000050UL
+#define LP_RUNNING_W1S  0x0000000000000060UL
+#define LP_RUNNING_W1C  0x0000000000000068UL
+#define  LP_RUNNING_1   0x0000000000000002UL
+#define  LP_RUNNING_0   0x0000000000000001UL
+
+/* ASI_CORE_RUNNING_STAT - shared */
+#define LP_RUN_STAT     0x0000000000000058UL
+#define  LP_RUN_STAT_1  0x0000000000000002UL
+#define  LP_RUN_STAT_0  0x0000000000000001UL
+
+/* ASI_XIR_STEERING - shared */
+#define LP_XIR_STEER    0x0000000000000030UL
+#define  LP_XIR_STEER_1 0x0000000000000002UL
+#define  LP_XIR_STEER_0 0x0000000000000001UL
+
+/* ASI_CMT_ERROR_STEERING - shared */
+#define CMT_ER_STEER    0x0000000000000040UL
+#define  CMT_ER_STEER_1 0x0000000000000002UL
+#define  CMT_ER_STEER_0 0x0000000000000001UL
+
+#endif /* _SPARC64_CMT_H */
diff --git a/arch/sparc/include/asm/cypress.h b/arch/sparc/include/asm/cypress.h
new file mode 100644
index 00000000000..95e9772ea39
--- /dev/null
+++ b/arch/sparc/include/asm/cypress.h
@@ -0,0 +1,79 @@
+/*
+ * cypress.h: Cypress module specific definitions and defines.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_CYPRESS_H
+#define _SPARC_CYPRESS_H
+
+/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
+
+/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
+ *
+ * ---------------------------------------------------------------
+ * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
+ * ---------------------------------------------------------------
+ *  31    24 23-22 21-20 19 18-15 14 13  12 11 10  9  8 7-2  1  0
+ *
+ * MCA: MultiChip Access -- Used for configuration of multiple
+ *      CY7C604/605 cache units.
+ * MCM: MultiChip Mask -- Again, for multiple cache unit config.
+ * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
+ * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
+ * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
+ * C: Cacheable -- Indicates whether accesses are cacheable while
+ *    the MMU is off.  0=no 1=yes
+ * MR: MemoryReflection -- Indicates whether the bus attached to the
+ *     MBus supports memory reflection. 0=no 1=yes (605 only)
+ * CM: CacheMode -- Indicates whether the cache is operating in write
+ *     through or copy-back mode. 0=write-through 1=copy-back
+ * CL: CacheLock -- Indicates if the entire cache is locked or not.
+ *     0=not-locked 1=locked  (604 only)
+ * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
+ * NF: NoFault -- Do faults generate traps? 0=yes 1=no
+ * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
+ */
+
+#define CYPRESS_MCA       0x00c00000
+#define CYPRESS_MCM       0x00300000
+#define CYPRESS_MVALID    0x00080000
+#define CYPRESS_MIDMASK   0x00078000   /* Only on 605 */
+#define CYPRESS_BMODE     0x00004000
+#define CYPRESS_ACENABLE  0x00002000
+#define CYPRESS_MRFLCT    0x00000800   /* Only on 605 */
+#define CYPRESS_CMODE     0x00000400
+#define CYPRESS_CLOCK     0x00000200   /* Only on 604 */
+#define CYPRESS_CENABLE   0x00000100
+#define CYPRESS_NFAULT    0x00000002
+#define CYPRESS_MENABLE   0x00000001
+
+static inline void cypress_flush_page(unsigned long page)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (page), "i" (ASI_M_FLUSH_PAGE));
+}
+
+static inline void cypress_flush_segment(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_SEG));
+}
+
+static inline void cypress_flush_region(unsigned long addr)
+{
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
+                             "r" (addr), "i" (ASI_M_FLUSH_REGION));
+}
+
+static inline void cypress_flush_context(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
+                             "i" (ASI_M_FLUSH_CTX));
+}
+
+/* XXX Displacement flushes for buggy chips and initial testing
+ * XXX go here.
+ */
+
+#endif /* !(_SPARC_CYPRESS_H) */
diff --git a/arch/sparc/include/asm/display7seg.h b/arch/sparc/include/asm/display7seg.h
new file mode 100644
index 00000000000..86d4a901df2
--- /dev/null
+++ b/arch/sparc/include/asm/display7seg.h
@@ -0,0 +1,79 @@
+/*
+ *
+ * display7seg - Driver interface for the 7-segment display
+ * present on Sun Microsystems CP1400 and CP1500
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef __display7seg_h__
+#define __display7seg_h__
+
+#define D7S_IOC 'p'
+
+#define D7SIOCRD _IOR(D7S_IOC, 0x45, int)       /* Read device state    */
+#define D7SIOCWR _IOW(D7S_IOC, 0x46, int)       /* Write device state   */
+#define D7SIOCTM _IO (D7S_IOC, 0x47)            /* Translate mode (FLIP)*/
+
+/*
+ * ioctl flag definitions
+ *
+ * POINT        - Toggle decimal point  (0=absent 1=present)
+ * ALARM        - Toggle alarm LED              (0=green  1=red)
+ * FLIP         - Toggle inverted mode  (0=normal 1=flipped)
+ * bits 0-4     - Character displayed   (see definitions below)
+ *
+ * Display segments are defined as follows,
+ * subject to D7S_FLIP register state:
+ *
+ *    a
+ *   ---
+ * f|   |b
+ *   -g-
+ * e|   |c
+ *   ---
+ *    d
+ */
+
+#define D7S_POINT       (1 << 7)        /* Decimal point*/
+#define D7S_ALARM       (1 << 6)        /* Alarm LED    */
+#define D7S_FLIP        (1 << 5)        /* Flip display */
+
+#define D7S_0           0x00            /* Numerals 0-9 */
+#define D7S_1           0x01
+#define D7S_2           0x02
+#define D7S_3           0x03
+#define D7S_4           0x04
+#define D7S_5           0x05
+#define D7S_6           0x06
+#define D7S_7           0x07
+#define D7S_8           0x08
+#define D7S_9           0x09
+#define D7S_A           0x0A            /* Letters A-F, H, L, P */
+#define D7S_B           0x0B
+#define D7S_C           0x0C
+#define D7S_D           0x0D
+#define D7S_E           0x0E
+#define D7S_F           0x0F
+#define D7S_H           0x10
+#define D7S_E2          0x11
+#define D7S_L           0x12
+#define D7S_P           0x13
+#define D7S_SEGA        0x14            /* Individual segments */
+#define D7S_SEGB        0x15
+#define D7S_SEGC        0x16
+#define D7S_SEGD        0x17
+#define D7S_SEGE        0x18
+#define D7S_SEGF        0x19
+#define D7S_SEGG        0x1A
+#define D7S_SEGABFG 0x1B                /* Segment groupings */
+#define D7S_SEGCDEG     0x1C
+#define D7S_SEGBCEF 0x1D
+#define D7S_SEGADG      0x1E
+#define D7S_BLANK       0x1F            /* Clear all segments */
+
+#define D7S_MIN_VAL     0x0
+#define D7S_MAX_VAL     0x1F
+
+#endif /* ifndef __display7seg_h__ */
diff --git a/arch/sparc/include/asm/envctrl.h b/arch/sparc/include/asm/envctrl.h
new file mode 100644
index 00000000000..624fa7e2da8
--- /dev/null
+++ b/arch/sparc/include/asm/envctrl.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * envctrl.h: Definitions for access to the i2c environment
+ *            monitoring on Ultrasparc systems.
+ *
+ * Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
+ * Copyright (C) 2000  Vinh Truong  (vinh.truong@eng.sun.com)
+ * VT - Add all ioctl commands and environment status definitions
+ * VT - Add application note
+ */
+#ifndef _SPARC64_ENVCTRL_H
+#define _SPARC64_ENVCTRL_H 1
+
+#include <linux/ioctl.h>
+
+/* Application note:
+ *
+ * The driver supports 4 operations: open(), close(), ioctl(), read()
+ * The device name is /dev/envctrl.
+ * Below is sample usage:
+ *
+ *      fd = open("/dev/envtrl", O_RDONLY);
+ *      if (ioctl(fd, ENVCTRL_READ_SHUTDOWN_TEMPERATURE, 0) < 0)
+ *              printf("error\n");
+ *      ret = read(fd, buf, 10);
+ *      close(fd);
+ *
+ * Notice in the case of cpu voltage and temperature, the default is
+ * cpu0.  If we need to know the info of cpu1, cpu2, cpu3, we need to
+ * pass in cpu number in ioctl() last parameter.  For example, to
+ * get the voltage of cpu2:
+ *
+ *      ioctlbuf[0] = 2;
+ *      if (ioctl(fd, ENVCTRL_READ_CPU_VOLTAGE, ioctlbuf) < 0)
+ *              printf("error\n");
+ *      ret = read(fd, buf, 10);
+ *
+ * All the return values are in ascii.  So check read return value
+ * and do appropriate conversions in your application.
+ */
+
+/* IOCTL commands */
+
+/* Note: these commands reflect possible monitor features.
+ * Some boards choose to support some of the features only.
+ */
+#define ENVCTRL_RD_CPU_TEMPERATURE      _IOR('p', 0x40, int)
+#define ENVCTRL_RD_CPU_VOLTAGE          _IOR('p', 0x41, int)
+#define ENVCTRL_RD_FAN_STATUS           _IOR('p', 0x42, int)
+#define ENVCTRL_RD_WARNING_TEMPERATURE  _IOR('p', 0x43, int)
+#define ENVCTRL_RD_SHUTDOWN_TEMPERATURE _IOR('p', 0x44, int)
+#define ENVCTRL_RD_VOLTAGE_STATUS       _IOR('p', 0x45, int)
+#define ENVCTRL_RD_SCSI_TEMPERATURE     _IOR('p', 0x46, int)
+#define ENVCTRL_RD_ETHERNET_TEMPERATURE _IOR('p', 0x47, int)
+#define ENVCTRL_RD_MTHRBD_TEMPERATURE   _IOR('p', 0x48, int)
+
+#define ENVCTRL_RD_GLOBALADDRESS        _IOR('p', 0x49, int)
+
+/* Read return values for a voltage status request. */
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_GOOD        0x01
+#define ENVCTRL_VOLTAGE_BAD                     0x02
+#define ENVCTRL_POWERSUPPLY_BAD                 0x03
+#define ENVCTRL_VOLTAGE_POWERSUPPLY_BAD         0x04
+
+/* Read return values for a fan status request.
+ * A failure match means either the fan fails or
+ * the fan is not connected.  Some boards have optional
+ * connectors to connect extra fans.
+ *
+ * There are maximum 8 monitor fans.  Some are cpu fans
+ * some are system fans.  The mask below only indicates
+ * fan by order number.
+ * Below is a sample application:
+ *
+ *      if (ioctl(fd, ENVCTRL_READ_FAN_STATUS, 0) < 0) {
+ *              printf("ioctl fan failed\n");
+ *      }
+ *      if (read(fd, rslt, 1) <= 0) {
+ *              printf("error or fan not monitored\n");
+ *      } else {
+ *              if (rslt[0] == ENVCTRL_ALL_FANS_GOOD) {
+ *                      printf("all fans good\n");
+ *      } else if (rslt[0] == ENVCTRL_ALL_FANS_BAD) {
+ *              printf("all fans bad\n");
+ *      } else {
+ *              if (rslt[0] & ENVCTRL_FAN0_FAILURE_MASK) {
+ *                      printf("fan 0 failed or not connected\n");
+ *      }
+ *      ......
+ */
+
+#define ENVCTRL_ALL_FANS_GOOD                   0x00
+#define ENVCTRL_FAN0_FAILURE_MASK               0x01
+#define ENVCTRL_FAN1_FAILURE_MASK               0x02
+#define ENVCTRL_FAN2_FAILURE_MASK               0x04
+#define ENVCTRL_FAN3_FAILURE_MASK               0x08
+#define ENVCTRL_FAN4_FAILURE_MASK               0x10
+#define ENVCTRL_FAN5_FAILURE_MASK               0x20
+#define ENVCTRL_FAN6_FAILURE_MASK               0x40
+#define ENVCTRL_FAN7_FAILURE_MASK               0x80
+#define ENVCTRL_ALL_FANS_BAD                    0xFF
+
+#endif /* !(_SPARC64_ENVCTRL_H) */
diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h
new file mode 100644
index 00000000000..c351aba997b
--- /dev/null
+++ b/arch/sparc/include/asm/errno.h
@@ -0,0 +1,117 @@
+#ifndef _SPARC_ERRNO_H
+#define _SPARC_ERRNO_H
+
+/* These match the SunOS error numbering scheme. */
+
+#include <asm-generic/errno-base.h>
+
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EINPROGRESS     36      /* Operation now in progress */
+#define EALREADY        37      /* Operation already in progress */
+#define ENOTSOCK        38      /* Socket operation on non-socket */
+#define EDESTADDRREQ    39      /* Destination address required */
+#define EMSGSIZE        40      /* Message too long */
+#define EPROTOTYPE      41      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     42      /* Protocol not available */
+#define EPROTONOSUPPORT 43      /* Protocol not supported */
+#define ESOCKTNOSUPPORT 44      /* Socket type not supported */
+#define EOPNOTSUPP      45      /* Op not supported on transport endpoint */
+#define EPFNOSUPPORT    46      /* Protocol family not supported */
+#define EAFNOSUPPORT    47      /* Address family not supported by protocol */
+#define EADDRINUSE      48      /* Address already in use */
+#define EADDRNOTAVAIL   49      /* Cannot assign requested address */
+#define ENETDOWN        50      /* Network is down */
+#define ENETUNREACH     51      /* Network is unreachable */
+#define ENETRESET       52      /* Net dropped connection because of reset */
+#define ECONNABORTED    53      /* Software caused connection abort */
+#define ECONNRESET      54      /* Connection reset by peer */
+#define ENOBUFS         55      /* No buffer space available */
+#define EISCONN         56      /* Transport endpoint is already connected */
+#define ENOTCONN        57      /* Transport endpoint is not connected */
+#define ESHUTDOWN       58      /* No send after transport endpoint shutdown */
+#define ETOOMANYREFS    59      /* Too many references: cannot splice */
+#define ETIMEDOUT       60      /* Connection timed out */
+#define ECONNREFUSED    61      /* Connection refused */
+#define ELOOP           62      /* Too many symbolic links encountered */
+#define ENAMETOOLONG    63      /* File name too long */
+#define EHOSTDOWN       64      /* Host is down */
+#define EHOSTUNREACH    65      /* No route to host */
+#define ENOTEMPTY       66      /* Directory not empty */
+#define EPROCLIM        67      /* SUNOS: Too many processes */
+#define EUSERS          68      /* Too many users */
+#define EDQUOT          69      /* Quota exceeded */
+#define ESTALE          70      /* Stale NFS file handle */
+#define EREMOTE         71      /* Object is remote */
+#define ENOSTR          72      /* Device not a stream */
+#define ETIME           73      /* Timer expired */
+#define ENOSR           74      /* Out of streams resources */
+#define ENOMSG          75      /* No message of desired type */
+#define EBADMSG         76      /* Not a data message */
+#define EIDRM           77      /* Identifier removed */
+#define EDEADLK         78      /* Resource deadlock would occur */
+#define ENOLCK          79      /* No record locks available */
+#define ENONET          80      /* Machine is not on the network */
+#define ERREMOTE        81      /* SunOS: Too many lvls of remote in path */
+#define ENOLINK         82      /* Link has been severed */
+#define EADV            83      /* Advertise error */
+#define ESRMNT          84      /* Srmount error */
+#define ECOMM           85      /* Communication error on send */
+#define EPROTO          86      /* Protocol error */
+#define EMULTIHOP       87      /* Multihop attempted */
+#define EDOTDOT         88      /* RFS specific error */
+#define EREMCHG         89      /* Remote address changed */
+#define ENOSYS          90      /* Function not implemented */
+
+/* The rest have no SunOS equivalent. */
+#define ESTRPIPE        91      /* Streams pipe error */
+#define EOVERFLOW       92      /* Value too large for defined data type */
+#define EBADFD          93      /* File descriptor in bad state */
+#define ECHRNG          94      /* Channel number out of range */
+#define EL2NSYNC        95      /* Level 2 not synchronized */
+#define EL3HLT          96      /* Level 3 halted */
+#define EL3RST          97      /* Level 3 reset */
+#define ELNRNG          98      /* Link number out of range */
+#define EUNATCH         99      /* Protocol driver not attached */
+#define ENOCSI          100     /* No CSI structure available */
+#define EL2HLT          101     /* Level 2 halted */
+#define EBADE           102     /* Invalid exchange */
+#define EBADR           103     /* Invalid request descriptor */
+#define EXFULL          104     /* Exchange full */
+#define ENOANO          105     /* No anode */
+#define EBADRQC         106     /* Invalid request code */
+#define EBADSLT         107     /* Invalid slot */
+#define EDEADLOCK       108     /* File locking deadlock error */
+#define EBFONT          109     /* Bad font file format */
+#define ELIBEXEC        110     /* Cannot exec a shared library directly */
+#define ENODATA         111     /* No data available */
+#define ELIBBAD         112     /* Accessing a corrupted shared library */
+#define ENOPKG          113     /* Package not installed */
+#define ELIBACC         114     /* Can not access a needed shared library */
+#define ENOTUNIQ        115     /* Name not unique on network */
+#define ERESTART        116     /* Interrupted syscall should be restarted */
+#define EUCLEAN         117     /* Structure needs cleaning */
+#define ENOTNAM         118     /* Not a XENIX named type file */
+#define ENAVAIL         119     /* No XENIX semaphores available */
+#define EISNAM          120     /* Is a named type file */
+#define EREMOTEIO       121     /* Remote I/O error */
+#define EILSEQ          122     /* Illegal byte sequence */
+#define ELIBMAX         123     /* Atmpt to link in too many shared libs */
+#define ELIBSCN         124     /* .lib section in a.out corrupted */
+
+#define ENOMEDIUM       125     /* No medium found */
+#define EMEDIUMTYPE     126     /* Wrong medium type */
+#define ECANCELED       127     /* Operation Cancelled */
+#define ENOKEY          128     /* Required key not available */
+#define EKEYEXPIRED     129     /* Key has expired */
+#define EKEYREVOKED     130     /* Key has been revoked */
+#define EKEYREJECTED    131     /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD      132     /* Owner died */
+#define ENOTRECOVERABLE 133     /* State not recoverable */
+
+#define ERFKILL         134     /* Operation not possible due to RF-kill */
+
+#define EHWPOISON       135     /* Memory page has hardware error */
+
+#endif
diff --git a/arch/sparc/include/asm/fcntl.h b/arch/sparc/include/asm/fcntl.h
new file mode 100644
index 00000000000..d0b83f66f35
--- /dev/null
+++ b/arch/sparc/include/asm/fcntl.h
@@ -0,0 +1,55 @@
+#ifndef _SPARC_FCNTL_H
+#define _SPARC_FCNTL_H
+
+#define O_APPEND        0x0008
+#define FASYNC          0x0040  /* fcntl, for BSD compatibility */
+#define O_CREAT         0x0200  /* not fcntl */
+#define O_TRUNC         0x0400  /* not fcntl */
+#define O_EXCL          0x0800  /* not fcntl */
+#define O_DSYNC         0x2000  /* used to be O_SYNC, see below */
+#define O_NONBLOCK      0x4000
+#if defined(__sparc__) && defined(__arch64__)
+#define O_NDELAY        0x0004
+#else
+#define O_NDELAY        (0x0004 | O_NONBLOCK)
+#endif
+#define O_NOCTTY        0x8000  /* not fcntl */
+#define O_LARGEFILE     0x40000
+#define O_DIRECT        0x100000 /* direct disk access hint */
+#define O_NOATIME       0x200000
+#define O_CLOEXEC       0x400000
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        0x800000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
+
+#define O_PATH          0x1000000
+
+#define F_GETOWN        5       /*  for sockets. */
+#define F_SETOWN        6       /*  for sockets. */
+#define F_GETLK         7
+#define F_SETLK         8
+#define F_SETLKW        9
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         1
+#define F_WRLCK         2
+#define F_UNLCK         3
+
+#define __ARCH_FLOCK_PAD        short __unused;
+#define __ARCH_FLOCK64_PAD      short __unused;
+
+#include <asm-generic/fcntl.h>
+
+#endif
diff --git a/arch/sparc/include/asm/fixmap.h b/arch/sparc/include/asm/fixmap.h
new file mode 100644
index 00000000000..f18fc0755ad
--- /dev/null
+++ b/arch/sparc/include/asm/fixmap.h
@@ -0,0 +1,110 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanism,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+        FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN,
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+extern void __set_fixmap (enum fixed_addresses idx,
+                                        unsigned long phys, pgprot_t flags);
+
+#define set_fixmap(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL)
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between IO pages at 0xfd000000 and
+ * the start of the fixmap.
+ */
+#define FIXADDR_TOP     (0xfcfff000UL)
+#define FIXADDR_SIZE    ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+#endif
diff --git a/arch/sparc/include/asm/ioctl.h b/arch/sparc/include/asm/ioctl.h
new file mode 100644
index 00000000000..7d6bd51321b
--- /dev/null
+++ b/arch/sparc/include/asm/ioctl.h
@@ -0,0 +1,67 @@
+#ifndef _SPARC_IOCTL_H
+#define _SPARC_IOCTL_H
+
+/*
+ * Our DIR and SIZE overlap in order to simulteneously provide
+ * a non-zero _IOC_NONE (for binary compatibility) and
+ * 14 bits of size as on i386. Here's the layout:
+ *
+ *   0xE0000000   DIR
+ *   0x80000000     DIR = WRITE
+ *   0x40000000     DIR = READ
+ *   0x20000000     DIR = NONE
+ *   0x3FFF0000   SIZE (overlaps NONE bit)
+ *   0x0000FF00   TYPE
+ *   0x000000FF   NR (CMD)
+ */
+
+#define _IOC_NRBITS      8
+#define _IOC_TYPEBITS    8
+#define _IOC_SIZEBITS   13      /* Actually 14, see below. */
+#define _IOC_DIRBITS     3
+
+#define _IOC_NRMASK      ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK    ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK    ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_XSIZEMASK   ((1 << (_IOC_SIZEBITS+1))-1)
+#define _IOC_DIRMASK     ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT     0
+#define _IOC_TYPESHIFT   (_IOC_NRSHIFT + _IOC_NRBITS)
+#define _IOC_SIZESHIFT   (_IOC_TYPESHIFT + _IOC_TYPEBITS)
+#define _IOC_DIRSHIFT    (_IOC_SIZESHIFT + _IOC_SIZEBITS)
+
+#define _IOC_NONE        1U
+#define _IOC_READ        2U
+#define _IOC_WRITE       4U
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+#define _IO(type,nr)        _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* Used to decode ioctl numbers in drivers despite the leading underscore... */
+#define _IOC_DIR(nr)    \
+ ( (((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) != 0)?   \
+                            (((nr) >> _IOC_DIRSHIFT) & (_IOC_WRITE|_IOC_READ)):  \
+                            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
+#define _IOC_TYPE(nr)       (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)         (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)   \
+ ((((((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) & (_IOC_WRITE|_IOC_READ)) == 0)?    \
+                         0: (((nr) >> _IOC_SIZESHIFT) & _IOC_XSIZEMASK))
+
+/* ...and for the PCMCIA and sound. */
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_XSIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif /* !(_SPARC_IOCTL_H) */
diff --git a/arch/sparc/include/asm/ipcbuf.h b/arch/sparc/include/asm/ipcbuf.h
new file mode 100644
index 00000000000..66013b4fe10
--- /dev/null
+++ b/arch/sparc/include/asm/ipcbuf.h
@@ -0,0 +1,32 @@
+#ifndef __SPARC_IPCBUF_H
+#define __SPARC_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for sparc/sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - on sparc for 32 bit mode (it is 32 bit on sparc64)
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+#ifndef __arch64__
+        unsigned short  __pad0;
+#endif
+        __kernel_mode_t mode;
+        unsigned short  __pad1;
+        unsigned short  seq;
+        unsigned long long __unused1;
+        unsigned long long __unused2;
+};
+
+#endif /* __SPARC_IPCBUF_H */
diff --git a/arch/sparc/include/asm/jsflash.h b/arch/sparc/include/asm/jsflash.h
new file mode 100644
index 00000000000..0717d9e39d2
--- /dev/null
+++ b/arch/sparc/include/asm/jsflash.h
@@ -0,0 +1,39 @@
+/*
+ * jsflash.h: OS Flash SIMM support for JavaStations.
+ *
+ * Copyright (C) 1999  Pete Zaitcev
+ */
+
+#ifndef _SPARC_JSFLASH_H
+#define _SPARC_JSFLASH_H
+
+#ifndef _SPARC_TYPES_H
+#include <linux/types.h>
+#endif
+
+/*
+ * Semantics of the offset is a full address.
+ * Hardcode it or get it from probe ioctl.
+ *
+ * We use full bus address, so that we would be
+ * automatically compatible with possible future systems.
+ */
+
+#define JSFLASH_IDENT   (('F'<<8)|54)
+struct jsflash_ident_arg {
+        __u64 off;                /* 0x20000000 is included */
+        __u32 size;
+        char name[32];          /* With trailing zero */
+};
+
+#define JSFLASH_ERASE   (('F'<<8)|55)
+/* Put 0 as argument, may be flags or sector number... */
+
+#define JSFLASH_PROGRAM (('F'<<8)|56)
+struct jsflash_program_arg {
+        __u64 data;             /* char* for sparc and sparc64 */
+        __u64 off;
+        __u32 size;
+};
+
+#endif /* _SPARC_JSFLASH_H */
diff --git a/arch/sparc/include/asm/memblock.h b/arch/sparc/include/asm/memblock.h
new file mode 100644
index 00000000000..c67b047ef85
--- /dev/null
+++ b/arch/sparc/include/asm/memblock.h
@@ -0,0 +1,8 @@
+#ifndef _SPARC64_MEMBLOCK_H
+#define _SPARC64_MEMBLOCK_H
+
+#include <asm/oplib.h>
+
+#define MEMBLOCK_DBG(fmt...) prom_printf(fmt)
+
+#endif /* !(_SPARC64_MEMBLOCK_H) */
diff --git a/arch/sparc/include/asm/memreg.h b/arch/sparc/include/asm/memreg.h
new file mode 100644
index 00000000000..845ad2b3918
--- /dev/null
+++ b/arch/sparc/include/asm/memreg.h
@@ -0,0 +1,51 @@
+#ifndef _SPARC_MEMREG_H
+#define _SPARC_MEMREG_H
+/* memreg.h:  Definitions of the values found in the synchronous
+ *            and asynchronous memory error registers when a fault
+ *            occurs on the sun4c.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* First the synchronous error codes, these are usually just
+ * normal page faults.
+ */
+
+#define SUN4C_SYNC_WDRESET   0x0001  /* watchdog reset */
+#define SUN4C_SYNC_SIZE      0x0002  /* bad access size? whuz this? */
+#define SUN4C_SYNC_PARITY    0x0008  /* bad ram chips caused a parity error */
+#define SUN4C_SYNC_SBUS      0x0010  /* the SBUS had some problems... */
+#define SUN4C_SYNC_NOMEM     0x0020  /* translation to non-existent ram */
+#define SUN4C_SYNC_PROT      0x0040  /* access violated pte protections */
+#define SUN4C_SYNC_NPRESENT  0x0080  /* pte said that page was not present */
+#define SUN4C_SYNC_BADWRITE  0x8000  /* while writing something went bogus */
+
+#define SUN4C_SYNC_BOLIXED  \
+        (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
+         SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
+
+/* Now the asynchronous error codes, these are almost always produced
+ * by the cache writing things back to memory and getting a bad translation.
+ * Bad DVMA transactions can cause these faults too.
+ */
+
+#define SUN4C_ASYNC_BADDVMA 0x0010  /* error during DVMA access */
+#define SUN4C_ASYNC_NOMEM   0x0020  /* write back pointed to bad phys addr */
+#define SUN4C_ASYNC_BADWB   0x0080  /* write back points to non-present page */
+
+/* Memory parity error register with associated bit constants. */
+#ifndef __ASSEMBLY__
+extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
+#endif
+
+#define SUN4C_MPE_ERROR 0x80    /* Parity error detected. (ro) */
+#define SUN4C_MPE_MULTI 0x40    /* Multiple parity errors detected. (ro) */
+#define SUN4C_MPE_TEST  0x20    /* Write inverse parity. (rw) */
+#define SUN4C_MPE_CHECK 0x10    /* Enable parity checking. (rw) */
+#define SUN4C_MPE_ERR00 0x08    /* Parity error in bits 0-7. (ro) */
+#define SUN4C_MPE_ERR08 0x04    /* Parity error in bits 8-15. (ro) */
+#define SUN4C_MPE_ERR16 0x02    /* Parity error in bits 16-23. (ro) */
+#define SUN4C_MPE_ERR24 0x01    /* Parity error in bits 24-31. (ro) */
+#define SUN4C_MPE_ERRS  0x0F    /* Bit mask for the error bits. (ro) */
+
+#endif /* !(_SPARC_MEMREG_H) */
diff --git a/arch/sparc/include/asm/module.h b/arch/sparc/include/asm/module.h
new file mode 100644
index 00000000000..ff8e02d8033
--- /dev/null
+++ b/arch/sparc/include/asm/module.h
@@ -0,0 +1,24 @@
+#ifndef __SPARC_MODULE_H
+#define __SPARC_MODULE_H
+struct mod_arch_specific { };
+
+/*
+ * Use some preprocessor magic to define the correct symbol
+ * for sparc32 and sparc64.
+ * Elf_Addr becomes Elf32_Addr for sparc32 and Elf64_Addr for sparc64
+ */
+#define ___ELF(a, b, c) a##b##c
+#define __ELF(a, b, c)  ___ELF(a, b, c)
+#define  _Elf(t)        __ELF(Elf, CONFIG_BITS, t)
+#define  _ELF(t)        __ELF(ELF, CONFIG_BITS, t)
+
+#define Elf_Shdr     _Elf(_Shdr)
+#define Elf_Sym      _Elf(_Sym)
+#define Elf_Ehdr     _Elf(_Ehdr)
+#define Elf_Rela     _Elf(_Rela)
+#define Elf_Addr     _Elf(_Addr)
+
+#define ELF_R_SYM    _ELF(_R_SYM)
+#define ELF_R_TYPE   _ELF(_R_TYPE)
+
+#endif /* __SPARC_MODULE_H */
diff --git a/arch/sparc/include/asm/mpmbox.h b/arch/sparc/include/asm/mpmbox.h
new file mode 100644
index 00000000000..f8423039b24
--- /dev/null
+++ b/arch/sparc/include/asm/mpmbox.h
@@ -0,0 +1,67 @@
+/*
+ * mpmbox.h:  Interface and defines for the OpenProm mailbox
+ *               facilities for MP machines under Linux.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_MPMBOX_H
+#define _SPARC_MPMBOX_H
+
+/* The prom allocates, for each CPU on the machine an unsigned
+ * byte in physical ram.  You probe the device tree prom nodes
+ * for these values.  The purpose of this byte is to be able to
+ * pass messages from one cpu to another.
+ */
+
+/* These are the main message types we have to look for in our
+ * Cpu mailboxes, based upon these values we decide what course
+ * of action to take.
+ */
+
+/* The CPU is executing code in the kernel. */
+#define MAILBOX_ISRUNNING     0xf0
+
+/* Another CPU called romvec->pv_exit(), you should call
+ * prom_stopcpu() when you see this in your mailbox.
+ */
+#define MAILBOX_EXIT          0xfb
+
+/* Another CPU called romvec->pv_enter(), you should call
+ * prom_cpuidle() when this is seen.
+ */
+#define MAILBOX_GOSPIN        0xfc
+
+/* Another CPU has hit a breakpoint either into kadb or the prom
+ * itself.  Just like MAILBOX_GOSPIN, you should call prom_cpuidle()
+ * at this point.
+ */
+#define MAILBOX_BPT_SPIN      0xfd
+
+/* Oh geese, some other nitwit got a damn watchdog reset.  The party's
+ * over so go call prom_stopcpu().
+ */
+#define MAILBOX_WDOG_STOP     0xfe
+
+#ifndef __ASSEMBLY__
+
+/* Handy macro's to determine a cpu's state. */
+
+/* Is the cpu still in Power On Self Test? */
+#define MBOX_POST_P(letter)  ((letter) >= 0x00 && (letter) <= 0x7f)
+
+/* Is the cpu at the 'ok' prompt of the PROM? */
+#define MBOX_PROMPROMPT_P(letter) ((letter) >= 0x80 && (letter) <= 0x8f)
+
+/* Is the cpu spinning in the PROM? */
+#define MBOX_PROMSPIN_P(letter) ((letter) >= 0x90 && (letter) <= 0xef)
+
+/* Sanity check... This is junk mail, throw it out. */
+#define MBOX_BOGON_P(letter) ((letter) >= 0xf1 && (letter) <= 0xfa)
+
+/* Is the cpu actively running an application/kernel-code? */
+#define MBOX_RUNNING_P(letter) ((letter) == MAILBOX_ISRUNNING)
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_MPMBOX_H) */
diff --git a/arch/sparc/include/asm/msgbuf.h b/arch/sparc/include/asm/msgbuf.h
new file mode 100644
index 00000000000..efc7cbe9788
--- /dev/null
+++ b/arch/sparc/include/asm/msgbuf.h
@@ -0,0 +1,38 @@
+#ifndef _SPARC_MSGBUF_H
+#define _SPARC_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for sparc64 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        PADDING(__pad1)
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        PADDING(__pad2)
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        PADDING(__pad3)
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused1;
+        unsigned long  __unused2;
+};
+#undef PADDING
+#endif /* _SPARC_MSGBUF_H */
diff --git a/arch/sparc/include/asm/openpromio.h b/arch/sparc/include/asm/openpromio.h
new file mode 100644
index 00000000000..917fb8e9c63
--- /dev/null
+++ b/arch/sparc/include/asm/openpromio.h
@@ -0,0 +1,69 @@
+#ifndef _SPARC_OPENPROMIO_H
+#define _SPARC_OPENPROMIO_H
+
+#include <linux/compiler.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/*
+ * SunOS and Solaris /dev/openprom definitions. The ioctl values
+ * were chosen to be exactly equal to the SunOS equivalents.
+ */
+
+struct openpromio
+{
+        u_int   oprom_size;             /* Actual size of the oprom_array. */
+        char    oprom_array[1];         /* Holds property names and values. */
+};
+
+#define OPROMMAXPARAM   4096            /* Maximum size of oprom_array. */
+
+#define OPROMGETOPT             0x20004F01
+#define OPROMSETOPT             0x20004F02
+#define OPROMNXTOPT             0x20004F03
+#define OPROMSETOPT2            0x20004F04
+#define OPROMNEXT               0x20004F05
+#define OPROMCHILD              0x20004F06
+#define OPROMGETPROP            0x20004F07
+#define OPROMNXTPROP            0x20004F08
+#define OPROMU2P                0x20004F09
+#define OPROMGETCONS            0x20004F0A
+#define OPROMGETFBNAME          0x20004F0B
+#define OPROMGETBOOTARGS        0x20004F0C
+/* Linux extensions */                          /* Arguments in oprom_array: */
+#define OPROMSETCUR             0x20004FF0      /* int node - Sets current node */
+#define OPROMPCI2NODE           0x20004FF1      /* int pci_bus, pci_devfn - Sets current node to PCI device's node */
+#define OPROMPATH2NODE          0x20004FF2      /* char path[] - Set current node from fully qualified PROM path */
+
+/*
+ * Return values from OPROMGETCONS:
+ */
+
+#define OPROMCONS_NOT_WSCONS    0
+#define OPROMCONS_STDIN_IS_KBD  0x1     /* stdin device is kbd */
+#define OPROMCONS_STDOUT_IS_FB  0x2     /* stdout is a framebuffer */
+#define OPROMCONS_OPENPROM      0x4     /* supports openboot */
+
+
+/*
+ *  NetBSD/OpenBSD /dev/openprom definitions.
+ */
+
+struct opiocdesc
+{
+        int     op_nodeid;              /* PROM Node ID (value-result) */
+        int     op_namelen;             /* Length of op_name. */
+        char    __user *op_name;        /* Pointer to the property name. */
+        int     op_buflen;              /* Length of op_buf (value-result) */
+        char    __user *op_buf;         /* Pointer to buffer. */
+};
+
+#define OPIOCGET        _IOWR('O', 1, struct opiocdesc)
+#define OPIOCSET        _IOW('O', 2, struct opiocdesc)
+#define OPIOCNEXTPROP   _IOWR('O', 3, struct opiocdesc)
+#define OPIOCGETOPTNODE _IOR('O', 4, int)
+#define OPIOCGETNEXT    _IOWR('O', 5, int)
+#define OPIOCGETCHILD   _IOWR('O', 6, int)
+
+#endif /* _SPARC_OPENPROMIO_H */
+
diff --git a/arch/sparc/include/asm/param.h b/arch/sparc/include/asm/param.h
new file mode 100644
index 00000000000..0bc356bf8c5
--- /dev/null
+++ b/arch/sparc/include/asm/param.h
@@ -0,0 +1,7 @@
+#ifndef _ASMSPARC_PARAM_H
+#define _ASMSPARC_PARAM_H
+
+#define EXEC_PAGESIZE   8192    /* Thanks for sun4's we carry baggage... */
+#include <asm-generic/param.h>
+
+#endif /* _ASMSPARC_PARAM_H */
diff --git a/arch/sparc/include/asm/perfctr.h b/arch/sparc/include/asm/perfctr.h
new file mode 100644
index 00000000000..8d8720a8770
--- /dev/null
+++ b/arch/sparc/include/asm/perfctr.h
@@ -0,0 +1,173 @@
+/*----------------------------------------
+  PERFORMANCE INSTRUMENTATION  
+  Guillaume Thouvenin           08/10/98
+  David S. Miller               10/06/98
+  ---------------------------------------*/
+#ifndef PERF_COUNTER_API
+#define PERF_COUNTER_API
+
+/* sys_perfctr() interface.  First arg is operation code
+ * from enumeration below.  The meaning of further arguments
+ * are determined by the operation code.
+ *
+ * NOTE: This system call is no longer provided, use the perf_events
+ *       infrastructure.
+ *
+ * Pointers which are passed by the user are pointers to 64-bit
+ * integers.
+ *
+ * Once enabled, performance counter state is retained until the
+ * process either exits or performs an exec.  That is, performance
+ * counters remain enabled for fork/clone children.
+ */
+enum perfctr_opcode {
+        /* Enable UltraSparc performance counters, ARG0 is pointer
+         * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
+         * to 64-bit accumulator for D1 counter.  ARG2 is a pointer to
+         * the initial PCR register value to use.
+         */
+        PERFCTR_ON,
+
+        /* Disable UltraSparc performance counters.  The PCR is written
+         * with zero and the user counter accumulator pointers and
+         * working PCR register value are forgotten.
+         */
+        PERFCTR_OFF,
+
+        /* Add current D0 and D1 PIC values into user pointers given
+         * in PERFCTR_ON operation.  The PIC is cleared before returning.
+         */
+        PERFCTR_READ,
+
+        /* Clear the PIC register. */
+        PERFCTR_CLRPIC,
+
+        /* Begin using a new PCR value, the pointer to which is passed
+         * in ARG0.  The PIC is also cleared after the new PCR value is
+         * written.
+         */
+        PERFCTR_SETPCR,
+
+        /* Store in pointer given in ARG0 the current PCR register value
+         * being used.
+         */
+        PERFCTR_GETPCR
+};
+
+/* I don't want the kernel's namespace to be polluted with this
+ * stuff when this file is included.  --DaveM
+ */
+#ifndef __KERNEL__
+
+#define  PRIV 0x00000001
+#define  SYS  0x00000002
+#define  USR  0x00000004
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II  */
+#define  CYCLE_CNT            0x00000000
+#define  INSTR_CNT            0x00000010
+#define  DISPATCH0_IC_MISS    0x00000020
+#define  DISPATCH0_STOREBUF   0x00000030
+#define  IC_REF               0x00000080
+#define  DC_RD                0x00000090
+#define  DC_WR                0x000000A0
+#define  LOAD_USE             0x000000B0
+#define  EC_REF               0x000000C0
+#define  EC_WRITE_HIT_RDO     0x000000D0
+#define  EC_SNOOP_INV         0x000000E0
+#define  EC_RD_HIT            0x000000F0
+
+/* Pic.S0 Selection Bit Field Encoding, Ultra-III  */
+#define  US3_CYCLE_CNT          0x00000000
+#define  US3_INSTR_CNT          0x00000010
+#define  US3_DISPATCH0_IC_MISS  0x00000020
+#define  US3_DISPATCH0_BR_TGT   0x00000030
+#define  US3_DISPATCH0_2ND_BR   0x00000040
+#define  US3_RSTALL_STOREQ      0x00000050
+#define  US3_RSTALL_IU_USE      0x00000060
+#define  US3_IC_REF             0x00000080
+#define  US3_DC_RD              0x00000090
+#define  US3_DC_WR              0x000000a0
+#define  US3_EC_REF             0x000000c0
+#define  US3_EC_WR_HIT_RTO      0x000000d0
+#define  US3_EC_SNOOP_INV       0x000000e0
+#define  US3_EC_RD_MISS         0x000000f0
+#define  US3_PC_PORT0_RD        0x00000100
+#define  US3_SI_SNOOP           0x00000110
+#define  US3_SI_CIQ_FLOW        0x00000120
+#define  US3_SI_OWNED           0x00000130
+#define  US3_SW_COUNT_0         0x00000140
+#define  US3_IU_BR_MISS_TAKEN   0x00000150
+#define  US3_IU_BR_COUNT_TAKEN  0x00000160
+#define  US3_DISP_RS_MISPRED    0x00000170
+#define  US3_FA_PIPE_COMPL      0x00000180
+#define  US3_MC_READS_0         0x00000200
+#define  US3_MC_READS_1         0x00000210
+#define  US3_MC_READS_2         0x00000220
+#define  US3_MC_READS_3         0x00000230
+#define  US3_MC_STALLS_0        0x00000240
+#define  US3_MC_STALLS_2        0x00000250
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II  */
+#define  CYCLE_CNT_D1         0x00000000
+#define  INSTR_CNT_D1         0x00000800
+#define  DISPATCH0_IC_MISPRED 0x00001000
+#define  DISPATCH0_FP_USE     0x00001800
+#define  IC_HIT               0x00004000
+#define  DC_RD_HIT            0x00004800
+#define  DC_WR_HIT            0x00005000
+#define  LOAD_USE_RAW         0x00005800
+#define  EC_HIT               0x00006000
+#define  EC_WB                0x00006800
+#define  EC_SNOOP_CB          0x00007000
+#define  EC_IT_HIT            0x00007800
+
+/* Pic.S1 Selection Bit Field Encoding, Ultra-III  */
+#define  US3_CYCLE_CNT_D1       0x00000000
+#define  US3_INSTR_CNT_D1       0x00000800
+#define  US3_DISPATCH0_MISPRED  0x00001000
+#define  US3_IC_MISS_CANCELLED  0x00001800
+#define  US3_RE_ENDIAN_MISS     0x00002000
+#define  US3_RE_FPU_BYPASS      0x00002800
+#define  US3_RE_DC_MISS         0x00003000
+#define  US3_RE_EC_MISS         0x00003800
+#define  US3_IC_MISS            0x00004000
+#define  US3_DC_RD_MISS         0x00004800
+#define  US3_DC_WR_MISS         0x00005000
+#define  US3_RSTALL_FP_USE      0x00005800
+#define  US3_EC_MISSES          0x00006000
+#define  US3_EC_WB              0x00006800
+#define  US3_EC_SNOOP_CB        0x00007000
+#define  US3_EC_IC_MISS         0x00007800
+#define  US3_RE_PC_MISS         0x00008000
+#define  US3_ITLB_MISS          0x00008800
+#define  US3_DTLB_MISS          0x00009000
+#define  US3_WC_MISS            0x00009800
+#define  US3_WC_SNOOP_CB        0x0000a000
+#define  US3_WC_SCRUBBED        0x0000a800
+#define  US3_WC_WB_WO_READ      0x0000b000
+#define  US3_PC_SOFT_HIT        0x0000c000
+#define  US3_PC_SNOOP_INV       0x0000c800
+#define  US3_PC_HARD_HIT        0x0000d000
+#define  US3_PC_PORT1_RD        0x0000d800
+#define  US3_SW_COUNT_1         0x0000e000
+#define  US3_IU_STAT_BR_MIS_UNTAKEN     0x0000e800
+#define  US3_IU_STAT_BR_COUNT_UNTAKEN   0x0000f000
+#define  US3_PC_MS_MISSES       0x0000f800
+#define  US3_MC_WRITES_0        0x00010800
+#define  US3_MC_WRITES_1        0x00011000
+#define  US3_MC_WRITES_2        0x00011800
+#define  US3_MC_WRITES_3        0x00012000
+#define  US3_MC_STALLS_1        0x00012800
+#define  US3_MC_STALLS_3        0x00013000
+#define  US3_RE_RAW_MISS        0x00013800
+#define  US3_FM_PIPE_COMPLETION 0x00014000
+
+struct vcounter_struct {
+  unsigned long long vcnt0;
+  unsigned long long vcnt1;
+};
+
+#endif /* !(__KERNEL__) */
+
+#endif /* !(PERF_COUNTER_API) */
diff --git a/arch/sparc/include/asm/pgtsun4.h b/arch/sparc/include/asm/pgtsun4.h
new file mode 100644
index 00000000000..5a0d661fb82
--- /dev/null
+++ b/arch/sparc/include/asm/pgtsun4.h
@@ -0,0 +1,171 @@
+/*
+ * pgtsun4.h:  Sun4 specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT       23
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT       23
+#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT       18
+#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 19 bit PFN on sun4 */
+#define SUN4C_PFN_MASK 0x7ffff
+ 
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE    1024
+#define SUN4C_PTRS_PER_PMD    1
+#define SUN4C_PTRS_PER_PGD    1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID        0x80000000
+#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
+#define _SUN4C_PAGE_DIRTY        0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
+#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
+#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
+#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
+#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
+#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
+#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
+
+#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+                                 _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+                                 _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+                                         _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset.  This gives us
+ * 32 swapfiles of 4GB each.  Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK     0x1f
+#define SUN4C_SWP_OFF_MASK      0x7ffff
+#define SUN4C_SWP_OFF_SHIFT     5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+        unsigned long sync_err;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_err) :
+                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+        return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+        unsigned long sync_addr;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_addr) :
+                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+        return sync_addr;
+}
+
+/* SUN4 pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_SEGMAP));
+  return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), "r" (entry),
+                       "i" (ASI_SEGMAP)
+                       : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_PTE));
+  return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), 
+                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+                       : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+  register int ctx;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+                       "=r" (ctx) :
+                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+  return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+                       : "memory");
+
+  return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4_H) */
diff --git a/arch/sparc/include/asm/pgtsun4c.h b/arch/sparc/include/asm/pgtsun4c.h
new file mode 100644
index 00000000000..aeb25e91217
--- /dev/null
+++ b/arch/sparc/include/asm/pgtsun4c.h
@@ -0,0 +1,172 @@
+/*
+ * pgtsun4c.h:  Sun4c specific pgtable.h defines and code.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifndef _SPARC_PGTSUN4C_H
+#define _SPARC_PGTSUN4C_H
+
+#include <asm/contregs.h>
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define SUN4C_PMD_SHIFT       22
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define SUN4C_PGDIR_SHIFT       22
+#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
+#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
+#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
+
+/* To represent how the sun4c mmu really lays things out. */
+#define SUN4C_REAL_PGDIR_SHIFT       18
+#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
+#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
+#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
+
+/* 16 bit PFN on sun4c */
+#define SUN4C_PFN_MASK 0xffff
+
+/* Don't increase these unless the structures in sun4c.c are fixed */
+#define SUN4C_MAX_SEGMAPS 256
+#define SUN4C_MAX_CONTEXTS 16
+
+/*
+ * To be efficient, and not have to worry about allocating such
+ * a huge pgd, we make the kernel sun4c tables each hold 1024
+ * entries and the pgd similarly just like the i386 tables.
+ */
+#define SUN4C_PTRS_PER_PTE    1024
+#define SUN4C_PTRS_PER_PMD    1
+#define SUN4C_PTRS_PER_PGD    1024
+
+/*
+ * Sparc SUN4C pte fields.
+ */
+#define _SUN4C_PAGE_VALID        0x80000000
+#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
+#define _SUN4C_PAGE_DIRTY        0x40000000
+#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
+#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
+#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
+#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
+#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
+#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
+#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
+#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
+#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
+#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
+
+#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
+                                 _SUN4C_PAGE_ACCESSED)
+#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
+                                 _SUN4C_PAGE_MODIFIED)
+
+#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
+
+#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
+#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
+                                         _SUN4C_PAGE_WRITE)
+#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
+#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
+                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
+
+/* SUN4C swap entry encoding
+ *
+ * We use 5 bits for the type and 19 for the offset.  This gives us
+ * 32 swapfiles of 4GB each.  Encoding looks like:
+ *
+ * RRRRRRRRooooooooooooooooooottttt
+ * fedcba9876543210fedcba9876543210
+ *
+ * The top 8 bits are reserved for protection and status bits, especially
+ * FILE and PRESENT.
+ */
+#define SUN4C_SWP_TYPE_MASK     0x1f
+#define SUN4C_SWP_OFF_MASK      0x7ffff
+#define SUN4C_SWP_OFF_SHIFT     5
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned long sun4c_get_synchronous_error(void)
+{
+        unsigned long sync_err;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_err) :
+                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
+        return sync_err;
+}
+
+static inline unsigned long sun4c_get_synchronous_address(void)
+{
+        unsigned long sync_addr;
+
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (sync_addr) :
+                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
+        return sync_addr;
+}
+
+/* SUN4C pte, segmap, and context manipulation */
+static inline unsigned long sun4c_get_segmap(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_SEGMAP));
+
+  return entry;
+}
+
+static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
+{
+
+  __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), "r" (entry),
+                       "i" (ASI_SEGMAP)
+                       : "memory");
+}
+
+static inline unsigned long sun4c_get_pte(unsigned long addr)
+{
+  register unsigned long entry;
+
+  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
+                       "=r" (entry) :
+                       "r" (addr), "i" (ASI_PTE));
+  return entry;
+}
+
+static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
+{
+  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
+                       "r" (addr), 
+                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
+                       : "memory");
+}
+
+static inline int sun4c_get_context(void)
+{
+  register int ctx;
+
+  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
+                       "=r" (ctx) :
+                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
+
+  return ctx;
+}
+
+static inline int sun4c_set_context(int ctx)
+{
+  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
+                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
+                       : "memory");
+
+  return ctx;
+}
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(_SPARC_PGTSUN4C_H) */
diff --git a/arch/sparc/include/asm/poll.h b/arch/sparc/include/asm/poll.h
new file mode 100644
index 00000000000..091d3ad2e83
--- /dev/null
+++ b/arch/sparc/include/asm/poll.h
@@ -0,0 +1,12 @@
+#ifndef __SPARC_POLL_H
+#define __SPARC_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      256
+#define POLLMSG         512
+#define POLLREMOVE      1024
+#define POLLRDHUP       2048
+
+#include <asm-generic/poll.h>
+
+#endif
diff --git a/arch/sparc/include/asm/posix_types.h b/arch/sparc/include/asm/posix_types.h
new file mode 100644
index 00000000000..98d6ebb922f
--- /dev/null
+++ b/arch/sparc/include/asm/posix_types.h
@@ -0,0 +1,155 @@
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+#ifndef __SPARC_POSIX_TYPES_H
+#define __SPARC_POSIX_TYPES_H
+
+#if defined(__sparc__) && defined(__arch64__)
+/* sparc 64 bit */
+typedef unsigned long          __kernel_size_t;
+typedef long                   __kernel_ssize_t;
+typedef long                   __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_pid_t;
+typedef int                    __kernel_ipc_pid_t;
+typedef unsigned int           __kernel_uid_t;
+typedef unsigned int           __kernel_gid_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned int           __kernel_mode_t;
+typedef unsigned short         __kernel_umode_t;
+typedef unsigned int           __kernel_nlink_t;
+typedef int                    __kernel_daddr_t;
+typedef long                   __kernel_off_t;
+typedef char *                 __kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef int                    __kernel_clockid_t;
+typedef int                    __kernel_timer_t;
+
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+typedef __kernel_uid_t         __kernel_uid32_t;
+typedef __kernel_gid_t         __kernel_gid32_t;
+
+typedef unsigned int           __kernel_old_dev_t;
+
+/* Note this piece of asymmetry from the v9 ABI.  */
+typedef int                    __kernel_suseconds_t;
+
+#else
+/* sparc 32 bit */
+
+typedef unsigned int           __kernel_size_t;
+typedef int                    __kernel_ssize_t;
+typedef long int               __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_suseconds_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_pid_t;
+typedef unsigned short         __kernel_ipc_pid_t;
+typedef unsigned short         __kernel_uid_t;
+typedef unsigned short         __kernel_gid_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned short         __kernel_mode_t;
+typedef unsigned short         __kernel_umode_t;
+typedef short                  __kernel_nlink_t;
+typedef long                   __kernel_daddr_t;
+typedef long                   __kernel_off_t;
+typedef char *                 __kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef unsigned int           __kernel_uid32_t;
+typedef unsigned int           __kernel_gid32_t;
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+typedef unsigned short         __kernel_old_dev_t;
+typedef int                    __kernel_clockid_t;
+typedef int                    __kernel_timer_t;
+
+#endif /* defined(__sparc__) && defined(__arch64__) */
+
+#ifdef __GNUC__
+typedef long long              __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#ifdef __KERNEL__
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long fd, __const__ __kernel_fd_set *p)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant cases (8 or 32 longs,
+ * for 256 and 1024-bit fd_sets respectively)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned long *tmp = p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                        case 32:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          tmp[16] = 0; tmp[17] = 0; tmp[18] = 0; tmp[19] = 0;
+                          tmp[20] = 0; tmp[21] = 0; tmp[22] = 0; tmp[23] = 0;
+                          tmp[24] = 0; tmp[25] = 0; tmp[26] = 0; tmp[27] = 0;
+                          tmp[28] = 0; tmp[29] = 0; tmp[30] = 0; tmp[31] = 0;
+                          return;
+                        case 16:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+                          tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+                          return;
+                        case 8:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+                          return;
+                        case 4:
+                          tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+                          return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* __KERNEL__ */
+#endif /* __SPARC_POSIX_TYPES_H */
diff --git a/arch/sparc/include/asm/psrcompat.h b/arch/sparc/include/asm/psrcompat.h
new file mode 100644
index 00000000000..44b6327dbbf
--- /dev/null
+++ b/arch/sparc/include/asm/psrcompat.h
@@ -0,0 +1,45 @@
+#ifndef _SPARC64_PSRCOMPAT_H
+#define _SPARC64_PSRCOMPAT_H
+
+#include <asm/pstate.h>
+
+/* Old 32-bit PSR fields for the compatibility conversion code. */
+#define PSR_CWP     0x0000001f         /* current window pointer     */
+#define PSR_ET      0x00000020         /* enable traps field         */
+#define PSR_PS      0x00000040         /* previous privilege level   */
+#define PSR_S       0x00000080         /* current privilege level    */
+#define PSR_PIL     0x00000f00         /* processor interrupt level  */
+#define PSR_EF      0x00001000         /* enable floating point      */
+#define PSR_EC      0x00002000         /* enable co-processor        */
+#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
+#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
+#define PSR_ICC     0x00f00000         /* integer condition codes    */
+#define PSR_C       0x00100000         /* carry bit                  */
+#define PSR_V       0x00200000         /* overflow bit               */
+#define PSR_Z       0x00400000         /* zero bit                   */
+#define PSR_N       0x00800000         /* negative bit               */
+#define PSR_VERS    0x0f000000         /* cpu-version field          */
+#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
+
+#define PSR_V8PLUS  0xff000000         /* fake impl/ver, meaning a 64bit CPU is present */
+#define PSR_XCC     0x000f0000         /* if PSR_V8PLUS, this is %xcc */
+
+static inline unsigned int tstate_to_psr(unsigned long tstate)
+{
+        return ((tstate & TSTATE_CWP)                   |
+                PSR_S                                   |
+                ((tstate & TSTATE_ICC) >> 12)           |
+                ((tstate & TSTATE_XCC) >> 20)           |
+                ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
+                PSR_V8PLUS);
+}
+
+static inline unsigned long psr_to_tstate_icc(unsigned int psr)
+{
+        unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
+        if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
+                tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
+        return tstate;
+}
+
+#endif /* !(_SPARC64_PSRCOMPAT_H) */
diff --git a/arch/sparc/include/asm/pstate.h b/arch/sparc/include/asm/pstate.h
new file mode 100644
index 00000000000..a26a53777bb
--- /dev/null
+++ b/arch/sparc/include/asm/pstate.h
@@ -0,0 +1,91 @@
+#ifndef _SPARC64_PSTATE_H
+#define _SPARC64_PSTATE_H
+
+#include <linux/const.h>
+
+/* The V9 PSTATE Register (with SpitFire extensions).
+ *
+ * -----------------------------------------------------------------------
+ * | Resv | IG | MG | CLE | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
+ * -----------------------------------------------------------------------
+ *  63  12  11   10    9     8    7   6   5     4     3     2     1    0
+ */
+#define PSTATE_IG   _AC(0x0000000000000800,UL) /* Interrupt Globals.    */
+#define PSTATE_MG   _AC(0x0000000000000400,UL) /* MMU Globals.          */
+#define PSTATE_CLE  _AC(0x0000000000000200,UL) /* Current Little Endian.*/
+#define PSTATE_TLE  _AC(0x0000000000000100,UL) /* Trap Little Endian.   */
+#define PSTATE_MM   _AC(0x00000000000000c0,UL) /* Memory Model.         */
+#define PSTATE_TSO  _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder   */
+#define PSTATE_PSO  _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */
+#define PSTATE_RMO  _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
+#define PSTATE_RED  _AC(0x0000000000000020,UL) /* Reset Error Debug.    */
+#define PSTATE_PEF  _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
+#define PSTATE_AM   _AC(0x0000000000000008,UL) /* Address Mask.         */
+#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege.            */
+#define PSTATE_IE   _AC(0x0000000000000002,UL) /* Interrupt Enable.     */
+#define PSTATE_AG   _AC(0x0000000000000001,UL) /* Alternate Globals.    */
+
+/* The V9 TSTATE Register (with SpitFire and Linux extensions).
+ *
+ * ---------------------------------------------------------------------
+ * |  Resv |  GL  |  CCR  |  ASI  |  %pil  |  PSTATE  |  Resv  |  CWP  |
+ * ---------------------------------------------------------------------
+ *  63   43 42  40 39   32 31   24 23    20 19       8 7      5 4     0
+ */
+#define TSTATE_GL       _AC(0x0000070000000000,UL) /* Global reg level  */
+#define TSTATE_CCR      _AC(0x000000ff00000000,UL) /* Condition Codes.  */
+#define TSTATE_XCC      _AC(0x000000f000000000,UL) /* Condition Codes.  */
+#define TSTATE_XNEG     _AC(0x0000008000000000,UL) /* %xcc Negative.    */
+#define TSTATE_XZERO    _AC(0x0000004000000000,UL) /* %xcc Zero.        */
+#define TSTATE_XOVFL    _AC(0x0000002000000000,UL) /* %xcc Overflow.    */
+#define TSTATE_XCARRY   _AC(0x0000001000000000,UL) /* %xcc Carry.       */
+#define TSTATE_ICC      _AC(0x0000000f00000000,UL) /* Condition Codes.  */
+#define TSTATE_INEG     _AC(0x0000000800000000,UL) /* %icc Negative.    */
+#define TSTATE_IZERO    _AC(0x0000000400000000,UL) /* %icc Zero.        */
+#define TSTATE_IOVFL    _AC(0x0000000200000000,UL) /* %icc Overflow.    */
+#define TSTATE_ICARRY   _AC(0x0000000100000000,UL) /* %icc Carry.       */
+#define TSTATE_ASI      _AC(0x00000000ff000000,UL) /* AddrSpace ID.     */
+#define TSTATE_PIL      _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
+#define TSTATE_PSTATE   _AC(0x00000000000fff00,UL) /* PSTATE.           */
+#define TSTATE_IG       _AC(0x0000000000080000,UL) /* Interrupt Globals.*/
+#define TSTATE_MG       _AC(0x0000000000040000,UL) /* MMU Globals.      */
+#define TSTATE_CLE      _AC(0x0000000000020000,UL) /* CurrLittleEndian. */
+#define TSTATE_TLE      _AC(0x0000000000010000,UL) /* TrapLittleEndian. */
+#define TSTATE_MM       _AC(0x000000000000c000,UL) /* Memory Model.     */
+#define TSTATE_TSO      _AC(0x0000000000000000,UL) /* MM: TSO           */
+#define TSTATE_PSO      _AC(0x0000000000004000,UL) /* MM: PSO           */
+#define TSTATE_RMO      _AC(0x0000000000008000,UL) /* MM: RMO           */
+#define TSTATE_RED      _AC(0x0000000000002000,UL) /* Reset Error Debug.*/
+#define TSTATE_PEF      _AC(0x0000000000001000,UL) /* FPU Enable.       */
+#define TSTATE_AM       _AC(0x0000000000000800,UL) /* Address Mask.     */
+#define TSTATE_PRIV     _AC(0x0000000000000400,UL) /* Privilege.        */
+#define TSTATE_IE       _AC(0x0000000000000200,UL) /* Interrupt Enable. */
+#define TSTATE_AG       _AC(0x0000000000000100,UL) /* Alternate Globals.*/
+#define TSTATE_SYSCALL  _AC(0x0000000000000020,UL) /* in syscall trap   */
+#define TSTATE_CWP      _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
+
+/* Floating-Point Registers State Register.
+ *
+ * --------------------------------
+ * |  Resv  |  FEF  |  DU  |  DL  |
+ * --------------------------------
+ *  63     3    2       1      0
+ */
+#define FPRS_FEF        _AC(0x0000000000000004,UL) /* FPU Enable.       */
+#define FPRS_DU         _AC(0x0000000000000002,UL) /* Dirty Upper.      */
+#define FPRS_DL         _AC(0x0000000000000001,UL) /* Dirty Lower.      */
+
+/* Version Register.
+ *
+ * ------------------------------------------------------
+ * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN |
+ * ------------------------------------------------------
+ *  63   48 47  32 31  24 23  16 15    8 7    5 4      0
+ */
+#define VERS_MANUF      _AC(0xffff000000000000,UL) /* Manufacturer.     */
+#define VERS_IMPL       _AC(0x0000ffff00000000,UL) /* Implementation.   */
+#define VERS_MASK       _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
+#define VERS_MAXTL      _AC(0x000000000000ff00,UL) /* Max Trap Level.   */
+#define VERS_MAXWIN     _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
+
+#endif /* !(_SPARC64_PSTATE_H) */
diff --git a/arch/sparc/include/asm/resource.h b/arch/sparc/include/asm/resource.h
new file mode 100644
index 00000000000..fe163cafb4c
--- /dev/null
+++ b/arch/sparc/include/asm/resource.h
@@ -0,0 +1,30 @@
+/*
+ * resource.h: Resource definitions.
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_RESOURCE_H
+#define _SPARC_RESOURCE_H
+
+/*
+ * These two resource limit IDs have a Sparc/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           6       /* max number of open files */
+#define RLIMIT_NPROC            7       /* max number of processes */
+
+#if defined(__sparc__) && defined(__arch64__)
+/* Use generic version */
+#else
+/*
+ * SuS says limits have to be unsigned.
+ * We make this unsigned, but keep the
+ * old value for compatibility:
+ */
+#define RLIM_INFINITY           0x7fffffff
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* !(_SPARC_RESOURCE_H) */
diff --git a/arch/sparc/include/asm/sembuf.h b/arch/sparc/include/asm/sembuf.h
new file mode 100644
index 00000000000..faee1be08d6
--- /dev/null
+++ b/arch/sparc/include/asm/sembuf.h
@@ -0,0 +1,31 @@
+#ifndef _SPARC_SEMBUF_H
+#define _SPARC_SEMBUF_H
+
+/*
+ * The semid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        PADDING(__pad1)
+        __kernel_time_t sem_otime;              /* last semop time */
+        PADDING(__pad2)
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+#undef PADDING
+
+#endif /* _SPARC64_SEMBUF_H */
diff --git a/arch/sparc/include/asm/shmbuf.h b/arch/sparc/include/asm/shmbuf.h
new file mode 100644
index 00000000000..83a16055363
--- /dev/null
+++ b/arch/sparc/include/asm/shmbuf.h
@@ -0,0 +1,50 @@
+#ifndef _SPARC_SHMBUF_H
+#define _SPARC_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for sparc architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+#if defined(__sparc__) && defined(__arch64__)
+# define PADDING(x)
+#else
+# define PADDING(x) unsigned int x;
+#endif
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        PADDING(__pad1)
+        __kernel_time_t         shm_atime;      /* last attach time */
+        PADDING(__pad2)
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        PADDING(__pad3)
+        __kernel_time_t         shm_ctime;      /* last change time */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#undef PADDING
+
+#endif /* _SPARC_SHMBUF_H */
diff --git a/arch/sparc/include/asm/smpprim.h b/arch/sparc/include/asm/smpprim.h
new file mode 100644
index 00000000000..eb849d862c6
--- /dev/null
+++ b/arch/sparc/include/asm/smpprim.h
@@ -0,0 +1,54 @@
+/*
+ *  smpprim.h:  SMP locking primitives on the Sparc
+ *
+ *  God knows we won't be actually using this code for some time
+ *  but I thought I'd write it since I knew how.
+ *
+ *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_SMPPRIM_H
+#define __SPARC_SMPPRIM_H
+
+/* Test and set the unsigned byte at ADDR to 1.  Returns the previous
+ * value.  On the Sparc we use the ldstub instruction since it is
+ * atomic.
+ */
+
+static inline __volatile__ char test_and_set(void *addr)
+{
+        char state = 0;
+
+        __asm__ __volatile__("ldstub [%0], %1         ! test_and_set\n\t"
+                             "=r" (addr), "=r" (state) :
+                             "0" (addr), "1" (state) : "memory");
+
+        return state;
+}
+
+/* Initialize a spin-lock. */
+static inline __volatile__ smp_initlock(void *spinlock)
+{
+        /* Unset the lock. */
+        *((unsigned char *) spinlock) = 0;
+
+        return;
+}
+
+/* This routine spins until it acquires the lock at ADDR. */
+static inline __volatile__ smp_lock(void *addr)
+{
+        while(test_and_set(addr) == 0xff)
+                ;
+
+        /* We now have the lock */
+        return;
+}
+
+/* This routine releases the lock at ADDR. */
+static inline __volatile__ smp_unlock(void *addr)
+{
+        *((unsigned char *) addr) = 0;
+}
+
+#endif /* !(__SPARC_SMPPRIM_H) */
diff --git a/arch/sparc/include/asm/socket.h b/arch/sparc/include/asm/socket.h
new file mode 100644
index 00000000000..9d3fefcff2f
--- /dev/null
+++ b/arch/sparc/include/asm/socket.h
@@ -0,0 +1,66 @@
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001
+#define SO_PASSCRED     0x0002
+#define SO_REUSEADDR    0x0004
+#define SO_KEEPALIVE    0x0008
+#define SO_DONTROUTE    0x0010
+#define SO_BROADCAST    0x0020
+#define SO_PEERCRED     0x0040
+#define SO_LINGER       0x0080
+#define SO_OOBINLINE    0x0100
+/* To add :#define SO_REUSEPORT 0x0200 */
+#define SO_BSDCOMPAT    0x0400
+#define SO_RCVLOWAT     0x0800
+#define SO_SNDLOWAT     0x1000
+#define SO_RCVTIMEO     0x2000
+#define SO_SNDTIMEO     0x4000
+#define SO_ACCEPTCONN   0x8000
+
+#define SO_SNDBUF       0x1001
+#define SO_RCVBUF       0x1002
+#define SO_SNDBUFFORCE  0x100a
+#define SO_RCVBUFFORCE  0x100b
+#define SO_ERROR        0x1007
+#define SO_TYPE         0x1008
+#define SO_PROTOCOL     0x1028
+#define SO_DOMAIN       0x1029
+
+
+/* Linux specific, keep the same. */
+#define SO_NO_CHECK     0x000b
+#define SO_PRIORITY     0x000c
+
+#define SO_BINDTODEVICE 0x000d
+
+#define SO_ATTACH_FILTER        0x001a
+#define SO_DETACH_FILTER        0x001b
+
+#define SO_PEERNAME             0x001c
+#define SO_TIMESTAMP            0x001d
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_PEERSEC              0x001e
+#define SO_PASSSEC              0x001f
+#define SO_TIMESTAMPNS          0x0021
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 0x0022
+
+#define SO_TIMESTAMPING         0x0023
+#define SCM_TIMESTAMPING        SO_TIMESTAMPING
+
+#define SO_RXQ_OVFL             0x0024
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              0x5001
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        0x5002
+#define SO_SECURITY_ENCRYPTION_NETWORK          0x5004
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/sparc/include/asm/sockios.h b/arch/sparc/include/asm/sockios.h
new file mode 100644
index 00000000000..990ea746486
--- /dev/null
+++ b/arch/sparc/include/asm/sockios.h
@@ -0,0 +1,14 @@
+#ifndef _ASM_SPARC_SOCKIOS_H
+#define _ASM_SPARC_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* !(_ASM_SPARC_SOCKIOS_H) */
+
diff --git a/arch/sparc/include/asm/stat.h b/arch/sparc/include/asm/stat.h
new file mode 100644
index 00000000000..a232e9e1f4e
--- /dev/null
+++ b/arch/sparc/include/asm/stat.h
@@ -0,0 +1,107 @@
+#ifndef __SPARC_STAT_H
+#define __SPARC_STAT_H
+
+#include <linux/types.h>
+
+#if defined(__sparc__) && defined(__arch64__)
+/* 64 bit sparc */
+struct stat {
+        unsigned   st_dev;
+        ino_t   st_ino;
+        mode_t  st_mode;
+        short   st_nlink;
+        uid_t   st_uid;
+        gid_t   st_gid;
+        unsigned   st_rdev;
+        off_t   st_size;
+        time_t  st_atime;
+        time_t  st_mtime;
+        time_t  st_ctime;
+        off_t   st_blksize;
+        off_t   st_blocks;
+        unsigned long  __unused4[2];
+};
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_ino;
+        unsigned long   st_nlink;
+
+        unsigned int    st_mode;
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+        unsigned int    __pad0;
+
+        unsigned long   st_rdev;
+        long            st_size;
+        long            st_blksize;
+        long            st_blocks;
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        long            __unused[3];
+};
+
+#else
+/* 32 bit sparc */
+struct stat {
+        unsigned short  st_dev;
+        ino_t           st_ino;
+        mode_t          st_mode;
+        short           st_nlink;
+        unsigned short  st_uid;
+        unsigned short  st_gid;
+        unsigned short  st_rdev;
+        off_t           st_size;
+        time_t          st_atime;
+        unsigned long   st_atime_nsec;
+        time_t          st_mtime;
+        unsigned long   st_mtime_nsec;
+        time_t          st_ctime;
+        unsigned long   st_ctime_nsec;
+        off_t           st_blksize;
+        off_t           st_blocks;
+        unsigned long   __unused4[2];
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat64 {
+        unsigned long long st_dev;
+
+        unsigned long long st_ino;
+
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned int    st_uid;
+        unsigned int    st_gid;
+
+        unsigned long long st_rdev;
+
+        unsigned char   __pad3[8];
+
+        long long       st_size;
+        unsigned int    st_blksize;
+
+        unsigned char   __pad4[8];
+        unsigned int    st_blocks;
+
+        unsigned int    st_atime;
+        unsigned int    st_atime_nsec;
+
+        unsigned int    st_mtime;
+        unsigned int    st_mtime_nsec;
+
+        unsigned int    st_ctime;
+        unsigned int    st_ctime_nsec;
+
+        unsigned int    __unused4;
+        unsigned int    __unused5;
+};
+#endif /* defined(__sparc__) && defined(__arch64__) */
+#endif /* __SPARC_STAT_H */
diff --git a/arch/sparc/include/asm/statfs.h b/arch/sparc/include/asm/statfs.h
new file mode 100644
index 00000000000..55e607ad461
--- /dev/null
+++ b/arch/sparc/include/asm/statfs.h
@@ -0,0 +1,6 @@
+#ifndef ___ASM_SPARC_STATFS_H
+#define ___ASM_SPARC_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif
diff --git a/arch/sparc/include/asm/swab.h b/arch/sparc/include/asm/swab.h
new file mode 100644
index 00000000000..a34ad079487
--- /dev/null
+++ b/arch/sparc/include/asm/swab.h
@@ -0,0 +1,45 @@
+#ifndef _SPARC_SWAB_H
+#define _SPARC_SWAB_H
+
+#include <linux/types.h>
+#include <asm/asi.h>
+
+#if defined(__sparc__) && defined(__arch64__)
+static inline __u16 __arch_swab16p(const __u16 *addr)
+{
+        __u16 ret;
+
+        __asm__ __volatile__ ("lduha [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+#define __arch_swab16p __arch_swab16p
+
+static inline __u32 __arch_swab32p(const __u32 *addr)
+{
+        __u32 ret;
+
+        __asm__ __volatile__ ("lduwa [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+#define __arch_swab32p __arch_swab32p
+
+static inline __u64 __arch_swab64p(const __u64 *addr)
+{
+        __u64 ret;
+
+        __asm__ __volatile__ ("ldxa [%1] %2, %0"
+                              : "=r" (ret)
+                              : "r" (addr), "i" (ASI_PL));
+        return ret;
+}
+#define __arch_swab64p __arch_swab64p
+
+#else
+#define __SWAB_64_THRU_32__
+#endif /* defined(__sparc__) && defined(__arch64__) */
+
+#endif /* _SPARC_SWAB_H */
diff --git a/arch/sparc/include/asm/sysen.h b/arch/sparc/include/asm/sysen.h
new file mode 100644
index 00000000000..6af34abde6e
--- /dev/null
+++ b/arch/sparc/include/asm/sysen.h
@@ -0,0 +1,15 @@
+/*
+ * sysen.h:  Bit fields within the "System Enable" register accessed via
+ *           the ASI_CONTROL address space at address AC_SYSENABLE.
+ *
+ * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef _SPARC_SYSEN_H
+#define _SPARC_SYSEN_H
+
+#define SENABLE_DVMA   0x20   /* enable dvma transfers */
+#define SENABLE_CACHE  0x10   /* enable VAC cache */
+#define SENABLE_RESET  0x04   /* reset whole machine, danger Will Robinson */
+
+#endif /* _SPARC_SYSEN_H */
diff --git a/arch/sparc/include/asm/system.h b/arch/sparc/include/asm/system.h
new file mode 100644
index 00000000000..7944a7cfc99
--- /dev/null
+++ b/arch/sparc/include/asm/system.h
@@ -0,0 +1,8 @@
+#ifndef ___ASM_SPARC_SYSTEM_H
+#define ___ASM_SPARC_SYSTEM_H
+#if defined(__sparc__) && defined(__arch64__)
+#include <asm/system_64.h>
+#else
+#include <asm/system_32.h>
+#endif
+#endif
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
new file mode 100644
index 00000000000..aba16092a81
--- /dev/null
+++ b/arch/sparc/include/asm/system_32.h
@@ -0,0 +1,284 @@
+#ifndef __SPARC_SYSTEM_H
+#define __SPARC_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <linux/threads.h>      /* NR_CPUS */
+#include <linux/thread_info.h>
+
+#include <asm/page.h>
+#include <asm/psr.h>
+#include <asm/ptrace.h>
+#include <asm/btfixup.h>
+#include <asm/smp.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+  sun4        = 0x00,
+  sun4c       = 0x01,
+  sun4m       = 0x02,
+  sun4d       = 0x03,
+  sun4e       = 0x04,
+  sun4u       = 0x05, /* V8 ploos ploos */
+  sun_unknown = 0x06,
+  ap1000      = 0x07, /* almost a sun4m */
+  sparc_leon  = 0x08, /* Leon SoC */
+};
+
+/* Really, userland should not be looking at any of this... */
+#ifdef __KERNEL__
+
+extern enum sparc_cpu sparc_cpu_model;
+
+#define ARCH_SUN4C (sparc_cpu_model==sun4c)
+
+#define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
+
+extern char reboot_command[];
+
+extern struct thread_info *current_set[NR_CPUS];
+
+extern unsigned long empty_bad_page;
+extern unsigned long empty_bad_page_table;
+extern unsigned long empty_zero_page;
+
+extern void sun_do_break(void);
+extern int serial_console;
+extern int stop_a_enabled;
+extern int scons_pwroff;
+
+static inline int con_is_present(void)
+{
+        return serial_console ? 0 : 1;
+}
+
+/* When a context switch happens we must flush all user windows so that
+ * the windows of the current process are flushed onto its stack. This
+ * way the windows are all clean for the next process and the stack
+ * frames are up to date.
+ */
+extern void flush_user_windows(void);
+extern void kill_user_windows(void);
+extern void synchronize_user_stack(void);
+extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
+                   void *fpqueue, unsigned long *fpqdepth);
+
+#ifdef CONFIG_SMP
+#define SWITCH_ENTER(prv) \
+        do {                    \
+        if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
+                put_psr(get_psr() | PSR_EF); \
+                fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
+                       &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
+                clear_tsk_thread_flag(prv, TIF_USEDFPU); \
+                (prv)->thread.kregs->psr &= ~PSR_EF; \
+        } \
+        } while(0)
+
+#define SWITCH_DO_LAZY_FPU(next)        /* */
+#else
+#define SWITCH_ENTER(prv)               /* */
+#define SWITCH_DO_LAZY_FPU(nxt) \
+        do {                    \
+        if (last_task_used_math != (nxt))               \
+                (nxt)->thread.kregs->psr&=~PSR_EF;      \
+        } while(0)
+#endif
+
+extern void flushw_all(void);
+
+/*
+ * Flush windows so that the VM switch which follows
+ * would not pull the stack from under us.
+ *
+ * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
+ * XXX WTF is the above comment? Found in late teen 2.4.x.
+ */
+#define prepare_arch_switch(next) do { \
+        __asm__ __volatile__( \
+        ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
+        "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+        "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
+        "save %sp, -0x40, %sp\n\t" \
+        "restore; restore; restore; restore; restore; restore; restore"); \
+} while(0)
+
+        /* Much care has gone into this code, do not touch it.
+         *
+         * We need to loadup regs l0/l1 for the newly forked child
+         * case because the trap return path relies on those registers
+         * holding certain values, gcc is told that they are clobbered.
+         * Gcc needs registers for 3 values in and 1 value out, so we
+         * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
+         *
+         * Hey Dave, that do not touch sign is too much of an incentive
+         * - Anton & Pete
+         */
+#define switch_to(prev, next, last) do {                                                \
+        SWITCH_ENTER(prev);                                                             \
+        SWITCH_DO_LAZY_FPU(next);                                                       \
+        cpumask_set_cpu(smp_processor_id(), mm_cpumask(next->active_mm));               \
+        __asm__ __volatile__(                                                           \
+        "sethi  %%hi(here - 0x8), %%o7\n\t"                                             \
+        "mov    %%g6, %%g3\n\t"                                                         \
+        "or     %%o7, %%lo(here - 0x8), %%o7\n\t"                                       \
+        "rd     %%psr, %%g4\n\t"                                                        \
+        "std    %%sp, [%%g6 + %4]\n\t"                                                  \
+        "rd     %%wim, %%g5\n\t"                                                        \
+        "wr     %%g4, 0x20, %%psr\n\t"                                                  \
+        "nop\n\t"                                                                       \
+        "std    %%g4, [%%g6 + %3]\n\t"                                                  \
+        "ldd    [%2 + %3], %%g4\n\t"                                                    \
+        "mov    %2, %%g6\n\t"                                                           \
+        ".globl patchme_store_new_current\n"                                            \
+"patchme_store_new_current:\n\t"                                                        \
+        "st     %2, [%1]\n\t"                                                           \
+        "wr     %%g4, 0x20, %%psr\n\t"                                                  \
+        "nop\n\t"                                                                       \
+        "nop\n\t"                                                                       \
+        "nop\n\t"       /* LEON needs all 3 nops: load to %sp depends on CWP. */                \
+        "ldd    [%%g6 + %4], %%sp\n\t"                                                  \
+        "wr     %%g5, 0x0, %%wim\n\t"                                                   \
+        "ldd    [%%sp + 0x00], %%l0\n\t"                                                \
+        "ldd    [%%sp + 0x38], %%i6\n\t"                                                \
+        "wr     %%g4, 0x0, %%psr\n\t"                                                   \
+        "nop\n\t"                                                                       \
+        "nop\n\t"                                                                       \
+        "jmpl   %%o7 + 0x8, %%g0\n\t"                                                   \
+        " ld    [%%g3 + %5], %0\n\t"                                                    \
+        "here:\n"                                                                       \
+        : "=&r" (last)                                                                  \
+        : "r" (&(current_set[hard_smp_processor_id()])),        \
+          "r" (task_thread_info(next)),                         \
+          "i" (TI_KPSR),                                        \
+          "i" (TI_KSP),                                         \
+          "i" (TI_TASK)                                         \
+        :       "g1", "g2", "g3", "g4", "g5",       "g7",       \
+          "l0", "l1",       "l3", "l4", "l5", "l6", "l7",       \
+          "i0", "i1", "i2", "i3", "i4", "i5",                   \
+          "o0", "o1", "o2", "o3",                   "o7");      \
+        } while(0)
+
+/* XXX Change this if we ever use a PSO mode kernel. */
+#define mb()    __asm__ __volatile__ ("" : : : "memory")
+#define rmb()   mb()
+#define wmb()   mb()
+#define read_barrier_depends()  do { } while(0)
+#define set_mb(__var, __value)  do { __var = __value; mb(); } while(0)
+#define smp_mb()        __asm__ __volatile__("":::"memory")
+#define smp_rmb()       __asm__ __volatile__("":::"memory")
+#define smp_wmb()       __asm__ __volatile__("":::"memory")
+#define smp_read_barrier_depends()      do { } while(0)
+
+#define nop() __asm__ __volatile__ ("nop")
+
+/* This has special calling conventions */
+#ifndef CONFIG_SMP
+BTFIXUPDEF_CALL(void, ___xchg32, void)
+#endif
+
+static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
+{
+#ifdef CONFIG_SMP
+        __asm__ __volatile__("swap [%2], %0"
+                             : "=&r" (val)
+                             : "0" (val), "r" (m)
+                             : "memory");
+        return val;
+#else
+        register unsigned long *ptr asm("g1");
+        register unsigned long ret asm("g2");
+
+        ptr = (unsigned long *) m;
+        ret = val;
+
+        /* Note: this is magic and the nop there is
+           really needed. */
+        __asm__ __volatile__(
+        "mov    %%o7, %%g4\n\t"
+        "call   ___f____xchg32\n\t"
+        " nop\n\t"
+        : "=&r" (ret)
+        : "0" (ret), "r" (ptr)
+        : "g3", "g4", "g7", "memory", "cc");
+
+        return ret;
+#endif
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
+{
+        switch (size) {
+        case 4:
+                return xchg_u32(ptr, x);
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+/* Emulate cmpxchg() the same way we emulate atomics,
+ * by hashing the object address and indexing into an array
+ * of spinlocks to get a bit of performance...
+ *
+ * See arch/sparc/lib/atomic32.c for implementation.
+ *
+ * Cribbed from <asm-parisc/atomic.h>
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+
+/* bug catcher for when unsupported size is used - won't link */
+extern void __cmpxchg_called_with_bad_pointer(void);
+/* we only need to support cmpxchg of a u32 on sparc */
+extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
+
+/* don't worry...optimizer will get rid of most of this */
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
+        default:
+                __cmpxchg_called_with_bad_pointer();
+                break;
+        }
+        return old;
+}
+
+#define cmpxchg(ptr, o, n)                                              \
+({                                                                      \
+        __typeof__(*(ptr)) _o_ = (o);                                   \
+        __typeof__(*(ptr)) _n_ = (n);                                   \
+        (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,       \
+                        (unsigned long)_n_, sizeof(*(ptr)));            \
+})
+
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                               \
+        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC_SYSTEM_H) */
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
new file mode 100644
index 00000000000..10bcabce97b
--- /dev/null
+++ b/arch/sparc/include/asm/system_64.h
@@ -0,0 +1,331 @@
+#ifndef __SPARC64_SYSTEM_H
+#define __SPARC64_SYSTEM_H
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
+#include <asm/visasm.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/irqflags.h>
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * Sparc (general) CPU types
+ */
+enum sparc_cpu {
+  sun4        = 0x00,
+  sun4c       = 0x01,
+  sun4m       = 0x02,
+  sun4d       = 0x03,
+  sun4e       = 0x04,
+  sun4u       = 0x05, /* V8 ploos ploos */
+  sun_unknown = 0x06,
+  ap1000      = 0x07, /* almost a sun4m */
+};
+
+#define sparc_cpu_model sun4u
+
+/* This cannot ever be a sun4c :) That's just history. */
+#define ARCH_SUN4C 0
+
+extern char reboot_command[];
+
+/* These are here in an effort to more fully work around Spitfire Errata
+ * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
+ * branch, the chip can stop executing instructions until a trap occurs.
+ * Therefore, if interrupts are disabled, the chip can hang forever.
+ *
+ * It used to be believed that the memory barrier had to be right in the
+ * delay slot, but a case has been traced recently wherein the memory barrier
+ * was one instruction after the branch delay slot and the chip still hung.
+ * The offending sequence was the following in sym_wakeup_done() of the
+ * sym53c8xx_2 driver:
+ *
+ *      call    sym_ccb_from_dsa, 0
+ *       movge  %icc, 0, %l0
+ *      brz,pn  %o0, .LL1303
+ *       mov    %o0, %l2
+ *      membar  #LoadLoad
+ *
+ * The branch has to be mispredicted for the bug to occur.  Therefore, we put
+ * the memory barrier explicitly into a "branch always, predicted taken"
+ * delay slot to avoid the problem case.
+ */
+#define membar_safe(type) \
+do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
+                             " membar   " type "\n" \
+                             "1:\n" \
+                             : : : "memory"); \
+} while (0)
+
+/* The kernel always executes in TSO memory model these days,
+ * and furthermore most sparc64 chips implement more stringent
+ * memory ordering than required by the specifications.
+ */
+#define mb()    membar_safe("#StoreLoad")
+#define rmb()   __asm__ __volatile__("":::"memory")
+#define wmb()   __asm__ __volatile__("":::"memory")
+
+#endif
+
+#define nop()           __asm__ __volatile__ ("nop")
+
+#define read_barrier_depends()          do { } while(0)
+#define set_mb(__var, __value) \
+        do { __var = __value; membar_safe("#StoreLoad"); } while(0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#else
+#define smp_mb()        __asm__ __volatile__("":::"memory")
+#define smp_rmb()       __asm__ __volatile__("":::"memory")
+#define smp_wmb()       __asm__ __volatile__("":::"memory")
+#endif
+
+#define smp_read_barrier_depends()      do { } while(0)
+
+#define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
+
+#define flushw_all()    __asm__ __volatile__("flushw")
+
+/* Performance counter register access. */
+#define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
+#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
+#define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
+
+/* Blackbird errata workaround.  See commentary in
+ * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
+ * for more information.
+ */
+#define write_pic(__p)                                          \
+        __asm__ __volatile__("ba,pt     %%xcc, 99f\n\t"         \
+                             " nop\n\t"                         \
+                             ".align    64\n"                   \
+                          "99:wr        %0, 0x0, %%pic\n\t"     \
+                             "rd        %%pic, %%g0" : : "r" (__p))
+#define reset_pic()     write_pic(0)
+
+#ifndef __ASSEMBLY__
+
+extern void sun_do_break(void);
+extern int stop_a_enabled;
+extern int scons_pwroff;
+
+extern void fault_in_user_windows(void);
+extern void synchronize_user_stack(void);
+
+extern void __flushw_user(void);
+#define flushw_user() __flushw_user()
+
+#define flush_user_windows flushw_user
+#define flush_register_windows flushw_all
+
+/* Don't hold the runqueue lock over context switch */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+#define prepare_arch_switch(next)               \
+do {                                            \
+        flushw_all();                           \
+} while (0)
+
+        /* See what happens when you design the chip correctly?
+         *
+         * We tell gcc we clobber all non-fixed-usage registers except
+         * for l0/l1.  It will use one for 'next' and the other to hold
+         * the output value of 'last'.  'next' is not referenced again
+         * past the invocation of switch_to in the scheduler, so we need
+         * not preserve it's value.  Hairy, but it lets us remove 2 loads
+         * and 2 stores in this critical code path.  -DaveM
+         */
+#define switch_to(prev, next, last)                                     \
+do {    flush_tlb_pending();                                            \
+        save_and_clear_fpu();                                           \
+        /* If you are tempted to conditionalize the following */        \
+        /* so that ASI is only written if it changes, think again. */   \
+        __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
+        : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
+        trap_block[current_thread_info()->cpu].thread =                 \
+                task_thread_info(next);                                 \
+        __asm__ __volatile__(                                           \
+        "mov    %%g4, %%g7\n\t"                                         \
+        "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
+        "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
+        "rdpr   %%wstate, %%o5\n\t"                                     \
+        "stx    %%o6, [%%g6 + %6]\n\t"                                  \
+        "stb    %%o5, [%%g6 + %5]\n\t"                                  \
+        "rdpr   %%cwp, %%o5\n\t"                                        \
+        "stb    %%o5, [%%g6 + %8]\n\t"                                  \
+        "wrpr   %%g0, 15, %%pil\n\t"                                    \
+        "mov    %4, %%g6\n\t"                                           \
+        "ldub   [%4 + %8], %%g1\n\t"                                    \
+        "wrpr   %%g1, %%cwp\n\t"                                        \
+        "ldx    [%%g6 + %6], %%o6\n\t"                                  \
+        "ldub   [%%g6 + %5], %%o5\n\t"                                  \
+        "ldub   [%%g6 + %7], %%o7\n\t"                                  \
+        "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
+        "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
+        "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
+        "ldx    [%%g6 + %9], %%g4\n\t"                                  \
+        "wrpr   %%g0, 14, %%pil\n\t"                                    \
+        "brz,pt %%o7, switch_to_pc\n\t"                                 \
+        " mov   %%g7, %0\n\t"                                           \
+        "sethi  %%hi(ret_from_syscall), %%g1\n\t"                       \
+        "jmpl   %%g1 + %%lo(ret_from_syscall), %%g0\n\t"                \
+        " nop\n\t"                                                      \
+        ".globl switch_to_pc\n\t"                                       \
+        "switch_to_pc:\n\t"                                             \
+        : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
+          "=r" (__local_per_cpu_offset)                                 \
+        : "0" (task_thread_info(next)),                                 \
+          "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
+          "i" (TI_CWP), "i" (TI_TASK)                                   \
+        : "cc",                                                         \
+                "g1", "g2", "g3",                   "g7",               \
+                "l1", "l2", "l3", "l4", "l5", "l6", "l7",               \
+          "i0", "i1", "i2", "i3", "i4", "i5",                           \
+          "o0", "o1", "o2", "o3", "o4", "o5",       "o7");              \
+} while(0)
+
+static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"       mov             %0, %1\n"
+"1:     lduw            [%4], %2\n"
+"       cas             [%4], %2, %0\n"
+"       cmp             %2, %0\n"
+"       bne,a,pn        %%icc, 1b\n"
+"        mov            %1, %0\n"
+        : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+        : "0" (val), "r" (m)
+        : "cc", "memory");
+        return val;
+}
+
+static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
+{
+        unsigned long tmp1, tmp2;
+
+        __asm__ __volatile__(
+"       mov             %0, %1\n"
+"1:     ldx             [%4], %2\n"
+"       casx            [%4], %2, %0\n"
+"       cmp             %2, %0\n"
+"       bne,a,pn        %%xcc, 1b\n"
+"        mov            %1, %0\n"
+        : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
+        : "0" (val), "r" (m)
+        : "cc", "memory");
+        return val;
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
+                                       int size)
+{
+        switch (size) {
+        case 4:
+                return xchg32(ptr, x);
+        case 8:
+                return xchg64(ptr, x);
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long
+__cmpxchg_u32(volatile int *m, int old, int new)
+{
+        __asm__ __volatile__("cas [%2], %3, %0"
+                             : "=&r" (new)
+                             : "0" (new), "r" (m), "r" (old)
+                             : "memory");
+
+        return new;
+}
+
+static inline unsigned long
+__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
+{
+        __asm__ __volatile__("casx [%2], %3, %0"
+                             : "=&r" (new)
+                             : "0" (new), "r" (m), "r" (old)
+                             : "memory");
+
+        return new;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static inline unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+        switch (size) {
+                case 4:
+                        return __cmpxchg_u32(ptr, old, new);
+                case 8:
+                        return __cmpxchg_u64(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+                                      unsigned long old,
+                                      unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+        case 8: return __cmpxchg(ptr, old, new, size);
+        default:
+                return __cmpxchg_local_generic(ptr, old, new, size);
+        }
+
+        return old;
+}
+
+#define cmpxchg_local(ptr, o, n)                                        \
+        ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+
+#endif /* !(__ASSEMBLY__) */
+
+#define arch_align_stack(x) (x)
+
+#endif /* !(__SPARC64_SYSTEM_H) */
diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h
new file mode 100644
index 00000000000..91e5a034f98
--- /dev/null
+++ b/arch/sparc/include/asm/types.h
@@ -0,0 +1,23 @@
+#ifndef _SPARC_TYPES_H
+#define _SPARC_TYPES_H
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+#if defined(__sparc__)
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* defined(__sparc__) */
+
+#endif /* defined(_SPARC_TYPES_H) */
diff --git a/arch/sparc/include/asm/uctx.h b/arch/sparc/include/asm/uctx.h
new file mode 100644
index 00000000000..dc937c75ffd
--- /dev/null
+++ b/arch/sparc/include/asm/uctx.h
@@ -0,0 +1,71 @@
+/*
+ * uctx.h: Sparc64 {set,get}context() register state layouts.
+ *
+ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC64_UCTX_H
+#define __SPARC64_UCTX_H
+
+#define MC_TSTATE       0
+#define MC_PC           1
+#define MC_NPC          2
+#define MC_Y            3
+#define MC_G1           4
+#define MC_G2           5
+#define MC_G3           6
+#define MC_G4           7
+#define MC_G5           8
+#define MC_G6           9
+#define MC_G7           10
+#define MC_O0           11
+#define MC_O1           12
+#define MC_O2           13
+#define MC_O3           14
+#define MC_O4           15
+#define MC_O5           16
+#define MC_O6           17
+#define MC_O7           18
+#define MC_NGREG        19
+
+typedef unsigned long mc_greg_t;
+typedef mc_greg_t mc_gregset_t[MC_NGREG];
+
+#define MC_MAXFPQ       16
+struct mc_fq {
+        unsigned long   *mcfq_addr;
+        unsigned int    mcfq_insn;
+};
+
+struct mc_fpu {
+        union {
+                unsigned int    sregs[32];
+                unsigned long   dregs[32];
+                long double     qregs[16];
+        } mcfpu_fregs;
+        unsigned long   mcfpu_fsr;
+        unsigned long   mcfpu_fprs;
+        unsigned long   mcfpu_gsr;
+        struct mc_fq    *mcfpu_fq;
+        unsigned char   mcfpu_qcnt;
+        unsigned char   mcfpu_qentsz;
+        unsigned char   mcfpu_enab;
+};
+typedef struct mc_fpu mc_fpu_t;
+
+typedef struct {
+        mc_gregset_t    mc_gregs;
+        mc_greg_t       mc_fp;
+        mc_greg_t       mc_i7;
+        mc_fpu_t        mc_fpregs;
+} mcontext_t;
+
+struct ucontext {
+        struct ucontext         *uc_link;
+        unsigned long           uc_flags;
+        sigset_t                uc_sigmask;
+        mcontext_t              uc_mcontext;
+};
+typedef struct ucontext ucontext_t;
+
+#endif /* __SPARC64_UCTX_H */
diff --git a/arch/sparc/include/asm/utrap.h b/arch/sparc/include/asm/utrap.h
new file mode 100644
index 00000000000..b10e527c22d
--- /dev/null
+++ b/arch/sparc/include/asm/utrap.h
@@ -0,0 +1,51 @@
+/*
+ * include/asm/utrap.h
+ *
+ * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ */
+
+#ifndef __ASM_SPARC64_UTRAP_H
+#define __ASM_SPARC64_UTRAP_H
+
+#define UT_INSTRUCTION_EXCEPTION                1
+#define UT_INSTRUCTION_ERROR                    2
+#define UT_INSTRUCTION_PROTECTION               3
+#define UT_ILLTRAP_INSTRUCTION                  4
+#define UT_ILLEGAL_INSTRUCTION                  5
+#define UT_PRIVILEGED_OPCODE                    6
+#define UT_FP_DISABLED                          7
+#define UT_FP_EXCEPTION_IEEE_754                8
+#define UT_FP_EXCEPTION_OTHER                   9
+#define UT_TAG_OVERVIEW                         10
+#define UT_DIVISION_BY_ZERO                     11
+#define UT_DATA_EXCEPTION                       12
+#define UT_DATA_ERROR                           13
+#define UT_DATA_PROTECTION                      14
+#define UT_MEM_ADDRESS_NOT_ALIGNED              15
+#define UT_PRIVILEGED_ACTION                    16
+#define UT_ASYNC_DATA_ERROR                     17
+#define UT_TRAP_INSTRUCTION_16                  18
+#define UT_TRAP_INSTRUCTION_17                  19
+#define UT_TRAP_INSTRUCTION_18                  20
+#define UT_TRAP_INSTRUCTION_19                  21
+#define UT_TRAP_INSTRUCTION_20                  22
+#define UT_TRAP_INSTRUCTION_21                  23
+#define UT_TRAP_INSTRUCTION_22                  24
+#define UT_TRAP_INSTRUCTION_23                  25
+#define UT_TRAP_INSTRUCTION_24                  26
+#define UT_TRAP_INSTRUCTION_25                  27
+#define UT_TRAP_INSTRUCTION_26                  28
+#define UT_TRAP_INSTRUCTION_27                  29
+#define UT_TRAP_INSTRUCTION_28                  30
+#define UT_TRAP_INSTRUCTION_29                  31
+#define UT_TRAP_INSTRUCTION_30                  32
+#define UT_TRAP_INSTRUCTION_31                  33
+
+#define UTH_NOCHANGE                            (-1)
+
+#ifndef __ASSEMBLY__
+typedef int utrap_entry_t;
+typedef void *utrap_handler_t;
+#endif /* __ASSEMBLY__ */
+
+#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h
new file mode 100644
index 00000000000..a63e88ef042
--- /dev/null
+++ b/arch/sparc/include/asm/vac-ops.h
@@ -0,0 +1,127 @@
+#ifndef _SPARC_VAC_OPS_H
+#define _SPARC_VAC_OPS_H
+
+/* vac-ops.h: Inline assembly routines to do operations on the Sparc
+ *            VAC (virtual address cache) for the sun4c.
+ *
+ * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#include <asm/sysen.h>
+#include <asm/contregs.h>
+#include <asm/asi.h>
+
+/* The SUN4C models have a virtually addressed write-through
+ * cache.
+ *
+ * The cache tags are directly accessible through an ASI and
+ * each have the form:
+ *
+ * ------------------------------------------------------------
+ * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
+ * ------------------------------------------------------------
+ *  31 25  24   22     21     20     19    18 16  15   2  1  0
+ *
+ * MBZ: These bits are either unused and/or reserved and should
+ *      be written as zeroes.
+ *
+ * CONTEXT: Records the context to which this cache line belongs.
+ *
+ * WRITE: A copy of the writable bit from the mmu pte access bits.
+ *
+ * PRIV: A copy of the privileged bit from the pte access bits.
+ *
+ * VALID: If set, this line is valid, else invalid.
+ *
+ * TagID: Fourteen bits of tag ID.
+ *
+ * Every virtual address is seen by the cache like this:
+ *
+ * ----------------------------------------
+ * |  RESV  | TagID | LINE | BYTE-in-LINE |
+ * ----------------------------------------
+ *  31    30 29   16 15   4 3            0
+ *
+ * RESV: Unused/reserved.
+ *
+ * TagID: Used to match the Tag-ID in that vac tags.
+ *
+ * LINE: Which line within the cache
+ *
+ * BYTE-in-LINE: Which byte within the cache line.
+ */
+
+/* Sun4c VAC Tags */
+#define S4CVACTAG_CID      0x01c00000
+#define S4CVACTAG_W        0x00200000
+#define S4CVACTAG_P        0x00100000
+#define S4CVACTAG_V        0x00080000
+#define S4CVACTAG_TID      0x0000fffc
+
+/* Sun4c VAC Virtual Address */
+/* These aren't used, why bother? (Anton) */
+#if 0
+#define S4CVACVA_TID       0x3fff0000
+#define S4CVACVA_LINE      0x0000fff0
+#define S4CVACVA_BIL       0x0000000f
+#endif
+
+/* The indexing of cache lines creates a problem.  Because the line
+ * field of a virtual address extends past the page offset within
+ * the virtual address it is possible to have what are called
+ * 'bad aliases' which will create inconsistencies.  So we must make
+ * sure that within a context that if a physical page is mapped
+ * more than once, that 'extra' line bits are the same.  If this is
+ * not the case, and thus is a 'bad alias' we must turn off the
+ * cacheable bit in the pte's of all such pages.
+ */
+
+#define S4CVAC_BADBITS    0x0000f000
+
+/* The following is true if vaddr1 and vaddr2 would cause
+ * a 'bad alias'.
+ */
+#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
+        ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
+         (S4CVAC_BADBITS))
+
+/* The following structure describes the characteristics of a sun4c
+ * VAC as probed from the prom during boot time.
+ */
+struct sun4c_vac_props {
+        unsigned int num_bytes;     /* Size of the cache */
+        unsigned int do_hwflushes;  /* Hardware flushing available? */
+        unsigned int linesize;      /* Size of each line in bytes */
+        unsigned int log2lsize;     /* log2(linesize) */
+        unsigned int on;            /* VAC is enabled */
+};
+
+extern struct sun4c_vac_props sun4c_vacinfo;
+
+/* sun4c_enable_vac() enables the sun4c virtual address cache. */
+static inline void sun4c_enable_vac(void)
+{
+        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+                             "or    %%g1, %2, %%g1\n\t"
+                             "stba  %%g1, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" ((unsigned int) AC_SENABLE),
+                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+                             : "g1", "memory");
+        sun4c_vacinfo.on = 1;
+}
+
+/* sun4c_disable_vac() disables the virtual address cache. */
+static inline void sun4c_disable_vac(void)
+{
+        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
+                             "andn  %%g1, %2, %%g1\n\t"
+                             "stba  %%g1, [%0] %1\n\t"
+                             : /* no outputs */
+                             : "r" ((unsigned int) AC_SENABLE),
+                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
+                             : "g1", "memory");
+        sun4c_vacinfo.on = 0;
+}
+
+#endif /* !(_SPARC_VAC_OPS_H) */
diff --git a/arch/sparc/include/asm/watchdog.h b/arch/sparc/include/asm/watchdog.h
new file mode 100644
index 00000000000..5baf2d3919c
--- /dev/null
+++ b/arch/sparc/include/asm/watchdog.h
@@ -0,0 +1,31 @@
+/*
+ *
+ * watchdog - Driver interface for the hardware watchdog timers
+ * present on Sun Microsystems boardsets
+ *
+ * Copyright (c) 2000 Eric Brower <ebrower@usa.net>
+ *
+ */
+
+#ifndef _SPARC64_WATCHDOG_H
+#define _SPARC64_WATCHDOG_H
+
+#include <linux/watchdog.h>
+
+/* Solaris compatibility ioctls--
+ * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
+ */
+#define WIOCSTART _IO (WATCHDOG_IOCTL_BASE, 10)         /* Start Timer          */
+#define WIOCSTOP  _IO (WATCHDOG_IOCTL_BASE, 11)         /* Stop Timer           */
+#define WIOCGSTAT _IOR(WATCHDOG_IOCTL_BASE, 12, int)/* Get Timer Status */
+
+/* Status flags from WIOCGSTAT ioctl
+ */
+#define WD_FREERUN      0x01    /* timer is running, interrupts disabled        */
+#define WD_EXPIRED      0x02    /* timer has expired                                            */
+#define WD_RUNNING      0x04    /* timer is running, interrupts enabled         */
+#define WD_STOPPED      0x08    /* timer has not been started                           */
+#define WD_SERVICED 0x10        /* timer interrupt was serviced                         */
+
+#endif /* ifndef _SPARC64_WATCHDOG_H */
+