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authorMagnus Damm <damm@opensource.se>2010-05-11 00:59:58 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:32:31 -0400
commit4780683a135abbe17f7867d295cd542cde5678b6 (patch)
tree2611ec0ab097c1c75367175f3a8ce42b617468d5 /arch/sh
parent25637f7ae0324c636bde172d9e92bc00d4f0121d (diff)
sh: sh7366 mstp32 index rework
This patch adds sh7366 MSTP enums for mstp_clks[] index. The MSTP bit for the SIU is removed as well since it is not included in the documentation. Most likely an old copy paste error from sh7722. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c92
1 files changed, 50 insertions, 42 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 44cc5a0965d..8b9cd314998 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -148,48 +148,56 @@ struct clk div6_clks[DIV6_NR] = {
148#define MSTP(_str, _parent, _reg, _bit, _flags) \ 148#define MSTP(_str, _parent, _reg, _bit, _flags) \
149 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 149 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
150 150
151static struct clk mstp_clks[] = { 151enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
152 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
153 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
154 MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
155 MSTP109, MSTP100,
156 MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
157 MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
158 MSTP_NR };
159
160static struct clk mstp_clks[MSTP_NR] = {
152 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 161 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
153 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 162 [MSTP031] = MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
154 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 163 [MSTP030] = MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
155 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 164 [MSTP029] = MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
156 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 165 [MSTP028] = MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
157 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 166 [MSTP026] = MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
158 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 167 [MSTP023] = MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
159 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 168 [MSTP022] = MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
160 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 169 [MSTP021] = MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
161 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 170 [MSTP020] = MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
162 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 171 [MSTP019] = MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
163 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 172 [MSTP017] = MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
164 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 173 [MSTP015] = MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
165 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), 174 [MSTP014] = MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
166 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 175 [MSTP013] = MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
167 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 176 [MSTP011] = MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 177 [MSTP010] = MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), 178 [MSTP007] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
170 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), 179 [MSTP006] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
171 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 180 [MSTP005] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
172 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 181 [MSTP002] = MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
173 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 182 [MSTP001] = MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
174 183
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 184 [MSTP109] = MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 185
177 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 186 [MSTP227] = MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
178 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 187 [MSTP226] = MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
179 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 188 [MSTP224] = MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 189 [MSTP223] = MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
181 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 190 [MSTP222] = MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
182 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 191 [MSTP218] = MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
183 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 192 [MSTP217] = MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
184 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 193 [MSTP211] = MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
185 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 194 [MSTP207] = MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
186 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 195 [MSTP205] = MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
187 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 196 [MSTP204] = MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
188 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 197 [MSTP203] = MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
189 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 198 [MSTP202] = MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
190 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 199 [MSTP201] = MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
191 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 200 [MSTP200] = MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
192 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
193}; 201};
194 202
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
@@ -221,7 +229,7 @@ int __init arch_clk_init(void)
221 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 229 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
222 230
223 if (!ret) 231 if (!ret)
224 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 232 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
225 233
226 return ret; 234 return ret;
227} 235}