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authorPaul Mundt <lethal@linux-sh.org>2012-05-09 22:51:07 -0400
committerPaul Mundt <lethal@linux-sh.org>2012-05-09 22:51:07 -0400
commit15f99cbd071aa402e113d342448603344a337046 (patch)
tree56f98892d1bd38029988eb8931e2321ef7e79aa0 /arch/sh/kernel
parentb2212ea41dacda8cce0e7681a3a6ccc76c63802e (diff)
parent41797f75486d8ca3b98d7658c2a506ac7879a8e5 (diff)
Merge branch 'sh/rsk-updates' into sh-latest
Conflicts: arch/sh/Kconfig Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/proc.c1
-rw-r--r--arch/sh/kernel/cpu/sh2a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7264.c153
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c2136
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c3
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7264.c606
6 files changed, 2901 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index e3a16d10452..27dd6f915ea 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -7,6 +7,7 @@
7static const char *cpu_name[] = { 7static const char *cpu_name[] = {
8 [CPU_SH7201] = "SH7201", 8 [CPU_SH7201] = "SH7201",
9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", 9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
10 [CPU_SH7264] = "SH7264",
10 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", 11 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
11 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", 12 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
12 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", 13 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 45f85c77ef7..64b0986275b 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -11,10 +11,12 @@ obj-$(CONFIG_SH_FPU) += fpu.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
15obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o 16obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
16 17
17# Pinmux setup 18# Pinmux setup
18pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o 19pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
20pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
19 21
20obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) 22obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7264.c b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
new file mode 100644
index 00000000000..fdf585c9528
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
@@ -0,0 +1,153 @@
1/*
2 * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
3 *
4 * SH7264 clock framework support
5 *
6 * Copyright (C) 2012 Phil Edworthy
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16#include <asm/clock.h>
17
18/* SH7264 registers */
19#define FRQCR 0xfffe0010
20#define STBCR3 0xfffe0408
21#define STBCR4 0xfffe040c
22#define STBCR5 0xfffe0410
23#define STBCR6 0xfffe0414
24#define STBCR7 0xfffe0418
25#define STBCR8 0xfffe041c
26
27static const unsigned int pll1rate[] = {8, 12};
28
29static unsigned int pll1_div;
30
31/* Fixed 32 KHz root clock for RTC */
32static struct clk r_clk = {
33 .rate = 32768,
34};
35
36/*
37 * Default rate for the root input clock, reset this with clk_set_rate()
38 * from the platform code.
39 */
40static struct clk extal_clk = {
41 .rate = 18000000,
42};
43
44static unsigned long pll_recalc(struct clk *clk)
45{
46 unsigned long rate = clk->parent->rate / pll1_div;
47 return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
48}
49
50static struct sh_clk_ops pll_clk_ops = {
51 .recalc = pll_recalc,
52};
53
54static struct clk pll_clk = {
55 .ops = &pll_clk_ops,
56 .parent = &extal_clk,
57 .flags = CLK_ENABLE_ON_INIT,
58};
59
60struct clk *main_clks[] = {
61 &r_clk,
62 &extal_clk,
63 &pll_clk,
64};
65
66static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
67
68static struct clk_div_mult_table div4_div_mult_table = {
69 .divisors = div2,
70 .nr_divisors = ARRAY_SIZE(div2),
71};
72
73static struct clk_div4_table div4_table = {
74 .div_mult_table = &div4_div_mult_table,
75};
76
77enum { DIV4_I, DIV4_P,
78 DIV4_NR };
79
80#define DIV4(_reg, _bit, _mask, _flags) \
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
82
83/* The mask field specifies the div2 entries that are valid */
84struct clk div4_clks[DIV4_NR] = {
85 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
86 | CLK_ENABLE_ON_INIT),
87 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
88};
89
90enum { MSTP77, MSTP74, MSTP72,
91 MSTP60,
92 MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
93 MSTP_NR };
94
95static struct clk mstp_clks[MSTP_NR] = {
96 [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
97 [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
98 [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
99 [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
100 [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
101 [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
102 [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
103 [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
104 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
105};
106
107static struct clk_lookup lookups[] = {
108 /* main clocks */
109 CLKDEV_CON_ID("rclk", &r_clk),
110 CLKDEV_CON_ID("extal", &extal_clk),
111 CLKDEV_CON_ID("pll_clk", &pll_clk),
112
113 /* DIV4 clocks */
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
115 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
116
117 /* MSTP clocks */
118 CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
119 CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
120 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
121 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
122 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
123 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
124 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
125 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
126 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
127};
128
129int __init arch_clk_init(void)
130{
131 int k, ret = 0;
132
133 if (test_mode_pin(MODE_PIN0)) {
134 if (test_mode_pin(MODE_PIN1))
135 pll1_div = 3;
136 else
137 pll1_div = 4;
138 } else
139 pll1_div = 1;
140
141 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
142 ret = clk_register(main_clks[k]);
143
144 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
145
146 if (!ret)
147 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
148
149 if (!ret)
150 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
151
152 return ret;
153}
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
new file mode 100644
index 00000000000..b055b55d6f2
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -0,0 +1,2136 @@
1/*
2 * SH7264 Pinmux
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <cpu/sh7264.h>
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 /* Port A */
21 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
22 /* Port B */
23 PB22_DATA, PB21_DATA, PB20_DATA,
24 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
25 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
26 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
27 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28 PB3_DATA, PB2_DATA, PB1_DATA,
29 /* Port C */
30 PC10_DATA, PC9_DATA, PC8_DATA,
31 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
32 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
33 /* Port D */
34 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
35 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
36 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
37 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
38 /* Port E */
39 PE5_DATA, PE4_DATA,
40 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
41 /* Port F */
42 PF12_DATA,
43 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
44 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
45 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
46 /* Port G */
47 PG24_DATA,
48 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
49 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
50 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
51 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
52 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
53 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
54 /* Port H */
55 /* NOTE - Port H does not have a Data Register, but PH Data is
56 connected to PH Port Register */
57 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
58 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
59 /* Port I - not on device */
60 /* Port J */
61 PJ12_DATA,
62 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
63 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
64 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
65 /* Port K */
66 PK12_DATA,
67 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
68 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
69 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
70 PINMUX_DATA_END,
71
72 PINMUX_INPUT_BEGIN,
73 FORCE_IN,
74 /* Port A */
75 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
76 /* Port B */
77 PB22_IN, PB21_IN, PB20_IN,
78 PB19_IN, PB18_IN, PB17_IN, PB16_IN,
79 PB15_IN, PB14_IN, PB13_IN, PB12_IN,
80 PB11_IN, PB10_IN, PB9_IN, PB8_IN,
81 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
82 PB3_IN, PB2_IN, PB1_IN,
83 /* Port C */
84 PC10_IN, PC9_IN, PC8_IN,
85 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
86 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
87 /* Port D */
88 PD15_IN, PD14_IN, PD13_IN, PD12_IN,
89 PD11_IN, PD10_IN, PD9_IN, PD8_IN,
90 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
91 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
92 /* Port E */
93 PE5_IN, PE4_IN,
94 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
95 /* Port F */
96 PF12_IN,
97 PF11_IN, PF10_IN, PF9_IN, PF8_IN,
98 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
99 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
100 /* Port G */
101 PG24_IN,
102 PG23_IN, PG22_IN, PG21_IN, PG20_IN,
103 PG19_IN, PG18_IN, PG17_IN, PG16_IN,
104 PG15_IN, PG14_IN, PG13_IN, PG12_IN,
105 PG11_IN, PG10_IN, PG9_IN, PG8_IN,
106 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
107 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
108 /* Port H - Port H does not have a Data Register */
109 /* Port I - not on device */
110 /* Port J */
111 PJ12_IN,
112 PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
113 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
114 PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
115 /* Port K */
116 PK12_IN,
117 PK11_IN, PK10_IN, PK9_IN, PK8_IN,
118 PK7_IN, PK6_IN, PK5_IN, PK4_IN,
119 PK3_IN, PK2_IN, PK1_IN, PK0_IN,
120 PINMUX_INPUT_END,
121
122 PINMUX_OUTPUT_BEGIN,
123 FORCE_OUT,
124 /* Port A */
125 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
126 /* Port B */
127 PB22_OUT, PB21_OUT, PB20_OUT,
128 PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
129 PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
130 PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
131 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
132 PB3_OUT, PB2_OUT, PB1_OUT,
133 /* Port C */
134 PC10_OUT, PC9_OUT, PC8_OUT,
135 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
136 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
137 /* Port D */
138 PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
139 PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
140 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
141 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
142 /* Port E */
143 PE5_OUT, PE4_OUT,
144 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
145 /* Port F */
146 PF12_OUT,
147 PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
148 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
149 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
150 /* Port G */
151 PG24_OUT,
152 PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
153 PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
154 PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
155 PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
156 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
157 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
158 /* Port H - Port H does not have a Data Register */
159 /* Port I - not on device */
160 /* Port J */
161 PJ12_OUT,
162 PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
163 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
164 PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
165 /* Port K */
166 PK12_OUT,
167 PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT,
168 PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
169 PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
170 PINMUX_OUTPUT_END,
171
172 PINMUX_FUNCTION_BEGIN,
173 /* Port A */
174 PA3_IOR_IN, PA3_IOR_OUT,
175 PA2_IOR_IN, PA2_IOR_OUT,
176 PA1_IOR_IN, PA1_IOR_OUT,
177 PA0_IOR_IN, PA0_IOR_OUT,
178
179 /* Port B */
180 PB11_IOR_IN, PB11_IOR_OUT,
181 PB10_IOR_IN, PB10_IOR_OUT,
182 PB9_IOR_IN, PB9_IOR_OUT,
183 PB8_IOR_IN, PB8_IOR_OUT,
184
185 PB22MD_00, PB22MD_01, PB22MD_10,
186 PB21MD_0, PB21MD_1,
187 PB20MD_0, PB20MD_1,
188 PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11,
189 PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11,
190 PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11,
191 PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11,
192 PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11,
193 PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11,
194 PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11,
195 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
196 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
197 PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
198 PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
199 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
200 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
201 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
202 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
203 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
204 PB3MD_0, PB3MD_1,
205 PB2MD_0, PB2MD_1,
206 PB1MD_0, PB1MD_1,
207
208 /* Port C */
209 PC14_IOR_IN, PC14_IOR_OUT,
210 PC13_IOR_IN, PC13_IOR_OUT,
211 PC12_IOR_IN, PC12_IOR_OUT,
212 PC11_IOR_IN, PC11_IOR_OUT,
213 PC10_IOR_IN, PC10_IOR_OUT,
214 PC9_IOR_IN, PC9_IOR_OUT,
215 PC8_IOR_IN, PC8_IOR_OUT,
216 PC7_IOR_IN, PC7_IOR_OUT,
217 PC6_IOR_IN, PC6_IOR_OUT,
218 PC5_IOR_IN, PC5_IOR_OUT,
219 PC4_IOR_IN, PC4_IOR_OUT,
220 PC3_IOR_IN, PC3_IOR_OUT,
221 PC2_IOR_IN, PC2_IOR_OUT,
222 PC1_IOR_IN, PC1_IOR_OUT,
223 PC0_IOR_IN, PC0_IOR_OUT,
224
225 PC10MD_0, PC10MD_1,
226 PC9MD_0, PC9MD_1,
227 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11,
228 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11,
229 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11,
230 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11,
231 PC4MD_0, PC4MD_1,
232 PC3MD_0, PC3MD_1,
233 PC2MD_0, PC2MD_1,
234 PC1MD_0, PC1MD_1,
235 PC0MD_0, PC0MD_1,
236
237 /* Port D */
238 PD15_IOR_IN, PD15_IOR_OUT,
239 PD14_IOR_IN, PD14_IOR_OUT,
240 PD13_IOR_IN, PD13_IOR_OUT,
241 PD12_IOR_IN, PD12_IOR_OUT,
242 PD11_IOR_IN, PD11_IOR_OUT,
243 PD10_IOR_IN, PD10_IOR_OUT,
244 PD9_IOR_IN, PD9_IOR_OUT,
245 PD8_IOR_IN, PD8_IOR_OUT,
246 PD7_IOR_IN, PD7_IOR_OUT,
247 PD6_IOR_IN, PD6_IOR_OUT,
248 PD5_IOR_IN, PD5_IOR_OUT,
249 PD4_IOR_IN, PD4_IOR_OUT,
250 PD3_IOR_IN, PD3_IOR_OUT,
251 PD2_IOR_IN, PD2_IOR_OUT,
252 PD1_IOR_IN, PD1_IOR_OUT,
253 PD0_IOR_IN, PD0_IOR_OUT,
254
255 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
256 PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
257 PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
258 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
259 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
260 PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
261 PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
262 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
263 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
264 PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
265 PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
266 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
267 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
268 PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
269 PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
270 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
271
272 /* Port E */
273 PE5_IOR_IN, PE5_IOR_OUT,
274 PE4_IOR_IN, PE4_IOR_OUT,
275 PE3_IOR_IN, PE3_IOR_OUT,
276 PE2_IOR_IN, PE2_IOR_OUT,
277 PE1_IOR_IN, PE1_IOR_OUT,
278 PE0_IOR_IN, PE0_IOR_OUT,
279
280 PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
281 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
282 PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11,
283 PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11,
284 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
285 PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
286 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
287
288 /* Port F */
289 PF12_IOR_IN, PF12_IOR_OUT,
290 PF11_IOR_IN, PF11_IOR_OUT,
291 PF10_IOR_IN, PF10_IOR_OUT,
292 PF9_IOR_IN, PF9_IOR_OUT,
293 PF8_IOR_IN, PF8_IOR_OUT,
294 PF7_IOR_IN, PF7_IOR_OUT,
295 PF6_IOR_IN, PF6_IOR_OUT,
296 PF5_IOR_IN, PF5_IOR_OUT,
297 PF4_IOR_IN, PF4_IOR_OUT,
298 PF3_IOR_IN, PF3_IOR_OUT,
299 PF2_IOR_IN, PF2_IOR_OUT,
300 PF1_IOR_IN, PF1_IOR_OUT,
301 PF0_IOR_IN, PF0_IOR_OUT,
302
303 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
304 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
305 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
306 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
307 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
308 PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
309 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
310 PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
311 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11,
312 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
313 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
314 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
315 PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
316 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
317 PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
318 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
319 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
320 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
321 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
322 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
323 PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
324 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
325 PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
326 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
327 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
328
329 /* Port G */
330 PG24_IOR_IN, PG24_IOR_OUT,
331 PG23_IOR_IN, PG23_IOR_OUT,
332 PG22_IOR_IN, PG22_IOR_OUT,
333 PG21_IOR_IN, PG21_IOR_OUT,
334 PG20_IOR_IN, PG20_IOR_OUT,
335 PG19_IOR_IN, PG19_IOR_OUT,
336 PG18_IOR_IN, PG18_IOR_OUT,
337 PG17_IOR_IN, PG17_IOR_OUT,
338 PG16_IOR_IN, PG16_IOR_OUT,
339 PG15_IOR_IN, PG15_IOR_OUT,
340 PG14_IOR_IN, PG14_IOR_OUT,
341 PG13_IOR_IN, PG13_IOR_OUT,
342 PG12_IOR_IN, PG12_IOR_OUT,
343 PG11_IOR_IN, PG11_IOR_OUT,
344 PG10_IOR_IN, PG10_IOR_OUT,
345 PG9_IOR_IN, PG9_IOR_OUT,
346 PG8_IOR_IN, PG8_IOR_OUT,
347 PG7_IOR_IN, PG7_IOR_OUT,
348 PG6_IOR_IN, PG6_IOR_OUT,
349 PG5_IOR_IN, PG5_IOR_OUT,
350 PG4_IOR_IN, PG4_IOR_OUT,
351 PG3_IOR_IN, PG3_IOR_OUT,
352 PG2_IOR_IN, PG2_IOR_OUT,
353 PG1_IOR_IN, PG1_IOR_OUT,
354 PG0_IOR_IN, PG0_IOR_OUT,
355
356 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
357 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11,
358 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11,
359 PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11,
360 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
361 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
362 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
363 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
364 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
365 PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
366 PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
367 PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111,
368 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
369 PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111,
370 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
371 PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111,
372 PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011,
373 PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111,
374 PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011,
375 PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111,
376 PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011,
377 PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111,
378 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
379 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
380 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
381 PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
382 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
383 PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
384 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
385 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
386 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11,
387 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11,
388 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11,
389 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11,
390 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11,
391 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11,
392 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11,
393 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
394 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
395
396 /* Port H */
397 PH7MD_0, PH7MD_1,
398 PH6MD_0, PH6MD_1,
399 PH5MD_0, PH5MD_1,
400 PH4MD_0, PH4MD_1,
401 PH3MD_0, PH3MD_1,
402 PH2MD_0, PH2MD_1,
403 PH1MD_0, PH1MD_1,
404 PH0MD_0, PH0MD_1,
405
406 /* Port I - not on device */
407
408 /* Port J */
409 PJ11_IOR_IN, PJ11_IOR_OUT,
410 PJ10_IOR_IN, PJ10_IOR_OUT,
411 PJ9_IOR_IN, PJ9_IOR_OUT,
412 PJ8_IOR_IN, PJ8_IOR_OUT,
413 PJ7_IOR_IN, PJ7_IOR_OUT,
414 PJ6_IOR_IN, PJ6_IOR_OUT,
415 PJ5_IOR_IN, PJ5_IOR_OUT,
416 PJ4_IOR_IN, PJ4_IOR_OUT,
417 PJ3_IOR_IN, PJ3_IOR_OUT,
418 PJ2_IOR_IN, PJ2_IOR_OUT,
419 PJ1_IOR_IN, PJ1_IOR_OUT,
420 PJ0_IOR_IN, PJ0_IOR_OUT,
421
422 PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11,
423 PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11,
424 PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11,
425 PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11,
426 PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11,
427 PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11,
428 PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11,
429 PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11,
430 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11,
431 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
432 PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
433 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
434 PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
435 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
436 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
437
438 /* Port K */
439 PK11_IOR_IN, PK11_IOR_OUT,
440 PK10_IOR_IN, PK10_IOR_OUT,
441 PK9_IOR_IN, PK9_IOR_OUT,
442 PK8_IOR_IN, PK8_IOR_OUT,
443 PK7_IOR_IN, PK7_IOR_OUT,
444 PK6_IOR_IN, PK6_IOR_OUT,
445 PK5_IOR_IN, PK5_IOR_OUT,
446 PK4_IOR_IN, PK4_IOR_OUT,
447 PK3_IOR_IN, PK3_IOR_OUT,
448 PK2_IOR_IN, PK2_IOR_OUT,
449 PK1_IOR_IN, PK1_IOR_OUT,
450 PK0_IOR_IN, PK0_IOR_OUT,
451
452 PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11,
453 PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11,
454 PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11,
455 PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11,
456 PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11,
457 PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11,
458 PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11,
459 PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11,
460 PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11,
461 PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11,
462 PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11,
463 PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11,
464 PINMUX_FUNCTION_END,
465
466 PINMUX_MARK_BEGIN,
467 /* Port A */
468
469 /* Port B */
470
471 /* Port C */
472
473 /* Port D */
474
475 /* Port E */
476
477 /* Port F */
478
479 /* Port G */
480
481 /* Port H */
482 PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
483 PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
484
485 /* Port I - not on device */
486
487 /* Port J */
488
489 /* Port K */
490
491 IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK,
492 IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
493 IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
494
495 PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
496 PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
497
498 SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
499 SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
500 CRX0_MARK, CRX1_MARK,
501 CTX0_MARK, CTX1_MARK,
502
503 PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
504 PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
505 PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
506 PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
507 IERXD_MARK, IETXD_MARK,
508 CRX0CRX1_MARK,
509 WDTOVF_MARK,
510
511 CRX0X1_MARK,
512
513 /* DMAC */
514 TEND0_MARK, DACK0_MARK, DREQ0_MARK,
515 TEND1_MARK, DACK1_MARK, DREQ1_MARK,
516
517 /* ADC */
518 ADTRG_MARK,
519
520 /* BSC */
521 A25_MARK, A24_MARK,
522 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
523 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
524 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
525 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
526 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
527 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
528 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
529 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
530 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
531 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
532 BS_MARK,
533 CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
534 CS6CE1B_MARK, CS5CE1A_MARK,
535 CE2A_MARK, CE2B_MARK,
536 RD_MARK, RDWR_MARK,
537 ICIOWRAH_MARK,
538 ICIORD_MARK,
539 WE1DQMUWE_MARK,
540 WE0DQML_MARK,
541 RAS_MARK, CAS_MARK, CKE_MARK,
542 WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
543
544 /* TMU */
545 TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
546 TIOC1A_MARK, TIOC1B_MARK,
547 TIOC2A_MARK, TIOC2B_MARK,
548 TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
549 TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
550 TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
551
552 /* SCIF */
553 SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK,
554 RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK,
555 TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK,
556 RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK,
557 TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK,
558 RTS1_MARK, RTS3_MARK,
559 CTS1_MARK, CTS3_MARK,
560
561 /* RSPI */
562 RSPCK0_MARK, RSPCK1_MARK,
563 MOSI0_MARK, MOSI1_MARK,
564 MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK,
565 SSL00_MARK, SSL10_MARK,
566
567 /* IIC3 */
568 SCL0_MARK, SCL1_MARK, SCL2_MARK,
569 SDA0_MARK, SDA1_MARK, SDA2_MARK,
570
571 /* SSI */
572 SSISCK0_MARK,
573 SSIWS0_MARK,
574 SSITXD0_MARK,
575 SSIRXD0_MARK,
576 SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK,
577 SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK,
578 SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK,
579 AUDIO_CLK_MARK,
580
581 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
582 SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
583
584 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
585 SPDIF_IN_MARK, SPDIF_OUT_MARK,
586
587 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
588 FCE_MARK,
589 FRB_MARK,
590
591 /* VDC3 */
592 DV_CLK_MARK,
593 DV_VSYNC_MARK, DV_HSYNC_MARK,
594 DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
595 DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
596 LCD_CLK_MARK, LCD_EXTCLK_MARK,
597 LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
598 LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
599 LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
600 LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
601 LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
602 LCD_M_DISP_MARK,
603 PINMUX_MARK_END,
604};
605
606static pinmux_enum_t pinmux_data[] = {
607
608 /* Port A */
609 PINMUX_DATA(PA3_DATA, PA3_IN),
610 PINMUX_DATA(PA2_DATA, PA2_IN),
611 PINMUX_DATA(PA1_DATA, PA1_IN),
612 PINMUX_DATA(PA0_DATA, PA0_IN),
613
614 /* Port B */
615 PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT),
616 PINMUX_DATA(A22_MARK, PB22MD_01),
617 PINMUX_DATA(CS4_MARK, PB22MD_10),
618
619 PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT),
620 PINMUX_DATA(A21_MARK, PB21MD_1),
621 PINMUX_DATA(A20_MARK, PB20MD_1),
622 PINMUX_DATA(A19_MARK, PB19MD_01),
623 PINMUX_DATA(A18_MARK, PB18MD_01),
624 PINMUX_DATA(A17_MARK, PB17MD_01),
625 PINMUX_DATA(A16_MARK, PB16MD_01),
626 PINMUX_DATA(A15_MARK, PB15MD_01),
627 PINMUX_DATA(A14_MARK, PB14MD_01),
628 PINMUX_DATA(A13_MARK, PB13MD_01),
629 PINMUX_DATA(A12_MARK, PB12MD_01),
630 PINMUX_DATA(A11_MARK, PB11MD_01),
631 PINMUX_DATA(A10_MARK, PB10MD_01),
632 PINMUX_DATA(A9_MARK, PB9MD_01),
633 PINMUX_DATA(A8_MARK, PB8MD_01),
634 PINMUX_DATA(A7_MARK, PB7MD_01),
635 PINMUX_DATA(A6_MARK, PB6MD_01),
636 PINMUX_DATA(A5_MARK, PB5MD_01),
637 PINMUX_DATA(A4_MARK, PB4MD_01),
638 PINMUX_DATA(A3_MARK, PB3MD_1),
639 PINMUX_DATA(A2_MARK, PB2MD_1),
640 PINMUX_DATA(A1_MARK, PB1MD_1),
641
642 /* Port C */
643 PINMUX_DATA(PC10_DATA, PC10MD_0),
644 PINMUX_DATA(TIOC2B_MARK, PC1MD_1),
645 PINMUX_DATA(PC9_DATA, PC9MD_0),
646 PINMUX_DATA(TIOC2A_MARK, PC9MD_1),
647 PINMUX_DATA(PC8_DATA, PC8MD_00),
648 PINMUX_DATA(CS3_MARK, PC8MD_01),
649 PINMUX_DATA(TIOC4D_MARK, PC8MD_10),
650 PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11),
651 PINMUX_DATA(PC7_DATA, PC7MD_00),
652 PINMUX_DATA(CKE_MARK, PC7MD_01),
653 PINMUX_DATA(TIOC4C_MARK, PC7MD_10),
654 PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11),
655 PINMUX_DATA(PC6_DATA, PC6MD_00),
656 PINMUX_DATA(CAS_MARK, PC6MD_01),
657 PINMUX_DATA(TIOC4B_MARK, PC6MD_10),
658 PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11),
659 PINMUX_DATA(PC5_DATA, PC5MD_00),
660 PINMUX_DATA(RAS_MARK, PC5MD_01),
661 PINMUX_DATA(TIOC4A_MARK, PC5MD_10),
662 PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11),
663 PINMUX_DATA(PC4_DATA, PC4MD_0),
664 PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1),
665 PINMUX_DATA(PC3_DATA, PC3MD_0),
666 PINMUX_DATA(WE0DQML_MARK, PC3MD_1),
667 PINMUX_DATA(PC2_DATA, PC2MD_0),
668 PINMUX_DATA(RDWR_MARK, PC2MD_1),
669 PINMUX_DATA(PC1_DATA, PC1MD_0),
670 PINMUX_DATA(RD_MARK, PC1MD_1),
671 PINMUX_DATA(PC0_DATA, PC0MD_0),
672 PINMUX_DATA(CS0_MARK, PC0MD_1),
673
674 /* Port D */
675 PINMUX_DATA(D15_MARK, PD15MD_01),
676 PINMUX_DATA(D14_MARK, PD14MD_01),
677 PINMUX_DATA(D13_MARK, PD13MD_01),
678 PINMUX_DATA(D12_MARK, PD12MD_01),
679 PINMUX_DATA(D11_MARK, PD11MD_01),
680 PINMUX_DATA(D10_MARK, PD10MD_01),
681 PINMUX_DATA(D9_MARK, PD9MD_01),
682 PINMUX_DATA(D8_MARK, PD8MD_01),
683 PINMUX_DATA(D7_MARK, PD7MD_01),
684 PINMUX_DATA(D6_MARK, PD6MD_01),
685 PINMUX_DATA(D5_MARK, PD5MD_01),
686 PINMUX_DATA(D4_MARK, PD4MD_01),
687 PINMUX_DATA(D3_MARK, PD3MD_01),
688 PINMUX_DATA(D2_MARK, PD2MD_01),
689 PINMUX_DATA(D1_MARK, PD1MD_01),
690 PINMUX_DATA(D0_MARK, PD0MD_01),
691
692 /* Port E */
693 PINMUX_DATA(PE5_DATA, PE5MD_00),
694 PINMUX_DATA(SDA2_MARK, PE5MD_01),
695 PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
696
697 PINMUX_DATA(PE4_DATA, PE4MD_00),
698 PINMUX_DATA(SCL2_MARK, PE4MD_01),
699 PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
700
701 PINMUX_DATA(PE3_DATA, PE3MD_00),
702 PINMUX_DATA(SDA1_MARK, PE3MD_01),
703 PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11),
704
705 PINMUX_DATA(PE2_DATA, PE2MD_00),
706 PINMUX_DATA(SCL1_MARK, PE2MD_01),
707 PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11),
708
709 PINMUX_DATA(PE1_DATA, PE1MD_000),
710 PINMUX_DATA(SDA0_MARK, PE1MD_001),
711 PINMUX_DATA(IOIS16_MARK, PE1MD_010),
712 PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011),
713 PINMUX_DATA(TCLKA_MARK, PE1MD_100),
714 PINMUX_DATA(ADTRG_MARK, PE1MD_101),
715
716 PINMUX_DATA(PE0_DATA, PE0MD_00),
717 PINMUX_DATA(SCL0_MARK, PE0MD_01),
718 PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10),
719 PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11),
720
721 /* Port F */
722 PINMUX_DATA(PF12_DATA, PF12MD_000),
723 PINMUX_DATA(BS_MARK, PF12MD_001),
724 PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011),
725 PINMUX_DATA(TIOC3D_MARK, PF12MD_100),
726 PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101),
727
728 PINMUX_DATA(PF11_DATA, PF11MD_000),
729 PINMUX_DATA(A25_MARK, PF11MD_001),
730 PINMUX_DATA(SSIDATA3_MARK, PF11MD_010),
731 PINMUX_DATA(MOSI0_MARK, PF11MD_011),
732 PINMUX_DATA(TIOC3C_MARK, PF11MD_100),
733 PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101),
734
735 PINMUX_DATA(PF10_DATA, PF10MD_000),
736 PINMUX_DATA(A24_MARK, PF10MD_001),
737 PINMUX_DATA(SSIWS3_MARK, PF10MD_010),
738 PINMUX_DATA(SSL00_MARK, PF10MD_011),
739 PINMUX_DATA(TIOC3B_MARK, PF10MD_100),
740 PINMUX_DATA(FCE_MARK, PF10MD_101),
741
742 PINMUX_DATA(PF9_DATA, PF9MD_000),
743 PINMUX_DATA(A23_MARK, PF9MD_001),
744 PINMUX_DATA(SSISCK3_MARK, PF9MD_010),
745 PINMUX_DATA(RSPCK0_MARK, PF9MD_011),
746 PINMUX_DATA(TIOC3A_MARK, PF9MD_100),
747 PINMUX_DATA(FRB_MARK, PF9MD_101),
748
749 PINMUX_DATA(PF8_DATA, PF8MD_00),
750 PINMUX_DATA(CE2B_MARK, PF8MD_01),
751 PINMUX_DATA(SSIDATA3_MARK, PF8MD_10),
752 PINMUX_DATA(DV_CLK_MARK, PF8MD_11),
753
754 PINMUX_DATA(PF7_DATA, PF7MD_000),
755 PINMUX_DATA(CE2A_MARK, PF7MD_001),
756 PINMUX_DATA(SSIWS3_MARK, PF7MD_010),
757 PINMUX_DATA(DV_DATA7_MARK, PF7MD_011),
758 PINMUX_DATA(TCLKD_MARK, PF7MD_100),
759
760 PINMUX_DATA(PF6_DATA, PF6MD_000),
761 PINMUX_DATA(CS6CE1B_MARK, PF6MD_001),
762 PINMUX_DATA(SSISCK3_MARK, PF6MD_010),
763 PINMUX_DATA(DV_DATA6_MARK, PF6MD_011),
764 PINMUX_DATA(TCLKB_MARK, PF6MD_100),
765
766 PINMUX_DATA(PF5_DATA, PF5MD_000),
767 PINMUX_DATA(CS5CE1A_MARK, PF5MD_001),
768 PINMUX_DATA(SSIDATA2_MARK, PF5MD_010),
769 PINMUX_DATA(DV_DATA5_MARK, PF5MD_011),
770 PINMUX_DATA(TCLKC_MARK, PF5MD_100),
771
772 PINMUX_DATA(PF4_DATA, PF4MD_000),
773 PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001),
774 PINMUX_DATA(SSIWS2_MARK, PF4MD_010),
775 PINMUX_DATA(DV_DATA4_MARK, PF4MD_011),
776 PINMUX_DATA(TXD3_MARK, PF4MD_100),
777
778 PINMUX_DATA(PF3_DATA, PF3MD_000),
779 PINMUX_DATA(ICIORD_MARK, PF3MD_001),
780 PINMUX_DATA(SSISCK2_MARK, PF3MD_010),
781 PINMUX_DATA(DV_DATA3_MARK, PF3MD_011),
782 PINMUX_DATA(RXD3_MARK, PF3MD_100),
783
784 PINMUX_DATA(PF2_DATA, PF2MD_000),
785 PINMUX_DATA(BACK_MARK, PF2MD_001),
786 PINMUX_DATA(SSIDATA1_MARK, PF2MD_010),
787 PINMUX_DATA(DV_DATA2_MARK, PF2MD_011),
788 PINMUX_DATA(TXD2_MARK, PF2MD_100),
789 PINMUX_DATA(DACK0_MARK, PF2MD_101),
790
791 PINMUX_DATA(PF1_DATA, PF1MD_000),
792 PINMUX_DATA(BREQ_MARK, PF1MD_001),
793 PINMUX_DATA(SSIWS1_MARK, PF1MD_010),
794 PINMUX_DATA(DV_DATA1_MARK, PF1MD_011),
795 PINMUX_DATA(RXD2_MARK, PF1MD_100),
796 PINMUX_DATA(DREQ0_MARK, PF1MD_101),
797
798 PINMUX_DATA(PF0_DATA, PF0MD_000),
799 PINMUX_DATA(WAIT_MARK, PF0MD_001),
800 PINMUX_DATA(SSISCK1_MARK, PF0MD_010),
801 PINMUX_DATA(DV_DATA0_MARK, PF0MD_011),
802 PINMUX_DATA(SCK2_MARK, PF0MD_100),
803 PINMUX_DATA(TEND0_MARK, PF0MD_101),
804
805 /* Port G */
806 PINMUX_DATA(PG24_DATA, PG24MD_00),
807 PINMUX_DATA(MOSI0_MARK, PG24MD_01),
808 PINMUX_DATA(TIOC0D_MARK, PG24MD_10),
809
810 PINMUX_DATA(PG23_DATA, PG23MD_00),
811 PINMUX_DATA(MOSI1_MARK, PG23MD_01),
812 PINMUX_DATA(TIOC0C_MARK, PG23MD_10),
813
814 PINMUX_DATA(PG22_DATA, PG22MD_00),
815 PINMUX_DATA(SSL10_MARK, PG22MD_01),
816 PINMUX_DATA(TIOC0B_MARK, PG22MD_10),
817
818 PINMUX_DATA(PG21_DATA, PG21MD_00),
819 PINMUX_DATA(RSPCK1_MARK, PG21MD_01),
820 PINMUX_DATA(TIOC0A_MARK, PG21MD_10),
821
822 PINMUX_DATA(PG20_DATA, PG20MD_000),
823 PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001),
824 PINMUX_DATA(MISO1_MARK, PG20MD_011),
825 PINMUX_DATA(TXD7_MARK, PG20MD_100),
826
827 PINMUX_DATA(PG19_DATA, PG19MD_000),
828 PINMUX_DATA(LCD_CLK_MARK, PG19MD_001),
829 PINMUX_DATA(TIOC2B_MARK, PG19MD_010),
830 PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011),
831 PINMUX_DATA(RXD7_MARK, PG19MD_100),
832
833 PINMUX_DATA(PG18_DATA, PG18MD_000),
834 PINMUX_DATA(LCD_DE_MARK, PG18MD_001),
835 PINMUX_DATA(TIOC2A_MARK, PG18MD_010),
836 PINMUX_DATA(SSL10_MARK, PG18MD_011),
837 PINMUX_DATA(TXD6_MARK, PG18MD_100),
838
839 PINMUX_DATA(PG17_DATA, PG17MD_000),
840 PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001),
841 PINMUX_DATA(TIOC1B_MARK, PG17MD_010),
842 PINMUX_DATA(RSPCK1_MARK, PG17MD_011),
843 PINMUX_DATA(RXD6_MARK, PG17MD_100),
844
845 PINMUX_DATA(PG16_DATA, PG16MD_000),
846 PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001),
847 PINMUX_DATA(TIOC1A_MARK, PG16MD_010),
848 PINMUX_DATA(TXD3_MARK, PG16MD_011),
849 PINMUX_DATA(CTS1_MARK, PG16MD_100),
850
851 PINMUX_DATA(PG15_DATA, PG15MD_000),
852 PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001),
853 PINMUX_DATA(TIOC0D_MARK, PG15MD_010),
854 PINMUX_DATA(RXD3_MARK, PG15MD_011),
855 PINMUX_DATA(RTS1_MARK, PG15MD_100),
856
857 PINMUX_DATA(PG14_DATA, PG14MD_000),
858 PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001),
859 PINMUX_DATA(TIOC0C_MARK, PG14MD_010),
860 PINMUX_DATA(SCK1_MARK, PG14MD_100),
861
862 PINMUX_DATA(PG13_DATA, PG13MD_000),
863 PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001),
864 PINMUX_DATA(TIOC0B_MARK, PG13MD_010),
865 PINMUX_DATA(TXD1_MARK, PG13MD_100),
866
867 PINMUX_DATA(PG12_DATA, PG12MD_000),
868 PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001),
869 PINMUX_DATA(TIOC0A_MARK, PG12MD_010),
870 PINMUX_DATA(RXD1_MARK, PG12MD_100),
871
872 PINMUX_DATA(PG11_DATA, PG11MD_000),
873 PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001),
874 PINMUX_DATA(SSITXD0_MARK, PG11MD_010),
875 PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011),
876 PINMUX_DATA(TXD5_MARK, PG11MD_100),
877 PINMUX_DATA(SIOFTXD_MARK, PG11MD_101),
878
879 PINMUX_DATA(PG10_DATA, PG10MD_000),
880 PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001),
881 PINMUX_DATA(SSIRXD0_MARK, PG10MD_010),
882 PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011),
883 PINMUX_DATA(RXD5_MARK, PG10MD_100),
884 PINMUX_DATA(SIOFRXD_MARK, PG10MD_101),
885
886 PINMUX_DATA(PG9_DATA, PG9MD_000),
887 PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001),
888 PINMUX_DATA(SSIWS0_MARK, PG9MD_010),
889 PINMUX_DATA(TXD4_MARK, PG9MD_100),
890 PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101),
891
892 PINMUX_DATA(PG8_DATA, PG8MD_000),
893 PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001),
894 PINMUX_DATA(SSISCK0_MARK, PG8MD_010),
895 PINMUX_DATA(RXD4_MARK, PG8MD_100),
896 PINMUX_DATA(SIOFSCK_MARK, PG8MD_101),
897
898 PINMUX_DATA(PG7_DATA, PG7MD_00),
899 PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01),
900 PINMUX_DATA(SD_CD_MARK, PG7MD_10),
901 PINMUX_DATA(PINT7_PG_MARK, PG7MD_11),
902
903 PINMUX_DATA(PG6_DATA, PG7MD_00),
904 PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01),
905 PINMUX_DATA(SD_WP_MARK, PG7MD_10),
906 PINMUX_DATA(PINT6_PG_MARK, PG7MD_11),
907
908 PINMUX_DATA(PG5_DATA, PG5MD_00),
909 PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01),
910 PINMUX_DATA(SD_D1_MARK, PG5MD_10),
911 PINMUX_DATA(PINT5_PG_MARK, PG5MD_11),
912
913 PINMUX_DATA(PG4_DATA, PG4MD_00),
914 PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01),
915 PINMUX_DATA(SD_D0_MARK, PG4MD_10),
916 PINMUX_DATA(PINT4_PG_MARK, PG4MD_11),
917
918 PINMUX_DATA(PG3_DATA, PG3MD_00),
919 PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01),
920 PINMUX_DATA(SD_CLK_MARK, PG3MD_10),
921 PINMUX_DATA(PINT3_PG_MARK, PG3MD_11),
922
923 PINMUX_DATA(PG2_DATA, PG2MD_00),
924 PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01),
925 PINMUX_DATA(SD_CMD_MARK, PG2MD_10),
926 PINMUX_DATA(PINT2_PG_MARK, PG2MD_11),
927
928 PINMUX_DATA(PG1_DATA, PG1MD_00),
929 PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01),
930 PINMUX_DATA(SD_D3_MARK, PG1MD_10),
931 PINMUX_DATA(PINT1_PG_MARK, PG1MD_11),
932
933 PINMUX_DATA(PG0_DATA, PG0MD_000),
934 PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001),
935 PINMUX_DATA(SD_D2_MARK, PG0MD_010),
936 PINMUX_DATA(PINT0_PG_MARK, PG0MD_011),
937 PINMUX_DATA(WDTOVF_MARK, PG0MD_100),
938
939 /* Port H */
940 PINMUX_DATA(PH7_DATA, PH7MD_0),
941 PINMUX_DATA(PHAN7_MARK, PH7MD_1),
942
943 PINMUX_DATA(PH6_DATA, PH6MD_0),
944 PINMUX_DATA(PHAN6_MARK, PH6MD_1),
945
946 PINMUX_DATA(PH5_DATA, PH5MD_0),
947 PINMUX_DATA(PHAN5_MARK, PH5MD_1),
948
949 PINMUX_DATA(PH4_DATA, PH4MD_0),
950 PINMUX_DATA(PHAN4_MARK, PH4MD_1),
951
952 PINMUX_DATA(PH3_DATA, PH3MD_0),
953 PINMUX_DATA(PHAN3_MARK, PH3MD_1),
954
955 PINMUX_DATA(PH2_DATA, PH2MD_0),
956 PINMUX_DATA(PHAN2_MARK, PH2MD_1),
957
958 PINMUX_DATA(PH1_DATA, PH1MD_0),
959 PINMUX_DATA(PHAN1_MARK, PH1MD_1),
960
961 PINMUX_DATA(PH0_DATA, PH0MD_0),
962 PINMUX_DATA(PHAN0_MARK, PH0MD_1),
963
964 /* Port I - not on device */
965
966 /* Port J */
967 PINMUX_DATA(PJ11_DATA, PJ11MD_00),
968 PINMUX_DATA(PWM2H_MARK, PJ11MD_01),
969 PINMUX_DATA(DACK1_MARK, PJ11MD_10),
970
971 PINMUX_DATA(PJ10_DATA, PJ10MD_00),
972 PINMUX_DATA(PWM2G_MARK, PJ10MD_01),
973 PINMUX_DATA(DREQ1_MARK, PJ10MD_10),
974
975 PINMUX_DATA(PJ9_DATA, PJ9MD_00),
976 PINMUX_DATA(PWM2F_MARK, PJ9MD_01),
977 PINMUX_DATA(TEND1_MARK, PJ9MD_10),
978
979 PINMUX_DATA(PJ8_DATA, PJ8MD_00),
980 PINMUX_DATA(PWM2E_MARK, PJ8MD_01),
981 PINMUX_DATA(RTS3_MARK, PJ8MD_10),
982
983 PINMUX_DATA(PJ7_DATA, PJ7MD_00),
984 PINMUX_DATA(TIOC1B_MARK, PJ7MD_01),
985 PINMUX_DATA(CTS3_MARK, PJ7MD_10),
986
987 PINMUX_DATA(PJ6_DATA, PJ6MD_00),
988 PINMUX_DATA(TIOC1A_MARK, PJ6MD_01),
989 PINMUX_DATA(SCK3_MARK, PJ6MD_10),
990
991 PINMUX_DATA(PJ5_DATA, PJ5MD_00),
992 PINMUX_DATA(IERXD_MARK, PJ5MD_01),
993 PINMUX_DATA(TXD3_MARK, PJ5MD_10),
994
995 PINMUX_DATA(PJ4_DATA, PJ4MD_00),
996 PINMUX_DATA(IETXD_MARK, PJ4MD_01),
997 PINMUX_DATA(RXD3_MARK, PJ4MD_10),
998
999 PINMUX_DATA(PJ3_DATA, PJ3MD_00),
1000 PINMUX_DATA(CRX1_MARK, PJ3MD_01),
1001 PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
1002 PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
1003
1004 PINMUX_DATA(PJ2_DATA, PJ2MD_000),
1005 PINMUX_DATA(CTX1_MARK, PJ2MD_001),
1006 PINMUX_DATA(CRX0CRX1_MARK, PJ2MD_010),
1007 PINMUX_DATA(CS2_MARK, PJ2MD_011),
1008 PINMUX_DATA(SCK0_MARK, PJ2MD_100),
1009 PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
1010
1011 PINMUX_DATA(PJ1_DATA, PJ1MD_000),
1012 PINMUX_DATA(CRX0_MARK, PJ1MD_001),
1013 PINMUX_DATA(IERXD_MARK, PJ1MD_010),
1014 PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011),
1015 PINMUX_DATA(RXD0_MARK, PJ1MD_100),
1016
1017 PINMUX_DATA(PJ0_DATA, PJ0MD_000),
1018 PINMUX_DATA(CTX0_MARK, PJ0MD_001),
1019 PINMUX_DATA(IERXD_MARK, PJ0MD_010),
1020 PINMUX_DATA(CS1_MARK, PJ0MD_011),
1021 PINMUX_DATA(TXD0_MARK, PJ0MD_100),
1022 PINMUX_DATA(A0_MARK, PJ0MD_101),
1023
1024 /* Port K */
1025 PINMUX_DATA(PK11_DATA, PK11MD_00),
1026 PINMUX_DATA(PWM2D_MARK, PK11MD_01),
1027 PINMUX_DATA(SSITXD0_MARK, PK11MD_10),
1028
1029 PINMUX_DATA(PK10_DATA, PK10MD_00),
1030 PINMUX_DATA(PWM2C_MARK, PK10MD_01),
1031 PINMUX_DATA(SSIRXD0_MARK, PK10MD_10),
1032
1033 PINMUX_DATA(PK9_DATA, PK9MD_00),
1034 PINMUX_DATA(PWM2B_MARK, PK9MD_01),
1035 PINMUX_DATA(SSIWS0_MARK, PK9MD_10),
1036
1037 PINMUX_DATA(PK8_DATA, PK8MD_00),
1038 PINMUX_DATA(PWM2A_MARK, PK8MD_01),
1039 PINMUX_DATA(SSISCK0_MARK, PK8MD_10),
1040
1041 PINMUX_DATA(PK7_DATA, PK7MD_00),
1042 PINMUX_DATA(PWM1H_MARK, PK7MD_01),
1043 PINMUX_DATA(SD_CD_MARK, PK7MD_10),
1044
1045 PINMUX_DATA(PK6_DATA, PK6MD_00),
1046 PINMUX_DATA(PWM1G_MARK, PK6MD_01),
1047 PINMUX_DATA(SD_WP_MARK, PK6MD_10),
1048
1049 PINMUX_DATA(PK5_DATA, PK5MD_00),
1050 PINMUX_DATA(PWM1F_MARK, PK5MD_01),
1051 PINMUX_DATA(SD_D1_MARK, PK5MD_10),
1052
1053 PINMUX_DATA(PK4_DATA, PK4MD_00),
1054 PINMUX_DATA(PWM1E_MARK, PK4MD_01),
1055 PINMUX_DATA(SD_D0_MARK, PK4MD_10),
1056
1057 PINMUX_DATA(PK3_DATA, PK3MD_00),
1058 PINMUX_DATA(PWM1D_MARK, PK3MD_01),
1059 PINMUX_DATA(SD_CLK_MARK, PK3MD_10),
1060
1061 PINMUX_DATA(PK2_DATA, PK2MD_00),
1062 PINMUX_DATA(PWM1C_MARK, PK2MD_01),
1063 PINMUX_DATA(SD_CMD_MARK, PK2MD_10),
1064
1065 PINMUX_DATA(PK1_DATA, PK1MD_00),
1066 PINMUX_DATA(PWM1B_MARK, PK1MD_01),
1067 PINMUX_DATA(SD_D3_MARK, PK1MD_10),
1068
1069 PINMUX_DATA(PK0_DATA, PK0MD_00),
1070 PINMUX_DATA(PWM1A_MARK, PK0MD_01),
1071 PINMUX_DATA(SD_D2_MARK, PK0MD_10),
1072};
1073
1074static struct pinmux_gpio pinmux_gpios[] = {
1075
1076 /* Port A */
1077 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
1078 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
1079 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
1080 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
1081
1082 /* Port B */
1083 PINMUX_GPIO(GPIO_PB22, PB22_DATA),
1084 PINMUX_GPIO(GPIO_PB21, PB21_DATA),
1085 PINMUX_GPIO(GPIO_PB20, PB20_DATA),
1086 PINMUX_GPIO(GPIO_PB19, PB19_DATA),
1087 PINMUX_GPIO(GPIO_PB18, PB18_DATA),
1088 PINMUX_GPIO(GPIO_PB17, PB17_DATA),
1089 PINMUX_GPIO(GPIO_PB16, PB16_DATA),
1090 PINMUX_GPIO(GPIO_PB15, PB15_DATA),
1091 PINMUX_GPIO(GPIO_PB14, PB14_DATA),
1092 PINMUX_GPIO(GPIO_PB13, PB13_DATA),
1093 PINMUX_GPIO(GPIO_PB12, PB12_DATA),
1094 PINMUX_GPIO(GPIO_PB11, PB11_DATA),
1095 PINMUX_GPIO(GPIO_PB10, PB10_DATA),
1096 PINMUX_GPIO(GPIO_PB9, PB9_DATA),
1097 PINMUX_GPIO(GPIO_PB8, PB8_DATA),
1098 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
1099 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
1100 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
1101 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
1102 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
1103 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
1104 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
1105
1106 /* Port C */
1107 PINMUX_GPIO(GPIO_PC10, PC10_DATA),
1108 PINMUX_GPIO(GPIO_PC9, PC9_DATA),
1109 PINMUX_GPIO(GPIO_PC8, PC8_DATA),
1110 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
1111 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
1112 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
1113 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
1114 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
1115 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
1116 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
1117 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
1118
1119 /* Port D */
1120 PINMUX_GPIO(GPIO_PD15, PD15_DATA),
1121 PINMUX_GPIO(GPIO_PD14, PD14_DATA),
1122 PINMUX_GPIO(GPIO_PD13, PD13_DATA),
1123 PINMUX_GPIO(GPIO_PD12, PD12_DATA),
1124 PINMUX_GPIO(GPIO_PD11, PD11_DATA),
1125 PINMUX_GPIO(GPIO_PD10, PD10_DATA),
1126 PINMUX_GPIO(GPIO_PD9, PD9_DATA),
1127 PINMUX_GPIO(GPIO_PD8, PD8_DATA),
1128 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
1129 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
1130 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
1131 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
1132 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
1133 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
1134 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
1135 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
1136
1137 /* Port E */
1138 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
1139 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
1140 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
1141 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
1142 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
1143 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
1144
1145 /* Port F */
1146 PINMUX_GPIO(GPIO_PF12, PF12_DATA),
1147 PINMUX_GPIO(GPIO_PF11, PF11_DATA),
1148 PINMUX_GPIO(GPIO_PF10, PF10_DATA),
1149 PINMUX_GPIO(GPIO_PF9, PF9_DATA),
1150 PINMUX_GPIO(GPIO_PF8, PF8_DATA),
1151 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
1152 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
1153 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
1154 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
1155 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
1156 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
1157 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
1158 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
1159
1160 /* Port G */
1161 PINMUX_GPIO(GPIO_PG24, PG24_DATA),
1162 PINMUX_GPIO(GPIO_PG23, PG23_DATA),
1163 PINMUX_GPIO(GPIO_PG22, PG22_DATA),
1164 PINMUX_GPIO(GPIO_PG21, PG21_DATA),
1165 PINMUX_GPIO(GPIO_PG20, PG20_DATA),
1166 PINMUX_GPIO(GPIO_PG19, PG19_DATA),
1167 PINMUX_GPIO(GPIO_PG18, PG18_DATA),
1168 PINMUX_GPIO(GPIO_PG17, PG17_DATA),
1169 PINMUX_GPIO(GPIO_PG16, PG16_DATA),
1170 PINMUX_GPIO(GPIO_PG15, PG15_DATA),
1171 PINMUX_GPIO(GPIO_PG14, PG14_DATA),
1172 PINMUX_GPIO(GPIO_PG13, PG13_DATA),
1173 PINMUX_GPIO(GPIO_PG12, PG12_DATA),
1174 PINMUX_GPIO(GPIO_PG11, PG11_DATA),
1175 PINMUX_GPIO(GPIO_PG10, PG10_DATA),
1176 PINMUX_GPIO(GPIO_PG9, PG9_DATA),
1177 PINMUX_GPIO(GPIO_PG8, PG8_DATA),
1178 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
1179 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
1180 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
1181 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
1182 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
1183 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
1184 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
1185 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
1186
1187 /* Port H - Port H does not have a Data Register */
1188
1189 /* Port I - not on device */
1190
1191 /* Port J */
1192 PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
1193 PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
1194 PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
1195 PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
1196 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
1197 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
1198 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
1199 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
1200 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
1201 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
1202 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
1203 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
1204
1205 /* Port K */
1206 PINMUX_GPIO(GPIO_PK11, PK11_DATA),
1207 PINMUX_GPIO(GPIO_PK10, PK10_DATA),
1208 PINMUX_GPIO(GPIO_PK9, PK9_DATA),
1209 PINMUX_GPIO(GPIO_PK8, PK8_DATA),
1210 PINMUX_GPIO(GPIO_PK7, PK7_DATA),
1211 PINMUX_GPIO(GPIO_PK6, PK6_DATA),
1212 PINMUX_GPIO(GPIO_PK5, PK5_DATA),
1213 PINMUX_GPIO(GPIO_PK4, PK4_DATA),
1214 PINMUX_GPIO(GPIO_PK3, PK3_DATA),
1215 PINMUX_GPIO(GPIO_PK2, PK2_DATA),
1216 PINMUX_GPIO(GPIO_PK1, PK1_DATA),
1217 PINMUX_GPIO(GPIO_PK0, PK0_DATA),
1218
1219 /* INTC */
1220 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
1221 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
1222 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
1223 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
1224 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
1225 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
1226 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
1227
1228 PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
1229 PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
1230 PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
1231 PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
1232 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
1233 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
1234 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
1235 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
1236 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
1237 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
1238 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
1239 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
1240
1241 /* WDT */
1242 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1243
1244 /* CAN */
1245 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
1246 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
1247 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
1248 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
1249 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK),
1250
1251 /* DMAC */
1252 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1253 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1254 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1255 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1256 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1257 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1258
1259 /* ADC */
1260 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
1261
1262 /* BSCh */
1263 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1264 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1265 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1266 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1267 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1268 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1269 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1270 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1271 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1272 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1273 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1274 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1275 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1276 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1277 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1278 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1279 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1280 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1281 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1282 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1283 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1284 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1285 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1286 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1287 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1288 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1289
1290 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1291 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1292 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1293 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1294 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1295 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1296 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1297 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1298 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1299 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1300 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1301 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1302 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1303 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1304 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1305 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1306
1307 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1308 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1309 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
1310 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
1311 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
1312 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1313 PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
1314 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
1315 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
1316 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
1317 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1318 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1319 PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
1320 PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
1321 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
1322 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
1323 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
1324 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
1325 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
1326 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1327 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
1328 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
1329 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1330
1331 /* TMU */
1332 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
1333 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
1334 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
1335 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
1336 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
1337 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
1338 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
1339 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
1340 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
1341 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
1342 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
1343 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
1344 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
1345 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
1346 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
1347 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
1348 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
1349 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
1350 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
1351 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
1352
1353 /* SCIF */
1354 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
1355 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
1356 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
1357 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
1358 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
1359 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
1360 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1361 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1362 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1363 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1364 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1365 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1366 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1367 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1368 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1369 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1370 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
1371 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
1372 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
1373 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
1374 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
1375 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
1377 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
1378
1379 /* RSPI */
1380 PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
1381 PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
1382 PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
1383 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
1384 PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
1385 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
1386 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
1387 PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
1388 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
1389
1390 /* IIC3 */
1391 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1392 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1393 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1394 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1395 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1396 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1397
1398 /* SSI */
1399 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
1400 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
1401 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
1402 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
1403 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
1404 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
1405 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
1406 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
1407 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
1408 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
1409 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
1410 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
1411 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
1412 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
1413
1414 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1415 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
1416 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
1417 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
1418 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
1419
1420 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1421 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
1422 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
1423
1424 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1425 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1426 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1427
1428 /* VDC3 */
1429 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1430 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1431 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1432
1433 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
1434 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
1435 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
1436 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
1437 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
1438 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
1439 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
1440 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
1441
1442 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
1443 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
1444 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
1445 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
1446 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
1447
1448 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
1449 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
1450 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
1451 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
1452 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
1453 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
1454 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
1455 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
1456 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
1457 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
1458 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
1459 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
1460 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
1461 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
1462 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
1463 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
1464
1465 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
1466};
1467
1468static struct pinmux_cfg_reg pinmux_config_regs[] = {
1469 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1470 0, 0, 0, 0, 0, 0, 0, 0,
1471 0, 0, 0, 0, 0, 0, 0, 0,
1472 0, 0, 0, 0, 0, 0, 0, 0,
1473 PA3_IN, PA3_OUT,
1474 PA2_IN, PA2_OUT,
1475 PA1_IN, PA1_OUT,
1476 PA0_IN, PA0_OUT }
1477 },
1478
1479 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
1480 0, 0, 0, 0, 0, 0, 0, 0,
1481 0, 0, 0, 0, 0, 0, 0, 0,
1482 PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
1483 0, 0, 0, 0, 0, 0, 0, 0,
1484 PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
1485 0, 0, 0, 0, 0, 0, 0, 0,
1486 0, PB20MD_1, 0, 0, 0, 0, 0, 0,
1487 0, 0, 0, 0, 0, 0, 0, 0 }
1488
1489 },
1490 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
1491 0, PB19MD_01, 0, 0, 0, 0, 0, 0,
1492 0, 0, 0, 0, 0, 0, 0, 0,
1493 0, PB18MD_01, 0, 0, 0, 0, 0, 0,
1494 0, 0, 0, 0, 0, 0, 0, 0,
1495 0, PB17MD_01, 0, 0, 0, 0, 0, 0,
1496 0, 0, 0, 0, 0, 0, 0, 0,
1497 0, PB16MD_01, 0, 0, 0, 0, 0, 0,
1498 0, 0, 0, 0, 0, 0, 0, 0 }
1499 },
1500 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
1501 0, PB15MD_01, 0, 0, 0, 0, 0, 0,
1502 0, 0, 0, 0, 0, 0, 0, 0,
1503 0, PB14MD_01, 0, 0, 0, 0, 0, 0,
1504 0, 0, 0, 0, 0, 0, 0, 0,
1505 0, PB13MD_01, 0, 0, 0, 0, 0, 0,
1506 0, 0, 0, 0, 0, 0, 0, 0,
1507 0, PB12MD_01, 0, 0, 0, 0, 0, 0,
1508 0, 0, 0, 0, 0, 0, 0, 0 }
1509 },
1510 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
1511 0, PB11MD_01, 0, 0, 0, 0, 0, 0,
1512 0, 0, 0, 0, 0, 0, 0, 0,
1513 0, PB10MD_01, 0, 0, 0, 0, 0, 0,
1514 0, 0, 0, 0, 0, 0, 0, 0,
1515 0, PB9MD_01, 0, 0, 0, 0, 0, 0,
1516 0, 0, 0, 0, 0, 0, 0, 0,
1517 0, PB8MD_01, 0, 0, 0, 0, 0, 0,
1518 0, 0, 0, 0, 0, 0, 0, 0 }
1519 },
1520 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
1521 0, PB7MD_01, 0, 0, 0, 0, 0, 0,
1522 0, 0, 0, 0, 0, 0, 0, 0,
1523 0, PB6MD_01, 0, 0, 0, 0, 0, 0,
1524 0, 0, 0, 0, 0, 0, 0, 0,
1525 0, PB5MD_01, 0, 0, 0, 0, 0, 0,
1526 0, 0, 0, 0, 0, 0, 0, 0,
1527 0, PB4MD_01, 0, 0, 0, 0, 0, 0,
1528 0, 0, 0, 0, 0, 0, 0, 0 }
1529 },
1530 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
1531 0, PB3MD_1, 0, 0, 0, 0, 0, 0,
1532 0, 0, 0, 0, 0, 0, 0, 0,
1533 0, PB2MD_1, 0, 0, 0, 0, 0, 0,
1534 0, 0, 0, 0, 0, 0, 0, 0,
1535 0, PB1MD_1, 0, 0, 0, 0, 0, 0,
1536 0, 0, 0, 0, 0, 0, 0, 0,
1537 0, 0, 0, 0, 0, 0, 0, 0,
1538 0, 0, 0, 0, 0, 0, 0, 0 }
1539 },
1540
1541 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
1542 0, 0, 0, 0, 0, 0, 0, 0,
1543 0, 0, 0, 0, 0, 0, 0, 0,
1544 0, 0,
1545 PB22_IN, PB22_OUT,
1546 PB21_IN, PB21_OUT,
1547 PB20_IN, PB20_OUT,
1548 PB19_IN, PB19_OUT,
1549 PB18_IN, PB18_OUT,
1550 PB17_IN, PB17_OUT,
1551 PB16_IN, PB16_OUT }
1552 },
1553
1554 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
1555 PB15_IN, PB15_OUT,
1556 PB14_IN, PB14_OUT,
1557 PB13_IN, PB13_OUT,
1558 PB12_IN, PB12_OUT,
1559 PB11_IN, PB11_OUT,
1560 PB10_IN, PB10_OUT,
1561 PB9_IN, PB9_OUT,
1562 PB8_IN, PB8_OUT,
1563 PB7_IN, PB7_OUT,
1564 PB6_IN, PB6_OUT,
1565 PB5_IN, PB5_OUT,
1566 PB4_IN, PB4_OUT,
1567 PB3_IN, PB3_OUT,
1568 PB2_IN, PB2_OUT,
1569 PB1_IN, PB1_OUT,
1570 0, 0 }
1571 },
1572
1573 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
1574 0, 0, 0, 0, 0, 0, 0, 0,
1575 0, 0, 0, 0, 0, 0, 0, 0,
1576 PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
1577 0, 0, 0, 0, 0, 0, 0, 0,
1578 PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
1579 0, 0, 0, 0, 0, 0, 0, 0,
1580 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
1581 0, 0, 0, 0, 0, 0, 0, 0 }
1582 },
1583 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
1584 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
1585 0, 0, 0, 0, 0, 0, 0, 0,
1586 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
1587 0, 0, 0, 0, 0, 0, 0, 0,
1588 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
1589 0, 0, 0, 0, 0, 0, 0, 0,
1590 PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
1591 0, 0, 0, 0, 0, 0, 0, 0 }
1592 },
1593 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
1594 PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0,
1596 PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
1597 0, 0, 0, 0, 0, 0, 0, 0,
1598 PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
1599 0, 0, 0, 0, 0, 0, 0, 0,
1600 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
1601 0, 0, 0, 0, 0, 0, 0, 0 }
1602 },
1603
1604 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1606 PC10_IN, PC10_OUT,
1607 PC9_IN, PC9_OUT,
1608 PC8_IN, PC8_OUT,
1609 PC7_IN, PC7_OUT,
1610 PC6_IN, PC6_OUT,
1611 PC5_IN, PC5_OUT,
1612 PC4_IN, PC4_OUT,
1613 PC3_IN, PC3_OUT,
1614 PC2_IN, PC2_OUT,
1615 PC1_IN, PC1_OUT,
1616 PC0_IN, PC0_OUT
1617 }
1618 },
1619
1620 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
1621 0, PD15MD_01, 0, 0, 0, 0, 0, 0,
1622 0, 0, 0, 0, 0, 0, 0, 0,
1623 0, PD14MD_01, 0, 0, 0, 0, 0, 0,
1624 0, 0, 0, 0, 0, 0, 0, 0,
1625 0, PD13MD_01, 0, 0, 0, 0, 0, 0,
1626 0, 0, 0, 0, 0, 0, 0, 0,
1627 0, PD12MD_01, 0, 0, 0, 0, 0, 0,
1628 0, 0, 0, 0, 0, 0, 0, 0 }
1629 },
1630 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
1631 0, PD11MD_01, 0, 0, 0, 0, 0, 0,
1632 0, 0, 0, 0, 0, 0, 0, 0,
1633 0, PD10MD_01, 0, 0, 0, 0, 0, 0,
1634 0, 0, 0, 0, 0, 0, 0, 0,
1635 0, PD9MD_01, 0, 0, 0, 0, 0, 0,
1636 0, 0, 0, 0, 0, 0, 0, 0,
1637 0, PD8MD_01, 0, 0, 0, 0, 0, 0,
1638 0, 0, 0, 0, 0, 0, 0, 0 }
1639 },
1640 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
1641 0, PD7MD_01, 0, 0, 0, 0, 0, 0,
1642 0, 0, 0, 0, 0, 0, 0, 0,
1643 0, PD6MD_01, 0, 0, 0, 0, 0, 0,
1644 0, 0, 0, 0, 0, 0, 0, 0,
1645 0, PD5MD_01, 0, 0, 0, 0, 0, 0,
1646 0, 0, 0, 0, 0, 0, 0, 0,
1647 0, PD4MD_01, 0, 0, 0, 0, 0, 0,
1648 0, 0, 0, 0, 0, 0, 0, 0 }
1649 },
1650 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
1651 0, PD3MD_01, 0, 0, 0, 0, 0, 0,
1652 0, 0, 0, 0, 0, 0, 0, 0,
1653 0, PD2MD_01, 0, 0, 0, 0, 0, 0,
1654 0, 0, 0, 0, 0, 0, 0, 0,
1655 0, PD1MD_01, 0, 0, 0, 0, 0, 0,
1656 0, 0, 0, 0, 0, 0, 0, 0,
1657 0, PD0MD_01, 0, 0, 0, 0, 0, 0,
1658 0, 0, 0, 0, 0, 0, 0, 0 }
1659 },
1660
1661 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
1662 PD15_IN, PD15_OUT,
1663 PD14_IN, PD14_OUT,
1664 PD13_IN, PD13_OUT,
1665 PD12_IN, PD12_OUT,
1666 PD11_IN, PD11_OUT,
1667 PD10_IN, PD10_OUT,
1668 PD9_IN, PD9_OUT,
1669 PD8_IN, PD8_OUT,
1670 PD7_IN, PD7_OUT,
1671 PD6_IN, PD6_OUT,
1672 PD5_IN, PD5_OUT,
1673 PD4_IN, PD4_OUT,
1674 PD3_IN, PD3_OUT,
1675 PD2_IN, PD2_OUT,
1676 PD1_IN, PD1_OUT,
1677 PD0_IN, PD0_OUT }
1678 },
1679
1680 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
1681 0, 0, 0, 0, 0, 0, 0, 0,
1682 0, 0, 0, 0, 0, 0, 0, 0,
1683 0, 0, 0, 0, 0, 0, 0, 0,
1684 0, 0, 0, 0, 0, 0, 0, 0,
1685 PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
1686 0, 0, 0, 0, 0, 0, 0, 0,
1687 PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
1688 0, 0, 0, 0, 0, 0, 0, 0 }
1689 },
1690
1691 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
1692 PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
1693 0, 0, 0, 0, 0, 0, 0, 0,
1694 PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
1695 0, 0, 0, 0, 0, 0, 0, 0,
1696 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
1697 PE1MD_100, PE1MD_101, 0, 0,
1698 0, 0, 0, 0, 0, 0, 0, 0,
1699 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
1700 0, 0, 0, 0, 0, 0, 0, 0 }
1701 },
1702
1703 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
1704 0, 0, 0, 0, 0, 0, 0, 0,
1705 0, 0, 0, 0, 0, 0, 0, 0,
1706 0, 0, 0, 0,
1707 PE5_IN, PE5_OUT,
1708 PE4_IN, PE4_OUT,
1709 PE3_IN, PE3_OUT,
1710 PE2_IN, PE2_OUT,
1711 PE1_IN, PE1_OUT,
1712 PE0_IN, PE0_OUT }
1713 },
1714
1715 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
1716 PF12MD_000, PF12MD_001, 0, PF12MD_011,
1717 PF12MD_100, PF12MD_101, 0, 0,
1718 0, 0, 0, 0, 0, 0, 0, 0 }
1719 },
1720
1721 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
1722 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
1723 PF11MD_100, PF11MD_101, 0, 0,
1724 0, 0, 0, 0, 0, 0, 0, 0,
1725 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
1726 PF10MD_100, PF10MD_101, 0, 0,
1727 0, 0, 0, 0, 0, 0, 0, 0,
1728 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
1729 PF9MD_100, PF9MD_101, 0, 0,
1730 0, 0, 0, 0, 0, 0, 0, 0,
1731 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
1732 0, 0, 0, 0, 0, 0, 0, 0 }
1733 },
1734
1735 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
1736 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
1737 PF7MD_100, 0, 0, 0,
1738 0, 0, 0, 0, 0, 0, 0, 0,
1739 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
1740 PF6MD_100, 0, 0, 0,
1741 0, 0, 0, 0, 0, 0, 0, 0,
1742 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
1743 PF5MD_100, 0, 0, 0,
1744 0, 0, 0, 0, 0, 0, 0, 0,
1745 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
1746 PF4MD_100, 0, 0, 0,
1747 0, 0, 0, 0, 0, 0, 0, 0 }
1748 },
1749
1750 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
1751 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
1752 PF3MD_100, 0, 0, 0,
1753 0, 0, 0, 0, 0, 0, 0, 0,
1754 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
1755 PF2MD_100, PF2MD_101, 0, 0,
1756 0, 0, 0, 0, 0, 0, 0, 0,
1757 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
1758 PF1MD_100, PF1MD_101, 0, 0,
1759 0, 0, 0, 0, 0, 0, 0, 0
1760 }
1761 },
1762
1763 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
1764 0, 0, 0, 0, 0, 0,
1765 PF12_IN, PF12_OUT,
1766 PF11_IN, PF11_OUT,
1767 PF10_IN, PF10_OUT,
1768 PF9_IN, PF9_OUT,
1769 PF8_IN, PF8_OUT,
1770 PF7_IN, PF7_OUT,
1771 PF6_IN, PF6_OUT,
1772 PF5_IN, PF5_OUT,
1773 PF4_IN, PF4_OUT,
1774 PF3_IN, PF3_OUT,
1775 PF2_IN, PF2_OUT,
1776 PF1_IN, PF1_OUT,
1777 PF0_IN, PF0_OUT }
1778 },
1779
1780 { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) {
1781 0, 0, 0, 0, 0, 0, 0, 0,
1782 0, 0, 0, 0, 0, 0, 0, 0,
1783 0, 0, 0, 0, 0, 0, 0, 0,
1784 0, 0, 0, 0, 0, 0, 0, 0,
1785 0, 0, 0, 0, 0, 0, 0, 0,
1786 0, 0, 0, 0, 0, 0, 0, 0,
1787 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
1788 PG0MD_100, 0, 0, 0,
1789 0, 0, 0, 0, 0, 0, 0, 0 }
1790 },
1791
1792 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
1793 0, 0, 0, 0, 0, 0, 0, 0,
1794 0, 0, 0, 0, 0, 0, 0, 0,
1795 0, 0, 0, 0, 0, 0, 0, 0,
1796 0, 0, 0, 0, 0, 0, 0, 0,
1797 0, 0, 0, 0, 0, 0, 0, 0,
1798 0, 0, 0, 0, 0, 0, 0, 0,
1799 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
1800 0, 0, 0, 0, 0, 0, 0, 0 }
1801 },
1802
1803 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
1804 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
1805 0, 0, 0, 0, 0, 0, 0, 0,
1806 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
1807 0, 0, 0, 0, 0, 0, 0, 0,
1808 PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0,
1809 0, 0, 0, 0, 0, 0, 0, 0,
1810 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
1811 PG20MD_100, 0, 0, 0,
1812 0, 0, 0, 0, 0, 0, 0, 0 }
1813 },
1814
1815 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
1816 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
1817 PG19MD_100, 0, 0, 0,
1818 0, 0, 0, 0, 0, 0, 0, 0,
1819 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
1820 PG18MD_100, 0, 0, 0,
1821 0, 0, 0, 0, 0, 0, 0, 0,
1822 PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
1823 PG17MD_100, 0, 0, 0,
1824 0, 0, 0, 0, 0, 0, 0, 0,
1825 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
1826 PG16MD_100, 0, 0, 0,
1827 0, 0, 0, 0, 0, 0, 0, 0 }
1828 },
1829
1830 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
1831 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
1832 PG15MD_100, 0, 0, 0,
1833 0, 0, 0, 0, 0, 0, 0, 0,
1834 PG14MD_000, PG14MD_001, PG14MD_010, 0,
1835 PG14MD_100, 0, 0, 0,
1836 0, 0, 0, 0, 0, 0, 0, 0,
1837 PG13MD_000, PG13MD_001, PG13MD_010, 0,
1838 PG13MD_100, 0, 0, 0,
1839 0, 0, 0, 0, 0, 0, 0, 0,
1840 PG12MD_000, PG12MD_001, PG12MD_010, 0,
1841 PG12MD_100, 0, 0, 0,
1842 0, 0, 0, 0, 0, 0, 0, 0 }
1843 },
1844 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
1845 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
1846 PG11MD_100, PG11MD_101, 0, 0,
1847 0, 0, 0, 0, 0, 0, 0, 0,
1848 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
1849 PG10MD_100, PG10MD_101, 0, 0,
1850 0, 0, 0, 0, 0, 0, 0, 0,
1851 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
1852 PG9MD_100, PG9MD_101, 0, 0,
1853 0, 0, 0, 0, 0, 0, 0, 0,
1854 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
1855 PG8MD_100, PG8MD_101, 0, 0,
1856 0, 0, 0, 0, 0, 0, 0, 0 }
1857 },
1858
1859 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
1860 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
1861 0, 0, 0, 0, 0, 0, 0, 0,
1862 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
1863 0, 0, 0, 0, 0, 0, 0, 0,
1864 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
1865 0, 0, 0, 0, 0, 0, 0, 0,
1866 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
1867 0, 0, 0, 0, 0, 0, 0, 0 }
1868 },
1869 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
1870 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
1871 0, 0, 0, 0, 0, 0, 0, 0,
1872 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
1873 0, 0, 0, 0, 0, 0, 0, 0,
1874 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
1875 0, 0, 0, 0, 0, 0, 0, 0,
1876 0, 0, 0, 0, 0, 0, 0, 0,
1877 0, 0, 0, 0, 0, 0, 0, 0 }
1878 },
1879 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
1880 0, 0, 0, 0, 0, 0, 0, 0,
1881 0, 0, 0, 0, 0, 0,
1882 PG24_IN, PG24_OUT,
1883 PG23_IN, PG23_OUT,
1884 PG22_IN, PG22_OUT,
1885 PG21_IN, PG21_OUT,
1886 PG20_IN, PG20_OUT,
1887 PG19_IN, PG19_OUT,
1888 PG18_IN, PG18_OUT,
1889 PG17_IN, PG17_OUT,
1890 PG16_IN, PG16_OUT }
1891 },
1892
1893 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
1894 PG15_IN, PG15_OUT,
1895 PG14_IN, PG14_OUT,
1896 PG13_IN, PG13_OUT,
1897 PG12_IN, PG12_OUT,
1898 PG11_IN, PG11_OUT,
1899 PG10_IN, PG10_OUT,
1900 PG9_IN, PG9_OUT,
1901 PG8_IN, PG8_OUT,
1902 PG7_IN, PG7_OUT,
1903 PG6_IN, PG6_OUT,
1904 PG5_IN, PG5_OUT,
1905 PG4_IN, PG4_OUT,
1906 PG3_IN, PG3_OUT,
1907 PG2_IN, PG2_OUT,
1908 PG1_IN, PG1_OUT,
1909 PG0_IN, PG0_OUT
1910 }
1911 },
1912
1913 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
1914 PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
1915 0, 0, 0, 0, 0, 0, 0, 0,
1916 PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
1917 0, 0, 0, 0, 0, 0, 0, 0,
1918 PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
1919 0, 0, 0, 0, 0, 0, 0, 0,
1920 PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
1921 0, 0, 0, 0, 0, 0, 0, 0 }
1922 },
1923
1924 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
1925 PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
1926 0, 0, 0, 0, 0, 0, 0, 0,
1927 PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
1928 0, 0, 0, 0, 0, 0, 0, 0,
1929 PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
1930 0, 0, 0, 0, 0, 0, 0, 0,
1931 PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
1932 0, 0, 0, 0, 0, 0, 0, 0 }
1933 },
1934
1935 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
1936 PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
1937 0, 0, 0, 0, 0, 0, 0, 0,
1938 PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
1939 0, 0, 0, 0, 0, 0, 0, 0,
1940 PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
1941 0, 0, 0, 0, 0, 0, 0, 0,
1942 PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
1943 0, 0, 0, 0, 0, 0, 0, 0 }
1944 },
1945 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
1946 PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
1947 0, 0, 0, 0, 0, 0, 0, 0,
1948 PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
1949 0, 0, 0, 0, 0, 0, 0, 0,
1950 PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
1951 0, 0, 0, 0, 0, 0, 0, 0,
1952 PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
1953 0, 0, 0, 0, 0, 0, 0, 0 }
1954 },
1955 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
1956 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
1957 0, 0, 0, 0, 0, 0, 0, 0,
1958 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
1959 PJ2MD_100, PJ2MD_101, 0, 0,
1960 0, 0, 0, 0, 0, 0, 0, 0,
1961 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
1962 PJ1MD_100, 0, 0, 0,
1963 0, 0, 0, 0, 0, 0, 0, 0,
1964 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
1965 PJ0MD_100, PJ0MD_101, 0, 0,
1966 0, 0, 0, 0, 0, 0, 0, 0, }
1967 },
1968 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
1969 0, 0, 0, 0, 0, 0, 0, 0,
1970 PJ11_IN, PJ11_OUT,
1971 PJ10_IN, PJ10_OUT,
1972 PJ9_IN, PJ9_OUT,
1973 PJ8_IN, PJ8_OUT,
1974 PJ7_IN, PJ7_OUT,
1975 PJ6_IN, PJ6_OUT,
1976 PJ5_IN, PJ5_OUT,
1977 PJ4_IN, PJ4_OUT,
1978 PJ3_IN, PJ3_OUT,
1979 PJ2_IN, PJ2_OUT,
1980 PJ1_IN, PJ1_OUT,
1981 PJ0_IN, PJ0_OUT }
1982 },
1983
1984 { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) {
1985 PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
1986 0, 0, 0, 0, 0, 0, 0, 0,
1987 PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
1988 0, 0, 0, 0, 0, 0, 0, 0,
1989 PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
1990 0, 0, 0, 0, 0, 0, 0, 0,
1991 PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
1992 0, 0, 0, 0, 0, 0, 0, 0 }
1993 },
1994
1995 { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) {
1996 PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
1997 0, 0, 0, 0, 0, 0, 0, 0,
1998 PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0,
1999 0, 0, 0, 0, 0, 0, 0, 0,
2000 PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
2001 0, 0, 0, 0, 0, 0, 0, 0,
2002 PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
2003 0, 0, 0, 0, 0, 0, 0, 0 }
2004 },
2005 { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) {
2006 PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
2007 0, 0, 0, 0, 0, 0, 0, 0,
2008 PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
2009 0, 0, 0, 0, 0, 0, 0, 0,
2010 PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
2011 0, 0, 0, 0, 0, 0, 0, 0,
2012 PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
2013 0, 0, 0, 0, 0, 0, 0, 0 }
2014 },
2015
2016 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) {
2017 0, 0, 0, 0, 0, 0, 0, 0,
2018 PJ11_IN, PJ11_OUT,
2019 PJ10_IN, PJ10_OUT,
2020 PJ9_IN, PJ9_OUT,
2021 PJ8_IN, PJ8_OUT,
2022 PJ7_IN, PJ7_OUT,
2023 PJ6_IN, PJ6_OUT,
2024 PJ5_IN, PJ5_OUT,
2025 PJ4_IN, PJ4_OUT,
2026 PJ3_IN, PJ3_OUT,
2027 PJ2_IN, PJ2_OUT,
2028 PJ1_IN, PJ1_OUT,
2029 PJ0_IN, PJ0_OUT }
2030 },
2031 {}
2032};
2033
2034static struct pinmux_data_reg pinmux_data_regs[] = {
2035 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
2036 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
2037 0, 0, 0, 0, 0, 0, 0, PA2_DATA }
2038 },
2039
2040 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
2041 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2042 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
2043 },
2044
2045 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
2046 0, 0, 0, 0, 0, 0, 0, 0,
2047 0, PB22_DATA, PB21_DATA, PB20_DATA,
2048 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
2049 },
2050
2051 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
2052 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
2053 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
2054 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
2055 PB3_DATA, PB2_DATA, PB1_DATA, 0 }
2056 },
2057
2058 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
2059 0, 0, 0, 0,
2060 0, PC10_DATA, PC9_DATA, PC8_DATA,
2061 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
2062 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
2063 },
2064
2065 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
2066 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
2067 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
2068 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
2069 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
2070 },
2071
2072 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
2073 0, 0, 0, 0, 0, 0, 0, 0,
2074 0, 0, PE5_DATA, PE4_DATA,
2075 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
2076 },
2077
2078 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
2079 0, 0, 0, PF12_DATA,
2080 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
2081 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
2082 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
2083 },
2084
2085 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
2086 0, 0, 0, 0, 0, 0, 0, PG24_DATA,
2087 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
2088 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
2089 },
2090
2091 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
2092 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
2093 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
2094 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
2095 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
2096 },
2097 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
2098 0, 0, 0, PJ12_DATA,
2099 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
2100 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
2101 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
2102 },
2103 { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
2104 0, 0, 0, PK12_DATA,
2105 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
2106 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
2107 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
2108 },
2109 { }
2110};
2111
2112static struct pinmux_info sh7264_pinmux_info = {
2113 .name = "sh7264_pfc",
2114 .reserved_id = PINMUX_RESERVED,
2115 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2116 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2117 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2118 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2119 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2120
2121 .first_gpio = GPIO_PA3,
2122 .last_gpio = GPIO_FN_LCD_M_DISP,
2123
2124 .gpios = pinmux_gpios,
2125 .cfg_regs = pinmux_config_regs,
2126 .data_regs = pinmux_data_regs,
2127
2128 .gpio_data = pinmux_data,
2129 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2130};
2131
2132static int __init plat_pinmux_setup(void)
2133{
2134 return register_pinmux(&sh7264_pinmux_info);
2135}
2136arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 48e97a2a0c8..414b2581c60 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -29,6 +29,9 @@ void __cpuinit cpu_probe(void)
29#elif defined(CONFIG_CPU_SUBTYPE_SH7263) 29#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
30 boot_cpu_data.type = CPU_SH7263; 30 boot_cpu_data.type = CPU_SH7263;
31 boot_cpu_data.flags |= CPU_HAS_FPU; 31 boot_cpu_data.flags |= CPU_HAS_FPU;
32#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
33 boot_cpu_data.type = CPU_SH7264;
34 boot_cpu_data.flags |= CPU_HAS_FPU;
32#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 35#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
33 boot_cpu_data.type = CPU_SH7206; 36 boot_cpu_data.type = CPU_SH7206;
34 boot_cpu_data.flags |= CPU_HAS_DSP; 37 boot_cpu_data.flags |= CPU_HAS_DSP;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
new file mode 100644
index 00000000000..ce5c1b5aebf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -0,0 +1,606 @@
1/*
2 * SH7264 Setup
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/usb/r8a66597.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24
25 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
26 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
27 USB, VDC3, CMT0, CMT1, BSC, WDT,
28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
30 PWMT1, PWMT2, ADC_ADI,
31 SSIF0, SSII1, SSII2, SSII3,
32 RSPDIF,
33 IIC30, IIC31, IIC32, IIC33,
34 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
35 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
36 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
37 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
38 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
39 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
40 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
41 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
42 SIO_FIFO, RSPIC0, RSPIC1,
43 RCAN0, RCAN1, IEBC, CD_ROMD,
44 NFMC, SDHI, RTC,
45 SRCC0, SRCC1, DCOMU, OFFI, IFEI,
46
47 /* interrupt groups */
48 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
49};
50
51static struct intc_vect vectors[] __initdata = {
52 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
53 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
54 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
55 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
56
57 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
58 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
59 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
60 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
61
62 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
63 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
64 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
65 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
66 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
67 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
68 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
69 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
70 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
71 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
72 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
73 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
74 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
75 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
76 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
77 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
78
79 INTC_IRQ(USB, 170),
80 INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
81 INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
82 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
83 INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
84
85 INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
86 INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
87 INTC_IRQ(MTU0_VEF, 183),
88 INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
89 INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
90 INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
91 INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
92 INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
93 INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
94 INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
95 INTC_IRQ(MTU3_TCI3V, 198),
96 INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
97 INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
98 INTC_IRQ(MTU4_TCI4V, 203),
99
100 INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
101
102 INTC_IRQ(ADC_ADI, 206),
103
104 INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
105 INTC_IRQ(SSIF0, 209),
106 INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
107 INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
108 INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
109
110 INTC_IRQ(RSPDIF, 216),
111
112 INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
113 INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
114 INTC_IRQ(IIC30, 221),
115 INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
116 INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
117 INTC_IRQ(IIC31, 226),
118 INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
119 INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
120 INTC_IRQ(IIC32, 231),
121
122 INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
123 INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
124 INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
125 INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
126 INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
127 INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
128 INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
129 INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
130 INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
131 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
132 INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
133 INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
134 INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
135 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
136 INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
137 INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
138
139 INTC_IRQ(SIO_FIFO, 264),
140
141 INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
142 INTC_IRQ(RSPIC0, 267),
143 INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
144 INTC_IRQ(RSPIC1, 270),
145
146 INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
147 INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
148 INTC_IRQ(RCAN0, 275),
149 INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
150 INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
151 INTC_IRQ(RCAN1, 280),
152
153 INTC_IRQ(IEBC, 281),
154
155 INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
156 INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
157 INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
158
159 INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
160 INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
161
162 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
163 INTC_IRQ(SDHI, 294),
164
165 INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
166 INTC_IRQ(RTC, 298),
167
168 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
169 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
170 INTC_IRQ(SRCC0, 303),
171 INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
172 INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
173 INTC_IRQ(SRCC1, 308),
174
175 INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
176 INTC_IRQ(DCOMU, 312),
177};
178
179static struct intc_group groups[] __initdata = {
180 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
181 PINT4, PINT5, PINT6, PINT7),
182 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
183 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
184 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
185 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
186 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
187 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
188 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
189 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
190};
191
192static struct intc_prio_reg prio_registers[] __initdata = {
193 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
194 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
195 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
196 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
197 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
198 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
199 DMAC10, DMAC11 } },
200 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
201 DMAC14, DMAC15 } },
202 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
203 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
204 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
205 MTU2_AB, MTU2_VU } },
206 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
207 MTU4_ABCD, MTU4_TCI4V } },
208 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
209 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
210 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
211 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
212 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
213 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
214 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
215 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
216 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
217};
218
219static struct intc_mask_reg mask_registers[] __initdata = {
220 { 0xfffe0808, 0, 16, /* PINTER */
221 { 0, 0, 0, 0, 0, 0, 0, 0,
222 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
223};
224
225static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 mask_registers, prio_registers, NULL);
227
228static struct plat_sci_port scif0_platform_data = {
229 .mapbase = 0xfffe8000,
230 .flags = UPF_BOOT_AUTOCONF,
231 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 SCSCR_REIE | SCSCR_TOIE,
233 .scbrr_algo_id = SCBRR_ALGO_2,
234 .type = PORT_SCIF,
235 .irqs = { 233, 234, 235, 232 },
236 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237};
238
239static struct platform_device scif0_device = {
240 .name = "sh-sci",
241 .id = 0,
242 .dev = {
243 .platform_data = &scif0_platform_data,
244 },
245};
246
247static struct plat_sci_port scif1_platform_data = {
248 .mapbase = 0xfffe8800,
249 .flags = UPF_BOOT_AUTOCONF,
250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 SCSCR_REIE | SCSCR_TOIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF,
254 .irqs = { 237, 238, 239, 236 },
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256};
257
258static struct platform_device scif1_device = {
259 .name = "sh-sci",
260 .id = 1,
261 .dev = {
262 .platform_data = &scif1_platform_data,
263 },
264};
265
266static struct plat_sci_port scif2_platform_data = {
267 .mapbase = 0xfffe9000,
268 .flags = UPF_BOOT_AUTOCONF,
269 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 SCSCR_REIE | SCSCR_TOIE,
271 .scbrr_algo_id = SCBRR_ALGO_2,
272 .type = PORT_SCIF,
273 .irqs = { 241, 242, 243, 240 },
274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275};
276
277static struct platform_device scif2_device = {
278 .name = "sh-sci",
279 .id = 2,
280 .dev = {
281 .platform_data = &scif2_platform_data,
282 },
283};
284
285static struct plat_sci_port scif3_platform_data = {
286 .mapbase = 0xfffe9800,
287 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 SCSCR_REIE | SCSCR_TOIE,
290 .scbrr_algo_id = SCBRR_ALGO_2,
291 .type = PORT_SCIF,
292 .irqs = { 245, 246, 247, 244 },
293 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294};
295
296static struct platform_device scif3_device = {
297 .name = "sh-sci",
298 .id = 3,
299 .dev = {
300 .platform_data = &scif3_platform_data,
301 },
302};
303
304static struct plat_sci_port scif4_platform_data = {
305 .mapbase = 0xfffea000,
306 .flags = UPF_BOOT_AUTOCONF,
307 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 SCSCR_REIE | SCSCR_TOIE,
309 .scbrr_algo_id = SCBRR_ALGO_2,
310 .type = PORT_SCIF,
311 .irqs = { 249, 250, 251, 248 },
312 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313};
314
315static struct platform_device scif4_device = {
316 .name = "sh-sci",
317 .id = 4,
318 .dev = {
319 .platform_data = &scif4_platform_data,
320 },
321};
322
323static struct plat_sci_port scif5_platform_data = {
324 .mapbase = 0xfffea800,
325 .flags = UPF_BOOT_AUTOCONF,
326 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 SCSCR_REIE | SCSCR_TOIE,
328 .scbrr_algo_id = SCBRR_ALGO_2,
329 .type = PORT_SCIF,
330 .irqs = { 253, 254, 255, 252 },
331 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332};
333
334static struct platform_device scif5_device = {
335 .name = "sh-sci",
336 .id = 5,
337 .dev = {
338 .platform_data = &scif5_platform_data,
339 },
340};
341
342static struct plat_sci_port scif6_platform_data = {
343 .mapbase = 0xfffeb000,
344 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 SCSCR_REIE | SCSCR_TOIE,
347 .scbrr_algo_id = SCBRR_ALGO_2,
348 .type = PORT_SCIF,
349 .irqs = { 257, 258, 259, 256 },
350 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351};
352
353static struct platform_device scif6_device = {
354 .name = "sh-sci",
355 .id = 6,
356 .dev = {
357 .platform_data = &scif6_platform_data,
358 },
359};
360
361static struct plat_sci_port scif7_platform_data = {
362 .mapbase = 0xfffeb800,
363 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 SCSCR_REIE | SCSCR_TOIE,
366 .scbrr_algo_id = SCBRR_ALGO_2,
367 .type = PORT_SCIF,
368 .irqs = { 261, 262, 263, 260 },
369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370};
371
372static struct platform_device scif7_device = {
373 .name = "sh-sci",
374 .id = 7,
375 .dev = {
376 .platform_data = &scif7_platform_data,
377 },
378};
379
380static struct sh_timer_config cmt0_platform_data = {
381 .channel_offset = 0x02,
382 .timer_bit = 0,
383 .clockevent_rating = 125,
384 .clocksource_rating = 0, /* disabled due to code generation issues */
385};
386
387static struct resource cmt0_resources[] = {
388 [0] = {
389 .name = "CMT0",
390 .start = 0xfffec002,
391 .end = 0xfffec007,
392 .flags = IORESOURCE_MEM,
393 },
394 [1] = {
395 .start = 175,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
400static struct platform_device cmt0_device = {
401 .name = "sh_cmt",
402 .id = 0,
403 .dev = {
404 .platform_data = &cmt0_platform_data,
405 },
406 .resource = cmt0_resources,
407 .num_resources = ARRAY_SIZE(cmt0_resources),
408};
409
410static struct sh_timer_config cmt1_platform_data = {
411 .name = "CMT1",
412 .channel_offset = 0x08,
413 .timer_bit = 1,
414 .clockevent_rating = 125,
415 .clocksource_rating = 0, /* disabled due to code generation issues */
416};
417
418static struct resource cmt1_resources[] = {
419 [0] = {
420 .name = "CMT1",
421 .start = 0xfffec008,
422 .end = 0xfffec00d,
423 .flags = IORESOURCE_MEM,
424 },
425 [1] = {
426 .start = 176,
427 .flags = IORESOURCE_IRQ,
428 },
429};
430
431static struct platform_device cmt1_device = {
432 .name = "sh_cmt",
433 .id = 1,
434 .dev = {
435 .platform_data = &cmt1_platform_data,
436 },
437 .resource = cmt1_resources,
438 .num_resources = ARRAY_SIZE(cmt1_resources),
439};
440
441static struct sh_timer_config mtu2_0_platform_data = {
442 .name = "MTU2_0",
443 .channel_offset = -0x80,
444 .timer_bit = 0,
445 .clockevent_rating = 200,
446};
447
448static struct resource mtu2_0_resources[] = {
449 [0] = {
450 .name = "MTU2_0",
451 .start = 0xfffe4300,
452 .end = 0xfffe4326,
453 .flags = IORESOURCE_MEM,
454 },
455 [1] = {
456 .start = 179,
457 .flags = IORESOURCE_IRQ,
458 },
459};
460
461static struct platform_device mtu2_0_device = {
462 .name = "sh_mtu2",
463 .id = 0,
464 .dev = {
465 .platform_data = &mtu2_0_platform_data,
466 },
467 .resource = mtu2_0_resources,
468 .num_resources = ARRAY_SIZE(mtu2_0_resources),
469};
470
471static struct sh_timer_config mtu2_1_platform_data = {
472 .name = "MTU2_1",
473 .channel_offset = -0x100,
474 .timer_bit = 1,
475 .clockevent_rating = 200,
476};
477
478static struct resource mtu2_1_resources[] = {
479 [0] = {
480 .name = "MTU2_1",
481 .start = 0xfffe4380,
482 .end = 0xfffe4390,
483 .flags = IORESOURCE_MEM,
484 },
485 [1] = {
486 .start = 186,
487 .flags = IORESOURCE_IRQ,
488 },
489};
490
491static struct platform_device mtu2_1_device = {
492 .name = "sh_mtu2",
493 .id = 1,
494 .dev = {
495 .platform_data = &mtu2_1_platform_data,
496 },
497 .resource = mtu2_1_resources,
498 .num_resources = ARRAY_SIZE(mtu2_1_resources),
499};
500
501static struct resource rtc_resources[] = {
502 [0] = {
503 .start = 0xfffe6000,
504 .end = 0xfffe6000 + 0x30 - 1,
505 .flags = IORESOURCE_IO,
506 },
507 [1] = {
508 /* Shared Period/Carry/Alarm IRQ */
509 .start = 296,
510 .flags = IORESOURCE_IRQ,
511 },
512};
513
514static struct platform_device rtc_device = {
515 .name = "sh-rtc",
516 .id = -1,
517 .num_resources = ARRAY_SIZE(rtc_resources),
518 .resource = rtc_resources,
519};
520
521/* USB Host */
522static void usb_port_power(int port, int power)
523{
524 __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
525}
526
527static struct r8a66597_platdata r8a66597_data = {
528 .on_chip = 1,
529 .endian = 1,
530 .port_power = usb_port_power,
531};
532
533static struct resource r8a66597_usb_host_resources[] = {
534 [0] = {
535 .start = 0xffffc000,
536 .end = 0xffffc0e4,
537 .flags = IORESOURCE_MEM,
538 },
539 [1] = {
540 .start = 170,
541 .end = 170,
542 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
543 },
544};
545
546static struct platform_device r8a66597_usb_host_device = {
547 .name = "r8a66597_hcd",
548 .id = 0,
549 .dev = {
550 .dma_mask = NULL, /* not use dma */
551 .coherent_dma_mask = 0xffffffff,
552 .platform_data = &r8a66597_data,
553 },
554 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
555 .resource = r8a66597_usb_host_resources,
556};
557
558static struct platform_device *sh7264_devices[] __initdata = {
559 &scif0_device,
560 &scif1_device,
561 &scif2_device,
562 &scif3_device,
563 &scif4_device,
564 &scif5_device,
565 &scif6_device,
566 &scif7_device,
567 &cmt0_device,
568 &cmt1_device,
569 &mtu2_0_device,
570 &mtu2_1_device,
571 &rtc_device,
572 &r8a66597_usb_host_device,
573};
574
575static int __init sh7264_devices_setup(void)
576{
577 return platform_add_devices(sh7264_devices,
578 ARRAY_SIZE(sh7264_devices));
579}
580arch_initcall(sh7264_devices_setup);
581
582void __init plat_irq_setup(void)
583{
584 register_intc_controller(&intc_desc);
585}
586
587static struct platform_device *sh7264_early_devices[] __initdata = {
588 &scif0_device,
589 &scif1_device,
590 &scif2_device,
591 &scif3_device,
592 &scif4_device,
593 &scif5_device,
594 &scif6_device,
595 &scif7_device,
596 &cmt0_device,
597 &cmt1_device,
598 &mtu2_0_device,
599 &mtu2_1_device,
600};
601
602void __init plat_early_device_setup(void)
603{
604 early_platform_add_devices(sh7264_early_devices,
605 ARRAY_SIZE(sh7264_early_devices));
606}
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-05 00:20:42 -0400