sh: Disable SCIF2 on the SH-X3 proto CPU.

SCIF2 and the FPU exceptions happen to share vector numbers, one in
EXPEVT and the other in INTEVT. This is a violation of the interface and
should have never made it in to silicon. On top of that, the demux hack
that was added for special dispatch is rather error prone, and introduces
more problems than it solves. Kill all of it off, and just refuse to deal
with SCIF2 outright.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

3 files changed, 9 insertions, 46 deletions

diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index bb407ef0b91..3f7e2a22c7c 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -297,41 +297,8 @@ ENTRY(vbr_base)
 !
         .balign         256,0,256
 general_exception:
-#ifndef CONFIG_CPU_SUBTYPE_SHX3
         bra     handle_exception
          sts    pr, k3          ! save original pr value in k3
-#else
-        mov.l   1f, k4
-        mov.l   @k4, k4
-
-        ! Is EXPEVT larger than 0x800?
-        mov     #0x8, k0
-        shll8   k0
-        cmp/hs  k0, k4
-        bf      0f
-
-        ! then add 0x580 (k2 is 0xd80 or 0xda0)
-        mov     #0x58, k0
-        shll2   k0
-        shll2   k0
-        add     k0, k4
-0:
-        ! Setup stack and save DSP context (k0 contains original r15 on return)
-        bsr     prepare_stack
-         nop
-
-        ! Save registers / Switch to bank 0
-        mov             k4, k2          ! keep vector in k2
-        mov.l   1f, k4          ! SR bits to clear in k4
-        bsr     save_regs       ! needs original pr value in k3
-         nop
-
-        bra     handle_exception_special
-         nop
-
-        .align  2
-1:      .long   EXPEVT
-#endif
 
 ! prepare_stack()
 ! - roll back gRB
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 485330cf854..c7ba9166e18 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -15,6 +15,15 @@
 #include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
+/*
+ * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
+ * INTEVT values overlap with the FPU EXPEVT ones, requiring special
+ * demuxing in the exception dispatch path.
+ *
+ * As this overlap is something that never should have made it in to
+ * silicon in the first place, we just refuse to deal with the port at
+ * all rather than adding infrastructure to hack around it.
+ */
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffc30000,
@@ -27,11 +36,6 @@ static struct plat_sci_port sci_platform_data[] = {
                 .type           = PORT_SCIF,
                 .irqs           = { 44, 45, 47, 46 },
         }, {
-                .mapbase        = 0xffc50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .type           = PORT_SCIF,
-                .irqs           = { 48, 49, 51, 50 },
-        }, {
                 .mapbase        = 0xffc60000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
@@ -313,8 +317,6 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
-        INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
-        INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
         INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
         INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
         INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
@@ -355,7 +357,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
-        INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
         INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 7a2ee3a6b8e..114d2176182 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -945,14 +945,9 @@ void __init trap_init(void)
         set_exception_table_evt(0x800, do_reserved_inst);
         set_exception_table_evt(0x820, do_illegal_slot_inst);
 #elif defined(CONFIG_SH_FPU)
-#ifdef CONFIG_CPU_SUBTYPE_SHX3
-        set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
-        set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
-#else
         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 #endif
-#endif
 
 #ifdef CONFIG_CPU_SH2
         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);