diff options
| author | Magnus Damm <damm@igel.co.jp> | 2007-08-12 02:22:02 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-09-20 22:57:49 -0400 |
| commit | 6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (patch) | |
| tree | ba5b4c0a19a1d81047d49488b6fe3e3b02e824cf /arch/sh/kernel/cpu/sh4a/setup-shx3.c | |
| parent | d6aee69ca11550f3ca325ceaa020ea74e173478f (diff) | |
sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-shx3.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-shx3.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 610343ea9a8..2c13f9ceac7 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
| @@ -192,18 +192,21 @@ static struct intc_mask_reg mask_registers[] = { | |||
| 192 | }; | 192 | }; |
| 193 | 193 | ||
| 194 | static struct intc_prio_reg prio_registers[] = { | 194 | static struct intc_prio_reg prio_registers[] = { |
| 195 | { 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | 195 | { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
| 196 | 196 | ||
| 197 | { 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, | 197 | { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, |
| 198 | TMU3, TMU2, TMU1, TMU0 } }, | 198 | TMU3, TMU2, TMU1, TMU0 } }, |
| 199 | { 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0, | 199 | { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0, |
| 200 | SCIF3, SCIF2, SCIF1, SCIF0 } }, | 200 | SCIF3, SCIF2, |
| 201 | { 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4, | 201 | SCIF1, SCIF0 } }, |
| 202 | PCII3, PCII2, PCII1, PCII0 } }, | 202 | { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, |
| 203 | { 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0, | 203 | PCII56789, PCII4, |
| 204 | VIN1, VIN0, IIC, DU} }, | 204 | PCII3, PCII2, |
| 205 | { 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3, | 205 | PCII1, PCII0 } }, |
| 206 | GPIO2, GPIO1, GPIO0, IRM } }, | 206 | { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0, |
| 207 | VIN1, VIN0, IIC, DU} }, | ||
| 208 | { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3, | ||
| 209 | GPIO2, GPIO1, GPIO0, IRM } }, | ||
| 207 | }; | 210 | }; |
| 208 | 211 | ||
| 209 | static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities, | 212 | static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities, |