sh: Preparation for uncached jumps through PMB.

Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index bf579e061e0..22070e43e34 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,11 +16,11 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 
-int __init detect_cpu_and_cache_system(void)
+int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
 {
         unsigned long addr0, addr1, data0, data1, data2, data3;
 
-        jump_to_P2();
+        jump_to_uncached();
         /*
          * Check if the entry shadows or not.
          * When shadowed, it's 128-entry system.
@@ -48,7 +48,7 @@ int __init detect_cpu_and_cache_system(void)
         ctrl_outl(data0&~SH_CACHE_VALID, addr0);
         ctrl_outl(data2&~SH_CACHE_VALID, addr1);
 
-        back_to_P1();
+        back_to_cached();
 
         boot_cpu_data.dcache.ways               = 4;
         boot_cpu_data.dcache.entry_shift        = 4;