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authorPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
commitf15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch)
tree774d7b11abaaf33561ab8268bf51ddd9ceb79025 /arch/sh/include/cpu-sh5
parent25326277d8d1393d1c66240e6255aca780f9e3eb (diff)
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh5')
-rw-r--r--arch/sh/include/cpu-sh5/cpu/addrspace.h11
-rw-r--r--arch/sh/include/cpu-sh5/cpu/cache.h97
-rw-r--r--arch/sh/include/cpu-sh5/cpu/cacheflush.h33
-rw-r--r--arch/sh/include/cpu-sh5/cpu/dma.h6
-rw-r--r--arch/sh/include/cpu-sh5/cpu/irq.h117
-rw-r--r--arch/sh/include/cpu-sh5/cpu/mmu_context.h21
-rw-r--r--arch/sh/include/cpu-sh5/cpu/registers.h106
-rw-r--r--arch/sh/include/cpu-sh5/cpu/rtc.h8
-rw-r--r--arch/sh/include/cpu-sh5/cpu/timer.h4
9 files changed, 403 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh5/cpu/addrspace.h b/arch/sh/include/cpu-sh5/cpu/addrspace.h
new file mode 100644
index 00000000000..dc36b9a03af
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/addrspace.h
@@ -0,0 +1,11 @@
1#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
2#define __ASM_SH_CPU_SH5_ADDRSPACE_H
3
4#define PHYS_PERIPHERAL_BLOCK 0x09000000
5#define PHYS_DMAC_BLOCK 0x0e000000
6#define PHYS_PCI_BLOCK 0x60000000
7#define PHYS_EMI_BLOCK 0xff000000
8
9/* No segmentation.. */
10
11#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cache.h b/arch/sh/include/cpu-sh5/cpu/cache.h
new file mode 100644
index 00000000000..ed050ab526f
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cache.h
@@ -0,0 +1,97 @@
1#ifndef __ASM_SH_CPU_SH5_CACHE_H
2#define __ASM_SH_CPU_SH5_CACHE_H
3
4/*
5 * include/asm-sh/cpu-sh5/cache.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003, 2004 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14
15#define L1_CACHE_SHIFT 5
16
17/* Valid and Dirty bits */
18#define SH_CACHE_VALID (1LL<<0)
19#define SH_CACHE_UPDATED (1LL<<57)
20
21/* Unimplemented compat bits.. */
22#define SH_CACHE_COMBINED 0
23#define SH_CACHE_ASSOC 0
24
25/* Cache flags */
26#define SH_CACHE_MODE_WT (1LL<<0)
27#define SH_CACHE_MODE_WB (1LL<<1)
28
29/*
30 * Control Registers.
31 */
32#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
33#define ICCR_REG0 0 /* Register 0 offset */
34#define ICCR_REG1 1 /* Register 1 offset */
35#define ICCR0 ICCR_BASE+ICCR_REG0
36#define ICCR1 ICCR_BASE+ICCR_REG1
37
38#define ICCR0_OFF 0x0 /* Set ICACHE off */
39#define ICCR0_ON 0x1 /* Set ICACHE on */
40#define ICCR0_ICI 0x2 /* Invalidate all in IC */
41
42#define ICCR1_NOLOCK 0x0 /* Set No Locking */
43
44#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
45#define OCCR_REG0 0 /* Register 0 offset */
46#define OCCR_REG1 1 /* Register 1 offset */
47#define OCCR0 OCCR_BASE+OCCR_REG0
48#define OCCR1 OCCR_BASE+OCCR_REG1
49
50#define OCCR0_OFF 0x0 /* Set OCACHE off */
51#define OCCR0_ON 0x1 /* Set OCACHE on */
52#define OCCR0_OCI 0x2 /* Invalidate all in OC */
53#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
54#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
55
56#define OCCR1_NOLOCK 0x0 /* Set No Locking */
57
58/*
59 * SH-5
60 * A bit of description here, for neff=32.
61 *
62 * |<--- tag (19 bits) --->|
63 * +-----------------------------+-----------------+------+----------+------+
64 * | | | ways |set index |offset|
65 * +-----------------------------+-----------------+------+----------+------+
66 * ^ 2 bits 8 bits 5 bits
67 * +- Bit 31
68 *
69 * Cacheline size is based on offset: 5 bits = 32 bytes per line
70 * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
71 * have a broader space for registers. These are outlined by
72 * CACHE_?C_*_STEP below.
73 *
74 */
75
76/* Instruction cache */
77#define CACHE_IC_ADDRESS_ARRAY 0x01000000
78
79/* Operand Cache */
80#define CACHE_OC_ADDRESS_ARRAY 0x01800000
81
82/* These declarations relate to cache 'synonyms' in the operand cache. A
83 'synonym' occurs where effective address bits overlap between those used for
84 indexing the cache sets and those passed to the MMU for translation. In the
85 case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
86
87#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
88#define CACHE_OC_SYN_SHIFT 12
89/* Mask to select synonym bit(s) */
90#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
91
92/*
93 * Instruction cache can't be invalidated based on physical addresses.
94 * No Instruction Cache defines required, then.
95 */
96
97#endif /* __ASM_SH_CPU_SH5_CACHE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
new file mode 100644
index 00000000000..5a11f0b7e66
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
2#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
3
4#ifndef __ASSEMBLY__
5
6struct vm_area_struct;
7struct page;
8struct mm_struct;
9
10extern void flush_cache_all(void);
11extern void flush_cache_mm(struct mm_struct *mm);
12extern void flush_cache_sigtramp(unsigned long vaddr);
13extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
14 unsigned long end);
15extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
16extern void flush_dcache_page(struct page *pg);
17extern void flush_icache_range(unsigned long start, unsigned long end);
18extern void flush_icache_user_range(struct vm_area_struct *vma,
19 struct page *page, unsigned long addr,
20 int len);
21
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23
24#define flush_dcache_mmap_lock(mapping) do { } while (0)
25#define flush_dcache_mmap_unlock(mapping) do { } while (0)
26
27#define flush_icache_page(vma, page) do { } while (0)
28void p3_cache_init(void);
29
30#endif /* __ASSEMBLY__ */
31
32#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
33
diff --git a/arch/sh/include/cpu-sh5/cpu/dma.h b/arch/sh/include/cpu-sh5/cpu/dma.h
new file mode 100644
index 00000000000..7bf6bb3d35e
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/dma.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_CPU_SH5_DMA_H
2#define __ASM_SH_CPU_SH5_DMA_H
3
4/* Nothing yet */
5
6#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
new file mode 100644
index 00000000000..f0f0756e6e8
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -0,0 +1,117 @@
1#ifndef __ASM_SH_CPU_SH5_IRQ_H
2#define __ASM_SH_CPU_SH5_IRQ_H
3
4/*
5 * include/asm-sh/cpu-sh5/irq.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14
15/*
16 * Encoded IRQs are not considered worth to be supported.
17 * Main reason is that there's no per-encoded-interrupt
18 * enable/disable mechanism (as there was in SH3/4).
19 * An all enabled/all disabled is worth only if there's
20 * a cascaded IC to disable/enable/ack on. Until such
21 * IC is available there's no such support.
22 *
23 * Presumably Encoded IRQs may use extra IRQs beyond 64,
24 * below. Some logic must be added to cope with IRQ_IRL?
25 * in an exclusive way.
26 *
27 * Priorities are set at Platform level, when IRQ_IRL0-3
28 * are set to 0 Encoding is allowed. Otherwise it's not
29 * allowed.
30 */
31
32/* Independent IRQs */
33#define IRQ_IRL0 0
34#define IRQ_IRL1 1
35#define IRQ_IRL2 2
36#define IRQ_IRL3 3
37
38#define IRQ_INTA 4
39#define IRQ_INTB 5
40#define IRQ_INTC 6
41#define IRQ_INTD 7
42
43#define IRQ_SERR 12
44#define IRQ_ERR 13
45#define IRQ_PWR3 14
46#define IRQ_PWR2 15
47#define IRQ_PWR1 16
48#define IRQ_PWR0 17
49
50#define IRQ_DMTE0 18
51#define IRQ_DMTE1 19
52#define IRQ_DMTE2 20
53#define IRQ_DMTE3 21
54#define IRQ_DAERR 22
55
56#define IRQ_TUNI0 32
57#define IRQ_TUNI1 33
58#define IRQ_TUNI2 34
59#define IRQ_TICPI2 35
60
61#define IRQ_ATI 36
62#define IRQ_PRI 37
63#define IRQ_CUI 38
64
65#define IRQ_ERI 39
66#define IRQ_RXI 40
67#define IRQ_BRI 41
68#define IRQ_TXI 42
69
70#define IRQ_ITI 63
71
72#define NR_INTC_IRQS 64
73
74#ifdef CONFIG_SH_CAYMAN
75#define NR_EXT_IRQS 32
76#define START_EXT_IRQS 64
77
78/* PCI bus 2 uses encoded external interrupts on the Cayman board */
79#define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0)
80#define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1)
81#define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2)
82#define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3)
83
84#define I8042_KBD_IRQ (START_EXT_IRQS + 2)
85#define I8042_AUX_IRQ (START_EXT_IRQS + 6)
86
87#define IRQ_CFCARD (START_EXT_IRQS + 7)
88#define IRQ_PCMCIA (0)
89
90#else
91#define NR_EXT_IRQS 0
92#endif
93
94/* Default IRQs, fixed */
95#define TIMER_IRQ IRQ_TUNI0
96#define RTC_IRQ IRQ_CUI
97
98/* Default Priorities, Platform may choose differently */
99#define NO_PRIORITY 0 /* Disabled */
100#define TIMER_PRIORITY 2
101#define RTC_PRIORITY TIMER_PRIORITY
102#define SCIF_PRIORITY 3
103#define INTD_PRIORITY 3
104#define IRL3_PRIORITY 4
105#define INTC_PRIORITY 6
106#define IRL2_PRIORITY 7
107#define INTB_PRIORITY 9
108#define IRL1_PRIORITY 10
109#define INTA_PRIORITY 12
110#define IRL0_PRIORITY 13
111#define TOP_PRIORITY 15
112
113extern int intc_evt_to_irq[(0xE20/0x20)+1];
114int intc_irq_describe(char* p, int irq);
115extern int platform_int_priority[NR_INTC_IRQS];
116
117#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/mmu_context.h b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
new file mode 100644
index 00000000000..68a1d2cff45
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
2#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
3
4/* Common defines */
5#define TLB_STEP 0x00000010
6#define TLB_PTEH 0x00000000
7#define TLB_PTEL 0x00000008
8
9/* PTEH defines */
10#define PTEH_ASID_SHIFT 2
11#define PTEH_VALID 0x0000000000000001
12#define PTEH_SHARED 0x0000000000000002
13#define PTEH_MATCH_ASID 0x00000000000003ff
14
15#ifndef __ASSEMBLY__
16/* This has to be a common function because the next location to fill
17 * information is shared. */
18extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
19#endif /* __ASSEMBLY__ */
20
21#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/registers.h b/arch/sh/include/cpu-sh5/cpu/registers.h
new file mode 100644
index 00000000000..6664ea6f156
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/registers.h
@@ -0,0 +1,106 @@
1#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
2#define __ASM_SH_CPU_SH5_REGISTERS_H
3
4/*
5 * include/asm-sh/cpu-sh5/registers.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2004 Richard Curnow
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14
15#ifdef __ASSEMBLY__
16/* =====================================================================
17**
18** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
19** Assigns symbolic names to control & target registers.
20*/
21
22/*
23 * Define some useful aliases for control registers.
24 */
25#define SR cr0
26#define SSR cr1
27#define PSSR cr2
28 /* cr3 UNDEFINED */
29#define INTEVT cr4
30#define EXPEVT cr5
31#define PEXPEVT cr6
32#define TRA cr7
33#define SPC cr8
34#define PSPC cr9
35#define RESVEC cr10
36#define VBR cr11
37 /* cr12 UNDEFINED */
38#define TEA cr13
39 /* cr14-cr15 UNDEFINED */
40#define DCR cr16
41#define KCR0 cr17
42#define KCR1 cr18
43 /* cr19-cr31 UNDEFINED */
44 /* cr32-cr61 RESERVED */
45#define CTC cr62
46#define USR cr63
47
48/*
49 * ABI dependent registers (general purpose set)
50 */
51#define RET r2
52#define ARG1 r2
53#define ARG2 r3
54#define ARG3 r4
55#define ARG4 r5
56#define ARG5 r6
57#define ARG6 r7
58#define SP r15
59#define LINK r18
60#define ZERO r63
61
62/*
63 * Status register defines: used only by assembly sources (and
64 * syntax independednt)
65 */
66#define SR_RESET_VAL 0x0000000050008000
67#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
68#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
69
70#if defined (CONFIG_SH64_SR_WATCH)
71#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
72#else
73#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
74#endif
75
76#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
77#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
78
79#else /* Not __ASSEMBLY__ syntax */
80
81/*
82** Stringify reg. name
83*/
84#define __str(x) #x
85
86/* Stringify control register names for use in inline assembly */
87#define __SR __str(SR)
88#define __SSR __str(SSR)
89#define __PSSR __str(PSSR)
90#define __INTEVT __str(INTEVT)
91#define __EXPEVT __str(EXPEVT)
92#define __PEXPEVT __str(PEXPEVT)
93#define __TRA __str(TRA)
94#define __SPC __str(SPC)
95#define __PSPC __str(PSPC)
96#define __RESVEC __str(RESVEC)
97#define __VBR __str(VBR)
98#define __TEA __str(TEA)
99#define __DCR __str(DCR)
100#define __KCR0 __str(KCR0)
101#define __KCR1 __str(KCR1)
102#define __CTC __str(CTC)
103#define __USR __str(USR)
104
105#endif /* __ASSEMBLY__ */
106#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/rtc.h b/arch/sh/include/cpu-sh5/cpu/rtc.h
new file mode 100644
index 00000000000..12ea0ed144e
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/rtc.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_CPU_SH5_RTC_H
2#define __ASM_SH_CPU_SH5_RTC_H
3
4#define rtc_reg_size sizeof(u32)
5#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */
6#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
7
8#endif /* __ASM_SH_CPU_SH5_RTC_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/timer.h b/arch/sh/include/cpu-sh5/cpu/timer.h
new file mode 100644
index 00000000000..88da9b341a3
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/timer.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_SH_CPU_SH5_TIMER_H
2#define __ASM_SH_CPU_SH5_TIMER_H
3
4#endif /* __ASM_SH_CPU_SH5_TIMER_H */
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