diff options
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2011-02-25 02:40:16 -0500 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-03-10 22:36:29 -0500 |
| commit | 8ac53ed537a4a32d81279d37476bfaeb2aff15ab (patch) | |
| tree | 2a0ffa6997403201f837ba771a6e655fffc5fe59 /arch/sh/include/cpu-sh4/cpu | |
| parent | 53bc18ef4d8cb287c0667389fa05721aedf54e15 (diff) | |
sh: dmaengine support for SH7757
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/dma-register.h | 5 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/sh7757.h | 32 |
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h index 9a6125eb007..18fa80aba15 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-register.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h | |||
| @@ -40,6 +40,11 @@ | |||
| 40 | #define CHCR_TS_LOW_SHIFT 3 | 40 | #define CHCR_TS_LOW_SHIFT 3 |
| 41 | #define CHCR_TS_HIGH_MASK 0 | 41 | #define CHCR_TS_HIGH_MASK 0 |
| 42 | #define CHCR_TS_HIGH_SHIFT 0 | 42 | #define CHCR_TS_HIGH_SHIFT 0 |
| 43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
| 44 | #define CHCR_TS_LOW_MASK 0x00000018 | ||
| 45 | #define CHCR_TS_LOW_SHIFT 3 | ||
| 46 | #define CHCR_TS_HIGH_MASK 0x00100000 | ||
| 47 | #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ | ||
| 43 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | 48 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 44 | #define CHCR_TS_LOW_MASK 0x00000018 | 49 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 45 | #define CHCR_TS_LOW_SHIFT 3 | 50 | #define CHCR_TS_LOW_SHIFT 3 |
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h index 15f3de11c55..05b8196c775 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7757.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h | |||
| @@ -251,4 +251,36 @@ enum { | |||
| 251 | GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, | 251 | GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, |
| 252 | }; | 252 | }; |
| 253 | 253 | ||
| 254 | enum { | ||
| 255 | SHDMA_SLAVE_SDHI_TX, | ||
| 256 | SHDMA_SLAVE_SDHI_RX, | ||
| 257 | SHDMA_SLAVE_MMCIF_TX, | ||
| 258 | SHDMA_SLAVE_MMCIF_RX, | ||
| 259 | SHDMA_SLAVE_SCIF2_TX, | ||
| 260 | SHDMA_SLAVE_SCIF2_RX, | ||
| 261 | SHDMA_SLAVE_SCIF3_TX, | ||
| 262 | SHDMA_SLAVE_SCIF3_RX, | ||
| 263 | SHDMA_SLAVE_SCIF4_TX, | ||
| 264 | SHDMA_SLAVE_SCIF4_RX, | ||
| 265 | SHDMA_SLAVE_RIIC0_TX, | ||
| 266 | SHDMA_SLAVE_RIIC0_RX, | ||
| 267 | SHDMA_SLAVE_RIIC1_TX, | ||
| 268 | SHDMA_SLAVE_RIIC1_RX, | ||
| 269 | SHDMA_SLAVE_RIIC2_TX, | ||
| 270 | SHDMA_SLAVE_RIIC2_RX, | ||
| 271 | SHDMA_SLAVE_RIIC3_TX, | ||
| 272 | SHDMA_SLAVE_RIIC3_RX, | ||
| 273 | SHDMA_SLAVE_RIIC4_TX, | ||
| 274 | SHDMA_SLAVE_RIIC4_RX, | ||
| 275 | SHDMA_SLAVE_RIIC5_TX, | ||
| 276 | SHDMA_SLAVE_RIIC5_RX, | ||
| 277 | SHDMA_SLAVE_RIIC6_TX, | ||
| 278 | SHDMA_SLAVE_RIIC6_RX, | ||
| 279 | SHDMA_SLAVE_RIIC7_TX, | ||
| 280 | SHDMA_SLAVE_RIIC7_RX, | ||
| 281 | SHDMA_SLAVE_RIIC8_TX, | ||
| 282 | SHDMA_SLAVE_RIIC8_RX, | ||
| 283 | SHDMA_SLAVE_RIIC9_TX, | ||
| 284 | SHDMA_SLAVE_RIIC9_RX, | ||
| 285 | }; | ||
| 254 | #endif /* __ASM_SH7757_H__ */ | 286 | #endif /* __ASM_SH7757_H__ */ |
