diff options
author | Kuninori Morimoto <morimoto.kuninori@renesas.com> | 2009-04-16 01:40:56 -0400 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2009-04-16 01:40:56 -0400 |
commit | 0207a2efb43d81e29e23662b5d035945688a103f (patch) | |
tree | b43cf6b34fd5c5d1f837c2915e4e055cbfb13883 /arch/sh/include/cpu-sh4/cpu/freq.h | |
parent | 3ee8da87ba6151ec91b2b8bbd27633bb248ea0d5 (diff) |
sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.
This implements initial support for the SH-Mobile R2R CPU.
Based on Rev 0.11 of the initial SH7724 hardware manual.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/freq.h')
-rw-r--r-- | arch/sh/include/cpu-sh4/cpu/freq.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h index 749d1c43433..ccf1d999db6 100644 --- a/arch/sh/include/cpu-sh4/cpu/freq.h +++ b/arch/sh/include/cpu-sh4/cpu/freq.h | |||
@@ -25,6 +25,24 @@ | |||
25 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | 25 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
26 | defined(CONFIG_CPU_SUBTYPE_SH7780) | 26 | defined(CONFIG_CPU_SUBTYPE_SH7780) |
27 | #define FRQCR 0xffc80000 | 27 | #define FRQCR 0xffc80000 |
28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
29 | #define FRQCRA 0xa4150000 | ||
30 | #define FRQCRB 0xa4150004 | ||
31 | #define VCLKCR 0xa4150048 | ||
32 | |||
33 | #define FCLKACR 0xa4150008 | ||
34 | #define FCLKBCR 0xa415000c | ||
35 | #define FRQCR FRQCRA | ||
36 | #define SCLKACR FCLKACR | ||
37 | #define SCLKBCR FCLKBCR | ||
38 | #define FCLKACR 0xa4150008 | ||
39 | #define FCLKBCR 0xa415000c | ||
40 | #define IrDACLKCR 0xa4150018 | ||
41 | |||
42 | #define MSTPCR0 0xa4150030 | ||
43 | #define MSTPCR1 0xa4150034 | ||
44 | #define MSTPCR2 0xa4150038 | ||
45 | |||
28 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) | 46 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
29 | #define FRQCR0 0xffc80000 | 47 | #define FRQCR0 0xffc80000 |
30 | #define FRQCR1 0xffc80004 | 48 | #define FRQCR1 0xffc80004 |