diff options
author | Paul Mundt <lethal@linux-sh.org> | 2012-05-19 05:50:09 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-19 05:50:09 -0400 |
commit | e24cca19babe33a7d05712df041f5abbeca4f1bf (patch) | |
tree | 59eac5df17932f08b2283ecf036dec2698f79d5f /arch/sh/include/asm | |
parent | 2ff9f317f15b7c3bd95273a7f04ca0b148850104 (diff) |
sh: Kill off MAX_DMA_ADDRESS leftovers.
We don't support the ISA DMA API, so this is only ever misused. The
dma-sh case inadvertently broke the dreamcast case by testing the wrong
variable for the total number of channels, so this fixes that up too.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm')
-rw-r--r-- | arch/sh/include/asm/dma-sh.h | 16 | ||||
-rw-r--r-- | arch/sh/include/asm/dma.h | 8 |
2 files changed, 8 insertions, 16 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index f3acb8e34c6..9a4875a8963 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h | |||
@@ -32,21 +32,21 @@ | |||
32 | #endif | 32 | #endif |
33 | 33 | ||
34 | static int dmte_irq_map[] __maybe_unused = { | 34 | static int dmte_irq_map[] __maybe_unused = { |
35 | #if (MAX_DMA_CHANNELS >= 4) | 35 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) |
36 | DMTE0_IRQ, | 36 | DMTE0_IRQ, |
37 | DMTE0_IRQ + 1, | 37 | DMTE0_IRQ + 1, |
38 | DMTE0_IRQ + 2, | 38 | DMTE0_IRQ + 2, |
39 | DMTE0_IRQ + 3, | 39 | DMTE0_IRQ + 3, |
40 | #endif | 40 | #endif |
41 | #if (MAX_DMA_CHANNELS >= 6) | 41 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) |
42 | DMTE4_IRQ, | 42 | DMTE4_IRQ, |
43 | DMTE4_IRQ + 1, | 43 | DMTE4_IRQ + 1, |
44 | #endif | 44 | #endif |
45 | #if (MAX_DMA_CHANNELS >= 8) | 45 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) |
46 | DMTE6_IRQ, | 46 | DMTE6_IRQ, |
47 | DMTE6_IRQ + 1, | 47 | DMTE6_IRQ + 1, |
48 | #endif | 48 | #endif |
49 | #if (MAX_DMA_CHANNELS >= 12) | 49 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) |
50 | DMTE8_IRQ, | 50 | DMTE8_IRQ, |
51 | DMTE9_IRQ, | 51 | DMTE9_IRQ, |
52 | DMTE10_IRQ, | 52 | DMTE10_IRQ, |
@@ -62,21 +62,21 @@ static int dmte_irq_map[] __maybe_unused = { | |||
62 | 62 | ||
63 | /* DMA base address */ | 63 | /* DMA base address */ |
64 | static u32 dma_base_addr[] __maybe_unused = { | 64 | static u32 dma_base_addr[] __maybe_unused = { |
65 | #if (MAX_DMA_CHANNELS >= 4) | 65 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) |
66 | SH_DMAC_BASE0 + 0x00, /* channel 0 */ | 66 | SH_DMAC_BASE0 + 0x00, /* channel 0 */ |
67 | SH_DMAC_BASE0 + 0x10, | 67 | SH_DMAC_BASE0 + 0x10, |
68 | SH_DMAC_BASE0 + 0x20, | 68 | SH_DMAC_BASE0 + 0x20, |
69 | SH_DMAC_BASE0 + 0x30, | 69 | SH_DMAC_BASE0 + 0x30, |
70 | #endif | 70 | #endif |
71 | #if (MAX_DMA_CHANNELS >= 6) | 71 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) |
72 | SH_DMAC_BASE0 + 0x50, | 72 | SH_DMAC_BASE0 + 0x50, |
73 | SH_DMAC_BASE0 + 0x60, | 73 | SH_DMAC_BASE0 + 0x60, |
74 | #endif | 74 | #endif |
75 | #if (MAX_DMA_CHANNELS >= 8) | 75 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) |
76 | SH_DMAC_BASE1 + 0x00, | 76 | SH_DMAC_BASE1 + 0x00, |
77 | SH_DMAC_BASE1 + 0x10, | 77 | SH_DMAC_BASE1 + 0x10, |
78 | #endif | 78 | #endif |
79 | #if (MAX_DMA_CHANNELS >= 12) | 79 | #if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) |
80 | SH_DMAC_BASE1 + 0x20, | 80 | SH_DMAC_BASE1 + 0x20, |
81 | SH_DMAC_BASE1 + 0x30, | 81 | SH_DMAC_BASE1 + 0x30, |
82 | SH_DMAC_BASE1 + 0x50, | 82 | SH_DMAC_BASE1 + 0x50, |
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h index e6c2871a00e..fb6e4f7b00a 100644 --- a/arch/sh/include/asm/dma.h +++ b/arch/sh/include/asm/dma.h | |||
@@ -17,14 +17,6 @@ | |||
17 | #include <linux/device.h> | 17 | #include <linux/device.h> |
18 | #include <asm-generic/dma.h> | 18 | #include <asm-generic/dma.h> |
19 | 19 | ||
20 | #ifdef CONFIG_NR_DMA_CHANNELS | ||
21 | # define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) | ||
22 | #elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS) | ||
23 | # define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) | ||
24 | #else | ||
25 | # define MAX_DMA_CHANNELS 0 | ||
26 | #endif | ||
27 | |||
28 | /* | 20 | /* |
29 | * Read and write modes can mean drastically different things depending on the | 21 | * Read and write modes can mean drastically different things depending on the |
30 | * channel configuration. Consult your DMAC documentation and module | 22 | * channel configuration. Consult your DMAC documentation and module |