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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 18:58:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 18:58:21 -0400
commit0195c00244dc2e9f522475868fa278c473ba7339 (patch)
treef97ca98ae64ede2c33ad3de05ed7bbfa4f4495ed /arch/sh/include/asm
parentf21ce8f8447c8be8847dadcfdbcc76b0d7365fa5 (diff)
parent141124c02059eee9dbc5c86ea797b1ca888e77f7 (diff)
Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-asm_system
Pull "Disintegrate and delete asm/system.h" from David Howells: "Here are a bunch of patches to disintegrate asm/system.h into a set of separate bits to relieve the problem of circular inclusion dependencies. I've built all the working defconfigs from all the arches that I can and made sure that they don't break. The reason for these patches is that I recently encountered a circular dependency problem that came about when I produced some patches to optimise get_order() by rewriting it to use ilog2(). This uses bitops - and on the SH arch asm/bitops.h drags in asm-generic/get_order.h by a circuituous route involving asm/system.h. The main difficulty seems to be asm/system.h. It holds a number of low level bits with no/few dependencies that are commonly used (eg. memory barriers) and a number of bits with more dependencies that aren't used in many places (eg. switch_to()). These patches break asm/system.h up into the following core pieces: (1) asm/barrier.h Move memory barriers here. This already done for MIPS and Alpha. (2) asm/switch_to.h Move switch_to() and related stuff here. (3) asm/exec.h Move arch_align_stack() here. Other process execution related bits could perhaps go here from asm/processor.h. (4) asm/cmpxchg.h Move xchg() and cmpxchg() here as they're full word atomic ops and frequently used by atomic_xchg() and atomic_cmpxchg(). (5) asm/bug.h Move die() and related bits. (6) asm/auxvec.h Move AT_VECTOR_SIZE_ARCH here. Other arch headers are created as needed on a per-arch basis." Fixed up some conflicts from other header file cleanups and moving code around that has happened in the meantime, so David's testing is somewhat weakened by that. We'll find out anything that got broken and fix it.. * tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-asm_system: (38 commits) Delete all instances of asm/system.h Remove all #inclusions of asm/system.h Add #includes needed to permit the removal of asm/system.h Move all declarations of free_initmem() to linux/mm.h Disintegrate asm/system.h for OpenRISC Split arch_align_stack() out from asm-generic/system.h Split the switch_to() wrapper out of asm-generic/system.h Move the asm-generic/system.h xchg() implementation to asm-generic/cmpxchg.h Create asm-generic/barrier.h Make asm-generic/cmpxchg.h #include asm-generic/cmpxchg-local.h Disintegrate asm/system.h for Xtensa Disintegrate asm/system.h for Unicore32 [based on ver #3, changed by gxt] Disintegrate asm/system.h for Tile Disintegrate asm/system.h for Sparc Disintegrate asm/system.h for SH Disintegrate asm/system.h for Score Disintegrate asm/system.h for S390 Disintegrate asm/system.h for PowerPC Disintegrate asm/system.h for PA-RISC Disintegrate asm/system.h for MN10300 ...
Diffstat (limited to 'arch/sh/include/asm')
-rw-r--r--arch/sh/include/asm/atomic-irq.h2
-rw-r--r--arch/sh/include/asm/atomic.h2
-rw-r--r--arch/sh/include/asm/auxvec.h2
-rw-r--r--arch/sh/include/asm/barrier.h54
-rw-r--r--arch/sh/include/asm/bitops.h1
-rw-r--r--arch/sh/include/asm/bl_bit.h10
-rw-r--r--arch/sh/include/asm/bl_bit_32.h33
-rw-r--r--arch/sh/include/asm/bl_bit_64.h40
-rw-r--r--arch/sh/include/asm/bug.h5
-rw-r--r--arch/sh/include/asm/cache_insns.h11
-rw-r--r--arch/sh/include/asm/cache_insns_32.h21
-rw-r--r--arch/sh/include/asm/cache_insns_64.h23
-rw-r--r--arch/sh/include/asm/cmpxchg-irq.h2
-rw-r--r--arch/sh/include/asm/cmpxchg.h70
-rw-r--r--arch/sh/include/asm/exec.h10
-rw-r--r--arch/sh/include/asm/futex-irq.h1
-rw-r--r--arch/sh/include/asm/io.h1
-rw-r--r--arch/sh/include/asm/processor.h15
-rw-r--r--arch/sh/include/asm/ptrace.h1
-rw-r--r--arch/sh/include/asm/setup.h1
-rw-r--r--arch/sh/include/asm/switch_to.h19
-rw-r--r--arch/sh/include/asm/switch_to_32.h (renamed from arch/sh/include/asm/system_32.h)108
-rw-r--r--arch/sh/include/asm/switch_to_64.h35
-rw-r--r--arch/sh/include/asm/system.h184
-rw-r--r--arch/sh/include/asm/system_64.h79
-rw-r--r--arch/sh/include/asm/traps.h21
-rw-r--r--arch/sh/include/asm/traps_32.h68
-rw-r--r--arch/sh/include/asm/traps_64.h24
-rw-r--r--arch/sh/include/asm/uaccess.h14
29 files changed, 484 insertions, 373 deletions
diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h
index 467d9415a32..9f7c56609e5 100644
--- a/arch/sh/include/asm/atomic-irq.h
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_SH_ATOMIC_IRQ_H 1#ifndef __ASM_SH_ATOMIC_IRQ_H
2#define __ASM_SH_ATOMIC_IRQ_H 2#define __ASM_SH_ATOMIC_IRQ_H
3 3
4#include <linux/irqflags.h>
5
4/* 6/*
5 * To get proper branch prediction for the main line, we must branch 7 * To get proper branch prediction for the main line, we must branch
6 * forward to code at the end of this object's .text section, then 8 * forward to code at the end of this object's .text section, then
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 63a27dbc952..37f2f4a5523 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -9,7 +9,7 @@
9 9
10#include <linux/compiler.h> 10#include <linux/compiler.h>
11#include <linux/types.h> 11#include <linux/types.h>
12#include <asm/system.h> 12#include <asm/cmpxchg.h>
13 13
14#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) 14#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
15 15
diff --git a/arch/sh/include/asm/auxvec.h b/arch/sh/include/asm/auxvec.h
index 483effd65e0..8bcc51af936 100644
--- a/arch/sh/include/asm/auxvec.h
+++ b/arch/sh/include/asm/auxvec.h
@@ -33,4 +33,6 @@
33#define AT_L1D_CACHESHAPE 35 33#define AT_L1D_CACHESHAPE 35
34#define AT_L2_CACHESHAPE 36 34#define AT_L2_CACHESHAPE 36
35 35
36#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
37
36#endif /* __ASM_SH_AUXVEC_H */ 38#endif /* __ASM_SH_AUXVEC_H */
diff --git a/arch/sh/include/asm/barrier.h b/arch/sh/include/asm/barrier.h
new file mode 100644
index 00000000000..72c103dae30
--- /dev/null
+++ b/arch/sh/include/asm/barrier.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
3 * Copyright (C) 2002 Paul Mundt
4 */
5#ifndef __ASM_SH_BARRIER_H
6#define __ASM_SH_BARRIER_H
7
8#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
9#include <asm/cache_insns.h>
10#endif
11
12/*
13 * A brief note on ctrl_barrier(), the control register write barrier.
14 *
15 * Legacy SH cores typically require a sequence of 8 nops after
16 * modification of a control register in order for the changes to take
17 * effect. On newer cores (like the sh4a and sh5) this is accomplished
18 * with icbi.
19 *
20 * Also note that on sh4a in the icbi case we can forego a synco for the
21 * write barrier, as it's not necessary for control registers.
22 *
23 * Historically we have only done this type of barrier for the MMUCR, but
24 * it's also necessary for the CCR, so we make it generic here instead.
25 */
26#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
27#define mb() __asm__ __volatile__ ("synco": : :"memory")
28#define rmb() mb()
29#define wmb() __asm__ __volatile__ ("synco": : :"memory")
30#define ctrl_barrier() __icbi(PAGE_OFFSET)
31#define read_barrier_depends() do { } while(0)
32#else
33#define mb() __asm__ __volatile__ ("": : :"memory")
34#define rmb() mb()
35#define wmb() __asm__ __volatile__ ("": : :"memory")
36#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
37#define read_barrier_depends() do { } while(0)
38#endif
39
40#ifdef CONFIG_SMP
41#define smp_mb() mb()
42#define smp_rmb() rmb()
43#define smp_wmb() wmb()
44#define smp_read_barrier_depends() read_barrier_depends()
45#else
46#define smp_mb() barrier()
47#define smp_rmb() barrier()
48#define smp_wmb() barrier()
49#define smp_read_barrier_depends() do { } while(0)
50#endif
51
52#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
53
54#endif /* __ASM_SH_BARRIER_H */
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
index 90fa3e48b4d..ea8706d94f0 100644
--- a/arch/sh/include/asm/bitops.h
+++ b/arch/sh/include/asm/bitops.h
@@ -7,7 +7,6 @@
7#error only <linux/bitops.h> can be included directly 7#error only <linux/bitops.h> can be included directly
8#endif 8#endif
9 9
10#include <asm/system.h>
11/* For __swab32 */ 10/* For __swab32 */
12#include <asm/byteorder.h> 11#include <asm/byteorder.h>
13 12
diff --git a/arch/sh/include/asm/bl_bit.h b/arch/sh/include/asm/bl_bit.h
new file mode 100644
index 00000000000..45e6b9fc37a
--- /dev/null
+++ b/arch/sh/include/asm/bl_bit.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_SH_BL_BIT_H
2#define __ASM_SH_BL_BIT_H
3
4#ifdef CONFIG_SUPERH32
5# include "bl_bit_32.h"
6#else
7# include "bl_bit_64.h"
8#endif
9
10#endif /* __ASM_SH_BL_BIT_H */
diff --git a/arch/sh/include/asm/bl_bit_32.h b/arch/sh/include/asm/bl_bit_32.h
new file mode 100644
index 00000000000..fd21eee6214
--- /dev/null
+++ b/arch/sh/include/asm/bl_bit_32.h
@@ -0,0 +1,33 @@
1#ifndef __ASM_SH_BL_BIT_32_H
2#define __ASM_SH_BL_BIT_32_H
3
4static inline void set_bl_bit(void)
5{
6 unsigned long __dummy0, __dummy1;
7
8 __asm__ __volatile__ (
9 "stc sr, %0\n\t"
10 "or %2, %0\n\t"
11 "and %3, %0\n\t"
12 "ldc %0, sr\n\t"
13 : "=&r" (__dummy0), "=r" (__dummy1)
14 : "r" (0x10000000), "r" (0xffffff0f)
15 : "memory"
16 );
17}
18
19static inline void clear_bl_bit(void)
20{
21 unsigned long __dummy0, __dummy1;
22
23 __asm__ __volatile__ (
24 "stc sr, %0\n\t"
25 "and %2, %0\n\t"
26 "ldc %0, sr\n\t"
27 : "=&r" (__dummy0), "=r" (__dummy1)
28 : "1" (~0x10000000)
29 : "memory"
30 );
31}
32
33#endif /* __ASM_SH_BL_BIT_32_H */
diff --git a/arch/sh/include/asm/bl_bit_64.h b/arch/sh/include/asm/bl_bit_64.h
new file mode 100644
index 00000000000..6cc8711af43
--- /dev/null
+++ b/arch/sh/include/asm/bl_bit_64.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2000, 2001 Paolo Alberelli
3 * Copyright (C) 2003 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_BL_BIT_64_H
11#define __ASM_SH_BL_BIT_64_H
12
13#include <asm/processor.h>
14
15#define SR_BL_LL 0x0000000010000000LL
16
17static inline void set_bl_bit(void)
18{
19 unsigned long long __dummy0, __dummy1 = SR_BL_LL;
20
21 __asm__ __volatile__("getcon " __SR ", %0\n\t"
22 "or %0, %1, %0\n\t"
23 "putcon %0, " __SR "\n\t"
24 : "=&r" (__dummy0)
25 : "r" (__dummy1));
26
27}
28
29static inline void clear_bl_bit(void)
30{
31 unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
32
33 __asm__ __volatile__("getcon " __SR ", %0\n\t"
34 "and %0, %1, %0\n\t"
35 "putcon %0, " __SR "\n\t"
36 : "=&r" (__dummy0)
37 : "r" (__dummy1));
38}
39
40#endif /* __ASM_SH_BL_BIT_64_H */
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
index 6323f864d11..2b87d86bfc4 100644
--- a/arch/sh/include/asm/bug.h
+++ b/arch/sh/include/asm/bug.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_SH_BUG_H 1#ifndef __ASM_SH_BUG_H
2#define __ASM_SH_BUG_H 2#define __ASM_SH_BUG_H
3 3
4#include <linux/linkage.h>
5
4#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */ 6#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
5#define BUGFLAG_UNWINDER (1 << 1) 7#define BUGFLAG_UNWINDER (1 << 1)
6 8
@@ -107,4 +109,7 @@ do { \
107 109
108#include <asm-generic/bug.h> 110#include <asm-generic/bug.h>
109 111
112struct pt_regs;
113extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
114
110#endif /* __ASM_SH_BUG_H */ 115#endif /* __ASM_SH_BUG_H */
diff --git a/arch/sh/include/asm/cache_insns.h b/arch/sh/include/asm/cache_insns.h
new file mode 100644
index 00000000000..d25fbe53090
--- /dev/null
+++ b/arch/sh/include/asm/cache_insns.h
@@ -0,0 +1,11 @@
1#ifndef __ASM_SH_CACHE_INSNS_H
2#define __ASM_SH_CACHE_INSNS_H
3
4
5#ifdef CONFIG_SUPERH32
6# include "cache_insns_32.h"
7#else
8# include "cache_insns_64.h"
9#endif
10
11#endif /* __ASM_SH_CACHE_INSNS_H */
diff --git a/arch/sh/include/asm/cache_insns_32.h b/arch/sh/include/asm/cache_insns_32.h
new file mode 100644
index 00000000000..b92fe541609
--- /dev/null
+++ b/arch/sh/include/asm/cache_insns_32.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_SH_CACHE_INSNS_32_H
2#define __ASM_SH_CACHE_INSNS_32_H
3
4#include <linux/types.h>
5
6#if defined(CONFIG_CPU_SH4A)
7#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
8#else
9#define __icbi(addr) mb()
10#endif
11
12#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
13#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
14#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
15
16static inline reg_size_t register_align(void *val)
17{
18 return (unsigned long)(signed long)val;
19}
20
21#endif /* __ASM_SH_CACHE_INSNS_32_H */
diff --git a/arch/sh/include/asm/cache_insns_64.h b/arch/sh/include/asm/cache_insns_64.h
new file mode 100644
index 00000000000..70b6357eaf1
--- /dev/null
+++ b/arch/sh/include/asm/cache_insns_64.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2000, 2001 Paolo Alberelli
3 * Copyright (C) 2003 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_CACHE_INSNS_64_H
11#define __ASM_SH_CACHE_INSNS_64_H
12
13#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
14#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
15#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
16#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
17
18static inline reg_size_t register_align(void *val)
19{
20 return (unsigned long long)(signed long long)(signed long)val;
21}
22
23#endif /* __ASM_SH_CACHE_INSNS_64_H */
diff --git a/arch/sh/include/asm/cmpxchg-irq.h b/arch/sh/include/asm/cmpxchg-irq.h
index 43049ec0554..bd11f630414 100644
--- a/arch/sh/include/asm/cmpxchg-irq.h
+++ b/arch/sh/include/asm/cmpxchg-irq.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_SH_CMPXCHG_IRQ_H 1#ifndef __ASM_SH_CMPXCHG_IRQ_H
2#define __ASM_SH_CMPXCHG_IRQ_H 2#define __ASM_SH_CMPXCHG_IRQ_H
3 3
4#include <linux/irqflags.h>
5
4static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) 6static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
5{ 7{
6 unsigned long flags, retval; 8 unsigned long flags, retval;
diff --git a/arch/sh/include/asm/cmpxchg.h b/arch/sh/include/asm/cmpxchg.h
new file mode 100644
index 00000000000..f6bd1406b89
--- /dev/null
+++ b/arch/sh/include/asm/cmpxchg.h
@@ -0,0 +1,70 @@
1#ifndef __ASM_SH_CMPXCHG_H
2#define __ASM_SH_CMPXCHG_H
3
4/*
5 * Atomic operations that C can't guarantee us. Useful for
6 * resource counting etc..
7 */
8
9#include <linux/compiler.h>
10#include <linux/types.h>
11
12#if defined(CONFIG_GUSA_RB)
13#include <asm/cmpxchg-grb.h>
14#elif defined(CONFIG_CPU_SH4A)
15#include <asm/cmpxchg-llsc.h>
16#else
17#include <asm/cmpxchg-irq.h>
18#endif
19
20extern void __xchg_called_with_bad_pointer(void);
21
22#define __xchg(ptr, x, size) \
23({ \
24 unsigned long __xchg__res; \
25 volatile void *__xchg_ptr = (ptr); \
26 switch (size) { \
27 case 4: \
28 __xchg__res = xchg_u32(__xchg_ptr, x); \
29 break; \
30 case 1: \
31 __xchg__res = xchg_u8(__xchg_ptr, x); \
32 break; \
33 default: \
34 __xchg_called_with_bad_pointer(); \
35 __xchg__res = x; \
36 break; \
37 } \
38 \
39 __xchg__res; \
40})
41
42#define xchg(ptr,x) \
43 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
44
45/* This function doesn't exist, so you'll get a linker error
46 * if something tries to do an invalid cmpxchg(). */
47extern void __cmpxchg_called_with_bad_pointer(void);
48
49#define __HAVE_ARCH_CMPXCHG 1
50
51static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
52 unsigned long new, int size)
53{
54 switch (size) {
55 case 4:
56 return __cmpxchg_u32(ptr, old, new);
57 }
58 __cmpxchg_called_with_bad_pointer();
59 return old;
60}
61
62#define cmpxchg(ptr,o,n) \
63 ({ \
64 __typeof__(*(ptr)) _o_ = (o); \
65 __typeof__(*(ptr)) _n_ = (n); \
66 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
67 (unsigned long)_n_, sizeof(*(ptr))); \
68 })
69
70#endif /* __ASM_SH_CMPXCHG_H */
diff --git a/arch/sh/include/asm/exec.h b/arch/sh/include/asm/exec.h
new file mode 100644
index 00000000000..69486a9497f
--- /dev/null
+++ b/arch/sh/include/asm/exec.h
@@ -0,0 +1,10 @@
1/*
2 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
3 * Copyright (C) 2002 Paul Mundt
4 */
5#ifndef __ASM_SH_EXEC_H
6#define __ASM_SH_EXEC_H
7
8#define arch_align_stack(x) (x)
9
10#endif /* __ASM_SH_EXEC_H */
diff --git a/arch/sh/include/asm/futex-irq.h b/arch/sh/include/asm/futex-irq.h
index 6cb9f193a95..63d33129ea2 100644
--- a/arch/sh/include/asm/futex-irq.h
+++ b/arch/sh/include/asm/futex-irq.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_SH_FUTEX_IRQ_H 1#ifndef __ASM_SH_FUTEX_IRQ_H
2#define __ASM_SH_FUTEX_IRQ_H 2#define __ASM_SH_FUTEX_IRQ_H
3 3
4#include <asm/system.h>
5 4
6static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, 5static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr,
7 int *oldval) 6 int *oldval)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 28c5aa58bb4..35fc8b077cb 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -14,7 +14,6 @@
14 */ 14 */
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/system.h>
18#include <asm/addrspace.h> 17#include <asm/addrspace.h>
19#include <asm/machvec.h> 18#include <asm/machvec.h>
20#include <asm/pgtable.h> 19#include <asm/pgtable.h>
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 9c7bdfcaebb..a229c393826 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -101,6 +101,10 @@ extern struct sh_cpuinfo cpu_data[];
101#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 101#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
102#define cpu_relax() barrier() 102#define cpu_relax() barrier()
103 103
104void default_idle(void);
105void cpu_idle_wait(void);
106void stop_this_cpu(void *);
107
104/* Forward decl */ 108/* Forward decl */
105struct seq_operations; 109struct seq_operations;
106struct task_struct; 110struct task_struct;
@@ -161,6 +165,17 @@ int vsyscall_init(void);
161#define vsyscall_init() do { } while (0) 165#define vsyscall_init() do { } while (0)
162#endif 166#endif
163 167
168/*
169 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
170 */
171#ifdef CONFIG_CPU_SH2A
172extern unsigned int instruction_size(unsigned int insn);
173#elif defined(CONFIG_SUPERH32)
174#define instruction_size(insn) (2)
175#else
176#define instruction_size(insn) (4)
177#endif
178
164#endif /* __ASSEMBLY__ */ 179#endif /* __ASSEMBLY__ */
165 180
166#ifdef CONFIG_SUPERH32 181#ifdef CONFIG_SUPERH32
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 2d3679b2447..c7b7e1ed194 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -37,7 +37,6 @@
37#include <linux/thread_info.h> 37#include <linux/thread_info.h>
38#include <asm/addrspace.h> 38#include <asm/addrspace.h>
39#include <asm/page.h> 39#include <asm/page.h>
40#include <asm/system.h>
41 40
42#define user_mode(regs) (((regs)->sr & 0x40000000)==0) 41#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
43#define kernel_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15]) 42#define kernel_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15])
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
index 01fa17a3d75..465a22df8fd 100644
--- a/arch/sh/include/asm/setup.h
+++ b/arch/sh/include/asm/setup.h
@@ -20,6 +20,7 @@
20 20
21void sh_mv_setup(void); 21void sh_mv_setup(void);
22void check_for_initrd(void); 22void check_for_initrd(void);
23void per_cpu_trap_init(void);
23 24
24#endif /* __KERNEL__ */ 25#endif /* __KERNEL__ */
25 26
diff --git a/arch/sh/include/asm/switch_to.h b/arch/sh/include/asm/switch_to.h
new file mode 100644
index 00000000000..62b1941813e
--- /dev/null
+++ b/arch/sh/include/asm/switch_to.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (C) 2000, 2001 Paolo Alberelli
3 * Copyright (C) 2003 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_SWITCH_TO_H
11#define __ASM_SH_SWITCH_TO_H
12
13#ifdef CONFIG_SUPERH32
14# include "switch_to_32.h"
15#else
16# include "switch_to_64.h"
17#endif
18
19#endif /* __ASM_SH_SWITCH_TO_H */
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/switch_to_32.h
index a4ad1cd9bc4..0c065513e7a 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/switch_to_32.h
@@ -1,8 +1,5 @@
1#ifndef __ASM_SH_SYSTEM_32_H 1#ifndef __ASM_SH_SWITCH_TO_32_H
2#define __ASM_SH_SYSTEM_32_H 2#define __ASM_SH_SWITCH_TO_32_H
3
4#include <linux/types.h>
5#include <asm/mmu.h>
6 3
7#ifdef CONFIG_SH_DSP 4#ifdef CONFIG_SH_DSP
8 5
@@ -32,7 +29,6 @@ do { \
32 : : "r" (__ts2)); \ 29 : : "r" (__ts2)); \
33} while (0) 30} while (0)
34 31
35
36#define __save_dsp(tsk) \ 32#define __save_dsp(tsk) \
37do { \ 33do { \
38 register u32 *__ts2 __asm__ ("r2") = \ 34 register u32 *__ts2 __asm__ ("r2") = \
@@ -64,16 +60,6 @@ do { \
64#define __restore_dsp(tsk) do { } while (0) 60#define __restore_dsp(tsk) do { } while (0)
65#endif 61#endif
66 62
67#if defined(CONFIG_CPU_SH4A)
68#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
69#else
70#define __icbi(addr) mb()
71#endif
72
73#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
74#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
75#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
76
77struct task_struct *__switch_to(struct task_struct *prev, 63struct task_struct *__switch_to(struct task_struct *prev,
78 struct task_struct *next); 64 struct task_struct *next);
79 65
@@ -145,92 +131,4 @@ do { \
145 __restore_dsp(prev); \ 131 __restore_dsp(prev); \
146} while (0) 132} while (0)
147 133
148#ifdef CONFIG_CPU_HAS_SR_RB 134#endif /* __ASM_SH_SWITCH_TO_32_H */
149#define lookup_exception_vector() \
150({ \
151 unsigned long _vec; \
152 \
153 __asm__ __volatile__ ( \
154 "stc r2_bank, %0\n\t" \
155 : "=r" (_vec) \
156 ); \
157 \
158 _vec; \
159})
160#else
161#define lookup_exception_vector() \
162({ \
163 unsigned long _vec; \
164 __asm__ __volatile__ ( \
165 "mov r4, %0\n\t" \
166 : "=r" (_vec) \
167 ); \
168 \
169 _vec; \
170})
171#endif
172
173static inline reg_size_t register_align(void *val)
174{
175 return (unsigned long)(signed long)val;
176}
177
178int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
179 struct mem_access *ma, int, unsigned long address);
180
181static inline void trigger_address_error(void)
182{
183 __asm__ __volatile__ (
184 "ldc %0, sr\n\t"
185 "mov.l @%1, %0"
186 :
187 : "r" (0x10000000), "r" (0x80000001)
188 );
189}
190
191asmlinkage void do_address_error(struct pt_regs *regs,
192 unsigned long writeaccess,
193 unsigned long address);
194asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
195 unsigned long r6, unsigned long r7,
196 struct pt_regs __regs);
197asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
198 unsigned long r6, unsigned long r7,
199 struct pt_regs __regs);
200asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
201 unsigned long r6, unsigned long r7,
202 struct pt_regs __regs);
203asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
204 unsigned long r6, unsigned long r7,
205 struct pt_regs __regs);
206
207static inline void set_bl_bit(void)
208{
209 unsigned long __dummy0, __dummy1;
210
211 __asm__ __volatile__ (
212 "stc sr, %0\n\t"
213 "or %2, %0\n\t"
214 "and %3, %0\n\t"
215 "ldc %0, sr\n\t"
216 : "=&r" (__dummy0), "=r" (__dummy1)
217 : "r" (0x10000000), "r" (0xffffff0f)
218 : "memory"
219 );
220}
221
222static inline void clear_bl_bit(void)
223{
224 unsigned long __dummy0, __dummy1;
225
226 __asm__ __volatile__ (
227 "stc sr, %0\n\t"
228 "and %2, %0\n\t"
229 "ldc %0, sr\n\t"
230 : "=&r" (__dummy0), "=r" (__dummy1)
231 : "1" (~0x10000000)
232 : "memory"
233 );
234}
235
236#endif /* __ASM_SH_SYSTEM_32_H */
diff --git a/arch/sh/include/asm/switch_to_64.h b/arch/sh/include/asm/switch_to_64.h
new file mode 100644
index 00000000000..ba3129d6bc2
--- /dev/null
+++ b/arch/sh/include/asm/switch_to_64.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2000, 2001 Paolo Alberelli
3 * Copyright (C) 2003 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_SWITCH_TO_64_H
11#define __ASM_SH_SWITCH_TO_64_H
12
13struct thread_struct;
14struct task_struct;
15
16/*
17 * switch_to() should switch tasks to task nr n, first
18 */
19struct task_struct *sh64_switch_to(struct task_struct *prev,
20 struct thread_struct *prev_thread,
21 struct task_struct *next,
22 struct thread_struct *next_thread);
23
24#define switch_to(prev,next,last) \
25do { \
26 if (last_task_used_math != next) { \
27 struct pt_regs *regs = next->thread.uregs; \
28 if (regs) regs->sr |= SR_FD; \
29 } \
30 last = sh64_switch_to(prev, &prev->thread, next, \
31 &next->thread); \
32} while (0)
33
34
35#endif /* __ASM_SH_SWITCH_TO_64_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
deleted file mode 100644
index 10c8b1823a1..00000000000
--- a/arch/sh/include/asm/system.h
+++ /dev/null
@@ -1,184 +0,0 @@
1#ifndef __ASM_SH_SYSTEM_H
2#define __ASM_SH_SYSTEM_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
7 */
8
9#include <linux/irqflags.h>
10#include <linux/compiler.h>
11#include <linux/linkage.h>
12#include <asm/types.h>
13#include <asm/uncached.h>
14
15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16
17/*
18 * A brief note on ctrl_barrier(), the control register write barrier.
19 *
20 * Legacy SH cores typically require a sequence of 8 nops after
21 * modification of a control register in order for the changes to take
22 * effect. On newer cores (like the sh4a and sh5) this is accomplished
23 * with icbi.
24 *
25 * Also note that on sh4a in the icbi case we can forego a synco for the
26 * write barrier, as it's not necessary for control registers.
27 *
28 * Historically we have only done this type of barrier for the MMUCR, but
29 * it's also necessary for the CCR, so we make it generic here instead.
30 */
31#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
32#define mb() __asm__ __volatile__ ("synco": : :"memory")
33#define rmb() mb()
34#define wmb() __asm__ __volatile__ ("synco": : :"memory")
35#define ctrl_barrier() __icbi(PAGE_OFFSET)
36#define read_barrier_depends() do { } while(0)
37#else
38#define mb() __asm__ __volatile__ ("": : :"memory")
39#define rmb() mb()
40#define wmb() __asm__ __volatile__ ("": : :"memory")
41#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
42#define read_barrier_depends() do { } while(0)
43#endif
44
45#ifdef CONFIG_SMP
46#define smp_mb() mb()
47#define smp_rmb() rmb()
48#define smp_wmb() wmb()
49#define smp_read_barrier_depends() read_barrier_depends()
50#else
51#define smp_mb() barrier()
52#define smp_rmb() barrier()
53#define smp_wmb() barrier()
54#define smp_read_barrier_depends() do { } while(0)
55#endif
56
57#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
58
59#ifdef CONFIG_GUSA_RB
60#include <asm/cmpxchg-grb.h>
61#elif defined(CONFIG_CPU_SH4A)
62#include <asm/cmpxchg-llsc.h>
63#else
64#include <asm/cmpxchg-irq.h>
65#endif
66
67extern void __xchg_called_with_bad_pointer(void);
68
69#define __xchg(ptr, x, size) \
70({ \
71 unsigned long __xchg__res; \
72 volatile void *__xchg_ptr = (ptr); \
73 switch (size) { \
74 case 4: \
75 __xchg__res = xchg_u32(__xchg_ptr, x); \
76 break; \
77 case 1: \
78 __xchg__res = xchg_u8(__xchg_ptr, x); \
79 break; \
80 default: \
81 __xchg_called_with_bad_pointer(); \
82 __xchg__res = x; \
83 break; \
84 } \
85 \
86 __xchg__res; \
87})
88
89#define xchg(ptr,x) \
90 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
91
92/* This function doesn't exist, so you'll get a linker error
93 * if something tries to do an invalid cmpxchg(). */
94extern void __cmpxchg_called_with_bad_pointer(void);
95
96#define __HAVE_ARCH_CMPXCHG 1
97
98static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
99 unsigned long new, int size)
100{
101 switch (size) {
102 case 4:
103 return __cmpxchg_u32(ptr, old, new);
104 }
105 __cmpxchg_called_with_bad_pointer();
106 return old;
107}
108
109#define cmpxchg(ptr,o,n) \
110 ({ \
111 __typeof__(*(ptr)) _o_ = (o); \
112 __typeof__(*(ptr)) _n_ = (n); \
113 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
114 (unsigned long)_n_, sizeof(*(ptr))); \
115 })
116
117struct pt_regs;
118
119extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
120void free_initmem(void);
121void free_initrd_mem(unsigned long start, unsigned long end);
122
123extern void *set_exception_table_vec(unsigned int vec, void *handler);
124
125static inline void *set_exception_table_evt(unsigned int evt, void *handler)
126{
127 return set_exception_table_vec(evt >> 5, handler);
128}
129
130/*
131 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
132 */
133#ifdef CONFIG_CPU_SH2A
134extern unsigned int instruction_size(unsigned int insn);
135#elif defined(CONFIG_SUPERH32)
136#define instruction_size(insn) (2)
137#else
138#define instruction_size(insn) (4)
139#endif
140
141void per_cpu_trap_init(void);
142void default_idle(void);
143void cpu_idle_wait(void);
144void stop_this_cpu(void *);
145
146#ifdef CONFIG_SUPERH32
147#define BUILD_TRAP_HANDLER(name) \
148asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
149 unsigned long r6, unsigned long r7, \
150 struct pt_regs __regs)
151
152#define TRAP_HANDLER_DECL \
153 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
154 unsigned int vec = regs->tra; \
155 (void)vec;
156#else
157#define BUILD_TRAP_HANDLER(name) \
158asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
159#define TRAP_HANDLER_DECL
160#endif
161
162BUILD_TRAP_HANDLER(address_error);
163BUILD_TRAP_HANDLER(debug);
164BUILD_TRAP_HANDLER(bug);
165BUILD_TRAP_HANDLER(breakpoint);
166BUILD_TRAP_HANDLER(singlestep);
167BUILD_TRAP_HANDLER(fpu_error);
168BUILD_TRAP_HANDLER(fpu_state_restore);
169BUILD_TRAP_HANDLER(nmi);
170
171#define arch_align_stack(x) (x)
172
173struct mem_access {
174 unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
175 unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
176};
177
178#ifdef CONFIG_SUPERH32
179# include "system_32.h"
180#else
181# include "system_64.h"
182#endif
183
184#endif
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
deleted file mode 100644
index 8593bc8d1a4..00000000000
--- a/arch/sh/include/asm/system_64.h
+++ /dev/null
@@ -1,79 +0,0 @@
1#ifndef __ASM_SH_SYSTEM_64_H
2#define __ASM_SH_SYSTEM_64_H
3
4/*
5 * include/asm-sh/system_64.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003 Paul Mundt
9 * Copyright (C) 2004 Richard Curnow
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <cpu/registers.h>
16#include <asm/processor.h>
17
18/*
19 * switch_to() should switch tasks to task nr n, first
20 */
21struct thread_struct;
22struct task_struct *sh64_switch_to(struct task_struct *prev,
23 struct thread_struct *prev_thread,
24 struct task_struct *next,
25 struct thread_struct *next_thread);
26
27#define switch_to(prev,next,last) \
28do { \
29 if (last_task_used_math != next) { \
30 struct pt_regs *regs = next->thread.uregs; \
31 if (regs) regs->sr |= SR_FD; \
32 } \
33 last = sh64_switch_to(prev, &prev->thread, next, \
34 &next->thread); \
35} while (0)
36
37#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
38#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
39#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
40#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
41
42static inline reg_size_t register_align(void *val)
43{
44 return (unsigned long long)(signed long long)(signed long)val;
45}
46
47extern void phys_stext(void);
48
49static inline void trigger_address_error(void)
50{
51 phys_stext();
52}
53
54#define SR_BL_LL 0x0000000010000000LL
55
56static inline void set_bl_bit(void)
57{
58 unsigned long long __dummy0, __dummy1 = SR_BL_LL;
59
60 __asm__ __volatile__("getcon " __SR ", %0\n\t"
61 "or %0, %1, %0\n\t"
62 "putcon %0, " __SR "\n\t"
63 : "=&r" (__dummy0)
64 : "r" (__dummy1));
65
66}
67
68static inline void clear_bl_bit(void)
69{
70 unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
71
72 __asm__ __volatile__("getcon " __SR ", %0\n\t"
73 "and %0, %1, %0\n\t"
74 "putcon %0, " __SR "\n\t"
75 : "=&r" (__dummy0)
76 : "r" (__dummy1));
77}
78
79#endif /* __ASM_SH_SYSTEM_64_H */
diff --git a/arch/sh/include/asm/traps.h b/arch/sh/include/asm/traps.h
new file mode 100644
index 00000000000..afd9df8d064
--- /dev/null
+++ b/arch/sh/include/asm/traps.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_SH_TRAPS_H
2#define __ASM_SH_TRAPS_H
3
4#include <linux/compiler.h>
5
6#ifdef CONFIG_SUPERH32
7# include "traps_32.h"
8#else
9# include "traps_64.h"
10#endif
11
12BUILD_TRAP_HANDLER(address_error);
13BUILD_TRAP_HANDLER(debug);
14BUILD_TRAP_HANDLER(bug);
15BUILD_TRAP_HANDLER(breakpoint);
16BUILD_TRAP_HANDLER(singlestep);
17BUILD_TRAP_HANDLER(fpu_error);
18BUILD_TRAP_HANDLER(fpu_state_restore);
19BUILD_TRAP_HANDLER(nmi);
20
21#endif /* __ASM_SH_TRAPS_H */
diff --git a/arch/sh/include/asm/traps_32.h b/arch/sh/include/asm/traps_32.h
new file mode 100644
index 00000000000..cfd55ff9dff
--- /dev/null
+++ b/arch/sh/include/asm/traps_32.h
@@ -0,0 +1,68 @@
1#ifndef __ASM_SH_TRAPS_32_H
2#define __ASM_SH_TRAPS_32_H
3
4#include <linux/types.h>
5#include <asm/mmu.h>
6
7#ifdef CONFIG_CPU_HAS_SR_RB
8#define lookup_exception_vector() \
9({ \
10 unsigned long _vec; \
11 \
12 __asm__ __volatile__ ( \
13 "stc r2_bank, %0\n\t" \
14 : "=r" (_vec) \
15 ); \
16 \
17 _vec; \
18})
19#else
20#define lookup_exception_vector() \
21({ \
22 unsigned long _vec; \
23 __asm__ __volatile__ ( \
24 "mov r4, %0\n\t" \
25 : "=r" (_vec) \
26 ); \
27 \
28 _vec; \
29})
30#endif
31
32static inline void trigger_address_error(void)
33{
34 __asm__ __volatile__ (
35 "ldc %0, sr\n\t"
36 "mov.l @%1, %0"
37 :
38 : "r" (0x10000000), "r" (0x80000001)
39 );
40}
41
42asmlinkage void do_address_error(struct pt_regs *regs,
43 unsigned long writeaccess,
44 unsigned long address);
45asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
46 unsigned long r6, unsigned long r7,
47 struct pt_regs __regs);
48asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
49 unsigned long r6, unsigned long r7,
50 struct pt_regs __regs);
51asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
52 unsigned long r6, unsigned long r7,
53 struct pt_regs __regs);
54asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
55 unsigned long r6, unsigned long r7,
56 struct pt_regs __regs);
57
58#define BUILD_TRAP_HANDLER(name) \
59asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
60 unsigned long r6, unsigned long r7, \
61 struct pt_regs __regs)
62
63#define TRAP_HANDLER_DECL \
64 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
65 unsigned int vec = regs->tra; \
66 (void)vec;
67
68#endif /* __ASM_SH_TRAPS_32_H */
diff --git a/arch/sh/include/asm/traps_64.h b/arch/sh/include/asm/traps_64.h
new file mode 100644
index 00000000000..c52d7f9a06c
--- /dev/null
+++ b/arch/sh/include/asm/traps_64.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (C) 2000, 2001 Paolo Alberelli
3 * Copyright (C) 2003 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_TRAPS_64_H
11#define __ASM_SH_TRAPS_64_H
12
13extern void phys_stext(void);
14
15static inline void trigger_address_error(void)
16{
17 phys_stext();
18}
19
20#define BUILD_TRAP_HANDLER(name) \
21asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
22#define TRAP_HANDLER_DECL
23
24#endif /* __ASM_SH_TRAPS_64_H */
diff --git a/arch/sh/include/asm/uaccess.h b/arch/sh/include/asm/uaccess.h
index 075848f43b6..050f221fa89 100644
--- a/arch/sh/include/asm/uaccess.h
+++ b/arch/sh/include/asm/uaccess.h
@@ -254,5 +254,19 @@ int fixup_exception(struct pt_regs *regs);
254unsigned long search_exception_table(unsigned long addr); 254unsigned long search_exception_table(unsigned long addr);
255const struct exception_table_entry *search_exception_tables(unsigned long addr); 255const struct exception_table_entry *search_exception_tables(unsigned long addr);
256 256
257extern void *set_exception_table_vec(unsigned int vec, void *handler);
258
259static inline void *set_exception_table_evt(unsigned int evt, void *handler)
260{
261 return set_exception_table_vec(evt >> 5, handler);
262}
263
264struct mem_access {
265 unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
266 unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
267};
268
269int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
270 struct mem_access *ma, int, unsigned long address);
257 271
258#endif /* __ASM_SH_UACCESS_H */ 272#endif /* __ASM_SH_UACCESS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 05:45:51 -0500