diff options
author | Andy Fleming <afleming@freescale.com> | 2005-10-28 20:46:27 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-10-29 00:42:28 -0400 |
commit | b37665e0ba1d3f05697bfae249b09a2e9cc95132 (patch) | |
tree | 22c80609e3254524038d5b690f1f886b0987f58d /arch/ppc/platforms/85xx/mpc85xx_cds_common.c | |
parent | dd03d25fac90ee6f394874fb4e6995866304e4ba (diff) |
[PATCH] ppc32: 85xx PHY Platform Update
This patch updates the 85xx platform code to support the new PHY Layer.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <Kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms/85xx/mpc85xx_cds_common.c')
-rw-r--r-- | arch/ppc/platforms/85xx/mpc85xx_cds_common.c | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index eda659916f2..a21156967a5 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c | |||
@@ -391,6 +391,9 @@ mpc85xx_cds_pcibios_fixup(void) | |||
391 | 391 | ||
392 | TODC_ALLOC(); | 392 | TODC_ALLOC(); |
393 | 393 | ||
394 | static const char *GFAR_PHY_0 = "phy0:0"; | ||
395 | static const char *GFAR_PHY_1 = "phy0:1"; | ||
396 | |||
394 | /* ************************************************************************ | 397 | /* ************************************************************************ |
395 | * | 398 | * |
396 | * Setup the architecture | 399 | * Setup the architecture |
@@ -402,6 +405,7 @@ mpc85xx_cds_setup_arch(void) | |||
402 | bd_t *binfo = (bd_t *) __res; | 405 | bd_t *binfo = (bd_t *) __res; |
403 | unsigned int freq; | 406 | unsigned int freq; |
404 | struct gianfar_platform_data *pdata; | 407 | struct gianfar_platform_data *pdata; |
408 | struct gianfar_mdio_data *mdata; | ||
405 | 409 | ||
406 | /* get the core frequency */ | 410 | /* get the core frequency */ |
407 | freq = binfo->bi_intfreq; | 411 | freq = binfo->bi_intfreq; |
@@ -445,44 +449,42 @@ mpc85xx_cds_setup_arch(void) | |||
445 | invalidate_tlbcam_entry(num_tlbcam_entries - 1); | 449 | invalidate_tlbcam_entry(num_tlbcam_entries - 1); |
446 | #endif | 450 | #endif |
447 | 451 | ||
452 | /* setup the board related info for the MDIO bus */ | ||
453 | mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); | ||
454 | |||
455 | mdata->irq[0] = MPC85xx_IRQ_EXT5; | ||
456 | mdata->irq[1] = MPC85xx_IRQ_EXT5; | ||
457 | mdata->irq[2] = -1; | ||
458 | mdata->irq[3] = -1; | ||
459 | mdata->irq[31] = -1; | ||
460 | mdata->paddr += binfo->bi_immr_base; | ||
461 | |||
448 | /* setup the board related information for the enet controllers */ | 462 | /* setup the board related information for the enet controllers */ |
449 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); | 463 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); |
450 | if (pdata) { | 464 | if (pdata) { |
451 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | 465 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
452 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | 466 | pdata->bus_id = GFAR_PHY_0; |
453 | pdata->phyid = 0; | ||
454 | /* fixup phy address */ | ||
455 | pdata->phy_reg_addr += binfo->bi_immr_base; | ||
456 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); | 467 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
457 | } | 468 | } |
458 | 469 | ||
459 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); | 470 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); |
460 | if (pdata) { | 471 | if (pdata) { |
461 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | 472 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
462 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | 473 | pdata->bus_id = GFAR_PHY_1; |
463 | pdata->phyid = 1; | ||
464 | /* fixup phy address */ | ||
465 | pdata->phy_reg_addr += binfo->bi_immr_base; | ||
466 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | 474 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
467 | } | 475 | } |
468 | 476 | ||
469 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); | 477 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); |
470 | if (pdata) { | 478 | if (pdata) { |
471 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | 479 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
472 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | 480 | pdata->bus_id = GFAR_PHY_0; |
473 | pdata->phyid = 0; | ||
474 | /* fixup phy address */ | ||
475 | pdata->phy_reg_addr += binfo->bi_immr_base; | ||
476 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); | 481 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
477 | } | 482 | } |
478 | 483 | ||
479 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); | 484 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); |
480 | if (pdata) { | 485 | if (pdata) { |
481 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | 486 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
482 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | 487 | pdata->bus_id = GFAR_PHY_1; |
483 | pdata->phyid = 1; | ||
484 | /* fixup phy address */ | ||
485 | pdata->phy_reg_addr += binfo->bi_immr_base; | ||
486 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | 488 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
487 | } | 489 | } |
488 | 490 | ||