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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-04-27 02:28:26 -0400
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-04-27 02:31:11 -0400
commite9c549998dc24209847007e1f209f3b6c88d21ba (patch)
tree0f52fcbe1dfa158349afc6ad2edaa6738615dc3b /arch/powerpc
parent8e10cd74342c7f5ce259cceca36f6eba084f5d58 (diff)
Revert wrong fixes for common misspellings
These changes were incorrectly fixed by codespell. They were now manually corrected. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/uninorth.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index ae9c899c8a6..d12b11d7641 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
60 * 60 *
61 * Obviously, the GART is not cache coherent and so any change to it 61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non 62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself does't seem to be cache coherent neither. 63 * cachable). AGP memory itself doesn't seem to be cache coherent neither.
64 * 64 *
65 * In order to invalidate the GART (which is probably necessary to inval 65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written, 66 * the bridge internal TLBs), the following sequence has to be written,