diff options
author | Roy Zang <tie-fei.zang@freescale.com> | 2012-09-03 05:22:09 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2012-09-12 15:57:11 -0400 |
commit | 6cc1b4e931f8d8dccdcdb05b758a7d1178ad6b49 (patch) | |
tree | d91011b95f2d326c1a591129d7dba1d4d5118b06 /arch/powerpc | |
parent | c8c4e2c3d911cb004db1ae8483df3795d8d20459 (diff) |
powerpc/pci: Add IP revision register define for Freescale PCIe controller
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index baa0fd18289..54ed82c5323 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
@@ -16,6 +16,7 @@ | |||
16 | 16 | ||
17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ | 17 | #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ |
18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ | 18 | #define PCIE_LTSSM_L0 0x16 /* L0 state */ |
19 | #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ | ||
19 | #define PIWAR_EN 0x80000000 /* Enable */ | 20 | #define PIWAR_EN 0x80000000 /* Enable */ |
20 | #define PIWAR_PF 0x20000000 /* prefetch */ | 21 | #define PIWAR_PF 0x20000000 /* prefetch */ |
21 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ | 22 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ |
@@ -57,7 +58,9 @@ struct ccsr_pci { | |||
57 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ | 58 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ |
58 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ | 59 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ |
59 | __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ | 60 | __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ |
60 | u8 res3[3024]; | 61 | u8 res3[3016]; |
62 | __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */ | ||
63 | __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */ | ||
61 | 64 | ||
62 | /* PCI/PCI Express outbound window 0-4 | 65 | /* PCI/PCI Express outbound window 0-4 |
63 | * Window 0 is the default window and is the only window enabled upon reset. | 66 | * Window 0 is the default window and is the only window enabled upon reset. |